arch/x86/kernel/cpu/perf_event_intel_ds.c

   1 #include <linux/bitops.h>
   2 #include <linux/types.h>
   3 #include <linux/slab.h>
   4
   5 #include <asm/perf_event.h>
   6 #include <asm/insn.h>
   7
   8 #include "perf_event.h"
   9
  10 /* The size of a BTS record in bytes: */
  11 #define BTS_RECORD_SIZE         24
  12
  13 #define BTS_BUFFER_SIZE         (PAGE_SIZE << 4)
  14 #define PEBS_BUFFER_SIZE        PAGE_SIZE
  15 #define PEBS_FIXUP_SIZE         PAGE_SIZE
  16
  17 /*
  18  * pebs_record_32 for p4 and core not supported
  19
  20 struct pebs_record_32 {
  21         u32 flags, ip;
  22         u32 ax, bc, cx, dx;
  23         u32 si, di, bp, sp;
  24 };
  25
  26  */
  27
  28 union intel_x86_pebs_dse {
  29         u64 val;
  30         struct {
  31                 unsigned int ld_dse:4;
  32                 unsigned int ld_stlb_miss:1;
  33                 unsigned int ld_locked:1;
  34                 unsigned int ld_reserved:26;
  35         };
  36         struct {
  37                 unsigned int st_l1d_hit:1;
  38                 unsigned int st_reserved1:3;
  39                 unsigned int st_stlb_miss:1;
  40                 unsigned int st_locked:1;
  41                 unsigned int st_reserved2:26;
  42         };
  43 };
  44
  45
  46 /*
  47  * Map PEBS Load Latency Data Source encodings to generic
  48  * memory data source information
  49  */
  50 #define P(a, b) PERF_MEM_S(a, b)
  51 #define OP_LH (P(OP, LOAD) | P(LVL, HIT))
  52 #define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS))
  53
  54 static const u64 pebs_data_source[] = {
  55         P(OP, LOAD) | P(LVL, MISS) | P(LVL, L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
  56         OP_LH | P(LVL, L1)  | P(SNOOP, NONE),   /* 0x01: L1 local */
  57         OP_LH | P(LVL, LFB) | P(SNOOP, NONE),   /* 0x02: LFB hit */
  58         OP_LH | P(LVL, L2)  | P(SNOOP, NONE),   /* 0x03: L2 hit */
  59         OP_LH | P(LVL, L3)  | P(SNOOP, NONE),   /* 0x04: L3 hit */
  60         OP_LH | P(LVL, L3)  | P(SNOOP, MISS),   /* 0x05: L3 hit, snoop miss */
  61         OP_LH | P(LVL, L3)  | P(SNOOP, HIT),    /* 0x06: L3 hit, snoop hit */
  62         OP_LH | P(LVL, L3)  | P(SNOOP, HITM),   /* 0x07: L3 hit, snoop hitm */
  63         OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HIT),  /* 0x08: L3 miss snoop hit */
  64         OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
  65         OP_LH | P(LVL, LOC_RAM)  | P(SNOOP, HIT),  /* 0x0a: L3 miss, shared */
  66         OP_LH | P(LVL, REM_RAM1) | P(SNOOP, HIT),  /* 0x0b: L3 miss, shared */
  67         OP_LH | P(LVL, LOC_RAM)  | SNOOP_NONE_MISS,/* 0x0c: L3 miss, excl */
  68         OP_LH | P(LVL, REM_RAM1) | SNOOP_NONE_MISS,/* 0x0d: L3 miss, excl */
  69         OP_LH | P(LVL, IO)  | P(SNOOP, NONE), /* 0x0e: I/O */
  70         OP_LH | P(LVL, UNC) | P(SNOOP, NONE), /* 0x0f: uncached */
  71 };
  72
  73 static u64 precise_store_data(u64 status)
  74 {
  75         union intel_x86_pebs_dse dse;
  76         u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2);
  77
  78         dse.val = status;
  79
  80         /*
  81          * bit 4: TLB access
  82          * 1 = stored missed 2nd level TLB
  83          *
  84          * so it either hit the walker or the OS
  85          * otherwise hit 2nd level TLB
  86          */
  87         if (dse.st_stlb_miss)
  88                 val |= P(TLB, MISS);
  89         else
  90                 val |= P(TLB, HIT);
  91
  92         /*
  93          * bit 0: hit L1 data cache
  94          * if not set, then all we know is that
  95          * it missed L1D
  96          */
  97         if (dse.st_l1d_hit)
  98                 val |= P(LVL, HIT);
  99         else
 100                 val |= P(LVL, MISS);
 101
 102         /*
 103          * bit 5: Locked prefix
 104          */
 105         if (dse.st_locked)
 106                 val |= P(LOCK, LOCKED);
 107
 108         return val;
 109 }
 110
 111 static u64 precise_datala_hsw(struct perf_event *event, u64 status)
 112 {
 113         union perf_mem_data_src dse;
 114
 115         dse.val = PERF_MEM_NA;
 116
 117         if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW)
 118                 dse.mem_op = PERF_MEM_OP_STORE;
 119         else if (event->hw.flags & PERF_X86_EVENT_PEBS_LD_HSW)
 120                 dse.mem_op = PERF_MEM_OP_LOAD;
 121
 122         /*
 123          * L1 info only valid for following events:
 124          *
 125          * MEM_UOPS_RETIRED.STLB_MISS_STORES
 126          * MEM_UOPS_RETIRED.LOCK_STORES
 127          * MEM_UOPS_RETIRED.SPLIT_STORES
 128          * MEM_UOPS_RETIRED.ALL_STORES
 129          */
 130         if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) {
 131                 if (status & 1)
 132                         dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_HIT;
 133                 else
 134                         dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_MISS;
 135         }
 136         return dse.val;
 137 }
 138
 139 static u64 load_latency_data(u64 status)
 140 {
 141         union intel_x86_pebs_dse dse;
 142         u64 val;
 143         int model = boot_cpu_data.x86_model;
 144         int fam = boot_cpu_data.x86;
 145
 146         dse.val = status;
 147
 148         /*
 149          * use the mapping table for bit 0-3
 150          */
 151         val = pebs_data_source[dse.ld_dse];
 152
 153         /*
 154          * Nehalem models do not support TLB, Lock infos
 155          */
 156         if (fam == 0x6 && (model == 26 || model == 30
 157             || model == 31 || model == 46)) {
 158                 val |= P(TLB, NA) | P(LOCK, NA);
 159                 return val;
 160         }
 161         /*
 162          * bit 4: TLB access
 163          * 0 = did not miss 2nd level TLB
 164          * 1 = missed 2nd level TLB
 165          */
 166         if (dse.ld_stlb_miss)
 167                 val |= P(TLB, MISS) | P(TLB, L2);
 168         else
 169                 val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
 170
 171         /*
 172          * bit 5: locked prefix
 173          */
 174         if (dse.ld_locked)
 175                 val |= P(LOCK, LOCKED);
 176
 177         return val;
 178 }
 179
 180 struct pebs_record_core {
 181         u64 flags, ip;
 182         u64 ax, bx, cx, dx;
 183         u64 si, di, bp, sp;
 184         u64 r8,  r9,  r10, r11;
 185         u64 r12, r13, r14, r15;
 186 };
 187
 188 struct pebs_record_nhm {
 189         u64 flags, ip;
 190         u64 ax, bx, cx, dx;
 191         u64 si, di, bp, sp;
 192         u64 r8,  r9,  r10, r11;
 193         u64 r12, r13, r14, r15;
 194         u64 status, dla, dse, lat;
 195 };
 196
 197 /*
 198  * Same as pebs_record_nhm, with two additional fields.
 199  */
 200 struct pebs_record_hsw {
 201         u64 flags, ip;
 202         u64 ax, bx, cx, dx;
 203         u64 si, di, bp, sp;
 204         u64 r8,  r9,  r10, r11;
 205         u64 r12, r13, r14, r15;
 206         u64 status, dla, dse, lat;
 207         u64 real_ip, tsx_tuning;
 208 };
 209
 210 union hsw_tsx_tuning {
 211         struct {
 212                 u32 cycles_last_block     : 32,
 213                     hle_abort             : 1,
 214                     rtm_abort             : 1,
 215                     instruction_abort     : 1,
 216                     non_instruction_abort : 1,
 217                     retry                 : 1,
 218                     data_conflict         : 1,
 219                     capacity_writes       : 1,
 220                     capacity_reads        : 1;
 221         };
 222         u64         value;
 223 };
 224
 225 #define PEBS_HSW_TSX_FLAGS      0xff00000000ULL
 226
 227 void init_debug_store_on_cpu(int cpu)
 228 {
 229         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 230
 231         if (!ds)
 232                 return;
 233
 234         wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
 235                      (u32)((u64)(unsigned long)ds),
 236                      (u32)((u64)(unsigned long)ds >> 32));
 237 }
 238
 239 void fini_debug_store_on_cpu(int cpu)
 240 {
 241         if (!per_cpu(cpu_hw_events, cpu).ds)
 242                 return;
 243
 244         wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
 245 }
 246
 247 static DEFINE_PER_CPU(void *, insn_buffer);
 248
 249 static int alloc_pebs_buffer(int cpu)
 250 {
 251         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 252         int node = cpu_to_node(cpu);
 253         int max, thresh = 1; /* always use a single PEBS record */
 254         void *buffer, *ibuffer;
 255
 256         if (!x86_pmu.pebs)
 257                 return 0;
 258
 259         buffer = kzalloc_node(PEBS_BUFFER_SIZE, GFP_KERNEL, node);
 260         if (unlikely(!buffer))
 261                 return -ENOMEM;
 262
 263         /*
 264          * HSW+ already provides us the eventing ip; no need to allocate this
 265          * buffer then.
 266          */
 267         if (x86_pmu.intel_cap.pebs_format < 2) {
 268                 ibuffer = kzalloc_node(PEBS_FIXUP_SIZE, GFP_KERNEL, node);
 269                 if (!ibuffer) {
 270                         kfree(buffer);
 271                         return -ENOMEM;
 272                 }
 273                 per_cpu(insn_buffer, cpu) = ibuffer;
 274         }
 275
 276         max = PEBS_BUFFER_SIZE / x86_pmu.pebs_record_size;
 277
 278         ds->pebs_buffer_base = (u64)(unsigned long)buffer;
 279         ds->pebs_index = ds->pebs_buffer_base;
 280         ds->pebs_absolute_maximum = ds->pebs_buffer_base +
 281                 max * x86_pmu.pebs_record_size;
 282
 283         ds->pebs_interrupt_threshold = ds->pebs_buffer_base +
 284                 thresh * x86_pmu.pebs_record_size;
 285
 286         return 0;
 287 }
 288
 289 static void release_pebs_buffer(int cpu)
 290 {
 291         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 292
 293         if (!ds || !x86_pmu.pebs)
 294                 return;
 295
 296         kfree(per_cpu(insn_buffer, cpu));
 297         per_cpu(insn_buffer, cpu) = NULL;
 298
 299         kfree((void *)(unsigned long)ds->pebs_buffer_base);
 300         ds->pebs_buffer_base = 0;
 301 }
 302
 303 static int alloc_bts_buffer(int cpu)
 304 {
 305         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 306         int node = cpu_to_node(cpu);
 307         int max, thresh;
 308         void *buffer;
 309
 310         if (!x86_pmu.bts)
 311                 return 0;
 312
 313         buffer = kzalloc_node(BTS_BUFFER_SIZE, GFP_KERNEL | __GFP_NOWARN, node);
 314         if (unlikely(!buffer)) {
 315                 WARN_ONCE(1, "%s: BTS buffer allocation failure\n", __func__);
 316                 return -ENOMEM;
 317         }
 318
 319         max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE;
 320         thresh = max / 16;
 321
 322         ds->bts_buffer_base = (u64)(unsigned long)buffer;
 323         ds->bts_index = ds->bts_buffer_base;
 324         ds->bts_absolute_maximum = ds->bts_buffer_base +
 325                 max * BTS_RECORD_SIZE;
 326         ds->bts_interrupt_threshold = ds->bts_absolute_maximum -
 327                 thresh * BTS_RECORD_SIZE;
 328
 329         return 0;
 330 }
 331
 332 static void release_bts_buffer(int cpu)
 333 {
 334         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 335
 336         if (!ds || !x86_pmu.bts)
 337                 return;
 338
 339         kfree((void *)(unsigned long)ds->bts_buffer_base);
 340         ds->bts_buffer_base = 0;
 341 }
 342
 343 static int alloc_ds_buffer(int cpu)
 344 {
 345         int node = cpu_to_node(cpu);
 346         struct debug_store *ds;
 347
 348         ds = kzalloc_node(sizeof(*ds), GFP_KERNEL, node);
 349         if (unlikely(!ds))
 350                 return -ENOMEM;
 351
 352         per_cpu(cpu_hw_events, cpu).ds = ds;
 353
 354         return 0;
 355 }
 356
 357 static void release_ds_buffer(int cpu)
 358 {
 359         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
 360
 361         if (!ds)
 362                 return;
 363
 364         per_cpu(cpu_hw_events, cpu).ds = NULL;
 365         kfree(ds);
 366 }
 367
 368 void release_ds_buffers(void)
 369 {
 370         int cpu;
 371
 372         if (!x86_pmu.bts && !x86_pmu.pebs)
 373                 return;
 374
 375         get_online_cpus();
 376         for_each_online_cpu(cpu)
 377                 fini_debug_store_on_cpu(cpu);
 378
 379         for_each_possible_cpu(cpu) {
 380                 release_pebs_buffer(cpu);
 381                 release_bts_buffer(cpu);
 382                 release_ds_buffer(cpu);
 383         }
 384         put_online_cpus();
 385 }
 386
 387 void reserve_ds_buffers(void)
 388 {
 389         int bts_err = 0, pebs_err = 0;
 390         int cpu;
 391
 392         x86_pmu.bts_active = 0;
 393         x86_pmu.pebs_active = 0;
 394
 395         if (!x86_pmu.bts && !x86_pmu.pebs)
 396                 return;
 397
 398         if (!x86_pmu.bts)
 399                 bts_err = 1;
 400
 401         if (!x86_pmu.pebs)
 402                 pebs_err = 1;
 403
 404         get_online_cpus();
 405
 406         for_each_possible_cpu(cpu) {
 407                 if (alloc_ds_buffer(cpu)) {
 408                         bts_err = 1;
 409                         pebs_err = 1;
 410                 }
 411
 412                 if (!bts_err && alloc_bts_buffer(cpu))
 413                         bts_err = 1;
 414
 415                 if (!pebs_err && alloc_pebs_buffer(cpu))
 416                         pebs_err = 1;
 417
 418                 if (bts_err && pebs_err)
 419                         break;
 420         }
 421
 422         if (bts_err) {
 423                 for_each_possible_cpu(cpu)
 424                         release_bts_buffer(cpu);
 425         }
 426
 427         if (pebs_err) {
 428                 for_each_possible_cpu(cpu)
 429                         release_pebs_buffer(cpu);
 430         }
 431
 432         if (bts_err && pebs_err) {
 433                 for_each_possible_cpu(cpu)
 434                         release_ds_buffer(cpu);
 435         } else {
 436                 if (x86_pmu.bts && !bts_err)
 437                         x86_pmu.bts_active = 1;
 438
 439                 if (x86_pmu.pebs && !pebs_err)
 440                         x86_pmu.pebs_active = 1;
 441
 442                 for_each_online_cpu(cpu)
 443                         init_debug_store_on_cpu(cpu);
 444         }
 445
 446         put_online_cpus();
 447 }
 448
 449 /*
 450  * BTS
 451  */
 452
 453 struct event_constraint bts_constraint =
 454         EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS, 0);
 455
 456 void intel_pmu_enable_bts(u64 config)
 457 {
 458         unsigned long debugctlmsr;
 459
 460         debugctlmsr = get_debugctlmsr();
 461
 462         debugctlmsr |= DEBUGCTLMSR_TR;
 463         debugctlmsr |= DEBUGCTLMSR_BTS;
 464         debugctlmsr |= DEBUGCTLMSR_BTINT;
 465
 466         if (!(config & ARCH_PERFMON_EVENTSEL_OS))
 467                 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_OS;
 468
 469         if (!(config & ARCH_PERFMON_EVENTSEL_USR))
 470                 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_USR;
 471
 472         update_debugctlmsr(debugctlmsr);
 473 }
 474
 475 void intel_pmu_disable_bts(void)
 476 {
 477         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 478         unsigned long debugctlmsr;
 479
 480         if (!cpuc->ds)
 481                 return;
 482
 483         debugctlmsr = get_debugctlmsr();
 484
 485         debugctlmsr &=
 486                 ~(DEBUGCTLMSR_TR | DEBUGCTLMSR_BTS | DEBUGCTLMSR_BTINT |
 487                   DEBUGCTLMSR_BTS_OFF_OS | DEBUGCTLMSR_BTS_OFF_USR);
 488
 489         update_debugctlmsr(debugctlmsr);
 490 }
 491
 492 int intel_pmu_drain_bts_buffer(void)
 493 {
 494         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 495         struct debug_store *ds = cpuc->ds;
 496         struct bts_record {
 497                 u64     from;
 498                 u64     to;
 499                 u64     flags;
 500         };
 501         struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
 502         struct bts_record *at, *top;
 503         struct perf_output_handle handle;
 504         struct perf_event_header header;
 505         struct perf_sample_data data;
 506         struct pt_regs regs;
 507
 508         if (!event)
 509                 return 0;
 510
 511         if (!x86_pmu.bts_active)
 512                 return 0;
 513
 514         at  = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
 515         top = (struct bts_record *)(unsigned long)ds->bts_index;
 516
 517         if (top <= at)
 518                 return 0;
 519
 520         memset(&regs, 0, sizeof(regs));
 521
 522         ds->bts_index = ds->bts_buffer_base;
 523
 524         perf_sample_data_init(&data, 0, event->hw.last_period);
 525
 526         /*
 527          * Prepare a generic sample, i.e. fill in the invariant fields.
 528          * We will overwrite the from and to address before we output
 529          * the sample.
 530          */
 531         perf_prepare_sample(&header, &data, event, &regs);
 532
 533         if (perf_output_begin(&handle, event, header.size * (top - at)))
 534                 return 1;
 535
 536         for (; at < top; at++) {
 537                 data.ip         = at->from;
 538                 data.addr       = at->to;
 539
 540                 perf_output_sample(&handle, &header, &data, event);
 541         }
 542
 543         perf_output_end(&handle);
 544
 545         /* There's new data available. */
 546         event->hw.interrupts++;
 547         event->pending_kill = POLL_IN;
 548         return 1;
 549 }
 550
 551 /*
 552  * PEBS
 553  */
 554 struct event_constraint intel_core2_pebs_event_constraints[] = {
 555         INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
 556         INTEL_FLAGS_UEVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */
 557         INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
 558         INTEL_FLAGS_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
 559         INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1),    /* MEM_LOAD_RETIRED.* */
 560         EVENT_CONSTRAINT_END
 561 };
 562
 563 struct event_constraint intel_atom_pebs_event_constraints[] = {
 564         INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
 565         INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */
 566         INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1),    /* MEM_LOAD_RETIRED.* */
 567         EVENT_CONSTRAINT_END
 568 };
 569
 570 struct event_constraint intel_slm_pebs_event_constraints[] = {
 571         /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
 572         INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
 573         /* Allow all events as PEBS with no flags */
 574         INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
 575         EVENT_CONSTRAINT_END
 576 };
 577
 578 struct event_constraint intel_nehalem_pebs_event_constraints[] = {
 579         INTEL_PLD_CONSTRAINT(0x100b, 0xf),      /* MEM_INST_RETIRED.* */
 580         INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf),    /* MEM_UNCORE_RETIRED.* */
 581         INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
 582         INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf),    /* INST_RETIRED.ANY */
 583         INTEL_EVENT_CONSTRAINT(0xc2, 0xf),    /* UOPS_RETIRED.* */
 584         INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
 585         INTEL_FLAGS_UEVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */
 586         INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf),    /* SSEX_UOPS_RETIRED.* */
 587         INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
 588         INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf),    /* MEM_LOAD_RETIRED.* */
 589         INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf),    /* FP_ASSIST.* */
 590         EVENT_CONSTRAINT_END
 591 };
 592
 593 struct event_constraint intel_westmere_pebs_event_constraints[] = {
 594         INTEL_PLD_CONSTRAINT(0x100b, 0xf),      /* MEM_INST_RETIRED.* */
 595         INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf),    /* MEM_UNCORE_RETIRED.* */
 596         INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
 597         INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf),    /* INSTR_RETIRED.* */
 598         INTEL_EVENT_CONSTRAINT(0xc2, 0xf),    /* UOPS_RETIRED.* */
 599         INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
 600         INTEL_FLAGS_EVENT_CONSTRAINT(0xc5, 0xf),    /* BR_MISP_RETIRED.* */
 601         INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf),    /* SSEX_UOPS_RETIRED.* */
 602         INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
 603         INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf),    /* MEM_LOAD_RETIRED.* */
 604         INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf),    /* FP_ASSIST.* */
 605         EVENT_CONSTRAINT_END
 606 };
 607
 608 struct event_constraint intel_snb_pebs_event_constraints[] = {
 609         INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
 610         INTEL_PLD_CONSTRAINT(0x01cd, 0x8),    /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
 611         INTEL_PST_CONSTRAINT(0x02cd, 0x8),    /* MEM_TRANS_RETIRED.PRECISE_STORES */
 612         /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
 613         INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
 614         /* Allow all events as PEBS with no flags */
 615         INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
 616         EVENT_CONSTRAINT_END
 617 };
 618
 619 struct event_constraint intel_ivb_pebs_event_constraints[] = {
 620         INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
 621         INTEL_PLD_CONSTRAINT(0x01cd, 0x8),    /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
 622         INTEL_PST_CONSTRAINT(0x02cd, 0x8),    /* MEM_TRANS_RETIRED.PRECISE_STORES */
 623         /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
 624         INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
 625         /* Allow all events as PEBS with no flags */
 626         INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
 627         EVENT_CONSTRAINT_END
 628 };
 629
 630 struct event_constraint intel_hsw_pebs_event_constraints[] = {
 631         INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
 632         INTEL_PLD_CONSTRAINT(0x01cd, 0xf),    /* MEM_TRANS_RETIRED.* */
 633         /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
 634         INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
 635         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
 636         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
 637         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
 638         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
 639         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
 640         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
 641         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
 642         INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
 643         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */
 644         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf),    /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */
 645         INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf),    /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */
 646         /* Allow all events as PEBS with no flags */
 647         INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
 648         EVENT_CONSTRAINT_END
 649 };
 650
 651 struct event_constraint *intel_pebs_constraints(struct perf_event *event)
 652 {
 653         struct event_constraint *c;
 654
 655         if (!event->attr.precise_ip)
 656                 return NULL;
 657
 658         if (x86_pmu.pebs_constraints) {
 659                 for_each_event_constraint(c, x86_pmu.pebs_constraints) {
 660                         if ((event->hw.config & c->cmask) == c->code) {
 661                                 event->hw.flags |= c->flags;
 662                                 return c;
 663                         }
 664                 }
 665         }
 666
 667         return &emptyconstraint;
 668 }
 669
 670 void intel_pmu_pebs_enable(struct perf_event *event)
 671 {
 672         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 673         struct hw_perf_event *hwc = &event->hw;
 674
 675         hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
 676
 677         cpuc->pebs_enabled |= 1ULL << hwc->idx;
 678
 679         if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT)
 680                 cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32);
 681         else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
 682                 cpuc->pebs_enabled |= 1ULL << 63;
 683 }
 684
 685 void intel_pmu_pebs_disable(struct perf_event *event)
 686 {
 687         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 688         struct hw_perf_event *hwc = &event->hw;
 689
 690         cpuc->pebs_enabled &= ~(1ULL << hwc->idx);
 691
 692         if (event->hw.constraint->flags & PERF_X86_EVENT_PEBS_LDLAT)
 693                 cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32));
 694         else if (event->hw.constraint->flags & PERF_X86_EVENT_PEBS_ST)
 695                 cpuc->pebs_enabled &= ~(1ULL << 63);
 696
 697         if (cpuc->enabled)
 698                 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
 699
 700         hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
 701 }
 702
 703 void intel_pmu_pebs_enable_all(void)
 704 {
 705         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 706
 707         if (cpuc->pebs_enabled)
 708                 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
 709 }
 710
 711 void intel_pmu_pebs_disable_all(void)
 712 {
 713         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 714
 715         if (cpuc->pebs_enabled)
 716                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
 717 }
 718
 719 static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
 720 {
 721         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 722         unsigned long from = cpuc->lbr_entries[0].from;
 723         unsigned long old_to, to = cpuc->lbr_entries[0].to;
 724         unsigned long ip = regs->ip;
 725         int is_64bit = 0;
 726         void *kaddr;
 727         int size;
 728
 729         /*
 730          * We don't need to fixup if the PEBS assist is fault like
 731          */
 732         if (!x86_pmu.intel_cap.pebs_trap)
 733                 return 1;
 734
 735         /*
 736          * No LBR entry, no basic block, no rewinding
 737          */
 738         if (!cpuc->lbr_stack.nr || !from || !to)
 739                 return 0;
 740
 741         /*
 742          * Basic blocks should never cross user/kernel boundaries
 743          */
 744         if (kernel_ip(ip) != kernel_ip(to))
 745                 return 0;
 746
 747         /*
 748          * unsigned math, either ip is before the start (impossible) or
 749          * the basic block is larger than 1 page (sanity)
 750          */
 751         if ((ip - to) > PEBS_FIXUP_SIZE)
 752                 return 0;
 753
 754         /*
 755          * We sampled a branch insn, rewind using the LBR stack
 756          */
 757         if (ip == to) {
 758                 set_linear_ip(regs, from);
 759                 return 1;
 760         }
 761
 762         size = ip - to;
 763         if (!kernel_ip(ip)) {
 764                 int bytes;
 765                 u8 *buf = this_cpu_read(insn_buffer);
 766
 767                 /* 'size' must fit our buffer, see above */
 768                 bytes = copy_from_user_nmi(buf, (void __user *)to, size);
 769                 if (bytes != 0)
 770                         return 0;
 771
 772                 kaddr = buf;
 773         } else {
 774                 kaddr = (void *)to;
 775         }
 776
 777         do {
 778                 struct insn insn;
 779
 780                 old_to = to;
 781
 782 #ifdef CONFIG_X86_64
 783                 is_64bit = kernel_ip(to) || !test_thread_flag(TIF_IA32);
 784 #endif
 785                 insn_init(&insn, kaddr, size, is_64bit);
 786                 insn_get_length(&insn);
 787                 /*
 788                  * Make sure there was not a problem decoding the
 789                  * instruction and getting the length.  This is
 790                  * doubly important because we have an infinite
 791                  * loop if insn.length=0.
 792                  */
 793                 if (!insn.length)
 794                         break;
 795
 796                 to += insn.length;
 797                 kaddr += insn.length;
 798                 size -= insn.length;
 799         } while (to < ip);
 800
 801         if (to == ip) {
 802                 set_linear_ip(regs, old_to);
 803                 return 1;
 804         }
 805
 806         /*
 807          * Even though we decoded the basic block, the instruction stream
 808          * never matched the given IP, either the TO or the IP got corrupted.
 809          */
 810         return 0;
 811 }
 812
 813 static inline u64 intel_hsw_weight(struct pebs_record_hsw *pebs)
 814 {
 815         if (pebs->tsx_tuning) {
 816                 union hsw_tsx_tuning tsx = { .value = pebs->tsx_tuning };
 817                 return tsx.cycles_last_block;
 818         }
 819         return 0;
 820 }
 821
 822 static inline u64 intel_hsw_transaction(struct pebs_record_hsw *pebs)
 823 {
 824         u64 txn = (pebs->tsx_tuning & PEBS_HSW_TSX_FLAGS) >> 32;
 825
 826         /* For RTM XABORTs also log the abort code from AX */
 827         if ((txn & PERF_TXN_TRANSACTION) && (pebs->ax & 1))
 828                 txn |= ((pebs->ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT;
 829         return txn;
 830 }
 831
 832 static void __intel_pmu_pebs_event(struct perf_event *event,
 833                                    struct pt_regs *iregs, void *__pebs)
 834 {
 835 #define PERF_X86_EVENT_PEBS_HSW_PREC \
 836                 (PERF_X86_EVENT_PEBS_ST_HSW | \
 837                  PERF_X86_EVENT_PEBS_LD_HSW | \
 838                  PERF_X86_EVENT_PEBS_NA_HSW)
 839         /*
 840          * We cast to the biggest pebs_record but are careful not to
 841          * unconditionally access the 'extra' entries.
 842          */
 843         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 844         struct pebs_record_hsw *pebs = __pebs;
 845         struct perf_sample_data data;
 846         struct pt_regs regs;
 847         u64 sample_type;
 848         int fll, fst, dsrc;
 849         int fl = event->hw.flags;
 850
 851         if (!intel_pmu_save_and_restart(event))
 852                 return;
 853
 854         sample_type = event->attr.sample_type;
 855         dsrc = sample_type & PERF_SAMPLE_DATA_SRC;
 856
 857         fll = fl & PERF_X86_EVENT_PEBS_LDLAT;
 858         fst = fl & (PERF_X86_EVENT_PEBS_ST | PERF_X86_EVENT_PEBS_HSW_PREC);
 859
 860         perf_sample_data_init(&data, 0, event->hw.last_period);
 861
 862         data.period = event->hw.last_period;
 863
 864         /*
 865          * Use latency for weight (only avail with PEBS-LL)
 866          */
 867         if (fll && (sample_type & PERF_SAMPLE_WEIGHT))
 868                 data.weight = pebs->lat;
 869
 870         /*
 871          * data.data_src encodes the data source
 872          */
 873         if (dsrc) {
 874                 u64 val = PERF_MEM_NA;
 875                 if (fll)
 876                         val = load_latency_data(pebs->dse);
 877                 else if (fst && (fl & PERF_X86_EVENT_PEBS_HSW_PREC))
 878                         val = precise_datala_hsw(event, pebs->dse);
 879                 else if (fst)
 880                         val = precise_store_data(pebs->dse);
 881                 data.data_src.val = val;
 882         }
 883
 884         /*
 885          * We use the interrupt regs as a base because the PEBS record
 886          * does not contain a full regs set, specifically it seems to
 887          * lack segment descriptors, which get used by things like
 888          * user_mode().
 889          *
 890          * In the simple case fix up only the IP and BP,SP regs, for
 891          * PERF_SAMPLE_IP and PERF_SAMPLE_CALLCHAIN to function properly.
 892          * A possible PERF_SAMPLE_REGS will have to transfer all regs.
 893          */
 894         regs = *iregs;
 895         regs.flags = pebs->flags;
 896         set_linear_ip(&regs, pebs->ip);
 897         regs.bp = pebs->bp;
 898         regs.sp = pebs->sp;
 899
 900         if (sample_type & PERF_SAMPLE_REGS_INTR) {
 901                 regs.ax = pebs->ax;
 902                 regs.bx = pebs->bx;
 903                 regs.cx = pebs->cx;
 904                 regs.dx = pebs->dx;
 905                 regs.si = pebs->si;
 906                 regs.di = pebs->di;
 907                 regs.bp = pebs->bp;
 908                 regs.sp = pebs->sp;
 909
 910                 regs.flags = pebs->flags;
 911 #ifndef CONFIG_X86_32
 912                 regs.r8 = pebs->r8;
 913                 regs.r9 = pebs->r9;
 914                 regs.r10 = pebs->r10;
 915                 regs.r11 = pebs->r11;
 916                 regs.r12 = pebs->r12;
 917                 regs.r13 = pebs->r13;
 918                 regs.r14 = pebs->r14;
 919                 regs.r15 = pebs->r15;
 920 #endif
 921         }
 922
 923         if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format >= 2) {
 924                 regs.ip = pebs->real_ip;
 925                 regs.flags |= PERF_EFLAGS_EXACT;
 926         } else if (event->attr.precise_ip > 1 && intel_pmu_pebs_fixup_ip(&regs))
 927                 regs.flags |= PERF_EFLAGS_EXACT;
 928         else
 929                 regs.flags &= ~PERF_EFLAGS_EXACT;
 930
 931         if ((sample_type & PERF_SAMPLE_ADDR) &&
 932             x86_pmu.intel_cap.pebs_format >= 1)
 933                 data.addr = pebs->dla;
 934
 935         if (x86_pmu.intel_cap.pebs_format >= 2) {
 936                 /* Only set the TSX weight when no memory weight. */
 937                 if ((sample_type & PERF_SAMPLE_WEIGHT) && !fll)
 938                         data.weight = intel_hsw_weight(pebs);
 939
 940                 if (sample_type & PERF_SAMPLE_TRANSACTION)
 941                         data.txn = intel_hsw_transaction(pebs);
 942         }
 943
 944         if (has_branch_stack(event))
 945                 data.br_stack = &cpuc->lbr_stack;
 946
 947         if (perf_event_overflow(event, &data, &regs))
 948                 x86_pmu_stop(event, 0);
 949 }
 950
 951 static void intel_pmu_drain_pebs_core(struct pt_regs *iregs)
 952 {
 953         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 954         struct debug_store *ds = cpuc->ds;
 955         struct perf_event *event = cpuc->events[0]; /* PMC0 only */
 956         struct pebs_record_core *at, *top;
 957         int n;
 958
 959         if (!x86_pmu.pebs_active)
 960                 return;
 961
 962         at  = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base;
 963         top = (struct pebs_record_core *)(unsigned long)ds->pebs_index;
 964
 965         /*
 966          * Whatever else happens, drain the thing
 967          */
 968         ds->pebs_index = ds->pebs_buffer_base;
 969
 970         if (!test_bit(0, cpuc->active_mask))
 971                 return;
 972
 973         WARN_ON_ONCE(!event);
 974
 975         if (!event->attr.precise_ip)
 976                 return;
 977
 978         n = top - at;
 979         if (n <= 0)
 980                 return;
 981
 982         /*
 983          * Should not happen, we program the threshold at 1 and do not
 984          * set a reset value.
 985          */
 986         WARN_ONCE(n > 1, "bad leftover pebs %d\n", n);
 987         at += n - 1;
 988
 989         __intel_pmu_pebs_event(event, iregs, at);
 990 }
 991
 992 static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
 993 {
 994         struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 995         struct debug_store *ds = cpuc->ds;
 996         struct perf_event *event = NULL;
 997         void *at, *top;
 998         u64 status = 0;
 999         int bit;
1000
1001         if (!x86_pmu.pebs_active)
1002                 return;
1003
1004         at  = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
1005         top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
1006
1007         ds->pebs_index = ds->pebs_buffer_base;
1008
1009         if (unlikely(at > top))
1010                 return;
1011
1012         /*
1013          * Should not happen, we program the threshold at 1 and do not
1014          * set a reset value.
1015          */
1016         WARN_ONCE(top - at > x86_pmu.max_pebs_events * x86_pmu.pebs_record_size,
1017                   "Unexpected number of pebs records %ld\n",
1018                   (long)(top - at) / x86_pmu.pebs_record_size);
1019
1020         for (; at < top; at += x86_pmu.pebs_record_size) {
1021                 struct pebs_record_nhm *p = at;
1022
1023                 for_each_set_bit(bit, (unsigned long *)&p->status,
1024                                  x86_pmu.max_pebs_events) {
1025                         event = cpuc->events[bit];
1026                         if (!test_bit(bit, cpuc->active_mask))
1027                                 continue;
1028
1029                         WARN_ON_ONCE(!event);
1030
1031                         if (!event->attr.precise_ip)
1032                                 continue;
1033
1034                         if (__test_and_set_bit(bit, (unsigned long *)&status))
1035                                 continue;
1036
1037                         break;
1038                 }
1039
1040                 if (!event || bit >= x86_pmu.max_pebs_events)
1041                         continue;
1042
1043                 __intel_pmu_pebs_event(event, iregs, at);
1044         }
1045 }
1046
1047 /*
1048  * BTS, PEBS probe and setup
1049  */
1050
1051 void __init intel_ds_init(void)
1052 {
1053         /*
1054          * No support for 32bit formats
1055          */
1056         if (!boot_cpu_has(X86_FEATURE_DTES64))
1057                 return;
1058
1059         x86_pmu.bts  = boot_cpu_has(X86_FEATURE_BTS);
1060         x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
1061         if (x86_pmu.pebs) {
1062                 char pebs_type = x86_pmu.intel_cap.pebs_trap ?  '+' : '-';
1063                 int format = x86_pmu.intel_cap.pebs_format;
1064
1065                 switch (format) {
1066                 case 0:
1067                         printk(KERN_CONT "PEBS fmt0%c, ", pebs_type);
1068                         x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);
1069                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
1070                         break;
1071
1072                 case 1:
1073                         printk(KERN_CONT "PEBS fmt1%c, ", pebs_type);
1074                         x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
1075                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1076                         break;
1077
1078                 case 2:
1079                         pr_cont("PEBS fmt2%c, ", pebs_type);
1080                         x86_pmu.pebs_record_size = sizeof(struct pebs_record_hsw);
1081                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1082                         break;
1083
1084                 default:
1085                         printk(KERN_CONT "no PEBS fmt%d%c, ", format, pebs_type);
1086                         x86_pmu.pebs = 0;
1087                 }
1088         }
1089 }
1090
1091 void perf_restore_debug_store(void)
1092 {
1093         struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
1094
1095         if (!x86_pmu.bts && !x86_pmu.pebs)
1096                 return;
1097
1098         wrmsrl(MSR_IA32_DS_AREA, (unsigned long)ds);
1099 }