arch/x86/kernel/cpu/perf_event_intel_uncore.c

   1 #include "perf_event_intel_uncore.h"
   2
   3 static struct intel_uncore_type *empty_uncore[] = { NULL, };
   4 struct intel_uncore_type **uncore_msr_uncores = empty_uncore;
   5 struct intel_uncore_type **uncore_pci_uncores = empty_uncore;
   6
   7 static bool pcidrv_registered;
   8 struct pci_driver *uncore_pci_driver;
   9 /* pci bus to socket mapping */
  10 int uncore_pcibus_to_physid[256] = { [0 ... 255] = -1, };
  11 struct pci_dev *uncore_extra_pci_dev[UNCORE_SOCKET_MAX][UNCORE_EXTRA_PCI_DEV_MAX];
  12
  13 static DEFINE_RAW_SPINLOCK(uncore_box_lock);
  14 /* mask of cpus that collect uncore events */
  15 static cpumask_t uncore_cpu_mask;
  16
  17 /* constraint for the fixed counter */
  18 static struct event_constraint uncore_constraint_fixed =
  19         EVENT_CONSTRAINT(~0ULL, 1 << UNCORE_PMC_IDX_FIXED, ~0ULL);
  20 struct event_constraint uncore_constraint_empty =
  21         EVENT_CONSTRAINT(0, 0, 0);
  22
  23 ssize_t uncore_event_show(struct kobject *kobj,
  24                           struct kobj_attribute *attr, char *buf)
  25 {
  26         struct uncore_event_desc *event =
  27                 container_of(attr, struct uncore_event_desc, attr);
  28         return sprintf(buf, "%s", event->config);
  29 }
  30
  31 struct intel_uncore_pmu *uncore_event_to_pmu(struct perf_event *event)
  32 {
  33         return container_of(event->pmu, struct intel_uncore_pmu, pmu);
  34 }
  35
  36 struct intel_uncore_box *uncore_pmu_to_box(struct intel_uncore_pmu *pmu, int cpu)
  37 {
  38         struct intel_uncore_box *box;
  39
  40         box = *per_cpu_ptr(pmu->box, cpu);
  41         if (box)
  42                 return box;
  43
  44         raw_spin_lock(&uncore_box_lock);
  45         /* Recheck in lock to handle races. */
  46         if (*per_cpu_ptr(pmu->box, cpu))
  47                 goto out;
  48         list_for_each_entry(box, &pmu->box_list, list) {
  49                 if (box->phys_id == topology_physical_package_id(cpu)) {
  50                         atomic_inc(&box->refcnt);
  51                         *per_cpu_ptr(pmu->box, cpu) = box;
  52                         break;
  53                 }
  54         }
  55 out:
  56         raw_spin_unlock(&uncore_box_lock);
  57
  58         return *per_cpu_ptr(pmu->box, cpu);
  59 }
  60
  61 struct intel_uncore_box *uncore_event_to_box(struct perf_event *event)
  62 {
  63         /*
  64          * perf core schedules event on the basis of cpu, uncore events are
  65          * collected by one of the cpus inside a physical package.
  66          */
  67         return uncore_pmu_to_box(uncore_event_to_pmu(event), smp_processor_id());
  68 }
  69
  70 u64 uncore_msr_read_counter(struct intel_uncore_box *box, struct perf_event *event)
  71 {
  72         u64 count;
  73
  74         rdmsrl(event->hw.event_base, count);
  75
  76         return count;
  77 }
  78
  79 /*
  80  * generic get constraint function for shared match/mask registers.
  81  */
  82 struct event_constraint *
  83 uncore_get_constraint(struct intel_uncore_box *box, struct perf_event *event)
  84 {
  85         struct intel_uncore_extra_reg *er;
  86         struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
  87         struct hw_perf_event_extra *reg2 = &event->hw.branch_reg;
  88         unsigned long flags;
  89         bool ok = false;
  90
  91         /*
  92          * reg->alloc can be set due to existing state, so for fake box we
  93          * need to ignore this, otherwise we might fail to allocate proper
  94          * fake state for this extra reg constraint.
  95          */
  96         if (reg1->idx == EXTRA_REG_NONE ||
  97             (!uncore_box_is_fake(box) && reg1->alloc))
  98                 return NULL;
  99
 100         er = &box->shared_regs[reg1->idx];
 101         raw_spin_lock_irqsave(&er->lock, flags);
 102         if (!atomic_read(&er->ref) ||
 103             (er->config1 == reg1->config && er->config2 == reg2->config)) {
 104                 atomic_inc(&er->ref);
 105                 er->config1 = reg1->config;
 106                 er->config2 = reg2->config;
 107                 ok = true;
 108         }
 109         raw_spin_unlock_irqrestore(&er->lock, flags);
 110
 111         if (ok) {
 112                 if (!uncore_box_is_fake(box))
 113                         reg1->alloc = 1;
 114                 return NULL;
 115         }
 116
 117         return &uncore_constraint_empty;
 118 }
 119
 120 void uncore_put_constraint(struct intel_uncore_box *box, struct perf_event *event)
 121 {
 122         struct intel_uncore_extra_reg *er;
 123         struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
 124
 125         /*
 126          * Only put constraint if extra reg was actually allocated. Also
 127          * takes care of event which do not use an extra shared reg.
 128          *
 129          * Also, if this is a fake box we shouldn't touch any event state
 130          * (reg->alloc) and we don't care about leaving inconsistent box
 131          * state either since it will be thrown out.
 132          */
 133         if (uncore_box_is_fake(box) || !reg1->alloc)
 134                 return;
 135
 136         er = &box->shared_regs[reg1->idx];
 137         atomic_dec(&er->ref);
 138         reg1->alloc = 0;
 139 }
 140
 141 u64 uncore_shared_reg_config(struct intel_uncore_box *box, int idx)
 142 {
 143         struct intel_uncore_extra_reg *er;
 144         unsigned long flags;
 145         u64 config;
 146
 147         er = &box->shared_regs[idx];
 148
 149         raw_spin_lock_irqsave(&er->lock, flags);
 150         config = er->config;
 151         raw_spin_unlock_irqrestore(&er->lock, flags);
 152
 153         return config;
 154 }
 155
 156 static void uncore_assign_hw_event(struct intel_uncore_box *box, struct perf_event *event, int idx)
 157 {
 158         struct hw_perf_event *hwc = &event->hw;
 159
 160         hwc->idx = idx;
 161         hwc->last_tag = ++box->tags[idx];
 162
 163         if (hwc->idx == UNCORE_PMC_IDX_FIXED) {
 164                 hwc->event_base = uncore_fixed_ctr(box);
 165                 hwc->config_base = uncore_fixed_ctl(box);
 166                 return;
 167         }
 168
 169         hwc->config_base = uncore_event_ctl(box, hwc->idx);
 170         hwc->event_base  = uncore_perf_ctr(box, hwc->idx);
 171 }
 172
 173 void uncore_perf_event_update(struct intel_uncore_box *box, struct perf_event *event)
 174 {
 175         u64 prev_count, new_count, delta;
 176         int shift;
 177
 178         if (event->hw.idx >= UNCORE_PMC_IDX_FIXED)
 179                 shift = 64 - uncore_fixed_ctr_bits(box);
 180         else
 181                 shift = 64 - uncore_perf_ctr_bits(box);
 182
 183         /* the hrtimer might modify the previous event value */
 184 again:
 185         prev_count = local64_read(&event->hw.prev_count);
 186         new_count = uncore_read_counter(box, event);
 187         if (local64_xchg(&event->hw.prev_count, new_count) != prev_count)
 188                 goto again;
 189
 190         delta = (new_count << shift) - (prev_count << shift);
 191         delta >>= shift;
 192
 193         local64_add(delta, &event->count);
 194 }
 195
 196 /*
 197  * The overflow interrupt is unavailable for SandyBridge-EP, is broken
 198  * for SandyBridge. So we use hrtimer to periodically poll the counter
 199  * to avoid overflow.
 200  */
 201 static enum hrtimer_restart uncore_pmu_hrtimer(struct hrtimer *hrtimer)
 202 {
 203         struct intel_uncore_box *box;
 204         struct perf_event *event;
 205         unsigned long flags;
 206         int bit;
 207
 208         box = container_of(hrtimer, struct intel_uncore_box, hrtimer);
 209         if (!box->n_active || box->cpu != smp_processor_id())
 210                 return HRTIMER_NORESTART;
 211         /*
 212          * disable local interrupt to prevent uncore_pmu_event_start/stop
 213          * to interrupt the update process
 214          */
 215         local_irq_save(flags);
 216
 217         /*
 218          * handle boxes with an active event list as opposed to active
 219          * counters
 220          */
 221         list_for_each_entry(event, &box->active_list, active_entry) {
 222                 uncore_perf_event_update(box, event);
 223         }
 224
 225         for_each_set_bit(bit, box->active_mask, UNCORE_PMC_IDX_MAX)
 226                 uncore_perf_event_update(box, box->events[bit]);
 227
 228         local_irq_restore(flags);
 229
 230         hrtimer_forward_now(hrtimer, ns_to_ktime(box->hrtimer_duration));
 231         return HRTIMER_RESTART;
 232 }
 233
 234 void uncore_pmu_start_hrtimer(struct intel_uncore_box *box)
 235 {
 236         __hrtimer_start_range_ns(&box->hrtimer,
 237                         ns_to_ktime(box->hrtimer_duration), 0,
 238                         HRTIMER_MODE_REL_PINNED, 0);
 239 }
 240
 241 void uncore_pmu_cancel_hrtimer(struct intel_uncore_box *box)
 242 {
 243         hrtimer_cancel(&box->hrtimer);
 244 }
 245
 246 static void uncore_pmu_init_hrtimer(struct intel_uncore_box *box)
 247 {
 248         hrtimer_init(&box->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
 249         box->hrtimer.function = uncore_pmu_hrtimer;
 250 }
 251
 252 static struct intel_uncore_box *uncore_alloc_box(struct intel_uncore_type *type, int node)
 253 {
 254         struct intel_uncore_box *box;
 255         int i, size;
 256
 257         size = sizeof(*box) + type->num_shared_regs * sizeof(struct intel_uncore_extra_reg);
 258
 259         box = kzalloc_node(size, GFP_KERNEL, node);
 260         if (!box)
 261                 return NULL;
 262
 263         for (i = 0; i < type->num_shared_regs; i++)
 264                 raw_spin_lock_init(&box->shared_regs[i].lock);
 265
 266         uncore_pmu_init_hrtimer(box);
 267         atomic_set(&box->refcnt, 1);
 268         box->cpu = -1;
 269         box->phys_id = -1;
 270
 271         /* set default hrtimer timeout */
 272         box->hrtimer_duration = UNCORE_PMU_HRTIMER_INTERVAL;
 273
 274         INIT_LIST_HEAD(&box->active_list);
 275
 276         return box;
 277 }
 278
 279 static int
 280 uncore_collect_events(struct intel_uncore_box *box, struct perf_event *leader, bool dogrp)
 281 {
 282         struct perf_event *event;
 283         int n, max_count;
 284
 285         max_count = box->pmu->type->num_counters;
 286         if (box->pmu->type->fixed_ctl)
 287                 max_count++;
 288
 289         if (box->n_events >= max_count)
 290                 return -EINVAL;
 291
 292         n = box->n_events;
 293         box->event_list[n] = leader;
 294         n++;
 295         if (!dogrp)
 296                 return n;
 297
 298         list_for_each_entry(event, &leader->sibling_list, group_entry) {
 299                 if (event->state <= PERF_EVENT_STATE_OFF)
 300                         continue;
 301
 302                 if (n >= max_count)
 303                         return -EINVAL;
 304
 305                 box->event_list[n] = event;
 306                 n++;
 307         }
 308         return n;
 309 }
 310
 311 static struct event_constraint *
 312 uncore_get_event_constraint(struct intel_uncore_box *box, struct perf_event *event)
 313 {
 314         struct intel_uncore_type *type = box->pmu->type;
 315         struct event_constraint *c;
 316
 317         if (type->ops->get_constraint) {
 318                 c = type->ops->get_constraint(box, event);
 319                 if (c)
 320                         return c;
 321         }
 322
 323         if (event->attr.config == UNCORE_FIXED_EVENT)
 324                 return &uncore_constraint_fixed;
 325
 326         if (type->constraints) {
 327                 for_each_event_constraint(c, type->constraints) {
 328                         if ((event->hw.config & c->cmask) == c->code)
 329                                 return c;
 330                 }
 331         }
 332
 333         return &type->unconstrainted;
 334 }
 335
 336 static void uncore_put_event_constraint(struct intel_uncore_box *box, struct perf_event *event)
 337 {
 338         if (box->pmu->type->ops->put_constraint)
 339                 box->pmu->type->ops->put_constraint(box, event);
 340 }
 341
 342 static int uncore_assign_events(struct intel_uncore_box *box, int assign[], int n)
 343 {
 344         unsigned long used_mask[BITS_TO_LONGS(UNCORE_PMC_IDX_MAX)];
 345         struct event_constraint *c;
 346         int i, wmin, wmax, ret = 0;
 347         struct hw_perf_event *hwc;
 348
 349         bitmap_zero(used_mask, UNCORE_PMC_IDX_MAX);
 350
 351         for (i = 0, wmin = UNCORE_PMC_IDX_MAX, wmax = 0; i < n; i++) {
 352                 hwc = &box->event_list[i]->hw;
 353                 c = uncore_get_event_constraint(box, box->event_list[i]);
 354                 hwc->constraint = c;
 355                 wmin = min(wmin, c->weight);
 356                 wmax = max(wmax, c->weight);
 357         }
 358
 359         /* fastpath, try to reuse previous register */
 360         for (i = 0; i < n; i++) {
 361                 hwc = &box->event_list[i]->hw;
 362                 c = hwc->constraint;
 363
 364                 /* never assigned */
 365                 if (hwc->idx == -1)
 366                         break;
 367
 368                 /* constraint still honored */
 369                 if (!test_bit(hwc->idx, c->idxmsk))
 370                         break;
 371
 372                 /* not already used */
 373                 if (test_bit(hwc->idx, used_mask))
 374                         break;
 375
 376                 __set_bit(hwc->idx, used_mask);
 377                 if (assign)
 378                         assign[i] = hwc->idx;
 379         }
 380         /* slow path */
 381         if (i != n)
 382                 ret = perf_assign_events(box->event_list, n,
 383                                          wmin, wmax, assign);
 384
 385         if (!assign || ret) {
 386                 for (i = 0; i < n; i++)
 387                         uncore_put_event_constraint(box, box->event_list[i]);
 388         }
 389         return ret ? -EINVAL : 0;
 390 }
 391
 392 static void uncore_pmu_event_start(struct perf_event *event, int flags)
 393 {
 394         struct intel_uncore_box *box = uncore_event_to_box(event);
 395         int idx = event->hw.idx;
 396
 397         if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
 398                 return;
 399
 400         if (WARN_ON_ONCE(idx == -1 || idx >= UNCORE_PMC_IDX_MAX))
 401                 return;
 402
 403         event->hw.state = 0;
 404         box->events[idx] = event;
 405         box->n_active++;
 406         __set_bit(idx, box->active_mask);
 407
 408         local64_set(&event->hw.prev_count, uncore_read_counter(box, event));
 409         uncore_enable_event(box, event);
 410
 411         if (box->n_active == 1) {
 412                 uncore_enable_box(box);
 413                 uncore_pmu_start_hrtimer(box);
 414         }
 415 }
 416
 417 static void uncore_pmu_event_stop(struct perf_event *event, int flags)
 418 {
 419         struct intel_uncore_box *box = uncore_event_to_box(event);
 420         struct hw_perf_event *hwc = &event->hw;
 421
 422         if (__test_and_clear_bit(hwc->idx, box->active_mask)) {
 423                 uncore_disable_event(box, event);
 424                 box->n_active--;
 425                 box->events[hwc->idx] = NULL;
 426                 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
 427                 hwc->state |= PERF_HES_STOPPED;
 428
 429                 if (box->n_active == 0) {
 430                         uncore_disable_box(box);
 431                         uncore_pmu_cancel_hrtimer(box);
 432                 }
 433         }
 434
 435         if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
 436                 /*
 437                  * Drain the remaining delta count out of a event
 438                  * that we are disabling:
 439                  */
 440                 uncore_perf_event_update(box, event);
 441                 hwc->state |= PERF_HES_UPTODATE;
 442         }
 443 }
 444
 445 static int uncore_pmu_event_add(struct perf_event *event, int flags)
 446 {
 447         struct intel_uncore_box *box = uncore_event_to_box(event);
 448         struct hw_perf_event *hwc = &event->hw;
 449         int assign[UNCORE_PMC_IDX_MAX];
 450         int i, n, ret;
 451
 452         if (!box)
 453                 return -ENODEV;
 454
 455         ret = n = uncore_collect_events(box, event, false);
 456         if (ret < 0)
 457                 return ret;
 458
 459         hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
 460         if (!(flags & PERF_EF_START))
 461                 hwc->state |= PERF_HES_ARCH;
 462
 463         ret = uncore_assign_events(box, assign, n);
 464         if (ret)
 465                 return ret;
 466
 467         /* save events moving to new counters */
 468         for (i = 0; i < box->n_events; i++) {
 469                 event = box->event_list[i];
 470                 hwc = &event->hw;
 471
 472                 if (hwc->idx == assign[i] &&
 473                         hwc->last_tag == box->tags[assign[i]])
 474                         continue;
 475                 /*
 476                  * Ensure we don't accidentally enable a stopped
 477                  * counter simply because we rescheduled.
 478                  */
 479                 if (hwc->state & PERF_HES_STOPPED)
 480                         hwc->state |= PERF_HES_ARCH;
 481
 482                 uncore_pmu_event_stop(event, PERF_EF_UPDATE);
 483         }
 484
 485         /* reprogram moved events into new counters */
 486         for (i = 0; i < n; i++) {
 487                 event = box->event_list[i];
 488                 hwc = &event->hw;
 489
 490                 if (hwc->idx != assign[i] ||
 491                         hwc->last_tag != box->tags[assign[i]])
 492                         uncore_assign_hw_event(box, event, assign[i]);
 493                 else if (i < box->n_events)
 494                         continue;
 495
 496                 if (hwc->state & PERF_HES_ARCH)
 497                         continue;
 498
 499                 uncore_pmu_event_start(event, 0);
 500         }
 501         box->n_events = n;
 502
 503         return 0;
 504 }
 505
 506 static void uncore_pmu_event_del(struct perf_event *event, int flags)
 507 {
 508         struct intel_uncore_box *box = uncore_event_to_box(event);
 509         int i;
 510
 511         uncore_pmu_event_stop(event, PERF_EF_UPDATE);
 512
 513         for (i = 0; i < box->n_events; i++) {
 514                 if (event == box->event_list[i]) {
 515                         uncore_put_event_constraint(box, event);
 516
 517                         while (++i < box->n_events)
 518                                 box->event_list[i - 1] = box->event_list[i];
 519
 520                         --box->n_events;
 521                         break;
 522                 }
 523         }
 524
 525         event->hw.idx = -1;
 526         event->hw.last_tag = ~0ULL;
 527 }
 528
 529 void uncore_pmu_event_read(struct perf_event *event)
 530 {
 531         struct intel_uncore_box *box = uncore_event_to_box(event);
 532         uncore_perf_event_update(box, event);
 533 }
 534
 535 /*
 536  * validation ensures the group can be loaded onto the
 537  * PMU if it was the only group available.
 538  */
 539 static int uncore_validate_group(struct intel_uncore_pmu *pmu,
 540                                 struct perf_event *event)
 541 {
 542         struct perf_event *leader = event->group_leader;
 543         struct intel_uncore_box *fake_box;
 544         int ret = -EINVAL, n;
 545
 546         fake_box = uncore_alloc_box(pmu->type, NUMA_NO_NODE);
 547         if (!fake_box)
 548                 return -ENOMEM;
 549
 550         fake_box->pmu = pmu;
 551         /*
 552          * the event is not yet connected with its
 553          * siblings therefore we must first collect
 554          * existing siblings, then add the new event
 555          * before we can simulate the scheduling
 556          */
 557         n = uncore_collect_events(fake_box, leader, true);
 558         if (n < 0)
 559                 goto out;
 560
 561         fake_box->n_events = n;
 562         n = uncore_collect_events(fake_box, event, false);
 563         if (n < 0)
 564                 goto out;
 565
 566         fake_box->n_events = n;
 567
 568         ret = uncore_assign_events(fake_box, NULL, n);
 569 out:
 570         kfree(fake_box);
 571         return ret;
 572 }
 573
 574 static int uncore_pmu_event_init(struct perf_event *event)
 575 {
 576         struct intel_uncore_pmu *pmu;
 577         struct intel_uncore_box *box;
 578         struct hw_perf_event *hwc = &event->hw;
 579         int ret;
 580
 581         if (event->attr.type != event->pmu->type)
 582                 return -ENOENT;
 583
 584         pmu = uncore_event_to_pmu(event);
 585         /* no device found for this pmu */
 586         if (pmu->func_id < 0)
 587                 return -ENOENT;
 588
 589         /*
 590          * Uncore PMU does measure at all privilege level all the time.
 591          * So it doesn't make sense to specify any exclude bits.
 592          */
 593         if (event->attr.exclude_user || event->attr.exclude_kernel ||
 594                         event->attr.exclude_hv || event->attr.exclude_idle)
 595                 return -EINVAL;
 596
 597         /* Sampling not supported yet */
 598         if (hwc->sample_period)
 599                 return -EINVAL;
 600
 601         /*
 602          * Place all uncore events for a particular physical package
 603          * onto a single cpu
 604          */
 605         if (event->cpu < 0)
 606                 return -EINVAL;
 607         box = uncore_pmu_to_box(pmu, event->cpu);
 608         if (!box || box->cpu < 0)
 609                 return -EINVAL;
 610         event->cpu = box->cpu;
 611
 612         event->hw.idx = -1;
 613         event->hw.last_tag = ~0ULL;
 614         event->hw.extra_reg.idx = EXTRA_REG_NONE;
 615         event->hw.branch_reg.idx = EXTRA_REG_NONE;
 616
 617         if (event->attr.config == UNCORE_FIXED_EVENT) {
 618                 /* no fixed counter */
 619                 if (!pmu->type->fixed_ctl)
 620                         return -EINVAL;
 621                 /*
 622                  * if there is only one fixed counter, only the first pmu
 623                  * can access the fixed counter
 624                  */
 625                 if (pmu->type->single_fixed && pmu->pmu_idx > 0)
 626                         return -EINVAL;
 627
 628                 /* fixed counters have event field hardcoded to zero */
 629                 hwc->config = 0ULL;
 630         } else {
 631                 hwc->config = event->attr.config & pmu->type->event_mask;
 632                 if (pmu->type->ops->hw_config) {
 633                         ret = pmu->type->ops->hw_config(box, event);
 634                         if (ret)
 635                                 return ret;
 636                 }
 637         }
 638
 639         if (event->group_leader != event)
 640                 ret = uncore_validate_group(pmu, event);
 641         else
 642                 ret = 0;
 643
 644         return ret;
 645 }
 646
 647 static ssize_t uncore_get_attr_cpumask(struct device *dev,
 648                                 struct device_attribute *attr, char *buf)
 649 {
 650         int n = cpulist_scnprintf(buf, PAGE_SIZE - 2, &uncore_cpu_mask);
 651
 652         buf[n++] = '\n';
 653         buf[n] = '\0';
 654         return n;
 655 }
 656
 657 static DEVICE_ATTR(cpumask, S_IRUGO, uncore_get_attr_cpumask, NULL);
 658
 659 static struct attribute *uncore_pmu_attrs[] = {
 660         &dev_attr_cpumask.attr,
 661         NULL,
 662 };
 663
 664 static struct attribute_group uncore_pmu_attr_group = {
 665         .attrs = uncore_pmu_attrs,
 666 };
 667
 668 static int uncore_pmu_register(struct intel_uncore_pmu *pmu)
 669 {
 670         int ret;
 671
 672         if (!pmu->type->pmu) {
 673                 pmu->pmu = (struct pmu) {
 674                         .attr_groups    = pmu->type->attr_groups,
 675                         .task_ctx_nr    = perf_invalid_context,
 676                         .event_init     = uncore_pmu_event_init,
 677                         .add            = uncore_pmu_event_add,
 678                         .del            = uncore_pmu_event_del,
 679                         .start          = uncore_pmu_event_start,
 680                         .stop           = uncore_pmu_event_stop,
 681                         .read           = uncore_pmu_event_read,
 682                 };
 683         } else {
 684                 pmu->pmu = *pmu->type->pmu;
 685                 pmu->pmu.attr_groups = pmu->type->attr_groups;
 686         }
 687
 688         if (pmu->type->num_boxes == 1) {
 689                 if (strlen(pmu->type->name) > 0)
 690                         sprintf(pmu->name, "uncore_%s", pmu->type->name);
 691                 else
 692                         sprintf(pmu->name, "uncore");
 693         } else {
 694                 sprintf(pmu->name, "uncore_%s_%d", pmu->type->name,
 695                         pmu->pmu_idx);
 696         }
 697
 698         ret = perf_pmu_register(&pmu->pmu, pmu->name, -1);
 699         return ret;
 700 }
 701
 702 static void __init uncore_type_exit(struct intel_uncore_type *type)
 703 {
 704         int i;
 705
 706         for (i = 0; i < type->num_boxes; i++)
 707                 free_percpu(type->pmus[i].box);
 708         kfree(type->pmus);
 709         type->pmus = NULL;
 710         kfree(type->events_group);
 711         type->events_group = NULL;
 712 }
 713
 714 static void __init uncore_types_exit(struct intel_uncore_type **types)
 715 {
 716         int i;
 717         for (i = 0; types[i]; i++)
 718                 uncore_type_exit(types[i]);
 719 }
 720
 721 static int __init uncore_type_init(struct intel_uncore_type *type)
 722 {
 723         struct intel_uncore_pmu *pmus;
 724         struct attribute_group *attr_group;
 725         struct attribute **attrs;
 726         int i, j;
 727
 728         pmus = kzalloc(sizeof(*pmus) * type->num_boxes, GFP_KERNEL);
 729         if (!pmus)
 730                 return -ENOMEM;
 731
 732         type->pmus = pmus;
 733
 734         type->unconstrainted = (struct event_constraint)
 735                 __EVENT_CONSTRAINT(0, (1ULL << type->num_counters) - 1,
 736                                 0, type->num_counters, 0, 0);
 737
 738         for (i = 0; i < type->num_boxes; i++) {
 739                 pmus[i].func_id = -1;
 740                 pmus[i].pmu_idx = i;
 741                 pmus[i].type = type;
 742                 INIT_LIST_HEAD(&pmus[i].box_list);
 743                 pmus[i].box = alloc_percpu(struct intel_uncore_box *);
 744                 if (!pmus[i].box)
 745                         goto fail;
 746         }
 747
 748         if (type->event_descs) {
 749                 i = 0;
 750                 while (type->event_descs[i].attr.attr.name)
 751                         i++;
 752
 753                 attr_group = kzalloc(sizeof(struct attribute *) * (i + 1) +
 754                                         sizeof(*attr_group), GFP_KERNEL);
 755                 if (!attr_group)
 756                         goto fail;
 757
 758                 attrs = (struct attribute **)(attr_group + 1);
 759                 attr_group->name = "events";
 760                 attr_group->attrs = attrs;
 761
 762                 for (j = 0; j < i; j++)
 763                         attrs[j] = &type->event_descs[j].attr.attr;
 764
 765                 type->events_group = attr_group;
 766         }
 767
 768         type->pmu_group = &uncore_pmu_attr_group;
 769         return 0;
 770 fail:
 771         uncore_type_exit(type);
 772         return -ENOMEM;
 773 }
 774
 775 static int __init uncore_types_init(struct intel_uncore_type **types)
 776 {
 777         int i, ret;
 778
 779         for (i = 0; types[i]; i++) {
 780                 ret = uncore_type_init(types[i]);
 781                 if (ret)
 782                         goto fail;
 783         }
 784         return 0;
 785 fail:
 786         while (--i >= 0)
 787                 uncore_type_exit(types[i]);
 788         return ret;
 789 }
 790
 791 /*
 792  * add a pci uncore device
 793  */
 794 static int uncore_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 795 {
 796         struct intel_uncore_pmu *pmu;
 797         struct intel_uncore_box *box;
 798         struct intel_uncore_type *type;
 799         int phys_id;
 800         bool first_box = false;
 801
 802         phys_id = uncore_pcibus_to_physid[pdev->bus->number];
 803         if (phys_id < 0)
 804                 return -ENODEV;
 805
 806         if (UNCORE_PCI_DEV_TYPE(id->driver_data) == UNCORE_EXTRA_PCI_DEV) {
 807                 int idx = UNCORE_PCI_DEV_IDX(id->driver_data);
 808                 uncore_extra_pci_dev[phys_id][idx] = pdev;
 809                 pci_set_drvdata(pdev, NULL);
 810                 return 0;
 811         }
 812
 813         type = uncore_pci_uncores[UNCORE_PCI_DEV_TYPE(id->driver_data)];
 814         box = uncore_alloc_box(type, NUMA_NO_NODE);
 815         if (!box)
 816                 return -ENOMEM;
 817
 818         /*
 819          * for performance monitoring unit with multiple boxes,
 820          * each box has a different function id.
 821          */
 822         pmu = &type->pmus[UNCORE_PCI_DEV_IDX(id->driver_data)];
 823         if (pmu->func_id < 0)
 824                 pmu->func_id = pdev->devfn;
 825         else
 826                 WARN_ON_ONCE(pmu->func_id != pdev->devfn);
 827
 828         box->phys_id = phys_id;
 829         box->pci_dev = pdev;
 830         box->pmu = pmu;
 831         uncore_box_init(box);
 832         pci_set_drvdata(pdev, box);
 833
 834         raw_spin_lock(&uncore_box_lock);
 835         if (list_empty(&pmu->box_list))
 836                 first_box = true;
 837         list_add_tail(&box->list, &pmu->box_list);
 838         raw_spin_unlock(&uncore_box_lock);
 839
 840         if (first_box)
 841                 uncore_pmu_register(pmu);
 842         return 0;
 843 }
 844
 845 static void uncore_pci_remove(struct pci_dev *pdev)
 846 {
 847         struct intel_uncore_box *box = pci_get_drvdata(pdev);
 848         struct intel_uncore_pmu *pmu;
 849         int i, cpu, phys_id = uncore_pcibus_to_physid[pdev->bus->number];
 850         bool last_box = false;
 851
 852         box = pci_get_drvdata(pdev);
 853         if (!box) {
 854                 for (i = 0; i < UNCORE_EXTRA_PCI_DEV_MAX; i++) {
 855                         if (uncore_extra_pci_dev[phys_id][i] == pdev) {
 856                                 uncore_extra_pci_dev[phys_id][i] = NULL;
 857                                 break;
 858                         }
 859                 }
 860                 WARN_ON_ONCE(i >= UNCORE_EXTRA_PCI_DEV_MAX);
 861                 return;
 862         }
 863
 864         pmu = box->pmu;
 865         if (WARN_ON_ONCE(phys_id != box->phys_id))
 866                 return;
 867
 868         pci_set_drvdata(pdev, NULL);
 869
 870         raw_spin_lock(&uncore_box_lock);
 871         list_del(&box->list);
 872         if (list_empty(&pmu->box_list))
 873                 last_box = true;
 874         raw_spin_unlock(&uncore_box_lock);
 875
 876         for_each_possible_cpu(cpu) {
 877                 if (*per_cpu_ptr(pmu->box, cpu) == box) {
 878                         *per_cpu_ptr(pmu->box, cpu) = NULL;
 879                         atomic_dec(&box->refcnt);
 880                 }
 881         }
 882
 883         WARN_ON_ONCE(atomic_read(&box->refcnt) != 1);
 884         kfree(box);
 885
 886         if (last_box)
 887                 perf_pmu_unregister(&pmu->pmu);
 888 }
 889
 890 static int __init uncore_pci_init(void)
 891 {
 892         int ret;
 893
 894         switch (boot_cpu_data.x86_model) {
 895         case 45: /* Sandy Bridge-EP */
 896                 ret = snbep_uncore_pci_init();
 897                 break;
 898         case 62: /* Ivy Bridge-EP */
 899                 ret = ivbep_uncore_pci_init();
 900                 break;
 901         case 63: /* Haswell-EP */
 902                 ret = hswep_uncore_pci_init();
 903                 break;
 904         case 42: /* Sandy Bridge */
 905                 ret = snb_uncore_pci_init();
 906                 break;
 907         case 58: /* Ivy Bridge */
 908                 ret = ivb_uncore_pci_init();
 909                 break;
 910         case 60: /* Haswell */
 911         case 69: /* Haswell Celeron */
 912                 ret = hsw_uncore_pci_init();
 913                 break;
 914         default:
 915                 return 0;
 916         }
 917
 918         if (ret)
 919                 return ret;
 920
 921         ret = uncore_types_init(uncore_pci_uncores);
 922         if (ret)
 923                 return ret;
 924
 925         uncore_pci_driver->probe = uncore_pci_probe;
 926         uncore_pci_driver->remove = uncore_pci_remove;
 927
 928         ret = pci_register_driver(uncore_pci_driver);
 929         if (ret == 0)
 930                 pcidrv_registered = true;
 931         else
 932                 uncore_types_exit(uncore_pci_uncores);
 933
 934         return ret;
 935 }
 936
 937 static void __init uncore_pci_exit(void)
 938 {
 939         if (pcidrv_registered) {
 940                 pcidrv_registered = false;
 941                 pci_unregister_driver(uncore_pci_driver);
 942                 uncore_types_exit(uncore_pci_uncores);
 943         }
 944 }
 945
 946 /* CPU hot plug/unplug are serialized by cpu_add_remove_lock mutex */
 947 static LIST_HEAD(boxes_to_free);
 948
 949 static void uncore_kfree_boxes(void)
 950 {
 951         struct intel_uncore_box *box;
 952
 953         while (!list_empty(&boxes_to_free)) {
 954                 box = list_entry(boxes_to_free.next,
 955                                  struct intel_uncore_box, list);
 956                 list_del(&box->list);
 957                 kfree(box);
 958         }
 959 }
 960
 961 static void uncore_cpu_dying(int cpu)
 962 {
 963         struct intel_uncore_type *type;
 964         struct intel_uncore_pmu *pmu;
 965         struct intel_uncore_box *box;
 966         int i, j;
 967
 968         for (i = 0; uncore_msr_uncores[i]; i++) {
 969                 type = uncore_msr_uncores[i];
 970                 for (j = 0; j < type->num_boxes; j++) {
 971                         pmu = &type->pmus[j];
 972                         box = *per_cpu_ptr(pmu->box, cpu);
 973                         *per_cpu_ptr(pmu->box, cpu) = NULL;
 974                         if (box && atomic_dec_and_test(&box->refcnt))
 975                                 list_add(&box->list, &boxes_to_free);
 976                 }
 977         }
 978 }
 979
 980 static int uncore_cpu_starting(int cpu)
 981 {
 982         struct intel_uncore_type *type;
 983         struct intel_uncore_pmu *pmu;
 984         struct intel_uncore_box *box, *exist;
 985         int i, j, k, phys_id;
 986
 987         phys_id = topology_physical_package_id(cpu);
 988
 989         for (i = 0; uncore_msr_uncores[i]; i++) {
 990                 type = uncore_msr_uncores[i];
 991                 for (j = 0; j < type->num_boxes; j++) {
 992                         pmu = &type->pmus[j];
 993                         box = *per_cpu_ptr(pmu->box, cpu);
 994                         /* called by uncore_cpu_init? */
 995                         if (box && box->phys_id >= 0) {
 996                                 uncore_box_init(box);
 997                                 continue;
 998                         }
 999
1000                         for_each_online_cpu(k) {
1001                                 exist = *per_cpu_ptr(pmu->box, k);
1002                                 if (exist && exist->phys_id == phys_id) {
1003                                         atomic_inc(&exist->refcnt);
1004                                         *per_cpu_ptr(pmu->box, cpu) = exist;
1005                                         if (box) {
1006                                                 list_add(&box->list,
1007                                                          &boxes_to_free);
1008                                                 box = NULL;
1009                                         }
1010                                         break;
1011                                 }
1012                         }
1013
1014                         if (box) {
1015                                 box->phys_id = phys_id;
1016                                 uncore_box_init(box);
1017                         }
1018                 }
1019         }
1020         return 0;
1021 }
1022
1023 static int uncore_cpu_prepare(int cpu, int phys_id)
1024 {
1025         struct intel_uncore_type *type;
1026         struct intel_uncore_pmu *pmu;
1027         struct intel_uncore_box *box;
1028         int i, j;
1029
1030         for (i = 0; uncore_msr_uncores[i]; i++) {
1031                 type = uncore_msr_uncores[i];
1032                 for (j = 0; j < type->num_boxes; j++) {
1033                         pmu = &type->pmus[j];
1034                         if (pmu->func_id < 0)
1035                                 pmu->func_id = j;
1036
1037                         box = uncore_alloc_box(type, cpu_to_node(cpu));
1038                         if (!box)
1039                                 return -ENOMEM;
1040
1041                         box->pmu = pmu;
1042                         box->phys_id = phys_id;
1043                         *per_cpu_ptr(pmu->box, cpu) = box;
1044                 }
1045         }
1046         return 0;
1047 }
1048
1049 static void
1050 uncore_change_context(struct intel_uncore_type **uncores, int old_cpu, int new_cpu)
1051 {
1052         struct intel_uncore_type *type;
1053         struct intel_uncore_pmu *pmu;
1054         struct intel_uncore_box *box;
1055         int i, j;
1056
1057         for (i = 0; uncores[i]; i++) {
1058                 type = uncores[i];
1059                 for (j = 0; j < type->num_boxes; j++) {
1060                         pmu = &type->pmus[j];
1061                         if (old_cpu < 0)
1062                                 box = uncore_pmu_to_box(pmu, new_cpu);
1063                         else
1064                                 box = uncore_pmu_to_box(pmu, old_cpu);
1065                         if (!box)
1066                                 continue;
1067
1068                         if (old_cpu < 0) {
1069                                 WARN_ON_ONCE(box->cpu != -1);
1070                                 box->cpu = new_cpu;
1071                                 continue;
1072                         }
1073
1074                         WARN_ON_ONCE(box->cpu != old_cpu);
1075                         if (new_cpu >= 0) {
1076                                 uncore_pmu_cancel_hrtimer(box);
1077                                 perf_pmu_migrate_context(&pmu->pmu,
1078                                                 old_cpu, new_cpu);
1079                                 box->cpu = new_cpu;
1080                         } else {
1081                                 box->cpu = -1;
1082                         }
1083                 }
1084         }
1085 }
1086
1087 static void uncore_event_exit_cpu(int cpu)
1088 {
1089         int i, phys_id, target;
1090
1091         /* if exiting cpu is used for collecting uncore events */
1092         if (!cpumask_test_and_clear_cpu(cpu, &uncore_cpu_mask))
1093                 return;
1094
1095         /* find a new cpu to collect uncore events */
1096         phys_id = topology_physical_package_id(cpu);
1097         target = -1;
1098         for_each_online_cpu(i) {
1099                 if (i == cpu)
1100                         continue;
1101                 if (phys_id == topology_physical_package_id(i)) {
1102                         target = i;
1103                         break;
1104                 }
1105         }
1106
1107         /* migrate uncore events to the new cpu */
1108         if (target >= 0)
1109                 cpumask_set_cpu(target, &uncore_cpu_mask);
1110
1111         uncore_change_context(uncore_msr_uncores, cpu, target);
1112         uncore_change_context(uncore_pci_uncores, cpu, target);
1113 }
1114
1115 static void uncore_event_init_cpu(int cpu)
1116 {
1117         int i, phys_id;
1118
1119         phys_id = topology_physical_package_id(cpu);
1120         for_each_cpu(i, &uncore_cpu_mask) {
1121                 if (phys_id == topology_physical_package_id(i))
1122                         return;
1123         }
1124
1125         cpumask_set_cpu(cpu, &uncore_cpu_mask);
1126
1127         uncore_change_context(uncore_msr_uncores, -1, cpu);
1128         uncore_change_context(uncore_pci_uncores, -1, cpu);
1129 }
1130
1131 static int uncore_cpu_notifier(struct notifier_block *self,
1132                                unsigned long action, void *hcpu)
1133 {
1134         unsigned int cpu = (long)hcpu;
1135
1136         /* allocate/free data structure for uncore box */
1137         switch (action & ~CPU_TASKS_FROZEN) {
1138         case CPU_UP_PREPARE:
1139                 uncore_cpu_prepare(cpu, -1);
1140                 break;
1141         case CPU_STARTING:
1142                 uncore_cpu_starting(cpu);
1143                 break;
1144         case CPU_UP_CANCELED:
1145         case CPU_DYING:
1146                 uncore_cpu_dying(cpu);
1147                 break;
1148         case CPU_ONLINE:
1149         case CPU_DEAD:
1150                 uncore_kfree_boxes();
1151                 break;
1152         default:
1153                 break;
1154         }
1155
1156         /* select the cpu that collects uncore events */
1157         switch (action & ~CPU_TASKS_FROZEN) {
1158         case CPU_DOWN_FAILED:
1159         case CPU_STARTING:
1160                 uncore_event_init_cpu(cpu);
1161                 break;
1162         case CPU_DOWN_PREPARE:
1163                 uncore_event_exit_cpu(cpu);
1164                 break;
1165         default:
1166                 break;
1167         }
1168
1169         return NOTIFY_OK;
1170 }
1171
1172 static struct notifier_block uncore_cpu_nb = {
1173         .notifier_call  = uncore_cpu_notifier,
1174         /*
1175          * to migrate uncore events, our notifier should be executed
1176          * before perf core's notifier.
1177          */
1178         .priority       = CPU_PRI_PERF + 1,
1179 };
1180
1181 static void __init uncore_cpu_setup(void *dummy)
1182 {
1183         uncore_cpu_starting(smp_processor_id());
1184 }
1185
1186 static int __init uncore_cpu_init(void)
1187 {
1188         int ret;
1189
1190         switch (boot_cpu_data.x86_model) {
1191         case 26: /* Nehalem */
1192         case 30:
1193         case 37: /* Westmere */
1194         case 44:
1195                 nhm_uncore_cpu_init();
1196                 break;
1197         case 42: /* Sandy Bridge */
1198         case 58: /* Ivy Bridge */
1199                 snb_uncore_cpu_init();
1200                 break;
1201         case 45: /* Sandy Bridge-EP */
1202                 snbep_uncore_cpu_init();
1203                 break;
1204         case 46: /* Nehalem-EX */
1205         case 47: /* Westmere-EX aka. Xeon E7 */
1206                 nhmex_uncore_cpu_init();
1207                 break;
1208         case 62: /* Ivy Bridge-EP */
1209                 ivbep_uncore_cpu_init();
1210                 break;
1211         case 63: /* Haswell-EP */
1212                 hswep_uncore_cpu_init();
1213                 break;
1214         default:
1215                 return 0;
1216         }
1217
1218         ret = uncore_types_init(uncore_msr_uncores);
1219         if (ret)
1220                 return ret;
1221
1222         return 0;
1223 }
1224
1225 static int __init uncore_pmus_register(void)
1226 {
1227         struct intel_uncore_pmu *pmu;
1228         struct intel_uncore_type *type;
1229         int i, j;
1230
1231         for (i = 0; uncore_msr_uncores[i]; i++) {
1232                 type = uncore_msr_uncores[i];
1233                 for (j = 0; j < type->num_boxes; j++) {
1234                         pmu = &type->pmus[j];
1235                         uncore_pmu_register(pmu);
1236                 }
1237         }
1238
1239         return 0;
1240 }
1241
1242 static void __init uncore_cpumask_init(void)
1243 {
1244         int cpu;
1245
1246         /*
1247          * ony invoke once from msr or pci init code
1248          */
1249         if (!cpumask_empty(&uncore_cpu_mask))
1250                 return;
1251
1252         cpu_notifier_register_begin();
1253
1254         for_each_online_cpu(cpu) {
1255                 int i, phys_id = topology_physical_package_id(cpu);
1256
1257                 for_each_cpu(i, &uncore_cpu_mask) {
1258                         if (phys_id == topology_physical_package_id(i)) {
1259                                 phys_id = -1;
1260                                 break;
1261                         }
1262                 }
1263                 if (phys_id < 0)
1264                         continue;
1265
1266                 uncore_cpu_prepare(cpu, phys_id);
1267                 uncore_event_init_cpu(cpu);
1268         }
1269         on_each_cpu(uncore_cpu_setup, NULL, 1);
1270
1271         __register_cpu_notifier(&uncore_cpu_nb);
1272
1273         cpu_notifier_register_done();
1274 }
1275
1276
1277 static int __init intel_uncore_init(void)
1278 {
1279         int ret;
1280
1281         if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
1282                 return -ENODEV;
1283
1284         if (cpu_has_hypervisor)
1285                 return -ENODEV;
1286
1287         ret = uncore_pci_init();
1288         if (ret)
1289                 goto fail;
1290         ret = uncore_cpu_init();
1291         if (ret) {
1292                 uncore_pci_exit();
1293                 goto fail;
1294         }
1295         uncore_cpumask_init();
1296
1297         uncore_pmus_register();
1298         return 0;
1299 fail:
1300         return ret;
1301 }
1302 device_initcall(intel_uncore_init);