arch/x86/kernel/i387.c

   1 /*
   2  *  Copyright (C) 1994 Linus Torvalds
   3  *
   4  *  Pentium III FXSR, SSE support
   5  *  General FPU state handling cleanups
   6  *      Gareth Hughes <gareth@valinux.com>, May 2000
   7  */
   8 #include <linux/module.h>
   9 #include <linux/regset.h>
  10 #include <linux/sched.h>
  11 #include <linux/slab.h>
  12
  13 #include <asm/sigcontext.h>
  14 #include <asm/processor.h>
  15 #include <asm/math_emu.h>
  16 #include <asm/uaccess.h>
  17 #include <asm/ptrace.h>
  18 #include <asm/i387.h>
  19 #include <asm/fpu-internal.h>
  20 #include <asm/user.h>
  21
  22 /*
  23  * Were we in an interrupt that interrupted kernel mode?
  24  *
  25  * On others, we can do a kernel_fpu_begin/end() pair *ONLY* if that
  26  * pair does nothing at all: the thread must not have fpu (so
  27  * that we don't try to save the FPU state), and TS must
  28  * be set (so that the clts/stts pair does nothing that is
  29  * visible in the interrupted kernel thread).
  30  *
  31  * Except for the eagerfpu case when we return 1 unless we've already
  32  * been eager and saved the state in kernel_fpu_begin().
  33  */
  34 static inline bool interrupted_kernel_fpu_idle(void)
  35 {
  36         if (use_eager_fpu())
  37                 return __thread_has_fpu(current);
  38
  39         return !__thread_has_fpu(current) &&
  40                 (read_cr0() & X86_CR0_TS);
  41 }
  42
  43 /*
  44  * Were we in user mode (or vm86 mode) when we were
  45  * interrupted?
  46  *
  47  * Doing kernel_fpu_begin/end() is ok if we are running
  48  * in an interrupt context from user mode - we'll just
  49  * save the FPU state as required.
  50  */
  51 static inline bool interrupted_user_mode(void)
  52 {
  53         struct pt_regs *regs = get_irq_regs();
  54         return regs && user_mode_vm(regs);
  55 }
  56
  57 /*
  58  * Can we use the FPU in kernel mode with the
  59  * whole "kernel_fpu_begin/end()" sequence?
  60  *
  61  * It's always ok in process context (ie "not interrupt")
  62  * but it is sometimes ok even from an irq.
  63  */
  64 bool irq_fpu_usable(void)
  65 {
  66         return !in_interrupt() ||
  67                 interrupted_user_mode() ||
  68                 interrupted_kernel_fpu_idle();
  69 }
  70 EXPORT_SYMBOL(irq_fpu_usable);
  71
  72 void __kernel_fpu_begin(void)
  73 {
  74         struct task_struct *me = current;
  75
  76         if (__thread_has_fpu(me)) {
  77                 __thread_clear_has_fpu(me);
  78                 __save_init_fpu(me);
  79                 /* We do 'stts()' in __kernel_fpu_end() */
  80         } else if (!use_eager_fpu()) {
  81                 this_cpu_write(fpu_owner_task, NULL);
  82                 clts();
  83         }
  84 }
  85 EXPORT_SYMBOL(__kernel_fpu_begin);
  86
  87 void __kernel_fpu_end(void)
  88 {
  89         if (use_eager_fpu())
  90                 math_state_restore();
  91         else
  92                 stts();
  93 }
  94 EXPORT_SYMBOL(__kernel_fpu_end);
  95
  96 void unlazy_fpu(struct task_struct *tsk)
  97 {
  98         preempt_disable();
  99         if (__thread_has_fpu(tsk)) {
 100                 __save_init_fpu(tsk);
 101                 __thread_fpu_end(tsk);
 102         } else
 103                 tsk->thread.fpu_counter = 0;
 104         preempt_enable();
 105 }
 106 EXPORT_SYMBOL(unlazy_fpu);
 107
 108 unsigned int mxcsr_feature_mask __read_mostly = 0xffffffffu;
 109 unsigned int xstate_size;
 110 EXPORT_SYMBOL_GPL(xstate_size);
 111 static struct i387_fxsave_struct fx_scratch;
 112
 113 static void mxcsr_feature_mask_init(void)
 114 {
 115         unsigned long mask = 0;
 116
 117         if (cpu_has_fxsr) {
 118                 memset(&fx_scratch, 0, sizeof(struct i387_fxsave_struct));
 119                 asm volatile("fxsave %0" : "+m" (fx_scratch));
 120                 mask = fx_scratch.mxcsr_mask;
 121                 if (mask == 0)
 122                         mask = 0x0000ffbf;
 123         }
 124         mxcsr_feature_mask &= mask;
 125 }
 126
 127 static void init_thread_xstate(void)
 128 {
 129         /*
 130          * Note that xstate_size might be overwriten later during
 131          * xsave_init().
 132          */
 133
 134         if (!cpu_has_fpu) {
 135                 /*
 136                  * Disable xsave as we do not support it if i387
 137                  * emulation is enabled.
 138                  */
 139                 setup_clear_cpu_cap(X86_FEATURE_XSAVE);
 140                 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
 141                 xstate_size = sizeof(struct i387_soft_struct);
 142                 return;
 143         }
 144
 145         if (cpu_has_fxsr)
 146                 xstate_size = sizeof(struct i387_fxsave_struct);
 147         else
 148                 xstate_size = sizeof(struct i387_fsave_struct);
 149 }
 150
 151 /*
 152  * Called at bootup to set up the initial FPU state that is later cloned
 153  * into all processes.
 154  */
 155
 156 void fpu_init(void)
 157 {
 158         unsigned long cr0;
 159         unsigned long cr4_mask = 0;
 160
 161 #ifndef CONFIG_MATH_EMULATION
 162         if (!cpu_has_fpu) {
 163                 pr_emerg("No FPU found and no math emulation present\n");
 164                 pr_emerg("Giving up\n");
 165                 for (;;)
 166                         asm volatile("hlt");
 167         }
 168 #endif
 169         if (cpu_has_fxsr)
 170                 cr4_mask |= X86_CR4_OSFXSR;
 171         if (cpu_has_xmm)
 172                 cr4_mask |= X86_CR4_OSXMMEXCPT;
 173         if (cr4_mask)
 174                 set_in_cr4(cr4_mask);
 175
 176         cr0 = read_cr0();
 177         cr0 &= ~(X86_CR0_TS|X86_CR0_EM); /* clear TS and EM */
 178         if (!cpu_has_fpu)
 179                 cr0 |= X86_CR0_EM;
 180         write_cr0(cr0);
 181
 182         /*
 183          * init_thread_xstate is only called once to avoid overriding
 184          * xstate_size during boot time or during CPU hotplug.
 185          */
 186         if (xstate_size == 0)
 187                 init_thread_xstate();
 188
 189         mxcsr_feature_mask_init();
 190         xsave_init();
 191         eager_fpu_init();
 192 }
 193
 194 void fpu_finit(struct fpu *fpu)
 195 {
 196         if (!cpu_has_fpu) {
 197                 finit_soft_fpu(&fpu->state->soft);
 198                 return;
 199         }
 200
 201         if (cpu_has_fxsr) {
 202                 fx_finit(&fpu->state->fxsave);
 203         } else {
 204                 struct i387_fsave_struct *fp = &fpu->state->fsave;
 205                 memset(fp, 0, xstate_size);
 206                 fp->cwd = 0xffff037fu;
 207                 fp->swd = 0xffff0000u;
 208                 fp->twd = 0xffffffffu;
 209                 fp->fos = 0xffff0000u;
 210         }
 211 }
 212 EXPORT_SYMBOL_GPL(fpu_finit);
 213
 214 /*
 215  * The _current_ task is using the FPU for the first time
 216  * so initialize it and set the mxcsr to its default
 217  * value at reset if we support XMM instructions and then
 218  * remember the current task has used the FPU.
 219  */
 220 int init_fpu(struct task_struct *tsk)
 221 {
 222         int ret;
 223
 224         if (tsk_used_math(tsk)) {
 225                 if (cpu_has_fpu && tsk == current)
 226                         unlazy_fpu(tsk);
 227                 tsk->thread.fpu.last_cpu = ~0;
 228                 return 0;
 229         }
 230
 231         /*
 232          * Memory allocation at the first usage of the FPU and other state.
 233          */
 234         ret = fpu_alloc(&tsk->thread.fpu);
 235         if (ret)
 236                 return ret;
 237
 238         fpu_finit(&tsk->thread.fpu);
 239
 240         set_stopped_child_used_math(tsk);
 241         return 0;
 242 }
 243 EXPORT_SYMBOL_GPL(init_fpu);
 244
 245 /*
 246  * The xstateregs_active() routine is the same as the fpregs_active() routine,
 247  * as the "regset->n" for the xstate regset will be updated based on the feature
 248  * capabilites supported by the xsave.
 249  */
 250 int fpregs_active(struct task_struct *target, const struct user_regset *regset)
 251 {
 252         return tsk_used_math(target) ? regset->n : 0;
 253 }
 254
 255 int xfpregs_active(struct task_struct *target, const struct user_regset *regset)
 256 {
 257         return (cpu_has_fxsr && tsk_used_math(target)) ? regset->n : 0;
 258 }
 259
 260 int xfpregs_get(struct task_struct *target, const struct user_regset *regset,
 261                 unsigned int pos, unsigned int count,
 262                 void *kbuf, void __user *ubuf)
 263 {
 264         int ret;
 265
 266         if (!cpu_has_fxsr)
 267                 return -ENODEV;
 268
 269         ret = init_fpu(target);
 270         if (ret)
 271                 return ret;
 272
 273         sanitize_i387_state(target);
 274
 275         return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
 276                                    &target->thread.fpu.state->fxsave, 0, -1);
 277 }
 278
 279 int xfpregs_set(struct task_struct *target, const struct user_regset *regset,
 280                 unsigned int pos, unsigned int count,
 281                 const void *kbuf, const void __user *ubuf)
 282 {
 283         int ret;
 284
 285         if (!cpu_has_fxsr)
 286                 return -ENODEV;
 287
 288         ret = init_fpu(target);
 289         if (ret)
 290                 return ret;
 291
 292         sanitize_i387_state(target);
 293
 294         ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
 295                                  &target->thread.fpu.state->fxsave, 0, -1);
 296
 297         /*
 298          * mxcsr reserved bits must be masked to zero for security reasons.
 299          */
 300         target->thread.fpu.state->fxsave.mxcsr &= mxcsr_feature_mask;
 301
 302         /*
 303          * update the header bits in the xsave header, indicating the
 304          * presence of FP and SSE state.
 305          */
 306         if (cpu_has_xsave)
 307                 target->thread.fpu.state->xsave.xsave_hdr.xstate_bv |= XSTATE_FPSSE;
 308
 309         return ret;
 310 }
 311
 312 int xstateregs_get(struct task_struct *target, const struct user_regset *regset,
 313                 unsigned int pos, unsigned int count,
 314                 void *kbuf, void __user *ubuf)
 315 {
 316         int ret;
 317
 318         if (!cpu_has_xsave)
 319                 return -ENODEV;
 320
 321         ret = init_fpu(target);
 322         if (ret)
 323                 return ret;
 324
 325         /*
 326          * Copy the 48bytes defined by the software first into the xstate
 327          * memory layout in the thread struct, so that we can copy the entire
 328          * xstateregs to the user using one user_regset_copyout().
 329          */
 330         memcpy(&target->thread.fpu.state->fxsave.sw_reserved,
 331                xstate_fx_sw_bytes, sizeof(xstate_fx_sw_bytes));
 332
 333         /*
 334          * Copy the xstate memory layout.
 335          */
 336         ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
 337                                   &target->thread.fpu.state->xsave, 0, -1);
 338         return ret;
 339 }
 340
 341 int xstateregs_set(struct task_struct *target, const struct user_regset *regset,
 342                   unsigned int pos, unsigned int count,
 343                   const void *kbuf, const void __user *ubuf)
 344 {
 345         int ret;
 346         struct xsave_hdr_struct *xsave_hdr;
 347
 348         if (!cpu_has_xsave)
 349                 return -ENODEV;
 350
 351         ret = init_fpu(target);
 352         if (ret)
 353                 return ret;
 354
 355         ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
 356                                  &target->thread.fpu.state->xsave, 0, -1);
 357
 358         /*
 359          * mxcsr reserved bits must be masked to zero for security reasons.
 360          */
 361         target->thread.fpu.state->fxsave.mxcsr &= mxcsr_feature_mask;
 362
 363         xsave_hdr = &target->thread.fpu.state->xsave.xsave_hdr;
 364
 365         xsave_hdr->xstate_bv &= pcntxt_mask;
 366         /*
 367          * These bits must be zero.
 368          */
 369         xsave_hdr->reserved1[0] = xsave_hdr->reserved1[1] = 0;
 370
 371         return ret;
 372 }
 373
 374 #if defined CONFIG_X86_32 || defined CONFIG_IA32_EMULATION
 375
 376 /*
 377  * FPU tag word conversions.
 378  */
 379
 380 static inline unsigned short twd_i387_to_fxsr(unsigned short twd)
 381 {
 382         unsigned int tmp; /* to avoid 16 bit prefixes in the code */
 383
 384         /* Transform each pair of bits into 01 (valid) or 00 (empty) */
 385         tmp = ~twd;
 386         tmp = (tmp | (tmp>>1)) & 0x5555; /* 0V0V0V0V0V0V0V0V */
 387         /* and move the valid bits to the lower byte. */
 388         tmp = (tmp | (tmp >> 1)) & 0x3333; /* 00VV00VV00VV00VV */
 389         tmp = (tmp | (tmp >> 2)) & 0x0f0f; /* 0000VVVV0000VVVV */
 390         tmp = (tmp | (tmp >> 4)) & 0x00ff; /* 00000000VVVVVVVV */
 391
 392         return tmp;
 393 }
 394
 395 #define FPREG_ADDR(f, n)        ((void *)&(f)->st_space + (n) * 16)
 396 #define FP_EXP_TAG_VALID        0
 397 #define FP_EXP_TAG_ZERO         1
 398 #define FP_EXP_TAG_SPECIAL      2
 399 #define FP_EXP_TAG_EMPTY        3
 400
 401 static inline u32 twd_fxsr_to_i387(struct i387_fxsave_struct *fxsave)
 402 {
 403         struct _fpxreg *st;
 404         u32 tos = (fxsave->swd >> 11) & 7;
 405         u32 twd = (unsigned long) fxsave->twd;
 406         u32 tag;
 407         u32 ret = 0xffff0000u;
 408         int i;
 409
 410         for (i = 0; i < 8; i++, twd >>= 1) {
 411                 if (twd & 0x1) {
 412                         st = FPREG_ADDR(fxsave, (i - tos) & 7);
 413
 414                         switch (st->exponent & 0x7fff) {
 415                         case 0x7fff:
 416                                 tag = FP_EXP_TAG_SPECIAL;
 417                                 break;
 418                         case 0x0000:
 419                                 if (!st->significand[0] &&
 420                                     !st->significand[1] &&
 421                                     !st->significand[2] &&
 422                                     !st->significand[3])
 423                                         tag = FP_EXP_TAG_ZERO;
 424                                 else
 425                                         tag = FP_EXP_TAG_SPECIAL;
 426                                 break;
 427                         default:
 428                                 if (st->significand[3] & 0x8000)
 429                                         tag = FP_EXP_TAG_VALID;
 430                                 else
 431                                         tag = FP_EXP_TAG_SPECIAL;
 432                                 break;
 433                         }
 434                 } else {
 435                         tag = FP_EXP_TAG_EMPTY;
 436                 }
 437                 ret |= tag << (2 * i);
 438         }
 439         return ret;
 440 }
 441
 442 /*
 443  * FXSR floating point environment conversions.
 444  */
 445
 446 void
 447 convert_from_fxsr(struct user_i387_ia32_struct *env, struct task_struct *tsk)
 448 {
 449         struct i387_fxsave_struct *fxsave = &tsk->thread.fpu.state->fxsave;
 450         struct _fpreg *to = (struct _fpreg *) &env->st_space[0];
 451         struct _fpxreg *from = (struct _fpxreg *) &fxsave->st_space[0];
 452         int i;
 453
 454         env->cwd = fxsave->cwd | 0xffff0000u;
 455         env->swd = fxsave->swd | 0xffff0000u;
 456         env->twd = twd_fxsr_to_i387(fxsave);
 457
 458 #ifdef CONFIG_X86_64
 459         env->fip = fxsave->rip;
 460         env->foo = fxsave->rdp;
 461         /*
 462          * should be actually ds/cs at fpu exception time, but
 463          * that information is not available in 64bit mode.
 464          */
 465         env->fcs = task_pt_regs(tsk)->cs;
 466         if (tsk == current) {
 467                 savesegment(ds, env->fos);
 468         } else {
 469                 env->fos = tsk->thread.ds;
 470         }
 471         env->fos |= 0xffff0000;
 472 #else
 473         env->fip = fxsave->fip;
 474         env->fcs = (u16) fxsave->fcs | ((u32) fxsave->fop << 16);
 475         env->foo = fxsave->foo;
 476         env->fos = fxsave->fos;
 477 #endif
 478
 479         for (i = 0; i < 8; ++i)
 480                 memcpy(&to[i], &from[i], sizeof(to[0]));
 481 }
 482
 483 void convert_to_fxsr(struct task_struct *tsk,
 484                      const struct user_i387_ia32_struct *env)
 485
 486 {
 487         struct i387_fxsave_struct *fxsave = &tsk->thread.fpu.state->fxsave;
 488         struct _fpreg *from = (struct _fpreg *) &env->st_space[0];
 489         struct _fpxreg *to = (struct _fpxreg *) &fxsave->st_space[0];
 490         int i;
 491
 492         fxsave->cwd = env->cwd;
 493         fxsave->swd = env->swd;
 494         fxsave->twd = twd_i387_to_fxsr(env->twd);
 495         fxsave->fop = (u16) ((u32) env->fcs >> 16);
 496 #ifdef CONFIG_X86_64
 497         fxsave->rip = env->fip;
 498         fxsave->rdp = env->foo;
 499         /* cs and ds ignored */
 500 #else
 501         fxsave->fip = env->fip;
 502         fxsave->fcs = (env->fcs & 0xffff);
 503         fxsave->foo = env->foo;
 504         fxsave->fos = env->fos;
 505 #endif
 506
 507         for (i = 0; i < 8; ++i)
 508                 memcpy(&to[i], &from[i], sizeof(from[0]));
 509 }
 510
 511 int fpregs_get(struct task_struct *target, const struct user_regset *regset,
 512                unsigned int pos, unsigned int count,
 513                void *kbuf, void __user *ubuf)
 514 {
 515         struct user_i387_ia32_struct env;
 516         int ret;
 517
 518         ret = init_fpu(target);
 519         if (ret)
 520                 return ret;
 521
 522         if (!static_cpu_has(X86_FEATURE_FPU))
 523                 return fpregs_soft_get(target, regset, pos, count, kbuf, ubuf);
 524
 525         if (!cpu_has_fxsr)
 526                 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
 527                                            &target->thread.fpu.state->fsave, 0,
 528                                            -1);
 529
 530         sanitize_i387_state(target);
 531
 532         if (kbuf && pos == 0 && count == sizeof(env)) {
 533                 convert_from_fxsr(kbuf, target);
 534                 return 0;
 535         }
 536
 537         convert_from_fxsr(&env, target);
 538
 539         return user_regset_copyout(&pos, &count, &kbuf, &ubuf, &env, 0, -1);
 540 }
 541
 542 int fpregs_set(struct task_struct *target, const struct user_regset *regset,
 543                unsigned int pos, unsigned int count,
 544                const void *kbuf, const void __user *ubuf)
 545 {
 546         struct user_i387_ia32_struct env;
 547         int ret;
 548
 549         ret = init_fpu(target);
 550         if (ret)
 551                 return ret;
 552
 553         sanitize_i387_state(target);
 554
 555         if (!static_cpu_has(X86_FEATURE_FPU))
 556                 return fpregs_soft_set(target, regset, pos, count, kbuf, ubuf);
 557
 558         if (!cpu_has_fxsr)
 559                 return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
 560                                           &target->thread.fpu.state->fsave, 0,
 561                                           -1);
 562
 563         if (pos > 0 || count < sizeof(env))
 564                 convert_from_fxsr(&env, target);
 565
 566         ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &env, 0, -1);
 567         if (!ret)
 568                 convert_to_fxsr(target, &env);
 569
 570         /*
 571          * update the header bit in the xsave header, indicating the
 572          * presence of FP.
 573          */
 574         if (cpu_has_xsave)
 575                 target->thread.fpu.state->xsave.xsave_hdr.xstate_bv |= XSTATE_FP;
 576         return ret;
 577 }
 578
 579 /*
 580  * FPU state for core dumps.
 581  * This is only used for a.out dumps now.
 582  * It is declared generically using elf_fpregset_t (which is
 583  * struct user_i387_struct) but is in fact only used for 32-bit
 584  * dumps, so on 64-bit it is really struct user_i387_ia32_struct.
 585  */
 586 int dump_fpu(struct pt_regs *regs, struct user_i387_struct *fpu)
 587 {
 588         struct task_struct *tsk = current;
 589         int fpvalid;
 590
 591         fpvalid = !!used_math();
 592         if (fpvalid)
 593                 fpvalid = !fpregs_get(tsk, NULL,
 594                                       0, sizeof(struct user_i387_ia32_struct),
 595                                       fpu, NULL);
 596
 597         return fpvalid;
 598 }
 599 EXPORT_SYMBOL(dump_fpu);
 600
 601 #endif  /* CONFIG_X86_32 || CONFIG_IA32_EMULATION */
 602
 603 static int __init no_387(char *s)
 604 {
 605         setup_clear_cpu_cap(X86_FEATURE_FPU);
 606         return 1;
 607 }
 608
 609 __setup("no387", no_387);
 610
 611 void fpu_detect(struct cpuinfo_x86 *c)
 612 {
 613         unsigned long cr0;
 614         u16 fsw, fcw;
 615
 616         fsw = fcw = 0xffff;
 617
 618         cr0 = read_cr0();
 619         cr0 &= ~(X86_CR0_TS | X86_CR0_EM);
 620         write_cr0(cr0);
 621
 622         asm volatile("fninit ; fnstsw %0 ; fnstcw %1"
 623                      : "+m" (fsw), "+m" (fcw));
 624
 625         if (fsw == 0 && (fcw & 0x103f) == 0x003f)
 626                 set_cpu_cap(c, X86_FEATURE_FPU);
 627         else
 628                 clear_cpu_cap(c, X86_FEATURE_FPU);
 629
 630         /* The final cr0 value is set in fpu_init() */
 631 }