arch/x86/kernel/irq.c

   1 /*
   2  * Common interrupt code for 32 and 64 bit
   3  */
   4 #include <linux/cpu.h>
   5 #include <linux/interrupt.h>
   6 #include <linux/kernel_stat.h>
   7 #include <linux/of.h>
   8 #include <linux/seq_file.h>
   9 #include <linux/smp.h>
  10 #include <linux/ftrace.h>
  11 #include <linux/delay.h>
  12 #include <linux/export.h>
  13
  14 #include <asm/apic.h>
  15 #include <asm/io_apic.h>
  16 #include <asm/irq.h>
  17 #include <asm/idle.h>
  18 #include <asm/mce.h>
  19 #include <asm/hw_irq.h>
  20 #include <asm/desc.h>
  21
  22 #define CREATE_TRACE_POINTS
  23 #include <asm/trace/irq_vectors.h>
  24
  25 DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
  26 EXPORT_PER_CPU_SYMBOL(irq_stat);
  27
  28 DEFINE_PER_CPU(struct pt_regs *, irq_regs);
  29 EXPORT_PER_CPU_SYMBOL(irq_regs);
  30
  31 atomic_t irq_err_count;
  32
  33 /* Function pointer for generic interrupt vector handling */
  34 void (*x86_platform_ipi_callback)(void) = NULL;
  35
  36 /*
  37  * 'what should we do if we get a hw irq event on an illegal vector'.
  38  * each architecture has to answer this themselves.
  39  */
  40 void ack_bad_irq(unsigned int irq)
  41 {
  42         if (printk_ratelimit())
  43                 pr_err("unexpected IRQ trap at vector %02x\n", irq);
  44
  45         /*
  46          * Currently unexpected vectors happen only on SMP and APIC.
  47          * We _must_ ack these because every local APIC has only N
  48          * irq slots per priority level, and a 'hanging, unacked' IRQ
  49          * holds up an irq slot - in excessive cases (when multiple
  50          * unexpected vectors occur) that might lock up the APIC
  51          * completely.
  52          * But only ack when the APIC is enabled -AK
  53          */
  54         ack_APIC_irq();
  55 }
  56
  57 #define irq_stats(x)            (&per_cpu(irq_stat, x))
  58 /*
  59  * /proc/interrupts printing for arch specific interrupts
  60  */
  61 int arch_show_interrupts(struct seq_file *p, int prec)
  62 {
  63         int j;
  64
  65         seq_printf(p, "%*s: ", prec, "NMI");
  66         for_each_online_cpu(j)
  67                 seq_printf(p, "%10u ", irq_stats(j)->__nmi_count);
  68         seq_puts(p, "  Non-maskable interrupts\n");
  69 #ifdef CONFIG_X86_LOCAL_APIC
  70         seq_printf(p, "%*s: ", prec, "LOC");
  71         for_each_online_cpu(j)
  72                 seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs);
  73         seq_puts(p, "  Local timer interrupts\n");
  74
  75         seq_printf(p, "%*s: ", prec, "SPU");
  76         for_each_online_cpu(j)
  77                 seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count);
  78         seq_puts(p, "  Spurious interrupts\n");
  79         seq_printf(p, "%*s: ", prec, "PMI");
  80         for_each_online_cpu(j)
  81                 seq_printf(p, "%10u ", irq_stats(j)->apic_perf_irqs);
  82         seq_puts(p, "  Performance monitoring interrupts\n");
  83         seq_printf(p, "%*s: ", prec, "IWI");
  84         for_each_online_cpu(j)
  85                 seq_printf(p, "%10u ", irq_stats(j)->apic_irq_work_irqs);
  86         seq_puts(p, "  IRQ work interrupts\n");
  87         seq_printf(p, "%*s: ", prec, "RTR");
  88         for_each_online_cpu(j)
  89                 seq_printf(p, "%10u ", irq_stats(j)->icr_read_retry_count);
  90         seq_puts(p, "  APIC ICR read retries\n");
  91 #endif
  92         if (x86_platform_ipi_callback) {
  93                 seq_printf(p, "%*s: ", prec, "PLT");
  94                 for_each_online_cpu(j)
  95                         seq_printf(p, "%10u ", irq_stats(j)->x86_platform_ipis);
  96                 seq_puts(p, "  Platform interrupts\n");
  97         }
  98 #ifdef CONFIG_SMP
  99         seq_printf(p, "%*s: ", prec, "RES");
 100         for_each_online_cpu(j)
 101                 seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count);
 102         seq_puts(p, "  Rescheduling interrupts\n");
 103         seq_printf(p, "%*s: ", prec, "CAL");
 104         for_each_online_cpu(j)
 105                 seq_printf(p, "%10u ", irq_stats(j)->irq_call_count);
 106         seq_puts(p, "  Function call interrupts\n");
 107         seq_printf(p, "%*s: ", prec, "TLB");
 108         for_each_online_cpu(j)
 109                 seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count);
 110         seq_puts(p, "  TLB shootdowns\n");
 111 #endif
 112 #ifdef CONFIG_X86_THERMAL_VECTOR
 113         seq_printf(p, "%*s: ", prec, "TRM");
 114         for_each_online_cpu(j)
 115                 seq_printf(p, "%10u ", irq_stats(j)->irq_thermal_count);
 116         seq_puts(p, "  Thermal event interrupts\n");
 117 #endif
 118 #ifdef CONFIG_X86_MCE_THRESHOLD
 119         seq_printf(p, "%*s: ", prec, "THR");
 120         for_each_online_cpu(j)
 121                 seq_printf(p, "%10u ", irq_stats(j)->irq_threshold_count);
 122         seq_puts(p, "  Threshold APIC interrupts\n");
 123 #endif
 124 #ifdef CONFIG_X86_MCE_AMD
 125         seq_printf(p, "%*s: ", prec, "DFR");
 126         for_each_online_cpu(j)
 127                 seq_printf(p, "%10u ", irq_stats(j)->irq_deferred_error_count);
 128         seq_puts(p, "  Deferred Error APIC interrupts\n");
 129 #endif
 130 #ifdef CONFIG_X86_MCE
 131         seq_printf(p, "%*s: ", prec, "MCE");
 132         for_each_online_cpu(j)
 133                 seq_printf(p, "%10u ", per_cpu(mce_exception_count, j));
 134         seq_puts(p, "  Machine check exceptions\n");
 135         seq_printf(p, "%*s: ", prec, "MCP");
 136         for_each_online_cpu(j)
 137                 seq_printf(p, "%10u ", per_cpu(mce_poll_count, j));
 138         seq_puts(p, "  Machine check polls\n");
 139 #endif
 140 #if IS_ENABLED(CONFIG_HYPERV) || defined(CONFIG_XEN)
 141         if (test_bit(HYPERVISOR_CALLBACK_VECTOR, used_vectors)) {
 142                 seq_printf(p, "%*s: ", prec, "HYP");
 143                 for_each_online_cpu(j)
 144                         seq_printf(p, "%10u ",
 145                                    irq_stats(j)->irq_hv_callback_count);
 146                 seq_puts(p, "  Hypervisor callback interrupts\n");
 147         }
 148 #endif
 149         seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
 150 #if defined(CONFIG_X86_IO_APIC)
 151         seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count));
 152 #endif
 153 #ifdef CONFIG_HAVE_KVM
 154         seq_printf(p, "%*s: ", prec, "PIN");
 155         for_each_online_cpu(j)
 156                 seq_printf(p, "%10u ", irq_stats(j)->kvm_posted_intr_ipis);
 157         seq_puts(p, "  Posted-interrupt notification event\n");
 158
 159         seq_printf(p, "%*s: ", prec, "PIW");
 160         for_each_online_cpu(j)
 161                 seq_printf(p, "%10u ",
 162                            irq_stats(j)->kvm_posted_intr_wakeup_ipis);
 163         seq_puts(p, "  Posted-interrupt wakeup event\n");
 164 #endif
 165         return 0;
 166 }
 167
 168 /*
 169  * /proc/stat helpers
 170  */
 171 u64 arch_irq_stat_cpu(unsigned int cpu)
 172 {
 173         u64 sum = irq_stats(cpu)->__nmi_count;
 174
 175 #ifdef CONFIG_X86_LOCAL_APIC
 176         sum += irq_stats(cpu)->apic_timer_irqs;
 177         sum += irq_stats(cpu)->irq_spurious_count;
 178         sum += irq_stats(cpu)->apic_perf_irqs;
 179         sum += irq_stats(cpu)->apic_irq_work_irqs;
 180         sum += irq_stats(cpu)->icr_read_retry_count;
 181 #endif
 182         if (x86_platform_ipi_callback)
 183                 sum += irq_stats(cpu)->x86_platform_ipis;
 184 #ifdef CONFIG_SMP
 185         sum += irq_stats(cpu)->irq_resched_count;
 186         sum += irq_stats(cpu)->irq_call_count;
 187 #endif
 188 #ifdef CONFIG_X86_THERMAL_VECTOR
 189         sum += irq_stats(cpu)->irq_thermal_count;
 190 #endif
 191 #ifdef CONFIG_X86_MCE_THRESHOLD
 192         sum += irq_stats(cpu)->irq_threshold_count;
 193 #endif
 194 #ifdef CONFIG_X86_MCE
 195         sum += per_cpu(mce_exception_count, cpu);
 196         sum += per_cpu(mce_poll_count, cpu);
 197 #endif
 198         return sum;
 199 }
 200
 201 u64 arch_irq_stat(void)
 202 {
 203         u64 sum = atomic_read(&irq_err_count);
 204         return sum;
 205 }
 206
 207
 208 /*
 209  * do_IRQ handles all normal device IRQ's (the special
 210  * SMP cross-CPU interrupts have their own specific
 211  * handlers).
 212  */
 213 __visible unsigned int __irq_entry do_IRQ(struct pt_regs *regs)
 214 {
 215         struct pt_regs *old_regs = set_irq_regs(regs);
 216         struct irq_desc * desc;
 217         /* high bit used in ret_from_ code  */
 218         unsigned vector = ~regs->orig_ax;
 219
 220         /*
 221          * NB: Unlike exception entries, IRQ entries do not reliably
 222          * handle context tracking in the low-level entry code.  This is
 223          * because syscall entries execute briefly with IRQs on before
 224          * updating context tracking state, so we can take an IRQ from
 225          * kernel mode with CONTEXT_USER.  The low-level entry code only
 226          * updates the context if we came from user mode, so we won't
 227          * switch to CONTEXT_KERNEL.  We'll fix that once the syscall
 228          * code is cleaned up enough that we can cleanly defer enabling
 229          * IRQs.
 230          */
 231
 232         entering_irq();
 233
 234         /* entering_irq() tells RCU that we're not quiescent.  Check it. */
 235         RCU_LOCKDEP_WARN(!rcu_is_watching(), "IRQ failed to wake up RCU");
 236
 237         desc = __this_cpu_read(vector_irq[vector]);
 238
 239         if (!handle_irq(desc, regs)) {
 240                 ack_APIC_irq();
 241
 242                 if (desc != VECTOR_RETRIGGERED) {
 243                         pr_emerg_ratelimited("%s: %d.%d No irq handler for vector\n",
 244                                              __func__, smp_processor_id(),
 245                                              vector);
 246                 } else {
 247                         __this_cpu_write(vector_irq[vector], VECTOR_UNUSED);
 248                 }
 249         }
 250
 251         exiting_irq();
 252
 253         set_irq_regs(old_regs);
 254         return 1;
 255 }
 256
 257 /*
 258  * Handler for X86_PLATFORM_IPI_VECTOR.
 259  */
 260 void __smp_x86_platform_ipi(void)
 261 {
 262         inc_irq_stat(x86_platform_ipis);
 263
 264         if (x86_platform_ipi_callback)
 265                 x86_platform_ipi_callback();
 266 }
 267
 268 __visible void smp_x86_platform_ipi(struct pt_regs *regs)
 269 {
 270         struct pt_regs *old_regs = set_irq_regs(regs);
 271
 272         entering_ack_irq();
 273         __smp_x86_platform_ipi();
 274         exiting_irq();
 275         set_irq_regs(old_regs);
 276 }
 277
 278 #ifdef CONFIG_HAVE_KVM
 279 static void dummy_handler(void) {}
 280 static void (*kvm_posted_intr_wakeup_handler)(void) = dummy_handler;
 281
 282 void kvm_set_posted_intr_wakeup_handler(void (*handler)(void))
 283 {
 284         if (handler)
 285                 kvm_posted_intr_wakeup_handler = handler;
 286         else
 287                 kvm_posted_intr_wakeup_handler = dummy_handler;
 288 }
 289 EXPORT_SYMBOL_GPL(kvm_set_posted_intr_wakeup_handler);
 290
 291 /*
 292  * Handler for POSTED_INTERRUPT_VECTOR.
 293  */
 294 __visible void smp_kvm_posted_intr_ipi(struct pt_regs *regs)
 295 {
 296         struct pt_regs *old_regs = set_irq_regs(regs);
 297
 298         entering_ack_irq();
 299         inc_irq_stat(kvm_posted_intr_ipis);
 300         exiting_irq();
 301         set_irq_regs(old_regs);
 302 }
 303
 304 /*
 305  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
 306  */
 307 __visible void smp_kvm_posted_intr_wakeup_ipi(struct pt_regs *regs)
 308 {
 309         struct pt_regs *old_regs = set_irq_regs(regs);
 310
 311         entering_ack_irq();
 312         inc_irq_stat(kvm_posted_intr_wakeup_ipis);
 313         kvm_posted_intr_wakeup_handler();
 314         exiting_irq();
 315         set_irq_regs(old_regs);
 316 }
 317 #endif
 318
 319 __visible void smp_trace_x86_platform_ipi(struct pt_regs *regs)
 320 {
 321         struct pt_regs *old_regs = set_irq_regs(regs);
 322
 323         entering_ack_irq();
 324         trace_x86_platform_ipi_entry(X86_PLATFORM_IPI_VECTOR);
 325         __smp_x86_platform_ipi();
 326         trace_x86_platform_ipi_exit(X86_PLATFORM_IPI_VECTOR);
 327         exiting_irq();
 328         set_irq_regs(old_regs);
 329 }
 330
 331 EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq);
 332
 333 #ifdef CONFIG_HOTPLUG_CPU
 334
 335 /* These two declarations are only used in check_irq_vectors_for_cpu_disable()
 336  * below, which is protected by stop_machine().  Putting them on the stack
 337  * results in a stack frame overflow.  Dynamically allocating could result in a
 338  * failure so declare these two cpumasks as global.
 339  */
 340 static struct cpumask affinity_new, online_new;
 341
 342 /*
 343  * This cpu is going to be removed and its vectors migrated to the remaining
 344  * online cpus.  Check to see if there are enough vectors in the remaining cpus.
 345  * This function is protected by stop_machine().
 346  */
 347 int check_irq_vectors_for_cpu_disable(void)
 348 {
 349         unsigned int this_cpu, vector, this_count, count;
 350         struct irq_desc *desc;
 351         struct irq_data *data;
 352         int cpu;
 353
 354         this_cpu = smp_processor_id();
 355         cpumask_copy(&online_new, cpu_online_mask);
 356         cpumask_clear_cpu(this_cpu, &online_new);
 357
 358         this_count = 0;
 359         for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
 360                 desc = __this_cpu_read(vector_irq[vector]);
 361                 if (IS_ERR_OR_NULL(desc))
 362                         continue;
 363                 /*
 364                  * Protect against concurrent action removal, affinity
 365                  * changes etc.
 366                  */
 367                 raw_spin_lock(&desc->lock);
 368                 data = irq_desc_get_irq_data(desc);
 369                 cpumask_copy(&affinity_new,
 370                              irq_data_get_affinity_mask(data));
 371                 cpumask_clear_cpu(this_cpu, &affinity_new);
 372
 373                 /* Do not count inactive or per-cpu irqs. */
 374                 if (!irq_desc_has_action(desc) || irqd_is_per_cpu(data)) {
 375                         raw_spin_unlock(&desc->lock);
 376                         continue;
 377                 }
 378
 379                 raw_spin_unlock(&desc->lock);
 380                 /*
 381                  * A single irq may be mapped to multiple cpu's
 382                  * vector_irq[] (for example IOAPIC cluster mode).  In
 383                  * this case we have two possibilities:
 384                  *
 385                  * 1) the resulting affinity mask is empty; that is
 386                  * this the down'd cpu is the last cpu in the irq's
 387                  * affinity mask, or
 388                  *
 389                  * 2) the resulting affinity mask is no longer a
 390                  * subset of the online cpus but the affinity mask is
 391                  * not zero; that is the down'd cpu is the last online
 392                  * cpu in a user set affinity mask.
 393                  */
 394                 if (cpumask_empty(&affinity_new) ||
 395                     !cpumask_subset(&affinity_new, &online_new))
 396                         this_count++;
 397         }
 398
 399         count = 0;
 400         for_each_online_cpu(cpu) {
 401                 if (cpu == this_cpu)
 402                         continue;
 403                 /*
 404                  * We scan from FIRST_EXTERNAL_VECTOR to first system
 405                  * vector. If the vector is marked in the used vectors
 406                  * bitmap or an irq is assigned to it, we don't count
 407                  * it as available.
 408                  *
 409                  * As this is an inaccurate snapshot anyway, we can do
 410                  * this w/o holding vector_lock.
 411                  */
 412                 for (vector = FIRST_EXTERNAL_VECTOR;
 413                      vector < first_system_vector; vector++) {
 414                         if (!test_bit(vector, used_vectors) &&
 415                             IS_ERR_OR_NULL(per_cpu(vector_irq, cpu)[vector]))
 416                             count++;
 417                 }
 418         }
 419
 420         if (count < this_count) {
 421                 pr_warn("CPU %d disable failed: CPU has %u vectors assigned and there are only %u available.\n",
 422                         this_cpu, this_count, count);
 423                 return -ERANGE;
 424         }
 425         return 0;
 426 }
 427
 428 /* A cpu has been removed from cpu_online_mask.  Reset irq affinities. */
 429 void fixup_irqs(void)
 430 {
 431         unsigned int irq, vector;
 432         static int warned;
 433         struct irq_desc *desc;
 434         struct irq_data *data;
 435         struct irq_chip *chip;
 436         int ret;
 437
 438         for_each_irq_desc(irq, desc) {
 439                 int break_affinity = 0;
 440                 int set_affinity = 1;
 441                 const struct cpumask *affinity;
 442
 443                 if (!desc)
 444                         continue;
 445                 if (irq == 2)
 446                         continue;
 447
 448                 /* interrupt's are disabled at this point */
 449                 raw_spin_lock(&desc->lock);
 450
 451                 data = irq_desc_get_irq_data(desc);
 452                 affinity = irq_data_get_affinity_mask(data);
 453                 if (!irq_has_action(irq) || irqd_is_per_cpu(data) ||
 454                     cpumask_subset(affinity, cpu_online_mask)) {
 455                         raw_spin_unlock(&desc->lock);
 456                         continue;
 457                 }
 458
 459                 /*
 460                  * Complete the irq move. This cpu is going down and for
 461                  * non intr-remapping case, we can't wait till this interrupt
 462                  * arrives at this cpu before completing the irq move.
 463                  */
 464                 irq_force_complete_move(desc);
 465
 466                 if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) {
 467                         break_affinity = 1;
 468                         affinity = cpu_online_mask;
 469                 }
 470
 471                 chip = irq_data_get_irq_chip(data);
 472                 /*
 473                  * The interrupt descriptor might have been cleaned up
 474                  * already, but it is not yet removed from the radix tree
 475                  */
 476                 if (!chip) {
 477                         raw_spin_unlock(&desc->lock);
 478                         continue;
 479                 }
 480
 481                 if (!irqd_can_move_in_process_context(data) && chip->irq_mask)
 482                         chip->irq_mask(data);
 483
 484                 if (chip->irq_set_affinity) {
 485                         ret = chip->irq_set_affinity(data, affinity, true);
 486                         if (ret == -ENOSPC)
 487                                 pr_crit("IRQ %d set affinity failed because there are no available vectors.  The device assigned to this IRQ is unstable.\n", irq);
 488                 } else {
 489                         if (!(warned++))
 490                                 set_affinity = 0;
 491                 }
 492
 493                 /*
 494                  * We unmask if the irq was not marked masked by the
 495                  * core code. That respects the lazy irq disable
 496                  * behaviour.
 497                  */
 498                 if (!irqd_can_move_in_process_context(data) &&
 499                     !irqd_irq_masked(data) && chip->irq_unmask)
 500                         chip->irq_unmask(data);
 501
 502                 raw_spin_unlock(&desc->lock);
 503
 504                 if (break_affinity && set_affinity)
 505                         pr_notice("Broke affinity for irq %i\n", irq);
 506                 else if (!set_affinity)
 507                         pr_notice("Cannot set affinity for irq %i\n", irq);
 508         }
 509
 510         /*
 511          * We can remove mdelay() and then send spuriuous interrupts to
 512          * new cpu targets for all the irqs that were handled previously by
 513          * this cpu. While it works, I have seen spurious interrupt messages
 514          * (nothing wrong but still...).
 515          *
 516          * So for now, retain mdelay(1) and check the IRR and then send those
 517          * interrupts to new targets as this cpu is already offlined...
 518          */
 519         mdelay(1);
 520
 521         /*
 522          * We can walk the vector array of this cpu without holding
 523          * vector_lock because the cpu is already marked !online, so
 524          * nothing else will touch it.
 525          */
 526         for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
 527                 unsigned int irr;
 528
 529                 if (IS_ERR_OR_NULL(__this_cpu_read(vector_irq[vector])))
 530                         continue;
 531
 532                 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
 533                 if (irr  & (1 << (vector % 32))) {
 534                         desc = __this_cpu_read(vector_irq[vector]);
 535
 536                         raw_spin_lock(&desc->lock);
 537                         data = irq_desc_get_irq_data(desc);
 538                         chip = irq_data_get_irq_chip(data);
 539                         if (chip->irq_retrigger) {
 540                                 chip->irq_retrigger(data);
 541                                 __this_cpu_write(vector_irq[vector], VECTOR_RETRIGGERED);
 542                         }
 543                         raw_spin_unlock(&desc->lock);
 544                 }
 545                 if (__this_cpu_read(vector_irq[vector]) != VECTOR_RETRIGGERED)
 546                         __this_cpu_write(vector_irq[vector], VECTOR_UNUSED);
 547         }
 548 }
 549 #endif