2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44 #include <linux/init.h>
45 #include <linux/smp.h>
46 #include <linux/module.h>
47 #include <linux/sched.h>
48 #include <linux/percpu.h>
49 #include <linux/bootmem.h>
50 #include <linux/err.h>
51 #include <linux/nmi.h>
52 #include <linux/tboot.h>
53 #include <linux/stackprotector.h>
54 #include <linux/gfp.h>
55 #include <linux/cpuidle.h>
62 #include <asm/realmode.h>
65 #include <asm/pgtable.h>
66 #include <asm/tlbflush.h>
68 #include <asm/mwait.h>
70 #include <asm/io_apic.h>
72 #include <asm/fpu-internal.h>
73 #include <asm/setup.h>
74 #include <asm/uv/uv.h>
75 #include <linux/mc146818rtc.h>
76 #include <asm/i8259.h>
77 #include <asm/realmode.h>
80 /* Number of siblings per CPU package */
81 int smp_num_siblings = 1;
82 EXPORT_SYMBOL(smp_num_siblings);
84 /* Last level cache ID of each logical CPU */
85 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID;
87 /* representing HT siblings of each logical CPU */
88 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
89 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
91 /* representing HT and core siblings of each logical CPU */
92 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
93 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
95 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
97 /* Per CPU bogomips and other parameters */
98 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
99 EXPORT_PER_CPU_SYMBOL(cpu_info);
101 atomic_t init_deasserted;
103 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
107 spin_lock_irqsave(&rtc_lock, flags);
108 CMOS_WRITE(0xa, 0xf);
109 spin_unlock_irqrestore(&rtc_lock, flags);
112 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) =
115 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) =
120 static inline void smpboot_restore_warm_reset_vector(void)
125 * Install writable page 0 entry to set BIOS data area.
130 * Paranoid: Set warm reset code and vector here back
133 spin_lock_irqsave(&rtc_lock, flags);
135 spin_unlock_irqrestore(&rtc_lock, flags);
137 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
141 * Report back to the Boot Processor during boot time or to the caller processor
144 static void smp_callin(void)
149 * If waken up by an INIT in an 82489DX configuration
150 * we may get here before an INIT-deassert IPI reaches
151 * our local APIC. We have to wait for the IPI or we'll
152 * lock up on an APIC access.
154 * Since CPU0 is not wakened up by INIT, it doesn't wait for the IPI.
156 cpuid = smp_processor_id();
157 if (apic->wait_for_init_deassert && cpuid)
158 while (!atomic_read(&init_deasserted))
162 * (This works even if the APIC is not enabled.)
164 phys_id = read_apic_id();
167 * the boot CPU has finished the init stage and is spinning
168 * on callin_map until we finish. We are free to set up this
169 * CPU, first the APIC. (this is probably redundant on most
175 * Need to setup vector mappings before we enable interrupts.
177 setup_vector_irq(smp_processor_id());
180 * Save our processor parameters. Note: this information
181 * is needed for clock calibration.
183 smp_store_cpu_info(cpuid);
187 * Update loops_per_jiffy in cpu_data. Previous call to
188 * smp_store_cpu_info() stored a value that is close but not as
189 * accurate as the value just calculated.
192 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
193 pr_debug("Stack at about %p\n", &cpuid);
196 * This must be done before setting cpu_online_mask
197 * or calling notify_cpu_starting.
199 set_cpu_sibling_map(raw_smp_processor_id());
202 notify_cpu_starting(cpuid);
205 * Allow the master to continue.
207 cpumask_set_cpu(cpuid, cpu_callin_mask);
210 static int cpu0_logical_apicid;
211 static int enable_start_cpu0;
213 * Activate a secondary processor.
215 static void notrace start_secondary(void *unused)
218 * Don't put *anything* before cpu_init(), SMP booting is too
219 * fragile that we want to limit the things done here to the
220 * most necessary things.
223 x86_cpuinit.early_percpu_clock_init();
227 enable_start_cpu0 = 0;
230 /* switch away from the initial page table */
231 load_cr3(swapper_pg_dir);
235 /* otherwise gcc will move up smp_processor_id before the cpu_init */
238 * Check TSC synchronization with the BP:
240 check_tsc_sync_target();
243 * Enable the espfix hack for this CPU
245 #ifdef CONFIG_X86_ESPFIX64
250 * We need to hold vector_lock so there the set of online cpus
251 * does not change while we are assigning vectors to cpus. Holding
252 * this lock ensures we don't half assign or remove an irq from a cpu.
255 set_cpu_online(smp_processor_id(), true);
256 unlock_vector_lock();
257 cpu_set_state_online(smp_processor_id());
258 x86_platform.nmi_init();
260 /* enable local interrupts */
263 /* to prevent fake stack check failure in clock setup */
264 boot_init_stack_canary();
266 x86_cpuinit.setup_percpu_clockev();
269 cpu_startup_entry(CPUHP_ONLINE);
272 void __init smp_store_boot_cpu_info(void)
274 int id = 0; /* CPU 0 */
275 struct cpuinfo_x86 *c = &cpu_data(id);
282 * The bootstrap kernel entry code has set these up. Save them for
285 void smp_store_cpu_info(int id)
287 struct cpuinfo_x86 *c = &cpu_data(id);
292 * During boot time, CPU0 has this setup already. Save the info when
293 * bringing up AP or offlined CPU0.
295 identify_secondary_cpu(c);
299 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
301 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
303 return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
307 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
309 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
311 return !WARN_ONCE(!topology_same_node(c, o),
312 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
313 "[node: %d != %d]. Ignoring dependency.\n",
314 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
317 #define link_mask(mfunc, c1, c2) \
319 cpumask_set_cpu((c1), mfunc(c2)); \
320 cpumask_set_cpu((c2), mfunc(c1)); \
323 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
325 if (cpu_has_topoext) {
326 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
328 if (c->phys_proc_id == o->phys_proc_id &&
329 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) &&
330 c->compute_unit_id == o->compute_unit_id)
331 return topology_sane(c, o, "smt");
333 } else if (c->phys_proc_id == o->phys_proc_id &&
334 c->cpu_core_id == o->cpu_core_id) {
335 return topology_sane(c, o, "smt");
341 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
343 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
345 if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID &&
346 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2))
347 return topology_sane(c, o, "llc");
353 * Unlike the other levels, we do not enforce keeping a
354 * multicore group inside a NUMA node. If this happens, we will
355 * discard the MC level of the topology later.
357 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
359 if (c->phys_proc_id == o->phys_proc_id)
364 static struct sched_domain_topology_level numa_inside_package_topology[] = {
365 #ifdef CONFIG_SCHED_SMT
366 { cpu_smt_mask, cpu_smt_flags, SD_INIT_NAME(SMT) },
368 #ifdef CONFIG_SCHED_MC
369 { cpu_coregroup_mask, cpu_core_flags, SD_INIT_NAME(MC) },
374 * set_sched_topology() sets the topology internal to a CPU. The
375 * NUMA topologies are layered on top of it to build the full
378 * If NUMA nodes are observed to occur within a CPU package, this
379 * function should be called. It forces the sched domain code to
380 * only use the SMT level for the CPU portion of the topology.
381 * This essentially falls back to relying on NUMA information
382 * from the SRAT table to describe the entire system topology
383 * (except for hyperthreads).
385 static void primarily_use_numa_for_topology(void)
387 set_sched_topology(numa_inside_package_topology);
390 void set_cpu_sibling_map(int cpu)
392 bool has_smt = smp_num_siblings > 1;
393 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
394 struct cpuinfo_x86 *c = &cpu_data(cpu);
395 struct cpuinfo_x86 *o;
398 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
401 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu));
402 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
403 cpumask_set_cpu(cpu, topology_core_cpumask(cpu));
408 for_each_cpu(i, cpu_sibling_setup_mask) {
411 if ((i == cpu) || (has_smt && match_smt(c, o)))
412 link_mask(topology_sibling_cpumask, cpu, i);
414 if ((i == cpu) || (has_mp && match_llc(c, o)))
415 link_mask(cpu_llc_shared_mask, cpu, i);
420 * This needs a separate iteration over the cpus because we rely on all
421 * topology_sibling_cpumask links to be set-up.
423 for_each_cpu(i, cpu_sibling_setup_mask) {
426 if ((i == cpu) || (has_mp && match_die(c, o))) {
427 link_mask(topology_core_cpumask, cpu, i);
430 * Does this new cpu bringup a new core?
433 topology_sibling_cpumask(cpu)) == 1) {
435 * for each core in package, increment
436 * the booted_cores for this new cpu
439 topology_sibling_cpumask(i)) == i)
442 * increment the core count for all
443 * the other cpus in this package
446 cpu_data(i).booted_cores++;
447 } else if (i != cpu && !c->booted_cores)
448 c->booted_cores = cpu_data(i).booted_cores;
450 if (match_die(c, o) && !topology_same_node(c, o))
451 primarily_use_numa_for_topology();
455 /* maps the cpu to the sched domain representing multi-core */
456 const struct cpumask *cpu_coregroup_mask(int cpu)
458 return cpu_llc_shared_mask(cpu);
461 static void impress_friends(void)
464 unsigned long bogosum = 0;
466 * Allow the user to impress friends.
468 pr_debug("Before bogomips\n");
469 for_each_possible_cpu(cpu)
470 if (cpumask_test_cpu(cpu, cpu_callout_mask))
471 bogosum += cpu_data(cpu).loops_per_jiffy;
472 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
475 (bogosum/(5000/HZ))%100);
477 pr_debug("Before bogocount - setting activated=1\n");
480 void __inquire_remote_apic(int apicid)
482 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
483 const char * const names[] = { "ID", "VERSION", "SPIV" };
487 pr_info("Inquiring remote APIC 0x%x...\n", apicid);
489 for (i = 0; i < ARRAY_SIZE(regs); i++) {
490 pr_info("... APIC 0x%x %s: ", apicid, names[i]);
495 status = safe_apic_wait_icr_idle();
497 pr_cont("a previous APIC delivery may have failed\n");
499 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
504 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
505 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
508 case APIC_ICR_RR_VALID:
509 status = apic_read(APIC_RRR);
510 pr_cont("%08x\n", status);
519 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
520 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
521 * won't ... remember to clear down the APIC, etc later.
524 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
526 unsigned long send_status, accept_status = 0;
530 /* Boot on the stack */
531 /* Kick the second */
532 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid);
534 pr_debug("Waiting for send to finish...\n");
535 send_status = safe_apic_wait_icr_idle();
538 * Give the other CPU some time to accept the IPI.
541 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
542 maxlvt = lapic_get_maxlvt();
543 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
544 apic_write(APIC_ESR, 0);
545 accept_status = (apic_read(APIC_ESR) & 0xEF);
547 pr_debug("NMI sent\n");
550 pr_err("APIC never delivered???\n");
552 pr_err("APIC delivery error (%lx)\n", accept_status);
554 return (send_status | accept_status);
558 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
560 unsigned long send_status, accept_status = 0;
561 int maxlvt, num_starts, j;
563 maxlvt = lapic_get_maxlvt();
566 * Be paranoid about clearing APIC errors.
568 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
569 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
570 apic_write(APIC_ESR, 0);
574 pr_debug("Asserting INIT\n");
577 * Turn INIT on target chip
582 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
585 pr_debug("Waiting for send to finish...\n");
586 send_status = safe_apic_wait_icr_idle();
590 pr_debug("Deasserting INIT\n");
594 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
596 pr_debug("Waiting for send to finish...\n");
597 send_status = safe_apic_wait_icr_idle();
600 atomic_set(&init_deasserted, 1);
603 * Should we send STARTUP IPIs ?
605 * Determine this based on the APIC version.
606 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
608 if (APIC_INTEGRATED(apic_version[phys_apicid]))
614 * Paravirt / VMI wants a startup IPI hook here to set up the
615 * target processor state.
617 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary,
621 * Run STARTUP IPI loop.
623 pr_debug("#startup loops: %d\n", num_starts);
625 for (j = 1; j <= num_starts; j++) {
626 pr_debug("Sending STARTUP #%d\n", j);
627 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
628 apic_write(APIC_ESR, 0);
630 pr_debug("After apic_write\n");
637 /* Boot on the stack */
638 /* Kick the second */
639 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
643 * Give the other CPU some time to accept the IPI.
647 pr_debug("Startup point 1\n");
649 pr_debug("Waiting for send to finish...\n");
650 send_status = safe_apic_wait_icr_idle();
653 * Give the other CPU some time to accept the IPI.
656 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
657 apic_write(APIC_ESR, 0);
658 accept_status = (apic_read(APIC_ESR) & 0xEF);
659 if (send_status || accept_status)
662 pr_debug("After Startup\n");
665 pr_err("APIC never delivered???\n");
667 pr_err("APIC delivery error (%lx)\n", accept_status);
669 return (send_status | accept_status);
672 void smp_announce(void)
674 int num_nodes = num_online_nodes();
676 printk(KERN_INFO "x86: Booted up %d node%s, %d CPUs\n",
677 num_nodes, (num_nodes > 1 ? "s" : ""), num_online_cpus());
680 /* reduce the number of lines printed when booting a large cpu count system */
681 static void announce_cpu(int cpu, int apicid)
683 static int current_node = -1;
684 int node = early_cpu_to_node(cpu);
685 static int width, node_width;
688 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
691 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
694 printk(KERN_INFO "x86: Booting SMP configuration:\n");
696 if (system_state == SYSTEM_BOOTING) {
697 if (node != current_node) {
698 if (current_node > (-1))
702 printk(KERN_INFO ".... node %*s#%d, CPUs: ",
703 node_width - num_digits(node), " ", node);
706 /* Add padding for the BSP */
708 pr_cont("%*s", width + 1, " ");
710 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
713 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
717 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
721 cpu = smp_processor_id();
722 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
729 * Wake up AP by INIT, INIT, STARTUP sequence.
731 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
732 * boot-strap code which is not a desired behavior for waking up BSP. To
733 * void the boot-strap code, wake up CPU0 by NMI instead.
735 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
736 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
737 * We'll change this code in the future to wake up hard offlined CPU0 if
738 * real platform and request are available.
741 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
742 int *cpu0_nmi_registered)
750 * Wake up AP by INIT, INIT, STARTUP sequence.
753 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
758 * Wake up BSP by nmi.
760 * Register a NMI handler to help wake up CPU0.
762 boot_error = register_nmi_handler(NMI_LOCAL,
763 wakeup_cpu0_nmi, 0, "wake_cpu0");
766 enable_start_cpu0 = 1;
767 *cpu0_nmi_registered = 1;
768 if (apic->dest_logical == APIC_DEST_LOGICAL)
769 id = cpu0_logical_apicid;
772 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
781 void common_cpu_up(unsigned int cpu, struct task_struct *idle)
783 /* Just in case we booted with a single CPU. */
784 alternatives_enable_smp();
786 per_cpu(current_task, cpu) = idle;
789 /* Stack for startup_32 can be just as for start_secondary onwards */
791 per_cpu(cpu_current_top_of_stack, cpu) =
792 (unsigned long)task_stack_page(idle) + THREAD_SIZE;
794 clear_tsk_thread_flag(idle, TIF_FORK);
795 initial_gs = per_cpu_offset(cpu);
797 per_cpu(kernel_stack, cpu) =
798 (unsigned long)task_stack_page(idle) + THREAD_SIZE;
802 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
803 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
804 * Returns zero if CPU booted OK, else error code from
805 * ->wakeup_secondary_cpu.
807 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle)
809 volatile u32 *trampoline_status =
810 (volatile u32 *) __va(real_mode_header->trampoline_status);
811 /* start_ip had better be page-aligned! */
812 unsigned long start_ip = real_mode_header->trampoline_start;
814 unsigned long boot_error = 0;
815 int cpu0_nmi_registered = 0;
816 unsigned long timeout;
818 idle->thread.sp = (unsigned long) (((struct pt_regs *)
819 (THREAD_SIZE + task_stack_page(idle))) - 1);
821 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
822 initial_code = (unsigned long)start_secondary;
823 stack_start = idle->thread.sp;
825 /* So we see what's up */
826 announce_cpu(cpu, apicid);
829 * This grunge runs the startup process for
830 * the targeted processor.
833 atomic_set(&init_deasserted, 0);
835 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
837 pr_debug("Setting warm reset code and vector.\n");
839 smpboot_setup_warm_reset_vector(start_ip);
841 * Be paranoid about clearing APIC errors.
843 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
844 apic_write(APIC_ESR, 0);
850 * AP might wait on cpu_callout_mask in cpu_init() with
851 * cpu_initialized_mask set if previous attempt to online
852 * it timed-out. Clear cpu_initialized_mask so that after
853 * INIT/SIPI it could start with a clean state.
855 cpumask_clear_cpu(cpu, cpu_initialized_mask);
859 * Wake up a CPU in difference cases:
860 * - Use the method in the APIC driver if it's defined
862 * - Use an INIT boot APIC message for APs or NMI for BSP.
864 if (apic->wakeup_secondary_cpu)
865 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
867 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
868 &cpu0_nmi_registered);
872 * Wait 10s total for a response from AP
875 timeout = jiffies + 10*HZ;
876 while (time_before(jiffies, timeout)) {
877 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) {
879 * Tell AP to proceed with initialization
881 cpumask_set_cpu(cpu, cpu_callout_mask);
892 * Wait till AP completes initial initialization
894 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) {
896 * Allow other tasks to run while we wait for the
897 * AP to come online. This also gives a chance
898 * for the MTRR work(triggered by the AP coming online)
899 * to be completed in the stop machine context.
906 /* mark "stuck" area as not stuck */
907 *trampoline_status = 0;
909 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
911 * Cleanup possible dangling ends...
913 smpboot_restore_warm_reset_vector();
916 * Clean up the nmi handler. Do this after the callin and callout sync
917 * to avoid impact of possible long unregister time.
919 if (cpu0_nmi_registered)
920 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");
925 int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
927 int apicid = apic->cpu_present_to_apicid(cpu);
931 WARN_ON(irqs_disabled());
933 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
935 if (apicid == BAD_APICID ||
936 !physid_isset(apicid, phys_cpu_present_map) ||
937 !apic->apic_id_valid(apicid)) {
938 pr_err("%s: bad cpu %d\n", __func__, cpu);
943 * Already booted CPU?
945 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
946 pr_debug("do_boot_cpu %d Already started\n", cpu);
951 * Save current MTRR state in case it was changed since early boot
952 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
956 /* x86 CPUs take themselves offline, so delayed offline is OK. */
957 err = cpu_check_up_prepare(cpu);
958 if (err && err != -EBUSY)
961 /* the FPU context is blank, nobody can own it */
962 __cpu_disable_lazy_restore(cpu);
964 common_cpu_up(cpu, tidle);
966 err = do_boot_cpu(apicid, cpu, tidle);
968 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
973 * Check TSC synchronization with the AP (keep irqs disabled
976 local_irq_save(flags);
977 check_tsc_sync_source(cpu);
978 local_irq_restore(flags);
980 while (!cpu_online(cpu)) {
982 touch_nmi_watchdog();
989 * arch_disable_smp_support() - disables SMP support for x86 at runtime
991 void arch_disable_smp_support(void)
993 disable_ioapic_support();
997 * Fall back to non SMP mode after errors.
999 * RED-PEN audit/test this more. I bet there is more state messed up here.
1001 static __init void disable_smp(void)
1003 pr_info("SMP disabled\n");
1005 disable_ioapic_support();
1007 init_cpu_present(cpumask_of(0));
1008 init_cpu_possible(cpumask_of(0));
1010 if (smp_found_config)
1011 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1013 physid_set_mask_of_physid(0, &phys_cpu_present_map);
1014 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1015 cpumask_set_cpu(0, topology_core_cpumask(0));
1026 * Various sanity checks.
1028 static int __init smp_sanity_check(unsigned max_cpus)
1032 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1033 if (def_to_bigsmp && nr_cpu_ids > 8) {
1037 pr_warn("More than 8 CPUs detected - skipping them\n"
1038 "Use CONFIG_X86_BIGSMP\n");
1041 for_each_present_cpu(cpu) {
1043 set_cpu_present(cpu, false);
1048 for_each_possible_cpu(cpu) {
1050 set_cpu_possible(cpu, false);
1058 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1059 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1060 hard_smp_processor_id());
1062 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1066 * If we couldn't find an SMP configuration at boot time,
1067 * get out of here now!
1069 if (!smp_found_config && !acpi_lapic) {
1071 pr_notice("SMP motherboard not detected\n");
1072 return SMP_NO_CONFIG;
1076 * Should not be necessary because the MP table should list the boot
1077 * CPU too, but we do it for the sake of robustness anyway.
1079 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1080 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1081 boot_cpu_physical_apicid);
1082 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1087 * If we couldn't find a local APIC, then get out of here now!
1089 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) &&
1091 if (!disable_apic) {
1092 pr_err("BIOS bug, local APIC #%d not detected!...\n",
1093 boot_cpu_physical_apicid);
1094 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n");
1100 * If SMP should be disabled, then really disable it!
1103 pr_info("SMP mode deactivated\n");
1104 return SMP_FORCE_UP;
1110 static void __init smp_cpu_index_default(void)
1113 struct cpuinfo_x86 *c;
1115 for_each_possible_cpu(i) {
1117 /* mark all to hotplug */
1118 c->cpu_index = nr_cpu_ids;
1123 * Prepare for SMP bootup. The MP table or ACPI has been read
1124 * earlier. Just do some sanity checking here and enable APIC mode.
1126 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1130 smp_cpu_index_default();
1133 * Setup boot CPU information
1135 smp_store_boot_cpu_info(); /* Final full version of the data */
1136 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1139 current_thread_info()->cpu = 0; /* needed? */
1140 for_each_possible_cpu(i) {
1141 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1142 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1143 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1145 set_cpu_sibling_map(0);
1147 switch (smp_sanity_check(max_cpus)) {
1150 if (APIC_init_uniprocessor())
1151 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n");
1158 apic_bsp_setup(false);
1164 default_setup_apic_routing();
1166 if (read_apic_id() != boot_cpu_physical_apicid) {
1167 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1168 read_apic_id(), boot_cpu_physical_apicid);
1169 /* Or can we switch back to PIC here? */
1172 cpu0_logical_apicid = apic_bsp_setup(false);
1174 pr_info("CPU%d: ", 0);
1175 print_cpu_info(&cpu_data(0));
1180 set_mtrr_aps_delayed_init();
1183 void arch_enable_nonboot_cpus_begin(void)
1185 set_mtrr_aps_delayed_init();
1188 void arch_enable_nonboot_cpus_end(void)
1194 * Early setup to make printk work.
1196 void __init native_smp_prepare_boot_cpu(void)
1198 int me = smp_processor_id();
1199 switch_to_new_gdt(me);
1200 /* already set me in cpu_online_mask in boot_cpu_init() */
1201 cpumask_set_cpu(me, cpu_callout_mask);
1202 cpu_set_state_online(me);
1205 void __init native_smp_cpus_done(unsigned int max_cpus)
1207 pr_debug("Boot done\n");
1211 setup_ioapic_dest();
1215 static int __initdata setup_possible_cpus = -1;
1216 static int __init _setup_possible_cpus(char *str)
1218 get_option(&str, &setup_possible_cpus);
1221 early_param("possible_cpus", _setup_possible_cpus);
1225 * cpu_possible_mask should be static, it cannot change as cpu's
1226 * are onlined, or offlined. The reason is per-cpu data-structures
1227 * are allocated by some modules at init time, and dont expect to
1228 * do this dynamically on cpu arrival/departure.
1229 * cpu_present_mask on the other hand can change dynamically.
1230 * In case when cpu_hotplug is not compiled, then we resort to current
1231 * behaviour, which is cpu_possible == cpu_present.
1234 * Three ways to find out the number of additional hotplug CPUs:
1235 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1236 * - The user can overwrite it with possible_cpus=NUM
1237 * - Otherwise don't reserve additional CPUs.
1238 * We do this because additional CPUs waste a lot of memory.
1241 __init void prefill_possible_map(void)
1245 /* no processor from mptable or madt */
1246 if (!num_processors)
1249 i = setup_max_cpus ?: 1;
1250 if (setup_possible_cpus == -1) {
1251 possible = num_processors;
1252 #ifdef CONFIG_HOTPLUG_CPU
1254 possible += disabled_cpus;
1260 possible = setup_possible_cpus;
1262 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1264 /* nr_cpu_ids could be reduced via nr_cpus= */
1265 if (possible > nr_cpu_ids) {
1266 pr_warn("%d Processors exceeds NR_CPUS limit of %d\n",
1267 possible, nr_cpu_ids);
1268 possible = nr_cpu_ids;
1271 #ifdef CONFIG_HOTPLUG_CPU
1272 if (!setup_max_cpus)
1275 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1276 possible, setup_max_cpus);
1280 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1281 possible, max_t(int, possible - num_processors, 0));
1283 for (i = 0; i < possible; i++)
1284 set_cpu_possible(i, true);
1285 for (; i < NR_CPUS; i++)
1286 set_cpu_possible(i, false);
1288 nr_cpu_ids = possible;
1291 #ifdef CONFIG_HOTPLUG_CPU
1293 static void remove_siblinginfo(int cpu)
1296 struct cpuinfo_x86 *c = &cpu_data(cpu);
1298 for_each_cpu(sibling, topology_core_cpumask(cpu)) {
1299 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
1301 * last thread sibling in this cpu core going down
1303 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1)
1304 cpu_data(sibling).booted_cores--;
1307 for_each_cpu(sibling, topology_sibling_cpumask(cpu))
1308 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
1309 for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
1310 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
1311 cpumask_clear(cpu_llc_shared_mask(cpu));
1312 cpumask_clear(topology_sibling_cpumask(cpu));
1313 cpumask_clear(topology_core_cpumask(cpu));
1314 c->phys_proc_id = 0;
1316 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1319 static void __ref remove_cpu_from_maps(int cpu)
1321 set_cpu_online(cpu, false);
1322 cpumask_clear_cpu(cpu, cpu_callout_mask);
1323 cpumask_clear_cpu(cpu, cpu_callin_mask);
1324 /* was set by cpu_init() */
1325 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1326 numa_remove_cpu(cpu);
1329 void cpu_disable_common(void)
1331 int cpu = smp_processor_id();
1333 remove_siblinginfo(cpu);
1335 /* It's now safe to remove this processor from the online map */
1337 remove_cpu_from_maps(cpu);
1338 unlock_vector_lock();
1342 int native_cpu_disable(void)
1346 ret = check_irq_vectors_for_cpu_disable();
1351 cpu_disable_common();
1356 int common_cpu_die(unsigned int cpu)
1360 /* We don't do anything here: idle task is faking death itself. */
1362 /* They ack this in play_dead() by setting CPU_DEAD */
1363 if (cpu_wait_death(cpu, 5)) {
1364 if (system_state == SYSTEM_RUNNING)
1365 pr_info("CPU %u is now offline\n", cpu);
1367 pr_err("CPU %u didn't die...\n", cpu);
1374 void native_cpu_die(unsigned int cpu)
1376 common_cpu_die(cpu);
1379 void play_dead_common(void)
1382 reset_lazy_tlbstate();
1383 amd_e400_remove_cpu(raw_smp_processor_id());
1386 (void)cpu_report_death();
1389 * With physical CPU hotplug, we should halt the cpu
1391 local_irq_disable();
1394 static bool wakeup_cpu0(void)
1396 if (smp_processor_id() == 0 && enable_start_cpu0)
1403 * We need to flush the caches before going to sleep, lest we have
1404 * dirty data in our caches when we come back up.
1406 static inline void mwait_play_dead(void)
1408 unsigned int eax, ebx, ecx, edx;
1409 unsigned int highest_cstate = 0;
1410 unsigned int highest_subcstate = 0;
1414 if (!this_cpu_has(X86_FEATURE_MWAIT))
1416 if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1418 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1421 eax = CPUID_MWAIT_LEAF;
1423 native_cpuid(&eax, &ebx, &ecx, &edx);
1426 * eax will be 0 if EDX enumeration is not valid.
1427 * Initialized below to cstate, sub_cstate value when EDX is valid.
1429 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1432 edx >>= MWAIT_SUBSTATE_SIZE;
1433 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1434 if (edx & MWAIT_SUBSTATE_MASK) {
1436 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1439 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1440 (highest_subcstate - 1);
1444 * This should be a memory location in a cache line which is
1445 * unlikely to be touched by other processors. The actual
1446 * content is immaterial as it is not actually modified in any way.
1448 mwait_ptr = ¤t_thread_info()->flags;
1454 * The CLFLUSH is a workaround for erratum AAI65 for
1455 * the Xeon 7400 series. It's not clear it is actually
1456 * needed, but it should be harmless in either case.
1457 * The WBINVD is insufficient due to the spurious-wakeup
1458 * case where we return around the loop.
1463 __monitor(mwait_ptr, 0, 0);
1467 * If NMI wants to wake up CPU0, start CPU0.
1474 static inline void hlt_play_dead(void)
1476 if (__this_cpu_read(cpu_info.x86) >= 4)
1482 * If NMI wants to wake up CPU0, start CPU0.
1489 void native_play_dead(void)
1492 tboot_shutdown(TB_SHUTDOWN_WFS);
1494 mwait_play_dead(); /* Only returns on failure */
1495 if (cpuidle_play_dead())
1499 #else /* ... !CONFIG_HOTPLUG_CPU */
1500 int native_cpu_disable(void)
1505 void native_cpu_die(unsigned int cpu)
1507 /* We said "no" in __cpu_disable */
1511 void native_play_dead(void)