arch/x86/kvm/lapic.c

   1
   2 /*
   3  * Local APIC virtualization
   4  *
   5  * Copyright (C) 2006 Qumranet, Inc.
   6  * Copyright (C) 2007 Novell
   7  * Copyright (C) 2007 Intel
   8  * Copyright 2009 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Dor Laor <dor.laor@qumranet.com>
  12  *   Gregory Haskins <ghaskins@novell.com>
  13  *   Yaozu (Eddie) Dong <eddie.dong@intel.com>
  14  *
  15  * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
  16  *
  17  * This work is licensed under the terms of the GNU GPL, version 2.  See
  18  * the COPYING file in the top-level directory.
  19  */
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/kvm.h>
  23 #include <linux/mm.h>
  24 #include <linux/highmem.h>
  25 #include <linux/smp.h>
  26 #include <linux/hrtimer.h>
  27 #include <linux/io.h>
  28 #include <linux/module.h>
  29 #include <linux/math64.h>
  30 #include <linux/slab.h>
  31 #include <asm/processor.h>
  32 #include <asm/msr.h>
  33 #include <asm/page.h>
  34 #include <asm/current.h>
  35 #include <asm/apicdef.h>
  36 #include <asm/delay.h>
  37 #include <linux/atomic.h>
  38 #include <linux/jump_label.h>
  39 #include "kvm_cache_regs.h"
  40 #include "irq.h"
  41 #include "trace.h"
  42 #include "x86.h"
  43 #include "cpuid.h"
  44 #include "hyperv.h"
  45
  46 #ifndef CONFIG_X86_64
  47 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
  48 #else
  49 #define mod_64(x, y) ((x) % (y))
  50 #endif
  51
  52 #define PRId64 "d"
  53 #define PRIx64 "llx"
  54 #define PRIu64 "u"
  55 #define PRIo64 "o"
  56
  57 #define APIC_BUS_CYCLE_NS 1
  58
  59 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
  60 #define apic_debug(fmt, arg...)
  61
  62 /* 14 is the version for Xeon and Pentium 8.4.8*/
  63 #define APIC_VERSION                    (0x14UL | ((KVM_APIC_LVT_NUM - 1) << 16))
  64 #define LAPIC_MMIO_LENGTH               (1 << 12)
  65 /* followed define is not in apicdef.h */
  66 #define APIC_SHORT_MASK                 0xc0000
  67 #define APIC_DEST_NOSHORT               0x0
  68 #define APIC_DEST_MASK                  0x800
  69 #define MAX_APIC_VECTOR                 256
  70 #define APIC_VECTORS_PER_REG            32
  71
  72 #define APIC_BROADCAST                  0xFF
  73 #define X2APIC_BROADCAST                0xFFFFFFFFul
  74
  75 static inline int apic_test_vector(int vec, void *bitmap)
  76 {
  77         return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  78 }
  79
  80 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
  81 {
  82         struct kvm_lapic *apic = vcpu->arch.apic;
  83
  84         return apic_test_vector(vector, apic->regs + APIC_ISR) ||
  85                 apic_test_vector(vector, apic->regs + APIC_IRR);
  86 }
  87
  88 static inline void apic_clear_vector(int vec, void *bitmap)
  89 {
  90         clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  91 }
  92
  93 static inline int __apic_test_and_set_vector(int vec, void *bitmap)
  94 {
  95         return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  96 }
  97
  98 static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
  99 {
 100         return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 101 }
 102
 103 struct static_key_deferred apic_hw_disabled __read_mostly;
 104 struct static_key_deferred apic_sw_disabled __read_mostly;
 105
 106 static inline int apic_enabled(struct kvm_lapic *apic)
 107 {
 108         return kvm_apic_sw_enabled(apic) &&     kvm_apic_hw_enabled(apic);
 109 }
 110
 111 #define LVT_MASK        \
 112         (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
 113
 114 #define LINT_MASK       \
 115         (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
 116          APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
 117
 118 static inline bool kvm_apic_map_get_logical_dest(struct kvm_apic_map *map,
 119                 u32 dest_id, struct kvm_lapic ***cluster, u16 *mask) {
 120         switch (map->mode) {
 121         case KVM_APIC_MODE_X2APIC: {
 122                 u32 offset = (dest_id >> 16) * 16;
 123                 u32 max_apic_id = map->max_apic_id;
 124
 125                 if (offset <= max_apic_id) {
 126                         u8 cluster_size = min(max_apic_id - offset + 1, 16U);
 127
 128                         *cluster = &map->phys_map[offset];
 129                         *mask = dest_id & (0xffff >> (16 - cluster_size));
 130                 } else {
 131                         *mask = 0;
 132                 }
 133
 134                 return true;
 135                 }
 136         case KVM_APIC_MODE_XAPIC_FLAT:
 137                 *cluster = map->xapic_flat_map;
 138                 *mask = dest_id & 0xff;
 139                 return true;
 140         case KVM_APIC_MODE_XAPIC_CLUSTER:
 141                 *cluster = map->xapic_cluster_map[dest_id >> 4];
 142                 *mask = dest_id & 0xf;
 143                 return true;
 144         default:
 145                 /* Not optimized. */
 146                 return false;
 147         }
 148 }
 149
 150 static void kvm_apic_map_free(struct rcu_head *rcu)
 151 {
 152         struct kvm_apic_map *map = container_of(rcu, struct kvm_apic_map, rcu);
 153
 154         kvfree(map);
 155 }
 156
 157 static void recalculate_apic_map(struct kvm *kvm)
 158 {
 159         struct kvm_apic_map *new, *old = NULL;
 160         struct kvm_vcpu *vcpu;
 161         int i;
 162         u32 max_id = 255;
 163
 164         mutex_lock(&kvm->arch.apic_map_lock);
 165
 166         kvm_for_each_vcpu(i, vcpu, kvm)
 167                 if (kvm_apic_present(vcpu))
 168                         max_id = max(max_id, kvm_apic_id(vcpu->arch.apic));
 169
 170         new = kvm_kvzalloc(sizeof(struct kvm_apic_map) +
 171                            sizeof(struct kvm_lapic *) * ((u64)max_id + 1));
 172
 173         if (!new)
 174                 goto out;
 175
 176         new->max_apic_id = max_id;
 177
 178         kvm_for_each_vcpu(i, vcpu, kvm) {
 179                 struct kvm_lapic *apic = vcpu->arch.apic;
 180                 struct kvm_lapic **cluster;
 181                 u16 mask;
 182                 u32 ldr, aid;
 183
 184                 if (!kvm_apic_present(vcpu))
 185                         continue;
 186
 187                 aid = kvm_apic_id(apic);
 188                 ldr = kvm_lapic_get_reg(apic, APIC_LDR);
 189
 190                 if (aid <= new->max_apic_id)
 191                         new->phys_map[aid] = apic;
 192
 193                 if (apic_x2apic_mode(apic)) {
 194                         new->mode |= KVM_APIC_MODE_X2APIC;
 195                 } else if (ldr) {
 196                         ldr = GET_APIC_LOGICAL_ID(ldr);
 197                         if (kvm_lapic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT)
 198                                 new->mode |= KVM_APIC_MODE_XAPIC_FLAT;
 199                         else
 200                                 new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER;
 201                 }
 202
 203                 if (!kvm_apic_map_get_logical_dest(new, ldr, &cluster, &mask))
 204                         continue;
 205
 206                 if (mask)
 207                         cluster[ffs(mask) - 1] = apic;
 208         }
 209 out:
 210         old = rcu_dereference_protected(kvm->arch.apic_map,
 211                         lockdep_is_held(&kvm->arch.apic_map_lock));
 212         rcu_assign_pointer(kvm->arch.apic_map, new);
 213         mutex_unlock(&kvm->arch.apic_map_lock);
 214
 215         if (old)
 216                 call_rcu(&old->rcu, kvm_apic_map_free);
 217
 218         kvm_make_scan_ioapic_request(kvm);
 219 }
 220
 221 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
 222 {
 223         bool enabled = val & APIC_SPIV_APIC_ENABLED;
 224
 225         kvm_lapic_set_reg(apic, APIC_SPIV, val);
 226
 227         if (enabled != apic->sw_enabled) {
 228                 apic->sw_enabled = enabled;
 229                 if (enabled) {
 230                         static_key_slow_dec_deferred(&apic_sw_disabled);
 231                         recalculate_apic_map(apic->vcpu->kvm);
 232                 } else
 233                         static_key_slow_inc(&apic_sw_disabled.key);
 234         }
 235 }
 236
 237 static inline void kvm_apic_set_xapic_id(struct kvm_lapic *apic, u8 id)
 238 {
 239         kvm_lapic_set_reg(apic, APIC_ID, id << 24);
 240         recalculate_apic_map(apic->vcpu->kvm);
 241 }
 242
 243 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
 244 {
 245         kvm_lapic_set_reg(apic, APIC_LDR, id);
 246         recalculate_apic_map(apic->vcpu->kvm);
 247 }
 248
 249 static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u32 id)
 250 {
 251         u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
 252
 253         kvm_lapic_set_reg(apic, APIC_ID, id);
 254         kvm_lapic_set_reg(apic, APIC_LDR, ldr);
 255         recalculate_apic_map(apic->vcpu->kvm);
 256 }
 257
 258 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
 259 {
 260         return !(kvm_lapic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
 261 }
 262
 263 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
 264 {
 265         return kvm_lapic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
 266 }
 267
 268 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
 269 {
 270         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
 271 }
 272
 273 static inline int apic_lvtt_period(struct kvm_lapic *apic)
 274 {
 275         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
 276 }
 277
 278 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
 279 {
 280         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
 281 }
 282
 283 static inline int apic_lvt_nmi_mode(u32 lvt_val)
 284 {
 285         return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
 286 }
 287
 288 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
 289 {
 290         struct kvm_lapic *apic = vcpu->arch.apic;
 291         struct kvm_cpuid_entry2 *feat;
 292         u32 v = APIC_VERSION;
 293
 294         if (!lapic_in_kernel(vcpu))
 295                 return;
 296
 297         feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
 298         if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
 299                 v |= APIC_LVR_DIRECTED_EOI;
 300         kvm_lapic_set_reg(apic, APIC_LVR, v);
 301 }
 302
 303 static const unsigned int apic_lvt_mask[KVM_APIC_LVT_NUM] = {
 304         LVT_MASK ,      /* part LVTT mask, timer mode mask added at runtime */
 305         LVT_MASK | APIC_MODE_MASK,      /* LVTTHMR */
 306         LVT_MASK | APIC_MODE_MASK,      /* LVTPC */
 307         LINT_MASK, LINT_MASK,   /* LVT0-1 */
 308         LVT_MASK                /* LVTERR */
 309 };
 310
 311 static int find_highest_vector(void *bitmap)
 312 {
 313         int vec;
 314         u32 *reg;
 315
 316         for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
 317              vec >= 0; vec -= APIC_VECTORS_PER_REG) {
 318                 reg = bitmap + REG_POS(vec);
 319                 if (*reg)
 320                         return fls(*reg) - 1 + vec;
 321         }
 322
 323         return -1;
 324 }
 325
 326 static u8 count_vectors(void *bitmap)
 327 {
 328         int vec;
 329         u32 *reg;
 330         u8 count = 0;
 331
 332         for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
 333                 reg = bitmap + REG_POS(vec);
 334                 count += hweight32(*reg);
 335         }
 336
 337         return count;
 338 }
 339
 340 void __kvm_apic_update_irr(u32 *pir, void *regs)
 341 {
 342         u32 i, pir_val;
 343
 344         for (i = 0; i <= 7; i++) {
 345                 pir_val = xchg(&pir[i], 0);
 346                 if (pir_val)
 347                         *((u32 *)(regs + APIC_IRR + i * 0x10)) |= pir_val;
 348         }
 349 }
 350 EXPORT_SYMBOL_GPL(__kvm_apic_update_irr);
 351
 352 void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir)
 353 {
 354         struct kvm_lapic *apic = vcpu->arch.apic;
 355
 356         __kvm_apic_update_irr(pir, apic->regs);
 357
 358         kvm_make_request(KVM_REQ_EVENT, vcpu);
 359 }
 360 EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
 361
 362 static inline int apic_search_irr(struct kvm_lapic *apic)
 363 {
 364         return find_highest_vector(apic->regs + APIC_IRR);
 365 }
 366
 367 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
 368 {
 369         int result;
 370
 371         /*
 372          * Note that irr_pending is just a hint. It will be always
 373          * true with virtual interrupt delivery enabled.
 374          */
 375         if (!apic->irr_pending)
 376                 return -1;
 377
 378         if (apic->vcpu->arch.apicv_active)
 379                 kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
 380         result = apic_search_irr(apic);
 381         ASSERT(result == -1 || result >= 16);
 382
 383         return result;
 384 }
 385
 386 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
 387 {
 388         struct kvm_vcpu *vcpu;
 389
 390         vcpu = apic->vcpu;
 391
 392         if (unlikely(vcpu->arch.apicv_active)) {
 393                 /* try to update RVI */
 394                 apic_clear_vector(vec, apic->regs + APIC_IRR);
 395                 kvm_make_request(KVM_REQ_EVENT, vcpu);
 396         } else {
 397                 apic->irr_pending = false;
 398                 apic_clear_vector(vec, apic->regs + APIC_IRR);
 399                 if (apic_search_irr(apic) != -1)
 400                         apic->irr_pending = true;
 401         }
 402 }
 403
 404 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
 405 {
 406         struct kvm_vcpu *vcpu;
 407
 408         if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
 409                 return;
 410
 411         vcpu = apic->vcpu;
 412
 413         /*
 414          * With APIC virtualization enabled, all caching is disabled
 415          * because the processor can modify ISR under the hood.  Instead
 416          * just set SVI.
 417          */
 418         if (unlikely(vcpu->arch.apicv_active))
 419                 kvm_x86_ops->hwapic_isr_update(vcpu, vec);
 420         else {
 421                 ++apic->isr_count;
 422                 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
 423                 /*
 424                  * ISR (in service register) bit is set when injecting an interrupt.
 425                  * The highest vector is injected. Thus the latest bit set matches
 426                  * the highest bit in ISR.
 427                  */
 428                 apic->highest_isr_cache = vec;
 429         }
 430 }
 431
 432 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
 433 {
 434         int result;
 435
 436         /*
 437          * Note that isr_count is always 1, and highest_isr_cache
 438          * is always -1, with APIC virtualization enabled.
 439          */
 440         if (!apic->isr_count)
 441                 return -1;
 442         if (likely(apic->highest_isr_cache != -1))
 443                 return apic->highest_isr_cache;
 444
 445         result = find_highest_vector(apic->regs + APIC_ISR);
 446         ASSERT(result == -1 || result >= 16);
 447
 448         return result;
 449 }
 450
 451 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
 452 {
 453         struct kvm_vcpu *vcpu;
 454         if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
 455                 return;
 456
 457         vcpu = apic->vcpu;
 458
 459         /*
 460          * We do get here for APIC virtualization enabled if the guest
 461          * uses the Hyper-V APIC enlightenment.  In this case we may need
 462          * to trigger a new interrupt delivery by writing the SVI field;
 463          * on the other hand isr_count and highest_isr_cache are unused
 464          * and must be left alone.
 465          */
 466         if (unlikely(vcpu->arch.apicv_active))
 467                 kvm_x86_ops->hwapic_isr_update(vcpu,
 468                                                apic_find_highest_isr(apic));
 469         else {
 470                 --apic->isr_count;
 471                 BUG_ON(apic->isr_count < 0);
 472                 apic->highest_isr_cache = -1;
 473         }
 474 }
 475
 476 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
 477 {
 478         /* This may race with setting of irr in __apic_accept_irq() and
 479          * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
 480          * will cause vmexit immediately and the value will be recalculated
 481          * on the next vmentry.
 482          */
 483         return apic_find_highest_irr(vcpu->arch.apic);
 484 }
 485
 486 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 487                              int vector, int level, int trig_mode,
 488                              struct dest_map *dest_map);
 489
 490 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
 491                      struct dest_map *dest_map)
 492 {
 493         struct kvm_lapic *apic = vcpu->arch.apic;
 494
 495         return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
 496                         irq->level, irq->trig_mode, dest_map);
 497 }
 498
 499 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
 500 {
 501
 502         return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
 503                                       sizeof(val));
 504 }
 505
 506 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
 507 {
 508
 509         return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
 510                                       sizeof(*val));
 511 }
 512
 513 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
 514 {
 515         return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
 516 }
 517
 518 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
 519 {
 520         u8 val;
 521         if (pv_eoi_get_user(vcpu, &val) < 0)
 522                 apic_debug("Can't read EOI MSR value: 0x%llx\n",
 523                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 524         return val & 0x1;
 525 }
 526
 527 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
 528 {
 529         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
 530                 apic_debug("Can't set EOI MSR value: 0x%llx\n",
 531                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 532                 return;
 533         }
 534         __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 535 }
 536
 537 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
 538 {
 539         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
 540                 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
 541                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 542                 return;
 543         }
 544         __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 545 }
 546
 547 static void apic_update_ppr(struct kvm_lapic *apic)
 548 {
 549         u32 tpr, isrv, ppr, old_ppr;
 550         int isr;
 551
 552         old_ppr = kvm_lapic_get_reg(apic, APIC_PROCPRI);
 553         tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI);
 554         isr = apic_find_highest_isr(apic);
 555         isrv = (isr != -1) ? isr : 0;
 556
 557         if ((tpr & 0xf0) >= (isrv & 0xf0))
 558                 ppr = tpr & 0xff;
 559         else
 560                 ppr = isrv & 0xf0;
 561
 562         apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
 563                    apic, ppr, isr, isrv);
 564
 565         if (old_ppr != ppr) {
 566                 kvm_lapic_set_reg(apic, APIC_PROCPRI, ppr);
 567                 if (ppr < old_ppr)
 568                         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 569         }
 570 }
 571
 572 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
 573 {
 574         kvm_lapic_set_reg(apic, APIC_TASKPRI, tpr);
 575         apic_update_ppr(apic);
 576 }
 577
 578 static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda)
 579 {
 580         if (apic_x2apic_mode(apic))
 581                 return mda == X2APIC_BROADCAST;
 582
 583         return GET_APIC_DEST_FIELD(mda) == APIC_BROADCAST;
 584 }
 585
 586 static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda)
 587 {
 588         if (kvm_apic_broadcast(apic, mda))
 589                 return true;
 590
 591         if (apic_x2apic_mode(apic))
 592                 return mda == kvm_apic_id(apic);
 593
 594         return mda == SET_APIC_DEST_FIELD(kvm_apic_id(apic));
 595 }
 596
 597 static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
 598 {
 599         u32 logical_id;
 600
 601         if (kvm_apic_broadcast(apic, mda))
 602                 return true;
 603
 604         logical_id = kvm_lapic_get_reg(apic, APIC_LDR);
 605
 606         if (apic_x2apic_mode(apic))
 607                 return ((logical_id >> 16) == (mda >> 16))
 608                        && (logical_id & mda & 0xffff) != 0;
 609
 610         logical_id = GET_APIC_LOGICAL_ID(logical_id);
 611         mda = GET_APIC_DEST_FIELD(mda);
 612
 613         switch (kvm_lapic_get_reg(apic, APIC_DFR)) {
 614         case APIC_DFR_FLAT:
 615                 return (logical_id & mda) != 0;
 616         case APIC_DFR_CLUSTER:
 617                 return ((logical_id >> 4) == (mda >> 4))
 618                        && (logical_id & mda & 0xf) != 0;
 619         default:
 620                 apic_debug("Bad DFR vcpu %d: %08x\n",
 621                            apic->vcpu->vcpu_id, kvm_lapic_get_reg(apic, APIC_DFR));
 622                 return false;
 623         }
 624 }
 625
 626 /* The KVM local APIC implementation has two quirks:
 627  *
 628  *  - the xAPIC MDA stores the destination at bits 24-31, while this
 629  *    is not true of struct kvm_lapic_irq's dest_id field.  This is
 630  *    just a quirk in the API and is not problematic.
 631  *
 632  *  - in-kernel IOAPIC messages have to be delivered directly to
 633  *    x2APIC, because the kernel does not support interrupt remapping.
 634  *    In order to support broadcast without interrupt remapping, x2APIC
 635  *    rewrites the destination of non-IPI messages from APIC_BROADCAST
 636  *    to X2APIC_BROADCAST.
 637  *
 638  * The broadcast quirk can be disabled with KVM_CAP_X2APIC_API.  This is
 639  * important when userspace wants to use x2APIC-format MSIs, because
 640  * APIC_BROADCAST (0xff) is a legal route for "cluster 0, CPUs 0-7".
 641  */
 642 static u32 kvm_apic_mda(struct kvm_vcpu *vcpu, unsigned int dest_id,
 643                 struct kvm_lapic *source, struct kvm_lapic *target)
 644 {
 645         bool ipi = source != NULL;
 646         bool x2apic_mda = apic_x2apic_mode(ipi ? source : target);
 647
 648         if (!vcpu->kvm->arch.x2apic_broadcast_quirk_disabled &&
 649             !ipi && dest_id == APIC_BROADCAST && x2apic_mda)
 650                 return X2APIC_BROADCAST;
 651
 652         return x2apic_mda ? dest_id : SET_APIC_DEST_FIELD(dest_id);
 653 }
 654
 655 bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
 656                            int short_hand, unsigned int dest, int dest_mode)
 657 {
 658         struct kvm_lapic *target = vcpu->arch.apic;
 659         u32 mda = kvm_apic_mda(vcpu, dest, source, target);
 660
 661         apic_debug("target %p, source %p, dest 0x%x, "
 662                    "dest_mode 0x%x, short_hand 0x%x\n",
 663                    target, source, dest, dest_mode, short_hand);
 664
 665         ASSERT(target);
 666         switch (short_hand) {
 667         case APIC_DEST_NOSHORT:
 668                 if (dest_mode == APIC_DEST_PHYSICAL)
 669                         return kvm_apic_match_physical_addr(target, mda);
 670                 else
 671                         return kvm_apic_match_logical_addr(target, mda);
 672         case APIC_DEST_SELF:
 673                 return target == source;
 674         case APIC_DEST_ALLINC:
 675                 return true;
 676         case APIC_DEST_ALLBUT:
 677                 return target != source;
 678         default:
 679                 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
 680                            short_hand);
 681                 return false;
 682         }
 683 }
 684 EXPORT_SYMBOL_GPL(kvm_apic_match_dest);
 685
 686 int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
 687                        const unsigned long *bitmap, u32 bitmap_size)
 688 {
 689         u32 mod;
 690         int i, idx = -1;
 691
 692         mod = vector % dest_vcpus;
 693
 694         for (i = 0; i <= mod; i++) {
 695                 idx = find_next_bit(bitmap, bitmap_size, idx + 1);
 696                 BUG_ON(idx == bitmap_size);
 697         }
 698
 699         return idx;
 700 }
 701
 702 static void kvm_apic_disabled_lapic_found(struct kvm *kvm)
 703 {
 704         if (!kvm->arch.disabled_lapic_found) {
 705                 kvm->arch.disabled_lapic_found = true;
 706                 printk(KERN_INFO
 707                        "Disabled LAPIC found during irq injection\n");
 708         }
 709 }
 710
 711 static bool kvm_apic_is_broadcast_dest(struct kvm *kvm, struct kvm_lapic **src,
 712                 struct kvm_lapic_irq *irq, struct kvm_apic_map *map)
 713 {
 714         if (kvm->arch.x2apic_broadcast_quirk_disabled) {
 715                 if ((irq->dest_id == APIC_BROADCAST &&
 716                                 map->mode != KVM_APIC_MODE_X2APIC))
 717                         return true;
 718                 if (irq->dest_id == X2APIC_BROADCAST)
 719                         return true;
 720         } else {
 721                 bool x2apic_ipi = src && *src && apic_x2apic_mode(*src);
 722                 if (irq->dest_id == (x2apic_ipi ?
 723                                      X2APIC_BROADCAST : APIC_BROADCAST))
 724                         return true;
 725         }
 726
 727         return false;
 728 }
 729
 730 /* Return true if the interrupt can be handled by using *bitmap as index mask
 731  * for valid destinations in *dst array.
 732  * Return false if kvm_apic_map_get_dest_lapic did nothing useful.
 733  * Note: we may have zero kvm_lapic destinations when we return true, which
 734  * means that the interrupt should be dropped.  In this case, *bitmap would be
 735  * zero and *dst undefined.
 736  */
 737 static inline bool kvm_apic_map_get_dest_lapic(struct kvm *kvm,
 738                 struct kvm_lapic **src, struct kvm_lapic_irq *irq,
 739                 struct kvm_apic_map *map, struct kvm_lapic ***dst,
 740                 unsigned long *bitmap)
 741 {
 742         int i, lowest;
 743
 744         if (irq->shorthand == APIC_DEST_SELF && src) {
 745                 *dst = src;
 746                 *bitmap = 1;
 747                 return true;
 748         } else if (irq->shorthand)
 749                 return false;
 750
 751         if (!map || kvm_apic_is_broadcast_dest(kvm, src, irq, map))
 752                 return false;
 753
 754         if (irq->dest_mode == APIC_DEST_PHYSICAL) {
 755                 if (irq->dest_id > map->max_apic_id) {
 756                         *bitmap = 0;
 757                 } else {
 758                         *dst = &map->phys_map[irq->dest_id];
 759                         *bitmap = 1;
 760                 }
 761                 return true;
 762         }
 763
 764         *bitmap = 0;
 765         if (!kvm_apic_map_get_logical_dest(map, irq->dest_id, dst,
 766                                 (u16 *)bitmap))
 767                 return false;
 768
 769         if (!kvm_lowest_prio_delivery(irq))
 770                 return true;
 771
 772         if (!kvm_vector_hashing_enabled()) {
 773                 lowest = -1;
 774                 for_each_set_bit(i, bitmap, 16) {
 775                         if (!(*dst)[i])
 776                                 continue;
 777                         if (lowest < 0)
 778                                 lowest = i;
 779                         else if (kvm_apic_compare_prio((*dst)[i]->vcpu,
 780                                                 (*dst)[lowest]->vcpu) < 0)
 781                                 lowest = i;
 782                 }
 783         } else {
 784                 if (!*bitmap)
 785                         return true;
 786
 787                 lowest = kvm_vector_to_index(irq->vector, hweight16(*bitmap),
 788                                 bitmap, 16);
 789
 790                 if (!(*dst)[lowest]) {
 791                         kvm_apic_disabled_lapic_found(kvm);
 792                         *bitmap = 0;
 793                         return true;
 794                 }
 795         }
 796
 797         *bitmap = (lowest >= 0) ? 1 << lowest : 0;
 798
 799         return true;
 800 }
 801
 802 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
 803                 struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map)
 804 {
 805         struct kvm_apic_map *map;
 806         unsigned long bitmap;
 807         struct kvm_lapic **dst = NULL;
 808         int i;
 809         bool ret;
 810
 811         *r = -1;
 812
 813         if (irq->shorthand == APIC_DEST_SELF) {
 814                 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
 815                 return true;
 816         }
 817
 818         rcu_read_lock();
 819         map = rcu_dereference(kvm->arch.apic_map);
 820
 821         ret = kvm_apic_map_get_dest_lapic(kvm, &src, irq, map, &dst, &bitmap);
 822         if (ret)
 823                 for_each_set_bit(i, &bitmap, 16) {
 824                         if (!dst[i])
 825                                 continue;
 826                         if (*r < 0)
 827                                 *r = 0;
 828                         *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
 829                 }
 830
 831         rcu_read_unlock();
 832         return ret;
 833 }
 834
 835 /*
 836  * This routine tries to handler interrupts in posted mode, here is how
 837  * it deals with different cases:
 838  * - For single-destination interrupts, handle it in posted mode
 839  * - Else if vector hashing is enabled and it is a lowest-priority
 840  *   interrupt, handle it in posted mode and use the following mechanism
 841  *   to find the destinaiton vCPU.
 842  *      1. For lowest-priority interrupts, store all the possible
 843  *         destination vCPUs in an array.
 844  *      2. Use "guest vector % max number of destination vCPUs" to find
 845  *         the right destination vCPU in the array for the lowest-priority
 846  *         interrupt.
 847  * - Otherwise, use remapped mode to inject the interrupt.
 848  */
 849 bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq,
 850                         struct kvm_vcpu **dest_vcpu)
 851 {
 852         struct kvm_apic_map *map;
 853         unsigned long bitmap;
 854         struct kvm_lapic **dst = NULL;
 855         bool ret = false;
 856
 857         if (irq->shorthand)
 858                 return false;
 859
 860         rcu_read_lock();
 861         map = rcu_dereference(kvm->arch.apic_map);
 862
 863         if (kvm_apic_map_get_dest_lapic(kvm, NULL, irq, map, &dst, &bitmap) &&
 864                         hweight16(bitmap) == 1) {
 865                 unsigned long i = find_first_bit(&bitmap, 16);
 866
 867                 if (dst[i]) {
 868                         *dest_vcpu = dst[i]->vcpu;
 869                         ret = true;
 870                 }
 871         }
 872
 873         rcu_read_unlock();
 874         return ret;
 875 }
 876
 877 /*
 878  * Add a pending IRQ into lapic.
 879  * Return 1 if successfully added and 0 if discarded.
 880  */
 881 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 882                              int vector, int level, int trig_mode,
 883                              struct dest_map *dest_map)
 884 {
 885         int result = 0;
 886         struct kvm_vcpu *vcpu = apic->vcpu;
 887
 888         trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
 889                                   trig_mode, vector);
 890         switch (delivery_mode) {
 891         case APIC_DM_LOWEST:
 892                 vcpu->arch.apic_arb_prio++;
 893         case APIC_DM_FIXED:
 894                 if (unlikely(trig_mode && !level))
 895                         break;
 896
 897                 /* FIXME add logic for vcpu on reset */
 898                 if (unlikely(!apic_enabled(apic)))
 899                         break;
 900
 901                 result = 1;
 902
 903                 if (dest_map) {
 904                         __set_bit(vcpu->vcpu_id, dest_map->map);
 905                         dest_map->vectors[vcpu->vcpu_id] = vector;
 906                 }
 907
 908                 if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) {
 909                         if (trig_mode)
 910                                 kvm_lapic_set_vector(vector, apic->regs + APIC_TMR);
 911                         else
 912                                 apic_clear_vector(vector, apic->regs + APIC_TMR);
 913                 }
 914
 915                 if (vcpu->arch.apicv_active)
 916                         kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
 917                 else {
 918                         kvm_lapic_set_irr(vector, apic);
 919
 920                         kvm_make_request(KVM_REQ_EVENT, vcpu);
 921                         kvm_vcpu_kick(vcpu);
 922                 }
 923                 break;
 924
 925         case APIC_DM_REMRD:
 926                 result = 1;
 927                 vcpu->arch.pv.pv_unhalted = 1;
 928                 kvm_make_request(KVM_REQ_EVENT, vcpu);
 929                 kvm_vcpu_kick(vcpu);
 930                 break;
 931
 932         case APIC_DM_SMI:
 933                 result = 1;
 934                 kvm_make_request(KVM_REQ_SMI, vcpu);
 935                 kvm_vcpu_kick(vcpu);
 936                 break;
 937
 938         case APIC_DM_NMI:
 939                 result = 1;
 940                 kvm_inject_nmi(vcpu);
 941                 kvm_vcpu_kick(vcpu);
 942                 break;
 943
 944         case APIC_DM_INIT:
 945                 if (!trig_mode || level) {
 946                         result = 1;
 947                         /* assumes that there are only KVM_APIC_INIT/SIPI */
 948                         apic->pending_events = (1UL << KVM_APIC_INIT);
 949                         /* make sure pending_events is visible before sending
 950                          * the request */
 951                         smp_wmb();
 952                         kvm_make_request(KVM_REQ_EVENT, vcpu);
 953                         kvm_vcpu_kick(vcpu);
 954                 } else {
 955                         apic_debug("Ignoring de-assert INIT to vcpu %d\n",
 956                                    vcpu->vcpu_id);
 957                 }
 958                 break;
 959
 960         case APIC_DM_STARTUP:
 961                 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
 962                            vcpu->vcpu_id, vector);
 963                 result = 1;
 964                 apic->sipi_vector = vector;
 965                 /* make sure sipi_vector is visible for the receiver */
 966                 smp_wmb();
 967                 set_bit(KVM_APIC_SIPI, &apic->pending_events);
 968                 kvm_make_request(KVM_REQ_EVENT, vcpu);
 969                 kvm_vcpu_kick(vcpu);
 970                 break;
 971
 972         case APIC_DM_EXTINT:
 973                 /*
 974                  * Should only be called by kvm_apic_local_deliver() with LVT0,
 975                  * before NMI watchdog was enabled. Already handled by
 976                  * kvm_apic_accept_pic_intr().
 977                  */
 978                 break;
 979
 980         default:
 981                 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
 982                        delivery_mode);
 983                 break;
 984         }
 985         return result;
 986 }
 987
 988 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
 989 {
 990         return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
 991 }
 992
 993 static bool kvm_ioapic_handles_vector(struct kvm_lapic *apic, int vector)
 994 {
 995         return test_bit(vector, apic->vcpu->arch.ioapic_handled_vectors);
 996 }
 997
 998 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
 999 {
1000         int trigger_mode;
1001
1002         /* Eoi the ioapic only if the ioapic doesn't own the vector. */
1003         if (!kvm_ioapic_handles_vector(apic, vector))
1004                 return;
1005
1006         /* Request a KVM exit to inform the userspace IOAPIC. */
1007         if (irqchip_split(apic->vcpu->kvm)) {
1008                 apic->vcpu->arch.pending_ioapic_eoi = vector;
1009                 kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT, apic->vcpu);
1010                 return;
1011         }
1012
1013         if (apic_test_vector(vector, apic->regs + APIC_TMR))
1014                 trigger_mode = IOAPIC_LEVEL_TRIG;
1015         else
1016                 trigger_mode = IOAPIC_EDGE_TRIG;
1017
1018         kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
1019 }
1020
1021 static int apic_set_eoi(struct kvm_lapic *apic)
1022 {
1023         int vector = apic_find_highest_isr(apic);
1024
1025         trace_kvm_eoi(apic, vector);
1026
1027         /*
1028          * Not every write EOI will has corresponding ISR,
1029          * one example is when Kernel check timer on setup_IO_APIC
1030          */
1031         if (vector == -1)
1032                 return vector;
1033
1034         apic_clear_isr(vector, apic);
1035         apic_update_ppr(apic);
1036
1037         if (test_bit(vector, vcpu_to_synic(apic->vcpu)->vec_bitmap))
1038                 kvm_hv_synic_send_eoi(apic->vcpu, vector);
1039
1040         kvm_ioapic_send_eoi(apic, vector);
1041         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1042         return vector;
1043 }
1044
1045 /*
1046  * this interface assumes a trap-like exit, which has already finished
1047  * desired side effect including vISR and vPPR update.
1048  */
1049 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
1050 {
1051         struct kvm_lapic *apic = vcpu->arch.apic;
1052
1053         trace_kvm_eoi(apic, vector);
1054
1055         kvm_ioapic_send_eoi(apic, vector);
1056         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1057 }
1058 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
1059
1060 static void apic_send_ipi(struct kvm_lapic *apic)
1061 {
1062         u32 icr_low = kvm_lapic_get_reg(apic, APIC_ICR);
1063         u32 icr_high = kvm_lapic_get_reg(apic, APIC_ICR2);
1064         struct kvm_lapic_irq irq;
1065
1066         irq.vector = icr_low & APIC_VECTOR_MASK;
1067         irq.delivery_mode = icr_low & APIC_MODE_MASK;
1068         irq.dest_mode = icr_low & APIC_DEST_MASK;
1069         irq.level = (icr_low & APIC_INT_ASSERT) != 0;
1070         irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
1071         irq.shorthand = icr_low & APIC_SHORT_MASK;
1072         irq.msi_redir_hint = false;
1073         if (apic_x2apic_mode(apic))
1074                 irq.dest_id = icr_high;
1075         else
1076                 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
1077
1078         trace_kvm_apic_ipi(icr_low, irq.dest_id);
1079
1080         apic_debug("icr_high 0x%x, icr_low 0x%x, "
1081                    "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
1082                    "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x, "
1083                    "msi_redir_hint 0x%x\n",
1084                    icr_high, icr_low, irq.shorthand, irq.dest_id,
1085                    irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
1086                    irq.vector, irq.msi_redir_hint);
1087
1088         kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
1089 }
1090
1091 static u32 apic_get_tmcct(struct kvm_lapic *apic)
1092 {
1093         ktime_t remaining;
1094         s64 ns;
1095         u32 tmcct;
1096
1097         ASSERT(apic != NULL);
1098
1099         /* if initial count is 0, current count should also be 0 */
1100         if (kvm_lapic_get_reg(apic, APIC_TMICT) == 0 ||
1101                 apic->lapic_timer.period == 0)
1102                 return 0;
1103
1104         remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
1105         if (ktime_to_ns(remaining) < 0)
1106                 remaining = ktime_set(0, 0);
1107
1108         ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
1109         tmcct = div64_u64(ns,
1110                          (APIC_BUS_CYCLE_NS * apic->divide_count));
1111
1112         return tmcct;
1113 }
1114
1115 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
1116 {
1117         struct kvm_vcpu *vcpu = apic->vcpu;
1118         struct kvm_run *run = vcpu->run;
1119
1120         kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
1121         run->tpr_access.rip = kvm_rip_read(vcpu);
1122         run->tpr_access.is_write = write;
1123 }
1124
1125 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
1126 {
1127         if (apic->vcpu->arch.tpr_access_reporting)
1128                 __report_tpr_access(apic, write);
1129 }
1130
1131 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
1132 {
1133         u32 val = 0;
1134
1135         if (offset >= LAPIC_MMIO_LENGTH)
1136                 return 0;
1137
1138         switch (offset) {
1139         case APIC_ARBPRI:
1140                 apic_debug("Access APIC ARBPRI register which is for P6\n");
1141                 break;
1142
1143         case APIC_TMCCT:        /* Timer CCR */
1144                 if (apic_lvtt_tscdeadline(apic))
1145                         return 0;
1146
1147                 val = apic_get_tmcct(apic);
1148                 break;
1149         case APIC_PROCPRI:
1150                 apic_update_ppr(apic);
1151                 val = kvm_lapic_get_reg(apic, offset);
1152                 break;
1153         case APIC_TASKPRI:
1154                 report_tpr_access(apic, false);
1155                 /* fall thru */
1156         default:
1157                 val = kvm_lapic_get_reg(apic, offset);
1158                 break;
1159         }
1160
1161         return val;
1162 }
1163
1164 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
1165 {
1166         return container_of(dev, struct kvm_lapic, dev);
1167 }
1168
1169 int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
1170                 void *data)
1171 {
1172         unsigned char alignment = offset & 0xf;
1173         u32 result;
1174         /* this bitmask has a bit cleared for each reserved register */
1175         static const u64 rmask = 0x43ff01ffffffe70cULL;
1176
1177         if ((alignment + len) > 4) {
1178                 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1179                            offset, len);
1180                 return 1;
1181         }
1182
1183         if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
1184                 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1185                            offset);
1186                 return 1;
1187         }
1188
1189         result = __apic_read(apic, offset & ~0xf);
1190
1191         trace_kvm_apic_read(offset, result);
1192
1193         switch (len) {
1194         case 1:
1195         case 2:
1196         case 4:
1197                 memcpy(data, (char *)&result + alignment, len);
1198                 break;
1199         default:
1200                 printk(KERN_ERR "Local APIC read with len = %x, "
1201                        "should be 1,2, or 4 instead\n", len);
1202                 break;
1203         }
1204         return 0;
1205 }
1206 EXPORT_SYMBOL_GPL(kvm_lapic_reg_read);
1207
1208 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1209 {
1210         return kvm_apic_hw_enabled(apic) &&
1211             addr >= apic->base_address &&
1212             addr < apic->base_address + LAPIC_MMIO_LENGTH;
1213 }
1214
1215 static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1216                            gpa_t address, int len, void *data)
1217 {
1218         struct kvm_lapic *apic = to_lapic(this);
1219         u32 offset = address - apic->base_address;
1220
1221         if (!apic_mmio_in_range(apic, address))
1222                 return -EOPNOTSUPP;
1223
1224         kvm_lapic_reg_read(apic, offset, len, data);
1225
1226         return 0;
1227 }
1228
1229 static void update_divide_count(struct kvm_lapic *apic)
1230 {
1231         u32 tmp1, tmp2, tdcr;
1232
1233         tdcr = kvm_lapic_get_reg(apic, APIC_TDCR);
1234         tmp1 = tdcr & 0xf;
1235         tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
1236         apic->divide_count = 0x1 << (tmp2 & 0x7);
1237
1238         apic_debug("timer divide count is 0x%x\n",
1239                                    apic->divide_count);
1240 }
1241
1242 static void apic_update_lvtt(struct kvm_lapic *apic)
1243 {
1244         u32 timer_mode = kvm_lapic_get_reg(apic, APIC_LVTT) &
1245                         apic->lapic_timer.timer_mode_mask;
1246
1247         if (apic->lapic_timer.timer_mode != timer_mode) {
1248                 apic->lapic_timer.timer_mode = timer_mode;
1249                 hrtimer_cancel(&apic->lapic_timer.timer);
1250         }
1251 }
1252
1253 static void apic_timer_expired(struct kvm_lapic *apic)
1254 {
1255         struct kvm_vcpu *vcpu = apic->vcpu;
1256         struct swait_queue_head *q = &vcpu->wq;
1257         struct kvm_timer *ktimer = &apic->lapic_timer;
1258
1259         if (atomic_read(&apic->lapic_timer.pending))
1260                 return;
1261
1262         atomic_inc(&apic->lapic_timer.pending);
1263         kvm_set_pending_timer(vcpu);
1264
1265         if (swait_active(q))
1266                 swake_up(q);
1267
1268         if (apic_lvtt_tscdeadline(apic))
1269                 ktimer->expired_tscdeadline = ktimer->tscdeadline;
1270 }
1271
1272 /*
1273  * On APICv, this test will cause a busy wait
1274  * during a higher-priority task.
1275  */
1276
1277 static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu)
1278 {
1279         struct kvm_lapic *apic = vcpu->arch.apic;
1280         u32 reg = kvm_lapic_get_reg(apic, APIC_LVTT);
1281
1282         if (kvm_apic_hw_enabled(apic)) {
1283                 int vec = reg & APIC_VECTOR_MASK;
1284                 void *bitmap = apic->regs + APIC_ISR;
1285
1286                 if (vcpu->arch.apicv_active)
1287                         bitmap = apic->regs + APIC_IRR;
1288
1289                 if (apic_test_vector(vec, bitmap))
1290                         return true;
1291         }
1292         return false;
1293 }
1294
1295 void wait_lapic_expire(struct kvm_vcpu *vcpu)
1296 {
1297         struct kvm_lapic *apic = vcpu->arch.apic;
1298         u64 guest_tsc, tsc_deadline;
1299
1300         if (!lapic_in_kernel(vcpu))
1301                 return;
1302
1303         if (apic->lapic_timer.expired_tscdeadline == 0)
1304                 return;
1305
1306         if (!lapic_timer_int_injected(vcpu))
1307                 return;
1308
1309         tsc_deadline = apic->lapic_timer.expired_tscdeadline;
1310         apic->lapic_timer.expired_tscdeadline = 0;
1311         guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1312         trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline);
1313
1314         /* __delay is delay_tsc whenever the hardware has TSC, thus always.  */
1315         if (guest_tsc < tsc_deadline)
1316                 __delay(tsc_deadline - guest_tsc);
1317 }
1318
1319 static void start_sw_tscdeadline(struct kvm_lapic *apic)
1320 {
1321         u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1322         u64 ns = 0;
1323         ktime_t expire;
1324         struct kvm_vcpu *vcpu = apic->vcpu;
1325         unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1326         unsigned long flags;
1327         ktime_t now;
1328
1329         if (unlikely(!tscdeadline || !this_tsc_khz))
1330                 return;
1331
1332         local_irq_save(flags);
1333
1334         now = apic->lapic_timer.timer.base->get_time();
1335         guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1336         if (likely(tscdeadline > guest_tsc)) {
1337                 ns = (tscdeadline - guest_tsc) * 1000000ULL;
1338                 do_div(ns, this_tsc_khz);
1339                 expire = ktime_add_ns(now, ns);
1340                 expire = ktime_sub_ns(expire, lapic_timer_advance_ns);
1341                 hrtimer_start(&apic->lapic_timer.timer,
1342                                 expire, HRTIMER_MODE_ABS_PINNED);
1343         } else
1344                 apic_timer_expired(apic);
1345
1346         local_irq_restore(flags);
1347 }
1348
1349 bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu)
1350 {
1351         return vcpu->arch.apic->lapic_timer.hv_timer_in_use;
1352 }
1353 EXPORT_SYMBOL_GPL(kvm_lapic_hv_timer_in_use);
1354
1355 static void cancel_hv_tscdeadline(struct kvm_lapic *apic)
1356 {
1357         kvm_x86_ops->cancel_hv_timer(apic->vcpu);
1358         apic->lapic_timer.hv_timer_in_use = false;
1359 }
1360
1361 void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu)
1362 {
1363         struct kvm_lapic *apic = vcpu->arch.apic;
1364
1365         WARN_ON(!apic->lapic_timer.hv_timer_in_use);
1366         WARN_ON(swait_active(&vcpu->wq));
1367         cancel_hv_tscdeadline(apic);
1368         apic_timer_expired(apic);
1369 }
1370 EXPORT_SYMBOL_GPL(kvm_lapic_expired_hv_timer);
1371
1372 static bool start_hv_tscdeadline(struct kvm_lapic *apic)
1373 {
1374         u64 tscdeadline = apic->lapic_timer.tscdeadline;
1375
1376         if (atomic_read(&apic->lapic_timer.pending) ||
1377                 kvm_x86_ops->set_hv_timer(apic->vcpu, tscdeadline)) {
1378                 if (apic->lapic_timer.hv_timer_in_use)
1379                         cancel_hv_tscdeadline(apic);
1380         } else {
1381                 apic->lapic_timer.hv_timer_in_use = true;
1382                 hrtimer_cancel(&apic->lapic_timer.timer);
1383
1384                 /* In case the sw timer triggered in the window */
1385                 if (atomic_read(&apic->lapic_timer.pending))
1386                         cancel_hv_tscdeadline(apic);
1387         }
1388         trace_kvm_hv_timer_state(apic->vcpu->vcpu_id,
1389                         apic->lapic_timer.hv_timer_in_use);
1390         return apic->lapic_timer.hv_timer_in_use;
1391 }
1392
1393 void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu)
1394 {
1395         struct kvm_lapic *apic = vcpu->arch.apic;
1396
1397         WARN_ON(apic->lapic_timer.hv_timer_in_use);
1398
1399         if (apic_lvtt_tscdeadline(apic))
1400                 start_hv_tscdeadline(apic);
1401 }
1402 EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_hv_timer);
1403
1404 void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu)
1405 {
1406         struct kvm_lapic *apic = vcpu->arch.apic;
1407
1408         /* Possibly the TSC deadline timer is not enabled yet */
1409         if (!apic->lapic_timer.hv_timer_in_use)
1410                 return;
1411
1412         cancel_hv_tscdeadline(apic);
1413
1414         if (atomic_read(&apic->lapic_timer.pending))
1415                 return;
1416
1417         start_sw_tscdeadline(apic);
1418 }
1419 EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_sw_timer);
1420
1421 static void start_apic_timer(struct kvm_lapic *apic)
1422 {
1423         ktime_t now;
1424
1425         atomic_set(&apic->lapic_timer.pending, 0);
1426
1427         if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
1428                 /* lapic timer in oneshot or periodic mode */
1429                 now = apic->lapic_timer.timer.base->get_time();
1430                 apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT)
1431                             * APIC_BUS_CYCLE_NS * apic->divide_count;
1432
1433                 if (!apic->lapic_timer.period)
1434                         return;
1435                 /*
1436                  * Do not allow the guest to program periodic timers with small
1437                  * interval, since the hrtimers are not throttled by the host
1438                  * scheduler.
1439                  */
1440                 if (apic_lvtt_period(apic)) {
1441                         s64 min_period = min_timer_period_us * 1000LL;
1442
1443                         if (apic->lapic_timer.period < min_period) {
1444                                 pr_info_ratelimited(
1445                                     "kvm: vcpu %i: requested %lld ns "
1446                                     "lapic timer period limited to %lld ns\n",
1447                                     apic->vcpu->vcpu_id,
1448                                     apic->lapic_timer.period, min_period);
1449                                 apic->lapic_timer.period = min_period;
1450                         }
1451                 }
1452
1453                 hrtimer_start(&apic->lapic_timer.timer,
1454                               ktime_add_ns(now, apic->lapic_timer.period),
1455                               HRTIMER_MODE_ABS_PINNED);
1456
1457                 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
1458                            PRIx64 ", "
1459                            "timer initial count 0x%x, period %lldns, "
1460                            "expire @ 0x%016" PRIx64 ".\n", __func__,
1461                            APIC_BUS_CYCLE_NS, ktime_to_ns(now),
1462                            kvm_lapic_get_reg(apic, APIC_TMICT),
1463                            apic->lapic_timer.period,
1464                            ktime_to_ns(ktime_add_ns(now,
1465                                         apic->lapic_timer.period)));
1466         } else if (apic_lvtt_tscdeadline(apic)) {
1467                 if (!(kvm_x86_ops->set_hv_timer && start_hv_tscdeadline(apic)))
1468                         start_sw_tscdeadline(apic);
1469         }
1470 }
1471
1472 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1473 {
1474         bool lvt0_in_nmi_mode = apic_lvt_nmi_mode(lvt0_val);
1475
1476         if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) {
1477                 apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode;
1478                 if (lvt0_in_nmi_mode) {
1479                         apic_debug("Receive NMI setting on APIC_LVT0 "
1480                                    "for cpu %d\n", apic->vcpu->vcpu_id);
1481                         atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1482                 } else
1483                         atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1484         }
1485 }
1486
1487 int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
1488 {
1489         int ret = 0;
1490
1491         trace_kvm_apic_write(reg, val);
1492
1493         switch (reg) {
1494         case APIC_ID:           /* Local APIC ID */
1495                 if (!apic_x2apic_mode(apic))
1496                         kvm_apic_set_xapic_id(apic, val >> 24);
1497                 else
1498                         ret = 1;
1499                 break;
1500
1501         case APIC_TASKPRI:
1502                 report_tpr_access(apic, true);
1503                 apic_set_tpr(apic, val & 0xff);
1504                 break;
1505
1506         case APIC_EOI:
1507                 apic_set_eoi(apic);
1508                 break;
1509
1510         case APIC_LDR:
1511                 if (!apic_x2apic_mode(apic))
1512                         kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
1513                 else
1514                         ret = 1;
1515                 break;
1516
1517         case APIC_DFR:
1518                 if (!apic_x2apic_mode(apic)) {
1519                         kvm_lapic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1520                         recalculate_apic_map(apic->vcpu->kvm);
1521                 } else
1522                         ret = 1;
1523                 break;
1524
1525         case APIC_SPIV: {
1526                 u32 mask = 0x3ff;
1527                 if (kvm_lapic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
1528                         mask |= APIC_SPIV_DIRECTED_EOI;
1529                 apic_set_spiv(apic, val & mask);
1530                 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1531                         int i;
1532                         u32 lvt_val;
1533
1534                         for (i = 0; i < KVM_APIC_LVT_NUM; i++) {
1535                                 lvt_val = kvm_lapic_get_reg(apic,
1536                                                        APIC_LVTT + 0x10 * i);
1537                                 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i,
1538                                              lvt_val | APIC_LVT_MASKED);
1539                         }
1540                         apic_update_lvtt(apic);
1541                         atomic_set(&apic->lapic_timer.pending, 0);
1542
1543                 }
1544                 break;
1545         }
1546         case APIC_ICR:
1547                 /* No delay here, so we always clear the pending bit */
1548                 kvm_lapic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1549                 apic_send_ipi(apic);
1550                 break;
1551
1552         case APIC_ICR2:
1553                 if (!apic_x2apic_mode(apic))
1554                         val &= 0xff000000;
1555                 kvm_lapic_set_reg(apic, APIC_ICR2, val);
1556                 break;
1557
1558         case APIC_LVT0:
1559                 apic_manage_nmi_watchdog(apic, val);
1560         case APIC_LVTTHMR:
1561         case APIC_LVTPC:
1562         case APIC_LVT1:
1563         case APIC_LVTERR:
1564                 /* TODO: Check vector */
1565                 if (!kvm_apic_sw_enabled(apic))
1566                         val |= APIC_LVT_MASKED;
1567
1568                 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1569                 kvm_lapic_set_reg(apic, reg, val);
1570
1571                 break;
1572
1573         case APIC_LVTT:
1574                 if (!kvm_apic_sw_enabled(apic))
1575                         val |= APIC_LVT_MASKED;
1576                 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1577                 kvm_lapic_set_reg(apic, APIC_LVTT, val);
1578                 apic_update_lvtt(apic);
1579                 break;
1580
1581         case APIC_TMICT:
1582                 if (apic_lvtt_tscdeadline(apic))
1583                         break;
1584
1585                 hrtimer_cancel(&apic->lapic_timer.timer);
1586                 kvm_lapic_set_reg(apic, APIC_TMICT, val);
1587                 start_apic_timer(apic);
1588                 break;
1589
1590         case APIC_TDCR:
1591                 if (val & 4)
1592                         apic_debug("KVM_WRITE:TDCR %x\n", val);
1593                 kvm_lapic_set_reg(apic, APIC_TDCR, val);
1594                 update_divide_count(apic);
1595                 break;
1596
1597         case APIC_ESR:
1598                 if (apic_x2apic_mode(apic) && val != 0) {
1599                         apic_debug("KVM_WRITE:ESR not zero %x\n", val);
1600                         ret = 1;
1601                 }
1602                 break;
1603
1604         case APIC_SELF_IPI:
1605                 if (apic_x2apic_mode(apic)) {
1606                         kvm_lapic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1607                 } else
1608                         ret = 1;
1609                 break;
1610         default:
1611                 ret = 1;
1612                 break;
1613         }
1614         if (ret)
1615                 apic_debug("Local APIC Write to read-only register %x\n", reg);
1616         return ret;
1617 }
1618 EXPORT_SYMBOL_GPL(kvm_lapic_reg_write);
1619
1620 static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1621                             gpa_t address, int len, const void *data)
1622 {
1623         struct kvm_lapic *apic = to_lapic(this);
1624         unsigned int offset = address - apic->base_address;
1625         u32 val;
1626
1627         if (!apic_mmio_in_range(apic, address))
1628                 return -EOPNOTSUPP;
1629
1630         /*
1631          * APIC register must be aligned on 128-bits boundary.
1632          * 32/64/128 bits registers must be accessed thru 32 bits.
1633          * Refer SDM 8.4.1
1634          */
1635         if (len != 4 || (offset & 0xf)) {
1636                 /* Don't shout loud, $infamous_os would cause only noise. */
1637                 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
1638                 return 0;
1639         }
1640
1641         val = *(u32*)data;
1642
1643         /* too common printing */
1644         if (offset != APIC_EOI)
1645                 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1646                            "0x%x\n", __func__, offset, len, val);
1647
1648         kvm_lapic_reg_write(apic, offset & 0xff0, val);
1649
1650         return 0;
1651 }
1652
1653 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1654 {
1655         kvm_lapic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1656 }
1657 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1658
1659 /* emulate APIC access in a trap manner */
1660 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1661 {
1662         u32 val = 0;
1663
1664         /* hw has done the conditional check and inst decode */
1665         offset &= 0xff0;
1666
1667         kvm_lapic_reg_read(vcpu->arch.apic, offset, 4, &val);
1668
1669         /* TODO: optimize to just emulate side effect w/o one more write */
1670         kvm_lapic_reg_write(vcpu->arch.apic, offset, val);
1671 }
1672 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
1673
1674 void kvm_free_lapic(struct kvm_vcpu *vcpu)
1675 {
1676         struct kvm_lapic *apic = vcpu->arch.apic;
1677
1678         if (!vcpu->arch.apic)
1679                 return;
1680
1681         hrtimer_cancel(&apic->lapic_timer.timer);
1682
1683         if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1684                 static_key_slow_dec_deferred(&apic_hw_disabled);
1685
1686         if (!apic->sw_enabled)
1687                 static_key_slow_dec_deferred(&apic_sw_disabled);
1688
1689         if (apic->regs)
1690                 free_page((unsigned long)apic->regs);
1691
1692         kfree(apic);
1693 }
1694
1695 /*
1696  *----------------------------------------------------------------------
1697  * LAPIC interface
1698  *----------------------------------------------------------------------
1699  */
1700
1701 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1702 {
1703         struct kvm_lapic *apic = vcpu->arch.apic;
1704
1705         if (!lapic_in_kernel(vcpu) || apic_lvtt_oneshot(apic) ||
1706                         apic_lvtt_period(apic))
1707                 return 0;
1708
1709         return apic->lapic_timer.tscdeadline;
1710 }
1711
1712 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1713 {
1714         struct kvm_lapic *apic = vcpu->arch.apic;
1715
1716         if (!lapic_in_kernel(vcpu) || apic_lvtt_oneshot(apic) ||
1717                         apic_lvtt_period(apic))
1718                 return;
1719
1720         hrtimer_cancel(&apic->lapic_timer.timer);
1721         apic->lapic_timer.tscdeadline = data;
1722         start_apic_timer(apic);
1723 }
1724
1725 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1726 {
1727         struct kvm_lapic *apic = vcpu->arch.apic;
1728
1729         apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
1730                      | (kvm_lapic_get_reg(apic, APIC_TASKPRI) & 4));
1731 }
1732
1733 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1734 {
1735         u64 tpr;
1736
1737         tpr = (u64) kvm_lapic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
1738
1739         return (tpr & 0xf0) >> 4;
1740 }
1741
1742 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1743 {
1744         u64 old_value = vcpu->arch.apic_base;
1745         struct kvm_lapic *apic = vcpu->arch.apic;
1746
1747         if (!apic) {
1748                 value |= MSR_IA32_APICBASE_BSP;
1749                 vcpu->arch.apic_base = value;
1750                 return;
1751         }
1752
1753         vcpu->arch.apic_base = value;
1754
1755         /* update jump label if enable bit changes */
1756         if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
1757                 if (value & MSR_IA32_APICBASE_ENABLE) {
1758                         kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
1759                         static_key_slow_dec_deferred(&apic_hw_disabled);
1760                 } else
1761                         static_key_slow_inc(&apic_hw_disabled.key);
1762                 recalculate_apic_map(vcpu->kvm);
1763         }
1764
1765         if ((old_value ^ value) & X2APIC_ENABLE) {
1766                 if (value & X2APIC_ENABLE) {
1767                         kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id);
1768                         kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
1769                 } else
1770                         kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
1771         }
1772
1773         apic->base_address = apic->vcpu->arch.apic_base &
1774                              MSR_IA32_APICBASE_BASE;
1775
1776         if ((value & MSR_IA32_APICBASE_ENABLE) &&
1777              apic->base_address != APIC_DEFAULT_PHYS_BASE)
1778                 pr_warn_once("APIC base relocation is unsupported by KVM");
1779
1780         /* with FSB delivery interrupt, we can restart APIC functionality */
1781         apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
1782                    "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
1783
1784 }
1785
1786 void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
1787 {
1788         struct kvm_lapic *apic;
1789         int i;
1790
1791         apic_debug("%s\n", __func__);
1792
1793         ASSERT(vcpu);
1794         apic = vcpu->arch.apic;
1795         ASSERT(apic != NULL);
1796
1797         /* Stop the timer in case it's a reset to an active apic */
1798         hrtimer_cancel(&apic->lapic_timer.timer);
1799
1800         if (!init_event) {
1801                 kvm_lapic_set_base(vcpu, APIC_DEFAULT_PHYS_BASE |
1802                                          MSR_IA32_APICBASE_ENABLE);
1803                 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
1804         }
1805         kvm_apic_set_version(apic->vcpu);
1806
1807         for (i = 0; i < KVM_APIC_LVT_NUM; i++)
1808                 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
1809         apic_update_lvtt(apic);
1810         if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED))
1811                 kvm_lapic_set_reg(apic, APIC_LVT0,
1812                              SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
1813         apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
1814
1815         kvm_lapic_set_reg(apic, APIC_DFR, 0xffffffffU);
1816         apic_set_spiv(apic, 0xff);
1817         kvm_lapic_set_reg(apic, APIC_TASKPRI, 0);
1818         if (!apic_x2apic_mode(apic))
1819                 kvm_apic_set_ldr(apic, 0);
1820         kvm_lapic_set_reg(apic, APIC_ESR, 0);
1821         kvm_lapic_set_reg(apic, APIC_ICR, 0);
1822         kvm_lapic_set_reg(apic, APIC_ICR2, 0);
1823         kvm_lapic_set_reg(apic, APIC_TDCR, 0);
1824         kvm_lapic_set_reg(apic, APIC_TMICT, 0);
1825         for (i = 0; i < 8; i++) {
1826                 kvm_lapic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1827                 kvm_lapic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1828                 kvm_lapic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1829         }
1830         apic->irr_pending = vcpu->arch.apicv_active;
1831         apic->isr_count = vcpu->arch.apicv_active ? 1 : 0;
1832         apic->highest_isr_cache = -1;
1833         update_divide_count(apic);
1834         atomic_set(&apic->lapic_timer.pending, 0);
1835         if (kvm_vcpu_is_bsp(vcpu))
1836                 kvm_lapic_set_base(vcpu,
1837                                 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
1838         vcpu->arch.pv_eoi.msr_val = 0;
1839         apic_update_ppr(apic);
1840
1841         vcpu->arch.apic_arb_prio = 0;
1842         vcpu->arch.apic_attention = 0;
1843
1844         apic_debug("%s: vcpu=%p, id=%d, base_msr="
1845                    "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
1846                    vcpu, kvm_apic_id(apic),
1847                    vcpu->arch.apic_base, apic->base_address);
1848 }
1849
1850 /*
1851  *----------------------------------------------------------------------
1852  * timer interface
1853  *----------------------------------------------------------------------
1854  */
1855
1856 static bool lapic_is_periodic(struct kvm_lapic *apic)
1857 {
1858         return apic_lvtt_period(apic);
1859 }
1860
1861 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1862 {
1863         struct kvm_lapic *apic = vcpu->arch.apic;
1864
1865         if (apic_enabled(apic) && apic_lvt_enabled(apic, APIC_LVTT))
1866                 return atomic_read(&apic->lapic_timer.pending);
1867
1868         return 0;
1869 }
1870
1871 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1872 {
1873         u32 reg = kvm_lapic_get_reg(apic, lvt_type);
1874         int vector, mode, trig_mode;
1875
1876         if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
1877                 vector = reg & APIC_VECTOR_MASK;
1878                 mode = reg & APIC_MODE_MASK;
1879                 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1880                 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
1881                                         NULL);
1882         }
1883         return 0;
1884 }
1885
1886 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
1887 {
1888         struct kvm_lapic *apic = vcpu->arch.apic;
1889
1890         if (apic)
1891                 kvm_apic_local_deliver(apic, APIC_LVT0);
1892 }
1893
1894 static const struct kvm_io_device_ops apic_mmio_ops = {
1895         .read     = apic_mmio_read,
1896         .write    = apic_mmio_write,
1897 };
1898
1899 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
1900 {
1901         struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
1902         struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
1903
1904         apic_timer_expired(apic);
1905
1906         if (lapic_is_periodic(apic)) {
1907                 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
1908                 return HRTIMER_RESTART;
1909         } else
1910                 return HRTIMER_NORESTART;
1911 }
1912
1913 int kvm_create_lapic(struct kvm_vcpu *vcpu)
1914 {
1915         struct kvm_lapic *apic;
1916
1917         ASSERT(vcpu != NULL);
1918         apic_debug("apic_init %d\n", vcpu->vcpu_id);
1919
1920         apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1921         if (!apic)
1922                 goto nomem;
1923
1924         vcpu->arch.apic = apic;
1925
1926         apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1927         if (!apic->regs) {
1928                 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1929                        vcpu->vcpu_id);
1930                 goto nomem_free_apic;
1931         }
1932         apic->vcpu = vcpu;
1933
1934         hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1935                      HRTIMER_MODE_ABS_PINNED);
1936         apic->lapic_timer.timer.function = apic_timer_fn;
1937
1938         /*
1939          * APIC is created enabled. This will prevent kvm_lapic_set_base from
1940          * thinking that APIC satet has changed.
1941          */
1942         vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
1943         static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
1944         kvm_lapic_reset(vcpu, false);
1945         kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
1946
1947         return 0;
1948 nomem_free_apic:
1949         kfree(apic);
1950 nomem:
1951         return -ENOMEM;
1952 }
1953
1954 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1955 {
1956         struct kvm_lapic *apic = vcpu->arch.apic;
1957         int highest_irr;
1958
1959         if (!apic_enabled(apic))
1960                 return -1;
1961
1962         apic_update_ppr(apic);
1963         highest_irr = apic_find_highest_irr(apic);
1964         if ((highest_irr == -1) ||
1965             ((highest_irr & 0xF0) <= kvm_lapic_get_reg(apic, APIC_PROCPRI)))
1966                 return -1;
1967         return highest_irr;
1968 }
1969
1970 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1971 {
1972         u32 lvt0 = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVT0);
1973         int r = 0;
1974
1975         if (!kvm_apic_hw_enabled(vcpu->arch.apic))
1976                 r = 1;
1977         if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1978             GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1979                 r = 1;
1980         return r;
1981 }
1982
1983 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1984 {
1985         struct kvm_lapic *apic = vcpu->arch.apic;
1986
1987         if (atomic_read(&apic->lapic_timer.pending) > 0) {
1988                 kvm_apic_local_deliver(apic, APIC_LVTT);
1989                 if (apic_lvtt_tscdeadline(apic))
1990                         apic->lapic_timer.tscdeadline = 0;
1991                 atomic_set(&apic->lapic_timer.pending, 0);
1992         }
1993 }
1994
1995 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1996 {
1997         int vector = kvm_apic_has_interrupt(vcpu);
1998         struct kvm_lapic *apic = vcpu->arch.apic;
1999
2000         if (vector == -1)
2001                 return -1;
2002
2003         /*
2004          * We get here even with APIC virtualization enabled, if doing
2005          * nested virtualization and L1 runs with the "acknowledge interrupt
2006          * on exit" mode.  Then we cannot inject the interrupt via RVI,
2007          * because the process would deliver it through the IDT.
2008          */
2009
2010         apic_set_isr(vector, apic);
2011         apic_update_ppr(apic);
2012         apic_clear_irr(vector, apic);
2013
2014         if (test_bit(vector, vcpu_to_synic(vcpu)->auto_eoi_bitmap)) {
2015                 apic_clear_isr(vector, apic);
2016                 apic_update_ppr(apic);
2017         }
2018
2019         return vector;
2020 }
2021
2022 static int kvm_apic_state_fixup(struct kvm_vcpu *vcpu,
2023                 struct kvm_lapic_state *s, bool set)
2024 {
2025         if (apic_x2apic_mode(vcpu->arch.apic)) {
2026                 u32 *id = (u32 *)(s->regs + APIC_ID);
2027
2028                 if (vcpu->kvm->arch.x2apic_format) {
2029                         if (*id != vcpu->vcpu_id)
2030                                 return -EINVAL;
2031                 } else {
2032                         if (set)
2033                                 *id >>= 24;
2034                         else
2035                                 *id <<= 24;
2036                 }
2037         }
2038
2039         return 0;
2040 }
2041
2042 int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
2043 {
2044         memcpy(s->regs, vcpu->arch.apic->regs, sizeof(*s));
2045         return kvm_apic_state_fixup(vcpu, s, false);
2046 }
2047
2048 int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
2049 {
2050         struct kvm_lapic *apic = vcpu->arch.apic;
2051         int r;
2052
2053
2054         kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
2055         /* set SPIV separately to get count of SW disabled APICs right */
2056         apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
2057
2058         r = kvm_apic_state_fixup(vcpu, s, true);
2059         if (r)
2060                 return r;
2061         memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
2062
2063         recalculate_apic_map(vcpu->kvm);
2064         kvm_apic_set_version(vcpu);
2065
2066         apic_update_ppr(apic);
2067         hrtimer_cancel(&apic->lapic_timer.timer);
2068         apic_update_lvtt(apic);
2069         apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
2070         update_divide_count(apic);
2071         start_apic_timer(apic);
2072         apic->irr_pending = true;
2073         apic->isr_count = vcpu->arch.apicv_active ?
2074                                 1 : count_vectors(apic->regs + APIC_ISR);
2075         apic->highest_isr_cache = -1;
2076         if (vcpu->arch.apicv_active) {
2077                 if (kvm_x86_ops->apicv_post_state_restore)
2078                         kvm_x86_ops->apicv_post_state_restore(vcpu);
2079                 kvm_x86_ops->hwapic_irr_update(vcpu,
2080                                 apic_find_highest_irr(apic));
2081                 kvm_x86_ops->hwapic_isr_update(vcpu,
2082                                 apic_find_highest_isr(apic));
2083         }
2084         kvm_make_request(KVM_REQ_EVENT, vcpu);
2085         if (ioapic_in_kernel(vcpu->kvm))
2086                 kvm_rtc_eoi_tracking_restore_one(vcpu);
2087
2088         vcpu->arch.apic_arb_prio = 0;
2089
2090         return 0;
2091 }
2092
2093 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
2094 {
2095         struct hrtimer *timer;
2096
2097         if (!lapic_in_kernel(vcpu))
2098                 return;
2099
2100         timer = &vcpu->arch.apic->lapic_timer.timer;
2101         if (hrtimer_cancel(timer))
2102                 hrtimer_start_expires(timer, HRTIMER_MODE_ABS_PINNED);
2103 }
2104
2105 /*
2106  * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
2107  *
2108  * Detect whether guest triggered PV EOI since the
2109  * last entry. If yes, set EOI on guests's behalf.
2110  * Clear PV EOI in guest memory in any case.
2111  */
2112 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
2113                                         struct kvm_lapic *apic)
2114 {
2115         bool pending;
2116         int vector;
2117         /*
2118          * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
2119          * and KVM_PV_EOI_ENABLED in guest memory as follows:
2120          *
2121          * KVM_APIC_PV_EOI_PENDING is unset:
2122          *      -> host disabled PV EOI.
2123          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
2124          *      -> host enabled PV EOI, guest did not execute EOI yet.
2125          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
2126          *      -> host enabled PV EOI, guest executed EOI.
2127          */
2128         BUG_ON(!pv_eoi_enabled(vcpu));
2129         pending = pv_eoi_get_pending(vcpu);
2130         /*
2131          * Clear pending bit in any case: it will be set again on vmentry.
2132          * While this might not be ideal from performance point of view,
2133          * this makes sure pv eoi is only enabled when we know it's safe.
2134          */
2135         pv_eoi_clr_pending(vcpu);
2136         if (pending)
2137                 return;
2138         vector = apic_set_eoi(apic);
2139         trace_kvm_pv_eoi(apic, vector);
2140 }
2141
2142 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
2143 {
2144         u32 data;
2145
2146         if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
2147                 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
2148
2149         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
2150                 return;
2151
2152         if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2153                                   sizeof(u32)))
2154                 return;
2155
2156         apic_set_tpr(vcpu->arch.apic, data & 0xff);
2157 }
2158
2159 /*
2160  * apic_sync_pv_eoi_to_guest - called before vmentry
2161  *
2162  * Detect whether it's safe to enable PV EOI and
2163  * if yes do so.
2164  */
2165 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
2166                                         struct kvm_lapic *apic)
2167 {
2168         if (!pv_eoi_enabled(vcpu) ||
2169             /* IRR set or many bits in ISR: could be nested. */
2170             apic->irr_pending ||
2171             /* Cache not set: could be safe but we don't bother. */
2172             apic->highest_isr_cache == -1 ||
2173             /* Need EOI to update ioapic. */
2174             kvm_ioapic_handles_vector(apic, apic->highest_isr_cache)) {
2175                 /*
2176                  * PV EOI was disabled by apic_sync_pv_eoi_from_guest
2177                  * so we need not do anything here.
2178                  */
2179                 return;
2180         }
2181
2182         pv_eoi_set_pending(apic->vcpu);
2183 }
2184
2185 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
2186 {
2187         u32 data, tpr;
2188         int max_irr, max_isr;
2189         struct kvm_lapic *apic = vcpu->arch.apic;
2190
2191         apic_sync_pv_eoi_to_guest(vcpu, apic);
2192
2193         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
2194                 return;
2195
2196         tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI) & 0xff;
2197         max_irr = apic_find_highest_irr(apic);
2198         if (max_irr < 0)
2199                 max_irr = 0;
2200         max_isr = apic_find_highest_isr(apic);
2201         if (max_isr < 0)
2202                 max_isr = 0;
2203         data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
2204
2205         kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2206                                 sizeof(u32));
2207 }
2208
2209 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
2210 {
2211         if (vapic_addr) {
2212                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2213                                         &vcpu->arch.apic->vapic_cache,
2214                                         vapic_addr, sizeof(u32)))
2215                         return -EINVAL;
2216                 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
2217         } else {
2218                 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
2219         }
2220
2221         vcpu->arch.apic->vapic_addr = vapic_addr;
2222         return 0;
2223 }
2224
2225 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2226 {
2227         struct kvm_lapic *apic = vcpu->arch.apic;
2228         u32 reg = (msr - APIC_BASE_MSR) << 4;
2229
2230         if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
2231                 return 1;
2232
2233         if (reg == APIC_ICR2)
2234                 return 1;
2235
2236         /* if this is ICR write vector before command */
2237         if (reg == APIC_ICR)
2238                 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2239         return kvm_lapic_reg_write(apic, reg, (u32)data);
2240 }
2241
2242 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
2243 {
2244         struct kvm_lapic *apic = vcpu->arch.apic;
2245         u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
2246
2247         if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
2248                 return 1;
2249
2250         if (reg == APIC_DFR || reg == APIC_ICR2) {
2251                 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
2252                            reg);
2253                 return 1;
2254         }
2255
2256         if (kvm_lapic_reg_read(apic, reg, 4, &low))
2257                 return 1;
2258         if (reg == APIC_ICR)
2259                 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
2260
2261         *data = (((u64)high) << 32) | low;
2262
2263         return 0;
2264 }
2265
2266 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
2267 {
2268         struct kvm_lapic *apic = vcpu->arch.apic;
2269
2270         if (!lapic_in_kernel(vcpu))
2271                 return 1;
2272
2273         /* if this is ICR write vector before command */
2274         if (reg == APIC_ICR)
2275                 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2276         return kvm_lapic_reg_write(apic, reg, (u32)data);
2277 }
2278
2279 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
2280 {
2281         struct kvm_lapic *apic = vcpu->arch.apic;
2282         u32 low, high = 0;
2283
2284         if (!lapic_in_kernel(vcpu))
2285                 return 1;
2286
2287         if (kvm_lapic_reg_read(apic, reg, 4, &low))
2288                 return 1;
2289         if (reg == APIC_ICR)
2290                 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
2291
2292         *data = (((u64)high) << 32) | low;
2293
2294         return 0;
2295 }
2296
2297 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
2298 {
2299         u64 addr = data & ~KVM_MSR_ENABLED;
2300         if (!IS_ALIGNED(addr, 4))
2301                 return 1;
2302
2303         vcpu->arch.pv_eoi.msr_val = data;
2304         if (!pv_eoi_enabled(vcpu))
2305                 return 0;
2306         return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
2307                                          addr, sizeof(u8));
2308 }
2309
2310 void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
2311 {
2312         struct kvm_lapic *apic = vcpu->arch.apic;
2313         u8 sipi_vector;
2314         unsigned long pe;
2315
2316         if (!lapic_in_kernel(vcpu) || !apic->pending_events)
2317                 return;
2318
2319         /*
2320          * INITs are latched while in SMM.  Because an SMM CPU cannot
2321          * be in KVM_MP_STATE_INIT_RECEIVED state, just eat SIPIs
2322          * and delay processing of INIT until the next RSM.
2323          */
2324         if (is_smm(vcpu)) {
2325                 WARN_ON_ONCE(vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED);
2326                 if (test_bit(KVM_APIC_SIPI, &apic->pending_events))
2327                         clear_bit(KVM_APIC_SIPI, &apic->pending_events);
2328                 return;
2329         }
2330
2331         pe = xchg(&apic->pending_events, 0);
2332         if (test_bit(KVM_APIC_INIT, &pe)) {
2333                 kvm_lapic_reset(vcpu, true);
2334                 kvm_vcpu_reset(vcpu, true);
2335                 if (kvm_vcpu_is_bsp(apic->vcpu))
2336                         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2337                 else
2338                         vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
2339         }
2340         if (test_bit(KVM_APIC_SIPI, &pe) &&
2341             vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
2342                 /* evaluate pending_events before reading the vector */
2343                 smp_rmb();
2344                 sipi_vector = apic->sipi_vector;
2345                 apic_debug("vcpu %d received sipi with vector # %x\n",
2346                          vcpu->vcpu_id, sipi_vector);
2347                 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
2348                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2349         }
2350 }
2351
2352 void kvm_lapic_init(void)
2353 {
2354         /* do not patch jump label more than once per second */
2355         jump_label_rate_limit(&apic_hw_disabled, HZ);
2356         jump_label_rate_limit(&apic_sw_disabled, HZ);
2357 }