arch/x86/kvm/lapic.c

   1
   2 /*
   3  * Local APIC virtualization
   4  *
   5  * Copyright (C) 2006 Qumranet, Inc.
   6  * Copyright (C) 2007 Novell
   7  * Copyright (C) 2007 Intel
   8  * Copyright 2009 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Dor Laor <dor.laor@qumranet.com>
  12  *   Gregory Haskins <ghaskins@novell.com>
  13  *   Yaozu (Eddie) Dong <eddie.dong@intel.com>
  14  *
  15  * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
  16  *
  17  * This work is licensed under the terms of the GNU GPL, version 2.  See
  18  * the COPYING file in the top-level directory.
  19  */
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/kvm.h>
  23 #include <linux/mm.h>
  24 #include <linux/highmem.h>
  25 #include <linux/smp.h>
  26 #include <linux/hrtimer.h>
  27 #include <linux/io.h>
  28 #include <linux/module.h>
  29 #include <linux/math64.h>
  30 #include <linux/slab.h>
  31 #include <asm/processor.h>
  32 #include <asm/msr.h>
  33 #include <asm/page.h>
  34 #include <asm/current.h>
  35 #include <asm/apicdef.h>
  36 #include <asm/delay.h>
  37 #include <linux/atomic.h>
  38 #include <linux/jump_label.h>
  39 #include "kvm_cache_regs.h"
  40 #include "irq.h"
  41 #include "trace.h"
  42 #include "x86.h"
  43 #include "cpuid.h"
  44
  45 #ifndef CONFIG_X86_64
  46 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
  47 #else
  48 #define mod_64(x, y) ((x) % (y))
  49 #endif
  50
  51 #define PRId64 "d"
  52 #define PRIx64 "llx"
  53 #define PRIu64 "u"
  54 #define PRIo64 "o"
  55
  56 #define APIC_BUS_CYCLE_NS 1
  57
  58 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
  59 #define apic_debug(fmt, arg...)
  60
  61 #define APIC_LVT_NUM                    6
  62 /* 14 is the version for Xeon and Pentium 8.4.8*/
  63 #define APIC_VERSION                    (0x14UL | ((APIC_LVT_NUM - 1) << 16))
  64 #define LAPIC_MMIO_LENGTH               (1 << 12)
  65 /* followed define is not in apicdef.h */
  66 #define APIC_SHORT_MASK                 0xc0000
  67 #define APIC_DEST_NOSHORT               0x0
  68 #define APIC_DEST_MASK                  0x800
  69 #define MAX_APIC_VECTOR                 256
  70 #define APIC_VECTORS_PER_REG            32
  71
  72 #define APIC_BROADCAST                  0xFF
  73 #define X2APIC_BROADCAST                0xFFFFFFFFul
  74
  75 #define VEC_POS(v) ((v) & (32 - 1))
  76 #define REG_POS(v) (((v) >> 5) << 4)
  77
  78 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
  79 {
  80         *((u32 *) (apic->regs + reg_off)) = val;
  81 }
  82
  83 static inline int apic_test_vector(int vec, void *bitmap)
  84 {
  85         return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  86 }
  87
  88 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
  89 {
  90         struct kvm_lapic *apic = vcpu->arch.apic;
  91
  92         return apic_test_vector(vector, apic->regs + APIC_ISR) ||
  93                 apic_test_vector(vector, apic->regs + APIC_IRR);
  94 }
  95
  96 static inline void apic_set_vector(int vec, void *bitmap)
  97 {
  98         set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  99 }
 100
 101 static inline void apic_clear_vector(int vec, void *bitmap)
 102 {
 103         clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 104 }
 105
 106 static inline int __apic_test_and_set_vector(int vec, void *bitmap)
 107 {
 108         return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 109 }
 110
 111 static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
 112 {
 113         return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 114 }
 115
 116 struct static_key_deferred apic_hw_disabled __read_mostly;
 117 struct static_key_deferred apic_sw_disabled __read_mostly;
 118
 119 static inline int apic_enabled(struct kvm_lapic *apic)
 120 {
 121         return kvm_apic_sw_enabled(apic) &&     kvm_apic_hw_enabled(apic);
 122 }
 123
 124 #define LVT_MASK        \
 125         (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
 126
 127 #define LINT_MASK       \
 128         (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
 129          APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
 130
 131 static inline int kvm_apic_id(struct kvm_lapic *apic)
 132 {
 133         return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
 134 }
 135
 136 static void recalculate_apic_map(struct kvm *kvm)
 137 {
 138         struct kvm_apic_map *new, *old = NULL;
 139         struct kvm_vcpu *vcpu;
 140         int i;
 141
 142         new = kzalloc(sizeof(struct kvm_apic_map), GFP_KERNEL);
 143
 144         mutex_lock(&kvm->arch.apic_map_lock);
 145
 146         if (!new)
 147                 goto out;
 148
 149         new->ldr_bits = 8;
 150         /* flat mode is default */
 151         new->cid_shift = 8;
 152         new->cid_mask = 0;
 153         new->lid_mask = 0xff;
 154         new->broadcast = APIC_BROADCAST;
 155
 156         kvm_for_each_vcpu(i, vcpu, kvm) {
 157                 struct kvm_lapic *apic = vcpu->arch.apic;
 158
 159                 if (!kvm_apic_present(vcpu))
 160                         continue;
 161
 162                 if (apic_x2apic_mode(apic)) {
 163                         new->ldr_bits = 32;
 164                         new->cid_shift = 16;
 165                         new->cid_mask = new->lid_mask = 0xffff;
 166                         new->broadcast = X2APIC_BROADCAST;
 167                 } else if (kvm_apic_get_reg(apic, APIC_LDR)) {
 168                         if (kvm_apic_get_reg(apic, APIC_DFR) ==
 169                                                         APIC_DFR_CLUSTER) {
 170                                 new->cid_shift = 4;
 171                                 new->cid_mask = 0xf;
 172                                 new->lid_mask = 0xf;
 173                         } else {
 174                                 new->cid_shift = 8;
 175                                 new->cid_mask = 0;
 176                                 new->lid_mask = 0xff;
 177                         }
 178                 }
 179
 180                 /*
 181                  * All APICs have to be configured in the same mode by an OS.
 182                  * We take advatage of this while building logical id loockup
 183                  * table. After reset APICs are in software disabled mode, so if
 184                  * we find apic with different setting we assume this is the mode
 185                  * OS wants all apics to be in; build lookup table accordingly.
 186                  */
 187                 if (kvm_apic_sw_enabled(apic))
 188                         break;
 189         }
 190
 191         kvm_for_each_vcpu(i, vcpu, kvm) {
 192                 struct kvm_lapic *apic = vcpu->arch.apic;
 193                 u16 cid, lid;
 194                 u32 ldr, aid;
 195
 196                 aid = kvm_apic_id(apic);
 197                 ldr = kvm_apic_get_reg(apic, APIC_LDR);
 198                 cid = apic_cluster_id(new, ldr);
 199                 lid = apic_logical_id(new, ldr);
 200
 201                 if (aid < ARRAY_SIZE(new->phys_map))
 202                         new->phys_map[aid] = apic;
 203                 if (lid && cid < ARRAY_SIZE(new->logical_map))
 204                         new->logical_map[cid][ffs(lid) - 1] = apic;
 205         }
 206 out:
 207         old = rcu_dereference_protected(kvm->arch.apic_map,
 208                         lockdep_is_held(&kvm->arch.apic_map_lock));
 209         rcu_assign_pointer(kvm->arch.apic_map, new);
 210         mutex_unlock(&kvm->arch.apic_map_lock);
 211
 212         if (old)
 213                 kfree_rcu(old, rcu);
 214
 215         kvm_vcpu_request_scan_ioapic(kvm);
 216 }
 217
 218 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
 219 {
 220         bool enabled = val & APIC_SPIV_APIC_ENABLED;
 221
 222         apic_set_reg(apic, APIC_SPIV, val);
 223
 224         if (enabled != apic->sw_enabled) {
 225                 apic->sw_enabled = enabled;
 226                 if (enabled) {
 227                         static_key_slow_dec_deferred(&apic_sw_disabled);
 228                         recalculate_apic_map(apic->vcpu->kvm);
 229                 } else
 230                         static_key_slow_inc(&apic_sw_disabled.key);
 231         }
 232 }
 233
 234 static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id)
 235 {
 236         apic_set_reg(apic, APIC_ID, id << 24);
 237         recalculate_apic_map(apic->vcpu->kvm);
 238 }
 239
 240 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
 241 {
 242         apic_set_reg(apic, APIC_LDR, id);
 243         recalculate_apic_map(apic->vcpu->kvm);
 244 }
 245
 246 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
 247 {
 248         return !(kvm_apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
 249 }
 250
 251 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
 252 {
 253         return kvm_apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
 254 }
 255
 256 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
 257 {
 258         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
 259 }
 260
 261 static inline int apic_lvtt_period(struct kvm_lapic *apic)
 262 {
 263         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
 264 }
 265
 266 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
 267 {
 268         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
 269 }
 270
 271 static inline int apic_lvt_nmi_mode(u32 lvt_val)
 272 {
 273         return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
 274 }
 275
 276 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
 277 {
 278         struct kvm_lapic *apic = vcpu->arch.apic;
 279         struct kvm_cpuid_entry2 *feat;
 280         u32 v = APIC_VERSION;
 281
 282         if (!kvm_vcpu_has_lapic(vcpu))
 283                 return;
 284
 285         feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
 286         if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
 287                 v |= APIC_LVR_DIRECTED_EOI;
 288         apic_set_reg(apic, APIC_LVR, v);
 289 }
 290
 291 static const unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
 292         LVT_MASK ,      /* part LVTT mask, timer mode mask added at runtime */
 293         LVT_MASK | APIC_MODE_MASK,      /* LVTTHMR */
 294         LVT_MASK | APIC_MODE_MASK,      /* LVTPC */
 295         LINT_MASK, LINT_MASK,   /* LVT0-1 */
 296         LVT_MASK                /* LVTERR */
 297 };
 298
 299 static int find_highest_vector(void *bitmap)
 300 {
 301         int vec;
 302         u32 *reg;
 303
 304         for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
 305              vec >= 0; vec -= APIC_VECTORS_PER_REG) {
 306                 reg = bitmap + REG_POS(vec);
 307                 if (*reg)
 308                         return fls(*reg) - 1 + vec;
 309         }
 310
 311         return -1;
 312 }
 313
 314 static u8 count_vectors(void *bitmap)
 315 {
 316         int vec;
 317         u32 *reg;
 318         u8 count = 0;
 319
 320         for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
 321                 reg = bitmap + REG_POS(vec);
 322                 count += hweight32(*reg);
 323         }
 324
 325         return count;
 326 }
 327
 328 void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir)
 329 {
 330         u32 i, pir_val;
 331         struct kvm_lapic *apic = vcpu->arch.apic;
 332
 333         for (i = 0; i <= 7; i++) {
 334                 pir_val = xchg(&pir[i], 0);
 335                 if (pir_val)
 336                         *((u32 *)(apic->regs + APIC_IRR + i * 0x10)) |= pir_val;
 337         }
 338 }
 339 EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
 340
 341 static inline void apic_set_irr(int vec, struct kvm_lapic *apic)
 342 {
 343         apic_set_vector(vec, apic->regs + APIC_IRR);
 344         /*
 345          * irr_pending must be true if any interrupt is pending; set it after
 346          * APIC_IRR to avoid race with apic_clear_irr
 347          */
 348         apic->irr_pending = true;
 349 }
 350
 351 static inline int apic_search_irr(struct kvm_lapic *apic)
 352 {
 353         return find_highest_vector(apic->regs + APIC_IRR);
 354 }
 355
 356 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
 357 {
 358         int result;
 359
 360         /*
 361          * Note that irr_pending is just a hint. It will be always
 362          * true with virtual interrupt delivery enabled.
 363          */
 364         if (!apic->irr_pending)
 365                 return -1;
 366
 367         kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
 368         result = apic_search_irr(apic);
 369         ASSERT(result == -1 || result >= 16);
 370
 371         return result;
 372 }
 373
 374 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
 375 {
 376         struct kvm_vcpu *vcpu;
 377
 378         vcpu = apic->vcpu;
 379
 380         if (unlikely(kvm_apic_vid_enabled(vcpu->kvm))) {
 381                 /* try to update RVI */
 382                 apic_clear_vector(vec, apic->regs + APIC_IRR);
 383                 kvm_make_request(KVM_REQ_EVENT, vcpu);
 384         } else {
 385                 apic->irr_pending = false;
 386                 apic_clear_vector(vec, apic->regs + APIC_IRR);
 387                 if (apic_search_irr(apic) != -1)
 388                         apic->irr_pending = true;
 389         }
 390 }
 391
 392 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
 393 {
 394         struct kvm_vcpu *vcpu;
 395
 396         if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
 397                 return;
 398
 399         vcpu = apic->vcpu;
 400
 401         /*
 402          * With APIC virtualization enabled, all caching is disabled
 403          * because the processor can modify ISR under the hood.  Instead
 404          * just set SVI.
 405          */
 406         if (unlikely(kvm_x86_ops->hwapic_isr_update))
 407                 kvm_x86_ops->hwapic_isr_update(vcpu->kvm, vec);
 408         else {
 409                 ++apic->isr_count;
 410                 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
 411                 /*
 412                  * ISR (in service register) bit is set when injecting an interrupt.
 413                  * The highest vector is injected. Thus the latest bit set matches
 414                  * the highest bit in ISR.
 415                  */
 416                 apic->highest_isr_cache = vec;
 417         }
 418 }
 419
 420 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
 421 {
 422         int result;
 423
 424         /*
 425          * Note that isr_count is always 1, and highest_isr_cache
 426          * is always -1, with APIC virtualization enabled.
 427          */
 428         if (!apic->isr_count)
 429                 return -1;
 430         if (likely(apic->highest_isr_cache != -1))
 431                 return apic->highest_isr_cache;
 432
 433         result = find_highest_vector(apic->regs + APIC_ISR);
 434         ASSERT(result == -1 || result >= 16);
 435
 436         return result;
 437 }
 438
 439 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
 440 {
 441         struct kvm_vcpu *vcpu;
 442         if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
 443                 return;
 444
 445         vcpu = apic->vcpu;
 446
 447         /*
 448          * We do get here for APIC virtualization enabled if the guest
 449          * uses the Hyper-V APIC enlightenment.  In this case we may need
 450          * to trigger a new interrupt delivery by writing the SVI field;
 451          * on the other hand isr_count and highest_isr_cache are unused
 452          * and must be left alone.
 453          */
 454         if (unlikely(kvm_x86_ops->hwapic_isr_update))
 455                 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
 456                                                apic_find_highest_isr(apic));
 457         else {
 458                 --apic->isr_count;
 459                 BUG_ON(apic->isr_count < 0);
 460                 apic->highest_isr_cache = -1;
 461         }
 462 }
 463
 464 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
 465 {
 466         int highest_irr;
 467
 468         /* This may race with setting of irr in __apic_accept_irq() and
 469          * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
 470          * will cause vmexit immediately and the value will be recalculated
 471          * on the next vmentry.
 472          */
 473         if (!kvm_vcpu_has_lapic(vcpu))
 474                 return 0;
 475         highest_irr = apic_find_highest_irr(vcpu->arch.apic);
 476
 477         return highest_irr;
 478 }
 479
 480 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 481                              int vector, int level, int trig_mode,
 482                              unsigned long *dest_map);
 483
 484 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
 485                 unsigned long *dest_map)
 486 {
 487         struct kvm_lapic *apic = vcpu->arch.apic;
 488
 489         return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
 490                         irq->level, irq->trig_mode, dest_map);
 491 }
 492
 493 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
 494 {
 495
 496         return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
 497                                       sizeof(val));
 498 }
 499
 500 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
 501 {
 502
 503         return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
 504                                       sizeof(*val));
 505 }
 506
 507 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
 508 {
 509         return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
 510 }
 511
 512 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
 513 {
 514         u8 val;
 515         if (pv_eoi_get_user(vcpu, &val) < 0)
 516                 apic_debug("Can't read EOI MSR value: 0x%llx\n",
 517                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 518         return val & 0x1;
 519 }
 520
 521 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
 522 {
 523         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
 524                 apic_debug("Can't set EOI MSR value: 0x%llx\n",
 525                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 526                 return;
 527         }
 528         __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 529 }
 530
 531 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
 532 {
 533         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
 534                 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
 535                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 536                 return;
 537         }
 538         __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 539 }
 540
 541 void kvm_apic_update_tmr(struct kvm_vcpu *vcpu, u32 *tmr)
 542 {
 543         struct kvm_lapic *apic = vcpu->arch.apic;
 544         int i;
 545
 546         for (i = 0; i < 8; i++)
 547                 apic_set_reg(apic, APIC_TMR + 0x10 * i, tmr[i]);
 548 }
 549
 550 static void apic_update_ppr(struct kvm_lapic *apic)
 551 {
 552         u32 tpr, isrv, ppr, old_ppr;
 553         int isr;
 554
 555         old_ppr = kvm_apic_get_reg(apic, APIC_PROCPRI);
 556         tpr = kvm_apic_get_reg(apic, APIC_TASKPRI);
 557         isr = apic_find_highest_isr(apic);
 558         isrv = (isr != -1) ? isr : 0;
 559
 560         if ((tpr & 0xf0) >= (isrv & 0xf0))
 561                 ppr = tpr & 0xff;
 562         else
 563                 ppr = isrv & 0xf0;
 564
 565         apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
 566                    apic, ppr, isr, isrv);
 567
 568         if (old_ppr != ppr) {
 569                 apic_set_reg(apic, APIC_PROCPRI, ppr);
 570                 if (ppr < old_ppr)
 571                         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 572         }
 573 }
 574
 575 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
 576 {
 577         apic_set_reg(apic, APIC_TASKPRI, tpr);
 578         apic_update_ppr(apic);
 579 }
 580
 581 static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 dest)
 582 {
 583         return dest == (apic_x2apic_mode(apic) ?
 584                         X2APIC_BROADCAST : APIC_BROADCAST);
 585 }
 586
 587 static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 dest)
 588 {
 589         return kvm_apic_id(apic) == dest || kvm_apic_broadcast(apic, dest);
 590 }
 591
 592 static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
 593 {
 594         u32 logical_id;
 595
 596         if (kvm_apic_broadcast(apic, mda))
 597                 return true;
 598
 599         logical_id = kvm_apic_get_reg(apic, APIC_LDR);
 600
 601         if (apic_x2apic_mode(apic))
 602                 return (logical_id & mda) != 0;
 603
 604         logical_id = GET_APIC_LOGICAL_ID(logical_id);
 605
 606         switch (kvm_apic_get_reg(apic, APIC_DFR)) {
 607         case APIC_DFR_FLAT:
 608                 return (logical_id & mda) != 0;
 609         case APIC_DFR_CLUSTER:
 610                 return ((logical_id >> 4) == (mda >> 4))
 611                        && (logical_id & mda & 0xf) != 0;
 612         default:
 613                 apic_debug("Bad DFR vcpu %d: %08x\n",
 614                            apic->vcpu->vcpu_id, kvm_apic_get_reg(apic, APIC_DFR));
 615                 return false;
 616         }
 617 }
 618
 619 bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
 620                            int short_hand, unsigned int dest, int dest_mode)
 621 {
 622         struct kvm_lapic *target = vcpu->arch.apic;
 623
 624         apic_debug("target %p, source %p, dest 0x%x, "
 625                    "dest_mode 0x%x, short_hand 0x%x\n",
 626                    target, source, dest, dest_mode, short_hand);
 627
 628         ASSERT(target);
 629         switch (short_hand) {
 630         case APIC_DEST_NOSHORT:
 631                 if (dest_mode == APIC_DEST_PHYSICAL)
 632                         return kvm_apic_match_physical_addr(target, dest);
 633                 else
 634                         return kvm_apic_match_logical_addr(target, dest);
 635         case APIC_DEST_SELF:
 636                 return target == source;
 637         case APIC_DEST_ALLINC:
 638                 return true;
 639         case APIC_DEST_ALLBUT:
 640                 return target != source;
 641         default:
 642                 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
 643                            short_hand);
 644                 return false;
 645         }
 646 }
 647
 648 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
 649                 struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map)
 650 {
 651         struct kvm_apic_map *map;
 652         unsigned long bitmap = 1;
 653         struct kvm_lapic **dst;
 654         int i;
 655         bool ret = false;
 656
 657         *r = -1;
 658
 659         if (irq->shorthand == APIC_DEST_SELF) {
 660                 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
 661                 return true;
 662         }
 663
 664         if (irq->shorthand)
 665                 return false;
 666
 667         rcu_read_lock();
 668         map = rcu_dereference(kvm->arch.apic_map);
 669
 670         if (!map)
 671                 goto out;
 672
 673         if (irq->dest_id == map->broadcast)
 674                 goto out;
 675
 676         ret = true;
 677
 678         if (irq->dest_mode == APIC_DEST_PHYSICAL) {
 679                 if (irq->dest_id >= ARRAY_SIZE(map->phys_map))
 680                         goto out;
 681
 682                 dst = &map->phys_map[irq->dest_id];
 683         } else {
 684                 u32 mda = irq->dest_id << (32 - map->ldr_bits);
 685                 u16 cid = apic_cluster_id(map, mda);
 686
 687                 if (cid >= ARRAY_SIZE(map->logical_map))
 688                         goto out;
 689
 690                 dst = map->logical_map[cid];
 691
 692                 bitmap = apic_logical_id(map, mda);
 693
 694                 if (irq->delivery_mode == APIC_DM_LOWEST) {
 695                         int l = -1;
 696                         for_each_set_bit(i, &bitmap, 16) {
 697                                 if (!dst[i])
 698                                         continue;
 699                                 if (l < 0)
 700                                         l = i;
 701                                 else if (kvm_apic_compare_prio(dst[i]->vcpu, dst[l]->vcpu) < 0)
 702                                         l = i;
 703                         }
 704
 705                         bitmap = (l >= 0) ? 1 << l : 0;
 706                 }
 707         }
 708
 709         for_each_set_bit(i, &bitmap, 16) {
 710                 if (!dst[i])
 711                         continue;
 712                 if (*r < 0)
 713                         *r = 0;
 714                 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
 715         }
 716 out:
 717         rcu_read_unlock();
 718         return ret;
 719 }
 720
 721 /*
 722  * Add a pending IRQ into lapic.
 723  * Return 1 if successfully added and 0 if discarded.
 724  */
 725 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 726                              int vector, int level, int trig_mode,
 727                              unsigned long *dest_map)
 728 {
 729         int result = 0;
 730         struct kvm_vcpu *vcpu = apic->vcpu;
 731
 732         trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
 733                                   trig_mode, vector);
 734         switch (delivery_mode) {
 735         case APIC_DM_LOWEST:
 736                 vcpu->arch.apic_arb_prio++;
 737         case APIC_DM_FIXED:
 738                 /* FIXME add logic for vcpu on reset */
 739                 if (unlikely(!apic_enabled(apic)))
 740                         break;
 741
 742                 result = 1;
 743
 744                 if (dest_map)
 745                         __set_bit(vcpu->vcpu_id, dest_map);
 746
 747                 if (kvm_x86_ops->deliver_posted_interrupt)
 748                         kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
 749                 else {
 750                         apic_set_irr(vector, apic);
 751
 752                         kvm_make_request(KVM_REQ_EVENT, vcpu);
 753                         kvm_vcpu_kick(vcpu);
 754                 }
 755                 break;
 756
 757         case APIC_DM_REMRD:
 758                 result = 1;
 759                 vcpu->arch.pv.pv_unhalted = 1;
 760                 kvm_make_request(KVM_REQ_EVENT, vcpu);
 761                 kvm_vcpu_kick(vcpu);
 762                 break;
 763
 764         case APIC_DM_SMI:
 765                 apic_debug("Ignoring guest SMI\n");
 766                 break;
 767
 768         case APIC_DM_NMI:
 769                 result = 1;
 770                 kvm_inject_nmi(vcpu);
 771                 kvm_vcpu_kick(vcpu);
 772                 break;
 773
 774         case APIC_DM_INIT:
 775                 if (!trig_mode || level) {
 776                         result = 1;
 777                         /* assumes that there are only KVM_APIC_INIT/SIPI */
 778                         apic->pending_events = (1UL << KVM_APIC_INIT);
 779                         /* make sure pending_events is visible before sending
 780                          * the request */
 781                         smp_wmb();
 782                         kvm_make_request(KVM_REQ_EVENT, vcpu);
 783                         kvm_vcpu_kick(vcpu);
 784                 } else {
 785                         apic_debug("Ignoring de-assert INIT to vcpu %d\n",
 786                                    vcpu->vcpu_id);
 787                 }
 788                 break;
 789
 790         case APIC_DM_STARTUP:
 791                 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
 792                            vcpu->vcpu_id, vector);
 793                 result = 1;
 794                 apic->sipi_vector = vector;
 795                 /* make sure sipi_vector is visible for the receiver */
 796                 smp_wmb();
 797                 set_bit(KVM_APIC_SIPI, &apic->pending_events);
 798                 kvm_make_request(KVM_REQ_EVENT, vcpu);
 799                 kvm_vcpu_kick(vcpu);
 800                 break;
 801
 802         case APIC_DM_EXTINT:
 803                 /*
 804                  * Should only be called by kvm_apic_local_deliver() with LVT0,
 805                  * before NMI watchdog was enabled. Already handled by
 806                  * kvm_apic_accept_pic_intr().
 807                  */
 808                 break;
 809
 810         default:
 811                 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
 812                        delivery_mode);
 813                 break;
 814         }
 815         return result;
 816 }
 817
 818 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
 819 {
 820         return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
 821 }
 822
 823 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
 824 {
 825         if (!(kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI) &&
 826             kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) {
 827                 int trigger_mode;
 828                 if (apic_test_vector(vector, apic->regs + APIC_TMR))
 829                         trigger_mode = IOAPIC_LEVEL_TRIG;
 830                 else
 831                         trigger_mode = IOAPIC_EDGE_TRIG;
 832                 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
 833         }
 834 }
 835
 836 static int apic_set_eoi(struct kvm_lapic *apic)
 837 {
 838         int vector = apic_find_highest_isr(apic);
 839
 840         trace_kvm_eoi(apic, vector);
 841
 842         /*
 843          * Not every write EOI will has corresponding ISR,
 844          * one example is when Kernel check timer on setup_IO_APIC
 845          */
 846         if (vector == -1)
 847                 return vector;
 848
 849         apic_clear_isr(vector, apic);
 850         apic_update_ppr(apic);
 851
 852         kvm_ioapic_send_eoi(apic, vector);
 853         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 854         return vector;
 855 }
 856
 857 /*
 858  * this interface assumes a trap-like exit, which has already finished
 859  * desired side effect including vISR and vPPR update.
 860  */
 861 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
 862 {
 863         struct kvm_lapic *apic = vcpu->arch.apic;
 864
 865         trace_kvm_eoi(apic, vector);
 866
 867         kvm_ioapic_send_eoi(apic, vector);
 868         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 869 }
 870 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
 871
 872 static void apic_send_ipi(struct kvm_lapic *apic)
 873 {
 874         u32 icr_low = kvm_apic_get_reg(apic, APIC_ICR);
 875         u32 icr_high = kvm_apic_get_reg(apic, APIC_ICR2);
 876         struct kvm_lapic_irq irq;
 877
 878         irq.vector = icr_low & APIC_VECTOR_MASK;
 879         irq.delivery_mode = icr_low & APIC_MODE_MASK;
 880         irq.dest_mode = icr_low & APIC_DEST_MASK;
 881         irq.level = icr_low & APIC_INT_ASSERT;
 882         irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
 883         irq.shorthand = icr_low & APIC_SHORT_MASK;
 884         if (apic_x2apic_mode(apic))
 885                 irq.dest_id = icr_high;
 886         else
 887                 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
 888
 889         trace_kvm_apic_ipi(icr_low, irq.dest_id);
 890
 891         apic_debug("icr_high 0x%x, icr_low 0x%x, "
 892                    "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
 893                    "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
 894                    icr_high, icr_low, irq.shorthand, irq.dest_id,
 895                    irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
 896                    irq.vector);
 897
 898         kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
 899 }
 900
 901 static u32 apic_get_tmcct(struct kvm_lapic *apic)
 902 {
 903         ktime_t remaining;
 904         s64 ns;
 905         u32 tmcct;
 906
 907         ASSERT(apic != NULL);
 908
 909         /* if initial count is 0, current count should also be 0 */
 910         if (kvm_apic_get_reg(apic, APIC_TMICT) == 0 ||
 911                 apic->lapic_timer.period == 0)
 912                 return 0;
 913
 914         remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
 915         if (ktime_to_ns(remaining) < 0)
 916                 remaining = ktime_set(0, 0);
 917
 918         ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
 919         tmcct = div64_u64(ns,
 920                          (APIC_BUS_CYCLE_NS * apic->divide_count));
 921
 922         return tmcct;
 923 }
 924
 925 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
 926 {
 927         struct kvm_vcpu *vcpu = apic->vcpu;
 928         struct kvm_run *run = vcpu->run;
 929
 930         kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
 931         run->tpr_access.rip = kvm_rip_read(vcpu);
 932         run->tpr_access.is_write = write;
 933 }
 934
 935 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
 936 {
 937         if (apic->vcpu->arch.tpr_access_reporting)
 938                 __report_tpr_access(apic, write);
 939 }
 940
 941 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
 942 {
 943         u32 val = 0;
 944
 945         if (offset >= LAPIC_MMIO_LENGTH)
 946                 return 0;
 947
 948         switch (offset) {
 949         case APIC_ID:
 950                 if (apic_x2apic_mode(apic))
 951                         val = kvm_apic_id(apic);
 952                 else
 953                         val = kvm_apic_id(apic) << 24;
 954                 break;
 955         case APIC_ARBPRI:
 956                 apic_debug("Access APIC ARBPRI register which is for P6\n");
 957                 break;
 958
 959         case APIC_TMCCT:        /* Timer CCR */
 960                 if (apic_lvtt_tscdeadline(apic))
 961                         return 0;
 962
 963                 val = apic_get_tmcct(apic);
 964                 break;
 965         case APIC_PROCPRI:
 966                 apic_update_ppr(apic);
 967                 val = kvm_apic_get_reg(apic, offset);
 968                 break;
 969         case APIC_TASKPRI:
 970                 report_tpr_access(apic, false);
 971                 /* fall thru */
 972         default:
 973                 val = kvm_apic_get_reg(apic, offset);
 974                 break;
 975         }
 976
 977         return val;
 978 }
 979
 980 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
 981 {
 982         return container_of(dev, struct kvm_lapic, dev);
 983 }
 984
 985 static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
 986                 void *data)
 987 {
 988         unsigned char alignment = offset & 0xf;
 989         u32 result;
 990         /* this bitmask has a bit cleared for each reserved register */
 991         static const u64 rmask = 0x43ff01ffffffe70cULL;
 992
 993         if ((alignment + len) > 4) {
 994                 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
 995                            offset, len);
 996                 return 1;
 997         }
 998
 999         if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
1000                 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1001                            offset);
1002                 return 1;
1003         }
1004
1005         result = __apic_read(apic, offset & ~0xf);
1006
1007         trace_kvm_apic_read(offset, result);
1008
1009         switch (len) {
1010         case 1:
1011         case 2:
1012         case 4:
1013                 memcpy(data, (char *)&result + alignment, len);
1014                 break;
1015         default:
1016                 printk(KERN_ERR "Local APIC read with len = %x, "
1017                        "should be 1,2, or 4 instead\n", len);
1018                 break;
1019         }
1020         return 0;
1021 }
1022
1023 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1024 {
1025         return kvm_apic_hw_enabled(apic) &&
1026             addr >= apic->base_address &&
1027             addr < apic->base_address + LAPIC_MMIO_LENGTH;
1028 }
1029
1030 static int apic_mmio_read(struct kvm_io_device *this,
1031                            gpa_t address, int len, void *data)
1032 {
1033         struct kvm_lapic *apic = to_lapic(this);
1034         u32 offset = address - apic->base_address;
1035
1036         if (!apic_mmio_in_range(apic, address))
1037                 return -EOPNOTSUPP;
1038
1039         apic_reg_read(apic, offset, len, data);
1040
1041         return 0;
1042 }
1043
1044 static void update_divide_count(struct kvm_lapic *apic)
1045 {
1046         u32 tmp1, tmp2, tdcr;
1047
1048         tdcr = kvm_apic_get_reg(apic, APIC_TDCR);
1049         tmp1 = tdcr & 0xf;
1050         tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
1051         apic->divide_count = 0x1 << (tmp2 & 0x7);
1052
1053         apic_debug("timer divide count is 0x%x\n",
1054                                    apic->divide_count);
1055 }
1056
1057 static void apic_timer_expired(struct kvm_lapic *apic)
1058 {
1059         struct kvm_vcpu *vcpu = apic->vcpu;
1060         wait_queue_head_t *q = &vcpu->wq;
1061         struct kvm_timer *ktimer = &apic->lapic_timer;
1062
1063         if (atomic_read(&apic->lapic_timer.pending))
1064                 return;
1065
1066         atomic_inc(&apic->lapic_timer.pending);
1067         kvm_set_pending_timer(vcpu);
1068
1069         if (waitqueue_active(q))
1070                 wake_up_interruptible(q);
1071
1072         if (apic_lvtt_tscdeadline(apic))
1073                 ktimer->expired_tscdeadline = ktimer->tscdeadline;
1074 }
1075
1076 /*
1077  * On APICv, this test will cause a busy wait
1078  * during a higher-priority task.
1079  */
1080
1081 static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu)
1082 {
1083         struct kvm_lapic *apic = vcpu->arch.apic;
1084         u32 reg = kvm_apic_get_reg(apic, APIC_LVTT);
1085
1086         if (kvm_apic_hw_enabled(apic)) {
1087                 int vec = reg & APIC_VECTOR_MASK;
1088
1089                 if (kvm_x86_ops->test_posted_interrupt)
1090                         return kvm_x86_ops->test_posted_interrupt(vcpu, vec);
1091                 else {
1092                         if (apic_test_vector(vec, apic->regs + APIC_ISR))
1093                                 return true;
1094                 }
1095         }
1096         return false;
1097 }
1098
1099 void wait_lapic_expire(struct kvm_vcpu *vcpu)
1100 {
1101         struct kvm_lapic *apic = vcpu->arch.apic;
1102         u64 guest_tsc, tsc_deadline;
1103
1104         if (!kvm_vcpu_has_lapic(vcpu))
1105                 return;
1106
1107         if (apic->lapic_timer.expired_tscdeadline == 0)
1108                 return;
1109
1110         if (!lapic_timer_int_injected(vcpu))
1111                 return;
1112
1113         tsc_deadline = apic->lapic_timer.expired_tscdeadline;
1114         apic->lapic_timer.expired_tscdeadline = 0;
1115         guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc());
1116         trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline);
1117
1118         /* __delay is delay_tsc whenever the hardware has TSC, thus always.  */
1119         if (guest_tsc < tsc_deadline)
1120                 __delay(tsc_deadline - guest_tsc);
1121 }
1122
1123 static void start_apic_timer(struct kvm_lapic *apic)
1124 {
1125         ktime_t now;
1126
1127         atomic_set(&apic->lapic_timer.pending, 0);
1128
1129         if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
1130                 /* lapic timer in oneshot or periodic mode */
1131                 now = apic->lapic_timer.timer.base->get_time();
1132                 apic->lapic_timer.period = (u64)kvm_apic_get_reg(apic, APIC_TMICT)
1133                             * APIC_BUS_CYCLE_NS * apic->divide_count;
1134
1135                 if (!apic->lapic_timer.period)
1136                         return;
1137                 /*
1138                  * Do not allow the guest to program periodic timers with small
1139                  * interval, since the hrtimers are not throttled by the host
1140                  * scheduler.
1141                  */
1142                 if (apic_lvtt_period(apic)) {
1143                         s64 min_period = min_timer_period_us * 1000LL;
1144
1145                         if (apic->lapic_timer.period < min_period) {
1146                                 pr_info_ratelimited(
1147                                     "kvm: vcpu %i: requested %lld ns "
1148                                     "lapic timer period limited to %lld ns\n",
1149                                     apic->vcpu->vcpu_id,
1150                                     apic->lapic_timer.period, min_period);
1151                                 apic->lapic_timer.period = min_period;
1152                         }
1153                 }
1154
1155                 hrtimer_start(&apic->lapic_timer.timer,
1156                               ktime_add_ns(now, apic->lapic_timer.period),
1157                               HRTIMER_MODE_ABS);
1158
1159                 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
1160                            PRIx64 ", "
1161                            "timer initial count 0x%x, period %lldns, "
1162                            "expire @ 0x%016" PRIx64 ".\n", __func__,
1163                            APIC_BUS_CYCLE_NS, ktime_to_ns(now),
1164                            kvm_apic_get_reg(apic, APIC_TMICT),
1165                            apic->lapic_timer.period,
1166                            ktime_to_ns(ktime_add_ns(now,
1167                                         apic->lapic_timer.period)));
1168         } else if (apic_lvtt_tscdeadline(apic)) {
1169                 /* lapic timer in tsc deadline mode */
1170                 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1171                 u64 ns = 0;
1172                 ktime_t expire;
1173                 struct kvm_vcpu *vcpu = apic->vcpu;
1174                 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1175                 unsigned long flags;
1176
1177                 if (unlikely(!tscdeadline || !this_tsc_khz))
1178                         return;
1179
1180                 local_irq_save(flags);
1181
1182                 now = apic->lapic_timer.timer.base->get_time();
1183                 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc());
1184                 if (likely(tscdeadline > guest_tsc)) {
1185                         ns = (tscdeadline - guest_tsc) * 1000000ULL;
1186                         do_div(ns, this_tsc_khz);
1187                         expire = ktime_add_ns(now, ns);
1188                         expire = ktime_sub_ns(expire, lapic_timer_advance_ns);
1189                         hrtimer_start(&apic->lapic_timer.timer,
1190                                       expire, HRTIMER_MODE_ABS);
1191                 } else
1192                         apic_timer_expired(apic);
1193
1194                 local_irq_restore(flags);
1195         }
1196 }
1197
1198 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1199 {
1200         int nmi_wd_enabled = apic_lvt_nmi_mode(kvm_apic_get_reg(apic, APIC_LVT0));
1201
1202         if (apic_lvt_nmi_mode(lvt0_val)) {
1203                 if (!nmi_wd_enabled) {
1204                         apic_debug("Receive NMI setting on APIC_LVT0 "
1205                                    "for cpu %d\n", apic->vcpu->vcpu_id);
1206                         apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
1207                 }
1208         } else if (nmi_wd_enabled)
1209                 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
1210 }
1211
1212 static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
1213 {
1214         int ret = 0;
1215
1216         trace_kvm_apic_write(reg, val);
1217
1218         switch (reg) {
1219         case APIC_ID:           /* Local APIC ID */
1220                 if (!apic_x2apic_mode(apic))
1221                         kvm_apic_set_id(apic, val >> 24);
1222                 else
1223                         ret = 1;
1224                 break;
1225
1226         case APIC_TASKPRI:
1227                 report_tpr_access(apic, true);
1228                 apic_set_tpr(apic, val & 0xff);
1229                 break;
1230
1231         case APIC_EOI:
1232                 apic_set_eoi(apic);
1233                 break;
1234
1235         case APIC_LDR:
1236                 if (!apic_x2apic_mode(apic))
1237                         kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
1238                 else
1239                         ret = 1;
1240                 break;
1241
1242         case APIC_DFR:
1243                 if (!apic_x2apic_mode(apic)) {
1244                         apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1245                         recalculate_apic_map(apic->vcpu->kvm);
1246                 } else
1247                         ret = 1;
1248                 break;
1249
1250         case APIC_SPIV: {
1251                 u32 mask = 0x3ff;
1252                 if (kvm_apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
1253                         mask |= APIC_SPIV_DIRECTED_EOI;
1254                 apic_set_spiv(apic, val & mask);
1255                 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1256                         int i;
1257                         u32 lvt_val;
1258
1259                         for (i = 0; i < APIC_LVT_NUM; i++) {
1260                                 lvt_val = kvm_apic_get_reg(apic,
1261                                                        APIC_LVTT + 0x10 * i);
1262                                 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
1263                                              lvt_val | APIC_LVT_MASKED);
1264                         }
1265                         atomic_set(&apic->lapic_timer.pending, 0);
1266
1267                 }
1268                 break;
1269         }
1270         case APIC_ICR:
1271                 /* No delay here, so we always clear the pending bit */
1272                 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1273                 apic_send_ipi(apic);
1274                 break;
1275
1276         case APIC_ICR2:
1277                 if (!apic_x2apic_mode(apic))
1278                         val &= 0xff000000;
1279                 apic_set_reg(apic, APIC_ICR2, val);
1280                 break;
1281
1282         case APIC_LVT0:
1283                 apic_manage_nmi_watchdog(apic, val);
1284         case APIC_LVTTHMR:
1285         case APIC_LVTPC:
1286         case APIC_LVT1:
1287         case APIC_LVTERR:
1288                 /* TODO: Check vector */
1289                 if (!kvm_apic_sw_enabled(apic))
1290                         val |= APIC_LVT_MASKED;
1291
1292                 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1293                 apic_set_reg(apic, reg, val);
1294
1295                 break;
1296
1297         case APIC_LVTT: {
1298                 u32 timer_mode = val & apic->lapic_timer.timer_mode_mask;
1299
1300                 if (apic->lapic_timer.timer_mode != timer_mode) {
1301                         apic->lapic_timer.timer_mode = timer_mode;
1302                         hrtimer_cancel(&apic->lapic_timer.timer);
1303                 }
1304
1305                 if (!kvm_apic_sw_enabled(apic))
1306                         val |= APIC_LVT_MASKED;
1307                 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1308                 apic_set_reg(apic, APIC_LVTT, val);
1309                 break;
1310         }
1311
1312         case APIC_TMICT:
1313                 if (apic_lvtt_tscdeadline(apic))
1314                         break;
1315
1316                 hrtimer_cancel(&apic->lapic_timer.timer);
1317                 apic_set_reg(apic, APIC_TMICT, val);
1318                 start_apic_timer(apic);
1319                 break;
1320
1321         case APIC_TDCR:
1322                 if (val & 4)
1323                         apic_debug("KVM_WRITE:TDCR %x\n", val);
1324                 apic_set_reg(apic, APIC_TDCR, val);
1325                 update_divide_count(apic);
1326                 break;
1327
1328         case APIC_ESR:
1329                 if (apic_x2apic_mode(apic) && val != 0) {
1330                         apic_debug("KVM_WRITE:ESR not zero %x\n", val);
1331                         ret = 1;
1332                 }
1333                 break;
1334
1335         case APIC_SELF_IPI:
1336                 if (apic_x2apic_mode(apic)) {
1337                         apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1338                 } else
1339                         ret = 1;
1340                 break;
1341         default:
1342                 ret = 1;
1343                 break;
1344         }
1345         if (ret)
1346                 apic_debug("Local APIC Write to read-only register %x\n", reg);
1347         return ret;
1348 }
1349
1350 static int apic_mmio_write(struct kvm_io_device *this,
1351                             gpa_t address, int len, const void *data)
1352 {
1353         struct kvm_lapic *apic = to_lapic(this);
1354         unsigned int offset = address - apic->base_address;
1355         u32 val;
1356
1357         if (!apic_mmio_in_range(apic, address))
1358                 return -EOPNOTSUPP;
1359
1360         /*
1361          * APIC register must be aligned on 128-bits boundary.
1362          * 32/64/128 bits registers must be accessed thru 32 bits.
1363          * Refer SDM 8.4.1
1364          */
1365         if (len != 4 || (offset & 0xf)) {
1366                 /* Don't shout loud, $infamous_os would cause only noise. */
1367                 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
1368                 return 0;
1369         }
1370
1371         val = *(u32*)data;
1372
1373         /* too common printing */
1374         if (offset != APIC_EOI)
1375                 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1376                            "0x%x\n", __func__, offset, len, val);
1377
1378         apic_reg_write(apic, offset & 0xff0, val);
1379
1380         return 0;
1381 }
1382
1383 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1384 {
1385         if (kvm_vcpu_has_lapic(vcpu))
1386                 apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1387 }
1388 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1389
1390 /* emulate APIC access in a trap manner */
1391 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1392 {
1393         u32 val = 0;
1394
1395         /* hw has done the conditional check and inst decode */
1396         offset &= 0xff0;
1397
1398         apic_reg_read(vcpu->arch.apic, offset, 4, &val);
1399
1400         /* TODO: optimize to just emulate side effect w/o one more write */
1401         apic_reg_write(vcpu->arch.apic, offset, val);
1402 }
1403 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
1404
1405 void kvm_free_lapic(struct kvm_vcpu *vcpu)
1406 {
1407         struct kvm_lapic *apic = vcpu->arch.apic;
1408
1409         if (!vcpu->arch.apic)
1410                 return;
1411
1412         hrtimer_cancel(&apic->lapic_timer.timer);
1413
1414         if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1415                 static_key_slow_dec_deferred(&apic_hw_disabled);
1416
1417         if (!apic->sw_enabled)
1418                 static_key_slow_dec_deferred(&apic_sw_disabled);
1419
1420         if (apic->regs)
1421                 free_page((unsigned long)apic->regs);
1422
1423         kfree(apic);
1424 }
1425
1426 /*
1427  *----------------------------------------------------------------------
1428  * LAPIC interface
1429  *----------------------------------------------------------------------
1430  */
1431
1432 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1433 {
1434         struct kvm_lapic *apic = vcpu->arch.apic;
1435
1436         if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1437                         apic_lvtt_period(apic))
1438                 return 0;
1439
1440         return apic->lapic_timer.tscdeadline;
1441 }
1442
1443 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1444 {
1445         struct kvm_lapic *apic = vcpu->arch.apic;
1446
1447         if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1448                         apic_lvtt_period(apic))
1449                 return;
1450
1451         hrtimer_cancel(&apic->lapic_timer.timer);
1452         apic->lapic_timer.tscdeadline = data;
1453         start_apic_timer(apic);
1454 }
1455
1456 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1457 {
1458         struct kvm_lapic *apic = vcpu->arch.apic;
1459
1460         if (!kvm_vcpu_has_lapic(vcpu))
1461                 return;
1462
1463         apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
1464                      | (kvm_apic_get_reg(apic, APIC_TASKPRI) & 4));
1465 }
1466
1467 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1468 {
1469         u64 tpr;
1470
1471         if (!kvm_vcpu_has_lapic(vcpu))
1472                 return 0;
1473
1474         tpr = (u64) kvm_apic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
1475
1476         return (tpr & 0xf0) >> 4;
1477 }
1478
1479 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1480 {
1481         u64 old_value = vcpu->arch.apic_base;
1482         struct kvm_lapic *apic = vcpu->arch.apic;
1483
1484         if (!apic) {
1485                 value |= MSR_IA32_APICBASE_BSP;
1486                 vcpu->arch.apic_base = value;
1487                 return;
1488         }
1489
1490         if (!kvm_vcpu_is_bsp(apic->vcpu))
1491                 value &= ~MSR_IA32_APICBASE_BSP;
1492         vcpu->arch.apic_base = value;
1493
1494         /* update jump label if enable bit changes */
1495         if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
1496                 if (value & MSR_IA32_APICBASE_ENABLE)
1497                         static_key_slow_dec_deferred(&apic_hw_disabled);
1498                 else
1499                         static_key_slow_inc(&apic_hw_disabled.key);
1500                 recalculate_apic_map(vcpu->kvm);
1501         }
1502
1503         if ((old_value ^ value) & X2APIC_ENABLE) {
1504                 if (value & X2APIC_ENABLE) {
1505                         u32 id = kvm_apic_id(apic);
1506                         u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
1507                         kvm_apic_set_ldr(apic, ldr);
1508                         kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
1509                 } else
1510                         kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
1511         }
1512
1513         apic->base_address = apic->vcpu->arch.apic_base &
1514                              MSR_IA32_APICBASE_BASE;
1515
1516         if ((value & MSR_IA32_APICBASE_ENABLE) &&
1517              apic->base_address != APIC_DEFAULT_PHYS_BASE)
1518                 pr_warn_once("APIC base relocation is unsupported by KVM");
1519
1520         /* with FSB delivery interrupt, we can restart APIC functionality */
1521         apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
1522                    "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
1523
1524 }
1525
1526 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
1527 {
1528         struct kvm_lapic *apic;
1529         int i;
1530
1531         apic_debug("%s\n", __func__);
1532
1533         ASSERT(vcpu);
1534         apic = vcpu->arch.apic;
1535         ASSERT(apic != NULL);
1536
1537         /* Stop the timer in case it's a reset to an active apic */
1538         hrtimer_cancel(&apic->lapic_timer.timer);
1539
1540         kvm_apic_set_id(apic, vcpu->vcpu_id);
1541         kvm_apic_set_version(apic->vcpu);
1542
1543         for (i = 0; i < APIC_LVT_NUM; i++)
1544                 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
1545         apic->lapic_timer.timer_mode = 0;
1546         apic_set_reg(apic, APIC_LVT0,
1547                      SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
1548
1549         apic_set_reg(apic, APIC_DFR, 0xffffffffU);
1550         apic_set_spiv(apic, 0xff);
1551         apic_set_reg(apic, APIC_TASKPRI, 0);
1552         kvm_apic_set_ldr(apic, 0);
1553         apic_set_reg(apic, APIC_ESR, 0);
1554         apic_set_reg(apic, APIC_ICR, 0);
1555         apic_set_reg(apic, APIC_ICR2, 0);
1556         apic_set_reg(apic, APIC_TDCR, 0);
1557         apic_set_reg(apic, APIC_TMICT, 0);
1558         for (i = 0; i < 8; i++) {
1559                 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1560                 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1561                 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1562         }
1563         apic->irr_pending = kvm_apic_vid_enabled(vcpu->kvm);
1564         apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm);
1565         apic->highest_isr_cache = -1;
1566         update_divide_count(apic);
1567         atomic_set(&apic->lapic_timer.pending, 0);
1568         if (kvm_vcpu_is_bsp(vcpu))
1569                 kvm_lapic_set_base(vcpu,
1570                                 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
1571         vcpu->arch.pv_eoi.msr_val = 0;
1572         apic_update_ppr(apic);
1573
1574         vcpu->arch.apic_arb_prio = 0;
1575         vcpu->arch.apic_attention = 0;
1576
1577         apic_debug("%s: vcpu=%p, id=%d, base_msr="
1578                    "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
1579                    vcpu, kvm_apic_id(apic),
1580                    vcpu->arch.apic_base, apic->base_address);
1581 }
1582
1583 /*
1584  *----------------------------------------------------------------------
1585  * timer interface
1586  *----------------------------------------------------------------------
1587  */
1588
1589 static bool lapic_is_periodic(struct kvm_lapic *apic)
1590 {
1591         return apic_lvtt_period(apic);
1592 }
1593
1594 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1595 {
1596         struct kvm_lapic *apic = vcpu->arch.apic;
1597
1598         if (kvm_vcpu_has_lapic(vcpu) && apic_enabled(apic) &&
1599                         apic_lvt_enabled(apic, APIC_LVTT))
1600                 return atomic_read(&apic->lapic_timer.pending);
1601
1602         return 0;
1603 }
1604
1605 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1606 {
1607         u32 reg = kvm_apic_get_reg(apic, lvt_type);
1608         int vector, mode, trig_mode;
1609
1610         if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
1611                 vector = reg & APIC_VECTOR_MASK;
1612                 mode = reg & APIC_MODE_MASK;
1613                 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1614                 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
1615                                         NULL);
1616         }
1617         return 0;
1618 }
1619
1620 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
1621 {
1622         struct kvm_lapic *apic = vcpu->arch.apic;
1623
1624         if (apic)
1625                 kvm_apic_local_deliver(apic, APIC_LVT0);
1626 }
1627
1628 static const struct kvm_io_device_ops apic_mmio_ops = {
1629         .read     = apic_mmio_read,
1630         .write    = apic_mmio_write,
1631 };
1632
1633 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
1634 {
1635         struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
1636         struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
1637
1638         apic_timer_expired(apic);
1639
1640         if (lapic_is_periodic(apic)) {
1641                 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
1642                 return HRTIMER_RESTART;
1643         } else
1644                 return HRTIMER_NORESTART;
1645 }
1646
1647 int kvm_create_lapic(struct kvm_vcpu *vcpu)
1648 {
1649         struct kvm_lapic *apic;
1650
1651         ASSERT(vcpu != NULL);
1652         apic_debug("apic_init %d\n", vcpu->vcpu_id);
1653
1654         apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1655         if (!apic)
1656                 goto nomem;
1657
1658         vcpu->arch.apic = apic;
1659
1660         apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1661         if (!apic->regs) {
1662                 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1663                        vcpu->vcpu_id);
1664                 goto nomem_free_apic;
1665         }
1666         apic->vcpu = vcpu;
1667
1668         hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1669                      HRTIMER_MODE_ABS);
1670         apic->lapic_timer.timer.function = apic_timer_fn;
1671
1672         /*
1673          * APIC is created enabled. This will prevent kvm_lapic_set_base from
1674          * thinking that APIC satet has changed.
1675          */
1676         vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
1677         kvm_lapic_set_base(vcpu,
1678                         APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE);
1679
1680         static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
1681         kvm_lapic_reset(vcpu);
1682         kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
1683
1684         return 0;
1685 nomem_free_apic:
1686         kfree(apic);
1687 nomem:
1688         return -ENOMEM;
1689 }
1690
1691 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1692 {
1693         struct kvm_lapic *apic = vcpu->arch.apic;
1694         int highest_irr;
1695
1696         if (!kvm_vcpu_has_lapic(vcpu) || !apic_enabled(apic))
1697                 return -1;
1698
1699         apic_update_ppr(apic);
1700         highest_irr = apic_find_highest_irr(apic);
1701         if ((highest_irr == -1) ||
1702             ((highest_irr & 0xF0) <= kvm_apic_get_reg(apic, APIC_PROCPRI)))
1703                 return -1;
1704         return highest_irr;
1705 }
1706
1707 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1708 {
1709         u32 lvt0 = kvm_apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1710         int r = 0;
1711
1712         if (!kvm_apic_hw_enabled(vcpu->arch.apic))
1713                 r = 1;
1714         if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1715             GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1716                 r = 1;
1717         return r;
1718 }
1719
1720 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1721 {
1722         struct kvm_lapic *apic = vcpu->arch.apic;
1723
1724         if (!kvm_vcpu_has_lapic(vcpu))
1725                 return;
1726
1727         if (atomic_read(&apic->lapic_timer.pending) > 0) {
1728                 kvm_apic_local_deliver(apic, APIC_LVTT);
1729                 if (apic_lvtt_tscdeadline(apic))
1730                         apic->lapic_timer.tscdeadline = 0;
1731                 atomic_set(&apic->lapic_timer.pending, 0);
1732         }
1733 }
1734
1735 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1736 {
1737         int vector = kvm_apic_has_interrupt(vcpu);
1738         struct kvm_lapic *apic = vcpu->arch.apic;
1739
1740         if (vector == -1)
1741                 return -1;
1742
1743         /*
1744          * We get here even with APIC virtualization enabled, if doing
1745          * nested virtualization and L1 runs with the "acknowledge interrupt
1746          * on exit" mode.  Then we cannot inject the interrupt via RVI,
1747          * because the process would deliver it through the IDT.
1748          */
1749
1750         apic_set_isr(vector, apic);
1751         apic_update_ppr(apic);
1752         apic_clear_irr(vector, apic);
1753         return vector;
1754 }
1755
1756 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
1757                 struct kvm_lapic_state *s)
1758 {
1759         struct kvm_lapic *apic = vcpu->arch.apic;
1760
1761         kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
1762         /* set SPIV separately to get count of SW disabled APICs right */
1763         apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
1764         memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
1765         /* call kvm_apic_set_id() to put apic into apic_map */
1766         kvm_apic_set_id(apic, kvm_apic_id(apic));
1767         kvm_apic_set_version(vcpu);
1768
1769         apic_update_ppr(apic);
1770         hrtimer_cancel(&apic->lapic_timer.timer);
1771         update_divide_count(apic);
1772         start_apic_timer(apic);
1773         apic->irr_pending = true;
1774         apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm) ?
1775                                 1 : count_vectors(apic->regs + APIC_ISR);
1776         apic->highest_isr_cache = -1;
1777         if (kvm_x86_ops->hwapic_irr_update)
1778                 kvm_x86_ops->hwapic_irr_update(vcpu,
1779                                 apic_find_highest_irr(apic));
1780         if (unlikely(kvm_x86_ops->hwapic_isr_update))
1781                 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
1782                                 apic_find_highest_isr(apic));
1783         kvm_make_request(KVM_REQ_EVENT, vcpu);
1784         kvm_rtc_eoi_tracking_restore_one(vcpu);
1785 }
1786
1787 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1788 {
1789         struct hrtimer *timer;
1790
1791         if (!kvm_vcpu_has_lapic(vcpu))
1792                 return;
1793
1794         timer = &vcpu->arch.apic->lapic_timer.timer;
1795         if (hrtimer_cancel(timer))
1796                 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1797 }
1798
1799 /*
1800  * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
1801  *
1802  * Detect whether guest triggered PV EOI since the
1803  * last entry. If yes, set EOI on guests's behalf.
1804  * Clear PV EOI in guest memory in any case.
1805  */
1806 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
1807                                         struct kvm_lapic *apic)
1808 {
1809         bool pending;
1810         int vector;
1811         /*
1812          * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
1813          * and KVM_PV_EOI_ENABLED in guest memory as follows:
1814          *
1815          * KVM_APIC_PV_EOI_PENDING is unset:
1816          *      -> host disabled PV EOI.
1817          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
1818          *      -> host enabled PV EOI, guest did not execute EOI yet.
1819          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
1820          *      -> host enabled PV EOI, guest executed EOI.
1821          */
1822         BUG_ON(!pv_eoi_enabled(vcpu));
1823         pending = pv_eoi_get_pending(vcpu);
1824         /*
1825          * Clear pending bit in any case: it will be set again on vmentry.
1826          * While this might not be ideal from performance point of view,
1827          * this makes sure pv eoi is only enabled when we know it's safe.
1828          */
1829         pv_eoi_clr_pending(vcpu);
1830         if (pending)
1831                 return;
1832         vector = apic_set_eoi(apic);
1833         trace_kvm_pv_eoi(apic, vector);
1834 }
1835
1836 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1837 {
1838         u32 data;
1839
1840         if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
1841                 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
1842
1843         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1844                 return;
1845
1846         kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1847                                 sizeof(u32));
1848
1849         apic_set_tpr(vcpu->arch.apic, data & 0xff);
1850 }
1851
1852 /*
1853  * apic_sync_pv_eoi_to_guest - called before vmentry
1854  *
1855  * Detect whether it's safe to enable PV EOI and
1856  * if yes do so.
1857  */
1858 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
1859                                         struct kvm_lapic *apic)
1860 {
1861         if (!pv_eoi_enabled(vcpu) ||
1862             /* IRR set or many bits in ISR: could be nested. */
1863             apic->irr_pending ||
1864             /* Cache not set: could be safe but we don't bother. */
1865             apic->highest_isr_cache == -1 ||
1866             /* Need EOI to update ioapic. */
1867             kvm_ioapic_handles_vector(vcpu->kvm, apic->highest_isr_cache)) {
1868                 /*
1869                  * PV EOI was disabled by apic_sync_pv_eoi_from_guest
1870                  * so we need not do anything here.
1871                  */
1872                 return;
1873         }
1874
1875         pv_eoi_set_pending(apic->vcpu);
1876 }
1877
1878 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1879 {
1880         u32 data, tpr;
1881         int max_irr, max_isr;
1882         struct kvm_lapic *apic = vcpu->arch.apic;
1883
1884         apic_sync_pv_eoi_to_guest(vcpu, apic);
1885
1886         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1887                 return;
1888
1889         tpr = kvm_apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1890         max_irr = apic_find_highest_irr(apic);
1891         if (max_irr < 0)
1892                 max_irr = 0;
1893         max_isr = apic_find_highest_isr(apic);
1894         if (max_isr < 0)
1895                 max_isr = 0;
1896         data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1897
1898         kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1899                                 sizeof(u32));
1900 }
1901
1902 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1903 {
1904         if (vapic_addr) {
1905                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
1906                                         &vcpu->arch.apic->vapic_cache,
1907                                         vapic_addr, sizeof(u32)))
1908                         return -EINVAL;
1909                 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1910         } else {
1911                 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1912         }
1913
1914         vcpu->arch.apic->vapic_addr = vapic_addr;
1915         return 0;
1916 }
1917
1918 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1919 {
1920         struct kvm_lapic *apic = vcpu->arch.apic;
1921         u32 reg = (msr - APIC_BASE_MSR) << 4;
1922
1923         if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1924                 return 1;
1925
1926         if (reg == APIC_ICR2)
1927                 return 1;
1928
1929         /* if this is ICR write vector before command */
1930         if (reg == APIC_ICR)
1931                 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1932         return apic_reg_write(apic, reg, (u32)data);
1933 }
1934
1935 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
1936 {
1937         struct kvm_lapic *apic = vcpu->arch.apic;
1938         u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
1939
1940         if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1941                 return 1;
1942
1943         if (reg == APIC_DFR || reg == APIC_ICR2) {
1944                 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
1945                            reg);
1946                 return 1;
1947         }
1948
1949         if (apic_reg_read(apic, reg, 4, &low))
1950                 return 1;
1951         if (reg == APIC_ICR)
1952                 apic_reg_read(apic, APIC_ICR2, 4, &high);
1953
1954         *data = (((u64)high) << 32) | low;
1955
1956         return 0;
1957 }
1958
1959 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
1960 {
1961         struct kvm_lapic *apic = vcpu->arch.apic;
1962
1963         if (!kvm_vcpu_has_lapic(vcpu))
1964                 return 1;
1965
1966         /* if this is ICR write vector before command */
1967         if (reg == APIC_ICR)
1968                 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1969         return apic_reg_write(apic, reg, (u32)data);
1970 }
1971
1972 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
1973 {
1974         struct kvm_lapic *apic = vcpu->arch.apic;
1975         u32 low, high = 0;
1976
1977         if (!kvm_vcpu_has_lapic(vcpu))
1978                 return 1;
1979
1980         if (apic_reg_read(apic, reg, 4, &low))
1981                 return 1;
1982         if (reg == APIC_ICR)
1983                 apic_reg_read(apic, APIC_ICR2, 4, &high);
1984
1985         *data = (((u64)high) << 32) | low;
1986
1987         return 0;
1988 }
1989
1990 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
1991 {
1992         u64 addr = data & ~KVM_MSR_ENABLED;
1993         if (!IS_ALIGNED(addr, 4))
1994                 return 1;
1995
1996         vcpu->arch.pv_eoi.msr_val = data;
1997         if (!pv_eoi_enabled(vcpu))
1998                 return 0;
1999         return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
2000                                          addr, sizeof(u8));
2001 }
2002
2003 void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
2004 {
2005         struct kvm_lapic *apic = vcpu->arch.apic;
2006         u8 sipi_vector;
2007         unsigned long pe;
2008
2009         if (!kvm_vcpu_has_lapic(vcpu) || !apic->pending_events)
2010                 return;
2011
2012         pe = xchg(&apic->pending_events, 0);
2013
2014         if (test_bit(KVM_APIC_INIT, &pe)) {
2015                 kvm_lapic_reset(vcpu);
2016                 kvm_vcpu_reset(vcpu);
2017                 if (kvm_vcpu_is_bsp(apic->vcpu))
2018                         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2019                 else
2020                         vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
2021         }
2022         if (test_bit(KVM_APIC_SIPI, &pe) &&
2023             vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
2024                 /* evaluate pending_events before reading the vector */
2025                 smp_rmb();
2026                 sipi_vector = apic->sipi_vector;
2027                 apic_debug("vcpu %d received sipi with vector # %x\n",
2028                          vcpu->vcpu_id, sipi_vector);
2029                 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
2030                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2031         }
2032 }
2033
2034 void kvm_lapic_init(void)
2035 {
2036         /* do not patch jump label more than once per second */
2037         jump_label_rate_limit(&apic_hw_disabled, HZ);
2038         jump_label_rate_limit(&apic_sw_disabled, HZ);
2039 }