arch/x86/kvm/lapic.c

   1
   2 /*
   3  * Local APIC virtualization
   4  *
   5  * Copyright (C) 2006 Qumranet, Inc.
   6  * Copyright (C) 2007 Novell
   7  * Copyright (C) 2007 Intel
   8  * Copyright 2009 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Dor Laor <dor.laor@qumranet.com>
  12  *   Gregory Haskins <ghaskins@novell.com>
  13  *   Yaozu (Eddie) Dong <eddie.dong@intel.com>
  14  *
  15  * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
  16  *
  17  * This work is licensed under the terms of the GNU GPL, version 2.  See
  18  * the COPYING file in the top-level directory.
  19  */
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/kvm.h>
  23 #include <linux/mm.h>
  24 #include <linux/highmem.h>
  25 #include <linux/smp.h>
  26 #include <linux/hrtimer.h>
  27 #include <linux/io.h>
  28 #include <linux/module.h>
  29 #include <linux/math64.h>
  30 #include <linux/slab.h>
  31 #include <asm/processor.h>
  32 #include <asm/msr.h>
  33 #include <asm/page.h>
  34 #include <asm/current.h>
  35 #include <asm/apicdef.h>
  36 #include <linux/atomic.h>
  37 #include <linux/jump_label.h>
  38 #include "kvm_cache_regs.h"
  39 #include "irq.h"
  40 #include "trace.h"
  41 #include "x86.h"
  42 #include "cpuid.h"
  43
  44 #ifndef CONFIG_X86_64
  45 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
  46 #else
  47 #define mod_64(x, y) ((x) % (y))
  48 #endif
  49
  50 #define PRId64 "d"
  51 #define PRIx64 "llx"
  52 #define PRIu64 "u"
  53 #define PRIo64 "o"
  54
  55 #define APIC_BUS_CYCLE_NS 1
  56
  57 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
  58 #define apic_debug(fmt, arg...)
  59
  60 #define APIC_LVT_NUM                    6
  61 /* 14 is the version for Xeon and Pentium 8.4.8*/
  62 #define APIC_VERSION                    (0x14UL | ((APIC_LVT_NUM - 1) << 16))
  63 #define LAPIC_MMIO_LENGTH               (1 << 12)
  64 /* followed define is not in apicdef.h */
  65 #define APIC_SHORT_MASK                 0xc0000
  66 #define APIC_DEST_NOSHORT               0x0
  67 #define APIC_DEST_MASK                  0x800
  68 #define MAX_APIC_VECTOR                 256
  69 #define APIC_VECTORS_PER_REG            32
  70
  71 #define APIC_BROADCAST                  0xFF
  72 #define X2APIC_BROADCAST                0xFFFFFFFFul
  73
  74 #define VEC_POS(v) ((v) & (32 - 1))
  75 #define REG_POS(v) (((v) >> 5) << 4)
  76
  77 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
  78 {
  79         *((u32 *) (apic->regs + reg_off)) = val;
  80 }
  81
  82 static inline int apic_test_vector(int vec, void *bitmap)
  83 {
  84         return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  85 }
  86
  87 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
  88 {
  89         struct kvm_lapic *apic = vcpu->arch.apic;
  90
  91         return apic_test_vector(vector, apic->regs + APIC_ISR) ||
  92                 apic_test_vector(vector, apic->regs + APIC_IRR);
  93 }
  94
  95 static inline void apic_set_vector(int vec, void *bitmap)
  96 {
  97         set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  98 }
  99
 100 static inline void apic_clear_vector(int vec, void *bitmap)
 101 {
 102         clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 103 }
 104
 105 static inline int __apic_test_and_set_vector(int vec, void *bitmap)
 106 {
 107         return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 108 }
 109
 110 static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
 111 {
 112         return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 113 }
 114
 115 struct static_key_deferred apic_hw_disabled __read_mostly;
 116 struct static_key_deferred apic_sw_disabled __read_mostly;
 117
 118 static inline int apic_enabled(struct kvm_lapic *apic)
 119 {
 120         return kvm_apic_sw_enabled(apic) &&     kvm_apic_hw_enabled(apic);
 121 }
 122
 123 #define LVT_MASK        \
 124         (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
 125
 126 #define LINT_MASK       \
 127         (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
 128          APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
 129
 130 static inline int kvm_apic_id(struct kvm_lapic *apic)
 131 {
 132         return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
 133 }
 134
 135 #define KVM_X2APIC_CID_BITS 0
 136
 137 static void recalculate_apic_map(struct kvm *kvm)
 138 {
 139         struct kvm_apic_map *new, *old = NULL;
 140         struct kvm_vcpu *vcpu;
 141         int i;
 142
 143         new = kzalloc(sizeof(struct kvm_apic_map), GFP_KERNEL);
 144
 145         mutex_lock(&kvm->arch.apic_map_lock);
 146
 147         if (!new)
 148                 goto out;
 149
 150         new->ldr_bits = 8;
 151         /* flat mode is default */
 152         new->cid_shift = 8;
 153         new->cid_mask = 0;
 154         new->lid_mask = 0xff;
 155         new->broadcast = APIC_BROADCAST;
 156
 157         kvm_for_each_vcpu(i, vcpu, kvm) {
 158                 struct kvm_lapic *apic = vcpu->arch.apic;
 159
 160                 if (!kvm_apic_present(vcpu))
 161                         continue;
 162
 163                 /*
 164                  * All APICs have to be configured in the same mode by an OS.
 165                  * We take advatage of this while building logical id loockup
 166                  * table. After reset APICs are in xapic/flat mode, so if we
 167                  * find apic with different setting we assume this is the mode
 168                  * OS wants all apics to be in; build lookup table accordingly.
 169                  */
 170                 if (apic_x2apic_mode(apic)) {
 171                         new->ldr_bits = 32;
 172                         new->cid_shift = 16;
 173                         new->cid_mask = (1 << KVM_X2APIC_CID_BITS) - 1;
 174                         new->lid_mask = 0xffff;
 175                         new->broadcast = X2APIC_BROADCAST;
 176                         break;
 177                 } else if (kvm_apic_sw_enabled(apic)) {
 178                         if (kvm_apic_get_reg(apic, APIC_DFR) ==
 179                                                         APIC_DFR_CLUSTER) {
 180                                 new->cid_shift = 4;
 181                                 new->cid_mask = 0xf;
 182                                 new->lid_mask = 0xf;
 183                         }
 184                         break;
 185                 }
 186         }
 187
 188         kvm_for_each_vcpu(i, vcpu, kvm) {
 189                 struct kvm_lapic *apic = vcpu->arch.apic;
 190                 u16 cid, lid;
 191                 u32 ldr;
 192
 193                 new->phys_map[kvm_apic_id(apic)] = apic;
 194
 195                 ldr = kvm_apic_get_reg(apic, APIC_LDR);
 196                 cid = apic_cluster_id(new, ldr);
 197                 lid = apic_logical_id(new, ldr);
 198
 199                 if (lid)
 200                         new->logical_map[cid][ffs(lid) - 1] = apic;
 201         }
 202 out:
 203         old = rcu_dereference_protected(kvm->arch.apic_map,
 204                         lockdep_is_held(&kvm->arch.apic_map_lock));
 205         rcu_assign_pointer(kvm->arch.apic_map, new);
 206         mutex_unlock(&kvm->arch.apic_map_lock);
 207
 208         if (old)
 209                 kfree_rcu(old, rcu);
 210
 211         kvm_vcpu_request_scan_ioapic(kvm);
 212 }
 213
 214 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
 215 {
 216         bool enabled = val & APIC_SPIV_APIC_ENABLED;
 217
 218         apic_set_reg(apic, APIC_SPIV, val);
 219
 220         if (enabled != apic->sw_enabled) {
 221                 apic->sw_enabled = enabled;
 222                 if (enabled) {
 223                         static_key_slow_dec_deferred(&apic_sw_disabled);
 224                         recalculate_apic_map(apic->vcpu->kvm);
 225                 } else
 226                         static_key_slow_inc(&apic_sw_disabled.key);
 227         }
 228 }
 229
 230 static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id)
 231 {
 232         apic_set_reg(apic, APIC_ID, id << 24);
 233         recalculate_apic_map(apic->vcpu->kvm);
 234 }
 235
 236 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
 237 {
 238         apic_set_reg(apic, APIC_LDR, id);
 239         recalculate_apic_map(apic->vcpu->kvm);
 240 }
 241
 242 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
 243 {
 244         return !(kvm_apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
 245 }
 246
 247 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
 248 {
 249         return kvm_apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
 250 }
 251
 252 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
 253 {
 254         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
 255 }
 256
 257 static inline int apic_lvtt_period(struct kvm_lapic *apic)
 258 {
 259         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
 260 }
 261
 262 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
 263 {
 264         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
 265 }
 266
 267 static inline int apic_lvt_nmi_mode(u32 lvt_val)
 268 {
 269         return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
 270 }
 271
 272 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
 273 {
 274         struct kvm_lapic *apic = vcpu->arch.apic;
 275         struct kvm_cpuid_entry2 *feat;
 276         u32 v = APIC_VERSION;
 277
 278         if (!kvm_vcpu_has_lapic(vcpu))
 279                 return;
 280
 281         feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
 282         if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
 283                 v |= APIC_LVR_DIRECTED_EOI;
 284         apic_set_reg(apic, APIC_LVR, v);
 285 }
 286
 287 static const unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
 288         LVT_MASK ,      /* part LVTT mask, timer mode mask added at runtime */
 289         LVT_MASK | APIC_MODE_MASK,      /* LVTTHMR */
 290         LVT_MASK | APIC_MODE_MASK,      /* LVTPC */
 291         LINT_MASK, LINT_MASK,   /* LVT0-1 */
 292         LVT_MASK                /* LVTERR */
 293 };
 294
 295 static int find_highest_vector(void *bitmap)
 296 {
 297         int vec;
 298         u32 *reg;
 299
 300         for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
 301              vec >= 0; vec -= APIC_VECTORS_PER_REG) {
 302                 reg = bitmap + REG_POS(vec);
 303                 if (*reg)
 304                         return fls(*reg) - 1 + vec;
 305         }
 306
 307         return -1;
 308 }
 309
 310 static u8 count_vectors(void *bitmap)
 311 {
 312         int vec;
 313         u32 *reg;
 314         u8 count = 0;
 315
 316         for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
 317                 reg = bitmap + REG_POS(vec);
 318                 count += hweight32(*reg);
 319         }
 320
 321         return count;
 322 }
 323
 324 void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir)
 325 {
 326         u32 i, pir_val;
 327         struct kvm_lapic *apic = vcpu->arch.apic;
 328
 329         for (i = 0; i <= 7; i++) {
 330                 pir_val = xchg(&pir[i], 0);
 331                 if (pir_val)
 332                         *((u32 *)(apic->regs + APIC_IRR + i * 0x10)) |= pir_val;
 333         }
 334 }
 335 EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
 336
 337 static inline void apic_set_irr(int vec, struct kvm_lapic *apic)
 338 {
 339         apic->irr_pending = true;
 340         apic_set_vector(vec, apic->regs + APIC_IRR);
 341 }
 342
 343 static inline int apic_search_irr(struct kvm_lapic *apic)
 344 {
 345         return find_highest_vector(apic->regs + APIC_IRR);
 346 }
 347
 348 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
 349 {
 350         int result;
 351
 352         /*
 353          * Note that irr_pending is just a hint. It will be always
 354          * true with virtual interrupt delivery enabled.
 355          */
 356         if (!apic->irr_pending)
 357                 return -1;
 358
 359         kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
 360         result = apic_search_irr(apic);
 361         ASSERT(result == -1 || result >= 16);
 362
 363         return result;
 364 }
 365
 366 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
 367 {
 368         struct kvm_vcpu *vcpu;
 369
 370         vcpu = apic->vcpu;
 371
 372         apic_clear_vector(vec, apic->regs + APIC_IRR);
 373         if (unlikely(kvm_apic_vid_enabled(vcpu->kvm)))
 374                 /* try to update RVI */
 375                 kvm_make_request(KVM_REQ_EVENT, vcpu);
 376         else {
 377                 vec = apic_search_irr(apic);
 378                 apic->irr_pending = (vec != -1);
 379         }
 380 }
 381
 382 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
 383 {
 384         struct kvm_vcpu *vcpu;
 385
 386         if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
 387                 return;
 388
 389         vcpu = apic->vcpu;
 390
 391         /*
 392          * With APIC virtualization enabled, all caching is disabled
 393          * because the processor can modify ISR under the hood.  Instead
 394          * just set SVI.
 395          */
 396         if (unlikely(kvm_apic_vid_enabled(vcpu->kvm)))
 397                 kvm_x86_ops->hwapic_isr_update(vcpu->kvm, vec);
 398         else {
 399                 ++apic->isr_count;
 400                 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
 401                 /*
 402                  * ISR (in service register) bit is set when injecting an interrupt.
 403                  * The highest vector is injected. Thus the latest bit set matches
 404                  * the highest bit in ISR.
 405                  */
 406                 apic->highest_isr_cache = vec;
 407         }
 408 }
 409
 410 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
 411 {
 412         int result;
 413
 414         /*
 415          * Note that isr_count is always 1, and highest_isr_cache
 416          * is always -1, with APIC virtualization enabled.
 417          */
 418         if (!apic->isr_count)
 419                 return -1;
 420         if (likely(apic->highest_isr_cache != -1))
 421                 return apic->highest_isr_cache;
 422
 423         result = find_highest_vector(apic->regs + APIC_ISR);
 424         ASSERT(result == -1 || result >= 16);
 425
 426         return result;
 427 }
 428
 429 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
 430 {
 431         struct kvm_vcpu *vcpu;
 432         if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
 433                 return;
 434
 435         vcpu = apic->vcpu;
 436
 437         /*
 438          * We do get here for APIC virtualization enabled if the guest
 439          * uses the Hyper-V APIC enlightenment.  In this case we may need
 440          * to trigger a new interrupt delivery by writing the SVI field;
 441          * on the other hand isr_count and highest_isr_cache are unused
 442          * and must be left alone.
 443          */
 444         if (unlikely(kvm_apic_vid_enabled(vcpu->kvm)))
 445                 kvm_x86_ops->hwapic_isr_update(vcpu->kvm,
 446                                                apic_find_highest_isr(apic));
 447         else {
 448                 --apic->isr_count;
 449                 BUG_ON(apic->isr_count < 0);
 450                 apic->highest_isr_cache = -1;
 451         }
 452 }
 453
 454 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
 455 {
 456         int highest_irr;
 457
 458         /* This may race with setting of irr in __apic_accept_irq() and
 459          * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
 460          * will cause vmexit immediately and the value will be recalculated
 461          * on the next vmentry.
 462          */
 463         if (!kvm_vcpu_has_lapic(vcpu))
 464                 return 0;
 465         highest_irr = apic_find_highest_irr(vcpu->arch.apic);
 466
 467         return highest_irr;
 468 }
 469
 470 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 471                              int vector, int level, int trig_mode,
 472                              unsigned long *dest_map);
 473
 474 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
 475                 unsigned long *dest_map)
 476 {
 477         struct kvm_lapic *apic = vcpu->arch.apic;
 478
 479         return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
 480                         irq->level, irq->trig_mode, dest_map);
 481 }
 482
 483 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
 484 {
 485
 486         return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
 487                                       sizeof(val));
 488 }
 489
 490 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
 491 {
 492
 493         return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
 494                                       sizeof(*val));
 495 }
 496
 497 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
 498 {
 499         return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
 500 }
 501
 502 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
 503 {
 504         u8 val;
 505         if (pv_eoi_get_user(vcpu, &val) < 0)
 506                 apic_debug("Can't read EOI MSR value: 0x%llx\n",
 507                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 508         return val & 0x1;
 509 }
 510
 511 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
 512 {
 513         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
 514                 apic_debug("Can't set EOI MSR value: 0x%llx\n",
 515                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 516                 return;
 517         }
 518         __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 519 }
 520
 521 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
 522 {
 523         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
 524                 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
 525                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 526                 return;
 527         }
 528         __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 529 }
 530
 531 void kvm_apic_update_tmr(struct kvm_vcpu *vcpu, u32 *tmr)
 532 {
 533         struct kvm_lapic *apic = vcpu->arch.apic;
 534         int i;
 535
 536         for (i = 0; i < 8; i++)
 537                 apic_set_reg(apic, APIC_TMR + 0x10 * i, tmr[i]);
 538 }
 539
 540 static void apic_update_ppr(struct kvm_lapic *apic)
 541 {
 542         u32 tpr, isrv, ppr, old_ppr;
 543         int isr;
 544
 545         old_ppr = kvm_apic_get_reg(apic, APIC_PROCPRI);
 546         tpr = kvm_apic_get_reg(apic, APIC_TASKPRI);
 547         isr = apic_find_highest_isr(apic);
 548         isrv = (isr != -1) ? isr : 0;
 549
 550         if ((tpr & 0xf0) >= (isrv & 0xf0))
 551                 ppr = tpr & 0xff;
 552         else
 553                 ppr = isrv & 0xf0;
 554
 555         apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
 556                    apic, ppr, isr, isrv);
 557
 558         if (old_ppr != ppr) {
 559                 apic_set_reg(apic, APIC_PROCPRI, ppr);
 560                 if (ppr < old_ppr)
 561                         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 562         }
 563 }
 564
 565 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
 566 {
 567         apic_set_reg(apic, APIC_TASKPRI, tpr);
 568         apic_update_ppr(apic);
 569 }
 570
 571 static int kvm_apic_broadcast(struct kvm_lapic *apic, u32 dest)
 572 {
 573         return dest == (apic_x2apic_mode(apic) ?
 574                         X2APIC_BROADCAST : APIC_BROADCAST);
 575 }
 576
 577 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 dest)
 578 {
 579         return kvm_apic_id(apic) == dest || kvm_apic_broadcast(apic, dest);
 580 }
 581
 582 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
 583 {
 584         int result = 0;
 585         u32 logical_id;
 586
 587         if (kvm_apic_broadcast(apic, mda))
 588                 return 1;
 589
 590         if (apic_x2apic_mode(apic)) {
 591                 logical_id = kvm_apic_get_reg(apic, APIC_LDR);
 592                 return logical_id & mda;
 593         }
 594
 595         logical_id = GET_APIC_LOGICAL_ID(kvm_apic_get_reg(apic, APIC_LDR));
 596
 597         switch (kvm_apic_get_reg(apic, APIC_DFR)) {
 598         case APIC_DFR_FLAT:
 599                 if (logical_id & mda)
 600                         result = 1;
 601                 break;
 602         case APIC_DFR_CLUSTER:
 603                 if (((logical_id >> 4) == (mda >> 0x4))
 604                     && (logical_id & mda & 0xf))
 605                         result = 1;
 606                 break;
 607         default:
 608                 apic_debug("Bad DFR vcpu %d: %08x\n",
 609                            apic->vcpu->vcpu_id, kvm_apic_get_reg(apic, APIC_DFR));
 610                 break;
 611         }
 612
 613         return result;
 614 }
 615
 616 int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
 617                            int short_hand, unsigned int dest, int dest_mode)
 618 {
 619         int result = 0;
 620         struct kvm_lapic *target = vcpu->arch.apic;
 621
 622         apic_debug("target %p, source %p, dest 0x%x, "
 623                    "dest_mode 0x%x, short_hand 0x%x\n",
 624                    target, source, dest, dest_mode, short_hand);
 625
 626         ASSERT(target);
 627         switch (short_hand) {
 628         case APIC_DEST_NOSHORT:
 629                 if (dest_mode == 0)
 630                         /* Physical mode. */
 631                         result = kvm_apic_match_physical_addr(target, dest);
 632                 else
 633                         /* Logical mode. */
 634                         result = kvm_apic_match_logical_addr(target, dest);
 635                 break;
 636         case APIC_DEST_SELF:
 637                 result = (target == source);
 638                 break;
 639         case APIC_DEST_ALLINC:
 640                 result = 1;
 641                 break;
 642         case APIC_DEST_ALLBUT:
 643                 result = (target != source);
 644                 break;
 645         default:
 646                 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
 647                            short_hand);
 648                 break;
 649         }
 650
 651         return result;
 652 }
 653
 654 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
 655                 struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map)
 656 {
 657         struct kvm_apic_map *map;
 658         unsigned long bitmap = 1;
 659         struct kvm_lapic **dst;
 660         int i;
 661         bool ret = false;
 662
 663         *r = -1;
 664
 665         if (irq->shorthand == APIC_DEST_SELF) {
 666                 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
 667                 return true;
 668         }
 669
 670         if (irq->shorthand)
 671                 return false;
 672
 673         rcu_read_lock();
 674         map = rcu_dereference(kvm->arch.apic_map);
 675
 676         if (!map)
 677                 goto out;
 678
 679         if (irq->dest_id == map->broadcast)
 680                 goto out;
 681
 682         if (irq->dest_mode == 0) { /* physical mode */
 683                 if (irq->delivery_mode == APIC_DM_LOWEST)
 684                         goto out;
 685                 dst = &map->phys_map[irq->dest_id & 0xff];
 686         } else {
 687                 u32 mda = irq->dest_id << (32 - map->ldr_bits);
 688
 689                 dst = map->logical_map[apic_cluster_id(map, mda)];
 690
 691                 bitmap = apic_logical_id(map, mda);
 692
 693                 if (irq->delivery_mode == APIC_DM_LOWEST) {
 694                         int l = -1;
 695                         for_each_set_bit(i, &bitmap, 16) {
 696                                 if (!dst[i])
 697                                         continue;
 698                                 if (l < 0)
 699                                         l = i;
 700                                 else if (kvm_apic_compare_prio(dst[i]->vcpu, dst[l]->vcpu) < 0)
 701                                         l = i;
 702                         }
 703
 704                         bitmap = (l >= 0) ? 1 << l : 0;
 705                 }
 706         }
 707
 708         for_each_set_bit(i, &bitmap, 16) {
 709                 if (!dst[i])
 710                         continue;
 711                 if (*r < 0)
 712                         *r = 0;
 713                 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
 714         }
 715
 716         ret = true;
 717 out:
 718         rcu_read_unlock();
 719         return ret;
 720 }
 721
 722 /*
 723  * Add a pending IRQ into lapic.
 724  * Return 1 if successfully added and 0 if discarded.
 725  */
 726 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 727                              int vector, int level, int trig_mode,
 728                              unsigned long *dest_map)
 729 {
 730         int result = 0;
 731         struct kvm_vcpu *vcpu = apic->vcpu;
 732
 733         trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
 734                                   trig_mode, vector);
 735         switch (delivery_mode) {
 736         case APIC_DM_LOWEST:
 737                 vcpu->arch.apic_arb_prio++;
 738         case APIC_DM_FIXED:
 739                 /* FIXME add logic for vcpu on reset */
 740                 if (unlikely(!apic_enabled(apic)))
 741                         break;
 742
 743                 result = 1;
 744
 745                 if (dest_map)
 746                         __set_bit(vcpu->vcpu_id, dest_map);
 747
 748                 if (kvm_x86_ops->deliver_posted_interrupt)
 749                         kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
 750                 else {
 751                         apic_set_irr(vector, apic);
 752
 753                         kvm_make_request(KVM_REQ_EVENT, vcpu);
 754                         kvm_vcpu_kick(vcpu);
 755                 }
 756                 break;
 757
 758         case APIC_DM_REMRD:
 759                 result = 1;
 760                 vcpu->arch.pv.pv_unhalted = 1;
 761                 kvm_make_request(KVM_REQ_EVENT, vcpu);
 762                 kvm_vcpu_kick(vcpu);
 763                 break;
 764
 765         case APIC_DM_SMI:
 766                 apic_debug("Ignoring guest SMI\n");
 767                 break;
 768
 769         case APIC_DM_NMI:
 770                 result = 1;
 771                 kvm_inject_nmi(vcpu);
 772                 kvm_vcpu_kick(vcpu);
 773                 break;
 774
 775         case APIC_DM_INIT:
 776                 if (!trig_mode || level) {
 777                         result = 1;
 778                         /* assumes that there are only KVM_APIC_INIT/SIPI */
 779                         apic->pending_events = (1UL << KVM_APIC_INIT);
 780                         /* make sure pending_events is visible before sending
 781                          * the request */
 782                         smp_wmb();
 783                         kvm_make_request(KVM_REQ_EVENT, vcpu);
 784                         kvm_vcpu_kick(vcpu);
 785                 } else {
 786                         apic_debug("Ignoring de-assert INIT to vcpu %d\n",
 787                                    vcpu->vcpu_id);
 788                 }
 789                 break;
 790
 791         case APIC_DM_STARTUP:
 792                 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
 793                            vcpu->vcpu_id, vector);
 794                 result = 1;
 795                 apic->sipi_vector = vector;
 796                 /* make sure sipi_vector is visible for the receiver */
 797                 smp_wmb();
 798                 set_bit(KVM_APIC_SIPI, &apic->pending_events);
 799                 kvm_make_request(KVM_REQ_EVENT, vcpu);
 800                 kvm_vcpu_kick(vcpu);
 801                 break;
 802
 803         case APIC_DM_EXTINT:
 804                 /*
 805                  * Should only be called by kvm_apic_local_deliver() with LVT0,
 806                  * before NMI watchdog was enabled. Already handled by
 807                  * kvm_apic_accept_pic_intr().
 808                  */
 809                 break;
 810
 811         default:
 812                 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
 813                        delivery_mode);
 814                 break;
 815         }
 816         return result;
 817 }
 818
 819 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
 820 {
 821         return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
 822 }
 823
 824 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
 825 {
 826         if (!(kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI) &&
 827             kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) {
 828                 int trigger_mode;
 829                 if (apic_test_vector(vector, apic->regs + APIC_TMR))
 830                         trigger_mode = IOAPIC_LEVEL_TRIG;
 831                 else
 832                         trigger_mode = IOAPIC_EDGE_TRIG;
 833                 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
 834         }
 835 }
 836
 837 static int apic_set_eoi(struct kvm_lapic *apic)
 838 {
 839         int vector = apic_find_highest_isr(apic);
 840
 841         trace_kvm_eoi(apic, vector);
 842
 843         /*
 844          * Not every write EOI will has corresponding ISR,
 845          * one example is when Kernel check timer on setup_IO_APIC
 846          */
 847         if (vector == -1)
 848                 return vector;
 849
 850         apic_clear_isr(vector, apic);
 851         apic_update_ppr(apic);
 852
 853         kvm_ioapic_send_eoi(apic, vector);
 854         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 855         return vector;
 856 }
 857
 858 /*
 859  * this interface assumes a trap-like exit, which has already finished
 860  * desired side effect including vISR and vPPR update.
 861  */
 862 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
 863 {
 864         struct kvm_lapic *apic = vcpu->arch.apic;
 865
 866         trace_kvm_eoi(apic, vector);
 867
 868         kvm_ioapic_send_eoi(apic, vector);
 869         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 870 }
 871 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
 872
 873 static void apic_send_ipi(struct kvm_lapic *apic)
 874 {
 875         u32 icr_low = kvm_apic_get_reg(apic, APIC_ICR);
 876         u32 icr_high = kvm_apic_get_reg(apic, APIC_ICR2);
 877         struct kvm_lapic_irq irq;
 878
 879         irq.vector = icr_low & APIC_VECTOR_MASK;
 880         irq.delivery_mode = icr_low & APIC_MODE_MASK;
 881         irq.dest_mode = icr_low & APIC_DEST_MASK;
 882         irq.level = icr_low & APIC_INT_ASSERT;
 883         irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
 884         irq.shorthand = icr_low & APIC_SHORT_MASK;
 885         if (apic_x2apic_mode(apic))
 886                 irq.dest_id = icr_high;
 887         else
 888                 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
 889
 890         trace_kvm_apic_ipi(icr_low, irq.dest_id);
 891
 892         apic_debug("icr_high 0x%x, icr_low 0x%x, "
 893                    "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
 894                    "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
 895                    icr_high, icr_low, irq.shorthand, irq.dest_id,
 896                    irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
 897                    irq.vector);
 898
 899         kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
 900 }
 901
 902 static u32 apic_get_tmcct(struct kvm_lapic *apic)
 903 {
 904         ktime_t remaining;
 905         s64 ns;
 906         u32 tmcct;
 907
 908         ASSERT(apic != NULL);
 909
 910         /* if initial count is 0, current count should also be 0 */
 911         if (kvm_apic_get_reg(apic, APIC_TMICT) == 0 ||
 912                 apic->lapic_timer.period == 0)
 913                 return 0;
 914
 915         remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
 916         if (ktime_to_ns(remaining) < 0)
 917                 remaining = ktime_set(0, 0);
 918
 919         ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
 920         tmcct = div64_u64(ns,
 921                          (APIC_BUS_CYCLE_NS * apic->divide_count));
 922
 923         return tmcct;
 924 }
 925
 926 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
 927 {
 928         struct kvm_vcpu *vcpu = apic->vcpu;
 929         struct kvm_run *run = vcpu->run;
 930
 931         kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
 932         run->tpr_access.rip = kvm_rip_read(vcpu);
 933         run->tpr_access.is_write = write;
 934 }
 935
 936 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
 937 {
 938         if (apic->vcpu->arch.tpr_access_reporting)
 939                 __report_tpr_access(apic, write);
 940 }
 941
 942 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
 943 {
 944         u32 val = 0;
 945
 946         if (offset >= LAPIC_MMIO_LENGTH)
 947                 return 0;
 948
 949         switch (offset) {
 950         case APIC_ID:
 951                 if (apic_x2apic_mode(apic))
 952                         val = kvm_apic_id(apic);
 953                 else
 954                         val = kvm_apic_id(apic) << 24;
 955                 break;
 956         case APIC_ARBPRI:
 957                 apic_debug("Access APIC ARBPRI register which is for P6\n");
 958                 break;
 959
 960         case APIC_TMCCT:        /* Timer CCR */
 961                 if (apic_lvtt_tscdeadline(apic))
 962                         return 0;
 963
 964                 val = apic_get_tmcct(apic);
 965                 break;
 966         case APIC_PROCPRI:
 967                 apic_update_ppr(apic);
 968                 val = kvm_apic_get_reg(apic, offset);
 969                 break;
 970         case APIC_TASKPRI:
 971                 report_tpr_access(apic, false);
 972                 /* fall thru */
 973         default:
 974                 val = kvm_apic_get_reg(apic, offset);
 975                 break;
 976         }
 977
 978         return val;
 979 }
 980
 981 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
 982 {
 983         return container_of(dev, struct kvm_lapic, dev);
 984 }
 985
 986 static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
 987                 void *data)
 988 {
 989         unsigned char alignment = offset & 0xf;
 990         u32 result;
 991         /* this bitmask has a bit cleared for each reserved register */
 992         static const u64 rmask = 0x43ff01ffffffe70cULL;
 993
 994         if ((alignment + len) > 4) {
 995                 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
 996                            offset, len);
 997                 return 1;
 998         }
 999
1000         if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
1001                 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1002                            offset);
1003                 return 1;
1004         }
1005
1006         result = __apic_read(apic, offset & ~0xf);
1007
1008         trace_kvm_apic_read(offset, result);
1009
1010         switch (len) {
1011         case 1:
1012         case 2:
1013         case 4:
1014                 memcpy(data, (char *)&result + alignment, len);
1015                 break;
1016         default:
1017                 printk(KERN_ERR "Local APIC read with len = %x, "
1018                        "should be 1,2, or 4 instead\n", len);
1019                 break;
1020         }
1021         return 0;
1022 }
1023
1024 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1025 {
1026         return kvm_apic_hw_enabled(apic) &&
1027             addr >= apic->base_address &&
1028             addr < apic->base_address + LAPIC_MMIO_LENGTH;
1029 }
1030
1031 static int apic_mmio_read(struct kvm_io_device *this,
1032                            gpa_t address, int len, void *data)
1033 {
1034         struct kvm_lapic *apic = to_lapic(this);
1035         u32 offset = address - apic->base_address;
1036
1037         if (!apic_mmio_in_range(apic, address))
1038                 return -EOPNOTSUPP;
1039
1040         apic_reg_read(apic, offset, len, data);
1041
1042         return 0;
1043 }
1044
1045 static void update_divide_count(struct kvm_lapic *apic)
1046 {
1047         u32 tmp1, tmp2, tdcr;
1048
1049         tdcr = kvm_apic_get_reg(apic, APIC_TDCR);
1050         tmp1 = tdcr & 0xf;
1051         tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
1052         apic->divide_count = 0x1 << (tmp2 & 0x7);
1053
1054         apic_debug("timer divide count is 0x%x\n",
1055                                    apic->divide_count);
1056 }
1057
1058 static void apic_timer_expired(struct kvm_lapic *apic)
1059 {
1060         struct kvm_vcpu *vcpu = apic->vcpu;
1061         wait_queue_head_t *q = &vcpu->wq;
1062
1063         /*
1064          * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1065          * vcpu_enter_guest.
1066          */
1067         if (atomic_read(&apic->lapic_timer.pending))
1068                 return;
1069
1070         atomic_inc(&apic->lapic_timer.pending);
1071         /* FIXME: this code should not know anything about vcpus */
1072         kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1073
1074         if (waitqueue_active(q))
1075                 wake_up_interruptible(q);
1076 }
1077
1078 static void start_apic_timer(struct kvm_lapic *apic)
1079 {
1080         ktime_t now;
1081         atomic_set(&apic->lapic_timer.pending, 0);
1082
1083         if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
1084                 /* lapic timer in oneshot or periodic mode */
1085                 now = apic->lapic_timer.timer.base->get_time();
1086                 apic->lapic_timer.period = (u64)kvm_apic_get_reg(apic, APIC_TMICT)
1087                             * APIC_BUS_CYCLE_NS * apic->divide_count;
1088
1089                 if (!apic->lapic_timer.period)
1090                         return;
1091                 /*
1092                  * Do not allow the guest to program periodic timers with small
1093                  * interval, since the hrtimers are not throttled by the host
1094                  * scheduler.
1095                  */
1096                 if (apic_lvtt_period(apic)) {
1097                         s64 min_period = min_timer_period_us * 1000LL;
1098
1099                         if (apic->lapic_timer.period < min_period) {
1100                                 pr_info_ratelimited(
1101                                     "kvm: vcpu %i: requested %lld ns "
1102                                     "lapic timer period limited to %lld ns\n",
1103                                     apic->vcpu->vcpu_id,
1104                                     apic->lapic_timer.period, min_period);
1105                                 apic->lapic_timer.period = min_period;
1106                         }
1107                 }
1108
1109                 hrtimer_start(&apic->lapic_timer.timer,
1110                               ktime_add_ns(now, apic->lapic_timer.period),
1111                               HRTIMER_MODE_ABS);
1112
1113                 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
1114                            PRIx64 ", "
1115                            "timer initial count 0x%x, period %lldns, "
1116                            "expire @ 0x%016" PRIx64 ".\n", __func__,
1117                            APIC_BUS_CYCLE_NS, ktime_to_ns(now),
1118                            kvm_apic_get_reg(apic, APIC_TMICT),
1119                            apic->lapic_timer.period,
1120                            ktime_to_ns(ktime_add_ns(now,
1121                                         apic->lapic_timer.period)));
1122         } else if (apic_lvtt_tscdeadline(apic)) {
1123                 /* lapic timer in tsc deadline mode */
1124                 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1125                 u64 ns = 0;
1126                 struct kvm_vcpu *vcpu = apic->vcpu;
1127                 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1128                 unsigned long flags;
1129
1130                 if (unlikely(!tscdeadline || !this_tsc_khz))
1131                         return;
1132
1133                 local_irq_save(flags);
1134
1135                 now = apic->lapic_timer.timer.base->get_time();
1136                 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu, native_read_tsc());
1137                 if (likely(tscdeadline > guest_tsc)) {
1138                         ns = (tscdeadline - guest_tsc) * 1000000ULL;
1139                         do_div(ns, this_tsc_khz);
1140                         hrtimer_start(&apic->lapic_timer.timer,
1141                                 ktime_add_ns(now, ns), HRTIMER_MODE_ABS);
1142                 } else
1143                         apic_timer_expired(apic);
1144
1145                 local_irq_restore(flags);
1146         }
1147 }
1148
1149 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1150 {
1151         int nmi_wd_enabled = apic_lvt_nmi_mode(kvm_apic_get_reg(apic, APIC_LVT0));
1152
1153         if (apic_lvt_nmi_mode(lvt0_val)) {
1154                 if (!nmi_wd_enabled) {
1155                         apic_debug("Receive NMI setting on APIC_LVT0 "
1156                                    "for cpu %d\n", apic->vcpu->vcpu_id);
1157                         apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
1158                 }
1159         } else if (nmi_wd_enabled)
1160                 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
1161 }
1162
1163 static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
1164 {
1165         int ret = 0;
1166
1167         trace_kvm_apic_write(reg, val);
1168
1169         switch (reg) {
1170         case APIC_ID:           /* Local APIC ID */
1171                 if (!apic_x2apic_mode(apic))
1172                         kvm_apic_set_id(apic, val >> 24);
1173                 else
1174                         ret = 1;
1175                 break;
1176
1177         case APIC_TASKPRI:
1178                 report_tpr_access(apic, true);
1179                 apic_set_tpr(apic, val & 0xff);
1180                 break;
1181
1182         case APIC_EOI:
1183                 apic_set_eoi(apic);
1184                 break;
1185
1186         case APIC_LDR:
1187                 if (!apic_x2apic_mode(apic))
1188                         kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
1189                 else
1190                         ret = 1;
1191                 break;
1192
1193         case APIC_DFR:
1194                 if (!apic_x2apic_mode(apic)) {
1195                         apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1196                         recalculate_apic_map(apic->vcpu->kvm);
1197                 } else
1198                         ret = 1;
1199                 break;
1200
1201         case APIC_SPIV: {
1202                 u32 mask = 0x3ff;
1203                 if (kvm_apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
1204                         mask |= APIC_SPIV_DIRECTED_EOI;
1205                 apic_set_spiv(apic, val & mask);
1206                 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1207                         int i;
1208                         u32 lvt_val;
1209
1210                         for (i = 0; i < APIC_LVT_NUM; i++) {
1211                                 lvt_val = kvm_apic_get_reg(apic,
1212                                                        APIC_LVTT + 0x10 * i);
1213                                 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
1214                                              lvt_val | APIC_LVT_MASKED);
1215                         }
1216                         atomic_set(&apic->lapic_timer.pending, 0);
1217
1218                 }
1219                 break;
1220         }
1221         case APIC_ICR:
1222                 /* No delay here, so we always clear the pending bit */
1223                 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1224                 apic_send_ipi(apic);
1225                 break;
1226
1227         case APIC_ICR2:
1228                 if (!apic_x2apic_mode(apic))
1229                         val &= 0xff000000;
1230                 apic_set_reg(apic, APIC_ICR2, val);
1231                 break;
1232
1233         case APIC_LVT0:
1234                 apic_manage_nmi_watchdog(apic, val);
1235         case APIC_LVTTHMR:
1236         case APIC_LVTPC:
1237         case APIC_LVT1:
1238         case APIC_LVTERR:
1239                 /* TODO: Check vector */
1240                 if (!kvm_apic_sw_enabled(apic))
1241                         val |= APIC_LVT_MASKED;
1242
1243                 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1244                 apic_set_reg(apic, reg, val);
1245
1246                 break;
1247
1248         case APIC_LVTT: {
1249                 u32 timer_mode = val & apic->lapic_timer.timer_mode_mask;
1250
1251                 if (apic->lapic_timer.timer_mode != timer_mode) {
1252                         apic->lapic_timer.timer_mode = timer_mode;
1253                         hrtimer_cancel(&apic->lapic_timer.timer);
1254                 }
1255
1256                 if (!kvm_apic_sw_enabled(apic))
1257                         val |= APIC_LVT_MASKED;
1258                 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1259                 apic_set_reg(apic, APIC_LVTT, val);
1260                 break;
1261         }
1262
1263         case APIC_TMICT:
1264                 if (apic_lvtt_tscdeadline(apic))
1265                         break;
1266
1267                 hrtimer_cancel(&apic->lapic_timer.timer);
1268                 apic_set_reg(apic, APIC_TMICT, val);
1269                 start_apic_timer(apic);
1270                 break;
1271
1272         case APIC_TDCR:
1273                 if (val & 4)
1274                         apic_debug("KVM_WRITE:TDCR %x\n", val);
1275                 apic_set_reg(apic, APIC_TDCR, val);
1276                 update_divide_count(apic);
1277                 break;
1278
1279         case APIC_ESR:
1280                 if (apic_x2apic_mode(apic) && val != 0) {
1281                         apic_debug("KVM_WRITE:ESR not zero %x\n", val);
1282                         ret = 1;
1283                 }
1284                 break;
1285
1286         case APIC_SELF_IPI:
1287                 if (apic_x2apic_mode(apic)) {
1288                         apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1289                 } else
1290                         ret = 1;
1291                 break;
1292         default:
1293                 ret = 1;
1294                 break;
1295         }
1296         if (ret)
1297                 apic_debug("Local APIC Write to read-only register %x\n", reg);
1298         return ret;
1299 }
1300
1301 static int apic_mmio_write(struct kvm_io_device *this,
1302                             gpa_t address, int len, const void *data)
1303 {
1304         struct kvm_lapic *apic = to_lapic(this);
1305         unsigned int offset = address - apic->base_address;
1306         u32 val;
1307
1308         if (!apic_mmio_in_range(apic, address))
1309                 return -EOPNOTSUPP;
1310
1311         /*
1312          * APIC register must be aligned on 128-bits boundary.
1313          * 32/64/128 bits registers must be accessed thru 32 bits.
1314          * Refer SDM 8.4.1
1315          */
1316         if (len != 4 || (offset & 0xf)) {
1317                 /* Don't shout loud, $infamous_os would cause only noise. */
1318                 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
1319                 return 0;
1320         }
1321
1322         val = *(u32*)data;
1323
1324         /* too common printing */
1325         if (offset != APIC_EOI)
1326                 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1327                            "0x%x\n", __func__, offset, len, val);
1328
1329         apic_reg_write(apic, offset & 0xff0, val);
1330
1331         return 0;
1332 }
1333
1334 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1335 {
1336         if (kvm_vcpu_has_lapic(vcpu))
1337                 apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1338 }
1339 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1340
1341 /* emulate APIC access in a trap manner */
1342 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1343 {
1344         u32 val = 0;
1345
1346         /* hw has done the conditional check and inst decode */
1347         offset &= 0xff0;
1348
1349         apic_reg_read(vcpu->arch.apic, offset, 4, &val);
1350
1351         /* TODO: optimize to just emulate side effect w/o one more write */
1352         apic_reg_write(vcpu->arch.apic, offset, val);
1353 }
1354 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
1355
1356 void kvm_free_lapic(struct kvm_vcpu *vcpu)
1357 {
1358         struct kvm_lapic *apic = vcpu->arch.apic;
1359
1360         if (!vcpu->arch.apic)
1361                 return;
1362
1363         hrtimer_cancel(&apic->lapic_timer.timer);
1364
1365         if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1366                 static_key_slow_dec_deferred(&apic_hw_disabled);
1367
1368         if (!apic->sw_enabled)
1369                 static_key_slow_dec_deferred(&apic_sw_disabled);
1370
1371         if (apic->regs)
1372                 free_page((unsigned long)apic->regs);
1373
1374         kfree(apic);
1375 }
1376
1377 /*
1378  *----------------------------------------------------------------------
1379  * LAPIC interface
1380  *----------------------------------------------------------------------
1381  */
1382
1383 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1384 {
1385         struct kvm_lapic *apic = vcpu->arch.apic;
1386
1387         if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1388                         apic_lvtt_period(apic))
1389                 return 0;
1390
1391         return apic->lapic_timer.tscdeadline;
1392 }
1393
1394 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1395 {
1396         struct kvm_lapic *apic = vcpu->arch.apic;
1397
1398         if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
1399                         apic_lvtt_period(apic))
1400                 return;
1401
1402         hrtimer_cancel(&apic->lapic_timer.timer);
1403         apic->lapic_timer.tscdeadline = data;
1404         start_apic_timer(apic);
1405 }
1406
1407 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1408 {
1409         struct kvm_lapic *apic = vcpu->arch.apic;
1410
1411         if (!kvm_vcpu_has_lapic(vcpu))
1412                 return;
1413
1414         apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
1415                      | (kvm_apic_get_reg(apic, APIC_TASKPRI) & 4));
1416 }
1417
1418 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1419 {
1420         u64 tpr;
1421
1422         if (!kvm_vcpu_has_lapic(vcpu))
1423                 return 0;
1424
1425         tpr = (u64) kvm_apic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
1426
1427         return (tpr & 0xf0) >> 4;
1428 }
1429
1430 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1431 {
1432         u64 old_value = vcpu->arch.apic_base;
1433         struct kvm_lapic *apic = vcpu->arch.apic;
1434
1435         if (!apic) {
1436                 value |= MSR_IA32_APICBASE_BSP;
1437                 vcpu->arch.apic_base = value;
1438                 return;
1439         }
1440
1441         if (!kvm_vcpu_is_bsp(apic->vcpu))
1442                 value &= ~MSR_IA32_APICBASE_BSP;
1443         vcpu->arch.apic_base = value;
1444
1445         /* update jump label if enable bit changes */
1446         if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
1447                 if (value & MSR_IA32_APICBASE_ENABLE)
1448                         static_key_slow_dec_deferred(&apic_hw_disabled);
1449                 else
1450                         static_key_slow_inc(&apic_hw_disabled.key);
1451                 recalculate_apic_map(vcpu->kvm);
1452         }
1453
1454         if ((old_value ^ value) & X2APIC_ENABLE) {
1455                 if (value & X2APIC_ENABLE) {
1456                         u32 id = kvm_apic_id(apic);
1457                         u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
1458                         kvm_apic_set_ldr(apic, ldr);
1459                         kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
1460                 } else
1461                         kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
1462         }
1463
1464         apic->base_address = apic->vcpu->arch.apic_base &
1465                              MSR_IA32_APICBASE_BASE;
1466
1467         if ((value & MSR_IA32_APICBASE_ENABLE) &&
1468              apic->base_address != APIC_DEFAULT_PHYS_BASE)
1469                 pr_warn_once("APIC base relocation is unsupported by KVM");
1470
1471         /* with FSB delivery interrupt, we can restart APIC functionality */
1472         apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
1473                    "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
1474
1475 }
1476
1477 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
1478 {
1479         struct kvm_lapic *apic;
1480         int i;
1481
1482         apic_debug("%s\n", __func__);
1483
1484         ASSERT(vcpu);
1485         apic = vcpu->arch.apic;
1486         ASSERT(apic != NULL);
1487
1488         /* Stop the timer in case it's a reset to an active apic */
1489         hrtimer_cancel(&apic->lapic_timer.timer);
1490
1491         kvm_apic_set_id(apic, vcpu->vcpu_id);
1492         kvm_apic_set_version(apic->vcpu);
1493
1494         for (i = 0; i < APIC_LVT_NUM; i++)
1495                 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
1496         apic->lapic_timer.timer_mode = 0;
1497         apic_set_reg(apic, APIC_LVT0,
1498                      SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
1499
1500         apic_set_reg(apic, APIC_DFR, 0xffffffffU);
1501         apic_set_spiv(apic, 0xff);
1502         apic_set_reg(apic, APIC_TASKPRI, 0);
1503         kvm_apic_set_ldr(apic, 0);
1504         apic_set_reg(apic, APIC_ESR, 0);
1505         apic_set_reg(apic, APIC_ICR, 0);
1506         apic_set_reg(apic, APIC_ICR2, 0);
1507         apic_set_reg(apic, APIC_TDCR, 0);
1508         apic_set_reg(apic, APIC_TMICT, 0);
1509         for (i = 0; i < 8; i++) {
1510                 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1511                 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1512                 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1513         }
1514         apic->irr_pending = kvm_apic_vid_enabled(vcpu->kvm);
1515         apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm);
1516         apic->highest_isr_cache = -1;
1517         update_divide_count(apic);
1518         atomic_set(&apic->lapic_timer.pending, 0);
1519         if (kvm_vcpu_is_bsp(vcpu))
1520                 kvm_lapic_set_base(vcpu,
1521                                 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
1522         vcpu->arch.pv_eoi.msr_val = 0;
1523         apic_update_ppr(apic);
1524
1525         vcpu->arch.apic_arb_prio = 0;
1526         vcpu->arch.apic_attention = 0;
1527
1528         apic_debug("%s: vcpu=%p, id=%d, base_msr="
1529                    "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
1530                    vcpu, kvm_apic_id(apic),
1531                    vcpu->arch.apic_base, apic->base_address);
1532 }
1533
1534 /*
1535  *----------------------------------------------------------------------
1536  * timer interface
1537  *----------------------------------------------------------------------
1538  */
1539
1540 static bool lapic_is_periodic(struct kvm_lapic *apic)
1541 {
1542         return apic_lvtt_period(apic);
1543 }
1544
1545 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1546 {
1547         struct kvm_lapic *apic = vcpu->arch.apic;
1548
1549         if (kvm_vcpu_has_lapic(vcpu) && apic_enabled(apic) &&
1550                         apic_lvt_enabled(apic, APIC_LVTT))
1551                 return atomic_read(&apic->lapic_timer.pending);
1552
1553         return 0;
1554 }
1555
1556 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1557 {
1558         u32 reg = kvm_apic_get_reg(apic, lvt_type);
1559         int vector, mode, trig_mode;
1560
1561         if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
1562                 vector = reg & APIC_VECTOR_MASK;
1563                 mode = reg & APIC_MODE_MASK;
1564                 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1565                 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
1566                                         NULL);
1567         }
1568         return 0;
1569 }
1570
1571 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
1572 {
1573         struct kvm_lapic *apic = vcpu->arch.apic;
1574
1575         if (apic)
1576                 kvm_apic_local_deliver(apic, APIC_LVT0);
1577 }
1578
1579 static const struct kvm_io_device_ops apic_mmio_ops = {
1580         .read     = apic_mmio_read,
1581         .write    = apic_mmio_write,
1582 };
1583
1584 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
1585 {
1586         struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
1587         struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
1588
1589         apic_timer_expired(apic);
1590
1591         if (lapic_is_periodic(apic)) {
1592                 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
1593                 return HRTIMER_RESTART;
1594         } else
1595                 return HRTIMER_NORESTART;
1596 }
1597
1598 int kvm_create_lapic(struct kvm_vcpu *vcpu)
1599 {
1600         struct kvm_lapic *apic;
1601
1602         ASSERT(vcpu != NULL);
1603         apic_debug("apic_init %d\n", vcpu->vcpu_id);
1604
1605         apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1606         if (!apic)
1607                 goto nomem;
1608
1609         vcpu->arch.apic = apic;
1610
1611         apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1612         if (!apic->regs) {
1613                 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1614                        vcpu->vcpu_id);
1615                 goto nomem_free_apic;
1616         }
1617         apic->vcpu = vcpu;
1618
1619         hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1620                      HRTIMER_MODE_ABS);
1621         apic->lapic_timer.timer.function = apic_timer_fn;
1622
1623         /*
1624          * APIC is created enabled. This will prevent kvm_lapic_set_base from
1625          * thinking that APIC satet has changed.
1626          */
1627         vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
1628         kvm_lapic_set_base(vcpu,
1629                         APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE);
1630
1631         static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
1632         kvm_lapic_reset(vcpu);
1633         kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
1634
1635         return 0;
1636 nomem_free_apic:
1637         kfree(apic);
1638 nomem:
1639         return -ENOMEM;
1640 }
1641
1642 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1643 {
1644         struct kvm_lapic *apic = vcpu->arch.apic;
1645         int highest_irr;
1646
1647         if (!kvm_vcpu_has_lapic(vcpu) || !apic_enabled(apic))
1648                 return -1;
1649
1650         apic_update_ppr(apic);
1651         highest_irr = apic_find_highest_irr(apic);
1652         if ((highest_irr == -1) ||
1653             ((highest_irr & 0xF0) <= kvm_apic_get_reg(apic, APIC_PROCPRI)))
1654                 return -1;
1655         return highest_irr;
1656 }
1657
1658 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1659 {
1660         u32 lvt0 = kvm_apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1661         int r = 0;
1662
1663         if (!kvm_apic_hw_enabled(vcpu->arch.apic))
1664                 r = 1;
1665         if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1666             GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1667                 r = 1;
1668         return r;
1669 }
1670
1671 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1672 {
1673         struct kvm_lapic *apic = vcpu->arch.apic;
1674
1675         if (!kvm_vcpu_has_lapic(vcpu))
1676                 return;
1677
1678         if (atomic_read(&apic->lapic_timer.pending) > 0) {
1679                 kvm_apic_local_deliver(apic, APIC_LVTT);
1680                 if (apic_lvtt_tscdeadline(apic))
1681                         apic->lapic_timer.tscdeadline = 0;
1682                 atomic_set(&apic->lapic_timer.pending, 0);
1683         }
1684 }
1685
1686 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1687 {
1688         int vector = kvm_apic_has_interrupt(vcpu);
1689         struct kvm_lapic *apic = vcpu->arch.apic;
1690
1691         if (vector == -1)
1692                 return -1;
1693
1694         /*
1695          * We get here even with APIC virtualization enabled, if doing
1696          * nested virtualization and L1 runs with the "acknowledge interrupt
1697          * on exit" mode.  Then we cannot inject the interrupt via RVI,
1698          * because the process would deliver it through the IDT.
1699          */
1700
1701         apic_set_isr(vector, apic);
1702         apic_update_ppr(apic);
1703         apic_clear_irr(vector, apic);
1704         return vector;
1705 }
1706
1707 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
1708                 struct kvm_lapic_state *s)
1709 {
1710         struct kvm_lapic *apic = vcpu->arch.apic;
1711
1712         kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
1713         /* set SPIV separately to get count of SW disabled APICs right */
1714         apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
1715         memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
1716         /* call kvm_apic_set_id() to put apic into apic_map */
1717         kvm_apic_set_id(apic, kvm_apic_id(apic));
1718         kvm_apic_set_version(vcpu);
1719
1720         apic_update_ppr(apic);
1721         hrtimer_cancel(&apic->lapic_timer.timer);
1722         update_divide_count(apic);
1723         start_apic_timer(apic);
1724         apic->irr_pending = true;
1725         apic->isr_count = kvm_apic_vid_enabled(vcpu->kvm) ?
1726                                 1 : count_vectors(apic->regs + APIC_ISR);
1727         apic->highest_isr_cache = -1;
1728         if (kvm_x86_ops->hwapic_irr_update)
1729                 kvm_x86_ops->hwapic_irr_update(vcpu,
1730                                 apic_find_highest_irr(apic));
1731         kvm_x86_ops->hwapic_isr_update(vcpu->kvm, apic_find_highest_isr(apic));
1732         kvm_make_request(KVM_REQ_EVENT, vcpu);
1733         kvm_rtc_eoi_tracking_restore_one(vcpu);
1734 }
1735
1736 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1737 {
1738         struct hrtimer *timer;
1739
1740         if (!kvm_vcpu_has_lapic(vcpu))
1741                 return;
1742
1743         timer = &vcpu->arch.apic->lapic_timer.timer;
1744         if (hrtimer_cancel(timer))
1745                 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1746 }
1747
1748 /*
1749  * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
1750  *
1751  * Detect whether guest triggered PV EOI since the
1752  * last entry. If yes, set EOI on guests's behalf.
1753  * Clear PV EOI in guest memory in any case.
1754  */
1755 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
1756                                         struct kvm_lapic *apic)
1757 {
1758         bool pending;
1759         int vector;
1760         /*
1761          * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
1762          * and KVM_PV_EOI_ENABLED in guest memory as follows:
1763          *
1764          * KVM_APIC_PV_EOI_PENDING is unset:
1765          *      -> host disabled PV EOI.
1766          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
1767          *      -> host enabled PV EOI, guest did not execute EOI yet.
1768          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
1769          *      -> host enabled PV EOI, guest executed EOI.
1770          */
1771         BUG_ON(!pv_eoi_enabled(vcpu));
1772         pending = pv_eoi_get_pending(vcpu);
1773         /*
1774          * Clear pending bit in any case: it will be set again on vmentry.
1775          * While this might not be ideal from performance point of view,
1776          * this makes sure pv eoi is only enabled when we know it's safe.
1777          */
1778         pv_eoi_clr_pending(vcpu);
1779         if (pending)
1780                 return;
1781         vector = apic_set_eoi(apic);
1782         trace_kvm_pv_eoi(apic, vector);
1783 }
1784
1785 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1786 {
1787         u32 data;
1788
1789         if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
1790                 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
1791
1792         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1793                 return;
1794
1795         kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1796                                 sizeof(u32));
1797
1798         apic_set_tpr(vcpu->arch.apic, data & 0xff);
1799 }
1800
1801 /*
1802  * apic_sync_pv_eoi_to_guest - called before vmentry
1803  *
1804  * Detect whether it's safe to enable PV EOI and
1805  * if yes do so.
1806  */
1807 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
1808                                         struct kvm_lapic *apic)
1809 {
1810         if (!pv_eoi_enabled(vcpu) ||
1811             /* IRR set or many bits in ISR: could be nested. */
1812             apic->irr_pending ||
1813             /* Cache not set: could be safe but we don't bother. */
1814             apic->highest_isr_cache == -1 ||
1815             /* Need EOI to update ioapic. */
1816             kvm_ioapic_handles_vector(vcpu->kvm, apic->highest_isr_cache)) {
1817                 /*
1818                  * PV EOI was disabled by apic_sync_pv_eoi_from_guest
1819                  * so we need not do anything here.
1820                  */
1821                 return;
1822         }
1823
1824         pv_eoi_set_pending(apic->vcpu);
1825 }
1826
1827 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1828 {
1829         u32 data, tpr;
1830         int max_irr, max_isr;
1831         struct kvm_lapic *apic = vcpu->arch.apic;
1832
1833         apic_sync_pv_eoi_to_guest(vcpu, apic);
1834
1835         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
1836                 return;
1837
1838         tpr = kvm_apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1839         max_irr = apic_find_highest_irr(apic);
1840         if (max_irr < 0)
1841                 max_irr = 0;
1842         max_isr = apic_find_highest_isr(apic);
1843         if (max_isr < 0)
1844                 max_isr = 0;
1845         data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1846
1847         kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1848                                 sizeof(u32));
1849 }
1850
1851 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1852 {
1853         if (vapic_addr) {
1854                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
1855                                         &vcpu->arch.apic->vapic_cache,
1856                                         vapic_addr, sizeof(u32)))
1857                         return -EINVAL;
1858                 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1859         } else {
1860                 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
1861         }
1862
1863         vcpu->arch.apic->vapic_addr = vapic_addr;
1864         return 0;
1865 }
1866
1867 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1868 {
1869         struct kvm_lapic *apic = vcpu->arch.apic;
1870         u32 reg = (msr - APIC_BASE_MSR) << 4;
1871
1872         if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1873                 return 1;
1874
1875         /* if this is ICR write vector before command */
1876         if (msr == 0x830)
1877                 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1878         return apic_reg_write(apic, reg, (u32)data);
1879 }
1880
1881 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
1882 {
1883         struct kvm_lapic *apic = vcpu->arch.apic;
1884         u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
1885
1886         if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1887                 return 1;
1888
1889         if (apic_reg_read(apic, reg, 4, &low))
1890                 return 1;
1891         if (msr == 0x830)
1892                 apic_reg_read(apic, APIC_ICR2, 4, &high);
1893
1894         *data = (((u64)high) << 32) | low;
1895
1896         return 0;
1897 }
1898
1899 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
1900 {
1901         struct kvm_lapic *apic = vcpu->arch.apic;
1902
1903         if (!kvm_vcpu_has_lapic(vcpu))
1904                 return 1;
1905
1906         /* if this is ICR write vector before command */
1907         if (reg == APIC_ICR)
1908                 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1909         return apic_reg_write(apic, reg, (u32)data);
1910 }
1911
1912 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
1913 {
1914         struct kvm_lapic *apic = vcpu->arch.apic;
1915         u32 low, high = 0;
1916
1917         if (!kvm_vcpu_has_lapic(vcpu))
1918                 return 1;
1919
1920         if (apic_reg_read(apic, reg, 4, &low))
1921                 return 1;
1922         if (reg == APIC_ICR)
1923                 apic_reg_read(apic, APIC_ICR2, 4, &high);
1924
1925         *data = (((u64)high) << 32) | low;
1926
1927         return 0;
1928 }
1929
1930 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
1931 {
1932         u64 addr = data & ~KVM_MSR_ENABLED;
1933         if (!IS_ALIGNED(addr, 4))
1934                 return 1;
1935
1936         vcpu->arch.pv_eoi.msr_val = data;
1937         if (!pv_eoi_enabled(vcpu))
1938                 return 0;
1939         return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
1940                                          addr, sizeof(u8));
1941 }
1942
1943 void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
1944 {
1945         struct kvm_lapic *apic = vcpu->arch.apic;
1946         unsigned int sipi_vector;
1947         unsigned long pe;
1948
1949         if (!kvm_vcpu_has_lapic(vcpu) || !apic->pending_events)
1950                 return;
1951
1952         pe = xchg(&apic->pending_events, 0);
1953
1954         if (test_bit(KVM_APIC_INIT, &pe)) {
1955                 kvm_lapic_reset(vcpu);
1956                 kvm_vcpu_reset(vcpu);
1957                 if (kvm_vcpu_is_bsp(apic->vcpu))
1958                         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
1959                 else
1960                         vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
1961         }
1962         if (test_bit(KVM_APIC_SIPI, &pe) &&
1963             vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
1964                 /* evaluate pending_events before reading the vector */
1965                 smp_rmb();
1966                 sipi_vector = apic->sipi_vector;
1967                 apic_debug("vcpu %d received sipi with vector # %x\n",
1968                          vcpu->vcpu_id, sipi_vector);
1969                 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
1970                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
1971         }
1972 }
1973
1974 void kvm_lapic_init(void)
1975 {
1976         /* do not patch jump label more than once per second */
1977         jump_label_rate_limit(&apic_hw_disabled, HZ);
1978         jump_label_rate_limit(&apic_sw_disabled, HZ);
1979 }