arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22 #include "lapic.h"
  23
  24 #include <linux/kvm_host.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/mod_devicetable.h>
  32 #include <linux/trace_events.h>
  33 #include <linux/slab.h>
  34 #include <linux/tboot.h>
  35 #include <linux/hrtimer.h>
  36 #include "kvm_cache_regs.h"
  37 #include "x86.h"
  38
  39 #include <asm/cpu.h>
  40 #include <asm/io.h>
  41 #include <asm/desc.h>
  42 #include <asm/vmx.h>
  43 #include <asm/virtext.h>
  44 #include <asm/mce.h>
  45 #include <asm/fpu/internal.h>
  46 #include <asm/perf_event.h>
  47 #include <asm/debugreg.h>
  48 #include <asm/kexec.h>
  49 #include <asm/apic.h>
  50 #include <asm/irq_remapping.h>
  51
  52 #include "trace.h"
  53 #include "pmu.h"
  54
  55 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  56 #define __ex_clear(x, reg) \
  57         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  58
  59 MODULE_AUTHOR("Qumranet");
  60 MODULE_LICENSE("GPL");
  61
  62 static const struct x86_cpu_id vmx_cpu_id[] = {
  63         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  64         {}
  65 };
  66 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  67
  68 static bool __read_mostly enable_vpid = 1;
  69 module_param_named(vpid, enable_vpid, bool, 0444);
  70
  71 static bool __read_mostly flexpriority_enabled = 1;
  72 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  73
  74 static bool __read_mostly enable_ept = 1;
  75 module_param_named(ept, enable_ept, bool, S_IRUGO);
  76
  77 static bool __read_mostly enable_unrestricted_guest = 1;
  78 module_param_named(unrestricted_guest,
  79                         enable_unrestricted_guest, bool, S_IRUGO);
  80
  81 static bool __read_mostly enable_ept_ad_bits = 1;
  82 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  83
  84 static bool __read_mostly emulate_invalid_guest_state = true;
  85 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  86
  87 static bool __read_mostly vmm_exclusive = 1;
  88 module_param(vmm_exclusive, bool, S_IRUGO);
  89
  90 static bool __read_mostly fasteoi = 1;
  91 module_param(fasteoi, bool, S_IRUGO);
  92
  93 static bool __read_mostly enable_apicv = 1;
  94 module_param(enable_apicv, bool, S_IRUGO);
  95
  96 static bool __read_mostly enable_shadow_vmcs = 1;
  97 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  98 /*
  99  * If nested=1, nested virtualization is supported, i.e., guests may use
 100  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 101  * use VMX instructions.
 102  */
 103 static bool __read_mostly nested = 0;
 104 module_param(nested, bool, S_IRUGO);
 105
 106 static u64 __read_mostly host_xss;
 107
 108 static bool __read_mostly enable_pml = 1;
 109 module_param_named(pml, enable_pml, bool, S_IRUGO);
 110
 111 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 112
 113 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 114 static int __read_mostly cpu_preemption_timer_multi;
 115 static bool __read_mostly enable_preemption_timer = 1;
 116 #ifdef CONFIG_X86_64
 117 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 118 #endif
 119
 120 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 121 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 122 #define KVM_VM_CR0_ALWAYS_ON                                            \
 123         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 124 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 125         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 126          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 127
 128 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 129 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 130
 131 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 132
 133 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 134
 135 /*
 136  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 137  * ple_gap:    upper bound on the amount of time between two successive
 138  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 139  *             According to test, this time is usually smaller than 128 cycles.
 140  * ple_window: upper bound on the amount of time a guest is allowed to execute
 141  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 142  *             less than 2^12 cycles
 143  * Time is measured based on a counter that runs at the same rate as the TSC,
 144  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 145  */
 146 #define KVM_VMX_DEFAULT_PLE_GAP           128
 147 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 148 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 149 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 150 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 151                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 152
 153 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 154 module_param(ple_gap, int, S_IRUGO);
 155
 156 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 157 module_param(ple_window, int, S_IRUGO);
 158
 159 /* Default doubles per-vcpu window every exit. */
 160 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 161 module_param(ple_window_grow, int, S_IRUGO);
 162
 163 /* Default resets per-vcpu window every exit to ple_window. */
 164 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 165 module_param(ple_window_shrink, int, S_IRUGO);
 166
 167 /* Default is to compute the maximum so we can never overflow. */
 168 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 169 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 170 module_param(ple_window_max, int, S_IRUGO);
 171
 172 extern const ulong vmx_return;
 173
 174 #define NR_AUTOLOAD_MSRS 8
 175 #define VMCS02_POOL_SIZE 1
 176
 177 struct vmcs {
 178         u32 revision_id;
 179         u32 abort;
 180         char data[0];
 181 };
 182
 183 /*
 184  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 185  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 186  * loaded on this CPU (so we can clear them if the CPU goes down).
 187  */
 188 struct loaded_vmcs {
 189         struct vmcs *vmcs;
 190         int cpu;
 191         int launched;
 192         struct list_head loaded_vmcss_on_cpu_link;
 193 };
 194
 195 struct shared_msr_entry {
 196         unsigned index;
 197         u64 data;
 198         u64 mask;
 199 };
 200
 201 /*
 202  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 203  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 204  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 205  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 206  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 207  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 208  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 209  * underlying hardware which will be used to run L2.
 210  * This structure is packed to ensure that its layout is identical across
 211  * machines (necessary for live migration).
 212  * If there are changes in this struct, VMCS12_REVISION must be changed.
 213  */
 214 typedef u64 natural_width;
 215 struct __packed vmcs12 {
 216         /* According to the Intel spec, a VMCS region must start with the
 217          * following two fields. Then follow implementation-specific data.
 218          */
 219         u32 revision_id;
 220         u32 abort;
 221
 222         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 223         u32 padding[7]; /* room for future expansion */
 224
 225         u64 io_bitmap_a;
 226         u64 io_bitmap_b;
 227         u64 msr_bitmap;
 228         u64 vm_exit_msr_store_addr;
 229         u64 vm_exit_msr_load_addr;
 230         u64 vm_entry_msr_load_addr;
 231         u64 tsc_offset;
 232         u64 virtual_apic_page_addr;
 233         u64 apic_access_addr;
 234         u64 posted_intr_desc_addr;
 235         u64 ept_pointer;
 236         u64 eoi_exit_bitmap0;
 237         u64 eoi_exit_bitmap1;
 238         u64 eoi_exit_bitmap2;
 239         u64 eoi_exit_bitmap3;
 240         u64 xss_exit_bitmap;
 241         u64 guest_physical_address;
 242         u64 vmcs_link_pointer;
 243         u64 guest_ia32_debugctl;
 244         u64 guest_ia32_pat;
 245         u64 guest_ia32_efer;
 246         u64 guest_ia32_perf_global_ctrl;
 247         u64 guest_pdptr0;
 248         u64 guest_pdptr1;
 249         u64 guest_pdptr2;
 250         u64 guest_pdptr3;
 251         u64 guest_bndcfgs;
 252         u64 host_ia32_pat;
 253         u64 host_ia32_efer;
 254         u64 host_ia32_perf_global_ctrl;
 255         u64 padding64[8]; /* room for future expansion */
 256         /*
 257          * To allow migration of L1 (complete with its L2 guests) between
 258          * machines of different natural widths (32 or 64 bit), we cannot have
 259          * unsigned long fields with no explict size. We use u64 (aliased
 260          * natural_width) instead. Luckily, x86 is little-endian.
 261          */
 262         natural_width cr0_guest_host_mask;
 263         natural_width cr4_guest_host_mask;
 264         natural_width cr0_read_shadow;
 265         natural_width cr4_read_shadow;
 266         natural_width cr3_target_value0;
 267         natural_width cr3_target_value1;
 268         natural_width cr3_target_value2;
 269         natural_width cr3_target_value3;
 270         natural_width exit_qualification;
 271         natural_width guest_linear_address;
 272         natural_width guest_cr0;
 273         natural_width guest_cr3;
 274         natural_width guest_cr4;
 275         natural_width guest_es_base;
 276         natural_width guest_cs_base;
 277         natural_width guest_ss_base;
 278         natural_width guest_ds_base;
 279         natural_width guest_fs_base;
 280         natural_width guest_gs_base;
 281         natural_width guest_ldtr_base;
 282         natural_width guest_tr_base;
 283         natural_width guest_gdtr_base;
 284         natural_width guest_idtr_base;
 285         natural_width guest_dr7;
 286         natural_width guest_rsp;
 287         natural_width guest_rip;
 288         natural_width guest_rflags;
 289         natural_width guest_pending_dbg_exceptions;
 290         natural_width guest_sysenter_esp;
 291         natural_width guest_sysenter_eip;
 292         natural_width host_cr0;
 293         natural_width host_cr3;
 294         natural_width host_cr4;
 295         natural_width host_fs_base;
 296         natural_width host_gs_base;
 297         natural_width host_tr_base;
 298         natural_width host_gdtr_base;
 299         natural_width host_idtr_base;
 300         natural_width host_ia32_sysenter_esp;
 301         natural_width host_ia32_sysenter_eip;
 302         natural_width host_rsp;
 303         natural_width host_rip;
 304         natural_width paddingl[8]; /* room for future expansion */
 305         u32 pin_based_vm_exec_control;
 306         u32 cpu_based_vm_exec_control;
 307         u32 exception_bitmap;
 308         u32 page_fault_error_code_mask;
 309         u32 page_fault_error_code_match;
 310         u32 cr3_target_count;
 311         u32 vm_exit_controls;
 312         u32 vm_exit_msr_store_count;
 313         u32 vm_exit_msr_load_count;
 314         u32 vm_entry_controls;
 315         u32 vm_entry_msr_load_count;
 316         u32 vm_entry_intr_info_field;
 317         u32 vm_entry_exception_error_code;
 318         u32 vm_entry_instruction_len;
 319         u32 tpr_threshold;
 320         u32 secondary_vm_exec_control;
 321         u32 vm_instruction_error;
 322         u32 vm_exit_reason;
 323         u32 vm_exit_intr_info;
 324         u32 vm_exit_intr_error_code;
 325         u32 idt_vectoring_info_field;
 326         u32 idt_vectoring_error_code;
 327         u32 vm_exit_instruction_len;
 328         u32 vmx_instruction_info;
 329         u32 guest_es_limit;
 330         u32 guest_cs_limit;
 331         u32 guest_ss_limit;
 332         u32 guest_ds_limit;
 333         u32 guest_fs_limit;
 334         u32 guest_gs_limit;
 335         u32 guest_ldtr_limit;
 336         u32 guest_tr_limit;
 337         u32 guest_gdtr_limit;
 338         u32 guest_idtr_limit;
 339         u32 guest_es_ar_bytes;
 340         u32 guest_cs_ar_bytes;
 341         u32 guest_ss_ar_bytes;
 342         u32 guest_ds_ar_bytes;
 343         u32 guest_fs_ar_bytes;
 344         u32 guest_gs_ar_bytes;
 345         u32 guest_ldtr_ar_bytes;
 346         u32 guest_tr_ar_bytes;
 347         u32 guest_interruptibility_info;
 348         u32 guest_activity_state;
 349         u32 guest_sysenter_cs;
 350         u32 host_ia32_sysenter_cs;
 351         u32 vmx_preemption_timer_value;
 352         u32 padding32[7]; /* room for future expansion */
 353         u16 virtual_processor_id;
 354         u16 posted_intr_nv;
 355         u16 guest_es_selector;
 356         u16 guest_cs_selector;
 357         u16 guest_ss_selector;
 358         u16 guest_ds_selector;
 359         u16 guest_fs_selector;
 360         u16 guest_gs_selector;
 361         u16 guest_ldtr_selector;
 362         u16 guest_tr_selector;
 363         u16 guest_intr_status;
 364         u16 host_es_selector;
 365         u16 host_cs_selector;
 366         u16 host_ss_selector;
 367         u16 host_ds_selector;
 368         u16 host_fs_selector;
 369         u16 host_gs_selector;
 370         u16 host_tr_selector;
 371 };
 372
 373 /*
 374  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 375  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 376  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 377  */
 378 #define VMCS12_REVISION 0x11e57ed0
 379
 380 /*
 381  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 382  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 383  * current implementation, 4K are reserved to avoid future complications.
 384  */
 385 #define VMCS12_SIZE 0x1000
 386
 387 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 388 struct vmcs02_list {
 389         struct list_head list;
 390         gpa_t vmptr;
 391         struct loaded_vmcs vmcs02;
 392 };
 393
 394 /*
 395  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 396  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 397  */
 398 struct nested_vmx {
 399         /* Has the level1 guest done vmxon? */
 400         bool vmxon;
 401         gpa_t vmxon_ptr;
 402
 403         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 404         gpa_t current_vmptr;
 405         /* The host-usable pointer to the above */
 406         struct page *current_vmcs12_page;
 407         struct vmcs12 *current_vmcs12;
 408         /*
 409          * Cache of the guest's VMCS, existing outside of guest memory.
 410          * Loaded from guest memory during VMPTRLD. Flushed to guest
 411          * memory during VMXOFF, VMCLEAR, VMPTRLD.
 412          */
 413         struct vmcs12 *cached_vmcs12;
 414         struct vmcs *current_shadow_vmcs;
 415         /*
 416          * Indicates if the shadow vmcs must be updated with the
 417          * data hold by vmcs12
 418          */
 419         bool sync_shadow_vmcs;
 420
 421         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 422         struct list_head vmcs02_pool;
 423         int vmcs02_num;
 424         u64 vmcs01_tsc_offset;
 425         /* L2 must run next, and mustn't decide to exit to L1. */
 426         bool nested_run_pending;
 427         /*
 428          * Guest pages referred to in vmcs02 with host-physical pointers, so
 429          * we must keep them pinned while L2 runs.
 430          */
 431         struct page *apic_access_page;
 432         struct page *virtual_apic_page;
 433         struct page *pi_desc_page;
 434         struct pi_desc *pi_desc;
 435         bool pi_pending;
 436         u16 posted_intr_nv;
 437
 438         struct hrtimer preemption_timer;
 439         bool preemption_timer_expired;
 440
 441         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 442         u64 vmcs01_debugctl;
 443
 444         u16 vpid02;
 445         u16 last_vpid;
 446
 447         u32 nested_vmx_procbased_ctls_low;
 448         u32 nested_vmx_procbased_ctls_high;
 449         u32 nested_vmx_true_procbased_ctls_low;
 450         u32 nested_vmx_secondary_ctls_low;
 451         u32 nested_vmx_secondary_ctls_high;
 452         u32 nested_vmx_pinbased_ctls_low;
 453         u32 nested_vmx_pinbased_ctls_high;
 454         u32 nested_vmx_exit_ctls_low;
 455         u32 nested_vmx_exit_ctls_high;
 456         u32 nested_vmx_true_exit_ctls_low;
 457         u32 nested_vmx_entry_ctls_low;
 458         u32 nested_vmx_entry_ctls_high;
 459         u32 nested_vmx_true_entry_ctls_low;
 460         u32 nested_vmx_misc_low;
 461         u32 nested_vmx_misc_high;
 462         u32 nested_vmx_ept_caps;
 463         u32 nested_vmx_vpid_caps;
 464 };
 465
 466 #define POSTED_INTR_ON  0
 467 #define POSTED_INTR_SN  1
 468
 469 /* Posted-Interrupt Descriptor */
 470 struct pi_desc {
 471         u32 pir[8];     /* Posted interrupt requested */
 472         union {
 473                 struct {
 474                                 /* bit 256 - Outstanding Notification */
 475                         u16     on      : 1,
 476                                 /* bit 257 - Suppress Notification */
 477                                 sn      : 1,
 478                                 /* bit 271:258 - Reserved */
 479                                 rsvd_1  : 14;
 480                                 /* bit 279:272 - Notification Vector */
 481                         u8      nv;
 482                                 /* bit 287:280 - Reserved */
 483                         u8      rsvd_2;
 484                                 /* bit 319:288 - Notification Destination */
 485                         u32     ndst;
 486                 };
 487                 u64 control;
 488         };
 489         u32 rsvd[6];
 490 } __aligned(64);
 491
 492 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 493 {
 494         return test_and_set_bit(POSTED_INTR_ON,
 495                         (unsigned long *)&pi_desc->control);
 496 }
 497
 498 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 499 {
 500         return test_and_clear_bit(POSTED_INTR_ON,
 501                         (unsigned long *)&pi_desc->control);
 502 }
 503
 504 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 505 {
 506         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 507 }
 508
 509 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 510 {
 511         return clear_bit(POSTED_INTR_SN,
 512                         (unsigned long *)&pi_desc->control);
 513 }
 514
 515 static inline void pi_set_sn(struct pi_desc *pi_desc)
 516 {
 517         return set_bit(POSTED_INTR_SN,
 518                         (unsigned long *)&pi_desc->control);
 519 }
 520
 521 static inline int pi_test_on(struct pi_desc *pi_desc)
 522 {
 523         return test_bit(POSTED_INTR_ON,
 524                         (unsigned long *)&pi_desc->control);
 525 }
 526
 527 static inline int pi_test_sn(struct pi_desc *pi_desc)
 528 {
 529         return test_bit(POSTED_INTR_SN,
 530                         (unsigned long *)&pi_desc->control);
 531 }
 532
 533 struct vcpu_vmx {
 534         struct kvm_vcpu       vcpu;
 535         unsigned long         host_rsp;
 536         u8                    fail;
 537         bool                  nmi_known_unmasked;
 538         u32                   exit_intr_info;
 539         u32                   idt_vectoring_info;
 540         ulong                 rflags;
 541         struct shared_msr_entry *guest_msrs;
 542         int                   nmsrs;
 543         int                   save_nmsrs;
 544         unsigned long         host_idt_base;
 545 #ifdef CONFIG_X86_64
 546         u64                   msr_host_kernel_gs_base;
 547         u64                   msr_guest_kernel_gs_base;
 548 #endif
 549         u32 vm_entry_controls_shadow;
 550         u32 vm_exit_controls_shadow;
 551         /*
 552          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 553          * non-nested (L1) guest, it always points to vmcs01. For a nested
 554          * guest (L2), it points to a different VMCS.
 555          */
 556         struct loaded_vmcs    vmcs01;
 557         struct loaded_vmcs   *loaded_vmcs;
 558         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 559         struct msr_autoload {
 560                 unsigned nr;
 561                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 562                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 563         } msr_autoload;
 564         struct {
 565                 int           loaded;
 566                 u16           fs_sel, gs_sel, ldt_sel;
 567 #ifdef CONFIG_X86_64
 568                 u16           ds_sel, es_sel;
 569 #endif
 570                 int           gs_ldt_reload_needed;
 571                 int           fs_reload_needed;
 572                 u64           msr_host_bndcfgs;
 573                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 574         } host_state;
 575         struct {
 576                 int vm86_active;
 577                 ulong save_rflags;
 578                 struct kvm_segment segs[8];
 579         } rmode;
 580         struct {
 581                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 582                 struct kvm_save_segment {
 583                         u16 selector;
 584                         unsigned long base;
 585                         u32 limit;
 586                         u32 ar;
 587                 } seg[8];
 588         } segment_cache;
 589         int vpid;
 590         bool emulation_required;
 591
 592         /* Support for vnmi-less CPUs */
 593         int soft_vnmi_blocked;
 594         ktime_t entry_time;
 595         s64 vnmi_blocked_time;
 596         u32 exit_reason;
 597
 598         /* Posted interrupt descriptor */
 599         struct pi_desc pi_desc;
 600
 601         /* Support for a guest hypervisor (nested VMX) */
 602         struct nested_vmx nested;
 603
 604         /* Dynamic PLE window. */
 605         int ple_window;
 606         bool ple_window_dirty;
 607
 608         /* Support for PML */
 609 #define PML_ENTITY_NUM          512
 610         struct page *pml_pg;
 611
 612         /* apic deadline value in host tsc */
 613         u64 hv_deadline_tsc;
 614
 615         u64 current_tsc_ratio;
 616
 617         bool guest_pkru_valid;
 618         u32 guest_pkru;
 619         u32 host_pkru;
 620
 621         /*
 622          * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
 623          * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
 624          * in msr_ia32_feature_control_valid_bits.
 625          */
 626         u64 msr_ia32_feature_control;
 627         u64 msr_ia32_feature_control_valid_bits;
 628 };
 629
 630 enum segment_cache_field {
 631         SEG_FIELD_SEL = 0,
 632         SEG_FIELD_BASE = 1,
 633         SEG_FIELD_LIMIT = 2,
 634         SEG_FIELD_AR = 3,
 635
 636         SEG_FIELD_NR = 4
 637 };
 638
 639 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 640 {
 641         return container_of(vcpu, struct vcpu_vmx, vcpu);
 642 }
 643
 644 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 645 {
 646         return &(to_vmx(vcpu)->pi_desc);
 647 }
 648
 649 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 650 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 651 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 652                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 653
 654
 655 static unsigned long shadow_read_only_fields[] = {
 656         /*
 657          * We do NOT shadow fields that are modified when L0
 658          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 659          * VMXON...) executed by L1.
 660          * For example, VM_INSTRUCTION_ERROR is read
 661          * by L1 if a vmx instruction fails (part of the error path).
 662          * Note the code assumes this logic. If for some reason
 663          * we start shadowing these fields then we need to
 664          * force a shadow sync when L0 emulates vmx instructions
 665          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 666          * by nested_vmx_failValid)
 667          */
 668         VM_EXIT_REASON,
 669         VM_EXIT_INTR_INFO,
 670         VM_EXIT_INSTRUCTION_LEN,
 671         IDT_VECTORING_INFO_FIELD,
 672         IDT_VECTORING_ERROR_CODE,
 673         VM_EXIT_INTR_ERROR_CODE,
 674         EXIT_QUALIFICATION,
 675         GUEST_LINEAR_ADDRESS,
 676         GUEST_PHYSICAL_ADDRESS
 677 };
 678 static int max_shadow_read_only_fields =
 679         ARRAY_SIZE(shadow_read_only_fields);
 680
 681 static unsigned long shadow_read_write_fields[] = {
 682         TPR_THRESHOLD,
 683         GUEST_RIP,
 684         GUEST_RSP,
 685         GUEST_CR0,
 686         GUEST_CR3,
 687         GUEST_CR4,
 688         GUEST_INTERRUPTIBILITY_INFO,
 689         GUEST_RFLAGS,
 690         GUEST_CS_SELECTOR,
 691         GUEST_CS_AR_BYTES,
 692         GUEST_CS_LIMIT,
 693         GUEST_CS_BASE,
 694         GUEST_ES_BASE,
 695         GUEST_BNDCFGS,
 696         CR0_GUEST_HOST_MASK,
 697         CR0_READ_SHADOW,
 698         CR4_READ_SHADOW,
 699         TSC_OFFSET,
 700         EXCEPTION_BITMAP,
 701         CPU_BASED_VM_EXEC_CONTROL,
 702         VM_ENTRY_EXCEPTION_ERROR_CODE,
 703         VM_ENTRY_INTR_INFO_FIELD,
 704         VM_ENTRY_INSTRUCTION_LEN,
 705         VM_ENTRY_EXCEPTION_ERROR_CODE,
 706         HOST_FS_BASE,
 707         HOST_GS_BASE,
 708         HOST_FS_SELECTOR,
 709         HOST_GS_SELECTOR
 710 };
 711 static int max_shadow_read_write_fields =
 712         ARRAY_SIZE(shadow_read_write_fields);
 713
 714 static const unsigned short vmcs_field_to_offset_table[] = {
 715         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 716         FIELD(POSTED_INTR_NV, posted_intr_nv),
 717         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 718         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 719         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 720         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 721         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 722         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 723         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 724         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 725         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 726         FIELD(HOST_ES_SELECTOR, host_es_selector),
 727         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 728         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 729         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 730         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 731         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 732         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 733         FIELD64(IO_BITMAP_A, io_bitmap_a),
 734         FIELD64(IO_BITMAP_B, io_bitmap_b),
 735         FIELD64(MSR_BITMAP, msr_bitmap),
 736         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 737         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 738         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 739         FIELD64(TSC_OFFSET, tsc_offset),
 740         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 741         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 742         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 743         FIELD64(EPT_POINTER, ept_pointer),
 744         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 745         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 746         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 747         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 748         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 749         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 750         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 751         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 752         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 753         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 754         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 755         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 756         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 757         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 758         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 759         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 760         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 761         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 762         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 763         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 764         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 765         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 766         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 767         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 768         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 769         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 770         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 771         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 772         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 773         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 774         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 775         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 776         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 777         FIELD(TPR_THRESHOLD, tpr_threshold),
 778         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 779         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 780         FIELD(VM_EXIT_REASON, vm_exit_reason),
 781         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 782         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 783         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 784         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 785         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 786         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 787         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 788         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 789         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 790         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 791         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 792         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 793         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 794         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 795         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 796         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 797         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 798         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 799         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 800         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 801         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 802         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 803         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 804         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 805         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 806         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 807         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 808         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 809         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 810         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 811         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 812         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 813         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 814         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 815         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 816         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 817         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 818         FIELD(EXIT_QUALIFICATION, exit_qualification),
 819         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 820         FIELD(GUEST_CR0, guest_cr0),
 821         FIELD(GUEST_CR3, guest_cr3),
 822         FIELD(GUEST_CR4, guest_cr4),
 823         FIELD(GUEST_ES_BASE, guest_es_base),
 824         FIELD(GUEST_CS_BASE, guest_cs_base),
 825         FIELD(GUEST_SS_BASE, guest_ss_base),
 826         FIELD(GUEST_DS_BASE, guest_ds_base),
 827         FIELD(GUEST_FS_BASE, guest_fs_base),
 828         FIELD(GUEST_GS_BASE, guest_gs_base),
 829         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 830         FIELD(GUEST_TR_BASE, guest_tr_base),
 831         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 832         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 833         FIELD(GUEST_DR7, guest_dr7),
 834         FIELD(GUEST_RSP, guest_rsp),
 835         FIELD(GUEST_RIP, guest_rip),
 836         FIELD(GUEST_RFLAGS, guest_rflags),
 837         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 838         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 839         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 840         FIELD(HOST_CR0, host_cr0),
 841         FIELD(HOST_CR3, host_cr3),
 842         FIELD(HOST_CR4, host_cr4),
 843         FIELD(HOST_FS_BASE, host_fs_base),
 844         FIELD(HOST_GS_BASE, host_gs_base),
 845         FIELD(HOST_TR_BASE, host_tr_base),
 846         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 847         FIELD(HOST_IDTR_BASE, host_idtr_base),
 848         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 849         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 850         FIELD(HOST_RSP, host_rsp),
 851         FIELD(HOST_RIP, host_rip),
 852 };
 853
 854 static inline short vmcs_field_to_offset(unsigned long field)
 855 {
 856         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 857
 858         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 859             vmcs_field_to_offset_table[field] == 0)
 860                 return -ENOENT;
 861
 862         return vmcs_field_to_offset_table[field];
 863 }
 864
 865 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 866 {
 867         return to_vmx(vcpu)->nested.cached_vmcs12;
 868 }
 869
 870 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 871 {
 872         struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
 873         if (is_error_page(page))
 874                 return NULL;
 875
 876         return page;
 877 }
 878
 879 static void nested_release_page(struct page *page)
 880 {
 881         kvm_release_page_dirty(page);
 882 }
 883
 884 static void nested_release_page_clean(struct page *page)
 885 {
 886         kvm_release_page_clean(page);
 887 }
 888
 889 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 890 static u64 construct_eptp(unsigned long root_hpa);
 891 static void kvm_cpu_vmxon(u64 addr);
 892 static void kvm_cpu_vmxoff(void);
 893 static bool vmx_xsaves_supported(void);
 894 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 895 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 896                             struct kvm_segment *var, int seg);
 897 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 898                             struct kvm_segment *var, int seg);
 899 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 900 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 901 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 902 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 903 static int alloc_identity_pagetable(struct kvm *kvm);
 904
 905 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 906 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 907 /*
 908  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 909  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 910  */
 911 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 912 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 913
 914 /*
 915  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 916  * can find which vCPU should be waken up.
 917  */
 918 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 919 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 920
 921 static unsigned long *vmx_io_bitmap_a;
 922 static unsigned long *vmx_io_bitmap_b;
 923 static unsigned long *vmx_msr_bitmap_legacy;
 924 static unsigned long *vmx_msr_bitmap_longmode;
 925 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 926 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 927 static unsigned long *vmx_msr_bitmap_nested;
 928 static unsigned long *vmx_vmread_bitmap;
 929 static unsigned long *vmx_vmwrite_bitmap;
 930
 931 static bool cpu_has_load_ia32_efer;
 932 static bool cpu_has_load_perf_global_ctrl;
 933
 934 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 935 static DEFINE_SPINLOCK(vmx_vpid_lock);
 936
 937 static struct vmcs_config {
 938         int size;
 939         int order;
 940         u32 revision_id;
 941         u32 pin_based_exec_ctrl;
 942         u32 cpu_based_exec_ctrl;
 943         u32 cpu_based_2nd_exec_ctrl;
 944         u32 vmexit_ctrl;
 945         u32 vmentry_ctrl;
 946 } vmcs_config;
 947
 948 static struct vmx_capability {
 949         u32 ept;
 950         u32 vpid;
 951 } vmx_capability;
 952
 953 #define VMX_SEGMENT_FIELD(seg)                                  \
 954         [VCPU_SREG_##seg] = {                                   \
 955                 .selector = GUEST_##seg##_SELECTOR,             \
 956                 .base = GUEST_##seg##_BASE,                     \
 957                 .limit = GUEST_##seg##_LIMIT,                   \
 958                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 959         }
 960
 961 static const struct kvm_vmx_segment_field {
 962         unsigned selector;
 963         unsigned base;
 964         unsigned limit;
 965         unsigned ar_bytes;
 966 } kvm_vmx_segment_fields[] = {
 967         VMX_SEGMENT_FIELD(CS),
 968         VMX_SEGMENT_FIELD(DS),
 969         VMX_SEGMENT_FIELD(ES),
 970         VMX_SEGMENT_FIELD(FS),
 971         VMX_SEGMENT_FIELD(GS),
 972         VMX_SEGMENT_FIELD(SS),
 973         VMX_SEGMENT_FIELD(TR),
 974         VMX_SEGMENT_FIELD(LDTR),
 975 };
 976
 977 static u64 host_efer;
 978
 979 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 980
 981 /*
 982  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 983  * away by decrementing the array size.
 984  */
 985 static const u32 vmx_msr_index[] = {
 986 #ifdef CONFIG_X86_64
 987         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 988 #endif
 989         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 990 };
 991
 992 static inline bool is_exception_n(u32 intr_info, u8 vector)
 993 {
 994         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 995                              INTR_INFO_VALID_MASK)) ==
 996                 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
 997 }
 998
 999 static inline bool is_debug(u32 intr_info)
1000 {
1001         return is_exception_n(intr_info, DB_VECTOR);
1002 }
1003
1004 static inline bool is_breakpoint(u32 intr_info)
1005 {
1006         return is_exception_n(intr_info, BP_VECTOR);
1007 }
1008
1009 static inline bool is_page_fault(u32 intr_info)
1010 {
1011         return is_exception_n(intr_info, PF_VECTOR);
1012 }
1013
1014 static inline bool is_no_device(u32 intr_info)
1015 {
1016         return is_exception_n(intr_info, NM_VECTOR);
1017 }
1018
1019 static inline bool is_invalid_opcode(u32 intr_info)
1020 {
1021         return is_exception_n(intr_info, UD_VECTOR);
1022 }
1023
1024 static inline bool is_external_interrupt(u32 intr_info)
1025 {
1026         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1027                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1028 }
1029
1030 static inline bool is_machine_check(u32 intr_info)
1031 {
1032         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1033                              INTR_INFO_VALID_MASK)) ==
1034                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1035 }
1036
1037 static inline bool cpu_has_vmx_msr_bitmap(void)
1038 {
1039         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1040 }
1041
1042 static inline bool cpu_has_vmx_tpr_shadow(void)
1043 {
1044         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1045 }
1046
1047 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1048 {
1049         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1050 }
1051
1052 static inline bool cpu_has_secondary_exec_ctrls(void)
1053 {
1054         return vmcs_config.cpu_based_exec_ctrl &
1055                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1056 }
1057
1058 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1059 {
1060         return vmcs_config.cpu_based_2nd_exec_ctrl &
1061                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1062 }
1063
1064 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1065 {
1066         return vmcs_config.cpu_based_2nd_exec_ctrl &
1067                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1068 }
1069
1070 static inline bool cpu_has_vmx_apic_register_virt(void)
1071 {
1072         return vmcs_config.cpu_based_2nd_exec_ctrl &
1073                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1074 }
1075
1076 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1077 {
1078         return vmcs_config.cpu_based_2nd_exec_ctrl &
1079                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1080 }
1081
1082 /*
1083  * Comment's format: document - errata name - stepping - processor name.
1084  * Refer from
1085  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1086  */
1087 static u32 vmx_preemption_cpu_tfms[] = {
1088 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
1089 0x000206E6,
1090 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
1091 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1092 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1093 0x00020652,
1094 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1095 0x00020655,
1096 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
1097 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
1098 /*
1099  * 320767.pdf - AAP86  - B1 -
1100  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1101  */
1102 0x000106E5,
1103 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1104 0x000106A0,
1105 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1106 0x000106A1,
1107 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1108 0x000106A4,
1109  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1110  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1111  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1112 0x000106A5,
1113 };
1114
1115 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1116 {
1117         u32 eax = cpuid_eax(0x00000001), i;
1118
1119         /* Clear the reserved bits */
1120         eax &= ~(0x3U << 14 | 0xfU << 28);
1121         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1122                 if (eax == vmx_preemption_cpu_tfms[i])
1123                         return true;
1124
1125         return false;
1126 }
1127
1128 static inline bool cpu_has_vmx_preemption_timer(void)
1129 {
1130         return vmcs_config.pin_based_exec_ctrl &
1131                 PIN_BASED_VMX_PREEMPTION_TIMER;
1132 }
1133
1134 static inline bool cpu_has_vmx_posted_intr(void)
1135 {
1136         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1137                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1138 }
1139
1140 static inline bool cpu_has_vmx_apicv(void)
1141 {
1142         return cpu_has_vmx_apic_register_virt() &&
1143                 cpu_has_vmx_virtual_intr_delivery() &&
1144                 cpu_has_vmx_posted_intr();
1145 }
1146
1147 static inline bool cpu_has_vmx_flexpriority(void)
1148 {
1149         return cpu_has_vmx_tpr_shadow() &&
1150                 cpu_has_vmx_virtualize_apic_accesses();
1151 }
1152
1153 static inline bool cpu_has_vmx_ept_execute_only(void)
1154 {
1155         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1156 }
1157
1158 static inline bool cpu_has_vmx_ept_2m_page(void)
1159 {
1160         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1161 }
1162
1163 static inline bool cpu_has_vmx_ept_1g_page(void)
1164 {
1165         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1166 }
1167
1168 static inline bool cpu_has_vmx_ept_4levels(void)
1169 {
1170         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1171 }
1172
1173 static inline bool cpu_has_vmx_ept_ad_bits(void)
1174 {
1175         return vmx_capability.ept & VMX_EPT_AD_BIT;
1176 }
1177
1178 static inline bool cpu_has_vmx_invept_context(void)
1179 {
1180         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1181 }
1182
1183 static inline bool cpu_has_vmx_invept_global(void)
1184 {
1185         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1186 }
1187
1188 static inline bool cpu_has_vmx_invvpid_single(void)
1189 {
1190         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1191 }
1192
1193 static inline bool cpu_has_vmx_invvpid_global(void)
1194 {
1195         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1196 }
1197
1198 static inline bool cpu_has_vmx_ept(void)
1199 {
1200         return vmcs_config.cpu_based_2nd_exec_ctrl &
1201                 SECONDARY_EXEC_ENABLE_EPT;
1202 }
1203
1204 static inline bool cpu_has_vmx_unrestricted_guest(void)
1205 {
1206         return vmcs_config.cpu_based_2nd_exec_ctrl &
1207                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1208 }
1209
1210 static inline bool cpu_has_vmx_ple(void)
1211 {
1212         return vmcs_config.cpu_based_2nd_exec_ctrl &
1213                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1214 }
1215
1216 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1217 {
1218         return flexpriority_enabled && lapic_in_kernel(vcpu);
1219 }
1220
1221 static inline bool cpu_has_vmx_vpid(void)
1222 {
1223         return vmcs_config.cpu_based_2nd_exec_ctrl &
1224                 SECONDARY_EXEC_ENABLE_VPID;
1225 }
1226
1227 static inline bool cpu_has_vmx_rdtscp(void)
1228 {
1229         return vmcs_config.cpu_based_2nd_exec_ctrl &
1230                 SECONDARY_EXEC_RDTSCP;
1231 }
1232
1233 static inline bool cpu_has_vmx_invpcid(void)
1234 {
1235         return vmcs_config.cpu_based_2nd_exec_ctrl &
1236                 SECONDARY_EXEC_ENABLE_INVPCID;
1237 }
1238
1239 static inline bool cpu_has_virtual_nmis(void)
1240 {
1241         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1242 }
1243
1244 static inline bool cpu_has_vmx_wbinvd_exit(void)
1245 {
1246         return vmcs_config.cpu_based_2nd_exec_ctrl &
1247                 SECONDARY_EXEC_WBINVD_EXITING;
1248 }
1249
1250 static inline bool cpu_has_vmx_shadow_vmcs(void)
1251 {
1252         u64 vmx_msr;
1253         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1254         /* check if the cpu supports writing r/o exit information fields */
1255         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1256                 return false;
1257
1258         return vmcs_config.cpu_based_2nd_exec_ctrl &
1259                 SECONDARY_EXEC_SHADOW_VMCS;
1260 }
1261
1262 static inline bool cpu_has_vmx_pml(void)
1263 {
1264         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1265 }
1266
1267 static inline bool cpu_has_vmx_tsc_scaling(void)
1268 {
1269         return vmcs_config.cpu_based_2nd_exec_ctrl &
1270                 SECONDARY_EXEC_TSC_SCALING;
1271 }
1272
1273 static inline bool report_flexpriority(void)
1274 {
1275         return flexpriority_enabled;
1276 }
1277
1278 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1279 {
1280         return vmcs12->cpu_based_vm_exec_control & bit;
1281 }
1282
1283 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1284 {
1285         return (vmcs12->cpu_based_vm_exec_control &
1286                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1287                 (vmcs12->secondary_vm_exec_control & bit);
1288 }
1289
1290 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1291 {
1292         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1293 }
1294
1295 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1296 {
1297         return vmcs12->pin_based_vm_exec_control &
1298                 PIN_BASED_VMX_PREEMPTION_TIMER;
1299 }
1300
1301 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1302 {
1303         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1304 }
1305
1306 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1307 {
1308         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1309                 vmx_xsaves_supported();
1310 }
1311
1312 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1313 {
1314         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1315 }
1316
1317 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1318 {
1319         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1320 }
1321
1322 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1323 {
1324         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1325 }
1326
1327 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1328 {
1329         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1330 }
1331
1332 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1333 {
1334         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1335 }
1336
1337 static inline bool is_exception(u32 intr_info)
1338 {
1339         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1340                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1341 }
1342
1343 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1344                               u32 exit_intr_info,
1345                               unsigned long exit_qualification);
1346 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1347                         struct vmcs12 *vmcs12,
1348                         u32 reason, unsigned long qualification);
1349
1350 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1351 {
1352         int i;
1353
1354         for (i = 0; i < vmx->nmsrs; ++i)
1355                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1356                         return i;
1357         return -1;
1358 }
1359
1360 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1361 {
1362     struct {
1363         u64 vpid : 16;
1364         u64 rsvd : 48;
1365         u64 gva;
1366     } operand = { vpid, 0, gva };
1367
1368     asm volatile (__ex(ASM_VMX_INVVPID)
1369                   /* CF==1 or ZF==1 --> rc = -1 */
1370                   "; ja 1f ; ud2 ; 1:"
1371                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1372 }
1373
1374 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1375 {
1376         struct {
1377                 u64 eptp, gpa;
1378         } operand = {eptp, gpa};
1379
1380         asm volatile (__ex(ASM_VMX_INVEPT)
1381                         /* CF==1 or ZF==1 --> rc = -1 */
1382                         "; ja 1f ; ud2 ; 1:\n"
1383                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1384 }
1385
1386 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1387 {
1388         int i;
1389
1390         i = __find_msr_index(vmx, msr);
1391         if (i >= 0)
1392                 return &vmx->guest_msrs[i];
1393         return NULL;
1394 }
1395
1396 static void vmcs_clear(struct vmcs *vmcs)
1397 {
1398         u64 phys_addr = __pa(vmcs);
1399         u8 error;
1400
1401         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1402                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1403                       : "cc", "memory");
1404         if (error)
1405                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1406                        vmcs, phys_addr);
1407 }
1408
1409 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1410 {
1411         vmcs_clear(loaded_vmcs->vmcs);
1412         loaded_vmcs->cpu = -1;
1413         loaded_vmcs->launched = 0;
1414 }
1415
1416 static void vmcs_load(struct vmcs *vmcs)
1417 {
1418         u64 phys_addr = __pa(vmcs);
1419         u8 error;
1420
1421         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1422                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1423                         : "cc", "memory");
1424         if (error)
1425                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1426                        vmcs, phys_addr);
1427 }
1428
1429 #ifdef CONFIG_KEXEC_CORE
1430 /*
1431  * This bitmap is used to indicate whether the vmclear
1432  * operation is enabled on all cpus. All disabled by
1433  * default.
1434  */
1435 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1436
1437 static inline void crash_enable_local_vmclear(int cpu)
1438 {
1439         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1440 }
1441
1442 static inline void crash_disable_local_vmclear(int cpu)
1443 {
1444         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1445 }
1446
1447 static inline int crash_local_vmclear_enabled(int cpu)
1448 {
1449         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1450 }
1451
1452 static void crash_vmclear_local_loaded_vmcss(void)
1453 {
1454         int cpu = raw_smp_processor_id();
1455         struct loaded_vmcs *v;
1456
1457         if (!crash_local_vmclear_enabled(cpu))
1458                 return;
1459
1460         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1461                             loaded_vmcss_on_cpu_link)
1462                 vmcs_clear(v->vmcs);
1463 }
1464 #else
1465 static inline void crash_enable_local_vmclear(int cpu) { }
1466 static inline void crash_disable_local_vmclear(int cpu) { }
1467 #endif /* CONFIG_KEXEC_CORE */
1468
1469 static void __loaded_vmcs_clear(void *arg)
1470 {
1471         struct loaded_vmcs *loaded_vmcs = arg;
1472         int cpu = raw_smp_processor_id();
1473
1474         if (loaded_vmcs->cpu != cpu)
1475                 return; /* vcpu migration can race with cpu offline */
1476         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1477                 per_cpu(current_vmcs, cpu) = NULL;
1478         crash_disable_local_vmclear(cpu);
1479         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1480
1481         /*
1482          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1483          * is before setting loaded_vmcs->vcpu to -1 which is done in
1484          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1485          * then adds the vmcs into percpu list before it is deleted.
1486          */
1487         smp_wmb();
1488
1489         loaded_vmcs_init(loaded_vmcs);
1490         crash_enable_local_vmclear(cpu);
1491 }
1492
1493 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1494 {
1495         int cpu = loaded_vmcs->cpu;
1496
1497         if (cpu != -1)
1498                 smp_call_function_single(cpu,
1499                          __loaded_vmcs_clear, loaded_vmcs, 1);
1500 }
1501
1502 static inline void vpid_sync_vcpu_single(int vpid)
1503 {
1504         if (vpid == 0)
1505                 return;
1506
1507         if (cpu_has_vmx_invvpid_single())
1508                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1509 }
1510
1511 static inline void vpid_sync_vcpu_global(void)
1512 {
1513         if (cpu_has_vmx_invvpid_global())
1514                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1515 }
1516
1517 static inline void vpid_sync_context(int vpid)
1518 {
1519         if (cpu_has_vmx_invvpid_single())
1520                 vpid_sync_vcpu_single(vpid);
1521         else
1522                 vpid_sync_vcpu_global();
1523 }
1524
1525 static inline void ept_sync_global(void)
1526 {
1527         if (cpu_has_vmx_invept_global())
1528                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1529 }
1530
1531 static inline void ept_sync_context(u64 eptp)
1532 {
1533         if (enable_ept) {
1534                 if (cpu_has_vmx_invept_context())
1535                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1536                 else
1537                         ept_sync_global();
1538         }
1539 }
1540
1541 static __always_inline void vmcs_check16(unsigned long field)
1542 {
1543         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1544                          "16-bit accessor invalid for 64-bit field");
1545         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1546                          "16-bit accessor invalid for 64-bit high field");
1547         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1548                          "16-bit accessor invalid for 32-bit high field");
1549         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1550                          "16-bit accessor invalid for natural width field");
1551 }
1552
1553 static __always_inline void vmcs_check32(unsigned long field)
1554 {
1555         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1556                          "32-bit accessor invalid for 16-bit field");
1557         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1558                          "32-bit accessor invalid for natural width field");
1559 }
1560
1561 static __always_inline void vmcs_check64(unsigned long field)
1562 {
1563         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1564                          "64-bit accessor invalid for 16-bit field");
1565         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1566                          "64-bit accessor invalid for 64-bit high field");
1567         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1568                          "64-bit accessor invalid for 32-bit field");
1569         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1570                          "64-bit accessor invalid for natural width field");
1571 }
1572
1573 static __always_inline void vmcs_checkl(unsigned long field)
1574 {
1575         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1576                          "Natural width accessor invalid for 16-bit field");
1577         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1578                          "Natural width accessor invalid for 64-bit field");
1579         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1580                          "Natural width accessor invalid for 64-bit high field");
1581         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1582                          "Natural width accessor invalid for 32-bit field");
1583 }
1584
1585 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1586 {
1587         unsigned long value;
1588
1589         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1590                       : "=a"(value) : "d"(field) : "cc");
1591         return value;
1592 }
1593
1594 static __always_inline u16 vmcs_read16(unsigned long field)
1595 {
1596         vmcs_check16(field);
1597         return __vmcs_readl(field);
1598 }
1599
1600 static __always_inline u32 vmcs_read32(unsigned long field)
1601 {
1602         vmcs_check32(field);
1603         return __vmcs_readl(field);
1604 }
1605
1606 static __always_inline u64 vmcs_read64(unsigned long field)
1607 {
1608         vmcs_check64(field);
1609 #ifdef CONFIG_X86_64
1610         return __vmcs_readl(field);
1611 #else
1612         return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1613 #endif
1614 }
1615
1616 static __always_inline unsigned long vmcs_readl(unsigned long field)
1617 {
1618         vmcs_checkl(field);
1619         return __vmcs_readl(field);
1620 }
1621
1622 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1623 {
1624         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1625                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1626         dump_stack();
1627 }
1628
1629 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1630 {
1631         u8 error;
1632
1633         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1634                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1635         if (unlikely(error))
1636                 vmwrite_error(field, value);
1637 }
1638
1639 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1640 {
1641         vmcs_check16(field);
1642         __vmcs_writel(field, value);
1643 }
1644
1645 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1646 {
1647         vmcs_check32(field);
1648         __vmcs_writel(field, value);
1649 }
1650
1651 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1652 {
1653         vmcs_check64(field);
1654         __vmcs_writel(field, value);
1655 #ifndef CONFIG_X86_64
1656         asm volatile ("");
1657         __vmcs_writel(field+1, value >> 32);
1658 #endif
1659 }
1660
1661 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1662 {
1663         vmcs_checkl(field);
1664         __vmcs_writel(field, value);
1665 }
1666
1667 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1668 {
1669         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1670                          "vmcs_clear_bits does not support 64-bit fields");
1671         __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1672 }
1673
1674 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1675 {
1676         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1677                          "vmcs_set_bits does not support 64-bit fields");
1678         __vmcs_writel(field, __vmcs_readl(field) | mask);
1679 }
1680
1681 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
1682 {
1683         vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
1684 }
1685
1686 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1687 {
1688         vmcs_write32(VM_ENTRY_CONTROLS, val);
1689         vmx->vm_entry_controls_shadow = val;
1690 }
1691
1692 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1693 {
1694         if (vmx->vm_entry_controls_shadow != val)
1695                 vm_entry_controls_init(vmx, val);
1696 }
1697
1698 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1699 {
1700         return vmx->vm_entry_controls_shadow;
1701 }
1702
1703
1704 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1705 {
1706         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1707 }
1708
1709 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1710 {
1711         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1712 }
1713
1714 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
1715 {
1716         vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
1717 }
1718
1719 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1720 {
1721         vmcs_write32(VM_EXIT_CONTROLS, val);
1722         vmx->vm_exit_controls_shadow = val;
1723 }
1724
1725 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1726 {
1727         if (vmx->vm_exit_controls_shadow != val)
1728                 vm_exit_controls_init(vmx, val);
1729 }
1730
1731 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1732 {
1733         return vmx->vm_exit_controls_shadow;
1734 }
1735
1736
1737 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1738 {
1739         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1740 }
1741
1742 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1743 {
1744         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1745 }
1746
1747 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1748 {
1749         vmx->segment_cache.bitmask = 0;
1750 }
1751
1752 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1753                                        unsigned field)
1754 {
1755         bool ret;
1756         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1757
1758         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1759                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1760                 vmx->segment_cache.bitmask = 0;
1761         }
1762         ret = vmx->segment_cache.bitmask & mask;
1763         vmx->segment_cache.bitmask |= mask;
1764         return ret;
1765 }
1766
1767 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1768 {
1769         u16 *p = &vmx->segment_cache.seg[seg].selector;
1770
1771         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1772                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1773         return *p;
1774 }
1775
1776 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1777 {
1778         ulong *p = &vmx->segment_cache.seg[seg].base;
1779
1780         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1781                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1782         return *p;
1783 }
1784
1785 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1786 {
1787         u32 *p = &vmx->segment_cache.seg[seg].limit;
1788
1789         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1790                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1791         return *p;
1792 }
1793
1794 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1795 {
1796         u32 *p = &vmx->segment_cache.seg[seg].ar;
1797
1798         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1799                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1800         return *p;
1801 }
1802
1803 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1804 {
1805         u32 eb;
1806
1807         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1808              (1u << NM_VECTOR) | (1u << DB_VECTOR) | (1u << AC_VECTOR);
1809         if ((vcpu->guest_debug &
1810              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1811             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1812                 eb |= 1u << BP_VECTOR;
1813         if (to_vmx(vcpu)->rmode.vm86_active)
1814                 eb = ~0;
1815         if (enable_ept)
1816                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1817         if (vcpu->fpu_active)
1818                 eb &= ~(1u << NM_VECTOR);
1819
1820         /* When we are running a nested L2 guest and L1 specified for it a
1821          * certain exception bitmap, we must trap the same exceptions and pass
1822          * them to L1. When running L2, we will only handle the exceptions
1823          * specified above if L1 did not want them.
1824          */
1825         if (is_guest_mode(vcpu))
1826                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1827
1828         vmcs_write32(EXCEPTION_BITMAP, eb);
1829 }
1830
1831 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1832                 unsigned long entry, unsigned long exit)
1833 {
1834         vm_entry_controls_clearbit(vmx, entry);
1835         vm_exit_controls_clearbit(vmx, exit);
1836 }
1837
1838 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1839 {
1840         unsigned i;
1841         struct msr_autoload *m = &vmx->msr_autoload;
1842
1843         switch (msr) {
1844         case MSR_EFER:
1845                 if (cpu_has_load_ia32_efer) {
1846                         clear_atomic_switch_msr_special(vmx,
1847                                         VM_ENTRY_LOAD_IA32_EFER,
1848                                         VM_EXIT_LOAD_IA32_EFER);
1849                         return;
1850                 }
1851                 break;
1852         case MSR_CORE_PERF_GLOBAL_CTRL:
1853                 if (cpu_has_load_perf_global_ctrl) {
1854                         clear_atomic_switch_msr_special(vmx,
1855                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1856                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1857                         return;
1858                 }
1859                 break;
1860         }
1861
1862         for (i = 0; i < m->nr; ++i)
1863                 if (m->guest[i].index == msr)
1864                         break;
1865
1866         if (i == m->nr)
1867                 return;
1868         --m->nr;
1869         m->guest[i] = m->guest[m->nr];
1870         m->host[i] = m->host[m->nr];
1871         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1872         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1873 }
1874
1875 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1876                 unsigned long entry, unsigned long exit,
1877                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1878                 u64 guest_val, u64 host_val)
1879 {
1880         vmcs_write64(guest_val_vmcs, guest_val);
1881         vmcs_write64(host_val_vmcs, host_val);
1882         vm_entry_controls_setbit(vmx, entry);
1883         vm_exit_controls_setbit(vmx, exit);
1884 }
1885
1886 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1887                                   u64 guest_val, u64 host_val)
1888 {
1889         unsigned i;
1890         struct msr_autoload *m = &vmx->msr_autoload;
1891
1892         switch (msr) {
1893         case MSR_EFER:
1894                 if (cpu_has_load_ia32_efer) {
1895                         add_atomic_switch_msr_special(vmx,
1896                                         VM_ENTRY_LOAD_IA32_EFER,
1897                                         VM_EXIT_LOAD_IA32_EFER,
1898                                         GUEST_IA32_EFER,
1899                                         HOST_IA32_EFER,
1900                                         guest_val, host_val);
1901                         return;
1902                 }
1903                 break;
1904         case MSR_CORE_PERF_GLOBAL_CTRL:
1905                 if (cpu_has_load_perf_global_ctrl) {
1906                         add_atomic_switch_msr_special(vmx,
1907                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1908                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1909                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1910                                         HOST_IA32_PERF_GLOBAL_CTRL,
1911                                         guest_val, host_val);
1912                         return;
1913                 }
1914                 break;
1915         case MSR_IA32_PEBS_ENABLE:
1916                 /* PEBS needs a quiescent period after being disabled (to write
1917                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
1918                  * provide that period, so a CPU could write host's record into
1919                  * guest's memory.
1920                  */
1921                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1922         }
1923
1924         for (i = 0; i < m->nr; ++i)
1925                 if (m->guest[i].index == msr)
1926                         break;
1927
1928         if (i == NR_AUTOLOAD_MSRS) {
1929                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1930                                 "Can't add msr %x\n", msr);
1931                 return;
1932         } else if (i == m->nr) {
1933                 ++m->nr;
1934                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1935                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1936         }
1937
1938         m->guest[i].index = msr;
1939         m->guest[i].value = guest_val;
1940         m->host[i].index = msr;
1941         m->host[i].value = host_val;
1942 }
1943
1944 static void reload_tss(void)
1945 {
1946         /*
1947          * VT restores TR but not its size.  Useless.
1948          */
1949         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1950         struct desc_struct *descs;
1951
1952         descs = (void *)gdt->address;
1953         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1954         load_TR_desc();
1955 }
1956
1957 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1958 {
1959         u64 guest_efer = vmx->vcpu.arch.efer;
1960         u64 ignore_bits = 0;
1961
1962         if (!enable_ept) {
1963                 /*
1964                  * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
1965                  * host CPUID is more efficient than testing guest CPUID
1966                  * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
1967                  */
1968                 if (boot_cpu_has(X86_FEATURE_SMEP))
1969                         guest_efer |= EFER_NX;
1970                 else if (!(guest_efer & EFER_NX))
1971                         ignore_bits |= EFER_NX;
1972         }
1973
1974         /*
1975          * LMA and LME handled by hardware; SCE meaningless outside long mode.
1976          */
1977         ignore_bits |= EFER_SCE;
1978 #ifdef CONFIG_X86_64
1979         ignore_bits |= EFER_LMA | EFER_LME;
1980         /* SCE is meaningful only in long mode on Intel */
1981         if (guest_efer & EFER_LMA)
1982                 ignore_bits &= ~(u64)EFER_SCE;
1983 #endif
1984
1985         clear_atomic_switch_msr(vmx, MSR_EFER);
1986
1987         /*
1988          * On EPT, we can't emulate NX, so we must switch EFER atomically.
1989          * On CPUs that support "load IA32_EFER", always switch EFER
1990          * atomically, since it's faster than switching it manually.
1991          */
1992         if (cpu_has_load_ia32_efer ||
1993             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1994                 if (!(guest_efer & EFER_LMA))
1995                         guest_efer &= ~EFER_LME;
1996                 if (guest_efer != host_efer)
1997                         add_atomic_switch_msr(vmx, MSR_EFER,
1998                                               guest_efer, host_efer);
1999                 return false;
2000         } else {
2001                 guest_efer &= ~ignore_bits;
2002                 guest_efer |= host_efer & ignore_bits;
2003
2004                 vmx->guest_msrs[efer_offset].data = guest_efer;
2005                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2006
2007                 return true;
2008         }
2009 }
2010
2011 static unsigned long segment_base(u16 selector)
2012 {
2013         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2014         struct desc_struct *d;
2015         unsigned long table_base;
2016         unsigned long v;
2017
2018         if (!(selector & ~3))
2019                 return 0;
2020
2021         table_base = gdt->address;
2022
2023         if (selector & 4) {           /* from ldt */
2024                 u16 ldt_selector = kvm_read_ldt();
2025
2026                 if (!(ldt_selector & ~3))
2027                         return 0;
2028
2029                 table_base = segment_base(ldt_selector);
2030         }
2031         d = (struct desc_struct *)(table_base + (selector & ~7));
2032         v = get_desc_base(d);
2033 #ifdef CONFIG_X86_64
2034        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
2035                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
2036 #endif
2037         return v;
2038 }
2039
2040 static inline unsigned long kvm_read_tr_base(void)
2041 {
2042         u16 tr;
2043         asm("str %0" : "=g"(tr));
2044         return segment_base(tr);
2045 }
2046
2047 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
2048 {
2049         struct vcpu_vmx *vmx = to_vmx(vcpu);
2050         int i;
2051
2052         if (vmx->host_state.loaded)
2053                 return;
2054
2055         vmx->host_state.loaded = 1;
2056         /*
2057          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
2058          * allow segment selectors with cpl > 0 or ti == 1.
2059          */
2060         vmx->host_state.ldt_sel = kvm_read_ldt();
2061         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
2062         savesegment(fs, vmx->host_state.fs_sel);
2063         if (!(vmx->host_state.fs_sel & 7)) {
2064                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
2065                 vmx->host_state.fs_reload_needed = 0;
2066         } else {
2067                 vmcs_write16(HOST_FS_SELECTOR, 0);
2068                 vmx->host_state.fs_reload_needed = 1;
2069         }
2070         savesegment(gs, vmx->host_state.gs_sel);
2071         if (!(vmx->host_state.gs_sel & 7))
2072                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
2073         else {
2074                 vmcs_write16(HOST_GS_SELECTOR, 0);
2075                 vmx->host_state.gs_ldt_reload_needed = 1;
2076         }
2077
2078 #ifdef CONFIG_X86_64
2079         savesegment(ds, vmx->host_state.ds_sel);
2080         savesegment(es, vmx->host_state.es_sel);
2081 #endif
2082
2083 #ifdef CONFIG_X86_64
2084         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2085         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2086 #else
2087         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2088         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2089 #endif
2090
2091 #ifdef CONFIG_X86_64
2092         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2093         if (is_long_mode(&vmx->vcpu))
2094                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2095 #endif
2096         if (boot_cpu_has(X86_FEATURE_MPX))
2097                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2098         for (i = 0; i < vmx->save_nmsrs; ++i)
2099                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2100                                    vmx->guest_msrs[i].data,
2101                                    vmx->guest_msrs[i].mask);
2102 }
2103
2104 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2105 {
2106         if (!vmx->host_state.loaded)
2107                 return;
2108
2109         ++vmx->vcpu.stat.host_state_reload;
2110         vmx->host_state.loaded = 0;
2111 #ifdef CONFIG_X86_64
2112         if (is_long_mode(&vmx->vcpu))
2113                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2114 #endif
2115         if (vmx->host_state.gs_ldt_reload_needed) {
2116                 kvm_load_ldt(vmx->host_state.ldt_sel);
2117 #ifdef CONFIG_X86_64
2118                 load_gs_index(vmx->host_state.gs_sel);
2119 #else
2120                 loadsegment(gs, vmx->host_state.gs_sel);
2121 #endif
2122         }
2123         if (vmx->host_state.fs_reload_needed)
2124                 loadsegment(fs, vmx->host_state.fs_sel);
2125 #ifdef CONFIG_X86_64
2126         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2127                 loadsegment(ds, vmx->host_state.ds_sel);
2128                 loadsegment(es, vmx->host_state.es_sel);
2129         }
2130 #endif
2131         reload_tss();
2132 #ifdef CONFIG_X86_64
2133         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2134 #endif
2135         if (vmx->host_state.msr_host_bndcfgs)
2136                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2137         /*
2138          * If the FPU is not active (through the host task or
2139          * the guest vcpu), then restore the cr0.TS bit.
2140          */
2141         if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded)
2142                 stts();
2143         load_gdt(this_cpu_ptr(&host_gdt));
2144 }
2145
2146 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2147 {
2148         preempt_disable();
2149         __vmx_load_host_state(vmx);
2150         preempt_enable();
2151 }
2152
2153 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2154 {
2155         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2156         struct pi_desc old, new;
2157         unsigned int dest;
2158
2159         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2160                 !irq_remapping_cap(IRQ_POSTING_CAP))
2161                 return;
2162
2163         do {
2164                 old.control = new.control = pi_desc->control;
2165
2166                 /*
2167                  * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2168                  * are two possible cases:
2169                  * 1. After running 'pre_block', context switch
2170                  *    happened. For this case, 'sn' was set in
2171                  *    vmx_vcpu_put(), so we need to clear it here.
2172                  * 2. After running 'pre_block', we were blocked,
2173                  *    and woken up by some other guy. For this case,
2174                  *    we don't need to do anything, 'pi_post_block'
2175                  *    will do everything for us. However, we cannot
2176                  *    check whether it is case #1 or case #2 here
2177                  *    (maybe, not needed), so we also clear sn here,
2178                  *    I think it is not a big deal.
2179                  */
2180                 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2181                         if (vcpu->cpu != cpu) {
2182                                 dest = cpu_physical_id(cpu);
2183
2184                                 if (x2apic_enabled())
2185                                         new.ndst = dest;
2186                                 else
2187                                         new.ndst = (dest << 8) & 0xFF00;
2188                         }
2189
2190                         /* set 'NV' to 'notification vector' */
2191                         new.nv = POSTED_INTR_VECTOR;
2192                 }
2193
2194                 /* Allow posting non-urgent interrupts */
2195                 new.sn = 0;
2196         } while (cmpxchg(&pi_desc->control, old.control,
2197                         new.control) != old.control);
2198 }
2199
2200 /*
2201  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2202  * vcpu mutex is already taken.
2203  */
2204 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2205 {
2206         struct vcpu_vmx *vmx = to_vmx(vcpu);
2207         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2208         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
2209
2210         if (!vmm_exclusive)
2211                 kvm_cpu_vmxon(phys_addr);
2212         else if (!already_loaded)
2213                 loaded_vmcs_clear(vmx->loaded_vmcs);
2214
2215         if (!already_loaded) {
2216                 local_irq_disable();
2217                 crash_disable_local_vmclear(cpu);
2218
2219                 /*
2220                  * Read loaded_vmcs->cpu should be before fetching
2221                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2222                  * See the comments in __loaded_vmcs_clear().
2223                  */
2224                 smp_rmb();
2225
2226                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2227                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2228                 crash_enable_local_vmclear(cpu);
2229                 local_irq_enable();
2230         }
2231
2232         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2233                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2234                 vmcs_load(vmx->loaded_vmcs->vmcs);
2235         }
2236
2237         if (!already_loaded) {
2238                 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2239                 unsigned long sysenter_esp;
2240
2241                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2242
2243                 /*
2244                  * Linux uses per-cpu TSS and GDT, so set these when switching
2245                  * processors.
2246                  */
2247                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
2248                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
2249
2250                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2251                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2252
2253                 vmx->loaded_vmcs->cpu = cpu;
2254         }
2255
2256         /* Setup TSC multiplier */
2257         if (kvm_has_tsc_control &&
2258             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio) {
2259                 vmx->current_tsc_ratio = vcpu->arch.tsc_scaling_ratio;
2260                 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2261         }
2262
2263         vmx_vcpu_pi_load(vcpu, cpu);
2264         vmx->host_pkru = read_pkru();
2265 }
2266
2267 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2268 {
2269         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2270
2271         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2272                 !irq_remapping_cap(IRQ_POSTING_CAP))
2273                 return;
2274
2275         /* Set SN when the vCPU is preempted */
2276         if (vcpu->preempted)
2277                 pi_set_sn(pi_desc);
2278 }
2279
2280 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2281 {
2282         vmx_vcpu_pi_put(vcpu);
2283
2284         __vmx_load_host_state(to_vmx(vcpu));
2285         if (!vmm_exclusive) {
2286                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2287                 vcpu->cpu = -1;
2288                 kvm_cpu_vmxoff();
2289         }
2290 }
2291
2292 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
2293 {
2294         ulong cr0;
2295
2296         if (vcpu->fpu_active)
2297                 return;
2298         vcpu->fpu_active = 1;
2299         cr0 = vmcs_readl(GUEST_CR0);
2300         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
2301         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
2302         vmcs_writel(GUEST_CR0, cr0);
2303         update_exception_bitmap(vcpu);
2304         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
2305         if (is_guest_mode(vcpu))
2306                 vcpu->arch.cr0_guest_owned_bits &=
2307                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
2308         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2309 }
2310
2311 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2312
2313 /*
2314  * Return the cr0 value that a nested guest would read. This is a combination
2315  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2316  * its hypervisor (cr0_read_shadow).
2317  */
2318 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2319 {
2320         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2321                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2322 }
2323 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2324 {
2325         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2326                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2327 }
2328
2329 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
2330 {
2331         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2332          * set this *before* calling this function.
2333          */
2334         vmx_decache_cr0_guest_bits(vcpu);
2335         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
2336         update_exception_bitmap(vcpu);
2337         vcpu->arch.cr0_guest_owned_bits = 0;
2338         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2339         if (is_guest_mode(vcpu)) {
2340                 /*
2341                  * L1's specified read shadow might not contain the TS bit,
2342                  * so now that we turned on shadowing of this bit, we need to
2343                  * set this bit of the shadow. Like in nested_vmx_run we need
2344                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2345                  * up-to-date here because we just decached cr0.TS (and we'll
2346                  * only update vmcs12->guest_cr0 on nested exit).
2347                  */
2348                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2349                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2350                         (vcpu->arch.cr0 & X86_CR0_TS);
2351                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2352         } else
2353                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2354 }
2355
2356 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2357 {
2358         unsigned long rflags, save_rflags;
2359
2360         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2361                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2362                 rflags = vmcs_readl(GUEST_RFLAGS);
2363                 if (to_vmx(vcpu)->rmode.vm86_active) {
2364                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2365                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2366                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2367                 }
2368                 to_vmx(vcpu)->rflags = rflags;
2369         }
2370         return to_vmx(vcpu)->rflags;
2371 }
2372
2373 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2374 {
2375         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2376         to_vmx(vcpu)->rflags = rflags;
2377         if (to_vmx(vcpu)->rmode.vm86_active) {
2378                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2379                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2380         }
2381         vmcs_writel(GUEST_RFLAGS, rflags);
2382 }
2383
2384 static u32 vmx_get_pkru(struct kvm_vcpu *vcpu)
2385 {
2386         return to_vmx(vcpu)->guest_pkru;
2387 }
2388
2389 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2390 {
2391         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2392         int ret = 0;
2393
2394         if (interruptibility & GUEST_INTR_STATE_STI)
2395                 ret |= KVM_X86_SHADOW_INT_STI;
2396         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2397                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2398
2399         return ret;
2400 }
2401
2402 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2403 {
2404         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2405         u32 interruptibility = interruptibility_old;
2406
2407         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2408
2409         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2410                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2411         else if (mask & KVM_X86_SHADOW_INT_STI)
2412                 interruptibility |= GUEST_INTR_STATE_STI;
2413
2414         if ((interruptibility != interruptibility_old))
2415                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2416 }
2417
2418 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2419 {
2420         unsigned long rip;
2421
2422         rip = kvm_rip_read(vcpu);
2423         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2424         kvm_rip_write(vcpu, rip);
2425
2426         /* skipping an emulated instruction also counts */
2427         vmx_set_interrupt_shadow(vcpu, 0);
2428 }
2429
2430 /*
2431  * KVM wants to inject page-faults which it got to the guest. This function
2432  * checks whether in a nested guest, we need to inject them to L1 or L2.
2433  */
2434 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2435 {
2436         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2437
2438         if (!(vmcs12->exception_bitmap & (1u << nr)))
2439                 return 0;
2440
2441         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2442                           vmcs_read32(VM_EXIT_INTR_INFO),
2443                           vmcs_readl(EXIT_QUALIFICATION));
2444         return 1;
2445 }
2446
2447 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2448                                 bool has_error_code, u32 error_code,
2449                                 bool reinject)
2450 {
2451         struct vcpu_vmx *vmx = to_vmx(vcpu);
2452         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2453
2454         if (!reinject && is_guest_mode(vcpu) &&
2455             nested_vmx_check_exception(vcpu, nr))
2456                 return;
2457
2458         if (has_error_code) {
2459                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2460                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2461         }
2462
2463         if (vmx->rmode.vm86_active) {
2464                 int inc_eip = 0;
2465                 if (kvm_exception_is_soft(nr))
2466                         inc_eip = vcpu->arch.event_exit_inst_len;
2467                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2468                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2469                 return;
2470         }
2471
2472         if (kvm_exception_is_soft(nr)) {
2473                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2474                              vmx->vcpu.arch.event_exit_inst_len);
2475                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2476         } else
2477                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2478
2479         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2480 }
2481
2482 static bool vmx_rdtscp_supported(void)
2483 {
2484         return cpu_has_vmx_rdtscp();
2485 }
2486
2487 static bool vmx_invpcid_supported(void)
2488 {
2489         return cpu_has_vmx_invpcid() && enable_ept;
2490 }
2491
2492 /*
2493  * Swap MSR entry in host/guest MSR entry array.
2494  */
2495 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2496 {
2497         struct shared_msr_entry tmp;
2498
2499         tmp = vmx->guest_msrs[to];
2500         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2501         vmx->guest_msrs[from] = tmp;
2502 }
2503
2504 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2505 {
2506         unsigned long *msr_bitmap;
2507
2508         if (is_guest_mode(vcpu))
2509                 msr_bitmap = vmx_msr_bitmap_nested;
2510         else if (cpu_has_secondary_exec_ctrls() &&
2511                  (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
2512                   SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
2513                 if (is_long_mode(vcpu))
2514                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2515                 else
2516                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2517         } else {
2518                 if (is_long_mode(vcpu))
2519                         msr_bitmap = vmx_msr_bitmap_longmode;
2520                 else
2521                         msr_bitmap = vmx_msr_bitmap_legacy;
2522         }
2523
2524         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2525 }
2526
2527 /*
2528  * Set up the vmcs to automatically save and restore system
2529  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2530  * mode, as fiddling with msrs is very expensive.
2531  */
2532 static void setup_msrs(struct vcpu_vmx *vmx)
2533 {
2534         int save_nmsrs, index;
2535
2536         save_nmsrs = 0;
2537 #ifdef CONFIG_X86_64
2538         if (is_long_mode(&vmx->vcpu)) {
2539                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2540                 if (index >= 0)
2541                         move_msr_up(vmx, index, save_nmsrs++);
2542                 index = __find_msr_index(vmx, MSR_LSTAR);
2543                 if (index >= 0)
2544                         move_msr_up(vmx, index, save_nmsrs++);
2545                 index = __find_msr_index(vmx, MSR_CSTAR);
2546                 if (index >= 0)
2547                         move_msr_up(vmx, index, save_nmsrs++);
2548                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2549                 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2550                         move_msr_up(vmx, index, save_nmsrs++);
2551                 /*
2552                  * MSR_STAR is only needed on long mode guests, and only
2553                  * if efer.sce is enabled.
2554                  */
2555                 index = __find_msr_index(vmx, MSR_STAR);
2556                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2557                         move_msr_up(vmx, index, save_nmsrs++);
2558         }
2559 #endif
2560         index = __find_msr_index(vmx, MSR_EFER);
2561         if (index >= 0 && update_transition_efer(vmx, index))
2562                 move_msr_up(vmx, index, save_nmsrs++);
2563
2564         vmx->save_nmsrs = save_nmsrs;
2565
2566         if (cpu_has_vmx_msr_bitmap())
2567                 vmx_set_msr_bitmap(&vmx->vcpu);
2568 }
2569
2570 /*
2571  * reads and returns guest's timestamp counter "register"
2572  * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2573  * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2574  */
2575 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2576 {
2577         u64 host_tsc, tsc_offset;
2578
2579         host_tsc = rdtsc();
2580         tsc_offset = vmcs_read64(TSC_OFFSET);
2581         return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2582 }
2583
2584 /*
2585  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2586  * counter, even if a nested guest (L2) is currently running.
2587  */
2588 static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2589 {
2590         u64 tsc_offset;
2591
2592         tsc_offset = is_guest_mode(vcpu) ?
2593                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2594                 vmcs_read64(TSC_OFFSET);
2595         return host_tsc + tsc_offset;
2596 }
2597
2598 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2599 {
2600         return vmcs_read64(TSC_OFFSET);
2601 }
2602
2603 /*
2604  * writes 'offset' into guest's timestamp counter offset register
2605  */
2606 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2607 {
2608         if (is_guest_mode(vcpu)) {
2609                 /*
2610                  * We're here if L1 chose not to trap WRMSR to TSC. According
2611                  * to the spec, this should set L1's TSC; The offset that L1
2612                  * set for L2 remains unchanged, and still needs to be added
2613                  * to the newly set TSC to get L2's TSC.
2614                  */
2615                 struct vmcs12 *vmcs12;
2616                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2617                 /* recalculate vmcs02.TSC_OFFSET: */
2618                 vmcs12 = get_vmcs12(vcpu);
2619                 vmcs_write64(TSC_OFFSET, offset +
2620                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2621                          vmcs12->tsc_offset : 0));
2622         } else {
2623                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2624                                            vmcs_read64(TSC_OFFSET), offset);
2625                 vmcs_write64(TSC_OFFSET, offset);
2626         }
2627 }
2628
2629 static void vmx_adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, s64 adjustment)
2630 {
2631         u64 offset = vmcs_read64(TSC_OFFSET);
2632
2633         vmcs_write64(TSC_OFFSET, offset + adjustment);
2634         if (is_guest_mode(vcpu)) {
2635                 /* Even when running L2, the adjustment needs to apply to L1 */
2636                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2637         } else
2638                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2639                                            offset + adjustment);
2640 }
2641
2642 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2643 {
2644         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2645         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2646 }
2647
2648 /*
2649  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2650  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2651  * all guests if the "nested" module option is off, and can also be disabled
2652  * for a single guest by disabling its VMX cpuid bit.
2653  */
2654 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2655 {
2656         return nested && guest_cpuid_has_vmx(vcpu);
2657 }
2658
2659 /*
2660  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2661  * returned for the various VMX controls MSRs when nested VMX is enabled.
2662  * The same values should also be used to verify that vmcs12 control fields are
2663  * valid during nested entry from L1 to L2.
2664  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2665  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2666  * bit in the high half is on if the corresponding bit in the control field
2667  * may be on. See also vmx_control_verify().
2668  */
2669 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2670 {
2671         /*
2672          * Note that as a general rule, the high half of the MSRs (bits in
2673          * the control fields which may be 1) should be initialized by the
2674          * intersection of the underlying hardware's MSR (i.e., features which
2675          * can be supported) and the list of features we want to expose -
2676          * because they are known to be properly supported in our code.
2677          * Also, usually, the low half of the MSRs (bits which must be 1) can
2678          * be set to 0, meaning that L1 may turn off any of these bits. The
2679          * reason is that if one of these bits is necessary, it will appear
2680          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2681          * fields of vmcs01 and vmcs02, will turn these bits off - and
2682          * nested_vmx_exit_handled() will not pass related exits to L1.
2683          * These rules have exceptions below.
2684          */
2685
2686         /* pin-based controls */
2687         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2688                 vmx->nested.nested_vmx_pinbased_ctls_low,
2689                 vmx->nested.nested_vmx_pinbased_ctls_high);
2690         vmx->nested.nested_vmx_pinbased_ctls_low |=
2691                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2692         vmx->nested.nested_vmx_pinbased_ctls_high &=
2693                 PIN_BASED_EXT_INTR_MASK |
2694                 PIN_BASED_NMI_EXITING |
2695                 PIN_BASED_VIRTUAL_NMIS;
2696         vmx->nested.nested_vmx_pinbased_ctls_high |=
2697                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2698                 PIN_BASED_VMX_PREEMPTION_TIMER;
2699         if (kvm_vcpu_apicv_active(&vmx->vcpu))
2700                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2701                         PIN_BASED_POSTED_INTR;
2702
2703         /* exit controls */
2704         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2705                 vmx->nested.nested_vmx_exit_ctls_low,
2706                 vmx->nested.nested_vmx_exit_ctls_high);
2707         vmx->nested.nested_vmx_exit_ctls_low =
2708                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2709
2710         vmx->nested.nested_vmx_exit_ctls_high &=
2711 #ifdef CONFIG_X86_64
2712                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2713 #endif
2714                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2715         vmx->nested.nested_vmx_exit_ctls_high |=
2716                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2717                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2718                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2719
2720         if (kvm_mpx_supported())
2721                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2722
2723         /* We support free control of debug control saving. */
2724         vmx->nested.nested_vmx_true_exit_ctls_low =
2725                 vmx->nested.nested_vmx_exit_ctls_low &
2726                 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2727
2728         /* entry controls */
2729         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2730                 vmx->nested.nested_vmx_entry_ctls_low,
2731                 vmx->nested.nested_vmx_entry_ctls_high);
2732         vmx->nested.nested_vmx_entry_ctls_low =
2733                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2734         vmx->nested.nested_vmx_entry_ctls_high &=
2735 #ifdef CONFIG_X86_64
2736                 VM_ENTRY_IA32E_MODE |
2737 #endif
2738                 VM_ENTRY_LOAD_IA32_PAT;
2739         vmx->nested.nested_vmx_entry_ctls_high |=
2740                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2741         if (kvm_mpx_supported())
2742                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2743
2744         /* We support free control of debug control loading. */
2745         vmx->nested.nested_vmx_true_entry_ctls_low =
2746                 vmx->nested.nested_vmx_entry_ctls_low &
2747                 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2748
2749         /* cpu-based controls */
2750         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2751                 vmx->nested.nested_vmx_procbased_ctls_low,
2752                 vmx->nested.nested_vmx_procbased_ctls_high);
2753         vmx->nested.nested_vmx_procbased_ctls_low =
2754                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2755         vmx->nested.nested_vmx_procbased_ctls_high &=
2756                 CPU_BASED_VIRTUAL_INTR_PENDING |
2757                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2758                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2759                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2760                 CPU_BASED_CR3_STORE_EXITING |
2761 #ifdef CONFIG_X86_64
2762                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2763 #endif
2764                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2765                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2766                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2767                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2768                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2769         /*
2770          * We can allow some features even when not supported by the
2771          * hardware. For example, L1 can specify an MSR bitmap - and we
2772          * can use it to avoid exits to L1 - even when L0 runs L2
2773          * without MSR bitmaps.
2774          */
2775         vmx->nested.nested_vmx_procbased_ctls_high |=
2776                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2777                 CPU_BASED_USE_MSR_BITMAPS;
2778
2779         /* We support free control of CR3 access interception. */
2780         vmx->nested.nested_vmx_true_procbased_ctls_low =
2781                 vmx->nested.nested_vmx_procbased_ctls_low &
2782                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2783
2784         /* secondary cpu-based controls */
2785         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2786                 vmx->nested.nested_vmx_secondary_ctls_low,
2787                 vmx->nested.nested_vmx_secondary_ctls_high);
2788         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2789         vmx->nested.nested_vmx_secondary_ctls_high &=
2790                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2791                 SECONDARY_EXEC_RDTSCP |
2792                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2793                 SECONDARY_EXEC_ENABLE_VPID |
2794                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2795                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2796                 SECONDARY_EXEC_WBINVD_EXITING |
2797                 SECONDARY_EXEC_XSAVES |
2798                 SECONDARY_EXEC_PCOMMIT;
2799
2800         if (enable_ept) {
2801                 /* nested EPT: emulate EPT also to L1 */
2802                 vmx->nested.nested_vmx_secondary_ctls_high |=
2803                         SECONDARY_EXEC_ENABLE_EPT;
2804                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2805                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2806                          VMX_EPT_INVEPT_BIT;
2807                 if (cpu_has_vmx_ept_execute_only())
2808                         vmx->nested.nested_vmx_ept_caps |=
2809                                 VMX_EPT_EXECUTE_ONLY_BIT;
2810                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2811                 /*
2812                  * For nested guests, we don't do anything specific
2813                  * for single context invalidation. Hence, only advertise
2814                  * support for global context invalidation.
2815                  */
2816                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
2817         } else
2818                 vmx->nested.nested_vmx_ept_caps = 0;
2819
2820         /*
2821          * Old versions of KVM use the single-context version without
2822          * checking for support, so declare that it is supported even
2823          * though it is treated as global context.  The alternative is
2824          * not failing the single-context invvpid, and it is worse.
2825          */
2826         if (enable_vpid)
2827                 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2828                                 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |
2829                                 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
2830         else
2831                 vmx->nested.nested_vmx_vpid_caps = 0;
2832
2833         if (enable_unrestricted_guest)
2834                 vmx->nested.nested_vmx_secondary_ctls_high |=
2835                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2836
2837         /* miscellaneous data */
2838         rdmsr(MSR_IA32_VMX_MISC,
2839                 vmx->nested.nested_vmx_misc_low,
2840                 vmx->nested.nested_vmx_misc_high);
2841         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2842         vmx->nested.nested_vmx_misc_low |=
2843                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2844                 VMX_MISC_ACTIVITY_HLT;
2845         vmx->nested.nested_vmx_misc_high = 0;
2846 }
2847
2848 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2849 {
2850         /*
2851          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2852          */
2853         return ((control & high) | low) == control;
2854 }
2855
2856 static inline u64 vmx_control_msr(u32 low, u32 high)
2857 {
2858         return low | ((u64)high << 32);
2859 }
2860
2861 /* Returns 0 on success, non-0 otherwise. */
2862 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2863 {
2864         struct vcpu_vmx *vmx = to_vmx(vcpu);
2865
2866         switch (msr_index) {
2867         case MSR_IA32_VMX_BASIC:
2868                 /*
2869                  * This MSR reports some information about VMX support. We
2870                  * should return information about the VMX we emulate for the
2871                  * guest, and the VMCS structure we give it - not about the
2872                  * VMX support of the underlying hardware.
2873                  */
2874                 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2875                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2876                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2877                 break;
2878         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2879         case MSR_IA32_VMX_PINBASED_CTLS:
2880                 *pdata = vmx_control_msr(
2881                         vmx->nested.nested_vmx_pinbased_ctls_low,
2882                         vmx->nested.nested_vmx_pinbased_ctls_high);
2883                 break;
2884         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2885                 *pdata = vmx_control_msr(
2886                         vmx->nested.nested_vmx_true_procbased_ctls_low,
2887                         vmx->nested.nested_vmx_procbased_ctls_high);
2888                 break;
2889         case MSR_IA32_VMX_PROCBASED_CTLS:
2890                 *pdata = vmx_control_msr(
2891                         vmx->nested.nested_vmx_procbased_ctls_low,
2892                         vmx->nested.nested_vmx_procbased_ctls_high);
2893                 break;
2894         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2895                 *pdata = vmx_control_msr(
2896                         vmx->nested.nested_vmx_true_exit_ctls_low,
2897                         vmx->nested.nested_vmx_exit_ctls_high);
2898                 break;
2899         case MSR_IA32_VMX_EXIT_CTLS:
2900                 *pdata = vmx_control_msr(
2901                         vmx->nested.nested_vmx_exit_ctls_low,
2902                         vmx->nested.nested_vmx_exit_ctls_high);
2903                 break;
2904         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2905                 *pdata = vmx_control_msr(
2906                         vmx->nested.nested_vmx_true_entry_ctls_low,
2907                         vmx->nested.nested_vmx_entry_ctls_high);
2908                 break;
2909         case MSR_IA32_VMX_ENTRY_CTLS:
2910                 *pdata = vmx_control_msr(
2911                         vmx->nested.nested_vmx_entry_ctls_low,
2912                         vmx->nested.nested_vmx_entry_ctls_high);
2913                 break;
2914         case MSR_IA32_VMX_MISC:
2915                 *pdata = vmx_control_msr(
2916                         vmx->nested.nested_vmx_misc_low,
2917                         vmx->nested.nested_vmx_misc_high);
2918                 break;
2919         /*
2920          * These MSRs specify bits which the guest must keep fixed (on or off)
2921          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2922          * We picked the standard core2 setting.
2923          */
2924 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2925 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2926         case MSR_IA32_VMX_CR0_FIXED0:
2927                 *pdata = VMXON_CR0_ALWAYSON;
2928                 break;
2929         case MSR_IA32_VMX_CR0_FIXED1:
2930                 *pdata = -1ULL;
2931                 break;
2932         case MSR_IA32_VMX_CR4_FIXED0:
2933                 *pdata = VMXON_CR4_ALWAYSON;
2934                 break;
2935         case MSR_IA32_VMX_CR4_FIXED1:
2936                 *pdata = -1ULL;
2937                 break;
2938         case MSR_IA32_VMX_VMCS_ENUM:
2939                 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2940                 break;
2941         case MSR_IA32_VMX_PROCBASED_CTLS2:
2942                 *pdata = vmx_control_msr(
2943                         vmx->nested.nested_vmx_secondary_ctls_low,
2944                         vmx->nested.nested_vmx_secondary_ctls_high);
2945                 break;
2946         case MSR_IA32_VMX_EPT_VPID_CAP:
2947                 /* Currently, no nested vpid support */
2948                 *pdata = vmx->nested.nested_vmx_ept_caps |
2949                         ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
2950                 break;
2951         default:
2952                 return 1;
2953         }
2954
2955         return 0;
2956 }
2957
2958 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
2959                                                  uint64_t val)
2960 {
2961         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
2962
2963         return !(val & ~valid_bits);
2964 }
2965
2966 /*
2967  * Reads an msr value (of 'msr_index') into 'pdata'.
2968  * Returns 0 on success, non-0 otherwise.
2969  * Assumes vcpu_load() was already called.
2970  */
2971 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2972 {
2973         struct shared_msr_entry *msr;
2974
2975         switch (msr_info->index) {
2976 #ifdef CONFIG_X86_64
2977         case MSR_FS_BASE:
2978                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
2979                 break;
2980         case MSR_GS_BASE:
2981                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
2982                 break;
2983         case MSR_KERNEL_GS_BASE:
2984                 vmx_load_host_state(to_vmx(vcpu));
2985                 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2986                 break;
2987 #endif
2988         case MSR_EFER:
2989                 return kvm_get_msr_common(vcpu, msr_info);
2990         case MSR_IA32_TSC:
2991                 msr_info->data = guest_read_tsc(vcpu);
2992                 break;
2993         case MSR_IA32_SYSENTER_CS:
2994                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
2995                 break;
2996         case MSR_IA32_SYSENTER_EIP:
2997                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
2998                 break;
2999         case MSR_IA32_SYSENTER_ESP:
3000                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
3001                 break;
3002         case MSR_IA32_BNDCFGS:
3003                 if (!kvm_mpx_supported())
3004                         return 1;
3005                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
3006                 break;
3007         case MSR_IA32_MCG_EXT_CTL:
3008                 if (!msr_info->host_initiated &&
3009                     !(to_vmx(vcpu)->msr_ia32_feature_control &
3010                       FEATURE_CONTROL_LMCE))
3011                         return 1;
3012                 msr_info->data = vcpu->arch.mcg_ext_ctl;
3013                 break;
3014         case MSR_IA32_FEATURE_CONTROL:
3015                 msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control;
3016                 break;
3017         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3018                 if (!nested_vmx_allowed(vcpu))
3019                         return 1;
3020                 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
3021         case MSR_IA32_XSS:
3022                 if (!vmx_xsaves_supported())
3023                         return 1;
3024                 msr_info->data = vcpu->arch.ia32_xss;
3025                 break;
3026         case MSR_TSC_AUX:
3027                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3028                         return 1;
3029                 /* Otherwise falls through */
3030         default:
3031                 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3032                 if (msr) {
3033                         msr_info->data = msr->data;
3034                         break;
3035                 }
3036                 return kvm_get_msr_common(vcpu, msr_info);
3037         }
3038
3039         return 0;
3040 }
3041
3042 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3043
3044 /*
3045  * Writes msr value into into the appropriate "register".
3046  * Returns 0 on success, non-0 otherwise.
3047  * Assumes vcpu_load() was already called.
3048  */
3049 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3050 {
3051         struct vcpu_vmx *vmx = to_vmx(vcpu);
3052         struct shared_msr_entry *msr;
3053         int ret = 0;
3054         u32 msr_index = msr_info->index;
3055         u64 data = msr_info->data;
3056
3057         switch (msr_index) {
3058         case MSR_EFER:
3059                 ret = kvm_set_msr_common(vcpu, msr_info);
3060                 break;
3061 #ifdef CONFIG_X86_64
3062         case MSR_FS_BASE:
3063                 vmx_segment_cache_clear(vmx);
3064                 vmcs_writel(GUEST_FS_BASE, data);
3065                 break;
3066         case MSR_GS_BASE:
3067                 vmx_segment_cache_clear(vmx);
3068                 vmcs_writel(GUEST_GS_BASE, data);
3069                 break;
3070         case MSR_KERNEL_GS_BASE:
3071                 vmx_load_host_state(vmx);
3072                 vmx->msr_guest_kernel_gs_base = data;
3073                 break;
3074 #endif
3075         case MSR_IA32_SYSENTER_CS:
3076                 vmcs_write32(GUEST_SYSENTER_CS, data);
3077                 break;
3078         case MSR_IA32_SYSENTER_EIP:
3079                 vmcs_writel(GUEST_SYSENTER_EIP, data);
3080                 break;
3081         case MSR_IA32_SYSENTER_ESP:
3082                 vmcs_writel(GUEST_SYSENTER_ESP, data);
3083                 break;
3084         case MSR_IA32_BNDCFGS:
3085                 if (!kvm_mpx_supported())
3086                         return 1;
3087                 vmcs_write64(GUEST_BNDCFGS, data);
3088                 break;
3089         case MSR_IA32_TSC:
3090                 kvm_write_tsc(vcpu, msr_info);
3091                 break;
3092         case MSR_IA32_CR_PAT:
3093                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3094                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3095                                 return 1;
3096                         vmcs_write64(GUEST_IA32_PAT, data);
3097                         vcpu->arch.pat = data;
3098                         break;
3099                 }
3100                 ret = kvm_set_msr_common(vcpu, msr_info);
3101                 break;
3102         case MSR_IA32_TSC_ADJUST:
3103                 ret = kvm_set_msr_common(vcpu, msr_info);
3104                 break;
3105         case MSR_IA32_MCG_EXT_CTL:
3106                 if ((!msr_info->host_initiated &&
3107                      !(to_vmx(vcpu)->msr_ia32_feature_control &
3108                        FEATURE_CONTROL_LMCE)) ||
3109                     (data & ~MCG_EXT_CTL_LMCE_EN))
3110                         return 1;
3111                 vcpu->arch.mcg_ext_ctl = data;
3112                 break;
3113         case MSR_IA32_FEATURE_CONTROL:
3114                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3115                     (to_vmx(vcpu)->msr_ia32_feature_control &
3116                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3117                         return 1;
3118                 vmx->msr_ia32_feature_control = data;
3119                 if (msr_info->host_initiated && data == 0)
3120                         vmx_leave_nested(vcpu);
3121                 break;
3122         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3123                 return 1; /* they are read-only */
3124         case MSR_IA32_XSS:
3125                 if (!vmx_xsaves_supported())
3126                         return 1;
3127                 /*
3128                  * The only supported bit as of Skylake is bit 8, but
3129                  * it is not supported on KVM.
3130                  */
3131                 if (data != 0)
3132                         return 1;
3133                 vcpu->arch.ia32_xss = data;
3134                 if (vcpu->arch.ia32_xss != host_xss)
3135                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3136                                 vcpu->arch.ia32_xss, host_xss);
3137                 else
3138                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3139                 break;
3140         case MSR_TSC_AUX:
3141                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3142                         return 1;
3143                 /* Check reserved bit, higher 32 bits should be zero */
3144                 if ((data >> 32) != 0)
3145                         return 1;
3146                 /* Otherwise falls through */
3147         default:
3148                 msr = find_msr_entry(vmx, msr_index);
3149                 if (msr) {
3150                         u64 old_msr_data = msr->data;
3151                         msr->data = data;
3152                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3153                                 preempt_disable();
3154                                 ret = kvm_set_shared_msr(msr->index, msr->data,
3155                                                          msr->mask);
3156                                 preempt_enable();
3157                                 if (ret)
3158                                         msr->data = old_msr_data;
3159                         }
3160                         break;
3161                 }
3162                 ret = kvm_set_msr_common(vcpu, msr_info);
3163         }
3164
3165         return ret;
3166 }
3167
3168 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3169 {
3170         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3171         switch (reg) {
3172         case VCPU_REGS_RSP:
3173                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3174                 break;
3175         case VCPU_REGS_RIP:
3176                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3177                 break;
3178         case VCPU_EXREG_PDPTR:
3179                 if (enable_ept)
3180                         ept_save_pdptrs(vcpu);
3181                 break;
3182         default:
3183                 break;
3184         }
3185 }
3186
3187 static __init int cpu_has_kvm_support(void)
3188 {
3189         return cpu_has_vmx();
3190 }
3191
3192 static __init int vmx_disabled_by_bios(void)
3193 {
3194         u64 msr;
3195
3196         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3197         if (msr & FEATURE_CONTROL_LOCKED) {
3198                 /* launched w/ TXT and VMX disabled */
3199                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3200                         && tboot_enabled())
3201                         return 1;
3202                 /* launched w/o TXT and VMX only enabled w/ TXT */
3203                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3204                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3205                         && !tboot_enabled()) {
3206                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3207                                 "activate TXT before enabling KVM\n");
3208                         return 1;
3209                 }
3210                 /* launched w/o TXT and VMX disabled */
3211                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3212                         && !tboot_enabled())
3213                         return 1;
3214         }
3215
3216         return 0;
3217 }
3218
3219 static void kvm_cpu_vmxon(u64 addr)
3220 {
3221         intel_pt_handle_vmx(1);
3222
3223         asm volatile (ASM_VMX_VMXON_RAX
3224                         : : "a"(&addr), "m"(addr)
3225                         : "memory", "cc");
3226 }
3227
3228 static int hardware_enable(void)
3229 {
3230         int cpu = raw_smp_processor_id();
3231         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3232         u64 old, test_bits;
3233
3234         if (cr4_read_shadow() & X86_CR4_VMXE)
3235                 return -EBUSY;
3236
3237         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3238         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3239         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3240
3241         /*
3242          * Now we can enable the vmclear operation in kdump
3243          * since the loaded_vmcss_on_cpu list on this cpu
3244          * has been initialized.
3245          *
3246          * Though the cpu is not in VMX operation now, there
3247          * is no problem to enable the vmclear operation
3248          * for the loaded_vmcss_on_cpu list is empty!
3249          */
3250         crash_enable_local_vmclear(cpu);
3251
3252         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3253
3254         test_bits = FEATURE_CONTROL_LOCKED;
3255         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3256         if (tboot_enabled())
3257                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3258
3259         if ((old & test_bits) != test_bits) {
3260                 /* enable and lock */
3261                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3262         }
3263         cr4_set_bits(X86_CR4_VMXE);
3264
3265         if (vmm_exclusive) {
3266                 kvm_cpu_vmxon(phys_addr);
3267                 ept_sync_global();
3268         }
3269
3270         native_store_gdt(this_cpu_ptr(&host_gdt));
3271
3272         return 0;
3273 }
3274
3275 static void vmclear_local_loaded_vmcss(void)
3276 {
3277         int cpu = raw_smp_processor_id();
3278         struct loaded_vmcs *v, *n;
3279
3280         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3281                                  loaded_vmcss_on_cpu_link)
3282                 __loaded_vmcs_clear(v);
3283 }
3284
3285
3286 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3287  * tricks.
3288  */
3289 static void kvm_cpu_vmxoff(void)
3290 {
3291         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3292
3293         intel_pt_handle_vmx(0);
3294 }
3295
3296 static void hardware_disable(void)
3297 {
3298         if (vmm_exclusive) {
3299                 vmclear_local_loaded_vmcss();
3300                 kvm_cpu_vmxoff();
3301         }
3302         cr4_clear_bits(X86_CR4_VMXE);
3303 }
3304
3305 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3306                                       u32 msr, u32 *result)
3307 {
3308         u32 vmx_msr_low, vmx_msr_high;
3309         u32 ctl = ctl_min | ctl_opt;
3310
3311         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3312
3313         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3314         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3315
3316         /* Ensure minimum (required) set of control bits are supported. */
3317         if (ctl_min & ~ctl)
3318                 return -EIO;
3319
3320         *result = ctl;
3321         return 0;
3322 }
3323
3324 static __init bool allow_1_setting(u32 msr, u32 ctl)
3325 {
3326         u32 vmx_msr_low, vmx_msr_high;
3327
3328         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3329         return vmx_msr_high & ctl;
3330 }
3331
3332 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3333 {
3334         u32 vmx_msr_low, vmx_msr_high;
3335         u32 min, opt, min2, opt2;
3336         u32 _pin_based_exec_control = 0;
3337         u32 _cpu_based_exec_control = 0;
3338         u32 _cpu_based_2nd_exec_control = 0;
3339         u32 _vmexit_control = 0;
3340         u32 _vmentry_control = 0;
3341
3342         min = CPU_BASED_HLT_EXITING |
3343 #ifdef CONFIG_X86_64
3344               CPU_BASED_CR8_LOAD_EXITING |
3345               CPU_BASED_CR8_STORE_EXITING |
3346 #endif
3347               CPU_BASED_CR3_LOAD_EXITING |
3348               CPU_BASED_CR3_STORE_EXITING |
3349               CPU_BASED_USE_IO_BITMAPS |
3350               CPU_BASED_MOV_DR_EXITING |
3351               CPU_BASED_USE_TSC_OFFSETING |
3352               CPU_BASED_MWAIT_EXITING |
3353               CPU_BASED_MONITOR_EXITING |
3354               CPU_BASED_INVLPG_EXITING |
3355               CPU_BASED_RDPMC_EXITING;
3356
3357         opt = CPU_BASED_TPR_SHADOW |
3358               CPU_BASED_USE_MSR_BITMAPS |
3359               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3360         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3361                                 &_cpu_based_exec_control) < 0)
3362                 return -EIO;
3363 #ifdef CONFIG_X86_64
3364         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3365                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3366                                            ~CPU_BASED_CR8_STORE_EXITING;
3367 #endif
3368         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3369                 min2 = 0;
3370                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3371                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3372                         SECONDARY_EXEC_WBINVD_EXITING |
3373                         SECONDARY_EXEC_ENABLE_VPID |
3374                         SECONDARY_EXEC_ENABLE_EPT |
3375                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3376                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3377                         SECONDARY_EXEC_RDTSCP |
3378                         SECONDARY_EXEC_ENABLE_INVPCID |
3379                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3380                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3381                         SECONDARY_EXEC_SHADOW_VMCS |
3382                         SECONDARY_EXEC_XSAVES |
3383                         SECONDARY_EXEC_ENABLE_PML |
3384                         SECONDARY_EXEC_PCOMMIT |
3385                         SECONDARY_EXEC_TSC_SCALING;
3386                 if (adjust_vmx_controls(min2, opt2,
3387                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3388                                         &_cpu_based_2nd_exec_control) < 0)
3389                         return -EIO;
3390         }
3391 #ifndef CONFIG_X86_64
3392         if (!(_cpu_based_2nd_exec_control &
3393                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3394                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3395 #endif
3396
3397         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3398                 _cpu_based_2nd_exec_control &= ~(
3399                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3400                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3401                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3402
3403         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3404                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3405                    enabled */
3406                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3407                                              CPU_BASED_CR3_STORE_EXITING |
3408                                              CPU_BASED_INVLPG_EXITING);
3409                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3410                       vmx_capability.ept, vmx_capability.vpid);
3411         }
3412
3413         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
3414 #ifdef CONFIG_X86_64
3415         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3416 #endif
3417         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3418                 VM_EXIT_CLEAR_BNDCFGS;
3419         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3420                                 &_vmexit_control) < 0)
3421                 return -EIO;
3422
3423         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3424         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
3425                  PIN_BASED_VMX_PREEMPTION_TIMER;
3426         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3427                                 &_pin_based_exec_control) < 0)
3428                 return -EIO;
3429
3430         if (cpu_has_broken_vmx_preemption_timer())
3431                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3432         if (!(_cpu_based_2nd_exec_control &
3433                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
3434                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3435
3436         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3437         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3438         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3439                                 &_vmentry_control) < 0)
3440                 return -EIO;
3441
3442         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3443
3444         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3445         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3446                 return -EIO;
3447
3448 #ifdef CONFIG_X86_64
3449         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3450         if (vmx_msr_high & (1u<<16))
3451                 return -EIO;
3452 #endif
3453
3454         /* Require Write-Back (WB) memory type for VMCS accesses. */
3455         if (((vmx_msr_high >> 18) & 15) != 6)
3456                 return -EIO;
3457
3458         vmcs_conf->size = vmx_msr_high & 0x1fff;
3459         vmcs_conf->order = get_order(vmcs_config.size);
3460         vmcs_conf->revision_id = vmx_msr_low;
3461
3462         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3463         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3464         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3465         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3466         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3467
3468         cpu_has_load_ia32_efer =
3469                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3470                                 VM_ENTRY_LOAD_IA32_EFER)
3471                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3472                                    VM_EXIT_LOAD_IA32_EFER);
3473
3474         cpu_has_load_perf_global_ctrl =
3475                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3476                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3477                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3478                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3479
3480         /*
3481          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3482          * but due to errata below it can't be used. Workaround is to use
3483          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3484          *
3485          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3486          *
3487          * AAK155             (model 26)
3488          * AAP115             (model 30)
3489          * AAT100             (model 37)
3490          * BC86,AAY89,BD102   (model 44)
3491          * BA97               (model 46)
3492          *
3493          */
3494         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3495                 switch (boot_cpu_data.x86_model) {
3496                 case 26:
3497                 case 30:
3498                 case 37:
3499                 case 44:
3500                 case 46:
3501                         cpu_has_load_perf_global_ctrl = false;
3502                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3503                                         "does not work properly. Using workaround\n");
3504                         break;
3505                 default:
3506                         break;
3507                 }
3508         }
3509
3510         if (boot_cpu_has(X86_FEATURE_XSAVES))
3511                 rdmsrl(MSR_IA32_XSS, host_xss);
3512
3513         return 0;
3514 }
3515
3516 static struct vmcs *alloc_vmcs_cpu(int cpu)
3517 {
3518         int node = cpu_to_node(cpu);
3519         struct page *pages;
3520         struct vmcs *vmcs;
3521
3522         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3523         if (!pages)
3524                 return NULL;
3525         vmcs = page_address(pages);
3526         memset(vmcs, 0, vmcs_config.size);
3527         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3528         return vmcs;
3529 }
3530
3531 static struct vmcs *alloc_vmcs(void)
3532 {
3533         return alloc_vmcs_cpu(raw_smp_processor_id());
3534 }
3535
3536 static void free_vmcs(struct vmcs *vmcs)
3537 {
3538         free_pages((unsigned long)vmcs, vmcs_config.order);
3539 }
3540
3541 /*
3542  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3543  */
3544 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3545 {
3546         if (!loaded_vmcs->vmcs)
3547                 return;
3548         loaded_vmcs_clear(loaded_vmcs);
3549         free_vmcs(loaded_vmcs->vmcs);
3550         loaded_vmcs->vmcs = NULL;
3551 }
3552
3553 static void free_kvm_area(void)
3554 {
3555         int cpu;
3556
3557         for_each_possible_cpu(cpu) {
3558                 free_vmcs(per_cpu(vmxarea, cpu));
3559                 per_cpu(vmxarea, cpu) = NULL;
3560         }
3561 }
3562
3563 static void init_vmcs_shadow_fields(void)
3564 {
3565         int i, j;
3566
3567         /* No checks for read only fields yet */
3568
3569         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3570                 switch (shadow_read_write_fields[i]) {
3571                 case GUEST_BNDCFGS:
3572                         if (!kvm_mpx_supported())
3573                                 continue;
3574                         break;
3575                 default:
3576                         break;
3577                 }
3578
3579                 if (j < i)
3580                         shadow_read_write_fields[j] =
3581                                 shadow_read_write_fields[i];
3582                 j++;
3583         }
3584         max_shadow_read_write_fields = j;
3585
3586         /* shadowed fields guest access without vmexit */
3587         for (i = 0; i < max_shadow_read_write_fields; i++) {
3588                 clear_bit(shadow_read_write_fields[i],
3589                           vmx_vmwrite_bitmap);
3590                 clear_bit(shadow_read_write_fields[i],
3591                           vmx_vmread_bitmap);
3592         }
3593         for (i = 0; i < max_shadow_read_only_fields; i++)
3594                 clear_bit(shadow_read_only_fields[i],
3595                           vmx_vmread_bitmap);
3596 }
3597
3598 static __init int alloc_kvm_area(void)
3599 {
3600         int cpu;
3601
3602         for_each_possible_cpu(cpu) {
3603                 struct vmcs *vmcs;
3604
3605                 vmcs = alloc_vmcs_cpu(cpu);
3606                 if (!vmcs) {
3607                         free_kvm_area();
3608                         return -ENOMEM;
3609                 }
3610
3611                 per_cpu(vmxarea, cpu) = vmcs;
3612         }
3613         return 0;
3614 }
3615
3616 static bool emulation_required(struct kvm_vcpu *vcpu)
3617 {
3618         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3619 }
3620
3621 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3622                 struct kvm_segment *save)
3623 {
3624         if (!emulate_invalid_guest_state) {
3625                 /*
3626                  * CS and SS RPL should be equal during guest entry according
3627                  * to VMX spec, but in reality it is not always so. Since vcpu
3628                  * is in the middle of the transition from real mode to
3629                  * protected mode it is safe to assume that RPL 0 is a good
3630                  * default value.
3631                  */
3632                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3633                         save->selector &= ~SEGMENT_RPL_MASK;
3634                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3635                 save->s = 1;
3636         }
3637         vmx_set_segment(vcpu, save, seg);
3638 }
3639
3640 static void enter_pmode(struct kvm_vcpu *vcpu)
3641 {
3642         unsigned long flags;
3643         struct vcpu_vmx *vmx = to_vmx(vcpu);
3644
3645         /*
3646          * Update real mode segment cache. It may be not up-to-date if sement
3647          * register was written while vcpu was in a guest mode.
3648          */
3649         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3650         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3651         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3652         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3653         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3654         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3655
3656         vmx->rmode.vm86_active = 0;
3657
3658         vmx_segment_cache_clear(vmx);
3659
3660         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3661
3662         flags = vmcs_readl(GUEST_RFLAGS);
3663         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3664         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3665         vmcs_writel(GUEST_RFLAGS, flags);
3666
3667         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3668                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3669
3670         update_exception_bitmap(vcpu);
3671
3672         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3673         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3674         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3675         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3676         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3677         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3678 }
3679
3680 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3681 {
3682         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3683         struct kvm_segment var = *save;
3684
3685         var.dpl = 0x3;
3686         if (seg == VCPU_SREG_CS)
3687                 var.type = 0x3;
3688
3689         if (!emulate_invalid_guest_state) {
3690                 var.selector = var.base >> 4;
3691                 var.base = var.base & 0xffff0;
3692                 var.limit = 0xffff;
3693                 var.g = 0;
3694                 var.db = 0;
3695                 var.present = 1;
3696                 var.s = 1;
3697                 var.l = 0;
3698                 var.unusable = 0;
3699                 var.type = 0x3;
3700                 var.avl = 0;
3701                 if (save->base & 0xf)
3702                         printk_once(KERN_WARNING "kvm: segment base is not "
3703                                         "paragraph aligned when entering "
3704                                         "protected mode (seg=%d)", seg);
3705         }
3706
3707         vmcs_write16(sf->selector, var.selector);
3708         vmcs_write32(sf->base, var.base);
3709         vmcs_write32(sf->limit, var.limit);
3710         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3711 }
3712
3713 static void enter_rmode(struct kvm_vcpu *vcpu)
3714 {
3715         unsigned long flags;
3716         struct vcpu_vmx *vmx = to_vmx(vcpu);
3717
3718         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3719         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3720         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3721         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3722         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3723         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3724         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3725
3726         vmx->rmode.vm86_active = 1;
3727
3728         /*
3729          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3730          * vcpu. Warn the user that an update is overdue.
3731          */
3732         if (!vcpu->kvm->arch.tss_addr)
3733                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3734                              "called before entering vcpu\n");
3735
3736         vmx_segment_cache_clear(vmx);
3737
3738         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3739         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3740         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3741
3742         flags = vmcs_readl(GUEST_RFLAGS);
3743         vmx->rmode.save_rflags = flags;
3744
3745         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3746
3747         vmcs_writel(GUEST_RFLAGS, flags);
3748         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3749         update_exception_bitmap(vcpu);
3750
3751         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3752         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3753         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3754         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3755         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3756         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3757
3758         kvm_mmu_reset_context(vcpu);
3759 }
3760
3761 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3762 {
3763         struct vcpu_vmx *vmx = to_vmx(vcpu);
3764         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3765
3766         if (!msr)
3767                 return;
3768
3769         /*
3770          * Force kernel_gs_base reloading before EFER changes, as control
3771          * of this msr depends on is_long_mode().
3772          */
3773         vmx_load_host_state(to_vmx(vcpu));
3774         vcpu->arch.efer = efer;
3775         if (efer & EFER_LMA) {
3776                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3777                 msr->data = efer;
3778         } else {
3779                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3780
3781                 msr->data = efer & ~EFER_LME;
3782         }
3783         setup_msrs(vmx);
3784 }
3785
3786 #ifdef CONFIG_X86_64
3787
3788 static void enter_lmode(struct kvm_vcpu *vcpu)
3789 {
3790         u32 guest_tr_ar;
3791
3792         vmx_segment_cache_clear(to_vmx(vcpu));
3793
3794         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3795         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
3796                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3797                                      __func__);
3798                 vmcs_write32(GUEST_TR_AR_BYTES,
3799                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3800                              | VMX_AR_TYPE_BUSY_64_TSS);
3801         }
3802         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3803 }
3804
3805 static void exit_lmode(struct kvm_vcpu *vcpu)
3806 {
3807         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3808         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3809 }
3810
3811 #endif
3812
3813 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
3814 {
3815         vpid_sync_context(vpid);
3816         if (enable_ept) {
3817                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3818                         return;
3819                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3820         }
3821 }
3822
3823 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3824 {
3825         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
3826 }
3827
3828 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3829 {
3830         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3831
3832         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3833         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3834 }
3835
3836 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3837 {
3838         if (enable_ept && is_paging(vcpu))
3839                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3840         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3841 }
3842
3843 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3844 {
3845         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3846
3847         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3848         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3849 }
3850
3851 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3852 {
3853         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3854
3855         if (!test_bit(VCPU_EXREG_PDPTR,
3856                       (unsigned long *)&vcpu->arch.regs_dirty))
3857                 return;
3858
3859         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3860                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3861                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3862                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3863                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3864         }
3865 }
3866
3867 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3868 {
3869         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3870
3871         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3872                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3873                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3874                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3875                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3876         }
3877
3878         __set_bit(VCPU_EXREG_PDPTR,
3879                   (unsigned long *)&vcpu->arch.regs_avail);
3880         __set_bit(VCPU_EXREG_PDPTR,
3881                   (unsigned long *)&vcpu->arch.regs_dirty);
3882 }
3883
3884 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3885
3886 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3887                                         unsigned long cr0,
3888                                         struct kvm_vcpu *vcpu)
3889 {
3890         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3891                 vmx_decache_cr3(vcpu);
3892         if (!(cr0 & X86_CR0_PG)) {
3893                 /* From paging/starting to nonpaging */
3894                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3895                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3896                              (CPU_BASED_CR3_LOAD_EXITING |
3897                               CPU_BASED_CR3_STORE_EXITING));
3898                 vcpu->arch.cr0 = cr0;
3899                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3900         } else if (!is_paging(vcpu)) {
3901                 /* From nonpaging to paging */
3902                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3903                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3904                              ~(CPU_BASED_CR3_LOAD_EXITING |
3905                                CPU_BASED_CR3_STORE_EXITING));
3906                 vcpu->arch.cr0 = cr0;
3907                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3908         }
3909
3910         if (!(cr0 & X86_CR0_WP))
3911                 *hw_cr0 &= ~X86_CR0_WP;
3912 }
3913
3914 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3915 {
3916         struct vcpu_vmx *vmx = to_vmx(vcpu);
3917         unsigned long hw_cr0;
3918
3919         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3920         if (enable_unrestricted_guest)
3921                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3922         else {
3923                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3924
3925                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3926                         enter_pmode(vcpu);
3927
3928                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3929                         enter_rmode(vcpu);
3930         }
3931
3932 #ifdef CONFIG_X86_64
3933         if (vcpu->arch.efer & EFER_LME) {
3934                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3935                         enter_lmode(vcpu);
3936                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3937                         exit_lmode(vcpu);
3938         }
3939 #endif
3940
3941         if (enable_ept)
3942                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3943
3944         if (!vcpu->fpu_active)
3945                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3946
3947         vmcs_writel(CR0_READ_SHADOW, cr0);
3948         vmcs_writel(GUEST_CR0, hw_cr0);
3949         vcpu->arch.cr0 = cr0;
3950
3951         /* depends on vcpu->arch.cr0 to be set to a new value */
3952         vmx->emulation_required = emulation_required(vcpu);
3953 }
3954
3955 static u64 construct_eptp(unsigned long root_hpa)
3956 {
3957         u64 eptp;
3958
3959         /* TODO write the value reading from MSR */
3960         eptp = VMX_EPT_DEFAULT_MT |
3961                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3962         if (enable_ept_ad_bits)
3963                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3964         eptp |= (root_hpa & PAGE_MASK);
3965
3966         return eptp;
3967 }
3968
3969 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3970 {
3971         unsigned long guest_cr3;
3972         u64 eptp;
3973
3974         guest_cr3 = cr3;
3975         if (enable_ept) {
3976                 eptp = construct_eptp(cr3);
3977                 vmcs_write64(EPT_POINTER, eptp);
3978                 if (is_paging(vcpu) || is_guest_mode(vcpu))
3979                         guest_cr3 = kvm_read_cr3(vcpu);
3980                 else
3981                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3982                 ept_load_pdptrs(vcpu);
3983         }
3984
3985         vmx_flush_tlb(vcpu);
3986         vmcs_writel(GUEST_CR3, guest_cr3);
3987 }
3988
3989 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3990 {
3991         /*
3992          * Pass through host's Machine Check Enable value to hw_cr4, which
3993          * is in force while we are in guest mode.  Do not let guests control
3994          * this bit, even if host CR4.MCE == 0.
3995          */
3996         unsigned long hw_cr4 =
3997                 (cr4_read_shadow() & X86_CR4_MCE) |
3998                 (cr4 & ~X86_CR4_MCE) |
3999                 (to_vmx(vcpu)->rmode.vm86_active ?
4000                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
4001
4002         if (cr4 & X86_CR4_VMXE) {
4003                 /*
4004                  * To use VMXON (and later other VMX instructions), a guest
4005                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
4006                  * So basically the check on whether to allow nested VMX
4007                  * is here.
4008                  */
4009                 if (!nested_vmx_allowed(vcpu))
4010                         return 1;
4011         }
4012         if (to_vmx(vcpu)->nested.vmxon &&
4013             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
4014                 return 1;
4015
4016         vcpu->arch.cr4 = cr4;
4017         if (enable_ept) {
4018                 if (!is_paging(vcpu)) {
4019                         hw_cr4 &= ~X86_CR4_PAE;
4020                         hw_cr4 |= X86_CR4_PSE;
4021                 } else if (!(cr4 & X86_CR4_PAE)) {
4022                         hw_cr4 &= ~X86_CR4_PAE;
4023                 }
4024         }
4025
4026         if (!enable_unrestricted_guest && !is_paging(vcpu))
4027                 /*
4028                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4029                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
4030                  * to be manually disabled when guest switches to non-paging
4031                  * mode.
4032                  *
4033                  * If !enable_unrestricted_guest, the CPU is always running
4034                  * with CR0.PG=1 and CR4 needs to be modified.
4035                  * If enable_unrestricted_guest, the CPU automatically
4036                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4037                  */
4038                 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
4039
4040         vmcs_writel(CR4_READ_SHADOW, cr4);
4041         vmcs_writel(GUEST_CR4, hw_cr4);
4042         return 0;
4043 }
4044
4045 static void vmx_get_segment(struct kvm_vcpu *vcpu,
4046                             struct kvm_segment *var, int seg)
4047 {
4048         struct vcpu_vmx *vmx = to_vmx(vcpu);
4049         u32 ar;
4050
4051         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4052                 *var = vmx->rmode.segs[seg];
4053                 if (seg == VCPU_SREG_TR
4054                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
4055                         return;
4056                 var->base = vmx_read_guest_seg_base(vmx, seg);
4057                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4058                 return;
4059         }
4060         var->base = vmx_read_guest_seg_base(vmx, seg);
4061         var->limit = vmx_read_guest_seg_limit(vmx, seg);
4062         var->selector = vmx_read_guest_seg_selector(vmx, seg);
4063         ar = vmx_read_guest_seg_ar(vmx, seg);
4064         var->unusable = (ar >> 16) & 1;
4065         var->type = ar & 15;
4066         var->s = (ar >> 4) & 1;
4067         var->dpl = (ar >> 5) & 3;
4068         /*
4069          * Some userspaces do not preserve unusable property. Since usable
4070          * segment has to be present according to VMX spec we can use present
4071          * property to amend userspace bug by making unusable segment always
4072          * nonpresent. vmx_segment_access_rights() already marks nonpresent
4073          * segment as unusable.
4074          */
4075         var->present = !var->unusable;
4076         var->avl = (ar >> 12) & 1;
4077         var->l = (ar >> 13) & 1;
4078         var->db = (ar >> 14) & 1;
4079         var->g = (ar >> 15) & 1;
4080 }
4081
4082 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
4083 {
4084         struct kvm_segment s;
4085
4086         if (to_vmx(vcpu)->rmode.vm86_active) {
4087                 vmx_get_segment(vcpu, &s, seg);
4088                 return s.base;
4089         }
4090         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
4091 }
4092
4093 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
4094 {
4095         struct vcpu_vmx *vmx = to_vmx(vcpu);
4096
4097         if (unlikely(vmx->rmode.vm86_active))
4098                 return 0;
4099         else {
4100                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4101                 return VMX_AR_DPL(ar);
4102         }
4103 }
4104
4105 static u32 vmx_segment_access_rights(struct kvm_segment *var)
4106 {
4107         u32 ar;
4108
4109         if (var->unusable || !var->present)
4110                 ar = 1 << 16;
4111         else {
4112                 ar = var->type & 15;
4113                 ar |= (var->s & 1) << 4;
4114                 ar |= (var->dpl & 3) << 5;
4115                 ar |= (var->present & 1) << 7;
4116                 ar |= (var->avl & 1) << 12;
4117                 ar |= (var->l & 1) << 13;
4118                 ar |= (var->db & 1) << 14;
4119                 ar |= (var->g & 1) << 15;
4120         }
4121
4122         return ar;
4123 }
4124
4125 static void vmx_set_segment(struct kvm_vcpu *vcpu,
4126                             struct kvm_segment *var, int seg)
4127 {
4128         struct vcpu_vmx *vmx = to_vmx(vcpu);
4129         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4130
4131         vmx_segment_cache_clear(vmx);
4132
4133         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4134                 vmx->rmode.segs[seg] = *var;
4135                 if (seg == VCPU_SREG_TR)
4136                         vmcs_write16(sf->selector, var->selector);
4137                 else if (var->s)
4138                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
4139                 goto out;
4140         }
4141
4142         vmcs_writel(sf->base, var->base);
4143         vmcs_write32(sf->limit, var->limit);
4144         vmcs_write16(sf->selector, var->selector);
4145
4146         /*
4147          *   Fix the "Accessed" bit in AR field of segment registers for older
4148          * qemu binaries.
4149          *   IA32 arch specifies that at the time of processor reset the
4150          * "Accessed" bit in the AR field of segment registers is 1. And qemu
4151          * is setting it to 0 in the userland code. This causes invalid guest
4152          * state vmexit when "unrestricted guest" mode is turned on.
4153          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
4154          * tree. Newer qemu binaries with that qemu fix would not need this
4155          * kvm hack.
4156          */
4157         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
4158                 var->type |= 0x1; /* Accessed */
4159
4160         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
4161
4162 out:
4163         vmx->emulation_required = emulation_required(vcpu);
4164 }
4165
4166 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4167 {
4168         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4169
4170         *db = (ar >> 14) & 1;
4171         *l = (ar >> 13) & 1;
4172 }
4173
4174 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4175 {
4176         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4177         dt->address = vmcs_readl(GUEST_IDTR_BASE);
4178 }
4179
4180 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4181 {
4182         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4183         vmcs_writel(GUEST_IDTR_BASE, dt->address);
4184 }
4185
4186 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4187 {
4188         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4189         dt->address = vmcs_readl(GUEST_GDTR_BASE);
4190 }
4191
4192 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4193 {
4194         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4195         vmcs_writel(GUEST_GDTR_BASE, dt->address);
4196 }
4197
4198 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4199 {
4200         struct kvm_segment var;
4201         u32 ar;
4202
4203         vmx_get_segment(vcpu, &var, seg);
4204         var.dpl = 0x3;
4205         if (seg == VCPU_SREG_CS)
4206                 var.type = 0x3;
4207         ar = vmx_segment_access_rights(&var);
4208
4209         if (var.base != (var.selector << 4))
4210                 return false;
4211         if (var.limit != 0xffff)
4212                 return false;
4213         if (ar != 0xf3)
4214                 return false;
4215
4216         return true;
4217 }
4218
4219 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4220 {
4221         struct kvm_segment cs;
4222         unsigned int cs_rpl;
4223
4224         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4225         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4226
4227         if (cs.unusable)
4228                 return false;
4229         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4230                 return false;
4231         if (!cs.s)
4232                 return false;
4233         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4234                 if (cs.dpl > cs_rpl)
4235                         return false;
4236         } else {
4237                 if (cs.dpl != cs_rpl)
4238                         return false;
4239         }
4240         if (!cs.present)
4241                 return false;
4242
4243         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4244         return true;
4245 }
4246
4247 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4248 {
4249         struct kvm_segment ss;
4250         unsigned int ss_rpl;
4251
4252         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4253         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4254
4255         if (ss.unusable)
4256                 return true;
4257         if (ss.type != 3 && ss.type != 7)
4258                 return false;
4259         if (!ss.s)
4260                 return false;
4261         if (ss.dpl != ss_rpl) /* DPL != RPL */
4262                 return false;
4263         if (!ss.present)
4264                 return false;
4265
4266         return true;
4267 }
4268
4269 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4270 {
4271         struct kvm_segment var;
4272         unsigned int rpl;
4273
4274         vmx_get_segment(vcpu, &var, seg);
4275         rpl = var.selector & SEGMENT_RPL_MASK;
4276
4277         if (var.unusable)
4278                 return true;
4279         if (!var.s)
4280                 return false;
4281         if (!var.present)
4282                 return false;
4283         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4284                 if (var.dpl < rpl) /* DPL < RPL */
4285                         return false;
4286         }
4287
4288         /* TODO: Add other members to kvm_segment_field to allow checking for other access
4289          * rights flags
4290          */
4291         return true;
4292 }
4293
4294 static bool tr_valid(struct kvm_vcpu *vcpu)
4295 {
4296         struct kvm_segment tr;
4297
4298         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4299
4300         if (tr.unusable)
4301                 return false;
4302         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
4303                 return false;
4304         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4305                 return false;
4306         if (!tr.present)
4307                 return false;
4308
4309         return true;
4310 }
4311
4312 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4313 {
4314         struct kvm_segment ldtr;
4315
4316         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4317
4318         if (ldtr.unusable)
4319                 return true;
4320         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
4321                 return false;
4322         if (ldtr.type != 2)
4323                 return false;
4324         if (!ldtr.present)
4325                 return false;
4326
4327         return true;
4328 }
4329
4330 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4331 {
4332         struct kvm_segment cs, ss;
4333
4334         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4335         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4336
4337         return ((cs.selector & SEGMENT_RPL_MASK) ==
4338                  (ss.selector & SEGMENT_RPL_MASK));
4339 }
4340
4341 /*
4342  * Check if guest state is valid. Returns true if valid, false if
4343  * not.
4344  * We assume that registers are always usable
4345  */
4346 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4347 {
4348         if (enable_unrestricted_guest)
4349                 return true;
4350
4351         /* real mode guest state checks */
4352         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4353                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4354                         return false;
4355                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4356                         return false;
4357                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4358                         return false;
4359                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4360                         return false;
4361                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4362                         return false;
4363                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4364                         return false;
4365         } else {
4366         /* protected mode guest state checks */
4367                 if (!cs_ss_rpl_check(vcpu))
4368                         return false;
4369                 if (!code_segment_valid(vcpu))
4370                         return false;
4371                 if (!stack_segment_valid(vcpu))
4372                         return false;
4373                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4374                         return false;
4375                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4376                         return false;
4377                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4378                         return false;
4379                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4380                         return false;
4381                 if (!tr_valid(vcpu))
4382                         return false;
4383                 if (!ldtr_valid(vcpu))
4384                         return false;
4385         }
4386         /* TODO:
4387          * - Add checks on RIP
4388          * - Add checks on RFLAGS
4389          */
4390
4391         return true;
4392 }
4393
4394 static int init_rmode_tss(struct kvm *kvm)
4395 {
4396         gfn_t fn;
4397         u16 data = 0;
4398         int idx, r;
4399
4400         idx = srcu_read_lock(&kvm->srcu);
4401         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4402         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4403         if (r < 0)
4404                 goto out;
4405         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4406         r = kvm_write_guest_page(kvm, fn++, &data,
4407                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4408         if (r < 0)
4409                 goto out;
4410         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4411         if (r < 0)
4412                 goto out;
4413         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4414         if (r < 0)
4415                 goto out;
4416         data = ~0;
4417         r = kvm_write_guest_page(kvm, fn, &data,
4418                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4419                                  sizeof(u8));
4420 out:
4421         srcu_read_unlock(&kvm->srcu, idx);
4422         return r;
4423 }
4424
4425 static int init_rmode_identity_map(struct kvm *kvm)
4426 {
4427         int i, idx, r = 0;
4428         kvm_pfn_t identity_map_pfn;
4429         u32 tmp;
4430
4431         if (!enable_ept)
4432                 return 0;
4433
4434         /* Protect kvm->arch.ept_identity_pagetable_done. */
4435         mutex_lock(&kvm->slots_lock);
4436
4437         if (likely(kvm->arch.ept_identity_pagetable_done))
4438                 goto out2;
4439
4440         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4441
4442         r = alloc_identity_pagetable(kvm);
4443         if (r < 0)
4444                 goto out2;
4445
4446         idx = srcu_read_lock(&kvm->srcu);
4447         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4448         if (r < 0)
4449                 goto out;
4450         /* Set up identity-mapping pagetable for EPT in real mode */
4451         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4452                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4453                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4454                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4455                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4456                 if (r < 0)
4457                         goto out;
4458         }
4459         kvm->arch.ept_identity_pagetable_done = true;
4460
4461 out:
4462         srcu_read_unlock(&kvm->srcu, idx);
4463
4464 out2:
4465         mutex_unlock(&kvm->slots_lock);
4466         return r;
4467 }
4468
4469 static void seg_setup(int seg)
4470 {
4471         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4472         unsigned int ar;
4473
4474         vmcs_write16(sf->selector, 0);
4475         vmcs_writel(sf->base, 0);
4476         vmcs_write32(sf->limit, 0xffff);
4477         ar = 0x93;
4478         if (seg == VCPU_SREG_CS)
4479                 ar |= 0x08; /* code segment */
4480
4481         vmcs_write32(sf->ar_bytes, ar);
4482 }
4483
4484 static int alloc_apic_access_page(struct kvm *kvm)
4485 {
4486         struct page *page;
4487         int r = 0;
4488
4489         mutex_lock(&kvm->slots_lock);
4490         if (kvm->arch.apic_access_page_done)
4491                 goto out;
4492         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4493                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4494         if (r)
4495                 goto out;
4496
4497         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4498         if (is_error_page(page)) {
4499                 r = -EFAULT;
4500                 goto out;
4501         }
4502
4503         /*
4504          * Do not pin the page in memory, so that memory hot-unplug
4505          * is able to migrate it.
4506          */
4507         put_page(page);
4508         kvm->arch.apic_access_page_done = true;
4509 out:
4510         mutex_unlock(&kvm->slots_lock);
4511         return r;
4512 }
4513
4514 static int alloc_identity_pagetable(struct kvm *kvm)
4515 {
4516         /* Called with kvm->slots_lock held. */
4517
4518         int r = 0;
4519
4520         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4521
4522         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4523                                     kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4524
4525         return r;
4526 }
4527
4528 static int allocate_vpid(void)
4529 {
4530         int vpid;
4531
4532         if (!enable_vpid)
4533                 return 0;
4534         spin_lock(&vmx_vpid_lock);
4535         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4536         if (vpid < VMX_NR_VPIDS)
4537                 __set_bit(vpid, vmx_vpid_bitmap);
4538         else
4539                 vpid = 0;
4540         spin_unlock(&vmx_vpid_lock);
4541         return vpid;
4542 }
4543
4544 static void free_vpid(int vpid)
4545 {
4546         if (!enable_vpid || vpid == 0)
4547                 return;
4548         spin_lock(&vmx_vpid_lock);
4549         __clear_bit(vpid, vmx_vpid_bitmap);
4550         spin_unlock(&vmx_vpid_lock);
4551 }
4552
4553 #define MSR_TYPE_R      1
4554 #define MSR_TYPE_W      2
4555 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4556                                                 u32 msr, int type)
4557 {
4558         int f = sizeof(unsigned long);
4559
4560         if (!cpu_has_vmx_msr_bitmap())
4561                 return;
4562
4563         /*
4564          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4565          * have the write-low and read-high bitmap offsets the wrong way round.
4566          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4567          */
4568         if (msr <= 0x1fff) {
4569                 if (type & MSR_TYPE_R)
4570                         /* read-low */
4571                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4572
4573                 if (type & MSR_TYPE_W)
4574                         /* write-low */
4575                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4576
4577         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4578                 msr &= 0x1fff;
4579                 if (type & MSR_TYPE_R)
4580                         /* read-high */
4581                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4582
4583                 if (type & MSR_TYPE_W)
4584                         /* write-high */
4585                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4586
4587         }
4588 }
4589
4590 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4591                                                 u32 msr, int type)
4592 {
4593         int f = sizeof(unsigned long);
4594
4595         if (!cpu_has_vmx_msr_bitmap())
4596                 return;
4597
4598         /*
4599          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4600          * have the write-low and read-high bitmap offsets the wrong way round.
4601          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4602          */
4603         if (msr <= 0x1fff) {
4604                 if (type & MSR_TYPE_R)
4605                         /* read-low */
4606                         __set_bit(msr, msr_bitmap + 0x000 / f);
4607
4608                 if (type & MSR_TYPE_W)
4609                         /* write-low */
4610                         __set_bit(msr, msr_bitmap + 0x800 / f);
4611
4612         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4613                 msr &= 0x1fff;
4614                 if (type & MSR_TYPE_R)
4615                         /* read-high */
4616                         __set_bit(msr, msr_bitmap + 0x400 / f);
4617
4618                 if (type & MSR_TYPE_W)
4619                         /* write-high */
4620                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4621
4622         }
4623 }
4624
4625 /*
4626  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4627  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4628  */
4629 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4630                                                unsigned long *msr_bitmap_nested,
4631                                                u32 msr, int type)
4632 {
4633         int f = sizeof(unsigned long);
4634
4635         if (!cpu_has_vmx_msr_bitmap()) {
4636                 WARN_ON(1);
4637                 return;
4638         }
4639
4640         /*
4641          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4642          * have the write-low and read-high bitmap offsets the wrong way round.
4643          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4644          */
4645         if (msr <= 0x1fff) {
4646                 if (type & MSR_TYPE_R &&
4647                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4648                         /* read-low */
4649                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4650
4651                 if (type & MSR_TYPE_W &&
4652                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4653                         /* write-low */
4654                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4655
4656         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4657                 msr &= 0x1fff;
4658                 if (type & MSR_TYPE_R &&
4659                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4660                         /* read-high */
4661                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4662
4663                 if (type & MSR_TYPE_W &&
4664                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4665                         /* write-high */
4666                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4667
4668         }
4669 }
4670
4671 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4672 {
4673         if (!longmode_only)
4674                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4675                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4676         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4677                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4678 }
4679
4680 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4681 {
4682         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4683                         msr, MSR_TYPE_R);
4684         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4685                         msr, MSR_TYPE_R);
4686 }
4687
4688 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4689 {
4690         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4691                         msr, MSR_TYPE_R);
4692         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4693                         msr, MSR_TYPE_R);
4694 }
4695
4696 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4697 {
4698         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4699                         msr, MSR_TYPE_W);
4700         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4701                         msr, MSR_TYPE_W);
4702 }
4703
4704 static bool vmx_get_enable_apicv(void)
4705 {
4706         return enable_apicv;
4707 }
4708
4709 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4710 {
4711         struct vcpu_vmx *vmx = to_vmx(vcpu);
4712         int max_irr;
4713         void *vapic_page;
4714         u16 status;
4715
4716         if (vmx->nested.pi_desc &&
4717             vmx->nested.pi_pending) {
4718                 vmx->nested.pi_pending = false;
4719                 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4720                         return 0;
4721
4722                 max_irr = find_last_bit(
4723                         (unsigned long *)vmx->nested.pi_desc->pir, 256);
4724
4725                 if (max_irr == 256)
4726                         return 0;
4727
4728                 vapic_page = kmap(vmx->nested.virtual_apic_page);
4729                 if (!vapic_page) {
4730                         WARN_ON(1);
4731                         return -ENOMEM;
4732                 }
4733                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4734                 kunmap(vmx->nested.virtual_apic_page);
4735
4736                 status = vmcs_read16(GUEST_INTR_STATUS);
4737                 if ((u8)max_irr > ((u8)status & 0xff)) {
4738                         status &= ~0xff;
4739                         status |= (u8)max_irr;
4740                         vmcs_write16(GUEST_INTR_STATUS, status);
4741                 }
4742         }
4743         return 0;
4744 }
4745
4746 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4747 {
4748 #ifdef CONFIG_SMP
4749         if (vcpu->mode == IN_GUEST_MODE) {
4750                 struct vcpu_vmx *vmx = to_vmx(vcpu);
4751
4752                 /*
4753                  * Currently, we don't support urgent interrupt,
4754                  * all interrupts are recognized as non-urgent
4755                  * interrupt, so we cannot post interrupts when
4756                  * 'SN' is set.
4757                  *
4758                  * If the vcpu is in guest mode, it means it is
4759                  * running instead of being scheduled out and
4760                  * waiting in the run queue, and that's the only
4761                  * case when 'SN' is set currently, warning if
4762                  * 'SN' is set.
4763                  */
4764                 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4765
4766                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4767                                 POSTED_INTR_VECTOR);
4768                 return true;
4769         }
4770 #endif
4771         return false;
4772 }
4773
4774 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4775                                                 int vector)
4776 {
4777         struct vcpu_vmx *vmx = to_vmx(vcpu);
4778
4779         if (is_guest_mode(vcpu) &&
4780             vector == vmx->nested.posted_intr_nv) {
4781                 /* the PIR and ON have been set by L1. */
4782                 kvm_vcpu_trigger_posted_interrupt(vcpu);
4783                 /*
4784                  * If a posted intr is not recognized by hardware,
4785                  * we will accomplish it in the next vmentry.
4786                  */
4787                 vmx->nested.pi_pending = true;
4788                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4789                 return 0;
4790         }
4791         return -1;
4792 }
4793 /*
4794  * Send interrupt to vcpu via posted interrupt way.
4795  * 1. If target vcpu is running(non-root mode), send posted interrupt
4796  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4797  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4798  * interrupt from PIR in next vmentry.
4799  */
4800 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4801 {
4802         struct vcpu_vmx *vmx = to_vmx(vcpu);
4803         int r;
4804
4805         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4806         if (!r)
4807                 return;
4808
4809         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4810                 return;
4811
4812         r = pi_test_and_set_on(&vmx->pi_desc);
4813         kvm_make_request(KVM_REQ_EVENT, vcpu);
4814         if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
4815                 kvm_vcpu_kick(vcpu);
4816 }
4817
4818 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4819 {
4820         struct vcpu_vmx *vmx = to_vmx(vcpu);
4821
4822         if (!pi_test_and_clear_on(&vmx->pi_desc))
4823                 return;
4824
4825         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4826 }
4827
4828 /*
4829  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4830  * will not change in the lifetime of the guest.
4831  * Note that host-state that does change is set elsewhere. E.g., host-state
4832  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4833  */
4834 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4835 {
4836         u32 low32, high32;
4837         unsigned long tmpl;
4838         struct desc_ptr dt;
4839         unsigned long cr4;
4840
4841         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4842         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4843
4844         /* Save the most likely value for this task's CR4 in the VMCS. */
4845         cr4 = cr4_read_shadow();
4846         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
4847         vmx->host_state.vmcs_host_cr4 = cr4;
4848
4849         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4850 #ifdef CONFIG_X86_64
4851         /*
4852          * Load null selectors, so we can avoid reloading them in
4853          * __vmx_load_host_state(), in case userspace uses the null selectors
4854          * too (the expected case).
4855          */
4856         vmcs_write16(HOST_DS_SELECTOR, 0);
4857         vmcs_write16(HOST_ES_SELECTOR, 0);
4858 #else
4859         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4860         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4861 #endif
4862         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4863         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4864
4865         native_store_idt(&dt);
4866         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4867         vmx->host_idt_base = dt.address;
4868
4869         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4870
4871         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4872         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4873         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4874         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4875
4876         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4877                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4878                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4879         }
4880 }
4881
4882 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4883 {
4884         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4885         if (enable_ept)
4886                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4887         if (is_guest_mode(&vmx->vcpu))
4888                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4889                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4890         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4891 }
4892
4893 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4894 {
4895         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4896
4897         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4898                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4899         /* Enable the preemption timer dynamically */
4900         pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
4901         return pin_based_exec_ctrl;
4902 }
4903
4904 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4905 {
4906         struct vcpu_vmx *vmx = to_vmx(vcpu);
4907
4908         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4909         if (cpu_has_secondary_exec_ctrls()) {
4910                 if (kvm_vcpu_apicv_active(vcpu))
4911                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
4912                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
4913                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4914                 else
4915                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
4916                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
4917                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4918         }
4919
4920         if (cpu_has_vmx_msr_bitmap())
4921                 vmx_set_msr_bitmap(vcpu);
4922 }
4923
4924 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4925 {
4926         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4927
4928         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4929                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4930
4931         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4932                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4933 #ifdef CONFIG_X86_64
4934                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4935                                 CPU_BASED_CR8_LOAD_EXITING;
4936 #endif
4937         }
4938         if (!enable_ept)
4939                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4940                                 CPU_BASED_CR3_LOAD_EXITING  |
4941                                 CPU_BASED_INVLPG_EXITING;
4942         return exec_control;
4943 }
4944
4945 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4946 {
4947         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4948         if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
4949                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4950         if (vmx->vpid == 0)
4951                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4952         if (!enable_ept) {
4953                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4954                 enable_unrestricted_guest = 0;
4955                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4956                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4957         }
4958         if (!enable_unrestricted_guest)
4959                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4960         if (!ple_gap)
4961                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4962         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4963                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4964                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4965         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4966         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4967            (handle_vmptrld).
4968            We can NOT enable shadow_vmcs here because we don't have yet
4969            a current VMCS12
4970         */
4971         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4972
4973         if (!enable_pml)
4974                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4975
4976         /* Currently, we allow L1 guest to directly run pcommit instruction. */
4977         exec_control &= ~SECONDARY_EXEC_PCOMMIT;
4978
4979         return exec_control;
4980 }
4981
4982 static void ept_set_mmio_spte_mask(void)
4983 {
4984         /*
4985          * EPT Misconfigurations can be generated if the value of bits 2:0
4986          * of an EPT paging-structure entry is 110b (write/execute).
4987          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4988          * spte.
4989          */
4990         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4991 }
4992
4993 #define VMX_XSS_EXIT_BITMAP 0
4994 /*
4995  * Sets up the vmcs for emulated real mode.
4996  */
4997 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4998 {
4999 #ifdef CONFIG_X86_64
5000         unsigned long a;
5001 #endif
5002         int i;
5003
5004         /* I/O */
5005         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
5006         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
5007
5008         if (enable_shadow_vmcs) {
5009                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
5010                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
5011         }
5012         if (cpu_has_vmx_msr_bitmap())
5013                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
5014
5015         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
5016
5017         /* Control */
5018         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5019         vmx->hv_deadline_tsc = -1;
5020
5021         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
5022
5023         if (cpu_has_secondary_exec_ctrls())
5024                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5025                                 vmx_secondary_exec_control(vmx));
5026
5027         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
5028                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
5029                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
5030                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
5031                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
5032
5033                 vmcs_write16(GUEST_INTR_STATUS, 0);
5034
5035                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
5036                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
5037         }
5038
5039         if (ple_gap) {
5040                 vmcs_write32(PLE_GAP, ple_gap);
5041                 vmx->ple_window = ple_window;
5042                 vmx->ple_window_dirty = true;
5043         }
5044
5045         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
5046         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
5047         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
5048
5049         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
5050         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
5051         vmx_set_constant_host_state(vmx);
5052 #ifdef CONFIG_X86_64
5053         rdmsrl(MSR_FS_BASE, a);
5054         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
5055         rdmsrl(MSR_GS_BASE, a);
5056         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
5057 #else
5058         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
5059         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
5060 #endif
5061
5062         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
5063         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
5064         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
5065         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
5066         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
5067
5068         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
5069                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
5070
5071         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
5072                 u32 index = vmx_msr_index[i];
5073                 u32 data_low, data_high;
5074                 int j = vmx->nmsrs;
5075
5076                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
5077                         continue;
5078                 if (wrmsr_safe(index, data_low, data_high) < 0)
5079                         continue;
5080                 vmx->guest_msrs[j].index = i;
5081                 vmx->guest_msrs[j].data = 0;
5082                 vmx->guest_msrs[j].mask = -1ull;
5083                 ++vmx->nmsrs;
5084         }
5085
5086
5087         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
5088
5089         /* 22.2.1, 20.8.1 */
5090         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
5091
5092         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
5093         set_cr4_guest_host_mask(vmx);
5094
5095         if (vmx_xsaves_supported())
5096                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
5097
5098         return 0;
5099 }
5100
5101 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
5102 {
5103         struct vcpu_vmx *vmx = to_vmx(vcpu);
5104         struct msr_data apic_base_msr;
5105         u64 cr0;
5106
5107         vmx->rmode.vm86_active = 0;
5108
5109         vmx->soft_vnmi_blocked = 0;
5110
5111         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
5112         kvm_set_cr8(vcpu, 0);
5113
5114         if (!init_event) {
5115                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
5116                                      MSR_IA32_APICBASE_ENABLE;
5117                 if (kvm_vcpu_is_reset_bsp(vcpu))
5118                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
5119                 apic_base_msr.host_initiated = true;
5120                 kvm_set_apic_base(vcpu, &apic_base_msr);
5121         }
5122
5123         vmx_segment_cache_clear(vmx);
5124
5125         seg_setup(VCPU_SREG_CS);
5126         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
5127         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
5128
5129         seg_setup(VCPU_SREG_DS);
5130         seg_setup(VCPU_SREG_ES);
5131         seg_setup(VCPU_SREG_FS);
5132         seg_setup(VCPU_SREG_GS);
5133         seg_setup(VCPU_SREG_SS);
5134
5135         vmcs_write16(GUEST_TR_SELECTOR, 0);
5136         vmcs_writel(GUEST_TR_BASE, 0);
5137         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5138         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5139
5140         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5141         vmcs_writel(GUEST_LDTR_BASE, 0);
5142         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5143         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5144
5145         if (!init_event) {
5146                 vmcs_write32(GUEST_SYSENTER_CS, 0);
5147                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5148                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5149                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5150         }
5151
5152         vmcs_writel(GUEST_RFLAGS, 0x02);
5153         kvm_rip_write(vcpu, 0xfff0);
5154
5155         vmcs_writel(GUEST_GDTR_BASE, 0);
5156         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5157
5158         vmcs_writel(GUEST_IDTR_BASE, 0);
5159         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5160
5161         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
5162         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
5163         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
5164
5165         setup_msrs(vmx);
5166
5167         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
5168
5169         if (cpu_has_vmx_tpr_shadow() && !init_event) {
5170                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
5171                 if (cpu_need_tpr_shadow(vcpu))
5172                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
5173                                      __pa(vcpu->arch.apic->regs));
5174                 vmcs_write32(TPR_THRESHOLD, 0);
5175         }
5176
5177         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
5178
5179         if (kvm_vcpu_apicv_active(vcpu))
5180                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5181
5182         if (vmx->vpid != 0)
5183                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5184
5185         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5186         vmx->vcpu.arch.cr0 = cr0;
5187         vmx_set_cr0(vcpu, cr0); /* enter rmode */
5188         vmx_set_cr4(vcpu, 0);
5189         vmx_set_efer(vcpu, 0);
5190         vmx_fpu_activate(vcpu);
5191         update_exception_bitmap(vcpu);
5192
5193         vpid_sync_context(vmx->vpid);
5194 }
5195
5196 /*
5197  * In nested virtualization, check if L1 asked to exit on external interrupts.
5198  * For most existing hypervisors, this will always return true.
5199  */
5200 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5201 {
5202         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5203                 PIN_BASED_EXT_INTR_MASK;
5204 }
5205
5206 /*
5207  * In nested virtualization, check if L1 has set
5208  * VM_EXIT_ACK_INTR_ON_EXIT
5209  */
5210 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5211 {
5212         return get_vmcs12(vcpu)->vm_exit_controls &
5213                 VM_EXIT_ACK_INTR_ON_EXIT;
5214 }
5215
5216 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5217 {
5218         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5219                 PIN_BASED_NMI_EXITING;
5220 }
5221
5222 static void enable_irq_window(struct kvm_vcpu *vcpu)
5223 {
5224         u32 cpu_based_vm_exec_control;
5225
5226         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5227         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
5228         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5229 }
5230
5231 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5232 {
5233         u32 cpu_based_vm_exec_control;
5234
5235         if (!cpu_has_virtual_nmis() ||
5236             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5237                 enable_irq_window(vcpu);
5238                 return;
5239         }
5240
5241         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5242         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
5243         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5244 }
5245
5246 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5247 {
5248         struct vcpu_vmx *vmx = to_vmx(vcpu);
5249         uint32_t intr;
5250         int irq = vcpu->arch.interrupt.nr;
5251
5252         trace_kvm_inj_virq(irq);
5253
5254         ++vcpu->stat.irq_injections;
5255         if (vmx->rmode.vm86_active) {
5256                 int inc_eip = 0;
5257                 if (vcpu->arch.interrupt.soft)
5258                         inc_eip = vcpu->arch.event_exit_inst_len;
5259                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5260                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5261                 return;
5262         }
5263         intr = irq | INTR_INFO_VALID_MASK;
5264         if (vcpu->arch.interrupt.soft) {
5265                 intr |= INTR_TYPE_SOFT_INTR;
5266                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5267                              vmx->vcpu.arch.event_exit_inst_len);
5268         } else
5269                 intr |= INTR_TYPE_EXT_INTR;
5270         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5271 }
5272
5273 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5274 {
5275         struct vcpu_vmx *vmx = to_vmx(vcpu);
5276
5277         if (is_guest_mode(vcpu))
5278                 return;
5279
5280         if (!cpu_has_virtual_nmis()) {
5281                 /*
5282                  * Tracking the NMI-blocked state in software is built upon
5283                  * finding the next open IRQ window. This, in turn, depends on
5284                  * well-behaving guests: They have to keep IRQs disabled at
5285                  * least as long as the NMI handler runs. Otherwise we may
5286                  * cause NMI nesting, maybe breaking the guest. But as this is
5287                  * highly unlikely, we can live with the residual risk.
5288                  */
5289                 vmx->soft_vnmi_blocked = 1;
5290                 vmx->vnmi_blocked_time = 0;
5291         }
5292
5293         ++vcpu->stat.nmi_injections;
5294         vmx->nmi_known_unmasked = false;
5295         if (vmx->rmode.vm86_active) {
5296                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5297                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5298                 return;
5299         }
5300         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5301                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5302 }
5303
5304 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5305 {
5306         if (!cpu_has_virtual_nmis())
5307                 return to_vmx(vcpu)->soft_vnmi_blocked;
5308         if (to_vmx(vcpu)->nmi_known_unmasked)
5309                 return false;
5310         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5311 }
5312
5313 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5314 {
5315         struct vcpu_vmx *vmx = to_vmx(vcpu);
5316
5317         if (!cpu_has_virtual_nmis()) {
5318                 if (vmx->soft_vnmi_blocked != masked) {
5319                         vmx->soft_vnmi_blocked = masked;
5320                         vmx->vnmi_blocked_time = 0;
5321                 }
5322         } else {
5323                 vmx->nmi_known_unmasked = !masked;
5324                 if (masked)
5325                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5326                                       GUEST_INTR_STATE_NMI);
5327                 else
5328                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5329                                         GUEST_INTR_STATE_NMI);
5330         }
5331 }
5332
5333 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5334 {
5335         if (to_vmx(vcpu)->nested.nested_run_pending)
5336                 return 0;
5337
5338         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
5339                 return 0;
5340
5341         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5342                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5343                    | GUEST_INTR_STATE_NMI));
5344 }
5345
5346 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5347 {
5348         return (!to_vmx(vcpu)->nested.nested_run_pending &&
5349                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5350                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5351                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5352 }
5353
5354 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5355 {
5356         int ret;
5357
5358         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5359                                     PAGE_SIZE * 3);
5360         if (ret)
5361                 return ret;
5362         kvm->arch.tss_addr = addr;
5363         return init_rmode_tss(kvm);
5364 }
5365
5366 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5367 {
5368         switch (vec) {
5369         case BP_VECTOR:
5370                 /*
5371                  * Update instruction length as we may reinject the exception
5372                  * from user space while in guest debugging mode.
5373                  */
5374                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5375                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5376                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5377                         return false;
5378                 /* fall through */
5379         case DB_VECTOR:
5380                 if (vcpu->guest_debug &
5381                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5382                         return false;
5383                 /* fall through */
5384         case DE_VECTOR:
5385         case OF_VECTOR:
5386         case BR_VECTOR:
5387         case UD_VECTOR:
5388         case DF_VECTOR:
5389         case SS_VECTOR:
5390         case GP_VECTOR:
5391         case MF_VECTOR:
5392                 return true;
5393         break;
5394         }
5395         return false;
5396 }
5397
5398 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5399                                   int vec, u32 err_code)
5400 {
5401         /*
5402          * Instruction with address size override prefix opcode 0x67
5403          * Cause the #SS fault with 0 error code in VM86 mode.
5404          */
5405         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5406                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5407                         if (vcpu->arch.halt_request) {
5408                                 vcpu->arch.halt_request = 0;
5409                                 return kvm_vcpu_halt(vcpu);
5410                         }
5411                         return 1;
5412                 }
5413                 return 0;
5414         }
5415
5416         /*
5417          * Forward all other exceptions that are valid in real mode.
5418          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5419          *        the required debugging infrastructure rework.
5420          */
5421         kvm_queue_exception(vcpu, vec);
5422         return 1;
5423 }
5424
5425 /*
5426  * Trigger machine check on the host. We assume all the MSRs are already set up
5427  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5428  * We pass a fake environment to the machine check handler because we want
5429  * the guest to be always treated like user space, no matter what context
5430  * it used internally.
5431  */
5432 static void kvm_machine_check(void)
5433 {
5434 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5435         struct pt_regs regs = {
5436                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5437                 .flags = X86_EFLAGS_IF,
5438         };
5439
5440         do_machine_check(&regs, 0);
5441 #endif
5442 }
5443
5444 static int handle_machine_check(struct kvm_vcpu *vcpu)
5445 {
5446         /* already handled by vcpu_run */
5447         return 1;
5448 }
5449
5450 static int handle_exception(struct kvm_vcpu *vcpu)
5451 {
5452         struct vcpu_vmx *vmx = to_vmx(vcpu);
5453         struct kvm_run *kvm_run = vcpu->run;
5454         u32 intr_info, ex_no, error_code;
5455         unsigned long cr2, rip, dr6;
5456         u32 vect_info;
5457         enum emulation_result er;
5458
5459         vect_info = vmx->idt_vectoring_info;
5460         intr_info = vmx->exit_intr_info;
5461
5462         if (is_machine_check(intr_info))
5463                 return handle_machine_check(vcpu);
5464
5465         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
5466                 return 1;  /* already handled by vmx_vcpu_run() */
5467
5468         if (is_no_device(intr_info)) {
5469                 vmx_fpu_activate(vcpu);
5470                 return 1;
5471         }
5472
5473         if (is_invalid_opcode(intr_info)) {
5474                 if (is_guest_mode(vcpu)) {
5475                         kvm_queue_exception(vcpu, UD_VECTOR);
5476                         return 1;
5477                 }
5478                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5479                 if (er != EMULATE_DONE)
5480                         kvm_queue_exception(vcpu, UD_VECTOR);
5481                 return 1;
5482         }
5483
5484         error_code = 0;
5485         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5486                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5487
5488         /*
5489          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5490          * MMIO, it is better to report an internal error.
5491          * See the comments in vmx_handle_exit.
5492          */
5493         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5494             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5495                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5496                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5497                 vcpu->run->internal.ndata = 3;
5498                 vcpu->run->internal.data[0] = vect_info;
5499                 vcpu->run->internal.data[1] = intr_info;
5500                 vcpu->run->internal.data[2] = error_code;
5501                 return 0;
5502         }
5503
5504         if (is_page_fault(intr_info)) {
5505                 /* EPT won't cause page fault directly */
5506                 BUG_ON(enable_ept);
5507                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5508                 trace_kvm_page_fault(cr2, error_code);
5509
5510                 if (kvm_event_needs_reinjection(vcpu))
5511                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
5512                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5513         }
5514
5515         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5516
5517         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5518                 return handle_rmode_exception(vcpu, ex_no, error_code);
5519
5520         switch (ex_no) {
5521         case AC_VECTOR:
5522                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5523                 return 1;
5524         case DB_VECTOR:
5525                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5526                 if (!(vcpu->guest_debug &
5527                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5528                         vcpu->arch.dr6 &= ~15;
5529                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5530                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5531                                 skip_emulated_instruction(vcpu);
5532
5533                         kvm_queue_exception(vcpu, DB_VECTOR);
5534                         return 1;
5535                 }
5536                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5537                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5538                 /* fall through */
5539         case BP_VECTOR:
5540                 /*
5541                  * Update instruction length as we may reinject #BP from
5542                  * user space while in guest debugging mode. Reading it for
5543                  * #DB as well causes no harm, it is not used in that case.
5544                  */
5545                 vmx->vcpu.arch.event_exit_inst_len =
5546                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5547                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5548                 rip = kvm_rip_read(vcpu);
5549                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5550                 kvm_run->debug.arch.exception = ex_no;
5551                 break;
5552         default:
5553                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5554                 kvm_run->ex.exception = ex_no;
5555                 kvm_run->ex.error_code = error_code;
5556                 break;
5557         }
5558         return 0;
5559 }
5560
5561 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5562 {
5563         ++vcpu->stat.irq_exits;
5564         return 1;
5565 }
5566
5567 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5568 {
5569         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5570         return 0;
5571 }
5572
5573 static int handle_io(struct kvm_vcpu *vcpu)
5574 {
5575         unsigned long exit_qualification;
5576         int size, in, string;
5577         unsigned port;
5578
5579         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5580         string = (exit_qualification & 16) != 0;
5581         in = (exit_qualification & 8) != 0;
5582
5583         ++vcpu->stat.io_exits;
5584
5585         if (string || in)
5586                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5587
5588         port = exit_qualification >> 16;
5589         size = (exit_qualification & 7) + 1;
5590         skip_emulated_instruction(vcpu);
5591
5592         return kvm_fast_pio_out(vcpu, size, port);
5593 }
5594
5595 static void
5596 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5597 {
5598         /*
5599          * Patch in the VMCALL instruction:
5600          */
5601         hypercall[0] = 0x0f;
5602         hypercall[1] = 0x01;
5603         hypercall[2] = 0xc1;
5604 }
5605
5606 static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5607 {
5608         unsigned long always_on = VMXON_CR0_ALWAYSON;
5609         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5610
5611         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
5612                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5613             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5614                 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5615         return (val & always_on) == always_on;
5616 }
5617
5618 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5619 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5620 {
5621         if (is_guest_mode(vcpu)) {
5622                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5623                 unsigned long orig_val = val;
5624
5625                 /*
5626                  * We get here when L2 changed cr0 in a way that did not change
5627                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5628                  * but did change L0 shadowed bits. So we first calculate the
5629                  * effective cr0 value that L1 would like to write into the
5630                  * hardware. It consists of the L2-owned bits from the new
5631                  * value combined with the L1-owned bits from L1's guest_cr0.
5632                  */
5633                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5634                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5635
5636                 if (!nested_cr0_valid(vcpu, val))
5637                         return 1;
5638
5639                 if (kvm_set_cr0(vcpu, val))
5640                         return 1;
5641                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5642                 return 0;
5643         } else {
5644                 if (to_vmx(vcpu)->nested.vmxon &&
5645                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5646                         return 1;
5647                 return kvm_set_cr0(vcpu, val);
5648         }
5649 }
5650
5651 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5652 {
5653         if (is_guest_mode(vcpu)) {
5654                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5655                 unsigned long orig_val = val;
5656
5657                 /* analogously to handle_set_cr0 */
5658                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5659                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5660                 if (kvm_set_cr4(vcpu, val))
5661                         return 1;
5662                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5663                 return 0;
5664         } else
5665                 return kvm_set_cr4(vcpu, val);
5666 }
5667
5668 /* called to set cr0 as appropriate for clts instruction exit. */
5669 static void handle_clts(struct kvm_vcpu *vcpu)
5670 {
5671         if (is_guest_mode(vcpu)) {
5672                 /*
5673                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5674                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5675                  * just pretend it's off (also in arch.cr0 for fpu_activate).
5676                  */
5677                 vmcs_writel(CR0_READ_SHADOW,
5678                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5679                 vcpu->arch.cr0 &= ~X86_CR0_TS;
5680         } else
5681                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5682 }
5683
5684 static int handle_cr(struct kvm_vcpu *vcpu)
5685 {
5686         unsigned long exit_qualification, val;
5687         int cr;
5688         int reg;
5689         int err;
5690
5691         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5692         cr = exit_qualification & 15;
5693         reg = (exit_qualification >> 8) & 15;
5694         switch ((exit_qualification >> 4) & 3) {
5695         case 0: /* mov to cr */
5696                 val = kvm_register_readl(vcpu, reg);
5697                 trace_kvm_cr_write(cr, val);
5698                 switch (cr) {
5699                 case 0:
5700                         err = handle_set_cr0(vcpu, val);
5701                         kvm_complete_insn_gp(vcpu, err);
5702                         return 1;
5703                 case 3:
5704                         err = kvm_set_cr3(vcpu, val);
5705                         kvm_complete_insn_gp(vcpu, err);
5706                         return 1;
5707                 case 4:
5708                         err = handle_set_cr4(vcpu, val);
5709                         kvm_complete_insn_gp(vcpu, err);
5710                         return 1;
5711                 case 8: {
5712                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5713                                 u8 cr8 = (u8)val;
5714                                 err = kvm_set_cr8(vcpu, cr8);
5715                                 kvm_complete_insn_gp(vcpu, err);
5716                                 if (lapic_in_kernel(vcpu))
5717                                         return 1;
5718                                 if (cr8_prev <= cr8)
5719                                         return 1;
5720                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5721                                 return 0;
5722                         }
5723                 }
5724                 break;
5725         case 2: /* clts */
5726                 handle_clts(vcpu);
5727                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5728                 skip_emulated_instruction(vcpu);
5729                 vmx_fpu_activate(vcpu);
5730                 return 1;
5731         case 1: /*mov from cr*/
5732                 switch (cr) {
5733                 case 3:
5734                         val = kvm_read_cr3(vcpu);
5735                         kvm_register_write(vcpu, reg, val);
5736                         trace_kvm_cr_read(cr, val);
5737                         skip_emulated_instruction(vcpu);
5738                         return 1;
5739                 case 8:
5740                         val = kvm_get_cr8(vcpu);
5741                         kvm_register_write(vcpu, reg, val);
5742                         trace_kvm_cr_read(cr, val);
5743                         skip_emulated_instruction(vcpu);
5744                         return 1;
5745                 }
5746                 break;
5747         case 3: /* lmsw */
5748                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5749                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5750                 kvm_lmsw(vcpu, val);
5751
5752                 skip_emulated_instruction(vcpu);
5753                 return 1;
5754         default:
5755                 break;
5756         }
5757         vcpu->run->exit_reason = 0;
5758         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5759                (int)(exit_qualification >> 4) & 3, cr);
5760         return 0;
5761 }
5762
5763 static int handle_dr(struct kvm_vcpu *vcpu)
5764 {
5765         unsigned long exit_qualification;
5766         int dr, dr7, reg;
5767
5768         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5769         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5770
5771         /* First, if DR does not exist, trigger UD */
5772         if (!kvm_require_dr(vcpu, dr))
5773                 return 1;
5774
5775         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5776         if (!kvm_require_cpl(vcpu, 0))
5777                 return 1;
5778         dr7 = vmcs_readl(GUEST_DR7);
5779         if (dr7 & DR7_GD) {
5780                 /*
5781                  * As the vm-exit takes precedence over the debug trap, we
5782                  * need to emulate the latter, either for the host or the
5783                  * guest debugging itself.
5784                  */
5785                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5786                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5787                         vcpu->run->debug.arch.dr7 = dr7;
5788                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5789                         vcpu->run->debug.arch.exception = DB_VECTOR;
5790                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5791                         return 0;
5792                 } else {
5793                         vcpu->arch.dr6 &= ~15;
5794                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5795                         kvm_queue_exception(vcpu, DB_VECTOR);
5796                         return 1;
5797                 }
5798         }
5799
5800         if (vcpu->guest_debug == 0) {
5801                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
5802                                 CPU_BASED_MOV_DR_EXITING);
5803
5804                 /*
5805                  * No more DR vmexits; force a reload of the debug registers
5806                  * and reenter on this instruction.  The next vmexit will
5807                  * retrieve the full state of the debug registers.
5808                  */
5809                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5810                 return 1;
5811         }
5812
5813         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5814         if (exit_qualification & TYPE_MOV_FROM_DR) {
5815                 unsigned long val;
5816
5817                 if (kvm_get_dr(vcpu, dr, &val))
5818                         return 1;
5819                 kvm_register_write(vcpu, reg, val);
5820         } else
5821                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5822                         return 1;
5823
5824         skip_emulated_instruction(vcpu);
5825         return 1;
5826 }
5827
5828 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5829 {
5830         return vcpu->arch.dr6;
5831 }
5832
5833 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5834 {
5835 }
5836
5837 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5838 {
5839         get_debugreg(vcpu->arch.db[0], 0);
5840         get_debugreg(vcpu->arch.db[1], 1);
5841         get_debugreg(vcpu->arch.db[2], 2);
5842         get_debugreg(vcpu->arch.db[3], 3);
5843         get_debugreg(vcpu->arch.dr6, 6);
5844         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5845
5846         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5847         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
5848 }
5849
5850 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5851 {
5852         vmcs_writel(GUEST_DR7, val);
5853 }
5854
5855 static int handle_cpuid(struct kvm_vcpu *vcpu)
5856 {
5857         kvm_emulate_cpuid(vcpu);
5858         return 1;
5859 }
5860
5861 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5862 {
5863         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5864         struct msr_data msr_info;
5865
5866         msr_info.index = ecx;
5867         msr_info.host_initiated = false;
5868         if (vmx_get_msr(vcpu, &msr_info)) {
5869                 trace_kvm_msr_read_ex(ecx);
5870                 kvm_inject_gp(vcpu, 0);
5871                 return 1;
5872         }
5873
5874         trace_kvm_msr_read(ecx, msr_info.data);
5875
5876         /* FIXME: handling of bits 32:63 of rax, rdx */
5877         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
5878         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
5879         skip_emulated_instruction(vcpu);
5880         return 1;
5881 }
5882
5883 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5884 {
5885         struct msr_data msr;
5886         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5887         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5888                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5889
5890         msr.data = data;
5891         msr.index = ecx;
5892         msr.host_initiated = false;
5893         if (kvm_set_msr(vcpu, &msr) != 0) {
5894                 trace_kvm_msr_write_ex(ecx, data);
5895                 kvm_inject_gp(vcpu, 0);
5896                 return 1;
5897         }
5898
5899         trace_kvm_msr_write(ecx, data);
5900         skip_emulated_instruction(vcpu);
5901         return 1;
5902 }
5903
5904 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5905 {
5906         kvm_make_request(KVM_REQ_EVENT, vcpu);
5907         return 1;
5908 }
5909
5910 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5911 {
5912         u32 cpu_based_vm_exec_control;
5913
5914         /* clear pending irq */
5915         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5916         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5917         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5918
5919         kvm_make_request(KVM_REQ_EVENT, vcpu);
5920
5921         ++vcpu->stat.irq_window_exits;
5922         return 1;
5923 }
5924
5925 static int handle_halt(struct kvm_vcpu *vcpu)
5926 {
5927         return kvm_emulate_halt(vcpu);
5928 }
5929
5930 static int handle_vmcall(struct kvm_vcpu *vcpu)
5931 {
5932         return kvm_emulate_hypercall(vcpu);
5933 }
5934
5935 static int handle_invd(struct kvm_vcpu *vcpu)
5936 {
5937         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5938 }
5939
5940 static int handle_invlpg(struct kvm_vcpu *vcpu)
5941 {
5942         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5943
5944         kvm_mmu_invlpg(vcpu, exit_qualification);
5945         skip_emulated_instruction(vcpu);
5946         return 1;
5947 }
5948
5949 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5950 {
5951         int err;
5952
5953         err = kvm_rdpmc(vcpu);
5954         kvm_complete_insn_gp(vcpu, err);
5955
5956         return 1;
5957 }
5958
5959 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5960 {
5961         kvm_emulate_wbinvd(vcpu);
5962         return 1;
5963 }
5964
5965 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5966 {
5967         u64 new_bv = kvm_read_edx_eax(vcpu);
5968         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5969
5970         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5971                 skip_emulated_instruction(vcpu);
5972         return 1;
5973 }
5974
5975 static int handle_xsaves(struct kvm_vcpu *vcpu)
5976 {
5977         skip_emulated_instruction(vcpu);
5978         WARN(1, "this should never happen\n");
5979         return 1;
5980 }
5981
5982 static int handle_xrstors(struct kvm_vcpu *vcpu)
5983 {
5984         skip_emulated_instruction(vcpu);
5985         WARN(1, "this should never happen\n");
5986         return 1;
5987 }
5988
5989 static int handle_apic_access(struct kvm_vcpu *vcpu)
5990 {
5991         if (likely(fasteoi)) {
5992                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5993                 int access_type, offset;
5994
5995                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5996                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5997                 /*
5998                  * Sane guest uses MOV to write EOI, with written value
5999                  * not cared. So make a short-circuit here by avoiding
6000                  * heavy instruction emulation.
6001                  */
6002                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
6003                     (offset == APIC_EOI)) {
6004                         kvm_lapic_set_eoi(vcpu);
6005                         skip_emulated_instruction(vcpu);
6006                         return 1;
6007                 }
6008         }
6009         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6010 }
6011
6012 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
6013 {
6014         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6015         int vector = exit_qualification & 0xff;
6016
6017         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6018         kvm_apic_set_eoi_accelerated(vcpu, vector);
6019         return 1;
6020 }
6021
6022 static int handle_apic_write(struct kvm_vcpu *vcpu)
6023 {
6024         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6025         u32 offset = exit_qualification & 0xfff;
6026
6027         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6028         kvm_apic_write_nodecode(vcpu, offset);
6029         return 1;
6030 }
6031
6032 static int handle_task_switch(struct kvm_vcpu *vcpu)
6033 {
6034         struct vcpu_vmx *vmx = to_vmx(vcpu);
6035         unsigned long exit_qualification;
6036         bool has_error_code = false;
6037         u32 error_code = 0;
6038         u16 tss_selector;
6039         int reason, type, idt_v, idt_index;
6040
6041         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
6042         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
6043         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
6044
6045         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6046
6047         reason = (u32)exit_qualification >> 30;
6048         if (reason == TASK_SWITCH_GATE && idt_v) {
6049                 switch (type) {
6050                 case INTR_TYPE_NMI_INTR:
6051                         vcpu->arch.nmi_injected = false;
6052                         vmx_set_nmi_mask(vcpu, true);
6053                         break;
6054                 case INTR_TYPE_EXT_INTR:
6055                 case INTR_TYPE_SOFT_INTR:
6056                         kvm_clear_interrupt_queue(vcpu);
6057                         break;
6058                 case INTR_TYPE_HARD_EXCEPTION:
6059                         if (vmx->idt_vectoring_info &
6060                             VECTORING_INFO_DELIVER_CODE_MASK) {
6061                                 has_error_code = true;
6062                                 error_code =
6063                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
6064                         }
6065                         /* fall through */
6066                 case INTR_TYPE_SOFT_EXCEPTION:
6067                         kvm_clear_exception_queue(vcpu);
6068                         break;
6069                 default:
6070                         break;
6071                 }
6072         }
6073         tss_selector = exit_qualification;
6074
6075         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
6076                        type != INTR_TYPE_EXT_INTR &&
6077                        type != INTR_TYPE_NMI_INTR))
6078                 skip_emulated_instruction(vcpu);
6079
6080         if (kvm_task_switch(vcpu, tss_selector,
6081                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
6082                             has_error_code, error_code) == EMULATE_FAIL) {
6083                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6084                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6085                 vcpu->run->internal.ndata = 0;
6086                 return 0;
6087         }
6088
6089         /*
6090          * TODO: What about debug traps on tss switch?
6091          *       Are we supposed to inject them and update dr6?
6092          */
6093
6094         return 1;
6095 }
6096
6097 static int handle_ept_violation(struct kvm_vcpu *vcpu)
6098 {
6099         unsigned long exit_qualification;
6100         gpa_t gpa;
6101         u32 error_code;
6102         int gla_validity;
6103
6104         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6105
6106         gla_validity = (exit_qualification >> 7) & 0x3;
6107         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
6108                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
6109                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
6110                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
6111                         vmcs_readl(GUEST_LINEAR_ADDRESS));
6112                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
6113                         (long unsigned int)exit_qualification);
6114                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6115                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
6116                 return 0;
6117         }
6118
6119         /*
6120          * EPT violation happened while executing iret from NMI,
6121          * "blocked by NMI" bit has to be set before next VM entry.
6122          * There are errata that may cause this bit to not be set:
6123          * AAK134, BY25.
6124          */
6125         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
6126                         cpu_has_virtual_nmis() &&
6127                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
6128                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
6129
6130         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6131         trace_kvm_page_fault(gpa, exit_qualification);
6132
6133         /* it is a read fault? */
6134         error_code = (exit_qualification << 2) & PFERR_USER_MASK;
6135         /* it is a write fault? */
6136         error_code |= exit_qualification & PFERR_WRITE_MASK;
6137         /* It is a fetch fault? */
6138         error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
6139         /* ept page table is present? */
6140         error_code |= (exit_qualification & 0x38) != 0;
6141
6142         vcpu->arch.exit_qualification = exit_qualification;
6143
6144         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
6145 }
6146
6147 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
6148 {
6149         int ret;
6150         gpa_t gpa;
6151
6152         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6153         if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
6154                 skip_emulated_instruction(vcpu);
6155                 trace_kvm_fast_mmio(gpa);
6156                 return 1;
6157         }
6158
6159         ret = handle_mmio_page_fault(vcpu, gpa, true);
6160         if (likely(ret == RET_MMIO_PF_EMULATE))
6161                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
6162                                               EMULATE_DONE;
6163
6164         if (unlikely(ret == RET_MMIO_PF_INVALID))
6165                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
6166
6167         if (unlikely(ret == RET_MMIO_PF_RETRY))
6168                 return 1;
6169
6170         /* It is the real ept misconfig */
6171         WARN_ON(1);
6172
6173         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6174         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
6175
6176         return 0;
6177 }
6178
6179 static int handle_nmi_window(struct kvm_vcpu *vcpu)
6180 {
6181         u32 cpu_based_vm_exec_control;
6182
6183         /* clear pending NMI */
6184         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6185         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6186         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
6187         ++vcpu->stat.nmi_window_exits;
6188         kvm_make_request(KVM_REQ_EVENT, vcpu);
6189
6190         return 1;
6191 }
6192
6193 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6194 {
6195         struct vcpu_vmx *vmx = to_vmx(vcpu);
6196         enum emulation_result err = EMULATE_DONE;
6197         int ret = 1;
6198         u32 cpu_exec_ctrl;
6199         bool intr_window_requested;
6200         unsigned count = 130;
6201
6202         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6203         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6204
6205         while (vmx->emulation_required && count-- != 0) {
6206                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6207                         return handle_interrupt_window(&vmx->vcpu);
6208
6209                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
6210                         return 1;
6211
6212                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
6213
6214                 if (err == EMULATE_USER_EXIT) {
6215                         ++vcpu->stat.mmio_exits;
6216                         ret = 0;
6217                         goto out;
6218                 }
6219
6220                 if (err != EMULATE_DONE) {
6221                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6222                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6223                         vcpu->run->internal.ndata = 0;
6224                         return 0;
6225                 }
6226
6227                 if (vcpu->arch.halt_request) {
6228                         vcpu->arch.halt_request = 0;
6229                         ret = kvm_vcpu_halt(vcpu);
6230                         goto out;
6231                 }
6232
6233                 if (signal_pending(current))
6234                         goto out;
6235                 if (need_resched())
6236                         schedule();
6237         }
6238
6239 out:
6240         return ret;
6241 }
6242
6243 static int __grow_ple_window(int val)
6244 {
6245         if (ple_window_grow < 1)
6246                 return ple_window;
6247
6248         val = min(val, ple_window_actual_max);
6249
6250         if (ple_window_grow < ple_window)
6251                 val *= ple_window_grow;
6252         else
6253                 val += ple_window_grow;
6254
6255         return val;
6256 }
6257
6258 static int __shrink_ple_window(int val, int modifier, int minimum)
6259 {
6260         if (modifier < 1)
6261                 return ple_window;
6262
6263         if (modifier < ple_window)
6264                 val /= modifier;
6265         else
6266                 val -= modifier;
6267
6268         return max(val, minimum);
6269 }
6270
6271 static void grow_ple_window(struct kvm_vcpu *vcpu)
6272 {
6273         struct vcpu_vmx *vmx = to_vmx(vcpu);
6274         int old = vmx->ple_window;
6275
6276         vmx->ple_window = __grow_ple_window(old);
6277
6278         if (vmx->ple_window != old)
6279                 vmx->ple_window_dirty = true;
6280
6281         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6282 }
6283
6284 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6285 {
6286         struct vcpu_vmx *vmx = to_vmx(vcpu);
6287         int old = vmx->ple_window;
6288
6289         vmx->ple_window = __shrink_ple_window(old,
6290                                               ple_window_shrink, ple_window);
6291
6292         if (vmx->ple_window != old)
6293                 vmx->ple_window_dirty = true;
6294
6295         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6296 }
6297
6298 /*
6299  * ple_window_actual_max is computed to be one grow_ple_window() below
6300  * ple_window_max. (See __grow_ple_window for the reason.)
6301  * This prevents overflows, because ple_window_max is int.
6302  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6303  * this process.
6304  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6305  */
6306 static void update_ple_window_actual_max(void)
6307 {
6308         ple_window_actual_max =
6309                         __shrink_ple_window(max(ple_window_max, ple_window),
6310                                             ple_window_grow, INT_MIN);
6311 }
6312
6313 /*
6314  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6315  */
6316 static void wakeup_handler(void)
6317 {
6318         struct kvm_vcpu *vcpu;
6319         int cpu = smp_processor_id();
6320
6321         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6322         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6323                         blocked_vcpu_list) {
6324                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6325
6326                 if (pi_test_on(pi_desc) == 1)
6327                         kvm_vcpu_kick(vcpu);
6328         }
6329         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6330 }
6331
6332 static __init int hardware_setup(void)
6333 {
6334         int r = -ENOMEM, i, msr;
6335
6336         rdmsrl_safe(MSR_EFER, &host_efer);
6337
6338         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6339                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6340
6341         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6342         if (!vmx_io_bitmap_a)
6343                 return r;
6344
6345         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6346         if (!vmx_io_bitmap_b)
6347                 goto out;
6348
6349         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6350         if (!vmx_msr_bitmap_legacy)
6351                 goto out1;
6352
6353         vmx_msr_bitmap_legacy_x2apic =
6354                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6355         if (!vmx_msr_bitmap_legacy_x2apic)
6356                 goto out2;
6357
6358         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6359         if (!vmx_msr_bitmap_longmode)
6360                 goto out3;
6361
6362         vmx_msr_bitmap_longmode_x2apic =
6363                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6364         if (!vmx_msr_bitmap_longmode_x2apic)
6365                 goto out4;
6366
6367         if (nested) {
6368                 vmx_msr_bitmap_nested =
6369                         (unsigned long *)__get_free_page(GFP_KERNEL);
6370                 if (!vmx_msr_bitmap_nested)
6371                         goto out5;
6372         }
6373
6374         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6375         if (!vmx_vmread_bitmap)
6376                 goto out6;
6377
6378         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6379         if (!vmx_vmwrite_bitmap)
6380                 goto out7;
6381
6382         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6383         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6384
6385         /*
6386          * Allow direct access to the PC debug port (it is often used for I/O
6387          * delays, but the vmexits simply slow things down).
6388          */
6389         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6390         clear_bit(0x80, vmx_io_bitmap_a);
6391
6392         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6393
6394         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6395         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6396         if (nested)
6397                 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
6398
6399         if (setup_vmcs_config(&vmcs_config) < 0) {
6400                 r = -EIO;
6401                 goto out8;
6402         }
6403
6404         if (boot_cpu_has(X86_FEATURE_NX))
6405                 kvm_enable_efer_bits(EFER_NX);
6406
6407         if (!cpu_has_vmx_vpid())
6408                 enable_vpid = 0;
6409         if (!cpu_has_vmx_shadow_vmcs())
6410                 enable_shadow_vmcs = 0;
6411         if (enable_shadow_vmcs)
6412                 init_vmcs_shadow_fields();
6413
6414         if (!cpu_has_vmx_ept() ||
6415             !cpu_has_vmx_ept_4levels()) {
6416                 enable_ept = 0;
6417                 enable_unrestricted_guest = 0;
6418                 enable_ept_ad_bits = 0;
6419         }
6420
6421         if (!cpu_has_vmx_ept_ad_bits())
6422                 enable_ept_ad_bits = 0;
6423
6424         if (!cpu_has_vmx_unrestricted_guest())
6425                 enable_unrestricted_guest = 0;
6426
6427         if (!cpu_has_vmx_flexpriority())
6428                 flexpriority_enabled = 0;
6429
6430         /*
6431          * set_apic_access_page_addr() is used to reload apic access
6432          * page upon invalidation.  No need to do anything if not
6433          * using the APIC_ACCESS_ADDR VMCS field.
6434          */
6435         if (!flexpriority_enabled)
6436                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6437
6438         if (!cpu_has_vmx_tpr_shadow())
6439                 kvm_x86_ops->update_cr8_intercept = NULL;
6440
6441         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6442                 kvm_disable_largepages();
6443
6444         if (!cpu_has_vmx_ple())
6445                 ple_gap = 0;
6446
6447         if (!cpu_has_vmx_apicv())
6448                 enable_apicv = 0;
6449
6450         if (cpu_has_vmx_tsc_scaling()) {
6451                 kvm_has_tsc_control = true;
6452                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6453                 kvm_tsc_scaling_ratio_frac_bits = 48;
6454         }
6455
6456         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6457         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6458         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6459         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6460         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6461         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6462         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6463
6464         memcpy(vmx_msr_bitmap_legacy_x2apic,
6465                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6466         memcpy(vmx_msr_bitmap_longmode_x2apic,
6467                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6468
6469         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6470
6471         for (msr = 0x800; msr <= 0x8ff; msr++)
6472                 vmx_disable_intercept_msr_read_x2apic(msr);
6473
6474         /* TMCCT */
6475         vmx_enable_intercept_msr_read_x2apic(0x839);
6476         /* TPR */
6477         vmx_disable_intercept_msr_write_x2apic(0x808);
6478         /* EOI */
6479         vmx_disable_intercept_msr_write_x2apic(0x80b);
6480         /* SELF-IPI */
6481         vmx_disable_intercept_msr_write_x2apic(0x83f);
6482
6483         if (enable_ept) {
6484                 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
6485                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6486                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6487                         0ull, VMX_EPT_EXECUTABLE_MASK,
6488                         cpu_has_vmx_ept_execute_only() ?
6489                                       0ull : VMX_EPT_READABLE_MASK);
6490                 ept_set_mmio_spte_mask();
6491                 kvm_enable_tdp();
6492         } else
6493                 kvm_disable_tdp();
6494
6495         update_ple_window_actual_max();
6496
6497         /*
6498          * Only enable PML when hardware supports PML feature, and both EPT
6499          * and EPT A/D bit features are enabled -- PML depends on them to work.
6500          */
6501         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6502                 enable_pml = 0;
6503
6504         if (!enable_pml) {
6505                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6506                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6507                 kvm_x86_ops->flush_log_dirty = NULL;
6508                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6509         }
6510
6511         if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
6512                 u64 vmx_msr;
6513
6514                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
6515                 cpu_preemption_timer_multi =
6516                          vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
6517         } else {
6518                 kvm_x86_ops->set_hv_timer = NULL;
6519                 kvm_x86_ops->cancel_hv_timer = NULL;
6520         }
6521
6522         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6523
6524         kvm_mce_cap_supported |= MCG_LMCE_P;
6525
6526         return alloc_kvm_area();
6527
6528 out8:
6529         free_page((unsigned long)vmx_vmwrite_bitmap);
6530 out7:
6531         free_page((unsigned long)vmx_vmread_bitmap);
6532 out6:
6533         if (nested)
6534                 free_page((unsigned long)vmx_msr_bitmap_nested);
6535 out5:
6536         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6537 out4:
6538         free_page((unsigned long)vmx_msr_bitmap_longmode);
6539 out3:
6540         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6541 out2:
6542         free_page((unsigned long)vmx_msr_bitmap_legacy);
6543 out1:
6544         free_page((unsigned long)vmx_io_bitmap_b);
6545 out:
6546         free_page((unsigned long)vmx_io_bitmap_a);
6547
6548     return r;
6549 }
6550
6551 static __exit void hardware_unsetup(void)
6552 {
6553         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6554         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6555         free_page((unsigned long)vmx_msr_bitmap_legacy);
6556         free_page((unsigned long)vmx_msr_bitmap_longmode);
6557         free_page((unsigned long)vmx_io_bitmap_b);
6558         free_page((unsigned long)vmx_io_bitmap_a);
6559         free_page((unsigned long)vmx_vmwrite_bitmap);
6560         free_page((unsigned long)vmx_vmread_bitmap);
6561         if (nested)
6562                 free_page((unsigned long)vmx_msr_bitmap_nested);
6563
6564         free_kvm_area();
6565 }
6566
6567 /*
6568  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6569  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6570  */
6571 static int handle_pause(struct kvm_vcpu *vcpu)
6572 {
6573         if (ple_gap)
6574                 grow_ple_window(vcpu);
6575
6576         skip_emulated_instruction(vcpu);
6577         kvm_vcpu_on_spin(vcpu);
6578
6579         return 1;
6580 }
6581
6582 static int handle_nop(struct kvm_vcpu *vcpu)
6583 {
6584         skip_emulated_instruction(vcpu);
6585         return 1;
6586 }
6587
6588 static int handle_mwait(struct kvm_vcpu *vcpu)
6589 {
6590         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6591         return handle_nop(vcpu);
6592 }
6593
6594 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6595 {
6596         return 1;
6597 }
6598
6599 static int handle_monitor(struct kvm_vcpu *vcpu)
6600 {
6601         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6602         return handle_nop(vcpu);
6603 }
6604
6605 /*
6606  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6607  * We could reuse a single VMCS for all the L2 guests, but we also want the
6608  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6609  * allows keeping them loaded on the processor, and in the future will allow
6610  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6611  * every entry if they never change.
6612  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6613  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6614  *
6615  * The following functions allocate and free a vmcs02 in this pool.
6616  */
6617
6618 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6619 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6620 {
6621         struct vmcs02_list *item;
6622         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6623                 if (item->vmptr == vmx->nested.current_vmptr) {
6624                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6625                         return &item->vmcs02;
6626                 }
6627
6628         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6629                 /* Recycle the least recently used VMCS. */
6630                 item = list_last_entry(&vmx->nested.vmcs02_pool,
6631                                        struct vmcs02_list, list);
6632                 item->vmptr = vmx->nested.current_vmptr;
6633                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6634                 return &item->vmcs02;
6635         }
6636
6637         /* Create a new VMCS */
6638         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6639         if (!item)
6640                 return NULL;
6641         item->vmcs02.vmcs = alloc_vmcs();
6642         if (!item->vmcs02.vmcs) {
6643                 kfree(item);
6644                 return NULL;
6645         }
6646         loaded_vmcs_init(&item->vmcs02);
6647         item->vmptr = vmx->nested.current_vmptr;
6648         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6649         vmx->nested.vmcs02_num++;
6650         return &item->vmcs02;
6651 }
6652
6653 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6654 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6655 {
6656         struct vmcs02_list *item;
6657         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6658                 if (item->vmptr == vmptr) {
6659                         free_loaded_vmcs(&item->vmcs02);
6660                         list_del(&item->list);
6661                         kfree(item);
6662                         vmx->nested.vmcs02_num--;
6663                         return;
6664                 }
6665 }
6666
6667 /*
6668  * Free all VMCSs saved for this vcpu, except the one pointed by
6669  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6670  * must be &vmx->vmcs01.
6671  */
6672 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6673 {
6674         struct vmcs02_list *item, *n;
6675
6676         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6677         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6678                 /*
6679                  * Something will leak if the above WARN triggers.  Better than
6680                  * a use-after-free.
6681                  */
6682                 if (vmx->loaded_vmcs == &item->vmcs02)
6683                         continue;
6684
6685                 free_loaded_vmcs(&item->vmcs02);
6686                 list_del(&item->list);
6687                 kfree(item);
6688                 vmx->nested.vmcs02_num--;
6689         }
6690 }
6691
6692 /*
6693  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6694  * set the success or error code of an emulated VMX instruction, as specified
6695  * by Vol 2B, VMX Instruction Reference, "Conventions".
6696  */
6697 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6698 {
6699         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6700                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6701                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6702 }
6703
6704 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6705 {
6706         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6707                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6708                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6709                         | X86_EFLAGS_CF);
6710 }
6711
6712 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6713                                         u32 vm_instruction_error)
6714 {
6715         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6716                 /*
6717                  * failValid writes the error number to the current VMCS, which
6718                  * can't be done there isn't a current VMCS.
6719                  */
6720                 nested_vmx_failInvalid(vcpu);
6721                 return;
6722         }
6723         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6724                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6725                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6726                         | X86_EFLAGS_ZF);
6727         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6728         /*
6729          * We don't need to force a shadow sync because
6730          * VM_INSTRUCTION_ERROR is not shadowed
6731          */
6732 }
6733
6734 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6735 {
6736         /* TODO: not to reset guest simply here. */
6737         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6738         pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6739 }
6740
6741 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6742 {
6743         struct vcpu_vmx *vmx =
6744                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6745
6746         vmx->nested.preemption_timer_expired = true;
6747         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6748         kvm_vcpu_kick(&vmx->vcpu);
6749
6750         return HRTIMER_NORESTART;
6751 }
6752
6753 /*
6754  * Decode the memory-address operand of a vmx instruction, as recorded on an
6755  * exit caused by such an instruction (run by a guest hypervisor).
6756  * On success, returns 0. When the operand is invalid, returns 1 and throws
6757  * #UD or #GP.
6758  */
6759 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6760                                  unsigned long exit_qualification,
6761                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
6762 {
6763         gva_t off;
6764         bool exn;
6765         struct kvm_segment s;
6766
6767         /*
6768          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6769          * Execution", on an exit, vmx_instruction_info holds most of the
6770          * addressing components of the operand. Only the displacement part
6771          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6772          * For how an actual address is calculated from all these components,
6773          * refer to Vol. 1, "Operand Addressing".
6774          */
6775         int  scaling = vmx_instruction_info & 3;
6776         int  addr_size = (vmx_instruction_info >> 7) & 7;
6777         bool is_reg = vmx_instruction_info & (1u << 10);
6778         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6779         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6780         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6781         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6782         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6783
6784         if (is_reg) {
6785                 kvm_queue_exception(vcpu, UD_VECTOR);
6786                 return 1;
6787         }
6788
6789         /* Addr = segment_base + offset */
6790         /* offset = base + [index * scale] + displacement */
6791         off = exit_qualification; /* holds the displacement */
6792         if (base_is_valid)
6793                 off += kvm_register_read(vcpu, base_reg);
6794         if (index_is_valid)
6795                 off += kvm_register_read(vcpu, index_reg)<<scaling;
6796         vmx_get_segment(vcpu, &s, seg_reg);
6797         *ret = s.base + off;
6798
6799         if (addr_size == 1) /* 32 bit */
6800                 *ret &= 0xffffffff;
6801
6802         /* Checks for #GP/#SS exceptions. */
6803         exn = false;
6804         if (is_protmode(vcpu)) {
6805                 /* Protected mode: apply checks for segment validity in the
6806                  * following order:
6807                  * - segment type check (#GP(0) may be thrown)
6808                  * - usability check (#GP(0)/#SS(0))
6809                  * - limit check (#GP(0)/#SS(0))
6810                  */
6811                 if (wr)
6812                         /* #GP(0) if the destination operand is located in a
6813                          * read-only data segment or any code segment.
6814                          */
6815                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
6816                 else
6817                         /* #GP(0) if the source operand is located in an
6818                          * execute-only code segment
6819                          */
6820                         exn = ((s.type & 0xa) == 8);
6821         }
6822         if (exn) {
6823                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6824                 return 1;
6825         }
6826         if (is_long_mode(vcpu)) {
6827                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6828                  * non-canonical form. This is an only check for long mode.
6829                  */
6830                 exn = is_noncanonical_address(*ret);
6831         } else if (is_protmode(vcpu)) {
6832                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6833                  */
6834                 exn = (s.unusable != 0);
6835                 /* Protected mode: #GP(0)/#SS(0) if the memory
6836                  * operand is outside the segment limit.
6837                  */
6838                 exn = exn || (off + sizeof(u64) > s.limit);
6839         }
6840         if (exn) {
6841                 kvm_queue_exception_e(vcpu,
6842                                       seg_reg == VCPU_SREG_SS ?
6843                                                 SS_VECTOR : GP_VECTOR,
6844                                       0);
6845                 return 1;
6846         }
6847
6848         return 0;
6849 }
6850
6851 /*
6852  * This function performs the various checks including
6853  * - if it's 4KB aligned
6854  * - No bits beyond the physical address width are set
6855  * - Returns 0 on success or else 1
6856  * (Intel SDM Section 30.3)
6857  */
6858 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6859                                   gpa_t *vmpointer)
6860 {
6861         gva_t gva;
6862         gpa_t vmptr;
6863         struct x86_exception e;
6864         struct page *page;
6865         struct vcpu_vmx *vmx = to_vmx(vcpu);
6866         int maxphyaddr = cpuid_maxphyaddr(vcpu);
6867
6868         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6869                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6870                 return 1;
6871
6872         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6873                                 sizeof(vmptr), &e)) {
6874                 kvm_inject_page_fault(vcpu, &e);
6875                 return 1;
6876         }
6877
6878         switch (exit_reason) {
6879         case EXIT_REASON_VMON:
6880                 /*
6881                  * SDM 3: 24.11.5
6882                  * The first 4 bytes of VMXON region contain the supported
6883                  * VMCS revision identifier
6884                  *
6885                  * Note - IA32_VMX_BASIC[48] will never be 1
6886                  * for the nested case;
6887                  * which replaces physical address width with 32
6888                  *
6889                  */
6890                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6891                         nested_vmx_failInvalid(vcpu);
6892                         skip_emulated_instruction(vcpu);
6893                         return 1;
6894                 }
6895
6896                 page = nested_get_page(vcpu, vmptr);
6897                 if (page == NULL ||
6898                     *(u32 *)kmap(page) != VMCS12_REVISION) {
6899                         nested_vmx_failInvalid(vcpu);
6900                         kunmap(page);
6901                         skip_emulated_instruction(vcpu);
6902                         return 1;
6903                 }
6904                 kunmap(page);
6905                 vmx->nested.vmxon_ptr = vmptr;
6906                 break;
6907         case EXIT_REASON_VMCLEAR:
6908                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6909                         nested_vmx_failValid(vcpu,
6910                                              VMXERR_VMCLEAR_INVALID_ADDRESS);
6911                         skip_emulated_instruction(vcpu);
6912                         return 1;
6913                 }
6914
6915                 if (vmptr == vmx->nested.vmxon_ptr) {
6916                         nested_vmx_failValid(vcpu,
6917                                              VMXERR_VMCLEAR_VMXON_POINTER);
6918                         skip_emulated_instruction(vcpu);
6919                         return 1;
6920                 }
6921                 break;
6922         case EXIT_REASON_VMPTRLD:
6923                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6924                         nested_vmx_failValid(vcpu,
6925                                              VMXERR_VMPTRLD_INVALID_ADDRESS);
6926                         skip_emulated_instruction(vcpu);
6927                         return 1;
6928                 }
6929
6930                 if (vmptr == vmx->nested.vmxon_ptr) {
6931                         nested_vmx_failValid(vcpu,
6932                                              VMXERR_VMCLEAR_VMXON_POINTER);
6933                         skip_emulated_instruction(vcpu);
6934                         return 1;
6935                 }
6936                 break;
6937         default:
6938                 return 1; /* shouldn't happen */
6939         }
6940
6941         if (vmpointer)
6942                 *vmpointer = vmptr;
6943         return 0;
6944 }
6945
6946 /*
6947  * Emulate the VMXON instruction.
6948  * Currently, we just remember that VMX is active, and do not save or even
6949  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6950  * do not currently need to store anything in that guest-allocated memory
6951  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6952  * argument is different from the VMXON pointer (which the spec says they do).
6953  */
6954 static int handle_vmon(struct kvm_vcpu *vcpu)
6955 {
6956         struct kvm_segment cs;
6957         struct vcpu_vmx *vmx = to_vmx(vcpu);
6958         struct vmcs *shadow_vmcs;
6959         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6960                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6961
6962         /* The Intel VMX Instruction Reference lists a bunch of bits that
6963          * are prerequisite to running VMXON, most notably cr4.VMXE must be
6964          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6965          * Otherwise, we should fail with #UD. We test these now:
6966          */
6967         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6968             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6969             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6970                 kvm_queue_exception(vcpu, UD_VECTOR);
6971                 return 1;
6972         }
6973
6974         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6975         if (is_long_mode(vcpu) && !cs.l) {
6976                 kvm_queue_exception(vcpu, UD_VECTOR);
6977                 return 1;
6978         }
6979
6980         if (vmx_get_cpl(vcpu)) {
6981                 kvm_inject_gp(vcpu, 0);
6982                 return 1;
6983         }
6984
6985         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
6986                 return 1;
6987
6988         if (vmx->nested.vmxon) {
6989                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6990                 skip_emulated_instruction(vcpu);
6991                 return 1;
6992         }
6993
6994         if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6995                         != VMXON_NEEDED_FEATURES) {
6996                 kvm_inject_gp(vcpu, 0);
6997                 return 1;
6998         }
6999
7000         vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
7001         if (!vmx->nested.cached_vmcs12)
7002                 return -ENOMEM;
7003
7004         if (enable_shadow_vmcs) {
7005                 shadow_vmcs = alloc_vmcs();
7006                 if (!shadow_vmcs) {
7007                         kfree(vmx->nested.cached_vmcs12);
7008                         return -ENOMEM;
7009                 }
7010                 /* mark vmcs as shadow */
7011                 shadow_vmcs->revision_id |= (1u << 31);
7012                 /* init shadow vmcs */
7013                 vmcs_clear(shadow_vmcs);
7014                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
7015         }
7016
7017         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
7018         vmx->nested.vmcs02_num = 0;
7019
7020         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
7021                      HRTIMER_MODE_REL);
7022         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
7023
7024         vmx->nested.vmxon = true;
7025
7026         skip_emulated_instruction(vcpu);
7027         nested_vmx_succeed(vcpu);
7028         return 1;
7029 }
7030
7031 /*
7032  * Intel's VMX Instruction Reference specifies a common set of prerequisites
7033  * for running VMX instructions (except VMXON, whose prerequisites are
7034  * slightly different). It also specifies what exception to inject otherwise.
7035  */
7036 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7037 {
7038         struct kvm_segment cs;
7039         struct vcpu_vmx *vmx = to_vmx(vcpu);
7040
7041         if (!vmx->nested.vmxon) {
7042                 kvm_queue_exception(vcpu, UD_VECTOR);
7043                 return 0;
7044         }
7045
7046         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
7047         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
7048             (is_long_mode(vcpu) && !cs.l)) {
7049                 kvm_queue_exception(vcpu, UD_VECTOR);
7050                 return 0;
7051         }
7052
7053         if (vmx_get_cpl(vcpu)) {
7054                 kvm_inject_gp(vcpu, 0);
7055                 return 0;
7056         }
7057
7058         return 1;
7059 }
7060
7061 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7062 {
7063         if (vmx->nested.current_vmptr == -1ull)
7064                 return;
7065
7066         /* current_vmptr and current_vmcs12 are always set/reset together */
7067         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
7068                 return;
7069
7070         if (enable_shadow_vmcs) {
7071                 /* copy to memory all shadowed fields in case
7072                    they were modified */
7073                 copy_shadow_to_vmcs12(vmx);
7074                 vmx->nested.sync_shadow_vmcs = false;
7075                 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
7076                                 SECONDARY_EXEC_SHADOW_VMCS);
7077                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7078         }
7079         vmx->nested.posted_intr_nv = -1;
7080
7081         /* Flush VMCS12 to guest memory */
7082         memcpy(vmx->nested.current_vmcs12, vmx->nested.cached_vmcs12,
7083                VMCS12_SIZE);
7084
7085         kunmap(vmx->nested.current_vmcs12_page);
7086         nested_release_page(vmx->nested.current_vmcs12_page);
7087         vmx->nested.current_vmptr = -1ull;
7088         vmx->nested.current_vmcs12 = NULL;
7089 }
7090
7091 /*
7092  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7093  * just stops using VMX.
7094  */
7095 static void free_nested(struct vcpu_vmx *vmx)
7096 {
7097         if (!vmx->nested.vmxon)
7098                 return;
7099
7100         vmx->nested.vmxon = false;
7101         free_vpid(vmx->nested.vpid02);
7102         nested_release_vmcs12(vmx);
7103         if (enable_shadow_vmcs)
7104                 free_vmcs(vmx->nested.current_shadow_vmcs);
7105         kfree(vmx->nested.cached_vmcs12);
7106         /* Unpin physical memory we referred to in current vmcs02 */
7107         if (vmx->nested.apic_access_page) {
7108                 nested_release_page(vmx->nested.apic_access_page);
7109                 vmx->nested.apic_access_page = NULL;
7110         }
7111         if (vmx->nested.virtual_apic_page) {
7112                 nested_release_page(vmx->nested.virtual_apic_page);
7113                 vmx->nested.virtual_apic_page = NULL;
7114         }
7115         if (vmx->nested.pi_desc_page) {
7116                 kunmap(vmx->nested.pi_desc_page);
7117                 nested_release_page(vmx->nested.pi_desc_page);
7118                 vmx->nested.pi_desc_page = NULL;
7119                 vmx->nested.pi_desc = NULL;
7120         }
7121
7122         nested_free_all_saved_vmcss(vmx);
7123 }
7124
7125 /* Emulate the VMXOFF instruction */
7126 static int handle_vmoff(struct kvm_vcpu *vcpu)
7127 {
7128         if (!nested_vmx_check_permission(vcpu))
7129                 return 1;
7130         free_nested(to_vmx(vcpu));
7131         skip_emulated_instruction(vcpu);
7132         nested_vmx_succeed(vcpu);
7133         return 1;
7134 }
7135
7136 /* Emulate the VMCLEAR instruction */
7137 static int handle_vmclear(struct kvm_vcpu *vcpu)
7138 {
7139         struct vcpu_vmx *vmx = to_vmx(vcpu);
7140         gpa_t vmptr;
7141         struct vmcs12 *vmcs12;
7142         struct page *page;
7143
7144         if (!nested_vmx_check_permission(vcpu))
7145                 return 1;
7146
7147         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
7148                 return 1;
7149
7150         if (vmptr == vmx->nested.current_vmptr)
7151                 nested_release_vmcs12(vmx);
7152
7153         page = nested_get_page(vcpu, vmptr);
7154         if (page == NULL) {
7155                 /*
7156                  * For accurate processor emulation, VMCLEAR beyond available
7157                  * physical memory should do nothing at all. However, it is
7158                  * possible that a nested vmx bug, not a guest hypervisor bug,
7159                  * resulted in this case, so let's shut down before doing any
7160                  * more damage:
7161                  */
7162                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7163                 return 1;
7164         }
7165         vmcs12 = kmap(page);
7166         vmcs12->launch_state = 0;
7167         kunmap(page);
7168         nested_release_page(page);
7169
7170         nested_free_vmcs02(vmx, vmptr);
7171
7172         skip_emulated_instruction(vcpu);
7173         nested_vmx_succeed(vcpu);
7174         return 1;
7175 }
7176
7177 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7178
7179 /* Emulate the VMLAUNCH instruction */
7180 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7181 {
7182         return nested_vmx_run(vcpu, true);
7183 }
7184
7185 /* Emulate the VMRESUME instruction */
7186 static int handle_vmresume(struct kvm_vcpu *vcpu)
7187 {
7188
7189         return nested_vmx_run(vcpu, false);
7190 }
7191
7192 enum vmcs_field_type {
7193         VMCS_FIELD_TYPE_U16 = 0,
7194         VMCS_FIELD_TYPE_U64 = 1,
7195         VMCS_FIELD_TYPE_U32 = 2,
7196         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
7197 };
7198
7199 static inline int vmcs_field_type(unsigned long field)
7200 {
7201         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
7202                 return VMCS_FIELD_TYPE_U32;
7203         return (field >> 13) & 0x3 ;
7204 }
7205
7206 static inline int vmcs_field_readonly(unsigned long field)
7207 {
7208         return (((field >> 10) & 0x3) == 1);
7209 }
7210
7211 /*
7212  * Read a vmcs12 field. Since these can have varying lengths and we return
7213  * one type, we chose the biggest type (u64) and zero-extend the return value
7214  * to that size. Note that the caller, handle_vmread, might need to use only
7215  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7216  * 64-bit fields are to be returned).
7217  */
7218 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7219                                   unsigned long field, u64 *ret)
7220 {
7221         short offset = vmcs_field_to_offset(field);
7222         char *p;
7223
7224         if (offset < 0)
7225                 return offset;
7226
7227         p = ((char *)(get_vmcs12(vcpu))) + offset;
7228
7229         switch (vmcs_field_type(field)) {
7230         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7231                 *ret = *((natural_width *)p);
7232                 return 0;
7233         case VMCS_FIELD_TYPE_U16:
7234                 *ret = *((u16 *)p);
7235                 return 0;
7236         case VMCS_FIELD_TYPE_U32:
7237                 *ret = *((u32 *)p);
7238                 return 0;
7239         case VMCS_FIELD_TYPE_U64:
7240                 *ret = *((u64 *)p);
7241                 return 0;
7242         default:
7243                 WARN_ON(1);
7244                 return -ENOENT;
7245         }
7246 }
7247
7248
7249 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7250                                    unsigned long field, u64 field_value){
7251         short offset = vmcs_field_to_offset(field);
7252         char *p = ((char *) get_vmcs12(vcpu)) + offset;
7253         if (offset < 0)
7254                 return offset;
7255
7256         switch (vmcs_field_type(field)) {
7257         case VMCS_FIELD_TYPE_U16:
7258                 *(u16 *)p = field_value;
7259                 return 0;
7260         case VMCS_FIELD_TYPE_U32:
7261                 *(u32 *)p = field_value;
7262                 return 0;
7263         case VMCS_FIELD_TYPE_U64:
7264                 *(u64 *)p = field_value;
7265                 return 0;
7266         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7267                 *(natural_width *)p = field_value;
7268                 return 0;
7269         default:
7270                 WARN_ON(1);
7271                 return -ENOENT;
7272         }
7273
7274 }
7275
7276 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7277 {
7278         int i;
7279         unsigned long field;
7280         u64 field_value;
7281         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7282         const unsigned long *fields = shadow_read_write_fields;
7283         const int num_fields = max_shadow_read_write_fields;
7284
7285         preempt_disable();
7286
7287         vmcs_load(shadow_vmcs);
7288
7289         for (i = 0; i < num_fields; i++) {
7290                 field = fields[i];
7291                 switch (vmcs_field_type(field)) {
7292                 case VMCS_FIELD_TYPE_U16:
7293                         field_value = vmcs_read16(field);
7294                         break;
7295                 case VMCS_FIELD_TYPE_U32:
7296                         field_value = vmcs_read32(field);
7297                         break;
7298                 case VMCS_FIELD_TYPE_U64:
7299                         field_value = vmcs_read64(field);
7300                         break;
7301                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7302                         field_value = vmcs_readl(field);
7303                         break;
7304                 default:
7305                         WARN_ON(1);
7306                         continue;
7307                 }
7308                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7309         }
7310
7311         vmcs_clear(shadow_vmcs);
7312         vmcs_load(vmx->loaded_vmcs->vmcs);
7313
7314         preempt_enable();
7315 }
7316
7317 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7318 {
7319         const unsigned long *fields[] = {
7320                 shadow_read_write_fields,
7321                 shadow_read_only_fields
7322         };
7323         const int max_fields[] = {
7324                 max_shadow_read_write_fields,
7325                 max_shadow_read_only_fields
7326         };
7327         int i, q;
7328         unsigned long field;
7329         u64 field_value = 0;
7330         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7331
7332         vmcs_load(shadow_vmcs);
7333
7334         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7335                 for (i = 0; i < max_fields[q]; i++) {
7336                         field = fields[q][i];
7337                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7338
7339                         switch (vmcs_field_type(field)) {
7340                         case VMCS_FIELD_TYPE_U16:
7341                                 vmcs_write16(field, (u16)field_value);
7342                                 break;
7343                         case VMCS_FIELD_TYPE_U32:
7344                                 vmcs_write32(field, (u32)field_value);
7345                                 break;
7346                         case VMCS_FIELD_TYPE_U64:
7347                                 vmcs_write64(field, (u64)field_value);
7348                                 break;
7349                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7350                                 vmcs_writel(field, (long)field_value);
7351                                 break;
7352                         default:
7353                                 WARN_ON(1);
7354                                 break;
7355                         }
7356                 }
7357         }
7358
7359         vmcs_clear(shadow_vmcs);
7360         vmcs_load(vmx->loaded_vmcs->vmcs);
7361 }
7362
7363 /*
7364  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7365  * used before) all generate the same failure when it is missing.
7366  */
7367 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7368 {
7369         struct vcpu_vmx *vmx = to_vmx(vcpu);
7370         if (vmx->nested.current_vmptr == -1ull) {
7371                 nested_vmx_failInvalid(vcpu);
7372                 skip_emulated_instruction(vcpu);
7373                 return 0;
7374         }
7375         return 1;
7376 }
7377
7378 static int handle_vmread(struct kvm_vcpu *vcpu)
7379 {
7380         unsigned long field;
7381         u64 field_value;
7382         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7383         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7384         gva_t gva = 0;
7385
7386         if (!nested_vmx_check_permission(vcpu) ||
7387             !nested_vmx_check_vmcs12(vcpu))
7388                 return 1;
7389
7390         /* Decode instruction info and find the field to read */
7391         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7392         /* Read the field, zero-extended to a u64 field_value */
7393         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7394                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7395                 skip_emulated_instruction(vcpu);
7396                 return 1;
7397         }
7398         /*
7399          * Now copy part of this value to register or memory, as requested.
7400          * Note that the number of bits actually copied is 32 or 64 depending
7401          * on the guest's mode (32 or 64 bit), not on the given field's length.
7402          */
7403         if (vmx_instruction_info & (1u << 10)) {
7404                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7405                         field_value);
7406         } else {
7407                 if (get_vmx_mem_address(vcpu, exit_qualification,
7408                                 vmx_instruction_info, true, &gva))
7409                         return 1;
7410                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7411                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7412                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7413         }
7414
7415         nested_vmx_succeed(vcpu);
7416         skip_emulated_instruction(vcpu);
7417         return 1;
7418 }
7419
7420
7421 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7422 {
7423         unsigned long field;
7424         gva_t gva;
7425         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7426         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7427         /* The value to write might be 32 or 64 bits, depending on L1's long
7428          * mode, and eventually we need to write that into a field of several
7429          * possible lengths. The code below first zero-extends the value to 64
7430          * bit (field_value), and then copies only the appropriate number of
7431          * bits into the vmcs12 field.
7432          */
7433         u64 field_value = 0;
7434         struct x86_exception e;
7435
7436         if (!nested_vmx_check_permission(vcpu) ||
7437             !nested_vmx_check_vmcs12(vcpu))
7438                 return 1;
7439
7440         if (vmx_instruction_info & (1u << 10))
7441                 field_value = kvm_register_readl(vcpu,
7442                         (((vmx_instruction_info) >> 3) & 0xf));
7443         else {
7444                 if (get_vmx_mem_address(vcpu, exit_qualification,
7445                                 vmx_instruction_info, false, &gva))
7446                         return 1;
7447                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7448                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7449                         kvm_inject_page_fault(vcpu, &e);
7450                         return 1;
7451                 }
7452         }
7453
7454
7455         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7456         if (vmcs_field_readonly(field)) {
7457                 nested_vmx_failValid(vcpu,
7458                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7459                 skip_emulated_instruction(vcpu);
7460                 return 1;
7461         }
7462
7463         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7464                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7465                 skip_emulated_instruction(vcpu);
7466                 return 1;
7467         }
7468
7469         nested_vmx_succeed(vcpu);
7470         skip_emulated_instruction(vcpu);
7471         return 1;
7472 }
7473
7474 /* Emulate the VMPTRLD instruction */
7475 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7476 {
7477         struct vcpu_vmx *vmx = to_vmx(vcpu);
7478         gpa_t vmptr;
7479
7480         if (!nested_vmx_check_permission(vcpu))
7481                 return 1;
7482
7483         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7484                 return 1;
7485
7486         if (vmx->nested.current_vmptr != vmptr) {
7487                 struct vmcs12 *new_vmcs12;
7488                 struct page *page;
7489                 page = nested_get_page(vcpu, vmptr);
7490                 if (page == NULL) {
7491                         nested_vmx_failInvalid(vcpu);
7492                         skip_emulated_instruction(vcpu);
7493                         return 1;
7494                 }
7495                 new_vmcs12 = kmap(page);
7496                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7497                         kunmap(page);
7498                         nested_release_page_clean(page);
7499                         nested_vmx_failValid(vcpu,
7500                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7501                         skip_emulated_instruction(vcpu);
7502                         return 1;
7503                 }
7504
7505                 nested_release_vmcs12(vmx);
7506                 vmx->nested.current_vmptr = vmptr;
7507                 vmx->nested.current_vmcs12 = new_vmcs12;
7508                 vmx->nested.current_vmcs12_page = page;
7509                 /*
7510                  * Load VMCS12 from guest memory since it is not already
7511                  * cached.
7512                  */
7513                 memcpy(vmx->nested.cached_vmcs12,
7514                        vmx->nested.current_vmcs12, VMCS12_SIZE);
7515
7516                 if (enable_shadow_vmcs) {
7517                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7518                                       SECONDARY_EXEC_SHADOW_VMCS);
7519                         vmcs_write64(VMCS_LINK_POINTER,
7520                                      __pa(vmx->nested.current_shadow_vmcs));
7521                         vmx->nested.sync_shadow_vmcs = true;
7522                 }
7523         }
7524
7525         nested_vmx_succeed(vcpu);
7526         skip_emulated_instruction(vcpu);
7527         return 1;
7528 }
7529
7530 /* Emulate the VMPTRST instruction */
7531 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7532 {
7533         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7534         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7535         gva_t vmcs_gva;
7536         struct x86_exception e;
7537
7538         if (!nested_vmx_check_permission(vcpu))
7539                 return 1;
7540
7541         if (get_vmx_mem_address(vcpu, exit_qualification,
7542                         vmx_instruction_info, true, &vmcs_gva))
7543                 return 1;
7544         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7545         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7546                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7547                                  sizeof(u64), &e)) {
7548                 kvm_inject_page_fault(vcpu, &e);
7549                 return 1;
7550         }
7551         nested_vmx_succeed(vcpu);
7552         skip_emulated_instruction(vcpu);
7553         return 1;
7554 }
7555
7556 /* Emulate the INVEPT instruction */
7557 static int handle_invept(struct kvm_vcpu *vcpu)
7558 {
7559         struct vcpu_vmx *vmx = to_vmx(vcpu);
7560         u32 vmx_instruction_info, types;
7561         unsigned long type;
7562         gva_t gva;
7563         struct x86_exception e;
7564         struct {
7565                 u64 eptp, gpa;
7566         } operand;
7567
7568         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7569               SECONDARY_EXEC_ENABLE_EPT) ||
7570             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7571                 kvm_queue_exception(vcpu, UD_VECTOR);
7572                 return 1;
7573         }
7574
7575         if (!nested_vmx_check_permission(vcpu))
7576                 return 1;
7577
7578         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7579                 kvm_queue_exception(vcpu, UD_VECTOR);
7580                 return 1;
7581         }
7582
7583         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7584         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7585
7586         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7587
7588         if (!(types & (1UL << type))) {
7589                 nested_vmx_failValid(vcpu,
7590                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7591                 skip_emulated_instruction(vcpu);
7592                 return 1;
7593         }
7594
7595         /* According to the Intel VMX instruction reference, the memory
7596          * operand is read even if it isn't needed (e.g., for type==global)
7597          */
7598         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7599                         vmx_instruction_info, false, &gva))
7600                 return 1;
7601         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7602                                 sizeof(operand), &e)) {
7603                 kvm_inject_page_fault(vcpu, &e);
7604                 return 1;
7605         }
7606
7607         switch (type) {
7608         case VMX_EPT_EXTENT_GLOBAL:
7609                 kvm_mmu_sync_roots(vcpu);
7610                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7611                 nested_vmx_succeed(vcpu);
7612                 break;
7613         default:
7614                 /* Trap single context invalidation invept calls */
7615                 BUG_ON(1);
7616                 break;
7617         }
7618
7619         skip_emulated_instruction(vcpu);
7620         return 1;
7621 }
7622
7623 static int handle_invvpid(struct kvm_vcpu *vcpu)
7624 {
7625         struct vcpu_vmx *vmx = to_vmx(vcpu);
7626         u32 vmx_instruction_info;
7627         unsigned long type, types;
7628         gva_t gva;
7629         struct x86_exception e;
7630         int vpid;
7631
7632         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7633               SECONDARY_EXEC_ENABLE_VPID) ||
7634                         !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7635                 kvm_queue_exception(vcpu, UD_VECTOR);
7636                 return 1;
7637         }
7638
7639         if (!nested_vmx_check_permission(vcpu))
7640                 return 1;
7641
7642         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7643         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7644
7645         types = (vmx->nested.nested_vmx_vpid_caps >> 8) & 0x7;
7646
7647         if (!(types & (1UL << type))) {
7648                 nested_vmx_failValid(vcpu,
7649                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7650                 skip_emulated_instruction(vcpu);
7651                 return 1;
7652         }
7653
7654         /* according to the intel vmx instruction reference, the memory
7655          * operand is read even if it isn't needed (e.g., for type==global)
7656          */
7657         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7658                         vmx_instruction_info, false, &gva))
7659                 return 1;
7660         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7661                                 sizeof(u32), &e)) {
7662                 kvm_inject_page_fault(vcpu, &e);
7663                 return 1;
7664         }
7665
7666         switch (type) {
7667         case VMX_VPID_EXTENT_SINGLE_CONTEXT:
7668                 /*
7669                  * Old versions of KVM use the single-context version so we
7670                  * have to support it; just treat it the same as all-context.
7671                  */
7672         case VMX_VPID_EXTENT_ALL_CONTEXT:
7673                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
7674                 nested_vmx_succeed(vcpu);
7675                 break;
7676         default:
7677                 /* Trap individual address invalidation invvpid calls */
7678                 BUG_ON(1);
7679                 break;
7680         }
7681
7682         skip_emulated_instruction(vcpu);
7683         return 1;
7684 }
7685
7686 static int handle_pml_full(struct kvm_vcpu *vcpu)
7687 {
7688         unsigned long exit_qualification;
7689
7690         trace_kvm_pml_full(vcpu->vcpu_id);
7691
7692         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7693
7694         /*
7695          * PML buffer FULL happened while executing iret from NMI,
7696          * "blocked by NMI" bit has to be set before next VM entry.
7697          */
7698         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7699                         cpu_has_virtual_nmis() &&
7700                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7701                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7702                                 GUEST_INTR_STATE_NMI);
7703
7704         /*
7705          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7706          * here.., and there's no userspace involvement needed for PML.
7707          */
7708         return 1;
7709 }
7710
7711 static int handle_pcommit(struct kvm_vcpu *vcpu)
7712 {
7713         /* we never catch pcommit instruct for L1 guest. */
7714         WARN_ON(1);
7715         return 1;
7716 }
7717
7718 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
7719 {
7720         kvm_lapic_expired_hv_timer(vcpu);
7721         return 1;
7722 }
7723
7724 /*
7725  * The exit handlers return 1 if the exit was handled fully and guest execution
7726  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
7727  * to be done to userspace and return 0.
7728  */
7729 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7730         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
7731         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
7732         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
7733         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
7734         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
7735         [EXIT_REASON_CR_ACCESS]               = handle_cr,
7736         [EXIT_REASON_DR_ACCESS]               = handle_dr,
7737         [EXIT_REASON_CPUID]                   = handle_cpuid,
7738         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
7739         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
7740         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
7741         [EXIT_REASON_HLT]                     = handle_halt,
7742         [EXIT_REASON_INVD]                    = handle_invd,
7743         [EXIT_REASON_INVLPG]                  = handle_invlpg,
7744         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
7745         [EXIT_REASON_VMCALL]                  = handle_vmcall,
7746         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
7747         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
7748         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
7749         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
7750         [EXIT_REASON_VMREAD]                  = handle_vmread,
7751         [EXIT_REASON_VMRESUME]                = handle_vmresume,
7752         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
7753         [EXIT_REASON_VMOFF]                   = handle_vmoff,
7754         [EXIT_REASON_VMON]                    = handle_vmon,
7755         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
7756         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
7757         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
7758         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
7759         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
7760         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
7761         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
7762         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
7763         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
7764         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
7765         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
7766         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
7767         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
7768         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
7769         [EXIT_REASON_INVEPT]                  = handle_invept,
7770         [EXIT_REASON_INVVPID]                 = handle_invvpid,
7771         [EXIT_REASON_XSAVES]                  = handle_xsaves,
7772         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
7773         [EXIT_REASON_PML_FULL]                = handle_pml_full,
7774         [EXIT_REASON_PCOMMIT]                 = handle_pcommit,
7775         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
7776 };
7777
7778 static const int kvm_vmx_max_exit_handlers =
7779         ARRAY_SIZE(kvm_vmx_exit_handlers);
7780
7781 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7782                                        struct vmcs12 *vmcs12)
7783 {
7784         unsigned long exit_qualification;
7785         gpa_t bitmap, last_bitmap;
7786         unsigned int port;
7787         int size;
7788         u8 b;
7789
7790         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7791                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7792
7793         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7794
7795         port = exit_qualification >> 16;
7796         size = (exit_qualification & 7) + 1;
7797
7798         last_bitmap = (gpa_t)-1;
7799         b = -1;
7800
7801         while (size > 0) {
7802                 if (port < 0x8000)
7803                         bitmap = vmcs12->io_bitmap_a;
7804                 else if (port < 0x10000)
7805                         bitmap = vmcs12->io_bitmap_b;
7806                 else
7807                         return true;
7808                 bitmap += (port & 0x7fff) / 8;
7809
7810                 if (last_bitmap != bitmap)
7811                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7812                                 return true;
7813                 if (b & (1 << (port & 7)))
7814                         return true;
7815
7816                 port++;
7817                 size--;
7818                 last_bitmap = bitmap;
7819         }
7820
7821         return false;
7822 }
7823
7824 /*
7825  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7826  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7827  * disinterest in the current event (read or write a specific MSR) by using an
7828  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7829  */
7830 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7831         struct vmcs12 *vmcs12, u32 exit_reason)
7832 {
7833         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7834         gpa_t bitmap;
7835
7836         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7837                 return true;
7838
7839         /*
7840          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7841          * for the four combinations of read/write and low/high MSR numbers.
7842          * First we need to figure out which of the four to use:
7843          */
7844         bitmap = vmcs12->msr_bitmap;
7845         if (exit_reason == EXIT_REASON_MSR_WRITE)
7846                 bitmap += 2048;
7847         if (msr_index >= 0xc0000000) {
7848                 msr_index -= 0xc0000000;
7849                 bitmap += 1024;
7850         }
7851
7852         /* Then read the msr_index'th bit from this bitmap: */
7853         if (msr_index < 1024*8) {
7854                 unsigned char b;
7855                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7856                         return true;
7857                 return 1 & (b >> (msr_index & 7));
7858         } else
7859                 return true; /* let L1 handle the wrong parameter */
7860 }
7861
7862 /*
7863  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7864  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7865  * intercept (via guest_host_mask etc.) the current event.
7866  */
7867 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7868         struct vmcs12 *vmcs12)
7869 {
7870         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7871         int cr = exit_qualification & 15;
7872         int reg = (exit_qualification >> 8) & 15;
7873         unsigned long val = kvm_register_readl(vcpu, reg);
7874
7875         switch ((exit_qualification >> 4) & 3) {
7876         case 0: /* mov to cr */
7877                 switch (cr) {
7878                 case 0:
7879                         if (vmcs12->cr0_guest_host_mask &
7880                             (val ^ vmcs12->cr0_read_shadow))
7881                                 return true;
7882                         break;
7883                 case 3:
7884                         if ((vmcs12->cr3_target_count >= 1 &&
7885                                         vmcs12->cr3_target_value0 == val) ||
7886                                 (vmcs12->cr3_target_count >= 2 &&
7887                                         vmcs12->cr3_target_value1 == val) ||
7888                                 (vmcs12->cr3_target_count >= 3 &&
7889                                         vmcs12->cr3_target_value2 == val) ||
7890                                 (vmcs12->cr3_target_count >= 4 &&
7891                                         vmcs12->cr3_target_value3 == val))
7892                                 return false;
7893                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7894                                 return true;
7895                         break;
7896                 case 4:
7897                         if (vmcs12->cr4_guest_host_mask &
7898                             (vmcs12->cr4_read_shadow ^ val))
7899                                 return true;
7900                         break;
7901                 case 8:
7902                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7903                                 return true;
7904                         break;
7905                 }
7906                 break;
7907         case 2: /* clts */
7908                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7909                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
7910                         return true;
7911                 break;
7912         case 1: /* mov from cr */
7913                 switch (cr) {
7914                 case 3:
7915                         if (vmcs12->cpu_based_vm_exec_control &
7916                             CPU_BASED_CR3_STORE_EXITING)
7917                                 return true;
7918                         break;
7919                 case 8:
7920                         if (vmcs12->cpu_based_vm_exec_control &
7921                             CPU_BASED_CR8_STORE_EXITING)
7922                                 return true;
7923                         break;
7924                 }
7925                 break;
7926         case 3: /* lmsw */
7927                 /*
7928                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7929                  * cr0. Other attempted changes are ignored, with no exit.
7930                  */
7931                 if (vmcs12->cr0_guest_host_mask & 0xe &
7932                     (val ^ vmcs12->cr0_read_shadow))
7933                         return true;
7934                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7935                     !(vmcs12->cr0_read_shadow & 0x1) &&
7936                     (val & 0x1))
7937                         return true;
7938                 break;
7939         }
7940         return false;
7941 }
7942
7943 /*
7944  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7945  * should handle it ourselves in L0 (and then continue L2). Only call this
7946  * when in is_guest_mode (L2).
7947  */
7948 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7949 {
7950         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7951         struct vcpu_vmx *vmx = to_vmx(vcpu);
7952         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7953         u32 exit_reason = vmx->exit_reason;
7954
7955         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7956                                 vmcs_readl(EXIT_QUALIFICATION),
7957                                 vmx->idt_vectoring_info,
7958                                 intr_info,
7959                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7960                                 KVM_ISA_VMX);
7961
7962         if (vmx->nested.nested_run_pending)
7963                 return false;
7964
7965         if (unlikely(vmx->fail)) {
7966                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7967                                     vmcs_read32(VM_INSTRUCTION_ERROR));
7968                 return true;
7969         }
7970
7971         switch (exit_reason) {
7972         case EXIT_REASON_EXCEPTION_NMI:
7973                 if (!is_exception(intr_info))
7974                         return false;
7975                 else if (is_page_fault(intr_info))
7976                         return enable_ept;
7977                 else if (is_no_device(intr_info) &&
7978                          !(vmcs12->guest_cr0 & X86_CR0_TS))
7979                         return false;
7980                 else if (is_debug(intr_info) &&
7981                          vcpu->guest_debug &
7982                          (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
7983                         return false;
7984                 else if (is_breakpoint(intr_info) &&
7985                          vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
7986                         return false;
7987                 return vmcs12->exception_bitmap &
7988                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7989         case EXIT_REASON_EXTERNAL_INTERRUPT:
7990                 return false;
7991         case EXIT_REASON_TRIPLE_FAULT:
7992                 return true;
7993         case EXIT_REASON_PENDING_INTERRUPT:
7994                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
7995         case EXIT_REASON_NMI_WINDOW:
7996                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
7997         case EXIT_REASON_TASK_SWITCH:
7998                 return true;
7999         case EXIT_REASON_CPUID:
8000                 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
8001                         return false;
8002                 return true;
8003         case EXIT_REASON_HLT:
8004                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
8005         case EXIT_REASON_INVD:
8006                 return true;
8007         case EXIT_REASON_INVLPG:
8008                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8009         case EXIT_REASON_RDPMC:
8010                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
8011         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
8012                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
8013         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
8014         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
8015         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
8016         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
8017         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
8018         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
8019                 /*
8020                  * VMX instructions trap unconditionally. This allows L1 to
8021                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
8022                  */
8023                 return true;
8024         case EXIT_REASON_CR_ACCESS:
8025                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
8026         case EXIT_REASON_DR_ACCESS:
8027                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
8028         case EXIT_REASON_IO_INSTRUCTION:
8029                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
8030         case EXIT_REASON_MSR_READ:
8031         case EXIT_REASON_MSR_WRITE:
8032                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
8033         case EXIT_REASON_INVALID_STATE:
8034                 return true;
8035         case EXIT_REASON_MWAIT_INSTRUCTION:
8036                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
8037         case EXIT_REASON_MONITOR_TRAP_FLAG:
8038                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
8039         case EXIT_REASON_MONITOR_INSTRUCTION:
8040                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
8041         case EXIT_REASON_PAUSE_INSTRUCTION:
8042                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
8043                         nested_cpu_has2(vmcs12,
8044                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
8045         case EXIT_REASON_MCE_DURING_VMENTRY:
8046                 return false;
8047         case EXIT_REASON_TPR_BELOW_THRESHOLD:
8048                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
8049         case EXIT_REASON_APIC_ACCESS:
8050                 return nested_cpu_has2(vmcs12,
8051                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
8052         case EXIT_REASON_APIC_WRITE:
8053         case EXIT_REASON_EOI_INDUCED:
8054                 /* apic_write and eoi_induced should exit unconditionally. */
8055                 return true;
8056         case EXIT_REASON_EPT_VIOLATION:
8057                 /*
8058                  * L0 always deals with the EPT violation. If nested EPT is
8059                  * used, and the nested mmu code discovers that the address is
8060                  * missing in the guest EPT table (EPT12), the EPT violation
8061                  * will be injected with nested_ept_inject_page_fault()
8062                  */
8063                 return false;
8064         case EXIT_REASON_EPT_MISCONFIG:
8065                 /*
8066                  * L2 never uses directly L1's EPT, but rather L0's own EPT
8067                  * table (shadow on EPT) or a merged EPT table that L0 built
8068                  * (EPT on EPT). So any problems with the structure of the
8069                  * table is L0's fault.
8070                  */
8071                 return false;
8072         case EXIT_REASON_WBINVD:
8073                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
8074         case EXIT_REASON_XSETBV:
8075                 return true;
8076         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
8077                 /*
8078                  * This should never happen, since it is not possible to
8079                  * set XSS to a non-zero value---neither in L1 nor in L2.
8080                  * If if it were, XSS would have to be checked against
8081                  * the XSS exit bitmap in vmcs12.
8082                  */
8083                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
8084         case EXIT_REASON_PCOMMIT:
8085                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_PCOMMIT);
8086         case EXIT_REASON_PREEMPTION_TIMER:
8087                 return false;
8088         default:
8089                 return true;
8090         }
8091 }
8092
8093 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
8094 {
8095         *info1 = vmcs_readl(EXIT_QUALIFICATION);
8096         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
8097 }
8098
8099 static int vmx_create_pml_buffer(struct vcpu_vmx *vmx)
8100 {
8101         struct page *pml_pg;
8102
8103         pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
8104         if (!pml_pg)
8105                 return -ENOMEM;
8106
8107         vmx->pml_pg = pml_pg;
8108
8109         vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
8110         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8111
8112         return 0;
8113 }
8114
8115 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
8116 {
8117         if (vmx->pml_pg) {
8118                 __free_page(vmx->pml_pg);
8119                 vmx->pml_pg = NULL;
8120         }
8121 }
8122
8123 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
8124 {
8125         struct vcpu_vmx *vmx = to_vmx(vcpu);
8126         u64 *pml_buf;
8127         u16 pml_idx;
8128
8129         pml_idx = vmcs_read16(GUEST_PML_INDEX);
8130
8131         /* Do nothing if PML buffer is empty */
8132         if (pml_idx == (PML_ENTITY_NUM - 1))
8133                 return;
8134
8135         /* PML index always points to next available PML buffer entity */
8136         if (pml_idx >= PML_ENTITY_NUM)
8137                 pml_idx = 0;
8138         else
8139                 pml_idx++;
8140
8141         pml_buf = page_address(vmx->pml_pg);
8142         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
8143                 u64 gpa;
8144
8145                 gpa = pml_buf[pml_idx];
8146                 WARN_ON(gpa & (PAGE_SIZE - 1));
8147                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
8148         }
8149
8150         /* reset PML index */
8151         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8152 }
8153
8154 /*
8155  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8156  * Called before reporting dirty_bitmap to userspace.
8157  */
8158 static void kvm_flush_pml_buffers(struct kvm *kvm)
8159 {
8160         int i;
8161         struct kvm_vcpu *vcpu;
8162         /*
8163          * We only need to kick vcpu out of guest mode here, as PML buffer
8164          * is flushed at beginning of all VMEXITs, and it's obvious that only
8165          * vcpus running in guest are possible to have unflushed GPAs in PML
8166          * buffer.
8167          */
8168         kvm_for_each_vcpu(i, vcpu, kvm)
8169                 kvm_vcpu_kick(vcpu);
8170 }
8171
8172 static void vmx_dump_sel(char *name, uint32_t sel)
8173 {
8174         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8175                name, vmcs_read32(sel),
8176                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8177                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8178                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8179 }
8180
8181 static void vmx_dump_dtsel(char *name, uint32_t limit)
8182 {
8183         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
8184                name, vmcs_read32(limit),
8185                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8186 }
8187
8188 static void dump_vmcs(void)
8189 {
8190         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8191         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8192         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8193         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8194         u32 secondary_exec_control = 0;
8195         unsigned long cr4 = vmcs_readl(GUEST_CR4);
8196         u64 efer = vmcs_read64(GUEST_IA32_EFER);
8197         int i, n;
8198
8199         if (cpu_has_secondary_exec_ctrls())
8200                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8201
8202         pr_err("*** Guest State ***\n");
8203         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8204                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8205                vmcs_readl(CR0_GUEST_HOST_MASK));
8206         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8207                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8208         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8209         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8210             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8211         {
8212                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
8213                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8214                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
8215                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
8216         }
8217         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
8218                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8219         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
8220                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8221         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8222                vmcs_readl(GUEST_SYSENTER_ESP),
8223                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8224         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
8225         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
8226         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
8227         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
8228         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
8229         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
8230         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8231         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8232         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8233         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
8234         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8235             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
8236                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
8237                        efer, vmcs_read64(GUEST_IA32_PAT));
8238         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
8239                vmcs_read64(GUEST_IA32_DEBUGCTL),
8240                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8241         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
8242                 pr_err("PerfGlobCtl = 0x%016llx\n",
8243                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
8244         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
8245                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
8246         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
8247                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8248                vmcs_read32(GUEST_ACTIVITY_STATE));
8249         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8250                 pr_err("InterruptStatus = %04x\n",
8251                        vmcs_read16(GUEST_INTR_STATUS));
8252
8253         pr_err("*** Host State ***\n");
8254         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
8255                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8256         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8257                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8258                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8259                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8260                vmcs_read16(HOST_TR_SELECTOR));
8261         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8262                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8263                vmcs_readl(HOST_TR_BASE));
8264         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8265                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8266         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8267                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8268                vmcs_readl(HOST_CR4));
8269         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8270                vmcs_readl(HOST_IA32_SYSENTER_ESP),
8271                vmcs_read32(HOST_IA32_SYSENTER_CS),
8272                vmcs_readl(HOST_IA32_SYSENTER_EIP));
8273         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8274                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
8275                        vmcs_read64(HOST_IA32_EFER),
8276                        vmcs_read64(HOST_IA32_PAT));
8277         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8278                 pr_err("PerfGlobCtl = 0x%016llx\n",
8279                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
8280
8281         pr_err("*** Control State ***\n");
8282         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8283                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8284         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8285         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8286                vmcs_read32(EXCEPTION_BITMAP),
8287                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8288                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8289         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8290                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8291                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8292                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8293         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8294                vmcs_read32(VM_EXIT_INTR_INFO),
8295                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8296                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8297         pr_err("        reason=%08x qualification=%016lx\n",
8298                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8299         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8300                vmcs_read32(IDT_VECTORING_INFO_FIELD),
8301                vmcs_read32(IDT_VECTORING_ERROR_CODE));
8302         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8303         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8304                 pr_err("TSC Multiplier = 0x%016llx\n",
8305                        vmcs_read64(TSC_MULTIPLIER));
8306         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8307                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8308         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8309                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8310         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8311                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8312         n = vmcs_read32(CR3_TARGET_COUNT);
8313         for (i = 0; i + 1 < n; i += 4)
8314                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8315                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8316                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8317         if (i < n)
8318                 pr_err("CR3 target%u=%016lx\n",
8319                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8320         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8321                 pr_err("PLE Gap=%08x Window=%08x\n",
8322                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8323         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8324                 pr_err("Virtual processor ID = 0x%04x\n",
8325                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
8326 }
8327
8328 /*
8329  * The guest has exited.  See if we can fix it or if we need userspace
8330  * assistance.
8331  */
8332 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8333 {
8334         struct vcpu_vmx *vmx = to_vmx(vcpu);
8335         u32 exit_reason = vmx->exit_reason;
8336         u32 vectoring_info = vmx->idt_vectoring_info;
8337
8338         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8339
8340         /*
8341          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8342          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8343          * querying dirty_bitmap, we only need to kick all vcpus out of guest
8344          * mode as if vcpus is in root mode, the PML buffer must has been
8345          * flushed already.
8346          */
8347         if (enable_pml)
8348                 vmx_flush_pml_buffer(vcpu);
8349
8350         /* If guest state is invalid, start emulating */
8351         if (vmx->emulation_required)
8352                 return handle_invalid_guest_state(vcpu);
8353
8354         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8355                 nested_vmx_vmexit(vcpu, exit_reason,
8356                                   vmcs_read32(VM_EXIT_INTR_INFO),
8357                                   vmcs_readl(EXIT_QUALIFICATION));
8358                 return 1;
8359         }
8360
8361         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8362                 dump_vmcs();
8363                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8364                 vcpu->run->fail_entry.hardware_entry_failure_reason
8365                         = exit_reason;
8366                 return 0;
8367         }
8368
8369         if (unlikely(vmx->fail)) {
8370                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8371                 vcpu->run->fail_entry.hardware_entry_failure_reason
8372                         = vmcs_read32(VM_INSTRUCTION_ERROR);
8373                 return 0;
8374         }
8375
8376         /*
8377          * Note:
8378          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8379          * delivery event since it indicates guest is accessing MMIO.
8380          * The vm-exit can be triggered again after return to guest that
8381          * will cause infinite loop.
8382          */
8383         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8384                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8385                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
8386                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
8387                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8388                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8389                 vcpu->run->internal.ndata = 2;
8390                 vcpu->run->internal.data[0] = vectoring_info;
8391                 vcpu->run->internal.data[1] = exit_reason;
8392                 return 0;
8393         }
8394
8395         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
8396             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
8397                                         get_vmcs12(vcpu))))) {
8398                 if (vmx_interrupt_allowed(vcpu)) {
8399                         vmx->soft_vnmi_blocked = 0;
8400                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
8401                            vcpu->arch.nmi_pending) {
8402                         /*
8403                          * This CPU don't support us in finding the end of an
8404                          * NMI-blocked window if the guest runs with IRQs
8405                          * disabled. So we pull the trigger after 1 s of
8406                          * futile waiting, but inform the user about this.
8407                          */
8408                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8409                                "state on VCPU %d after 1 s timeout\n",
8410                                __func__, vcpu->vcpu_id);
8411                         vmx->soft_vnmi_blocked = 0;
8412                 }
8413         }
8414
8415         if (exit_reason < kvm_vmx_max_exit_handlers
8416             && kvm_vmx_exit_handlers[exit_reason])
8417                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8418         else {
8419                 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
8420                 kvm_queue_exception(vcpu, UD_VECTOR);
8421                 return 1;
8422         }
8423 }
8424
8425 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8426 {
8427         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8428
8429         if (is_guest_mode(vcpu) &&
8430                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8431                 return;
8432
8433         if (irr == -1 || tpr < irr) {
8434                 vmcs_write32(TPR_THRESHOLD, 0);
8435                 return;
8436         }
8437
8438         vmcs_write32(TPR_THRESHOLD, irr);
8439 }
8440
8441 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8442 {
8443         u32 sec_exec_control;
8444
8445         /*
8446          * There is not point to enable virtualize x2apic without enable
8447          * apicv
8448          */
8449         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
8450                                 !kvm_vcpu_apicv_active(vcpu))
8451                 return;
8452
8453         if (!cpu_need_tpr_shadow(vcpu))
8454                 return;
8455
8456         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8457
8458         if (set) {
8459                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8460                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8461         } else {
8462                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8463                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8464         }
8465         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8466
8467         vmx_set_msr_bitmap(vcpu);
8468 }
8469
8470 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8471 {
8472         struct vcpu_vmx *vmx = to_vmx(vcpu);
8473
8474         /*
8475          * Currently we do not handle the nested case where L2 has an
8476          * APIC access page of its own; that page is still pinned.
8477          * Hence, we skip the case where the VCPU is in guest mode _and_
8478          * L1 prepared an APIC access page for L2.
8479          *
8480          * For the case where L1 and L2 share the same APIC access page
8481          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8482          * in the vmcs12), this function will only update either the vmcs01
8483          * or the vmcs02.  If the former, the vmcs02 will be updated by
8484          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
8485          * the next L2->L1 exit.
8486          */
8487         if (!is_guest_mode(vcpu) ||
8488             !nested_cpu_has2(get_vmcs12(&vmx->vcpu),
8489                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8490                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8491 }
8492
8493 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
8494 {
8495         u16 status;
8496         u8 old;
8497
8498         if (max_isr == -1)
8499                 max_isr = 0;
8500
8501         status = vmcs_read16(GUEST_INTR_STATUS);
8502         old = status >> 8;
8503         if (max_isr != old) {
8504                 status &= 0xff;
8505                 status |= max_isr << 8;
8506                 vmcs_write16(GUEST_INTR_STATUS, status);
8507         }
8508 }
8509
8510 static void vmx_set_rvi(int vector)
8511 {
8512         u16 status;
8513         u8 old;
8514
8515         if (vector == -1)
8516                 vector = 0;
8517
8518         status = vmcs_read16(GUEST_INTR_STATUS);
8519         old = (u8)status & 0xff;
8520         if ((u8)vector != old) {
8521                 status &= ~0xff;
8522                 status |= (u8)vector;
8523                 vmcs_write16(GUEST_INTR_STATUS, status);
8524         }
8525 }
8526
8527 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8528 {
8529         if (!is_guest_mode(vcpu)) {
8530                 vmx_set_rvi(max_irr);
8531                 return;
8532         }
8533
8534         if (max_irr == -1)
8535                 return;
8536
8537         /*
8538          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
8539          * handles it.
8540          */
8541         if (nested_exit_on_intr(vcpu))
8542                 return;
8543
8544         /*
8545          * Else, fall back to pre-APICv interrupt injection since L2
8546          * is run without virtual interrupt delivery.
8547          */
8548         if (!kvm_event_needs_reinjection(vcpu) &&
8549             vmx_interrupt_allowed(vcpu)) {
8550                 kvm_queue_interrupt(vcpu, max_irr, false);
8551                 vmx_inject_irq(vcpu);
8552         }
8553 }
8554
8555 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
8556 {
8557         if (!kvm_vcpu_apicv_active(vcpu))
8558                 return;
8559
8560         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8561         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8562         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8563         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8564 }
8565
8566 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8567 {
8568         u32 exit_intr_info;
8569
8570         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8571               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8572                 return;
8573
8574         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8575         exit_intr_info = vmx->exit_intr_info;
8576
8577         /* Handle machine checks before interrupts are enabled */
8578         if (is_machine_check(exit_intr_info))
8579                 kvm_machine_check();
8580
8581         /* We need to handle NMIs before interrupts are enabled */
8582         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
8583             (exit_intr_info & INTR_INFO_VALID_MASK)) {
8584                 kvm_before_handle_nmi(&vmx->vcpu);
8585                 asm("int $2");
8586                 kvm_after_handle_nmi(&vmx->vcpu);
8587         }
8588 }
8589
8590 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8591 {
8592         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8593         register void *__sp asm(_ASM_SP);
8594
8595         /*
8596          * If external interrupt exists, IF bit is set in rflags/eflags on the
8597          * interrupt stack frame, and interrupt will be enabled on a return
8598          * from interrupt handler.
8599          */
8600         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8601                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8602                 unsigned int vector;
8603                 unsigned long entry;
8604                 gate_desc *desc;
8605                 struct vcpu_vmx *vmx = to_vmx(vcpu);
8606 #ifdef CONFIG_X86_64
8607                 unsigned long tmp;
8608 #endif
8609
8610                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
8611                 desc = (gate_desc *)vmx->host_idt_base + vector;
8612                 entry = gate_offset(*desc);
8613                 asm volatile(
8614 #ifdef CONFIG_X86_64
8615                         "mov %%" _ASM_SP ", %[sp]\n\t"
8616                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8617                         "push $%c[ss]\n\t"
8618                         "push %[sp]\n\t"
8619 #endif
8620                         "pushf\n\t"
8621                         __ASM_SIZE(push) " $%c[cs]\n\t"
8622                         "call *%[entry]\n\t"
8623                         :
8624 #ifdef CONFIG_X86_64
8625                         [sp]"=&r"(tmp),
8626 #endif
8627                         "+r"(__sp)
8628                         :
8629                         [entry]"r"(entry),
8630                         [ss]"i"(__KERNEL_DS),
8631                         [cs]"i"(__KERNEL_CS)
8632                         );
8633         }
8634 }
8635
8636 static bool vmx_has_high_real_mode_segbase(void)
8637 {
8638         return enable_unrestricted_guest || emulate_invalid_guest_state;
8639 }
8640
8641 static bool vmx_mpx_supported(void)
8642 {
8643         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8644                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8645 }
8646
8647 static bool vmx_xsaves_supported(void)
8648 {
8649         return vmcs_config.cpu_based_2nd_exec_ctrl &
8650                 SECONDARY_EXEC_XSAVES;
8651 }
8652
8653 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8654 {
8655         u32 exit_intr_info;
8656         bool unblock_nmi;
8657         u8 vector;
8658         bool idtv_info_valid;
8659
8660         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8661
8662         if (cpu_has_virtual_nmis()) {
8663                 if (vmx->nmi_known_unmasked)
8664                         return;
8665                 /*
8666                  * Can't use vmx->exit_intr_info since we're not sure what
8667                  * the exit reason is.
8668                  */
8669                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8670                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8671                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8672                 /*
8673                  * SDM 3: 27.7.1.2 (September 2008)
8674                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
8675                  * a guest IRET fault.
8676                  * SDM 3: 23.2.2 (September 2008)
8677                  * Bit 12 is undefined in any of the following cases:
8678                  *  If the VM exit sets the valid bit in the IDT-vectoring
8679                  *   information field.
8680                  *  If the VM exit is due to a double fault.
8681                  */
8682                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8683                     vector != DF_VECTOR && !idtv_info_valid)
8684                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8685                                       GUEST_INTR_STATE_NMI);
8686                 else
8687                         vmx->nmi_known_unmasked =
8688                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8689                                   & GUEST_INTR_STATE_NMI);
8690         } else if (unlikely(vmx->soft_vnmi_blocked))
8691                 vmx->vnmi_blocked_time +=
8692                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8693 }
8694
8695 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8696                                       u32 idt_vectoring_info,
8697                                       int instr_len_field,
8698                                       int error_code_field)
8699 {
8700         u8 vector;
8701         int type;
8702         bool idtv_info_valid;
8703
8704         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8705
8706         vcpu->arch.nmi_injected = false;
8707         kvm_clear_exception_queue(vcpu);
8708         kvm_clear_interrupt_queue(vcpu);
8709
8710         if (!idtv_info_valid)
8711                 return;
8712
8713         kvm_make_request(KVM_REQ_EVENT, vcpu);
8714
8715         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8716         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8717
8718         switch (type) {
8719         case INTR_TYPE_NMI_INTR:
8720                 vcpu->arch.nmi_injected = true;
8721                 /*
8722                  * SDM 3: 27.7.1.2 (September 2008)
8723                  * Clear bit "block by NMI" before VM entry if a NMI
8724                  * delivery faulted.
8725                  */
8726                 vmx_set_nmi_mask(vcpu, false);
8727                 break;
8728         case INTR_TYPE_SOFT_EXCEPTION:
8729                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8730                 /* fall through */
8731         case INTR_TYPE_HARD_EXCEPTION:
8732                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8733                         u32 err = vmcs_read32(error_code_field);
8734                         kvm_requeue_exception_e(vcpu, vector, err);
8735                 } else
8736                         kvm_requeue_exception(vcpu, vector);
8737                 break;
8738         case INTR_TYPE_SOFT_INTR:
8739                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8740                 /* fall through */
8741         case INTR_TYPE_EXT_INTR:
8742                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8743                 break;
8744         default:
8745                 break;
8746         }
8747 }
8748
8749 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8750 {
8751         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8752                                   VM_EXIT_INSTRUCTION_LEN,
8753                                   IDT_VECTORING_ERROR_CODE);
8754 }
8755
8756 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8757 {
8758         __vmx_complete_interrupts(vcpu,
8759                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8760                                   VM_ENTRY_INSTRUCTION_LEN,
8761                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
8762
8763         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8764 }
8765
8766 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8767 {
8768         int i, nr_msrs;
8769         struct perf_guest_switch_msr *msrs;
8770
8771         msrs = perf_guest_get_msrs(&nr_msrs);
8772
8773         if (!msrs)
8774                 return;
8775
8776         for (i = 0; i < nr_msrs; i++)
8777                 if (msrs[i].host == msrs[i].guest)
8778                         clear_atomic_switch_msr(vmx, msrs[i].msr);
8779                 else
8780                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8781                                         msrs[i].host);
8782 }
8783
8784 void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
8785 {
8786         struct vcpu_vmx *vmx = to_vmx(vcpu);
8787         u64 tscl;
8788         u32 delta_tsc;
8789
8790         if (vmx->hv_deadline_tsc == -1)
8791                 return;
8792
8793         tscl = rdtsc();
8794         if (vmx->hv_deadline_tsc > tscl)
8795                 /* sure to be 32 bit only because checked on set_hv_timer */
8796                 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
8797                         cpu_preemption_timer_multi);
8798         else
8799                 delta_tsc = 0;
8800
8801         vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
8802 }
8803
8804 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8805 {
8806         struct vcpu_vmx *vmx = to_vmx(vcpu);
8807         unsigned long debugctlmsr, cr4;
8808
8809         /* Record the guest's net vcpu time for enforced NMI injections. */
8810         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8811                 vmx->entry_time = ktime_get();
8812
8813         /* Don't enter VMX if guest state is invalid, let the exit handler
8814            start emulation until we arrive back to a valid state */
8815         if (vmx->emulation_required)
8816                 return;
8817
8818         if (vmx->ple_window_dirty) {
8819                 vmx->ple_window_dirty = false;
8820                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8821         }
8822
8823         if (vmx->nested.sync_shadow_vmcs) {
8824                 copy_vmcs12_to_shadow(vmx);
8825                 vmx->nested.sync_shadow_vmcs = false;
8826         }
8827
8828         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8829                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8830         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8831                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8832
8833         cr4 = cr4_read_shadow();
8834         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8835                 vmcs_writel(HOST_CR4, cr4);
8836                 vmx->host_state.vmcs_host_cr4 = cr4;
8837         }
8838
8839         /* When single-stepping over STI and MOV SS, we must clear the
8840          * corresponding interruptibility bits in the guest state. Otherwise
8841          * vmentry fails as it then expects bit 14 (BS) in pending debug
8842          * exceptions being set, but that's not correct for the guest debugging
8843          * case. */
8844         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8845                 vmx_set_interrupt_shadow(vcpu, 0);
8846
8847         if (vmx->guest_pkru_valid)
8848                 __write_pkru(vmx->guest_pkru);
8849
8850         atomic_switch_perf_msrs(vmx);
8851         debugctlmsr = get_debugctlmsr();
8852
8853         vmx_arm_hv_timer(vcpu);
8854
8855         vmx->__launched = vmx->loaded_vmcs->launched;
8856         asm(
8857                 /* Store host registers */
8858                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8859                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8860                 "push %%" _ASM_CX " \n\t"
8861                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8862                 "je 1f \n\t"
8863                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8864                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8865                 "1: \n\t"
8866                 /* Reload cr2 if changed */
8867                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8868                 "mov %%cr2, %%" _ASM_DX " \n\t"
8869                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8870                 "je 2f \n\t"
8871                 "mov %%" _ASM_AX", %%cr2 \n\t"
8872                 "2: \n\t"
8873                 /* Check if vmlaunch of vmresume is needed */
8874                 "cmpl $0, %c[launched](%0) \n\t"
8875                 /* Load guest registers.  Don't clobber flags. */
8876                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8877                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8878                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8879                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8880                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8881                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8882 #ifdef CONFIG_X86_64
8883                 "mov %c[r8](%0),  %%r8  \n\t"
8884                 "mov %c[r9](%0),  %%r9  \n\t"
8885                 "mov %c[r10](%0), %%r10 \n\t"
8886                 "mov %c[r11](%0), %%r11 \n\t"
8887                 "mov %c[r12](%0), %%r12 \n\t"
8888                 "mov %c[r13](%0), %%r13 \n\t"
8889                 "mov %c[r14](%0), %%r14 \n\t"
8890                 "mov %c[r15](%0), %%r15 \n\t"
8891 #endif
8892                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8893
8894                 /* Enter guest mode */
8895                 "jne 1f \n\t"
8896                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8897                 "jmp 2f \n\t"
8898                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8899                 "2: "
8900                 /* Save guest registers, load host registers, keep flags */
8901                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8902                 "pop %0 \n\t"
8903                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8904                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8905                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8906                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8907                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8908                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8909                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8910 #ifdef CONFIG_X86_64
8911                 "mov %%r8,  %c[r8](%0) \n\t"
8912                 "mov %%r9,  %c[r9](%0) \n\t"
8913                 "mov %%r10, %c[r10](%0) \n\t"
8914                 "mov %%r11, %c[r11](%0) \n\t"
8915                 "mov %%r12, %c[r12](%0) \n\t"
8916                 "mov %%r13, %c[r13](%0) \n\t"
8917                 "mov %%r14, %c[r14](%0) \n\t"
8918                 "mov %%r15, %c[r15](%0) \n\t"
8919 #endif
8920                 "mov %%cr2, %%" _ASM_AX "   \n\t"
8921                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
8922
8923                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
8924                 "setbe %c[fail](%0) \n\t"
8925                 ".pushsection .rodata \n\t"
8926                 ".global vmx_return \n\t"
8927                 "vmx_return: " _ASM_PTR " 2b \n\t"
8928                 ".popsection"
8929               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
8930                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
8931                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
8932                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
8933                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8934                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8935                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8936                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8937                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8938                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8939                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
8940 #ifdef CONFIG_X86_64
8941                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8942                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8943                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8944                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8945                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8946                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8947                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8948                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
8949 #endif
8950                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8951                 [wordsize]"i"(sizeof(ulong))
8952               : "cc", "memory"
8953 #ifdef CONFIG_X86_64
8954                 , "rax", "rbx", "rdi", "rsi"
8955                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8956 #else
8957                 , "eax", "ebx", "edi", "esi"
8958 #endif
8959               );
8960
8961         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8962         if (debugctlmsr)
8963                 update_debugctlmsr(debugctlmsr);
8964
8965 #ifndef CONFIG_X86_64
8966         /*
8967          * The sysexit path does not restore ds/es, so we must set them to
8968          * a reasonable value ourselves.
8969          *
8970          * We can't defer this to vmx_load_host_state() since that function
8971          * may be executed in interrupt context, which saves and restore segments
8972          * around it, nullifying its effect.
8973          */
8974         loadsegment(ds, __USER_DS);
8975         loadsegment(es, __USER_DS);
8976 #endif
8977
8978         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
8979                                   | (1 << VCPU_EXREG_RFLAGS)
8980                                   | (1 << VCPU_EXREG_PDPTR)
8981                                   | (1 << VCPU_EXREG_SEGMENTS)
8982                                   | (1 << VCPU_EXREG_CR3));
8983         vcpu->arch.regs_dirty = 0;
8984
8985         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8986
8987         vmx->loaded_vmcs->launched = 1;
8988
8989         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
8990
8991         /*
8992          * eager fpu is enabled if PKEY is supported and CR4 is switched
8993          * back on host, so it is safe to read guest PKRU from current
8994          * XSAVE.
8995          */
8996         if (boot_cpu_has(X86_FEATURE_OSPKE)) {
8997                 vmx->guest_pkru = __read_pkru();
8998                 if (vmx->guest_pkru != vmx->host_pkru) {
8999                         vmx->guest_pkru_valid = true;
9000                         __write_pkru(vmx->host_pkru);
9001                 } else
9002                         vmx->guest_pkru_valid = false;
9003         }
9004
9005         /*
9006          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9007          * we did not inject a still-pending event to L1 now because of
9008          * nested_run_pending, we need to re-enable this bit.
9009          */
9010         if (vmx->nested.nested_run_pending)
9011                 kvm_make_request(KVM_REQ_EVENT, vcpu);
9012
9013         vmx->nested.nested_run_pending = 0;
9014
9015         vmx_complete_atomic_exit(vmx);
9016         vmx_recover_nmi_blocking(vmx);
9017         vmx_complete_interrupts(vmx);
9018 }
9019
9020 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
9021 {
9022         struct vcpu_vmx *vmx = to_vmx(vcpu);
9023         int cpu;
9024
9025         if (vmx->loaded_vmcs == &vmx->vmcs01)
9026                 return;
9027
9028         cpu = get_cpu();
9029         vmx->loaded_vmcs = &vmx->vmcs01;
9030         vmx_vcpu_put(vcpu);
9031         vmx_vcpu_load(vcpu, cpu);
9032         vcpu->cpu = cpu;
9033         put_cpu();
9034 }
9035
9036 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
9037 {
9038         struct vcpu_vmx *vmx = to_vmx(vcpu);
9039
9040         if (enable_pml)
9041                 vmx_destroy_pml_buffer(vmx);
9042         free_vpid(vmx->vpid);
9043         leave_guest_mode(vcpu);
9044         vmx_load_vmcs01(vcpu);
9045         free_nested(vmx);
9046         free_loaded_vmcs(vmx->loaded_vmcs);
9047         kfree(vmx->guest_msrs);
9048         kvm_vcpu_uninit(vcpu);
9049         kmem_cache_free(kvm_vcpu_cache, vmx);
9050 }
9051
9052 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
9053 {
9054         int err;
9055         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
9056         int cpu;
9057
9058         if (!vmx)
9059                 return ERR_PTR(-ENOMEM);
9060
9061         vmx->vpid = allocate_vpid();
9062
9063         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
9064         if (err)
9065                 goto free_vcpu;
9066
9067         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
9068         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
9069                      > PAGE_SIZE);
9070
9071         err = -ENOMEM;
9072         if (!vmx->guest_msrs) {
9073                 goto uninit_vcpu;
9074         }
9075
9076         vmx->loaded_vmcs = &vmx->vmcs01;
9077         vmx->loaded_vmcs->vmcs = alloc_vmcs();
9078         if (!vmx->loaded_vmcs->vmcs)
9079                 goto free_msrs;
9080         if (!vmm_exclusive)
9081                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
9082         loaded_vmcs_init(vmx->loaded_vmcs);
9083         if (!vmm_exclusive)
9084                 kvm_cpu_vmxoff();
9085
9086         cpu = get_cpu();
9087         vmx_vcpu_load(&vmx->vcpu, cpu);
9088         vmx->vcpu.cpu = cpu;
9089         err = vmx_vcpu_setup(vmx);
9090         vmx_vcpu_put(&vmx->vcpu);
9091         put_cpu();
9092         if (err)
9093                 goto free_vmcs;
9094         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9095                 err = alloc_apic_access_page(kvm);
9096                 if (err)
9097                         goto free_vmcs;
9098         }
9099
9100         if (enable_ept) {
9101                 if (!kvm->arch.ept_identity_map_addr)
9102                         kvm->arch.ept_identity_map_addr =
9103                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
9104                 err = init_rmode_identity_map(kvm);
9105                 if (err)
9106                         goto free_vmcs;
9107         }
9108
9109         if (nested) {
9110                 nested_vmx_setup_ctls_msrs(vmx);
9111                 vmx->nested.vpid02 = allocate_vpid();
9112         }
9113
9114         vmx->nested.posted_intr_nv = -1;
9115         vmx->nested.current_vmptr = -1ull;
9116         vmx->nested.current_vmcs12 = NULL;
9117
9118         /*
9119          * If PML is turned on, failure on enabling PML just results in failure
9120          * of creating the vcpu, therefore we can simplify PML logic (by
9121          * avoiding dealing with cases, such as enabling PML partially on vcpus
9122          * for the guest, etc.
9123          */
9124         if (enable_pml) {
9125                 err = vmx_create_pml_buffer(vmx);
9126                 if (err)
9127                         goto free_vmcs;
9128         }
9129
9130         vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
9131
9132         return &vmx->vcpu;
9133
9134 free_vmcs:
9135         free_vpid(vmx->nested.vpid02);
9136         free_loaded_vmcs(vmx->loaded_vmcs);
9137 free_msrs:
9138         kfree(vmx->guest_msrs);
9139 uninit_vcpu:
9140         kvm_vcpu_uninit(&vmx->vcpu);
9141 free_vcpu:
9142         free_vpid(vmx->vpid);
9143         kmem_cache_free(kvm_vcpu_cache, vmx);
9144         return ERR_PTR(err);
9145 }
9146
9147 static void __init vmx_check_processor_compat(void *rtn)
9148 {
9149         struct vmcs_config vmcs_conf;
9150
9151         *(int *)rtn = 0;
9152         if (setup_vmcs_config(&vmcs_conf) < 0)
9153                 *(int *)rtn = -EIO;
9154         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
9155                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
9156                                 smp_processor_id());
9157                 *(int *)rtn = -EIO;
9158         }
9159 }
9160
9161 static int get_ept_level(void)
9162 {
9163         return VMX_EPT_DEFAULT_GAW + 1;
9164 }
9165
9166 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
9167 {
9168         u8 cache;
9169         u64 ipat = 0;
9170
9171         /* For VT-d and EPT combination
9172          * 1. MMIO: always map as UC
9173          * 2. EPT with VT-d:
9174          *   a. VT-d without snooping control feature: can't guarantee the
9175          *      result, try to trust guest.
9176          *   b. VT-d with snooping control feature: snooping control feature of
9177          *      VT-d engine can guarantee the cache correctness. Just set it
9178          *      to WB to keep consistent with host. So the same as item 3.
9179          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9180          *    consistent with host MTRR
9181          */
9182         if (is_mmio) {
9183                 cache = MTRR_TYPE_UNCACHABLE;
9184                 goto exit;
9185         }
9186
9187         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
9188                 ipat = VMX_EPT_IPAT_BIT;
9189                 cache = MTRR_TYPE_WRBACK;
9190                 goto exit;
9191         }
9192
9193         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
9194                 ipat = VMX_EPT_IPAT_BIT;
9195                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
9196                         cache = MTRR_TYPE_WRBACK;
9197                 else
9198                         cache = MTRR_TYPE_UNCACHABLE;
9199                 goto exit;
9200         }
9201
9202         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
9203
9204 exit:
9205         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
9206 }
9207
9208 static int vmx_get_lpage_level(void)
9209 {
9210         if (enable_ept && !cpu_has_vmx_ept_1g_page())
9211                 return PT_DIRECTORY_LEVEL;
9212         else
9213                 /* For shadow and EPT supported 1GB page */
9214                 return PT_PDPE_LEVEL;
9215 }
9216
9217 static void vmcs_set_secondary_exec_control(u32 new_ctl)
9218 {
9219         /*
9220          * These bits in the secondary execution controls field
9221          * are dynamic, the others are mostly based on the hypervisor
9222          * architecture and the guest's CPUID.  Do not touch the
9223          * dynamic bits.
9224          */
9225         u32 mask =
9226                 SECONDARY_EXEC_SHADOW_VMCS |
9227                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9228                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9229
9230         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9231
9232         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9233                      (new_ctl & ~mask) | (cur_ctl & mask));
9234 }
9235
9236 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9237 {
9238         struct kvm_cpuid_entry2 *best;
9239         struct vcpu_vmx *vmx = to_vmx(vcpu);
9240         u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
9241
9242         if (vmx_rdtscp_supported()) {
9243                 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
9244                 if (!rdtscp_enabled)
9245                         secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
9246
9247                 if (nested) {
9248                         if (rdtscp_enabled)
9249                                 vmx->nested.nested_vmx_secondary_ctls_high |=
9250                                         SECONDARY_EXEC_RDTSCP;
9251                         else
9252                                 vmx->nested.nested_vmx_secondary_ctls_high &=
9253                                         ~SECONDARY_EXEC_RDTSCP;
9254                 }
9255         }
9256
9257         /* Exposing INVPCID only when PCID is exposed */
9258         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9259         if (vmx_invpcid_supported() &&
9260             (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
9261             !guest_cpuid_has_pcid(vcpu))) {
9262                 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
9263
9264                 if (best)
9265                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
9266         }
9267
9268         if (cpu_has_secondary_exec_ctrls())
9269                 vmcs_set_secondary_exec_control(secondary_exec_ctl);
9270
9271         if (static_cpu_has(X86_FEATURE_PCOMMIT) && nested) {
9272                 if (guest_cpuid_has_pcommit(vcpu))
9273                         vmx->nested.nested_vmx_secondary_ctls_high |=
9274                                 SECONDARY_EXEC_PCOMMIT;
9275                 else
9276                         vmx->nested.nested_vmx_secondary_ctls_high &=
9277                                 ~SECONDARY_EXEC_PCOMMIT;
9278         }
9279
9280         if (nested_vmx_allowed(vcpu))
9281                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
9282                         FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9283         else
9284                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
9285                         ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9286 }
9287
9288 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9289 {
9290         if (func == 1 && nested)
9291                 entry->ecx |= bit(X86_FEATURE_VMX);
9292 }
9293
9294 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9295                 struct x86_exception *fault)
9296 {
9297         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9298         u32 exit_reason;
9299
9300         if (fault->error_code & PFERR_RSVD_MASK)
9301                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9302         else
9303                 exit_reason = EXIT_REASON_EPT_VIOLATION;
9304         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
9305         vmcs12->guest_physical_address = fault->address;
9306 }
9307
9308 /* Callbacks for nested_ept_init_mmu_context: */
9309
9310 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9311 {
9312         /* return the page table to be shadowed - in our case, EPT12 */
9313         return get_vmcs12(vcpu)->ept_pointer;
9314 }
9315
9316 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9317 {
9318         WARN_ON(mmu_is_nested(vcpu));
9319         kvm_init_shadow_ept_mmu(vcpu,
9320                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9321                         VMX_EPT_EXECUTE_ONLY_BIT);
9322         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
9323         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
9324         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9325
9326         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
9327 }
9328
9329 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9330 {
9331         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9332 }
9333
9334 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9335                                             u16 error_code)
9336 {
9337         bool inequality, bit;
9338
9339         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9340         inequality =
9341                 (error_code & vmcs12->page_fault_error_code_mask) !=
9342                  vmcs12->page_fault_error_code_match;
9343         return inequality ^ bit;
9344 }
9345
9346 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9347                 struct x86_exception *fault)
9348 {
9349         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9350
9351         WARN_ON(!is_guest_mode(vcpu));
9352
9353         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9354                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9355                                   vmcs_read32(VM_EXIT_INTR_INFO),
9356                                   vmcs_readl(EXIT_QUALIFICATION));
9357         else
9358                 kvm_inject_page_fault(vcpu, fault);
9359 }
9360
9361 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9362                                         struct vmcs12 *vmcs12)
9363 {
9364         struct vcpu_vmx *vmx = to_vmx(vcpu);
9365         int maxphyaddr = cpuid_maxphyaddr(vcpu);
9366
9367         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9368                 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
9369                     vmcs12->apic_access_addr >> maxphyaddr)
9370                         return false;
9371
9372                 /*
9373                  * Translate L1 physical address to host physical
9374                  * address for vmcs02. Keep the page pinned, so this
9375                  * physical address remains valid. We keep a reference
9376                  * to it so we can release it later.
9377                  */
9378                 if (vmx->nested.apic_access_page) /* shouldn't happen */
9379                         nested_release_page(vmx->nested.apic_access_page);
9380                 vmx->nested.apic_access_page =
9381                         nested_get_page(vcpu, vmcs12->apic_access_addr);
9382         }
9383
9384         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9385                 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
9386                     vmcs12->virtual_apic_page_addr >> maxphyaddr)
9387                         return false;
9388
9389                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9390                         nested_release_page(vmx->nested.virtual_apic_page);
9391                 vmx->nested.virtual_apic_page =
9392                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9393
9394                 /*
9395                  * Failing the vm entry is _not_ what the processor does
9396                  * but it's basically the only possibility we have.
9397                  * We could still enter the guest if CR8 load exits are
9398                  * enabled, CR8 store exits are enabled, and virtualize APIC
9399                  * access is disabled; in this case the processor would never
9400                  * use the TPR shadow and we could simply clear the bit from
9401                  * the execution control.  But such a configuration is useless,
9402                  * so let's keep the code simple.
9403                  */
9404                 if (!vmx->nested.virtual_apic_page)
9405                         return false;
9406         }
9407
9408         if (nested_cpu_has_posted_intr(vmcs12)) {
9409                 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
9410                     vmcs12->posted_intr_desc_addr >> maxphyaddr)
9411                         return false;
9412
9413                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9414                         kunmap(vmx->nested.pi_desc_page);
9415                         nested_release_page(vmx->nested.pi_desc_page);
9416                 }
9417                 vmx->nested.pi_desc_page =
9418                         nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9419                 if (!vmx->nested.pi_desc_page)
9420                         return false;
9421
9422                 vmx->nested.pi_desc =
9423                         (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9424                 if (!vmx->nested.pi_desc) {
9425                         nested_release_page_clean(vmx->nested.pi_desc_page);
9426                         return false;
9427                 }
9428                 vmx->nested.pi_desc =
9429                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
9430                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9431                         (PAGE_SIZE - 1)));
9432         }
9433
9434         return true;
9435 }
9436
9437 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9438 {
9439         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9440         struct vcpu_vmx *vmx = to_vmx(vcpu);
9441
9442         if (vcpu->arch.virtual_tsc_khz == 0)
9443                 return;
9444
9445         /* Make sure short timeouts reliably trigger an immediate vmexit.
9446          * hrtimer_start does not guarantee this. */
9447         if (preemption_timeout <= 1) {
9448                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9449                 return;
9450         }
9451
9452         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9453         preemption_timeout *= 1000000;
9454         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9455         hrtimer_start(&vmx->nested.preemption_timer,
9456                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9457 }
9458
9459 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9460                                                 struct vmcs12 *vmcs12)
9461 {
9462         int maxphyaddr;
9463         u64 addr;
9464
9465         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9466                 return 0;
9467
9468         if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9469                 WARN_ON(1);
9470                 return -EINVAL;
9471         }
9472         maxphyaddr = cpuid_maxphyaddr(vcpu);
9473
9474         if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9475            ((addr + PAGE_SIZE) >> maxphyaddr))
9476                 return -EINVAL;
9477
9478         return 0;
9479 }
9480
9481 /*
9482  * Merge L0's and L1's MSR bitmap, return false to indicate that
9483  * we do not use the hardware.
9484  */
9485 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9486                                                struct vmcs12 *vmcs12)
9487 {
9488         int msr;
9489         struct page *page;
9490         unsigned long *msr_bitmap;
9491
9492         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9493                 return false;
9494
9495         page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9496         if (!page) {
9497                 WARN_ON(1);
9498                 return false;
9499         }
9500         msr_bitmap = (unsigned long *)kmap(page);
9501         if (!msr_bitmap) {
9502                 nested_release_page_clean(page);
9503                 WARN_ON(1);
9504                 return false;
9505         }
9506
9507         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9508                 if (nested_cpu_has_apic_reg_virt(vmcs12))
9509                         for (msr = 0x800; msr <= 0x8ff; msr++)
9510                                 nested_vmx_disable_intercept_for_msr(
9511                                         msr_bitmap,
9512                                         vmx_msr_bitmap_nested,
9513                                         msr, MSR_TYPE_R);
9514                 /* TPR is allowed */
9515                 nested_vmx_disable_intercept_for_msr(msr_bitmap,
9516                                 vmx_msr_bitmap_nested,
9517                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9518                                 MSR_TYPE_R | MSR_TYPE_W);
9519                 if (nested_cpu_has_vid(vmcs12)) {
9520                         /* EOI and self-IPI are allowed */
9521                         nested_vmx_disable_intercept_for_msr(
9522                                 msr_bitmap,
9523                                 vmx_msr_bitmap_nested,
9524                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9525                                 MSR_TYPE_W);
9526                         nested_vmx_disable_intercept_for_msr(
9527                                 msr_bitmap,
9528                                 vmx_msr_bitmap_nested,
9529                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9530                                 MSR_TYPE_W);
9531                 }
9532         } else {
9533                 /*
9534                  * Enable reading intercept of all the x2apic
9535                  * MSRs. We should not rely on vmcs12 to do any
9536                  * optimizations here, it may have been modified
9537                  * by L1.
9538                  */
9539                 for (msr = 0x800; msr <= 0x8ff; msr++)
9540                         __vmx_enable_intercept_for_msr(
9541                                 vmx_msr_bitmap_nested,
9542                                 msr,
9543                                 MSR_TYPE_R);
9544
9545                 __vmx_enable_intercept_for_msr(
9546                                 vmx_msr_bitmap_nested,
9547                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9548                                 MSR_TYPE_W);
9549                 __vmx_enable_intercept_for_msr(
9550                                 vmx_msr_bitmap_nested,
9551                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9552                                 MSR_TYPE_W);
9553                 __vmx_enable_intercept_for_msr(
9554                                 vmx_msr_bitmap_nested,
9555                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9556                                 MSR_TYPE_W);
9557         }
9558         kunmap(page);
9559         nested_release_page_clean(page);
9560
9561         return true;
9562 }
9563
9564 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9565                                            struct vmcs12 *vmcs12)
9566 {
9567         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9568             !nested_cpu_has_apic_reg_virt(vmcs12) &&
9569             !nested_cpu_has_vid(vmcs12) &&
9570             !nested_cpu_has_posted_intr(vmcs12))
9571                 return 0;
9572
9573         /*
9574          * If virtualize x2apic mode is enabled,
9575          * virtualize apic access must be disabled.
9576          */
9577         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9578             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9579                 return -EINVAL;
9580
9581         /*
9582          * If virtual interrupt delivery is enabled,
9583          * we must exit on external interrupts.
9584          */
9585         if (nested_cpu_has_vid(vmcs12) &&
9586            !nested_exit_on_intr(vcpu))
9587                 return -EINVAL;
9588
9589         /*
9590          * bits 15:8 should be zero in posted_intr_nv,
9591          * the descriptor address has been already checked
9592          * in nested_get_vmcs12_pages.
9593          */
9594         if (nested_cpu_has_posted_intr(vmcs12) &&
9595            (!nested_cpu_has_vid(vmcs12) ||
9596             !nested_exit_intr_ack_set(vcpu) ||
9597             vmcs12->posted_intr_nv & 0xff00))
9598                 return -EINVAL;
9599
9600         /* tpr shadow is needed by all apicv features. */
9601         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9602                 return -EINVAL;
9603
9604         return 0;
9605 }
9606
9607 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9608                                        unsigned long count_field,
9609                                        unsigned long addr_field)
9610 {
9611         int maxphyaddr;
9612         u64 count, addr;
9613
9614         if (vmcs12_read_any(vcpu, count_field, &count) ||
9615             vmcs12_read_any(vcpu, addr_field, &addr)) {
9616                 WARN_ON(1);
9617                 return -EINVAL;
9618         }
9619         if (count == 0)
9620                 return 0;
9621         maxphyaddr = cpuid_maxphyaddr(vcpu);
9622         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9623             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9624                 pr_warn_ratelimited(
9625                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9626                         addr_field, maxphyaddr, count, addr);
9627                 return -EINVAL;
9628         }
9629         return 0;
9630 }
9631
9632 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9633                                                 struct vmcs12 *vmcs12)
9634 {
9635         if (vmcs12->vm_exit_msr_load_count == 0 &&
9636             vmcs12->vm_exit_msr_store_count == 0 &&
9637             vmcs12->vm_entry_msr_load_count == 0)
9638                 return 0; /* Fast path */
9639         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9640                                         VM_EXIT_MSR_LOAD_ADDR) ||
9641             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9642                                         VM_EXIT_MSR_STORE_ADDR) ||
9643             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9644                                         VM_ENTRY_MSR_LOAD_ADDR))
9645                 return -EINVAL;
9646         return 0;
9647 }
9648
9649 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9650                                        struct vmx_msr_entry *e)
9651 {
9652         /* x2APIC MSR accesses are not allowed */
9653         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9654                 return -EINVAL;
9655         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9656             e->index == MSR_IA32_UCODE_REV)
9657                 return -EINVAL;
9658         if (e->reserved != 0)
9659                 return -EINVAL;
9660         return 0;
9661 }
9662
9663 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9664                                      struct vmx_msr_entry *e)
9665 {
9666         if (e->index == MSR_FS_BASE ||
9667             e->index == MSR_GS_BASE ||
9668             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9669             nested_vmx_msr_check_common(vcpu, e))
9670                 return -EINVAL;
9671         return 0;
9672 }
9673
9674 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9675                                       struct vmx_msr_entry *e)
9676 {
9677         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9678             nested_vmx_msr_check_common(vcpu, e))
9679                 return -EINVAL;
9680         return 0;
9681 }
9682
9683 /*
9684  * Load guest's/host's msr at nested entry/exit.
9685  * return 0 for success, entry index for failure.
9686  */
9687 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9688 {
9689         u32 i;
9690         struct vmx_msr_entry e;
9691         struct msr_data msr;
9692
9693         msr.host_initiated = false;
9694         for (i = 0; i < count; i++) {
9695                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9696                                         &e, sizeof(e))) {
9697                         pr_warn_ratelimited(
9698                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9699                                 __func__, i, gpa + i * sizeof(e));
9700                         goto fail;
9701                 }
9702                 if (nested_vmx_load_msr_check(vcpu, &e)) {
9703                         pr_warn_ratelimited(
9704                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9705                                 __func__, i, e.index, e.reserved);
9706                         goto fail;
9707                 }
9708                 msr.index = e.index;
9709                 msr.data = e.value;
9710                 if (kvm_set_msr(vcpu, &msr)) {
9711                         pr_warn_ratelimited(
9712                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9713                                 __func__, i, e.index, e.value);
9714                         goto fail;
9715                 }
9716         }
9717         return 0;
9718 fail:
9719         return i + 1;
9720 }
9721
9722 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9723 {
9724         u32 i;
9725         struct vmx_msr_entry e;
9726
9727         for (i = 0; i < count; i++) {
9728                 struct msr_data msr_info;
9729                 if (kvm_vcpu_read_guest(vcpu,
9730                                         gpa + i * sizeof(e),
9731                                         &e, 2 * sizeof(u32))) {
9732                         pr_warn_ratelimited(
9733                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9734                                 __func__, i, gpa + i * sizeof(e));
9735                         return -EINVAL;
9736                 }
9737                 if (nested_vmx_store_msr_check(vcpu, &e)) {
9738                         pr_warn_ratelimited(
9739                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9740                                 __func__, i, e.index, e.reserved);
9741                         return -EINVAL;
9742                 }
9743                 msr_info.host_initiated = false;
9744                 msr_info.index = e.index;
9745                 if (kvm_get_msr(vcpu, &msr_info)) {
9746                         pr_warn_ratelimited(
9747                                 "%s cannot read MSR (%u, 0x%x)\n",
9748                                 __func__, i, e.index);
9749                         return -EINVAL;
9750                 }
9751                 if (kvm_vcpu_write_guest(vcpu,
9752                                          gpa + i * sizeof(e) +
9753                                              offsetof(struct vmx_msr_entry, value),
9754                                          &msr_info.data, sizeof(msr_info.data))) {
9755                         pr_warn_ratelimited(
9756                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9757                                 __func__, i, e.index, msr_info.data);
9758                         return -EINVAL;
9759                 }
9760         }
9761         return 0;
9762 }
9763
9764 /*
9765  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9766  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9767  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9768  * guest in a way that will both be appropriate to L1's requests, and our
9769  * needs. In addition to modifying the active vmcs (which is vmcs02), this
9770  * function also has additional necessary side-effects, like setting various
9771  * vcpu->arch fields.
9772  */
9773 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9774 {
9775         struct vcpu_vmx *vmx = to_vmx(vcpu);
9776         u32 exec_control;
9777
9778         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9779         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9780         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9781         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9782         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9783         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9784         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9785         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9786         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9787         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9788         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9789         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9790         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9791         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9792         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9793         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9794         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9795         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9796         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9797         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9798         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9799         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9800         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9801         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9802         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9803         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9804         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9805         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9806         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9807         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9808         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9809         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9810         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9811         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9812         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9813         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9814
9815         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9816                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9817                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9818         } else {
9819                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9820                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9821         }
9822         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9823                 vmcs12->vm_entry_intr_info_field);
9824         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9825                 vmcs12->vm_entry_exception_error_code);
9826         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9827                 vmcs12->vm_entry_instruction_len);
9828         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9829                 vmcs12->guest_interruptibility_info);
9830         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
9831         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
9832         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9833                 vmcs12->guest_pending_dbg_exceptions);
9834         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9835         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9836
9837         if (nested_cpu_has_xsaves(vmcs12))
9838                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
9839         vmcs_write64(VMCS_LINK_POINTER, -1ull);
9840
9841         exec_control = vmcs12->pin_based_vm_exec_control;
9842
9843         /* Preemption timer setting is only taken from vmcs01.  */
9844         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9845         exec_control |= vmcs_config.pin_based_exec_ctrl;
9846         if (vmx->hv_deadline_tsc == -1)
9847                 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9848
9849         /* Posted interrupts setting is only taken from vmcs12.  */
9850         if (nested_cpu_has_posted_intr(vmcs12)) {
9851                 /*
9852                  * Note that we use L0's vector here and in
9853                  * vmx_deliver_nested_posted_interrupt.
9854                  */
9855                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9856                 vmx->nested.pi_pending = false;
9857                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9858                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9859                         page_to_phys(vmx->nested.pi_desc_page) +
9860                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9861                         (PAGE_SIZE - 1)));
9862         } else
9863                 exec_control &= ~PIN_BASED_POSTED_INTR;
9864
9865         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
9866
9867         vmx->nested.preemption_timer_expired = false;
9868         if (nested_cpu_has_preemption_timer(vmcs12))
9869                 vmx_start_preemption_timer(vcpu);
9870
9871         /*
9872          * Whether page-faults are trapped is determined by a combination of
9873          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9874          * If enable_ept, L0 doesn't care about page faults and we should
9875          * set all of these to L1's desires. However, if !enable_ept, L0 does
9876          * care about (at least some) page faults, and because it is not easy
9877          * (if at all possible?) to merge L0 and L1's desires, we simply ask
9878          * to exit on each and every L2 page fault. This is done by setting
9879          * MASK=MATCH=0 and (see below) EB.PF=1.
9880          * Note that below we don't need special code to set EB.PF beyond the
9881          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9882          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9883          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9884          *
9885          * A problem with this approach (when !enable_ept) is that L1 may be
9886          * injected with more page faults than it asked for. This could have
9887          * caused problems, but in practice existing hypervisors don't care.
9888          * To fix this, we will need to emulate the PFEC checking (on the L1
9889          * page tables), using walk_addr(), when injecting PFs to L1.
9890          */
9891         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9892                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9893         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9894                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9895
9896         if (cpu_has_secondary_exec_ctrls()) {
9897                 exec_control = vmx_secondary_exec_control(vmx);
9898
9899                 /* Take the following fields only from vmcs12 */
9900                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9901                                   SECONDARY_EXEC_RDTSCP |
9902                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
9903                                   SECONDARY_EXEC_APIC_REGISTER_VIRT |
9904                                   SECONDARY_EXEC_PCOMMIT);
9905                 if (nested_cpu_has(vmcs12,
9906                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9907                         exec_control |= vmcs12->secondary_vm_exec_control;
9908
9909                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
9910                         /*
9911                          * If translation failed, no matter: This feature asks
9912                          * to exit when accessing the given address, and if it
9913                          * can never be accessed, this feature won't do
9914                          * anything anyway.
9915                          */
9916                         if (!vmx->nested.apic_access_page)
9917                                 exec_control &=
9918                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9919                         else
9920                                 vmcs_write64(APIC_ACCESS_ADDR,
9921                                   page_to_phys(vmx->nested.apic_access_page));
9922                 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9923                             cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9924                         exec_control |=
9925                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9926                         kvm_vcpu_reload_apic_access_page(vcpu);
9927                 }
9928
9929                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9930                         vmcs_write64(EOI_EXIT_BITMAP0,
9931                                 vmcs12->eoi_exit_bitmap0);
9932                         vmcs_write64(EOI_EXIT_BITMAP1,
9933                                 vmcs12->eoi_exit_bitmap1);
9934                         vmcs_write64(EOI_EXIT_BITMAP2,
9935                                 vmcs12->eoi_exit_bitmap2);
9936                         vmcs_write64(EOI_EXIT_BITMAP3,
9937                                 vmcs12->eoi_exit_bitmap3);
9938                         vmcs_write16(GUEST_INTR_STATUS,
9939                                 vmcs12->guest_intr_status);
9940                 }
9941
9942                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9943         }
9944
9945
9946         /*
9947          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9948          * Some constant fields are set here by vmx_set_constant_host_state().
9949          * Other fields are different per CPU, and will be set later when
9950          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9951          */
9952         vmx_set_constant_host_state(vmx);
9953
9954         /*
9955          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9956          * entry, but only if the current (host) sp changed from the value
9957          * we wrote last (vmx->host_rsp). This cache is no longer relevant
9958          * if we switch vmcs, and rather than hold a separate cache per vmcs,
9959          * here we just force the write to happen on entry.
9960          */
9961         vmx->host_rsp = 0;
9962
9963         exec_control = vmx_exec_control(vmx); /* L0's desires */
9964         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9965         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9966         exec_control &= ~CPU_BASED_TPR_SHADOW;
9967         exec_control |= vmcs12->cpu_based_vm_exec_control;
9968
9969         if (exec_control & CPU_BASED_TPR_SHADOW) {
9970                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9971                                 page_to_phys(vmx->nested.virtual_apic_page));
9972                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9973         }
9974
9975         if (cpu_has_vmx_msr_bitmap() &&
9976             exec_control & CPU_BASED_USE_MSR_BITMAPS) {
9977                 nested_vmx_merge_msr_bitmap(vcpu, vmcs12);
9978                 /* MSR_BITMAP will be set by following vmx_set_efer. */
9979         } else
9980                 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9981
9982         /*
9983          * Merging of IO bitmap not currently supported.
9984          * Rather, exit every time.
9985          */
9986         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9987         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9988
9989         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9990
9991         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9992          * bitwise-or of what L1 wants to trap for L2, and what we want to
9993          * trap. Note that CR0.TS also needs updating - we do this later.
9994          */
9995         update_exception_bitmap(vcpu);
9996         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9997         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9998
9999         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10000          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10001          * bits are further modified by vmx_set_efer() below.
10002          */
10003         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
10004
10005         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10006          * emulated by vmx_set_efer(), below.
10007          */
10008         vm_entry_controls_init(vmx,
10009                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
10010                         ~VM_ENTRY_IA32E_MODE) |
10011                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
10012
10013         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
10014                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
10015                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
10016         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
10017                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
10018
10019
10020         set_cr4_guest_host_mask(vmx);
10021
10022         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
10023                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
10024
10025         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
10026                 vmcs_write64(TSC_OFFSET,
10027                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
10028         else
10029                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10030
10031         if (enable_vpid) {
10032                 /*
10033                  * There is no direct mapping between vpid02 and vpid12, the
10034                  * vpid02 is per-vCPU for L0 and reused while the value of
10035                  * vpid12 is changed w/ one invvpid during nested vmentry.
10036                  * The vpid12 is allocated by L1 for L2, so it will not
10037                  * influence global bitmap(for vpid01 and vpid02 allocation)
10038                  * even if spawn a lot of nested vCPUs.
10039                  */
10040                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
10041                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
10042                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
10043                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
10044                                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
10045                         }
10046                 } else {
10047                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
10048                         vmx_flush_tlb(vcpu);
10049                 }
10050
10051         }
10052
10053         if (nested_cpu_has_ept(vmcs12)) {
10054                 kvm_mmu_unload(vcpu);
10055                 nested_ept_init_mmu_context(vcpu);
10056         }
10057
10058         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
10059                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
10060         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
10061                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10062         else
10063                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10064         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10065         vmx_set_efer(vcpu, vcpu->arch.efer);
10066
10067         /*
10068          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
10069          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
10070          * The CR0_READ_SHADOW is what L2 should have expected to read given
10071          * the specifications by L1; It's not enough to take
10072          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10073          * have more bits than L1 expected.
10074          */
10075         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
10076         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
10077
10078         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
10079         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
10080
10081         /* shadow page tables on either EPT or shadow page tables */
10082         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
10083         kvm_mmu_reset_context(vcpu);
10084
10085         if (!enable_ept)
10086                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
10087
10088         /*
10089          * L1 may access the L2's PDPTR, so save them to construct vmcs12
10090          */
10091         if (enable_ept) {
10092                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
10093                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
10094                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
10095                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
10096         }
10097
10098         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
10099         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
10100 }
10101
10102 /*
10103  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10104  * for running an L2 nested guest.
10105  */
10106 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
10107 {
10108         struct vmcs12 *vmcs12;
10109         struct vcpu_vmx *vmx = to_vmx(vcpu);
10110         int cpu;
10111         struct loaded_vmcs *vmcs02;
10112         bool ia32e;
10113         u32 msr_entry_idx;
10114
10115         if (!nested_vmx_check_permission(vcpu) ||
10116             !nested_vmx_check_vmcs12(vcpu))
10117                 return 1;
10118
10119         skip_emulated_instruction(vcpu);
10120         vmcs12 = get_vmcs12(vcpu);
10121
10122         if (enable_shadow_vmcs)
10123                 copy_shadow_to_vmcs12(vmx);
10124
10125         /*
10126          * The nested entry process starts with enforcing various prerequisites
10127          * on vmcs12 as required by the Intel SDM, and act appropriately when
10128          * they fail: As the SDM explains, some conditions should cause the
10129          * instruction to fail, while others will cause the instruction to seem
10130          * to succeed, but return an EXIT_REASON_INVALID_STATE.
10131          * To speed up the normal (success) code path, we should avoid checking
10132          * for misconfigurations which will anyway be caught by the processor
10133          * when using the merged vmcs02.
10134          */
10135         if (vmcs12->launch_state == launch) {
10136                 nested_vmx_failValid(vcpu,
10137                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10138                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
10139                 return 1;
10140         }
10141
10142         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
10143             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
10144                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10145                 return 1;
10146         }
10147
10148         if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
10149                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10150                 return 1;
10151         }
10152
10153         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
10154                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10155                 return 1;
10156         }
10157
10158         if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
10159                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10160                 return 1;
10161         }
10162
10163         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
10164                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10165                 return 1;
10166         }
10167
10168         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
10169                                 vmx->nested.nested_vmx_true_procbased_ctls_low,
10170                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
10171             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
10172                                 vmx->nested.nested_vmx_secondary_ctls_low,
10173                                 vmx->nested.nested_vmx_secondary_ctls_high) ||
10174             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
10175                                 vmx->nested.nested_vmx_pinbased_ctls_low,
10176                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
10177             !vmx_control_verify(vmcs12->vm_exit_controls,
10178                                 vmx->nested.nested_vmx_true_exit_ctls_low,
10179                                 vmx->nested.nested_vmx_exit_ctls_high) ||
10180             !vmx_control_verify(vmcs12->vm_entry_controls,
10181                                 vmx->nested.nested_vmx_true_entry_ctls_low,
10182                                 vmx->nested.nested_vmx_entry_ctls_high))
10183         {
10184                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10185                 return 1;
10186         }
10187
10188         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
10189             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
10190                 nested_vmx_failValid(vcpu,
10191                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
10192                 return 1;
10193         }
10194
10195         if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
10196             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
10197                 nested_vmx_entry_failure(vcpu, vmcs12,
10198                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
10199                 return 1;
10200         }
10201         if (vmcs12->vmcs_link_pointer != -1ull) {
10202                 nested_vmx_entry_failure(vcpu, vmcs12,
10203                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
10204                 return 1;
10205         }
10206
10207         /*
10208          * If the load IA32_EFER VM-entry control is 1, the following checks
10209          * are performed on the field for the IA32_EFER MSR:
10210          * - Bits reserved in the IA32_EFER MSR must be 0.
10211          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10212          *   the IA-32e mode guest VM-exit control. It must also be identical
10213          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10214          *   CR0.PG) is 1.
10215          */
10216         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
10217                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
10218                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
10219                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
10220                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
10221                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
10222                         nested_vmx_entry_failure(vcpu, vmcs12,
10223                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
10224                         return 1;
10225                 }
10226         }
10227
10228         /*
10229          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10230          * IA32_EFER MSR must be 0 in the field for that register. In addition,
10231          * the values of the LMA and LME bits in the field must each be that of
10232          * the host address-space size VM-exit control.
10233          */
10234         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
10235                 ia32e = (vmcs12->vm_exit_controls &
10236                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
10237                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
10238                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
10239                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
10240                         nested_vmx_entry_failure(vcpu, vmcs12,
10241                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
10242                         return 1;
10243                 }
10244         }
10245
10246         /*
10247          * We're finally done with prerequisite checking, and can start with
10248          * the nested entry.
10249          */
10250
10251         vmcs02 = nested_get_current_vmcs02(vmx);
10252         if (!vmcs02)
10253                 return -ENOMEM;
10254
10255         enter_guest_mode(vcpu);
10256
10257         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
10258
10259         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
10260                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10261
10262         cpu = get_cpu();
10263         vmx->loaded_vmcs = vmcs02;
10264         vmx_vcpu_put(vcpu);
10265         vmx_vcpu_load(vcpu, cpu);
10266         vcpu->cpu = cpu;
10267         put_cpu();
10268
10269         vmx_segment_cache_clear(vmx);
10270
10271         prepare_vmcs02(vcpu, vmcs12);
10272
10273         msr_entry_idx = nested_vmx_load_msr(vcpu,
10274                                             vmcs12->vm_entry_msr_load_addr,
10275                                             vmcs12->vm_entry_msr_load_count);
10276         if (msr_entry_idx) {
10277                 leave_guest_mode(vcpu);
10278                 vmx_load_vmcs01(vcpu);
10279                 nested_vmx_entry_failure(vcpu, vmcs12,
10280                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10281                 return 1;
10282         }
10283
10284         vmcs12->launch_state = 1;
10285
10286         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
10287                 return kvm_vcpu_halt(vcpu);
10288
10289         vmx->nested.nested_run_pending = 1;
10290
10291         /*
10292          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10293          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10294          * returned as far as L1 is concerned. It will only return (and set
10295          * the success flag) when L2 exits (see nested_vmx_vmexit()).
10296          */
10297         return 1;
10298 }
10299
10300 /*
10301  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10302  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10303  * This function returns the new value we should put in vmcs12.guest_cr0.
10304  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10305  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10306  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10307  *     didn't trap the bit, because if L1 did, so would L0).
10308  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10309  *     been modified by L2, and L1 knows it. So just leave the old value of
10310  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10311  *     isn't relevant, because if L0 traps this bit it can set it to anything.
10312  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10313  *     changed these bits, and therefore they need to be updated, but L0
10314  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10315  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10316  */
10317 static inline unsigned long
10318 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10319 {
10320         return
10321         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10322         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10323         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10324                         vcpu->arch.cr0_guest_owned_bits));
10325 }
10326
10327 static inline unsigned long
10328 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10329 {
10330         return
10331         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10332         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10333         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10334                         vcpu->arch.cr4_guest_owned_bits));
10335 }
10336
10337 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10338                                        struct vmcs12 *vmcs12)
10339 {
10340         u32 idt_vectoring;
10341         unsigned int nr;
10342
10343         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10344                 nr = vcpu->arch.exception.nr;
10345                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10346
10347                 if (kvm_exception_is_soft(nr)) {
10348                         vmcs12->vm_exit_instruction_len =
10349                                 vcpu->arch.event_exit_inst_len;
10350                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10351                 } else
10352                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10353
10354                 if (vcpu->arch.exception.has_error_code) {
10355                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10356                         vmcs12->idt_vectoring_error_code =
10357                                 vcpu->arch.exception.error_code;
10358                 }
10359
10360                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10361         } else if (vcpu->arch.nmi_injected) {
10362                 vmcs12->idt_vectoring_info_field =
10363                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10364         } else if (vcpu->arch.interrupt.pending) {
10365                 nr = vcpu->arch.interrupt.nr;
10366                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10367
10368                 if (vcpu->arch.interrupt.soft) {
10369                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
10370                         vmcs12->vm_entry_instruction_len =
10371                                 vcpu->arch.event_exit_inst_len;
10372                 } else
10373                         idt_vectoring |= INTR_TYPE_EXT_INTR;
10374
10375                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10376         }
10377 }
10378
10379 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10380 {
10381         struct vcpu_vmx *vmx = to_vmx(vcpu);
10382
10383         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10384             vmx->nested.preemption_timer_expired) {
10385                 if (vmx->nested.nested_run_pending)
10386                         return -EBUSY;
10387                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10388                 return 0;
10389         }
10390
10391         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10392                 if (vmx->nested.nested_run_pending ||
10393                     vcpu->arch.interrupt.pending)
10394                         return -EBUSY;
10395                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10396                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
10397                                   INTR_INFO_VALID_MASK, 0);
10398                 /*
10399                  * The NMI-triggered VM exit counts as injection:
10400                  * clear this one and block further NMIs.
10401                  */
10402                 vcpu->arch.nmi_pending = 0;
10403                 vmx_set_nmi_mask(vcpu, true);
10404                 return 0;
10405         }
10406
10407         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10408             nested_exit_on_intr(vcpu)) {
10409                 if (vmx->nested.nested_run_pending)
10410                         return -EBUSY;
10411                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10412                 return 0;
10413         }
10414
10415         return vmx_complete_nested_posted_interrupt(vcpu);
10416 }
10417
10418 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10419 {
10420         ktime_t remaining =
10421                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10422         u64 value;
10423
10424         if (ktime_to_ns(remaining) <= 0)
10425                 return 0;
10426
10427         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10428         do_div(value, 1000000);
10429         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10430 }
10431
10432 /*
10433  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10434  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10435  * and this function updates it to reflect the changes to the guest state while
10436  * L2 was running (and perhaps made some exits which were handled directly by L0
10437  * without going back to L1), and to reflect the exit reason.
10438  * Note that we do not have to copy here all VMCS fields, just those that
10439  * could have changed by the L2 guest or the exit - i.e., the guest-state and
10440  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10441  * which already writes to vmcs12 directly.
10442  */
10443 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10444                            u32 exit_reason, u32 exit_intr_info,
10445                            unsigned long exit_qualification)
10446 {
10447         /* update guest state fields: */
10448         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10449         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10450
10451         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10452         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10453         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10454
10455         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10456         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10457         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10458         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10459         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10460         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10461         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10462         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10463         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10464         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10465         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10466         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10467         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10468         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10469         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10470         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10471         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10472         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10473         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10474         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10475         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10476         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10477         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10478         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10479         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10480         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10481         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10482         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10483         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10484         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10485         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10486         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10487         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10488         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10489         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10490         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10491
10492         vmcs12->guest_interruptibility_info =
10493                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10494         vmcs12->guest_pending_dbg_exceptions =
10495                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10496         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10497                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10498         else
10499                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10500
10501         if (nested_cpu_has_preemption_timer(vmcs12)) {
10502                 if (vmcs12->vm_exit_controls &
10503                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10504                         vmcs12->vmx_preemption_timer_value =
10505                                 vmx_get_preemption_timer_value(vcpu);
10506                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10507         }
10508
10509         /*
10510          * In some cases (usually, nested EPT), L2 is allowed to change its
10511          * own CR3 without exiting. If it has changed it, we must keep it.
10512          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10513          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10514          *
10515          * Additionally, restore L2's PDPTR to vmcs12.
10516          */
10517         if (enable_ept) {
10518                 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
10519                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10520                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10521                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10522                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10523         }
10524
10525         if (nested_cpu_has_vid(vmcs12))
10526                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10527
10528         vmcs12->vm_entry_controls =
10529                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10530                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10531
10532         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10533                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10534                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10535         }
10536
10537         /* TODO: These cannot have changed unless we have MSR bitmaps and
10538          * the relevant bit asks not to trap the change */
10539         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10540                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10541         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10542                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10543         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10544         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10545         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10546         if (kvm_mpx_supported())
10547                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10548         if (nested_cpu_has_xsaves(vmcs12))
10549                 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
10550
10551         /* update exit information fields: */
10552
10553         vmcs12->vm_exit_reason = exit_reason;
10554         vmcs12->exit_qualification = exit_qualification;
10555
10556         vmcs12->vm_exit_intr_info = exit_intr_info;
10557         if ((vmcs12->vm_exit_intr_info &
10558              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10559             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10560                 vmcs12->vm_exit_intr_error_code =
10561                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10562         vmcs12->idt_vectoring_info_field = 0;
10563         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10564         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10565
10566         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10567                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10568                  * instead of reading the real value. */
10569                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10570
10571                 /*
10572                  * Transfer the event that L0 or L1 may wanted to inject into
10573                  * L2 to IDT_VECTORING_INFO_FIELD.
10574                  */
10575                 vmcs12_save_pending_event(vcpu, vmcs12);
10576         }
10577
10578         /*
10579          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10580          * preserved above and would only end up incorrectly in L1.
10581          */
10582         vcpu->arch.nmi_injected = false;
10583         kvm_clear_exception_queue(vcpu);
10584         kvm_clear_interrupt_queue(vcpu);
10585 }
10586
10587 /*
10588  * A part of what we need to when the nested L2 guest exits and we want to
10589  * run its L1 parent, is to reset L1's guest state to the host state specified
10590  * in vmcs12.
10591  * This function is to be called not only on normal nested exit, but also on
10592  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10593  * Failures During or After Loading Guest State").
10594  * This function should be called when the active VMCS is L1's (vmcs01).
10595  */
10596 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10597                                    struct vmcs12 *vmcs12)
10598 {
10599         struct kvm_segment seg;
10600
10601         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10602                 vcpu->arch.efer = vmcs12->host_ia32_efer;
10603         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10604                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10605         else
10606                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10607         vmx_set_efer(vcpu, vcpu->arch.efer);
10608
10609         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10610         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10611         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10612         /*
10613          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10614          * actually changed, because it depends on the current state of
10615          * fpu_active (which may have changed).
10616          * Note that vmx_set_cr0 refers to efer set above.
10617          */
10618         vmx_set_cr0(vcpu, vmcs12->host_cr0);
10619         /*
10620          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10621          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10622          * but we also need to update cr0_guest_host_mask and exception_bitmap.
10623          */
10624         update_exception_bitmap(vcpu);
10625         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
10626         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10627
10628         /*
10629          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10630          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10631          */
10632         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10633         kvm_set_cr4(vcpu, vmcs12->host_cr4);
10634
10635         nested_ept_uninit_mmu_context(vcpu);
10636
10637         kvm_set_cr3(vcpu, vmcs12->host_cr3);
10638         kvm_mmu_reset_context(vcpu);
10639
10640         if (!enable_ept)
10641                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10642
10643         if (enable_vpid) {
10644                 /*
10645                  * Trivially support vpid by letting L2s share their parent
10646                  * L1's vpid. TODO: move to a more elaborate solution, giving
10647                  * each L2 its own vpid and exposing the vpid feature to L1.
10648                  */
10649                 vmx_flush_tlb(vcpu);
10650         }
10651
10652
10653         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10654         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10655         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10656         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10657         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10658
10659         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
10660         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10661                 vmcs_write64(GUEST_BNDCFGS, 0);
10662
10663         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10664                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10665                 vcpu->arch.pat = vmcs12->host_ia32_pat;
10666         }
10667         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10668                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10669                         vmcs12->host_ia32_perf_global_ctrl);
10670
10671         /* Set L1 segment info according to Intel SDM
10672             27.5.2 Loading Host Segment and Descriptor-Table Registers */
10673         seg = (struct kvm_segment) {
10674                 .base = 0,
10675                 .limit = 0xFFFFFFFF,
10676                 .selector = vmcs12->host_cs_selector,
10677                 .type = 11,
10678                 .present = 1,
10679                 .s = 1,
10680                 .g = 1
10681         };
10682         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10683                 seg.l = 1;
10684         else
10685                 seg.db = 1;
10686         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10687         seg = (struct kvm_segment) {
10688                 .base = 0,
10689                 .limit = 0xFFFFFFFF,
10690                 .type = 3,
10691                 .present = 1,
10692                 .s = 1,
10693                 .db = 1,
10694                 .g = 1
10695         };
10696         seg.selector = vmcs12->host_ds_selector;
10697         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10698         seg.selector = vmcs12->host_es_selector;
10699         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10700         seg.selector = vmcs12->host_ss_selector;
10701         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10702         seg.selector = vmcs12->host_fs_selector;
10703         seg.base = vmcs12->host_fs_base;
10704         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10705         seg.selector = vmcs12->host_gs_selector;
10706         seg.base = vmcs12->host_gs_base;
10707         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10708         seg = (struct kvm_segment) {
10709                 .base = vmcs12->host_tr_base,
10710                 .limit = 0x67,
10711                 .selector = vmcs12->host_tr_selector,
10712                 .type = 11,
10713                 .present = 1
10714         };
10715         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10716
10717         kvm_set_dr(vcpu, 7, 0x400);
10718         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
10719
10720         if (cpu_has_vmx_msr_bitmap())
10721                 vmx_set_msr_bitmap(vcpu);
10722
10723         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10724                                 vmcs12->vm_exit_msr_load_count))
10725                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
10726 }
10727
10728 /*
10729  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10730  * and modify vmcs12 to make it see what it would expect to see there if
10731  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10732  */
10733 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10734                               u32 exit_intr_info,
10735                               unsigned long exit_qualification)
10736 {
10737         struct vcpu_vmx *vmx = to_vmx(vcpu);
10738         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10739
10740         /* trying to cancel vmlaunch/vmresume is a bug */
10741         WARN_ON_ONCE(vmx->nested.nested_run_pending);
10742
10743         leave_guest_mode(vcpu);
10744         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10745                        exit_qualification);
10746
10747         if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10748                                  vmcs12->vm_exit_msr_store_count))
10749                 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10750
10751         vmx_load_vmcs01(vcpu);
10752
10753         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10754             && nested_exit_intr_ack_set(vcpu)) {
10755                 int irq = kvm_cpu_get_interrupt(vcpu);
10756                 WARN_ON(irq < 0);
10757                 vmcs12->vm_exit_intr_info = irq |
10758                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10759         }
10760
10761         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10762                                        vmcs12->exit_qualification,
10763                                        vmcs12->idt_vectoring_info_field,
10764                                        vmcs12->vm_exit_intr_info,
10765                                        vmcs12->vm_exit_intr_error_code,
10766                                        KVM_ISA_VMX);
10767
10768         vm_entry_controls_reset_shadow(vmx);
10769         vm_exit_controls_reset_shadow(vmx);
10770         vmx_segment_cache_clear(vmx);
10771
10772         /* if no vmcs02 cache requested, remove the one we used */
10773         if (VMCS02_POOL_SIZE == 0)
10774                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10775
10776         load_vmcs12_host_state(vcpu, vmcs12);
10777
10778         /* Update any VMCS fields that might have changed while L2 ran */
10779         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10780         if (vmx->hv_deadline_tsc == -1)
10781                 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
10782                                 PIN_BASED_VMX_PREEMPTION_TIMER);
10783         else
10784                 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
10785                               PIN_BASED_VMX_PREEMPTION_TIMER);
10786
10787         /* This is needed for same reason as it was needed in prepare_vmcs02 */
10788         vmx->host_rsp = 0;
10789
10790         /* Unpin physical memory we referred to in vmcs02 */
10791         if (vmx->nested.apic_access_page) {
10792                 nested_release_page(vmx->nested.apic_access_page);
10793                 vmx->nested.apic_access_page = NULL;
10794         }
10795         if (vmx->nested.virtual_apic_page) {
10796                 nested_release_page(vmx->nested.virtual_apic_page);
10797                 vmx->nested.virtual_apic_page = NULL;
10798         }
10799         if (vmx->nested.pi_desc_page) {
10800                 kunmap(vmx->nested.pi_desc_page);
10801                 nested_release_page(vmx->nested.pi_desc_page);
10802                 vmx->nested.pi_desc_page = NULL;
10803                 vmx->nested.pi_desc = NULL;
10804         }
10805
10806         /*
10807          * We are now running in L2, mmu_notifier will force to reload the
10808          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10809          */
10810         kvm_vcpu_reload_apic_access_page(vcpu);
10811
10812         /*
10813          * Exiting from L2 to L1, we're now back to L1 which thinks it just
10814          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10815          * success or failure flag accordingly.
10816          */
10817         if (unlikely(vmx->fail)) {
10818                 vmx->fail = 0;
10819                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10820         } else
10821                 nested_vmx_succeed(vcpu);
10822         if (enable_shadow_vmcs)
10823                 vmx->nested.sync_shadow_vmcs = true;
10824
10825         /* in case we halted in L2 */
10826         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10827 }
10828
10829 /*
10830  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10831  */
10832 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10833 {
10834         if (is_guest_mode(vcpu))
10835                 nested_vmx_vmexit(vcpu, -1, 0, 0);
10836         free_nested(to_vmx(vcpu));
10837 }
10838
10839 /*
10840  * L1's failure to enter L2 is a subset of a normal exit, as explained in
10841  * 23.7 "VM-entry failures during or after loading guest state" (this also
10842  * lists the acceptable exit-reason and exit-qualification parameters).
10843  * It should only be called before L2 actually succeeded to run, and when
10844  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10845  */
10846 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10847                         struct vmcs12 *vmcs12,
10848                         u32 reason, unsigned long qualification)
10849 {
10850         load_vmcs12_host_state(vcpu, vmcs12);
10851         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10852         vmcs12->exit_qualification = qualification;
10853         nested_vmx_succeed(vcpu);
10854         if (enable_shadow_vmcs)
10855                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
10856 }
10857
10858 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10859                                struct x86_instruction_info *info,
10860                                enum x86_intercept_stage stage)
10861 {
10862         return X86EMUL_CONTINUE;
10863 }
10864
10865 #ifdef CONFIG_X86_64
10866 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
10867 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
10868                                   u64 divisor, u64 *result)
10869 {
10870         u64 low = a << shift, high = a >> (64 - shift);
10871
10872         /* To avoid the overflow on divq */
10873         if (high >= divisor)
10874                 return 1;
10875
10876         /* Low hold the result, high hold rem which is discarded */
10877         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
10878             "rm" (divisor), "0" (low), "1" (high));
10879         *result = low;
10880
10881         return 0;
10882 }
10883
10884 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
10885 {
10886         struct vcpu_vmx *vmx = to_vmx(vcpu);
10887         u64 tscl = rdtsc();
10888         u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
10889         u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
10890
10891         /* Convert to host delta tsc if tsc scaling is enabled */
10892         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
10893                         u64_shl_div_u64(delta_tsc,
10894                                 kvm_tsc_scaling_ratio_frac_bits,
10895                                 vcpu->arch.tsc_scaling_ratio,
10896                                 &delta_tsc))
10897                 return -ERANGE;
10898
10899         /*
10900          * If the delta tsc can't fit in the 32 bit after the multi shift,
10901          * we can't use the preemption timer.
10902          * It's possible that it fits on later vmentries, but checking
10903          * on every vmentry is costly so we just use an hrtimer.
10904          */
10905         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
10906                 return -ERANGE;
10907
10908         vmx->hv_deadline_tsc = tscl + delta_tsc;
10909         vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
10910                         PIN_BASED_VMX_PREEMPTION_TIMER);
10911         return 0;
10912 }
10913
10914 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
10915 {
10916         struct vcpu_vmx *vmx = to_vmx(vcpu);
10917         vmx->hv_deadline_tsc = -1;
10918         vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
10919                         PIN_BASED_VMX_PREEMPTION_TIMER);
10920 }
10921 #endif
10922
10923 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
10924 {
10925         if (ple_gap)
10926                 shrink_ple_window(vcpu);
10927 }
10928
10929 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10930                                      struct kvm_memory_slot *slot)
10931 {
10932         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10933         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10934 }
10935
10936 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10937                                        struct kvm_memory_slot *slot)
10938 {
10939         kvm_mmu_slot_set_dirty(kvm, slot);
10940 }
10941
10942 static void vmx_flush_log_dirty(struct kvm *kvm)
10943 {
10944         kvm_flush_pml_buffers(kvm);
10945 }
10946
10947 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10948                                            struct kvm_memory_slot *memslot,
10949                                            gfn_t offset, unsigned long mask)
10950 {
10951         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10952 }
10953
10954 /*
10955  * This routine does the following things for vCPU which is going
10956  * to be blocked if VT-d PI is enabled.
10957  * - Store the vCPU to the wakeup list, so when interrupts happen
10958  *   we can find the right vCPU to wake up.
10959  * - Change the Posted-interrupt descriptor as below:
10960  *      'NDST' <-- vcpu->pre_pcpu
10961  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
10962  * - If 'ON' is set during this process, which means at least one
10963  *   interrupt is posted for this vCPU, we cannot block it, in
10964  *   this case, return 1, otherwise, return 0.
10965  *
10966  */
10967 static int pi_pre_block(struct kvm_vcpu *vcpu)
10968 {
10969         unsigned long flags;
10970         unsigned int dest;
10971         struct pi_desc old, new;
10972         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10973
10974         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10975                 !irq_remapping_cap(IRQ_POSTING_CAP))
10976                 return 0;
10977
10978         vcpu->pre_pcpu = vcpu->cpu;
10979         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10980                           vcpu->pre_pcpu), flags);
10981         list_add_tail(&vcpu->blocked_vcpu_list,
10982                       &per_cpu(blocked_vcpu_on_cpu,
10983                       vcpu->pre_pcpu));
10984         spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
10985                                vcpu->pre_pcpu), flags);
10986
10987         do {
10988                 old.control = new.control = pi_desc->control;
10989
10990                 /*
10991                  * We should not block the vCPU if
10992                  * an interrupt is posted for it.
10993                  */
10994                 if (pi_test_on(pi_desc) == 1) {
10995                         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10996                                           vcpu->pre_pcpu), flags);
10997                         list_del(&vcpu->blocked_vcpu_list);
10998                         spin_unlock_irqrestore(
10999                                         &per_cpu(blocked_vcpu_on_cpu_lock,
11000                                         vcpu->pre_pcpu), flags);
11001                         vcpu->pre_pcpu = -1;
11002
11003                         return 1;
11004                 }
11005
11006                 WARN((pi_desc->sn == 1),
11007                      "Warning: SN field of posted-interrupts "
11008                      "is set before blocking\n");
11009
11010                 /*
11011                  * Since vCPU can be preempted during this process,
11012                  * vcpu->cpu could be different with pre_pcpu, we
11013                  * need to set pre_pcpu as the destination of wakeup
11014                  * notification event, then we can find the right vCPU
11015                  * to wakeup in wakeup handler if interrupts happen
11016                  * when the vCPU is in blocked state.
11017                  */
11018                 dest = cpu_physical_id(vcpu->pre_pcpu);
11019
11020                 if (x2apic_enabled())
11021                         new.ndst = dest;
11022                 else
11023                         new.ndst = (dest << 8) & 0xFF00;
11024
11025                 /* set 'NV' to 'wakeup vector' */
11026                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
11027         } while (cmpxchg(&pi_desc->control, old.control,
11028                         new.control) != old.control);
11029
11030         return 0;
11031 }
11032
11033 static int vmx_pre_block(struct kvm_vcpu *vcpu)
11034 {
11035         if (pi_pre_block(vcpu))
11036                 return 1;
11037
11038         if (kvm_lapic_hv_timer_in_use(vcpu))
11039                 kvm_lapic_switch_to_sw_timer(vcpu);
11040
11041         return 0;
11042 }
11043
11044 static void pi_post_block(struct kvm_vcpu *vcpu)
11045 {
11046         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11047         struct pi_desc old, new;
11048         unsigned int dest;
11049         unsigned long flags;
11050
11051         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11052                 !irq_remapping_cap(IRQ_POSTING_CAP))
11053                 return;
11054
11055         do {
11056                 old.control = new.control = pi_desc->control;
11057
11058                 dest = cpu_physical_id(vcpu->cpu);
11059
11060                 if (x2apic_enabled())
11061                         new.ndst = dest;
11062                 else
11063                         new.ndst = (dest << 8) & 0xFF00;
11064
11065                 /* Allow posting non-urgent interrupts */
11066                 new.sn = 0;
11067
11068                 /* set 'NV' to 'notification vector' */
11069                 new.nv = POSTED_INTR_VECTOR;
11070         } while (cmpxchg(&pi_desc->control, old.control,
11071                         new.control) != old.control);
11072
11073         if(vcpu->pre_pcpu != -1) {
11074                 spin_lock_irqsave(
11075                         &per_cpu(blocked_vcpu_on_cpu_lock,
11076                         vcpu->pre_pcpu), flags);
11077                 list_del(&vcpu->blocked_vcpu_list);
11078                 spin_unlock_irqrestore(
11079                         &per_cpu(blocked_vcpu_on_cpu_lock,
11080                         vcpu->pre_pcpu), flags);
11081                 vcpu->pre_pcpu = -1;
11082         }
11083 }
11084
11085 static void vmx_post_block(struct kvm_vcpu *vcpu)
11086 {
11087         if (kvm_x86_ops->set_hv_timer)
11088                 kvm_lapic_switch_to_hv_timer(vcpu);
11089
11090         pi_post_block(vcpu);
11091 }
11092
11093 /*
11094  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11095  *
11096  * @kvm: kvm
11097  * @host_irq: host irq of the interrupt
11098  * @guest_irq: gsi of the interrupt
11099  * @set: set or unset PI
11100  * returns 0 on success, < 0 on failure
11101  */
11102 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
11103                               uint32_t guest_irq, bool set)
11104 {
11105         struct kvm_kernel_irq_routing_entry *e;
11106         struct kvm_irq_routing_table *irq_rt;
11107         struct kvm_lapic_irq irq;
11108         struct kvm_vcpu *vcpu;
11109         struct vcpu_data vcpu_info;
11110         int idx, ret = -EINVAL;
11111
11112         if (!kvm_arch_has_assigned_device(kvm) ||
11113                 !irq_remapping_cap(IRQ_POSTING_CAP))
11114                 return 0;
11115
11116         idx = srcu_read_lock(&kvm->irq_srcu);
11117         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
11118         BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
11119
11120         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
11121                 if (e->type != KVM_IRQ_ROUTING_MSI)
11122                         continue;
11123                 /*
11124                  * VT-d PI cannot support posting multicast/broadcast
11125                  * interrupts to a vCPU, we still use interrupt remapping
11126                  * for these kind of interrupts.
11127                  *
11128                  * For lowest-priority interrupts, we only support
11129                  * those with single CPU as the destination, e.g. user
11130                  * configures the interrupts via /proc/irq or uses
11131                  * irqbalance to make the interrupts single-CPU.
11132                  *
11133                  * We will support full lowest-priority interrupt later.
11134                  */
11135
11136                 kvm_set_msi_irq(kvm, e, &irq);
11137                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
11138                         /*
11139                          * Make sure the IRTE is in remapped mode if
11140                          * we don't handle it in posted mode.
11141                          */
11142                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11143                         if (ret < 0) {
11144                                 printk(KERN_INFO
11145                                    "failed to back to remapped mode, irq: %u\n",
11146                                    host_irq);
11147                                 goto out;
11148                         }
11149
11150                         continue;
11151                 }
11152
11153                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
11154                 vcpu_info.vector = irq.vector;
11155
11156                 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
11157                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
11158
11159                 if (set)
11160                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
11161                 else {
11162                         /* suppress notification event before unposting */
11163                         pi_set_sn(vcpu_to_pi_desc(vcpu));
11164                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11165                         pi_clear_sn(vcpu_to_pi_desc(vcpu));
11166                 }
11167
11168                 if (ret < 0) {
11169                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
11170                                         __func__);
11171                         goto out;
11172                 }
11173         }
11174
11175         ret = 0;
11176 out:
11177         srcu_read_unlock(&kvm->irq_srcu, idx);
11178         return ret;
11179 }
11180
11181 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
11182 {
11183         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
11184                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
11185                         FEATURE_CONTROL_LMCE;
11186         else
11187                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
11188                         ~FEATURE_CONTROL_LMCE;
11189 }
11190
11191 static struct kvm_x86_ops vmx_x86_ops = {
11192         .cpu_has_kvm_support = cpu_has_kvm_support,
11193         .disabled_by_bios = vmx_disabled_by_bios,
11194         .hardware_setup = hardware_setup,
11195         .hardware_unsetup = hardware_unsetup,
11196         .check_processor_compatibility = vmx_check_processor_compat,
11197         .hardware_enable = hardware_enable,
11198         .hardware_disable = hardware_disable,
11199         .cpu_has_accelerated_tpr = report_flexpriority,
11200         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
11201
11202         .vcpu_create = vmx_create_vcpu,
11203         .vcpu_free = vmx_free_vcpu,
11204         .vcpu_reset = vmx_vcpu_reset,
11205
11206         .prepare_guest_switch = vmx_save_host_state,
11207         .vcpu_load = vmx_vcpu_load,
11208         .vcpu_put = vmx_vcpu_put,
11209
11210         .update_bp_intercept = update_exception_bitmap,
11211         .get_msr = vmx_get_msr,
11212         .set_msr = vmx_set_msr,
11213         .get_segment_base = vmx_get_segment_base,
11214         .get_segment = vmx_get_segment,
11215         .set_segment = vmx_set_segment,
11216         .get_cpl = vmx_get_cpl,
11217         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
11218         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
11219         .decache_cr3 = vmx_decache_cr3,
11220         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
11221         .set_cr0 = vmx_set_cr0,
11222         .set_cr3 = vmx_set_cr3,
11223         .set_cr4 = vmx_set_cr4,
11224         .set_efer = vmx_set_efer,
11225         .get_idt = vmx_get_idt,
11226         .set_idt = vmx_set_idt,
11227         .get_gdt = vmx_get_gdt,
11228         .set_gdt = vmx_set_gdt,
11229         .get_dr6 = vmx_get_dr6,
11230         .set_dr6 = vmx_set_dr6,
11231         .set_dr7 = vmx_set_dr7,
11232         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
11233         .cache_reg = vmx_cache_reg,
11234         .get_rflags = vmx_get_rflags,
11235         .set_rflags = vmx_set_rflags,
11236
11237         .get_pkru = vmx_get_pkru,
11238
11239         .fpu_activate = vmx_fpu_activate,
11240         .fpu_deactivate = vmx_fpu_deactivate,
11241
11242         .tlb_flush = vmx_flush_tlb,
11243
11244         .run = vmx_vcpu_run,
11245         .handle_exit = vmx_handle_exit,
11246         .skip_emulated_instruction = skip_emulated_instruction,
11247         .set_interrupt_shadow = vmx_set_interrupt_shadow,
11248         .get_interrupt_shadow = vmx_get_interrupt_shadow,
11249         .patch_hypercall = vmx_patch_hypercall,
11250         .set_irq = vmx_inject_irq,
11251         .set_nmi = vmx_inject_nmi,
11252         .queue_exception = vmx_queue_exception,
11253         .cancel_injection = vmx_cancel_injection,
11254         .interrupt_allowed = vmx_interrupt_allowed,
11255         .nmi_allowed = vmx_nmi_allowed,
11256         .get_nmi_mask = vmx_get_nmi_mask,
11257         .set_nmi_mask = vmx_set_nmi_mask,
11258         .enable_nmi_window = enable_nmi_window,
11259         .enable_irq_window = enable_irq_window,
11260         .update_cr8_intercept = update_cr8_intercept,
11261         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
11262         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
11263         .get_enable_apicv = vmx_get_enable_apicv,
11264         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
11265         .load_eoi_exitmap = vmx_load_eoi_exitmap,
11266         .hwapic_irr_update = vmx_hwapic_irr_update,
11267         .hwapic_isr_update = vmx_hwapic_isr_update,
11268         .sync_pir_to_irr = vmx_sync_pir_to_irr,
11269         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
11270
11271         .set_tss_addr = vmx_set_tss_addr,
11272         .get_tdp_level = get_ept_level,
11273         .get_mt_mask = vmx_get_mt_mask,
11274
11275         .get_exit_info = vmx_get_exit_info,
11276
11277         .get_lpage_level = vmx_get_lpage_level,
11278
11279         .cpuid_update = vmx_cpuid_update,
11280
11281         .rdtscp_supported = vmx_rdtscp_supported,
11282         .invpcid_supported = vmx_invpcid_supported,
11283
11284         .set_supported_cpuid = vmx_set_supported_cpuid,
11285
11286         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
11287
11288         .read_tsc_offset = vmx_read_tsc_offset,
11289         .write_tsc_offset = vmx_write_tsc_offset,
11290         .adjust_tsc_offset_guest = vmx_adjust_tsc_offset_guest,
11291         .read_l1_tsc = vmx_read_l1_tsc,
11292
11293         .set_tdp_cr3 = vmx_set_cr3,
11294
11295         .check_intercept = vmx_check_intercept,
11296         .handle_external_intr = vmx_handle_external_intr,
11297         .mpx_supported = vmx_mpx_supported,
11298         .xsaves_supported = vmx_xsaves_supported,
11299
11300         .check_nested_events = vmx_check_nested_events,
11301
11302         .sched_in = vmx_sched_in,
11303
11304         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
11305         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
11306         .flush_log_dirty = vmx_flush_log_dirty,
11307         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
11308
11309         .pre_block = vmx_pre_block,
11310         .post_block = vmx_post_block,
11311
11312         .pmu_ops = &intel_pmu_ops,
11313
11314         .update_pi_irte = vmx_update_pi_irte,
11315
11316 #ifdef CONFIG_X86_64
11317         .set_hv_timer = vmx_set_hv_timer,
11318         .cancel_hv_timer = vmx_cancel_hv_timer,
11319 #endif
11320
11321         .setup_mce = vmx_setup_mce,
11322 };
11323
11324 static int __init vmx_init(void)
11325 {
11326         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
11327                      __alignof__(struct vcpu_vmx), THIS_MODULE);
11328         if (r)
11329                 return r;
11330
11331 #ifdef CONFIG_KEXEC_CORE
11332         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
11333                            crash_vmclear_local_loaded_vmcss);
11334 #endif
11335
11336         return 0;
11337 }
11338
11339 static void __exit vmx_exit(void)
11340 {
11341 #ifdef CONFIG_KEXEC_CORE
11342         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
11343         synchronize_rcu();
11344 #endif
11345
11346         kvm_exit();
11347 }
11348
11349 module_init(vmx_init)
11350 module_exit(vmx_exit)