arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22 #include "lapic.h"
  23
  24 #include <linux/kvm_host.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/mod_devicetable.h>
  32 #include <linux/trace_events.h>
  33 #include <linux/slab.h>
  34 #include <linux/tboot.h>
  35 #include <linux/hrtimer.h>
  36 #include "kvm_cache_regs.h"
  37 #include "x86.h"
  38
  39 #include <asm/cpu.h>
  40 #include <asm/io.h>
  41 #include <asm/desc.h>
  42 #include <asm/vmx.h>
  43 #include <asm/virtext.h>
  44 #include <asm/mce.h>
  45 #include <asm/fpu/internal.h>
  46 #include <asm/perf_event.h>
  47 #include <asm/debugreg.h>
  48 #include <asm/kexec.h>
  49 #include <asm/apic.h>
  50 #include <asm/irq_remapping.h>
  51
  52 #include "trace.h"
  53 #include "pmu.h"
  54
  55 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  56 #define __ex_clear(x, reg) \
  57         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  58
  59 MODULE_AUTHOR("Qumranet");
  60 MODULE_LICENSE("GPL");
  61
  62 static const struct x86_cpu_id vmx_cpu_id[] = {
  63         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  64         {}
  65 };
  66 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  67
  68 static bool __read_mostly enable_vpid = 1;
  69 module_param_named(vpid, enable_vpid, bool, 0444);
  70
  71 static bool __read_mostly flexpriority_enabled = 1;
  72 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  73
  74 static bool __read_mostly enable_ept = 1;
  75 module_param_named(ept, enable_ept, bool, S_IRUGO);
  76
  77 static bool __read_mostly enable_unrestricted_guest = 1;
  78 module_param_named(unrestricted_guest,
  79                         enable_unrestricted_guest, bool, S_IRUGO);
  80
  81 static bool __read_mostly enable_ept_ad_bits = 1;
  82 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  83
  84 static bool __read_mostly emulate_invalid_guest_state = true;
  85 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  86
  87 static bool __read_mostly vmm_exclusive = 1;
  88 module_param(vmm_exclusive, bool, S_IRUGO);
  89
  90 static bool __read_mostly fasteoi = 1;
  91 module_param(fasteoi, bool, S_IRUGO);
  92
  93 static bool __read_mostly enable_apicv = 1;
  94 module_param(enable_apicv, bool, S_IRUGO);
  95
  96 static bool __read_mostly enable_shadow_vmcs = 1;
  97 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  98 /*
  99  * If nested=1, nested virtualization is supported, i.e., guests may use
 100  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 101  * use VMX instructions.
 102  */
 103 static bool __read_mostly nested = 0;
 104 module_param(nested, bool, S_IRUGO);
 105
 106 static u64 __read_mostly host_xss;
 107
 108 static bool __read_mostly enable_pml = 1;
 109 module_param_named(pml, enable_pml, bool, S_IRUGO);
 110
 111 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 112
 113 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 114 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 115 #define KVM_VM_CR0_ALWAYS_ON                                            \
 116         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 117 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 118         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 119          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 120
 121 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 122 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 123
 124 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 125
 126 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 127
 128 /*
 129  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 130  * ple_gap:    upper bound on the amount of time between two successive
 131  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 132  *             According to test, this time is usually smaller than 128 cycles.
 133  * ple_window: upper bound on the amount of time a guest is allowed to execute
 134  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 135  *             less than 2^12 cycles
 136  * Time is measured based on a counter that runs at the same rate as the TSC,
 137  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 138  */
 139 #define KVM_VMX_DEFAULT_PLE_GAP           128
 140 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 141 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 142 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 143 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 144                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 145
 146 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 147 module_param(ple_gap, int, S_IRUGO);
 148
 149 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 150 module_param(ple_window, int, S_IRUGO);
 151
 152 /* Default doubles per-vcpu window every exit. */
 153 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 154 module_param(ple_window_grow, int, S_IRUGO);
 155
 156 /* Default resets per-vcpu window every exit to ple_window. */
 157 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 158 module_param(ple_window_shrink, int, S_IRUGO);
 159
 160 /* Default is to compute the maximum so we can never overflow. */
 161 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 162 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 163 module_param(ple_window_max, int, S_IRUGO);
 164
 165 extern const ulong vmx_return;
 166
 167 #define NR_AUTOLOAD_MSRS 8
 168 #define VMCS02_POOL_SIZE 1
 169
 170 struct vmcs {
 171         u32 revision_id;
 172         u32 abort;
 173         char data[0];
 174 };
 175
 176 /*
 177  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 178  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 179  * loaded on this CPU (so we can clear them if the CPU goes down).
 180  */
 181 struct loaded_vmcs {
 182         struct vmcs *vmcs;
 183         int cpu;
 184         int launched;
 185         struct list_head loaded_vmcss_on_cpu_link;
 186 };
 187
 188 struct shared_msr_entry {
 189         unsigned index;
 190         u64 data;
 191         u64 mask;
 192 };
 193
 194 /*
 195  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 196  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 197  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 198  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 199  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 200  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 201  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 202  * underlying hardware which will be used to run L2.
 203  * This structure is packed to ensure that its layout is identical across
 204  * machines (necessary for live migration).
 205  * If there are changes in this struct, VMCS12_REVISION must be changed.
 206  */
 207 typedef u64 natural_width;
 208 struct __packed vmcs12 {
 209         /* According to the Intel spec, a VMCS region must start with the
 210          * following two fields. Then follow implementation-specific data.
 211          */
 212         u32 revision_id;
 213         u32 abort;
 214
 215         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 216         u32 padding[7]; /* room for future expansion */
 217
 218         u64 io_bitmap_a;
 219         u64 io_bitmap_b;
 220         u64 msr_bitmap;
 221         u64 vm_exit_msr_store_addr;
 222         u64 vm_exit_msr_load_addr;
 223         u64 vm_entry_msr_load_addr;
 224         u64 tsc_offset;
 225         u64 virtual_apic_page_addr;
 226         u64 apic_access_addr;
 227         u64 posted_intr_desc_addr;
 228         u64 ept_pointer;
 229         u64 eoi_exit_bitmap0;
 230         u64 eoi_exit_bitmap1;
 231         u64 eoi_exit_bitmap2;
 232         u64 eoi_exit_bitmap3;
 233         u64 xss_exit_bitmap;
 234         u64 guest_physical_address;
 235         u64 vmcs_link_pointer;
 236         u64 guest_ia32_debugctl;
 237         u64 guest_ia32_pat;
 238         u64 guest_ia32_efer;
 239         u64 guest_ia32_perf_global_ctrl;
 240         u64 guest_pdptr0;
 241         u64 guest_pdptr1;
 242         u64 guest_pdptr2;
 243         u64 guest_pdptr3;
 244         u64 guest_bndcfgs;
 245         u64 host_ia32_pat;
 246         u64 host_ia32_efer;
 247         u64 host_ia32_perf_global_ctrl;
 248         u64 padding64[8]; /* room for future expansion */
 249         /*
 250          * To allow migration of L1 (complete with its L2 guests) between
 251          * machines of different natural widths (32 or 64 bit), we cannot have
 252          * unsigned long fields with no explict size. We use u64 (aliased
 253          * natural_width) instead. Luckily, x86 is little-endian.
 254          */
 255         natural_width cr0_guest_host_mask;
 256         natural_width cr4_guest_host_mask;
 257         natural_width cr0_read_shadow;
 258         natural_width cr4_read_shadow;
 259         natural_width cr3_target_value0;
 260         natural_width cr3_target_value1;
 261         natural_width cr3_target_value2;
 262         natural_width cr3_target_value3;
 263         natural_width exit_qualification;
 264         natural_width guest_linear_address;
 265         natural_width guest_cr0;
 266         natural_width guest_cr3;
 267         natural_width guest_cr4;
 268         natural_width guest_es_base;
 269         natural_width guest_cs_base;
 270         natural_width guest_ss_base;
 271         natural_width guest_ds_base;
 272         natural_width guest_fs_base;
 273         natural_width guest_gs_base;
 274         natural_width guest_ldtr_base;
 275         natural_width guest_tr_base;
 276         natural_width guest_gdtr_base;
 277         natural_width guest_idtr_base;
 278         natural_width guest_dr7;
 279         natural_width guest_rsp;
 280         natural_width guest_rip;
 281         natural_width guest_rflags;
 282         natural_width guest_pending_dbg_exceptions;
 283         natural_width guest_sysenter_esp;
 284         natural_width guest_sysenter_eip;
 285         natural_width host_cr0;
 286         natural_width host_cr3;
 287         natural_width host_cr4;
 288         natural_width host_fs_base;
 289         natural_width host_gs_base;
 290         natural_width host_tr_base;
 291         natural_width host_gdtr_base;
 292         natural_width host_idtr_base;
 293         natural_width host_ia32_sysenter_esp;
 294         natural_width host_ia32_sysenter_eip;
 295         natural_width host_rsp;
 296         natural_width host_rip;
 297         natural_width paddingl[8]; /* room for future expansion */
 298         u32 pin_based_vm_exec_control;
 299         u32 cpu_based_vm_exec_control;
 300         u32 exception_bitmap;
 301         u32 page_fault_error_code_mask;
 302         u32 page_fault_error_code_match;
 303         u32 cr3_target_count;
 304         u32 vm_exit_controls;
 305         u32 vm_exit_msr_store_count;
 306         u32 vm_exit_msr_load_count;
 307         u32 vm_entry_controls;
 308         u32 vm_entry_msr_load_count;
 309         u32 vm_entry_intr_info_field;
 310         u32 vm_entry_exception_error_code;
 311         u32 vm_entry_instruction_len;
 312         u32 tpr_threshold;
 313         u32 secondary_vm_exec_control;
 314         u32 vm_instruction_error;
 315         u32 vm_exit_reason;
 316         u32 vm_exit_intr_info;
 317         u32 vm_exit_intr_error_code;
 318         u32 idt_vectoring_info_field;
 319         u32 idt_vectoring_error_code;
 320         u32 vm_exit_instruction_len;
 321         u32 vmx_instruction_info;
 322         u32 guest_es_limit;
 323         u32 guest_cs_limit;
 324         u32 guest_ss_limit;
 325         u32 guest_ds_limit;
 326         u32 guest_fs_limit;
 327         u32 guest_gs_limit;
 328         u32 guest_ldtr_limit;
 329         u32 guest_tr_limit;
 330         u32 guest_gdtr_limit;
 331         u32 guest_idtr_limit;
 332         u32 guest_es_ar_bytes;
 333         u32 guest_cs_ar_bytes;
 334         u32 guest_ss_ar_bytes;
 335         u32 guest_ds_ar_bytes;
 336         u32 guest_fs_ar_bytes;
 337         u32 guest_gs_ar_bytes;
 338         u32 guest_ldtr_ar_bytes;
 339         u32 guest_tr_ar_bytes;
 340         u32 guest_interruptibility_info;
 341         u32 guest_activity_state;
 342         u32 guest_sysenter_cs;
 343         u32 host_ia32_sysenter_cs;
 344         u32 vmx_preemption_timer_value;
 345         u32 padding32[7]; /* room for future expansion */
 346         u16 virtual_processor_id;
 347         u16 posted_intr_nv;
 348         u16 guest_es_selector;
 349         u16 guest_cs_selector;
 350         u16 guest_ss_selector;
 351         u16 guest_ds_selector;
 352         u16 guest_fs_selector;
 353         u16 guest_gs_selector;
 354         u16 guest_ldtr_selector;
 355         u16 guest_tr_selector;
 356         u16 guest_intr_status;
 357         u16 host_es_selector;
 358         u16 host_cs_selector;
 359         u16 host_ss_selector;
 360         u16 host_ds_selector;
 361         u16 host_fs_selector;
 362         u16 host_gs_selector;
 363         u16 host_tr_selector;
 364 };
 365
 366 /*
 367  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 368  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 369  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 370  */
 371 #define VMCS12_REVISION 0x11e57ed0
 372
 373 /*
 374  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 375  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 376  * current implementation, 4K are reserved to avoid future complications.
 377  */
 378 #define VMCS12_SIZE 0x1000
 379
 380 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 381 struct vmcs02_list {
 382         struct list_head list;
 383         gpa_t vmptr;
 384         struct loaded_vmcs vmcs02;
 385 };
 386
 387 /*
 388  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 389  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 390  */
 391 struct nested_vmx {
 392         /* Has the level1 guest done vmxon? */
 393         bool vmxon;
 394         gpa_t vmxon_ptr;
 395
 396         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 397         gpa_t current_vmptr;
 398         /* The host-usable pointer to the above */
 399         struct page *current_vmcs12_page;
 400         struct vmcs12 *current_vmcs12;
 401         struct vmcs *current_shadow_vmcs;
 402         /*
 403          * Indicates if the shadow vmcs must be updated with the
 404          * data hold by vmcs12
 405          */
 406         bool sync_shadow_vmcs;
 407
 408         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 409         struct list_head vmcs02_pool;
 410         int vmcs02_num;
 411         u64 vmcs01_tsc_offset;
 412         /* L2 must run next, and mustn't decide to exit to L1. */
 413         bool nested_run_pending;
 414         /*
 415          * Guest pages referred to in vmcs02 with host-physical pointers, so
 416          * we must keep them pinned while L2 runs.
 417          */
 418         struct page *apic_access_page;
 419         struct page *virtual_apic_page;
 420         struct page *pi_desc_page;
 421         struct pi_desc *pi_desc;
 422         bool pi_pending;
 423         u16 posted_intr_nv;
 424         u64 msr_ia32_feature_control;
 425
 426         struct hrtimer preemption_timer;
 427         bool preemption_timer_expired;
 428
 429         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 430         u64 vmcs01_debugctl;
 431
 432         u16 vpid02;
 433         u16 last_vpid;
 434
 435         u32 nested_vmx_procbased_ctls_low;
 436         u32 nested_vmx_procbased_ctls_high;
 437         u32 nested_vmx_true_procbased_ctls_low;
 438         u32 nested_vmx_secondary_ctls_low;
 439         u32 nested_vmx_secondary_ctls_high;
 440         u32 nested_vmx_pinbased_ctls_low;
 441         u32 nested_vmx_pinbased_ctls_high;
 442         u32 nested_vmx_exit_ctls_low;
 443         u32 nested_vmx_exit_ctls_high;
 444         u32 nested_vmx_true_exit_ctls_low;
 445         u32 nested_vmx_entry_ctls_low;
 446         u32 nested_vmx_entry_ctls_high;
 447         u32 nested_vmx_true_entry_ctls_low;
 448         u32 nested_vmx_misc_low;
 449         u32 nested_vmx_misc_high;
 450         u32 nested_vmx_ept_caps;
 451         u32 nested_vmx_vpid_caps;
 452 };
 453
 454 #define POSTED_INTR_ON  0
 455 #define POSTED_INTR_SN  1
 456
 457 /* Posted-Interrupt Descriptor */
 458 struct pi_desc {
 459         u32 pir[8];     /* Posted interrupt requested */
 460         union {
 461                 struct {
 462                                 /* bit 256 - Outstanding Notification */
 463                         u16     on      : 1,
 464                                 /* bit 257 - Suppress Notification */
 465                                 sn      : 1,
 466                                 /* bit 271:258 - Reserved */
 467                                 rsvd_1  : 14;
 468                                 /* bit 279:272 - Notification Vector */
 469                         u8      nv;
 470                                 /* bit 287:280 - Reserved */
 471                         u8      rsvd_2;
 472                                 /* bit 319:288 - Notification Destination */
 473                         u32     ndst;
 474                 };
 475                 u64 control;
 476         };
 477         u32 rsvd[6];
 478 } __aligned(64);
 479
 480 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 481 {
 482         return test_and_set_bit(POSTED_INTR_ON,
 483                         (unsigned long *)&pi_desc->control);
 484 }
 485
 486 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 487 {
 488         return test_and_clear_bit(POSTED_INTR_ON,
 489                         (unsigned long *)&pi_desc->control);
 490 }
 491
 492 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 493 {
 494         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 495 }
 496
 497 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 498 {
 499         return clear_bit(POSTED_INTR_SN,
 500                         (unsigned long *)&pi_desc->control);
 501 }
 502
 503 static inline void pi_set_sn(struct pi_desc *pi_desc)
 504 {
 505         return set_bit(POSTED_INTR_SN,
 506                         (unsigned long *)&pi_desc->control);
 507 }
 508
 509 static inline int pi_test_on(struct pi_desc *pi_desc)
 510 {
 511         return test_bit(POSTED_INTR_ON,
 512                         (unsigned long *)&pi_desc->control);
 513 }
 514
 515 static inline int pi_test_sn(struct pi_desc *pi_desc)
 516 {
 517         return test_bit(POSTED_INTR_SN,
 518                         (unsigned long *)&pi_desc->control);
 519 }
 520
 521 struct vcpu_vmx {
 522         struct kvm_vcpu       vcpu;
 523         unsigned long         host_rsp;
 524         u8                    fail;
 525         bool                  nmi_known_unmasked;
 526         u32                   exit_intr_info;
 527         u32                   idt_vectoring_info;
 528         ulong                 rflags;
 529         struct shared_msr_entry *guest_msrs;
 530         int                   nmsrs;
 531         int                   save_nmsrs;
 532         unsigned long         host_idt_base;
 533 #ifdef CONFIG_X86_64
 534         u64                   msr_host_kernel_gs_base;
 535         u64                   msr_guest_kernel_gs_base;
 536 #endif
 537         u32 vm_entry_controls_shadow;
 538         u32 vm_exit_controls_shadow;
 539         /*
 540          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 541          * non-nested (L1) guest, it always points to vmcs01. For a nested
 542          * guest (L2), it points to a different VMCS.
 543          */
 544         struct loaded_vmcs    vmcs01;
 545         struct loaded_vmcs   *loaded_vmcs;
 546         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 547         struct msr_autoload {
 548                 unsigned nr;
 549                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 550                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 551         } msr_autoload;
 552         struct {
 553                 int           loaded;
 554                 u16           fs_sel, gs_sel, ldt_sel;
 555 #ifdef CONFIG_X86_64
 556                 u16           ds_sel, es_sel;
 557 #endif
 558                 int           gs_ldt_reload_needed;
 559                 int           fs_reload_needed;
 560                 u64           msr_host_bndcfgs;
 561                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 562         } host_state;
 563         struct {
 564                 int vm86_active;
 565                 ulong save_rflags;
 566                 struct kvm_segment segs[8];
 567         } rmode;
 568         struct {
 569                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 570                 struct kvm_save_segment {
 571                         u16 selector;
 572                         unsigned long base;
 573                         u32 limit;
 574                         u32 ar;
 575                 } seg[8];
 576         } segment_cache;
 577         int vpid;
 578         bool emulation_required;
 579
 580         /* Support for vnmi-less CPUs */
 581         int soft_vnmi_blocked;
 582         ktime_t entry_time;
 583         s64 vnmi_blocked_time;
 584         u32 exit_reason;
 585
 586         /* Posted interrupt descriptor */
 587         struct pi_desc pi_desc;
 588
 589         /* Support for a guest hypervisor (nested VMX) */
 590         struct nested_vmx nested;
 591
 592         /* Dynamic PLE window. */
 593         int ple_window;
 594         bool ple_window_dirty;
 595
 596         /* Support for PML */
 597 #define PML_ENTITY_NUM          512
 598         struct page *pml_pg;
 599
 600         u64 current_tsc_ratio;
 601
 602         bool guest_pkru_valid;
 603         u32 guest_pkru;
 604         u32 host_pkru;
 605 };
 606
 607 enum segment_cache_field {
 608         SEG_FIELD_SEL = 0,
 609         SEG_FIELD_BASE = 1,
 610         SEG_FIELD_LIMIT = 2,
 611         SEG_FIELD_AR = 3,
 612
 613         SEG_FIELD_NR = 4
 614 };
 615
 616 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 617 {
 618         return container_of(vcpu, struct vcpu_vmx, vcpu);
 619 }
 620
 621 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 622 {
 623         return &(to_vmx(vcpu)->pi_desc);
 624 }
 625
 626 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 627 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 628 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 629                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 630
 631
 632 static unsigned long shadow_read_only_fields[] = {
 633         /*
 634          * We do NOT shadow fields that are modified when L0
 635          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 636          * VMXON...) executed by L1.
 637          * For example, VM_INSTRUCTION_ERROR is read
 638          * by L1 if a vmx instruction fails (part of the error path).
 639          * Note the code assumes this logic. If for some reason
 640          * we start shadowing these fields then we need to
 641          * force a shadow sync when L0 emulates vmx instructions
 642          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 643          * by nested_vmx_failValid)
 644          */
 645         VM_EXIT_REASON,
 646         VM_EXIT_INTR_INFO,
 647         VM_EXIT_INSTRUCTION_LEN,
 648         IDT_VECTORING_INFO_FIELD,
 649         IDT_VECTORING_ERROR_CODE,
 650         VM_EXIT_INTR_ERROR_CODE,
 651         EXIT_QUALIFICATION,
 652         GUEST_LINEAR_ADDRESS,
 653         GUEST_PHYSICAL_ADDRESS
 654 };
 655 static int max_shadow_read_only_fields =
 656         ARRAY_SIZE(shadow_read_only_fields);
 657
 658 static unsigned long shadow_read_write_fields[] = {
 659         TPR_THRESHOLD,
 660         GUEST_RIP,
 661         GUEST_RSP,
 662         GUEST_CR0,
 663         GUEST_CR3,
 664         GUEST_CR4,
 665         GUEST_INTERRUPTIBILITY_INFO,
 666         GUEST_RFLAGS,
 667         GUEST_CS_SELECTOR,
 668         GUEST_CS_AR_BYTES,
 669         GUEST_CS_LIMIT,
 670         GUEST_CS_BASE,
 671         GUEST_ES_BASE,
 672         GUEST_BNDCFGS,
 673         CR0_GUEST_HOST_MASK,
 674         CR0_READ_SHADOW,
 675         CR4_READ_SHADOW,
 676         TSC_OFFSET,
 677         EXCEPTION_BITMAP,
 678         CPU_BASED_VM_EXEC_CONTROL,
 679         VM_ENTRY_EXCEPTION_ERROR_CODE,
 680         VM_ENTRY_INTR_INFO_FIELD,
 681         VM_ENTRY_INSTRUCTION_LEN,
 682         VM_ENTRY_EXCEPTION_ERROR_CODE,
 683         HOST_FS_BASE,
 684         HOST_GS_BASE,
 685         HOST_FS_SELECTOR,
 686         HOST_GS_SELECTOR
 687 };
 688 static int max_shadow_read_write_fields =
 689         ARRAY_SIZE(shadow_read_write_fields);
 690
 691 static const unsigned short vmcs_field_to_offset_table[] = {
 692         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 693         FIELD(POSTED_INTR_NV, posted_intr_nv),
 694         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 695         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 696         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 697         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 698         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 699         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 700         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 701         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 702         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 703         FIELD(HOST_ES_SELECTOR, host_es_selector),
 704         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 705         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 706         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 707         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 708         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 709         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 710         FIELD64(IO_BITMAP_A, io_bitmap_a),
 711         FIELD64(IO_BITMAP_B, io_bitmap_b),
 712         FIELD64(MSR_BITMAP, msr_bitmap),
 713         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 714         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 715         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 716         FIELD64(TSC_OFFSET, tsc_offset),
 717         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 718         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 719         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 720         FIELD64(EPT_POINTER, ept_pointer),
 721         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 722         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 723         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 724         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 725         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 726         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 727         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 728         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 729         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 730         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 731         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 732         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 733         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 734         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 735         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 736         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 737         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 738         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 739         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 740         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 741         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 742         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 743         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 744         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 745         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 746         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 747         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 748         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 749         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 750         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 751         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 752         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 753         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 754         FIELD(TPR_THRESHOLD, tpr_threshold),
 755         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 756         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 757         FIELD(VM_EXIT_REASON, vm_exit_reason),
 758         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 759         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 760         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 761         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 762         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 763         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 764         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 765         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 766         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 767         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 768         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 769         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 770         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 771         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 772         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 773         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 774         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 775         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 776         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 777         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 778         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 779         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 780         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 781         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 782         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 783         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 784         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 785         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 786         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 787         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 788         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 789         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 790         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 791         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 792         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 793         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 794         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 795         FIELD(EXIT_QUALIFICATION, exit_qualification),
 796         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 797         FIELD(GUEST_CR0, guest_cr0),
 798         FIELD(GUEST_CR3, guest_cr3),
 799         FIELD(GUEST_CR4, guest_cr4),
 800         FIELD(GUEST_ES_BASE, guest_es_base),
 801         FIELD(GUEST_CS_BASE, guest_cs_base),
 802         FIELD(GUEST_SS_BASE, guest_ss_base),
 803         FIELD(GUEST_DS_BASE, guest_ds_base),
 804         FIELD(GUEST_FS_BASE, guest_fs_base),
 805         FIELD(GUEST_GS_BASE, guest_gs_base),
 806         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 807         FIELD(GUEST_TR_BASE, guest_tr_base),
 808         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 809         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 810         FIELD(GUEST_DR7, guest_dr7),
 811         FIELD(GUEST_RSP, guest_rsp),
 812         FIELD(GUEST_RIP, guest_rip),
 813         FIELD(GUEST_RFLAGS, guest_rflags),
 814         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 815         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 816         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 817         FIELD(HOST_CR0, host_cr0),
 818         FIELD(HOST_CR3, host_cr3),
 819         FIELD(HOST_CR4, host_cr4),
 820         FIELD(HOST_FS_BASE, host_fs_base),
 821         FIELD(HOST_GS_BASE, host_gs_base),
 822         FIELD(HOST_TR_BASE, host_tr_base),
 823         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 824         FIELD(HOST_IDTR_BASE, host_idtr_base),
 825         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 826         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 827         FIELD(HOST_RSP, host_rsp),
 828         FIELD(HOST_RIP, host_rip),
 829 };
 830
 831 static inline short vmcs_field_to_offset(unsigned long field)
 832 {
 833         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 834
 835         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 836             vmcs_field_to_offset_table[field] == 0)
 837                 return -ENOENT;
 838
 839         return vmcs_field_to_offset_table[field];
 840 }
 841
 842 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 843 {
 844         return to_vmx(vcpu)->nested.current_vmcs12;
 845 }
 846
 847 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 848 {
 849         struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
 850         if (is_error_page(page))
 851                 return NULL;
 852
 853         return page;
 854 }
 855
 856 static void nested_release_page(struct page *page)
 857 {
 858         kvm_release_page_dirty(page);
 859 }
 860
 861 static void nested_release_page_clean(struct page *page)
 862 {
 863         kvm_release_page_clean(page);
 864 }
 865
 866 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 867 static u64 construct_eptp(unsigned long root_hpa);
 868 static void kvm_cpu_vmxon(u64 addr);
 869 static void kvm_cpu_vmxoff(void);
 870 static bool vmx_xsaves_supported(void);
 871 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 872 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 873                             struct kvm_segment *var, int seg);
 874 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 875                             struct kvm_segment *var, int seg);
 876 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 877 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 878 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 879 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 880 static int alloc_identity_pagetable(struct kvm *kvm);
 881
 882 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 883 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 884 /*
 885  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 886  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 887  */
 888 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 889 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 890
 891 /*
 892  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 893  * can find which vCPU should be waken up.
 894  */
 895 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 896 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 897
 898 static unsigned long *vmx_io_bitmap_a;
 899 static unsigned long *vmx_io_bitmap_b;
 900 static unsigned long *vmx_msr_bitmap_legacy;
 901 static unsigned long *vmx_msr_bitmap_longmode;
 902 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 903 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 904 static unsigned long *vmx_msr_bitmap_nested;
 905 static unsigned long *vmx_vmread_bitmap;
 906 static unsigned long *vmx_vmwrite_bitmap;
 907
 908 static bool cpu_has_load_ia32_efer;
 909 static bool cpu_has_load_perf_global_ctrl;
 910
 911 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 912 static DEFINE_SPINLOCK(vmx_vpid_lock);
 913
 914 static struct vmcs_config {
 915         int size;
 916         int order;
 917         u32 revision_id;
 918         u32 pin_based_exec_ctrl;
 919         u32 cpu_based_exec_ctrl;
 920         u32 cpu_based_2nd_exec_ctrl;
 921         u32 vmexit_ctrl;
 922         u32 vmentry_ctrl;
 923 } vmcs_config;
 924
 925 static struct vmx_capability {
 926         u32 ept;
 927         u32 vpid;
 928 } vmx_capability;
 929
 930 #define VMX_SEGMENT_FIELD(seg)                                  \
 931         [VCPU_SREG_##seg] = {                                   \
 932                 .selector = GUEST_##seg##_SELECTOR,             \
 933                 .base = GUEST_##seg##_BASE,                     \
 934                 .limit = GUEST_##seg##_LIMIT,                   \
 935                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 936         }
 937
 938 static const struct kvm_vmx_segment_field {
 939         unsigned selector;
 940         unsigned base;
 941         unsigned limit;
 942         unsigned ar_bytes;
 943 } kvm_vmx_segment_fields[] = {
 944         VMX_SEGMENT_FIELD(CS),
 945         VMX_SEGMENT_FIELD(DS),
 946         VMX_SEGMENT_FIELD(ES),
 947         VMX_SEGMENT_FIELD(FS),
 948         VMX_SEGMENT_FIELD(GS),
 949         VMX_SEGMENT_FIELD(SS),
 950         VMX_SEGMENT_FIELD(TR),
 951         VMX_SEGMENT_FIELD(LDTR),
 952 };
 953
 954 static u64 host_efer;
 955
 956 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 957
 958 /*
 959  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 960  * away by decrementing the array size.
 961  */
 962 static const u32 vmx_msr_index[] = {
 963 #ifdef CONFIG_X86_64
 964         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 965 #endif
 966         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 967 };
 968
 969 static inline bool is_exception_n(u32 intr_info, u8 vector)
 970 {
 971         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 972                              INTR_INFO_VALID_MASK)) ==
 973                 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
 974 }
 975
 976 static inline bool is_debug(u32 intr_info)
 977 {
 978         return is_exception_n(intr_info, DB_VECTOR);
 979 }
 980
 981 static inline bool is_breakpoint(u32 intr_info)
 982 {
 983         return is_exception_n(intr_info, BP_VECTOR);
 984 }
 985
 986 static inline bool is_page_fault(u32 intr_info)
 987 {
 988         return is_exception_n(intr_info, PF_VECTOR);
 989 }
 990
 991 static inline bool is_no_device(u32 intr_info)
 992 {
 993         return is_exception_n(intr_info, NM_VECTOR);
 994 }
 995
 996 static inline bool is_invalid_opcode(u32 intr_info)
 997 {
 998         return is_exception_n(intr_info, UD_VECTOR);
 999 }
1000
1001 static inline bool is_external_interrupt(u32 intr_info)
1002 {
1003         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1004                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1005 }
1006
1007 static inline bool is_machine_check(u32 intr_info)
1008 {
1009         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1010                              INTR_INFO_VALID_MASK)) ==
1011                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1012 }
1013
1014 static inline bool cpu_has_vmx_msr_bitmap(void)
1015 {
1016         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1017 }
1018
1019 static inline bool cpu_has_vmx_tpr_shadow(void)
1020 {
1021         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1022 }
1023
1024 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1025 {
1026         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1027 }
1028
1029 static inline bool cpu_has_secondary_exec_ctrls(void)
1030 {
1031         return vmcs_config.cpu_based_exec_ctrl &
1032                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1033 }
1034
1035 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1036 {
1037         return vmcs_config.cpu_based_2nd_exec_ctrl &
1038                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1039 }
1040
1041 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1042 {
1043         return vmcs_config.cpu_based_2nd_exec_ctrl &
1044                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1045 }
1046
1047 static inline bool cpu_has_vmx_apic_register_virt(void)
1048 {
1049         return vmcs_config.cpu_based_2nd_exec_ctrl &
1050                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1051 }
1052
1053 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1054 {
1055         return vmcs_config.cpu_based_2nd_exec_ctrl &
1056                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1057 }
1058
1059 static inline bool cpu_has_vmx_posted_intr(void)
1060 {
1061         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1062                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1063 }
1064
1065 static inline bool cpu_has_vmx_apicv(void)
1066 {
1067         return cpu_has_vmx_apic_register_virt() &&
1068                 cpu_has_vmx_virtual_intr_delivery() &&
1069                 cpu_has_vmx_posted_intr();
1070 }
1071
1072 static inline bool cpu_has_vmx_flexpriority(void)
1073 {
1074         return cpu_has_vmx_tpr_shadow() &&
1075                 cpu_has_vmx_virtualize_apic_accesses();
1076 }
1077
1078 static inline bool cpu_has_vmx_ept_execute_only(void)
1079 {
1080         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1081 }
1082
1083 static inline bool cpu_has_vmx_ept_2m_page(void)
1084 {
1085         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1086 }
1087
1088 static inline bool cpu_has_vmx_ept_1g_page(void)
1089 {
1090         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1091 }
1092
1093 static inline bool cpu_has_vmx_ept_4levels(void)
1094 {
1095         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1096 }
1097
1098 static inline bool cpu_has_vmx_ept_ad_bits(void)
1099 {
1100         return vmx_capability.ept & VMX_EPT_AD_BIT;
1101 }
1102
1103 static inline bool cpu_has_vmx_invept_context(void)
1104 {
1105         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1106 }
1107
1108 static inline bool cpu_has_vmx_invept_global(void)
1109 {
1110         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1111 }
1112
1113 static inline bool cpu_has_vmx_invvpid_single(void)
1114 {
1115         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1116 }
1117
1118 static inline bool cpu_has_vmx_invvpid_global(void)
1119 {
1120         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1121 }
1122
1123 static inline bool cpu_has_vmx_ept(void)
1124 {
1125         return vmcs_config.cpu_based_2nd_exec_ctrl &
1126                 SECONDARY_EXEC_ENABLE_EPT;
1127 }
1128
1129 static inline bool cpu_has_vmx_unrestricted_guest(void)
1130 {
1131         return vmcs_config.cpu_based_2nd_exec_ctrl &
1132                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1133 }
1134
1135 static inline bool cpu_has_vmx_ple(void)
1136 {
1137         return vmcs_config.cpu_based_2nd_exec_ctrl &
1138                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1139 }
1140
1141 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1142 {
1143         return flexpriority_enabled && lapic_in_kernel(vcpu);
1144 }
1145
1146 static inline bool cpu_has_vmx_vpid(void)
1147 {
1148         return vmcs_config.cpu_based_2nd_exec_ctrl &
1149                 SECONDARY_EXEC_ENABLE_VPID;
1150 }
1151
1152 static inline bool cpu_has_vmx_rdtscp(void)
1153 {
1154         return vmcs_config.cpu_based_2nd_exec_ctrl &
1155                 SECONDARY_EXEC_RDTSCP;
1156 }
1157
1158 static inline bool cpu_has_vmx_invpcid(void)
1159 {
1160         return vmcs_config.cpu_based_2nd_exec_ctrl &
1161                 SECONDARY_EXEC_ENABLE_INVPCID;
1162 }
1163
1164 static inline bool cpu_has_virtual_nmis(void)
1165 {
1166         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1167 }
1168
1169 static inline bool cpu_has_vmx_wbinvd_exit(void)
1170 {
1171         return vmcs_config.cpu_based_2nd_exec_ctrl &
1172                 SECONDARY_EXEC_WBINVD_EXITING;
1173 }
1174
1175 static inline bool cpu_has_vmx_shadow_vmcs(void)
1176 {
1177         u64 vmx_msr;
1178         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1179         /* check if the cpu supports writing r/o exit information fields */
1180         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1181                 return false;
1182
1183         return vmcs_config.cpu_based_2nd_exec_ctrl &
1184                 SECONDARY_EXEC_SHADOW_VMCS;
1185 }
1186
1187 static inline bool cpu_has_vmx_pml(void)
1188 {
1189         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1190 }
1191
1192 static inline bool cpu_has_vmx_tsc_scaling(void)
1193 {
1194         return vmcs_config.cpu_based_2nd_exec_ctrl &
1195                 SECONDARY_EXEC_TSC_SCALING;
1196 }
1197
1198 static inline bool report_flexpriority(void)
1199 {
1200         return flexpriority_enabled;
1201 }
1202
1203 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1204 {
1205         return vmcs12->cpu_based_vm_exec_control & bit;
1206 }
1207
1208 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1209 {
1210         return (vmcs12->cpu_based_vm_exec_control &
1211                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1212                 (vmcs12->secondary_vm_exec_control & bit);
1213 }
1214
1215 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1216 {
1217         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1218 }
1219
1220 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1221 {
1222         return vmcs12->pin_based_vm_exec_control &
1223                 PIN_BASED_VMX_PREEMPTION_TIMER;
1224 }
1225
1226 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1227 {
1228         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1229 }
1230
1231 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1232 {
1233         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1234                 vmx_xsaves_supported();
1235 }
1236
1237 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1238 {
1239         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1240 }
1241
1242 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1243 {
1244         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1245 }
1246
1247 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1248 {
1249         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1250 }
1251
1252 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1253 {
1254         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1255 }
1256
1257 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1258 {
1259         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1260 }
1261
1262 static inline bool is_exception(u32 intr_info)
1263 {
1264         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1265                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1266 }
1267
1268 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1269                               u32 exit_intr_info,
1270                               unsigned long exit_qualification);
1271 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1272                         struct vmcs12 *vmcs12,
1273                         u32 reason, unsigned long qualification);
1274
1275 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1276 {
1277         int i;
1278
1279         for (i = 0; i < vmx->nmsrs; ++i)
1280                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1281                         return i;
1282         return -1;
1283 }
1284
1285 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1286 {
1287     struct {
1288         u64 vpid : 16;
1289         u64 rsvd : 48;
1290         u64 gva;
1291     } operand = { vpid, 0, gva };
1292
1293     asm volatile (__ex(ASM_VMX_INVVPID)
1294                   /* CF==1 or ZF==1 --> rc = -1 */
1295                   "; ja 1f ; ud2 ; 1:"
1296                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1297 }
1298
1299 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1300 {
1301         struct {
1302                 u64 eptp, gpa;
1303         } operand = {eptp, gpa};
1304
1305         asm volatile (__ex(ASM_VMX_INVEPT)
1306                         /* CF==1 or ZF==1 --> rc = -1 */
1307                         "; ja 1f ; ud2 ; 1:\n"
1308                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1309 }
1310
1311 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1312 {
1313         int i;
1314
1315         i = __find_msr_index(vmx, msr);
1316         if (i >= 0)
1317                 return &vmx->guest_msrs[i];
1318         return NULL;
1319 }
1320
1321 static void vmcs_clear(struct vmcs *vmcs)
1322 {
1323         u64 phys_addr = __pa(vmcs);
1324         u8 error;
1325
1326         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1327                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1328                       : "cc", "memory");
1329         if (error)
1330                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1331                        vmcs, phys_addr);
1332 }
1333
1334 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1335 {
1336         vmcs_clear(loaded_vmcs->vmcs);
1337         loaded_vmcs->cpu = -1;
1338         loaded_vmcs->launched = 0;
1339 }
1340
1341 static void vmcs_load(struct vmcs *vmcs)
1342 {
1343         u64 phys_addr = __pa(vmcs);
1344         u8 error;
1345
1346         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1347                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1348                         : "cc", "memory");
1349         if (error)
1350                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1351                        vmcs, phys_addr);
1352 }
1353
1354 #ifdef CONFIG_KEXEC_CORE
1355 /*
1356  * This bitmap is used to indicate whether the vmclear
1357  * operation is enabled on all cpus. All disabled by
1358  * default.
1359  */
1360 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1361
1362 static inline void crash_enable_local_vmclear(int cpu)
1363 {
1364         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1365 }
1366
1367 static inline void crash_disable_local_vmclear(int cpu)
1368 {
1369         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1370 }
1371
1372 static inline int crash_local_vmclear_enabled(int cpu)
1373 {
1374         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1375 }
1376
1377 static void crash_vmclear_local_loaded_vmcss(void)
1378 {
1379         int cpu = raw_smp_processor_id();
1380         struct loaded_vmcs *v;
1381
1382         if (!crash_local_vmclear_enabled(cpu))
1383                 return;
1384
1385         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1386                             loaded_vmcss_on_cpu_link)
1387                 vmcs_clear(v->vmcs);
1388 }
1389 #else
1390 static inline void crash_enable_local_vmclear(int cpu) { }
1391 static inline void crash_disable_local_vmclear(int cpu) { }
1392 #endif /* CONFIG_KEXEC_CORE */
1393
1394 static void __loaded_vmcs_clear(void *arg)
1395 {
1396         struct loaded_vmcs *loaded_vmcs = arg;
1397         int cpu = raw_smp_processor_id();
1398
1399         if (loaded_vmcs->cpu != cpu)
1400                 return; /* vcpu migration can race with cpu offline */
1401         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1402                 per_cpu(current_vmcs, cpu) = NULL;
1403         crash_disable_local_vmclear(cpu);
1404         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1405
1406         /*
1407          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1408          * is before setting loaded_vmcs->vcpu to -1 which is done in
1409          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1410          * then adds the vmcs into percpu list before it is deleted.
1411          */
1412         smp_wmb();
1413
1414         loaded_vmcs_init(loaded_vmcs);
1415         crash_enable_local_vmclear(cpu);
1416 }
1417
1418 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1419 {
1420         int cpu = loaded_vmcs->cpu;
1421
1422         if (cpu != -1)
1423                 smp_call_function_single(cpu,
1424                          __loaded_vmcs_clear, loaded_vmcs, 1);
1425 }
1426
1427 static inline void vpid_sync_vcpu_single(int vpid)
1428 {
1429         if (vpid == 0)
1430                 return;
1431
1432         if (cpu_has_vmx_invvpid_single())
1433                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1434 }
1435
1436 static inline void vpid_sync_vcpu_global(void)
1437 {
1438         if (cpu_has_vmx_invvpid_global())
1439                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1440 }
1441
1442 static inline void vpid_sync_context(int vpid)
1443 {
1444         if (cpu_has_vmx_invvpid_single())
1445                 vpid_sync_vcpu_single(vpid);
1446         else
1447                 vpid_sync_vcpu_global();
1448 }
1449
1450 static inline void ept_sync_global(void)
1451 {
1452         if (cpu_has_vmx_invept_global())
1453                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1454 }
1455
1456 static inline void ept_sync_context(u64 eptp)
1457 {
1458         if (enable_ept) {
1459                 if (cpu_has_vmx_invept_context())
1460                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1461                 else
1462                         ept_sync_global();
1463         }
1464 }
1465
1466 static __always_inline void vmcs_check16(unsigned long field)
1467 {
1468         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1469                          "16-bit accessor invalid for 64-bit field");
1470         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1471                          "16-bit accessor invalid for 64-bit high field");
1472         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1473                          "16-bit accessor invalid for 32-bit high field");
1474         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1475                          "16-bit accessor invalid for natural width field");
1476 }
1477
1478 static __always_inline void vmcs_check32(unsigned long field)
1479 {
1480         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1481                          "32-bit accessor invalid for 16-bit field");
1482         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1483                          "32-bit accessor invalid for natural width field");
1484 }
1485
1486 static __always_inline void vmcs_check64(unsigned long field)
1487 {
1488         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1489                          "64-bit accessor invalid for 16-bit field");
1490         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1491                          "64-bit accessor invalid for 64-bit high field");
1492         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1493                          "64-bit accessor invalid for 32-bit field");
1494         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1495                          "64-bit accessor invalid for natural width field");
1496 }
1497
1498 static __always_inline void vmcs_checkl(unsigned long field)
1499 {
1500         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1501                          "Natural width accessor invalid for 16-bit field");
1502         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1503                          "Natural width accessor invalid for 64-bit field");
1504         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1505                          "Natural width accessor invalid for 64-bit high field");
1506         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1507                          "Natural width accessor invalid for 32-bit field");
1508 }
1509
1510 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1511 {
1512         unsigned long value;
1513
1514         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1515                       : "=a"(value) : "d"(field) : "cc");
1516         return value;
1517 }
1518
1519 static __always_inline u16 vmcs_read16(unsigned long field)
1520 {
1521         vmcs_check16(field);
1522         return __vmcs_readl(field);
1523 }
1524
1525 static __always_inline u32 vmcs_read32(unsigned long field)
1526 {
1527         vmcs_check32(field);
1528         return __vmcs_readl(field);
1529 }
1530
1531 static __always_inline u64 vmcs_read64(unsigned long field)
1532 {
1533         vmcs_check64(field);
1534 #ifdef CONFIG_X86_64
1535         return __vmcs_readl(field);
1536 #else
1537         return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1538 #endif
1539 }
1540
1541 static __always_inline unsigned long vmcs_readl(unsigned long field)
1542 {
1543         vmcs_checkl(field);
1544         return __vmcs_readl(field);
1545 }
1546
1547 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1548 {
1549         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1550                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1551         dump_stack();
1552 }
1553
1554 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1555 {
1556         u8 error;
1557
1558         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1559                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1560         if (unlikely(error))
1561                 vmwrite_error(field, value);
1562 }
1563
1564 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1565 {
1566         vmcs_check16(field);
1567         __vmcs_writel(field, value);
1568 }
1569
1570 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1571 {
1572         vmcs_check32(field);
1573         __vmcs_writel(field, value);
1574 }
1575
1576 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1577 {
1578         vmcs_check64(field);
1579         __vmcs_writel(field, value);
1580 #ifndef CONFIG_X86_64
1581         asm volatile ("");
1582         __vmcs_writel(field+1, value >> 32);
1583 #endif
1584 }
1585
1586 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1587 {
1588         vmcs_checkl(field);
1589         __vmcs_writel(field, value);
1590 }
1591
1592 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1593 {
1594         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1595                          "vmcs_clear_bits does not support 64-bit fields");
1596         __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1597 }
1598
1599 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1600 {
1601         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1602                          "vmcs_set_bits does not support 64-bit fields");
1603         __vmcs_writel(field, __vmcs_readl(field) | mask);
1604 }
1605
1606 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1607 {
1608         vmcs_write32(VM_ENTRY_CONTROLS, val);
1609         vmx->vm_entry_controls_shadow = val;
1610 }
1611
1612 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1613 {
1614         if (vmx->vm_entry_controls_shadow != val)
1615                 vm_entry_controls_init(vmx, val);
1616 }
1617
1618 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1619 {
1620         return vmx->vm_entry_controls_shadow;
1621 }
1622
1623
1624 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1625 {
1626         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1627 }
1628
1629 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1630 {
1631         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1632 }
1633
1634 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1635 {
1636         vmcs_write32(VM_EXIT_CONTROLS, val);
1637         vmx->vm_exit_controls_shadow = val;
1638 }
1639
1640 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1641 {
1642         if (vmx->vm_exit_controls_shadow != val)
1643                 vm_exit_controls_init(vmx, val);
1644 }
1645
1646 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1647 {
1648         return vmx->vm_exit_controls_shadow;
1649 }
1650
1651
1652 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1653 {
1654         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1655 }
1656
1657 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1658 {
1659         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1660 }
1661
1662 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1663 {
1664         vmx->segment_cache.bitmask = 0;
1665 }
1666
1667 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1668                                        unsigned field)
1669 {
1670         bool ret;
1671         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1672
1673         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1674                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1675                 vmx->segment_cache.bitmask = 0;
1676         }
1677         ret = vmx->segment_cache.bitmask & mask;
1678         vmx->segment_cache.bitmask |= mask;
1679         return ret;
1680 }
1681
1682 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1683 {
1684         u16 *p = &vmx->segment_cache.seg[seg].selector;
1685
1686         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1687                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1688         return *p;
1689 }
1690
1691 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1692 {
1693         ulong *p = &vmx->segment_cache.seg[seg].base;
1694
1695         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1696                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1697         return *p;
1698 }
1699
1700 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1701 {
1702         u32 *p = &vmx->segment_cache.seg[seg].limit;
1703
1704         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1705                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1706         return *p;
1707 }
1708
1709 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1710 {
1711         u32 *p = &vmx->segment_cache.seg[seg].ar;
1712
1713         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1714                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1715         return *p;
1716 }
1717
1718 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1719 {
1720         u32 eb;
1721
1722         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1723              (1u << NM_VECTOR) | (1u << DB_VECTOR) | (1u << AC_VECTOR);
1724         if ((vcpu->guest_debug &
1725              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1726             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1727                 eb |= 1u << BP_VECTOR;
1728         if (to_vmx(vcpu)->rmode.vm86_active)
1729                 eb = ~0;
1730         if (enable_ept)
1731                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1732         if (vcpu->fpu_active)
1733                 eb &= ~(1u << NM_VECTOR);
1734
1735         /* When we are running a nested L2 guest and L1 specified for it a
1736          * certain exception bitmap, we must trap the same exceptions and pass
1737          * them to L1. When running L2, we will only handle the exceptions
1738          * specified above if L1 did not want them.
1739          */
1740         if (is_guest_mode(vcpu))
1741                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1742
1743         vmcs_write32(EXCEPTION_BITMAP, eb);
1744 }
1745
1746 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1747                 unsigned long entry, unsigned long exit)
1748 {
1749         vm_entry_controls_clearbit(vmx, entry);
1750         vm_exit_controls_clearbit(vmx, exit);
1751 }
1752
1753 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1754 {
1755         unsigned i;
1756         struct msr_autoload *m = &vmx->msr_autoload;
1757
1758         switch (msr) {
1759         case MSR_EFER:
1760                 if (cpu_has_load_ia32_efer) {
1761                         clear_atomic_switch_msr_special(vmx,
1762                                         VM_ENTRY_LOAD_IA32_EFER,
1763                                         VM_EXIT_LOAD_IA32_EFER);
1764                         return;
1765                 }
1766                 break;
1767         case MSR_CORE_PERF_GLOBAL_CTRL:
1768                 if (cpu_has_load_perf_global_ctrl) {
1769                         clear_atomic_switch_msr_special(vmx,
1770                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1771                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1772                         return;
1773                 }
1774                 break;
1775         }
1776
1777         for (i = 0; i < m->nr; ++i)
1778                 if (m->guest[i].index == msr)
1779                         break;
1780
1781         if (i == m->nr)
1782                 return;
1783         --m->nr;
1784         m->guest[i] = m->guest[m->nr];
1785         m->host[i] = m->host[m->nr];
1786         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1787         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1788 }
1789
1790 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1791                 unsigned long entry, unsigned long exit,
1792                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1793                 u64 guest_val, u64 host_val)
1794 {
1795         vmcs_write64(guest_val_vmcs, guest_val);
1796         vmcs_write64(host_val_vmcs, host_val);
1797         vm_entry_controls_setbit(vmx, entry);
1798         vm_exit_controls_setbit(vmx, exit);
1799 }
1800
1801 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1802                                   u64 guest_val, u64 host_val)
1803 {
1804         unsigned i;
1805         struct msr_autoload *m = &vmx->msr_autoload;
1806
1807         switch (msr) {
1808         case MSR_EFER:
1809                 if (cpu_has_load_ia32_efer) {
1810                         add_atomic_switch_msr_special(vmx,
1811                                         VM_ENTRY_LOAD_IA32_EFER,
1812                                         VM_EXIT_LOAD_IA32_EFER,
1813                                         GUEST_IA32_EFER,
1814                                         HOST_IA32_EFER,
1815                                         guest_val, host_val);
1816                         return;
1817                 }
1818                 break;
1819         case MSR_CORE_PERF_GLOBAL_CTRL:
1820                 if (cpu_has_load_perf_global_ctrl) {
1821                         add_atomic_switch_msr_special(vmx,
1822                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1823                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1824                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1825                                         HOST_IA32_PERF_GLOBAL_CTRL,
1826                                         guest_val, host_val);
1827                         return;
1828                 }
1829                 break;
1830         case MSR_IA32_PEBS_ENABLE:
1831                 /* PEBS needs a quiescent period after being disabled (to write
1832                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
1833                  * provide that period, so a CPU could write host's record into
1834                  * guest's memory.
1835                  */
1836                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1837         }
1838
1839         for (i = 0; i < m->nr; ++i)
1840                 if (m->guest[i].index == msr)
1841                         break;
1842
1843         if (i == NR_AUTOLOAD_MSRS) {
1844                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1845                                 "Can't add msr %x\n", msr);
1846                 return;
1847         } else if (i == m->nr) {
1848                 ++m->nr;
1849                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1850                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1851         }
1852
1853         m->guest[i].index = msr;
1854         m->guest[i].value = guest_val;
1855         m->host[i].index = msr;
1856         m->host[i].value = host_val;
1857 }
1858
1859 static void reload_tss(void)
1860 {
1861         /*
1862          * VT restores TR but not its size.  Useless.
1863          */
1864         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1865         struct desc_struct *descs;
1866
1867         descs = (void *)gdt->address;
1868         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1869         load_TR_desc();
1870 }
1871
1872 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1873 {
1874         u64 guest_efer = vmx->vcpu.arch.efer;
1875         u64 ignore_bits = 0;
1876
1877         if (!enable_ept) {
1878                 /*
1879                  * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
1880                  * host CPUID is more efficient than testing guest CPUID
1881                  * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
1882                  */
1883                 if (boot_cpu_has(X86_FEATURE_SMEP))
1884                         guest_efer |= EFER_NX;
1885                 else if (!(guest_efer & EFER_NX))
1886                         ignore_bits |= EFER_NX;
1887         }
1888
1889         /*
1890          * LMA and LME handled by hardware; SCE meaningless outside long mode.
1891          */
1892         ignore_bits |= EFER_SCE;
1893 #ifdef CONFIG_X86_64
1894         ignore_bits |= EFER_LMA | EFER_LME;
1895         /* SCE is meaningful only in long mode on Intel */
1896         if (guest_efer & EFER_LMA)
1897                 ignore_bits &= ~(u64)EFER_SCE;
1898 #endif
1899
1900         clear_atomic_switch_msr(vmx, MSR_EFER);
1901
1902         /*
1903          * On EPT, we can't emulate NX, so we must switch EFER atomically.
1904          * On CPUs that support "load IA32_EFER", always switch EFER
1905          * atomically, since it's faster than switching it manually.
1906          */
1907         if (cpu_has_load_ia32_efer ||
1908             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1909                 if (!(guest_efer & EFER_LMA))
1910                         guest_efer &= ~EFER_LME;
1911                 if (guest_efer != host_efer)
1912                         add_atomic_switch_msr(vmx, MSR_EFER,
1913                                               guest_efer, host_efer);
1914                 return false;
1915         } else {
1916                 guest_efer &= ~ignore_bits;
1917                 guest_efer |= host_efer & ignore_bits;
1918
1919                 vmx->guest_msrs[efer_offset].data = guest_efer;
1920                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1921
1922                 return true;
1923         }
1924 }
1925
1926 static unsigned long segment_base(u16 selector)
1927 {
1928         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1929         struct desc_struct *d;
1930         unsigned long table_base;
1931         unsigned long v;
1932
1933         if (!(selector & ~3))
1934                 return 0;
1935
1936         table_base = gdt->address;
1937
1938         if (selector & 4) {           /* from ldt */
1939                 u16 ldt_selector = kvm_read_ldt();
1940
1941                 if (!(ldt_selector & ~3))
1942                         return 0;
1943
1944                 table_base = segment_base(ldt_selector);
1945         }
1946         d = (struct desc_struct *)(table_base + (selector & ~7));
1947         v = get_desc_base(d);
1948 #ifdef CONFIG_X86_64
1949        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1950                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1951 #endif
1952         return v;
1953 }
1954
1955 static inline unsigned long kvm_read_tr_base(void)
1956 {
1957         u16 tr;
1958         asm("str %0" : "=g"(tr));
1959         return segment_base(tr);
1960 }
1961
1962 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1963 {
1964         struct vcpu_vmx *vmx = to_vmx(vcpu);
1965         int i;
1966
1967         if (vmx->host_state.loaded)
1968                 return;
1969
1970         vmx->host_state.loaded = 1;
1971         /*
1972          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1973          * allow segment selectors with cpl > 0 or ti == 1.
1974          */
1975         vmx->host_state.ldt_sel = kvm_read_ldt();
1976         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1977         savesegment(fs, vmx->host_state.fs_sel);
1978         if (!(vmx->host_state.fs_sel & 7)) {
1979                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1980                 vmx->host_state.fs_reload_needed = 0;
1981         } else {
1982                 vmcs_write16(HOST_FS_SELECTOR, 0);
1983                 vmx->host_state.fs_reload_needed = 1;
1984         }
1985         savesegment(gs, vmx->host_state.gs_sel);
1986         if (!(vmx->host_state.gs_sel & 7))
1987                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1988         else {
1989                 vmcs_write16(HOST_GS_SELECTOR, 0);
1990                 vmx->host_state.gs_ldt_reload_needed = 1;
1991         }
1992
1993 #ifdef CONFIG_X86_64
1994         savesegment(ds, vmx->host_state.ds_sel);
1995         savesegment(es, vmx->host_state.es_sel);
1996 #endif
1997
1998 #ifdef CONFIG_X86_64
1999         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2000         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2001 #else
2002         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2003         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2004 #endif
2005
2006 #ifdef CONFIG_X86_64
2007         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2008         if (is_long_mode(&vmx->vcpu))
2009                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2010 #endif
2011         if (boot_cpu_has(X86_FEATURE_MPX))
2012                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2013         for (i = 0; i < vmx->save_nmsrs; ++i)
2014                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2015                                    vmx->guest_msrs[i].data,
2016                                    vmx->guest_msrs[i].mask);
2017 }
2018
2019 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2020 {
2021         if (!vmx->host_state.loaded)
2022                 return;
2023
2024         ++vmx->vcpu.stat.host_state_reload;
2025         vmx->host_state.loaded = 0;
2026 #ifdef CONFIG_X86_64
2027         if (is_long_mode(&vmx->vcpu))
2028                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2029 #endif
2030         if (vmx->host_state.gs_ldt_reload_needed) {
2031                 kvm_load_ldt(vmx->host_state.ldt_sel);
2032 #ifdef CONFIG_X86_64
2033                 load_gs_index(vmx->host_state.gs_sel);
2034 #else
2035                 loadsegment(gs, vmx->host_state.gs_sel);
2036 #endif
2037         }
2038         if (vmx->host_state.fs_reload_needed)
2039                 loadsegment(fs, vmx->host_state.fs_sel);
2040 #ifdef CONFIG_X86_64
2041         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2042                 loadsegment(ds, vmx->host_state.ds_sel);
2043                 loadsegment(es, vmx->host_state.es_sel);
2044         }
2045 #endif
2046         reload_tss();
2047 #ifdef CONFIG_X86_64
2048         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2049 #endif
2050         if (vmx->host_state.msr_host_bndcfgs)
2051                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2052         /*
2053          * If the FPU is not active (through the host task or
2054          * the guest vcpu), then restore the cr0.TS bit.
2055          */
2056         if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded)
2057                 stts();
2058         load_gdt(this_cpu_ptr(&host_gdt));
2059 }
2060
2061 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2062 {
2063         preempt_disable();
2064         __vmx_load_host_state(vmx);
2065         preempt_enable();
2066 }
2067
2068 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2069 {
2070         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2071         struct pi_desc old, new;
2072         unsigned int dest;
2073
2074         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2075                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2076                 !kvm_vcpu_apicv_active(vcpu))
2077                 return;
2078
2079         do {
2080                 old.control = new.control = pi_desc->control;
2081
2082                 /*
2083                  * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2084                  * are two possible cases:
2085                  * 1. After running 'pre_block', context switch
2086                  *    happened. For this case, 'sn' was set in
2087                  *    vmx_vcpu_put(), so we need to clear it here.
2088                  * 2. After running 'pre_block', we were blocked,
2089                  *    and woken up by some other guy. For this case,
2090                  *    we don't need to do anything, 'pi_post_block'
2091                  *    will do everything for us. However, we cannot
2092                  *    check whether it is case #1 or case #2 here
2093                  *    (maybe, not needed), so we also clear sn here,
2094                  *    I think it is not a big deal.
2095                  */
2096                 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2097                         if (vcpu->cpu != cpu) {
2098                                 dest = cpu_physical_id(cpu);
2099
2100                                 if (x2apic_enabled())
2101                                         new.ndst = dest;
2102                                 else
2103                                         new.ndst = (dest << 8) & 0xFF00;
2104                         }
2105
2106                         /* set 'NV' to 'notification vector' */
2107                         new.nv = POSTED_INTR_VECTOR;
2108                 }
2109
2110                 /* Allow posting non-urgent interrupts */
2111                 new.sn = 0;
2112         } while (cmpxchg(&pi_desc->control, old.control,
2113                         new.control) != old.control);
2114 }
2115
2116 /*
2117  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2118  * vcpu mutex is already taken.
2119  */
2120 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2121 {
2122         struct vcpu_vmx *vmx = to_vmx(vcpu);
2123         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2124
2125         if (!vmm_exclusive)
2126                 kvm_cpu_vmxon(phys_addr);
2127         else if (vmx->loaded_vmcs->cpu != cpu)
2128                 loaded_vmcs_clear(vmx->loaded_vmcs);
2129
2130         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2131                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2132                 vmcs_load(vmx->loaded_vmcs->vmcs);
2133         }
2134
2135         if (vmx->loaded_vmcs->cpu != cpu) {
2136                 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2137                 unsigned long sysenter_esp;
2138
2139                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2140                 local_irq_disable();
2141                 crash_disable_local_vmclear(cpu);
2142
2143                 /*
2144                  * Read loaded_vmcs->cpu should be before fetching
2145                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2146                  * See the comments in __loaded_vmcs_clear().
2147                  */
2148                 smp_rmb();
2149
2150                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2151                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2152                 crash_enable_local_vmclear(cpu);
2153                 local_irq_enable();
2154
2155                 /*
2156                  * Linux uses per-cpu TSS and GDT, so set these when switching
2157                  * processors.
2158                  */
2159                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
2160                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
2161
2162                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2163                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2164
2165                 vmx->loaded_vmcs->cpu = cpu;
2166         }
2167
2168         /* Setup TSC multiplier */
2169         if (kvm_has_tsc_control &&
2170             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio) {
2171                 vmx->current_tsc_ratio = vcpu->arch.tsc_scaling_ratio;
2172                 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2173         }
2174
2175         vmx_vcpu_pi_load(vcpu, cpu);
2176         vmx->host_pkru = read_pkru();
2177 }
2178
2179 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2180 {
2181         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2182
2183         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2184                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2185                 !kvm_vcpu_apicv_active(vcpu))
2186                 return;
2187
2188         /* Set SN when the vCPU is preempted */
2189         if (vcpu->preempted)
2190                 pi_set_sn(pi_desc);
2191 }
2192
2193 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2194 {
2195         vmx_vcpu_pi_put(vcpu);
2196
2197         __vmx_load_host_state(to_vmx(vcpu));
2198         if (!vmm_exclusive) {
2199                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2200                 vcpu->cpu = -1;
2201                 kvm_cpu_vmxoff();
2202         }
2203 }
2204
2205 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
2206 {
2207         ulong cr0;
2208
2209         if (vcpu->fpu_active)
2210                 return;
2211         vcpu->fpu_active = 1;
2212         cr0 = vmcs_readl(GUEST_CR0);
2213         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
2214         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
2215         vmcs_writel(GUEST_CR0, cr0);
2216         update_exception_bitmap(vcpu);
2217         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
2218         if (is_guest_mode(vcpu))
2219                 vcpu->arch.cr0_guest_owned_bits &=
2220                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
2221         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2222 }
2223
2224 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2225
2226 /*
2227  * Return the cr0 value that a nested guest would read. This is a combination
2228  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2229  * its hypervisor (cr0_read_shadow).
2230  */
2231 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2232 {
2233         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2234                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2235 }
2236 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2237 {
2238         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2239                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2240 }
2241
2242 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
2243 {
2244         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2245          * set this *before* calling this function.
2246          */
2247         vmx_decache_cr0_guest_bits(vcpu);
2248         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
2249         update_exception_bitmap(vcpu);
2250         vcpu->arch.cr0_guest_owned_bits = 0;
2251         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2252         if (is_guest_mode(vcpu)) {
2253                 /*
2254                  * L1's specified read shadow might not contain the TS bit,
2255                  * so now that we turned on shadowing of this bit, we need to
2256                  * set this bit of the shadow. Like in nested_vmx_run we need
2257                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2258                  * up-to-date here because we just decached cr0.TS (and we'll
2259                  * only update vmcs12->guest_cr0 on nested exit).
2260                  */
2261                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2262                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2263                         (vcpu->arch.cr0 & X86_CR0_TS);
2264                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2265         } else
2266                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2267 }
2268
2269 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2270 {
2271         unsigned long rflags, save_rflags;
2272
2273         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2274                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2275                 rflags = vmcs_readl(GUEST_RFLAGS);
2276                 if (to_vmx(vcpu)->rmode.vm86_active) {
2277                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2278                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2279                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2280                 }
2281                 to_vmx(vcpu)->rflags = rflags;
2282         }
2283         return to_vmx(vcpu)->rflags;
2284 }
2285
2286 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2287 {
2288         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2289         to_vmx(vcpu)->rflags = rflags;
2290         if (to_vmx(vcpu)->rmode.vm86_active) {
2291                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2292                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2293         }
2294         vmcs_writel(GUEST_RFLAGS, rflags);
2295 }
2296
2297 static u32 vmx_get_pkru(struct kvm_vcpu *vcpu)
2298 {
2299         return to_vmx(vcpu)->guest_pkru;
2300 }
2301
2302 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2303 {
2304         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2305         int ret = 0;
2306
2307         if (interruptibility & GUEST_INTR_STATE_STI)
2308                 ret |= KVM_X86_SHADOW_INT_STI;
2309         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2310                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2311
2312         return ret;
2313 }
2314
2315 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2316 {
2317         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2318         u32 interruptibility = interruptibility_old;
2319
2320         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2321
2322         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2323                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2324         else if (mask & KVM_X86_SHADOW_INT_STI)
2325                 interruptibility |= GUEST_INTR_STATE_STI;
2326
2327         if ((interruptibility != interruptibility_old))
2328                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2329 }
2330
2331 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2332 {
2333         unsigned long rip;
2334
2335         rip = kvm_rip_read(vcpu);
2336         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2337         kvm_rip_write(vcpu, rip);
2338
2339         /* skipping an emulated instruction also counts */
2340         vmx_set_interrupt_shadow(vcpu, 0);
2341 }
2342
2343 /*
2344  * KVM wants to inject page-faults which it got to the guest. This function
2345  * checks whether in a nested guest, we need to inject them to L1 or L2.
2346  */
2347 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2348 {
2349         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2350
2351         if (!(vmcs12->exception_bitmap & (1u << nr)))
2352                 return 0;
2353
2354         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2355                           vmcs_read32(VM_EXIT_INTR_INFO),
2356                           vmcs_readl(EXIT_QUALIFICATION));
2357         return 1;
2358 }
2359
2360 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2361                                 bool has_error_code, u32 error_code,
2362                                 bool reinject)
2363 {
2364         struct vcpu_vmx *vmx = to_vmx(vcpu);
2365         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2366
2367         if (!reinject && is_guest_mode(vcpu) &&
2368             nested_vmx_check_exception(vcpu, nr))
2369                 return;
2370
2371         if (has_error_code) {
2372                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2373                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2374         }
2375
2376         if (vmx->rmode.vm86_active) {
2377                 int inc_eip = 0;
2378                 if (kvm_exception_is_soft(nr))
2379                         inc_eip = vcpu->arch.event_exit_inst_len;
2380                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2381                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2382                 return;
2383         }
2384
2385         if (kvm_exception_is_soft(nr)) {
2386                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2387                              vmx->vcpu.arch.event_exit_inst_len);
2388                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2389         } else
2390                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2391
2392         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2393 }
2394
2395 static bool vmx_rdtscp_supported(void)
2396 {
2397         return cpu_has_vmx_rdtscp();
2398 }
2399
2400 static bool vmx_invpcid_supported(void)
2401 {
2402         return cpu_has_vmx_invpcid() && enable_ept;
2403 }
2404
2405 /*
2406  * Swap MSR entry in host/guest MSR entry array.
2407  */
2408 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2409 {
2410         struct shared_msr_entry tmp;
2411
2412         tmp = vmx->guest_msrs[to];
2413         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2414         vmx->guest_msrs[from] = tmp;
2415 }
2416
2417 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2418 {
2419         unsigned long *msr_bitmap;
2420
2421         if (is_guest_mode(vcpu))
2422                 msr_bitmap = vmx_msr_bitmap_nested;
2423         else if (cpu_has_secondary_exec_ctrls() &&
2424                  (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
2425                   SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
2426                 if (is_long_mode(vcpu))
2427                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2428                 else
2429                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2430         } else {
2431                 if (is_long_mode(vcpu))
2432                         msr_bitmap = vmx_msr_bitmap_longmode;
2433                 else
2434                         msr_bitmap = vmx_msr_bitmap_legacy;
2435         }
2436
2437         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2438 }
2439
2440 /*
2441  * Set up the vmcs to automatically save and restore system
2442  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2443  * mode, as fiddling with msrs is very expensive.
2444  */
2445 static void setup_msrs(struct vcpu_vmx *vmx)
2446 {
2447         int save_nmsrs, index;
2448
2449         save_nmsrs = 0;
2450 #ifdef CONFIG_X86_64
2451         if (is_long_mode(&vmx->vcpu)) {
2452                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2453                 if (index >= 0)
2454                         move_msr_up(vmx, index, save_nmsrs++);
2455                 index = __find_msr_index(vmx, MSR_LSTAR);
2456                 if (index >= 0)
2457                         move_msr_up(vmx, index, save_nmsrs++);
2458                 index = __find_msr_index(vmx, MSR_CSTAR);
2459                 if (index >= 0)
2460                         move_msr_up(vmx, index, save_nmsrs++);
2461                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2462                 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2463                         move_msr_up(vmx, index, save_nmsrs++);
2464                 /*
2465                  * MSR_STAR is only needed on long mode guests, and only
2466                  * if efer.sce is enabled.
2467                  */
2468                 index = __find_msr_index(vmx, MSR_STAR);
2469                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2470                         move_msr_up(vmx, index, save_nmsrs++);
2471         }
2472 #endif
2473         index = __find_msr_index(vmx, MSR_EFER);
2474         if (index >= 0 && update_transition_efer(vmx, index))
2475                 move_msr_up(vmx, index, save_nmsrs++);
2476
2477         vmx->save_nmsrs = save_nmsrs;
2478
2479         if (cpu_has_vmx_msr_bitmap())
2480                 vmx_set_msr_bitmap(&vmx->vcpu);
2481 }
2482
2483 /*
2484  * reads and returns guest's timestamp counter "register"
2485  * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2486  * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2487  */
2488 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2489 {
2490         u64 host_tsc, tsc_offset;
2491
2492         host_tsc = rdtsc();
2493         tsc_offset = vmcs_read64(TSC_OFFSET);
2494         return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2495 }
2496
2497 /*
2498  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2499  * counter, even if a nested guest (L2) is currently running.
2500  */
2501 static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2502 {
2503         u64 tsc_offset;
2504
2505         tsc_offset = is_guest_mode(vcpu) ?
2506                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2507                 vmcs_read64(TSC_OFFSET);
2508         return host_tsc + tsc_offset;
2509 }
2510
2511 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2512 {
2513         return vmcs_read64(TSC_OFFSET);
2514 }
2515
2516 /*
2517  * writes 'offset' into guest's timestamp counter offset register
2518  */
2519 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2520 {
2521         if (is_guest_mode(vcpu)) {
2522                 /*
2523                  * We're here if L1 chose not to trap WRMSR to TSC. According
2524                  * to the spec, this should set L1's TSC; The offset that L1
2525                  * set for L2 remains unchanged, and still needs to be added
2526                  * to the newly set TSC to get L2's TSC.
2527                  */
2528                 struct vmcs12 *vmcs12;
2529                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2530                 /* recalculate vmcs02.TSC_OFFSET: */
2531                 vmcs12 = get_vmcs12(vcpu);
2532                 vmcs_write64(TSC_OFFSET, offset +
2533                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2534                          vmcs12->tsc_offset : 0));
2535         } else {
2536                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2537                                            vmcs_read64(TSC_OFFSET), offset);
2538                 vmcs_write64(TSC_OFFSET, offset);
2539         }
2540 }
2541
2542 static void vmx_adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, s64 adjustment)
2543 {
2544         u64 offset = vmcs_read64(TSC_OFFSET);
2545
2546         vmcs_write64(TSC_OFFSET, offset + adjustment);
2547         if (is_guest_mode(vcpu)) {
2548                 /* Even when running L2, the adjustment needs to apply to L1 */
2549                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2550         } else
2551                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2552                                            offset + adjustment);
2553 }
2554
2555 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2556 {
2557         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2558         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2559 }
2560
2561 /*
2562  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2563  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2564  * all guests if the "nested" module option is off, and can also be disabled
2565  * for a single guest by disabling its VMX cpuid bit.
2566  */
2567 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2568 {
2569         return nested && guest_cpuid_has_vmx(vcpu);
2570 }
2571
2572 /*
2573  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2574  * returned for the various VMX controls MSRs when nested VMX is enabled.
2575  * The same values should also be used to verify that vmcs12 control fields are
2576  * valid during nested entry from L1 to L2.
2577  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2578  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2579  * bit in the high half is on if the corresponding bit in the control field
2580  * may be on. See also vmx_control_verify().
2581  */
2582 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2583 {
2584         /*
2585          * Note that as a general rule, the high half of the MSRs (bits in
2586          * the control fields which may be 1) should be initialized by the
2587          * intersection of the underlying hardware's MSR (i.e., features which
2588          * can be supported) and the list of features we want to expose -
2589          * because they are known to be properly supported in our code.
2590          * Also, usually, the low half of the MSRs (bits which must be 1) can
2591          * be set to 0, meaning that L1 may turn off any of these bits. The
2592          * reason is that if one of these bits is necessary, it will appear
2593          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2594          * fields of vmcs01 and vmcs02, will turn these bits off - and
2595          * nested_vmx_exit_handled() will not pass related exits to L1.
2596          * These rules have exceptions below.
2597          */
2598
2599         /* pin-based controls */
2600         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2601                 vmx->nested.nested_vmx_pinbased_ctls_low,
2602                 vmx->nested.nested_vmx_pinbased_ctls_high);
2603         vmx->nested.nested_vmx_pinbased_ctls_low |=
2604                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2605         vmx->nested.nested_vmx_pinbased_ctls_high &=
2606                 PIN_BASED_EXT_INTR_MASK |
2607                 PIN_BASED_NMI_EXITING |
2608                 PIN_BASED_VIRTUAL_NMIS;
2609         vmx->nested.nested_vmx_pinbased_ctls_high |=
2610                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2611                 PIN_BASED_VMX_PREEMPTION_TIMER;
2612         if (kvm_vcpu_apicv_active(&vmx->vcpu))
2613                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2614                         PIN_BASED_POSTED_INTR;
2615
2616         /* exit controls */
2617         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2618                 vmx->nested.nested_vmx_exit_ctls_low,
2619                 vmx->nested.nested_vmx_exit_ctls_high);
2620         vmx->nested.nested_vmx_exit_ctls_low =
2621                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2622
2623         vmx->nested.nested_vmx_exit_ctls_high &=
2624 #ifdef CONFIG_X86_64
2625                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2626 #endif
2627                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2628         vmx->nested.nested_vmx_exit_ctls_high |=
2629                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2630                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2631                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2632
2633         if (kvm_mpx_supported())
2634                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2635
2636         /* We support free control of debug control saving. */
2637         vmx->nested.nested_vmx_true_exit_ctls_low =
2638                 vmx->nested.nested_vmx_exit_ctls_low &
2639                 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2640
2641         /* entry controls */
2642         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2643                 vmx->nested.nested_vmx_entry_ctls_low,
2644                 vmx->nested.nested_vmx_entry_ctls_high);
2645         vmx->nested.nested_vmx_entry_ctls_low =
2646                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2647         vmx->nested.nested_vmx_entry_ctls_high &=
2648 #ifdef CONFIG_X86_64
2649                 VM_ENTRY_IA32E_MODE |
2650 #endif
2651                 VM_ENTRY_LOAD_IA32_PAT;
2652         vmx->nested.nested_vmx_entry_ctls_high |=
2653                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2654         if (kvm_mpx_supported())
2655                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2656
2657         /* We support free control of debug control loading. */
2658         vmx->nested.nested_vmx_true_entry_ctls_low =
2659                 vmx->nested.nested_vmx_entry_ctls_low &
2660                 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2661
2662         /* cpu-based controls */
2663         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2664                 vmx->nested.nested_vmx_procbased_ctls_low,
2665                 vmx->nested.nested_vmx_procbased_ctls_high);
2666         vmx->nested.nested_vmx_procbased_ctls_low =
2667                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2668         vmx->nested.nested_vmx_procbased_ctls_high &=
2669                 CPU_BASED_VIRTUAL_INTR_PENDING |
2670                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2671                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2672                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2673                 CPU_BASED_CR3_STORE_EXITING |
2674 #ifdef CONFIG_X86_64
2675                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2676 #endif
2677                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2678                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2679                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2680                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2681                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2682         /*
2683          * We can allow some features even when not supported by the
2684          * hardware. For example, L1 can specify an MSR bitmap - and we
2685          * can use it to avoid exits to L1 - even when L0 runs L2
2686          * without MSR bitmaps.
2687          */
2688         vmx->nested.nested_vmx_procbased_ctls_high |=
2689                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2690                 CPU_BASED_USE_MSR_BITMAPS;
2691
2692         /* We support free control of CR3 access interception. */
2693         vmx->nested.nested_vmx_true_procbased_ctls_low =
2694                 vmx->nested.nested_vmx_procbased_ctls_low &
2695                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2696
2697         /* secondary cpu-based controls */
2698         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2699                 vmx->nested.nested_vmx_secondary_ctls_low,
2700                 vmx->nested.nested_vmx_secondary_ctls_high);
2701         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2702         vmx->nested.nested_vmx_secondary_ctls_high &=
2703                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2704                 SECONDARY_EXEC_RDTSCP |
2705                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2706                 SECONDARY_EXEC_ENABLE_VPID |
2707                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2708                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2709                 SECONDARY_EXEC_WBINVD_EXITING |
2710                 SECONDARY_EXEC_XSAVES;
2711
2712         if (enable_ept) {
2713                 /* nested EPT: emulate EPT also to L1 */
2714                 vmx->nested.nested_vmx_secondary_ctls_high |=
2715                         SECONDARY_EXEC_ENABLE_EPT;
2716                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2717                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2718                          VMX_EPT_INVEPT_BIT;
2719                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2720                 /*
2721                  * For nested guests, we don't do anything specific
2722                  * for single context invalidation. Hence, only advertise
2723                  * support for global context invalidation.
2724                  */
2725                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
2726         } else
2727                 vmx->nested.nested_vmx_ept_caps = 0;
2728
2729         /*
2730          * Old versions of KVM use the single-context version without
2731          * checking for support, so declare that it is supported even
2732          * though it is treated as global context.  The alternative is
2733          * not failing the single-context invvpid, and it is worse.
2734          */
2735         if (enable_vpid)
2736                 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2737                                 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |
2738                                 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
2739         else
2740                 vmx->nested.nested_vmx_vpid_caps = 0;
2741
2742         if (enable_unrestricted_guest)
2743                 vmx->nested.nested_vmx_secondary_ctls_high |=
2744                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2745
2746         /* miscellaneous data */
2747         rdmsr(MSR_IA32_VMX_MISC,
2748                 vmx->nested.nested_vmx_misc_low,
2749                 vmx->nested.nested_vmx_misc_high);
2750         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2751         vmx->nested.nested_vmx_misc_low |=
2752                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2753                 VMX_MISC_ACTIVITY_HLT;
2754         vmx->nested.nested_vmx_misc_high = 0;
2755 }
2756
2757 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2758 {
2759         /*
2760          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2761          */
2762         return ((control & high) | low) == control;
2763 }
2764
2765 static inline u64 vmx_control_msr(u32 low, u32 high)
2766 {
2767         return low | ((u64)high << 32);
2768 }
2769
2770 /* Returns 0 on success, non-0 otherwise. */
2771 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2772 {
2773         struct vcpu_vmx *vmx = to_vmx(vcpu);
2774
2775         switch (msr_index) {
2776         case MSR_IA32_VMX_BASIC:
2777                 /*
2778                  * This MSR reports some information about VMX support. We
2779                  * should return information about the VMX we emulate for the
2780                  * guest, and the VMCS structure we give it - not about the
2781                  * VMX support of the underlying hardware.
2782                  */
2783                 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2784                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2785                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2786                 break;
2787         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2788         case MSR_IA32_VMX_PINBASED_CTLS:
2789                 *pdata = vmx_control_msr(
2790                         vmx->nested.nested_vmx_pinbased_ctls_low,
2791                         vmx->nested.nested_vmx_pinbased_ctls_high);
2792                 break;
2793         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2794                 *pdata = vmx_control_msr(
2795                         vmx->nested.nested_vmx_true_procbased_ctls_low,
2796                         vmx->nested.nested_vmx_procbased_ctls_high);
2797                 break;
2798         case MSR_IA32_VMX_PROCBASED_CTLS:
2799                 *pdata = vmx_control_msr(
2800                         vmx->nested.nested_vmx_procbased_ctls_low,
2801                         vmx->nested.nested_vmx_procbased_ctls_high);
2802                 break;
2803         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2804                 *pdata = vmx_control_msr(
2805                         vmx->nested.nested_vmx_true_exit_ctls_low,
2806                         vmx->nested.nested_vmx_exit_ctls_high);
2807                 break;
2808         case MSR_IA32_VMX_EXIT_CTLS:
2809                 *pdata = vmx_control_msr(
2810                         vmx->nested.nested_vmx_exit_ctls_low,
2811                         vmx->nested.nested_vmx_exit_ctls_high);
2812                 break;
2813         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2814                 *pdata = vmx_control_msr(
2815                         vmx->nested.nested_vmx_true_entry_ctls_low,
2816                         vmx->nested.nested_vmx_entry_ctls_high);
2817                 break;
2818         case MSR_IA32_VMX_ENTRY_CTLS:
2819                 *pdata = vmx_control_msr(
2820                         vmx->nested.nested_vmx_entry_ctls_low,
2821                         vmx->nested.nested_vmx_entry_ctls_high);
2822                 break;
2823         case MSR_IA32_VMX_MISC:
2824                 *pdata = vmx_control_msr(
2825                         vmx->nested.nested_vmx_misc_low,
2826                         vmx->nested.nested_vmx_misc_high);
2827                 break;
2828         /*
2829          * These MSRs specify bits which the guest must keep fixed (on or off)
2830          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2831          * We picked the standard core2 setting.
2832          */
2833 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2834 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2835         case MSR_IA32_VMX_CR0_FIXED0:
2836                 *pdata = VMXON_CR0_ALWAYSON;
2837                 break;
2838         case MSR_IA32_VMX_CR0_FIXED1:
2839                 *pdata = -1ULL;
2840                 break;
2841         case MSR_IA32_VMX_CR4_FIXED0:
2842                 *pdata = VMXON_CR4_ALWAYSON;
2843                 break;
2844         case MSR_IA32_VMX_CR4_FIXED1:
2845                 *pdata = -1ULL;
2846                 break;
2847         case MSR_IA32_VMX_VMCS_ENUM:
2848                 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2849                 break;
2850         case MSR_IA32_VMX_PROCBASED_CTLS2:
2851                 *pdata = vmx_control_msr(
2852                         vmx->nested.nested_vmx_secondary_ctls_low,
2853                         vmx->nested.nested_vmx_secondary_ctls_high);
2854                 break;
2855         case MSR_IA32_VMX_EPT_VPID_CAP:
2856                 /* Currently, no nested vpid support */
2857                 *pdata = vmx->nested.nested_vmx_ept_caps |
2858                         ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
2859                 break;
2860         default:
2861                 return 1;
2862         }
2863
2864         return 0;
2865 }
2866
2867 /*
2868  * Reads an msr value (of 'msr_index') into 'pdata'.
2869  * Returns 0 on success, non-0 otherwise.
2870  * Assumes vcpu_load() was already called.
2871  */
2872 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2873 {
2874         struct shared_msr_entry *msr;
2875
2876         switch (msr_info->index) {
2877 #ifdef CONFIG_X86_64
2878         case MSR_FS_BASE:
2879                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
2880                 break;
2881         case MSR_GS_BASE:
2882                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
2883                 break;
2884         case MSR_KERNEL_GS_BASE:
2885                 vmx_load_host_state(to_vmx(vcpu));
2886                 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2887                 break;
2888 #endif
2889         case MSR_EFER:
2890                 return kvm_get_msr_common(vcpu, msr_info);
2891         case MSR_IA32_TSC:
2892                 msr_info->data = guest_read_tsc(vcpu);
2893                 break;
2894         case MSR_IA32_SYSENTER_CS:
2895                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
2896                 break;
2897         case MSR_IA32_SYSENTER_EIP:
2898                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
2899                 break;
2900         case MSR_IA32_SYSENTER_ESP:
2901                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
2902                 break;
2903         case MSR_IA32_BNDCFGS:
2904                 if (!kvm_mpx_supported())
2905                         return 1;
2906                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
2907                 break;
2908         case MSR_IA32_FEATURE_CONTROL:
2909                 if (!nested_vmx_allowed(vcpu))
2910                         return 1;
2911                 msr_info->data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2912                 break;
2913         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2914                 if (!nested_vmx_allowed(vcpu))
2915                         return 1;
2916                 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
2917         case MSR_IA32_XSS:
2918                 if (!vmx_xsaves_supported())
2919                         return 1;
2920                 msr_info->data = vcpu->arch.ia32_xss;
2921                 break;
2922         case MSR_TSC_AUX:
2923                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
2924                         return 1;
2925                 /* Otherwise falls through */
2926         default:
2927                 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
2928                 if (msr) {
2929                         msr_info->data = msr->data;
2930                         break;
2931                 }
2932                 return kvm_get_msr_common(vcpu, msr_info);
2933         }
2934
2935         return 0;
2936 }
2937
2938 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2939
2940 /*
2941  * Writes msr value into into the appropriate "register".
2942  * Returns 0 on success, non-0 otherwise.
2943  * Assumes vcpu_load() was already called.
2944  */
2945 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2946 {
2947         struct vcpu_vmx *vmx = to_vmx(vcpu);
2948         struct shared_msr_entry *msr;
2949         int ret = 0;
2950         u32 msr_index = msr_info->index;
2951         u64 data = msr_info->data;
2952
2953         switch (msr_index) {
2954         case MSR_EFER:
2955                 ret = kvm_set_msr_common(vcpu, msr_info);
2956                 break;
2957 #ifdef CONFIG_X86_64
2958         case MSR_FS_BASE:
2959                 vmx_segment_cache_clear(vmx);
2960                 vmcs_writel(GUEST_FS_BASE, data);
2961                 break;
2962         case MSR_GS_BASE:
2963                 vmx_segment_cache_clear(vmx);
2964                 vmcs_writel(GUEST_GS_BASE, data);
2965                 break;
2966         case MSR_KERNEL_GS_BASE:
2967                 vmx_load_host_state(vmx);
2968                 vmx->msr_guest_kernel_gs_base = data;
2969                 break;
2970 #endif
2971         case MSR_IA32_SYSENTER_CS:
2972                 vmcs_write32(GUEST_SYSENTER_CS, data);
2973                 break;
2974         case MSR_IA32_SYSENTER_EIP:
2975                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2976                 break;
2977         case MSR_IA32_SYSENTER_ESP:
2978                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2979                 break;
2980         case MSR_IA32_BNDCFGS:
2981                 if (!kvm_mpx_supported())
2982                         return 1;
2983                 vmcs_write64(GUEST_BNDCFGS, data);
2984                 break;
2985         case MSR_IA32_TSC:
2986                 kvm_write_tsc(vcpu, msr_info);
2987                 break;
2988         case MSR_IA32_CR_PAT:
2989                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2990                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2991                                 return 1;
2992                         vmcs_write64(GUEST_IA32_PAT, data);
2993                         vcpu->arch.pat = data;
2994                         break;
2995                 }
2996                 ret = kvm_set_msr_common(vcpu, msr_info);
2997                 break;
2998         case MSR_IA32_TSC_ADJUST:
2999                 ret = kvm_set_msr_common(vcpu, msr_info);
3000                 break;
3001         case MSR_IA32_FEATURE_CONTROL:
3002                 if (!nested_vmx_allowed(vcpu) ||
3003                     (to_vmx(vcpu)->nested.msr_ia32_feature_control &
3004                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3005                         return 1;
3006                 vmx->nested.msr_ia32_feature_control = data;
3007                 if (msr_info->host_initiated && data == 0)
3008                         vmx_leave_nested(vcpu);
3009                 break;
3010         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3011                 return 1; /* they are read-only */
3012         case MSR_IA32_XSS:
3013                 if (!vmx_xsaves_supported())
3014                         return 1;
3015                 /*
3016                  * The only supported bit as of Skylake is bit 8, but
3017                  * it is not supported on KVM.
3018                  */
3019                 if (data != 0)
3020                         return 1;
3021                 vcpu->arch.ia32_xss = data;
3022                 if (vcpu->arch.ia32_xss != host_xss)
3023                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3024                                 vcpu->arch.ia32_xss, host_xss);
3025                 else
3026                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3027                 break;
3028         case MSR_TSC_AUX:
3029                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3030                         return 1;
3031                 /* Check reserved bit, higher 32 bits should be zero */
3032                 if ((data >> 32) != 0)
3033                         return 1;
3034                 /* Otherwise falls through */
3035         default:
3036                 msr = find_msr_entry(vmx, msr_index);
3037                 if (msr) {
3038                         u64 old_msr_data = msr->data;
3039                         msr->data = data;
3040                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3041                                 preempt_disable();
3042                                 ret = kvm_set_shared_msr(msr->index, msr->data,
3043                                                          msr->mask);
3044                                 preempt_enable();
3045                                 if (ret)
3046                                         msr->data = old_msr_data;
3047                         }
3048                         break;
3049                 }
3050                 ret = kvm_set_msr_common(vcpu, msr_info);
3051         }
3052
3053         return ret;
3054 }
3055
3056 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3057 {
3058         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3059         switch (reg) {
3060         case VCPU_REGS_RSP:
3061                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3062                 break;
3063         case VCPU_REGS_RIP:
3064                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3065                 break;
3066         case VCPU_EXREG_PDPTR:
3067                 if (enable_ept)
3068                         ept_save_pdptrs(vcpu);
3069                 break;
3070         default:
3071                 break;
3072         }
3073 }
3074
3075 static __init int cpu_has_kvm_support(void)
3076 {
3077         return cpu_has_vmx();
3078 }
3079
3080 static __init int vmx_disabled_by_bios(void)
3081 {
3082         u64 msr;
3083
3084         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3085         if (msr & FEATURE_CONTROL_LOCKED) {
3086                 /* launched w/ TXT and VMX disabled */
3087                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3088                         && tboot_enabled())
3089                         return 1;
3090                 /* launched w/o TXT and VMX only enabled w/ TXT */
3091                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3092                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3093                         && !tboot_enabled()) {
3094                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3095                                 "activate TXT before enabling KVM\n");
3096                         return 1;
3097                 }
3098                 /* launched w/o TXT and VMX disabled */
3099                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3100                         && !tboot_enabled())
3101                         return 1;
3102         }
3103
3104         return 0;
3105 }
3106
3107 static void kvm_cpu_vmxon(u64 addr)
3108 {
3109         intel_pt_handle_vmx(1);
3110
3111         asm volatile (ASM_VMX_VMXON_RAX
3112                         : : "a"(&addr), "m"(addr)
3113                         : "memory", "cc");
3114 }
3115
3116 static int hardware_enable(void)
3117 {
3118         int cpu = raw_smp_processor_id();
3119         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3120         u64 old, test_bits;
3121
3122         if (cr4_read_shadow() & X86_CR4_VMXE)
3123                 return -EBUSY;
3124
3125         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3126         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3127         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3128
3129         /*
3130          * Now we can enable the vmclear operation in kdump
3131          * since the loaded_vmcss_on_cpu list on this cpu
3132          * has been initialized.
3133          *
3134          * Though the cpu is not in VMX operation now, there
3135          * is no problem to enable the vmclear operation
3136          * for the loaded_vmcss_on_cpu list is empty!
3137          */
3138         crash_enable_local_vmclear(cpu);
3139
3140         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3141
3142         test_bits = FEATURE_CONTROL_LOCKED;
3143         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3144         if (tboot_enabled())
3145                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3146
3147         if ((old & test_bits) != test_bits) {
3148                 /* enable and lock */
3149                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3150         }
3151         cr4_set_bits(X86_CR4_VMXE);
3152
3153         if (vmm_exclusive) {
3154                 kvm_cpu_vmxon(phys_addr);
3155                 ept_sync_global();
3156         }
3157
3158         native_store_gdt(this_cpu_ptr(&host_gdt));
3159
3160         return 0;
3161 }
3162
3163 static void vmclear_local_loaded_vmcss(void)
3164 {
3165         int cpu = raw_smp_processor_id();
3166         struct loaded_vmcs *v, *n;
3167
3168         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3169                                  loaded_vmcss_on_cpu_link)
3170                 __loaded_vmcs_clear(v);
3171 }
3172
3173
3174 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3175  * tricks.
3176  */
3177 static void kvm_cpu_vmxoff(void)
3178 {
3179         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3180
3181         intel_pt_handle_vmx(0);
3182 }
3183
3184 static void hardware_disable(void)
3185 {
3186         if (vmm_exclusive) {
3187                 vmclear_local_loaded_vmcss();
3188                 kvm_cpu_vmxoff();
3189         }
3190         cr4_clear_bits(X86_CR4_VMXE);
3191 }
3192
3193 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3194                                       u32 msr, u32 *result)
3195 {
3196         u32 vmx_msr_low, vmx_msr_high;
3197         u32 ctl = ctl_min | ctl_opt;
3198
3199         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3200
3201         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3202         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3203
3204         /* Ensure minimum (required) set of control bits are supported. */
3205         if (ctl_min & ~ctl)
3206                 return -EIO;
3207
3208         *result = ctl;
3209         return 0;
3210 }
3211
3212 static __init bool allow_1_setting(u32 msr, u32 ctl)
3213 {
3214         u32 vmx_msr_low, vmx_msr_high;
3215
3216         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3217         return vmx_msr_high & ctl;
3218 }
3219
3220 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3221 {
3222         u32 vmx_msr_low, vmx_msr_high;
3223         u32 min, opt, min2, opt2;
3224         u32 _pin_based_exec_control = 0;
3225         u32 _cpu_based_exec_control = 0;
3226         u32 _cpu_based_2nd_exec_control = 0;
3227         u32 _vmexit_control = 0;
3228         u32 _vmentry_control = 0;
3229
3230         min = CPU_BASED_HLT_EXITING |
3231 #ifdef CONFIG_X86_64
3232               CPU_BASED_CR8_LOAD_EXITING |
3233               CPU_BASED_CR8_STORE_EXITING |
3234 #endif
3235               CPU_BASED_CR3_LOAD_EXITING |
3236               CPU_BASED_CR3_STORE_EXITING |
3237               CPU_BASED_USE_IO_BITMAPS |
3238               CPU_BASED_MOV_DR_EXITING |
3239               CPU_BASED_USE_TSC_OFFSETING |
3240               CPU_BASED_MWAIT_EXITING |
3241               CPU_BASED_MONITOR_EXITING |
3242               CPU_BASED_INVLPG_EXITING |
3243               CPU_BASED_RDPMC_EXITING;
3244
3245         opt = CPU_BASED_TPR_SHADOW |
3246               CPU_BASED_USE_MSR_BITMAPS |
3247               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3248         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3249                                 &_cpu_based_exec_control) < 0)
3250                 return -EIO;
3251 #ifdef CONFIG_X86_64
3252         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3253                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3254                                            ~CPU_BASED_CR8_STORE_EXITING;
3255 #endif
3256         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3257                 min2 = 0;
3258                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3259                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3260                         SECONDARY_EXEC_WBINVD_EXITING |
3261                         SECONDARY_EXEC_ENABLE_VPID |
3262                         SECONDARY_EXEC_ENABLE_EPT |
3263                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3264                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3265                         SECONDARY_EXEC_RDTSCP |
3266                         SECONDARY_EXEC_ENABLE_INVPCID |
3267                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3268                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3269                         SECONDARY_EXEC_SHADOW_VMCS |
3270                         SECONDARY_EXEC_XSAVES |
3271                         SECONDARY_EXEC_ENABLE_PML |
3272                         SECONDARY_EXEC_TSC_SCALING;
3273                 if (adjust_vmx_controls(min2, opt2,
3274                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3275                                         &_cpu_based_2nd_exec_control) < 0)
3276                         return -EIO;
3277         }
3278 #ifndef CONFIG_X86_64
3279         if (!(_cpu_based_2nd_exec_control &
3280                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3281                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3282 #endif
3283
3284         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3285                 _cpu_based_2nd_exec_control &= ~(
3286                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3287                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3288                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3289
3290         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3291                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3292                    enabled */
3293                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3294                                              CPU_BASED_CR3_STORE_EXITING |
3295                                              CPU_BASED_INVLPG_EXITING);
3296                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3297                       vmx_capability.ept, vmx_capability.vpid);
3298         }
3299
3300         min = VM_EXIT_SAVE_DEBUG_CONTROLS;
3301 #ifdef CONFIG_X86_64
3302         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3303 #endif
3304         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3305                 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
3306         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3307                                 &_vmexit_control) < 0)
3308                 return -EIO;
3309
3310         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3311         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3312         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3313                                 &_pin_based_exec_control) < 0)
3314                 return -EIO;
3315
3316         if (!(_cpu_based_2nd_exec_control &
3317                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3318                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3319                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3320
3321         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3322         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3323         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3324                                 &_vmentry_control) < 0)
3325                 return -EIO;
3326
3327         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3328
3329         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3330         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3331                 return -EIO;
3332
3333 #ifdef CONFIG_X86_64
3334         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3335         if (vmx_msr_high & (1u<<16))
3336                 return -EIO;
3337 #endif
3338
3339         /* Require Write-Back (WB) memory type for VMCS accesses. */
3340         if (((vmx_msr_high >> 18) & 15) != 6)
3341                 return -EIO;
3342
3343         vmcs_conf->size = vmx_msr_high & 0x1fff;
3344         vmcs_conf->order = get_order(vmcs_config.size);
3345         vmcs_conf->revision_id = vmx_msr_low;
3346
3347         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3348         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3349         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3350         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3351         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3352
3353         cpu_has_load_ia32_efer =
3354                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3355                                 VM_ENTRY_LOAD_IA32_EFER)
3356                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3357                                    VM_EXIT_LOAD_IA32_EFER);
3358
3359         cpu_has_load_perf_global_ctrl =
3360                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3361                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3362                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3363                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3364
3365         /*
3366          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3367          * but due to arrata below it can't be used. Workaround is to use
3368          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3369          *
3370          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3371          *
3372          * AAK155             (model 26)
3373          * AAP115             (model 30)
3374          * AAT100             (model 37)
3375          * BC86,AAY89,BD102   (model 44)
3376          * BA97               (model 46)
3377          *
3378          */
3379         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3380                 switch (boot_cpu_data.x86_model) {
3381                 case 26:
3382                 case 30:
3383                 case 37:
3384                 case 44:
3385                 case 46:
3386                         cpu_has_load_perf_global_ctrl = false;
3387                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3388                                         "does not work properly. Using workaround\n");
3389                         break;
3390                 default:
3391                         break;
3392                 }
3393         }
3394
3395         if (boot_cpu_has(X86_FEATURE_XSAVES))
3396                 rdmsrl(MSR_IA32_XSS, host_xss);
3397
3398         return 0;
3399 }
3400
3401 static struct vmcs *alloc_vmcs_cpu(int cpu)
3402 {
3403         int node = cpu_to_node(cpu);
3404         struct page *pages;
3405         struct vmcs *vmcs;
3406
3407         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3408         if (!pages)
3409                 return NULL;
3410         vmcs = page_address(pages);
3411         memset(vmcs, 0, vmcs_config.size);
3412         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3413         return vmcs;
3414 }
3415
3416 static struct vmcs *alloc_vmcs(void)
3417 {
3418         return alloc_vmcs_cpu(raw_smp_processor_id());
3419 }
3420
3421 static void free_vmcs(struct vmcs *vmcs)
3422 {
3423         free_pages((unsigned long)vmcs, vmcs_config.order);
3424 }
3425
3426 /*
3427  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3428  */
3429 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3430 {
3431         if (!loaded_vmcs->vmcs)
3432                 return;
3433         loaded_vmcs_clear(loaded_vmcs);
3434         free_vmcs(loaded_vmcs->vmcs);
3435         loaded_vmcs->vmcs = NULL;
3436 }
3437
3438 static void free_kvm_area(void)
3439 {
3440         int cpu;
3441
3442         for_each_possible_cpu(cpu) {
3443                 free_vmcs(per_cpu(vmxarea, cpu));
3444                 per_cpu(vmxarea, cpu) = NULL;
3445         }
3446 }
3447
3448 static void init_vmcs_shadow_fields(void)
3449 {
3450         int i, j;
3451
3452         /* No checks for read only fields yet */
3453
3454         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3455                 switch (shadow_read_write_fields[i]) {
3456                 case GUEST_BNDCFGS:
3457                         if (!kvm_mpx_supported())
3458                                 continue;
3459                         break;
3460                 default:
3461                         break;
3462                 }
3463
3464                 if (j < i)
3465                         shadow_read_write_fields[j] =
3466                                 shadow_read_write_fields[i];
3467                 j++;
3468         }
3469         max_shadow_read_write_fields = j;
3470
3471         /* shadowed fields guest access without vmexit */
3472         for (i = 0; i < max_shadow_read_write_fields; i++) {
3473                 clear_bit(shadow_read_write_fields[i],
3474                           vmx_vmwrite_bitmap);
3475                 clear_bit(shadow_read_write_fields[i],
3476                           vmx_vmread_bitmap);
3477         }
3478         for (i = 0; i < max_shadow_read_only_fields; i++)
3479                 clear_bit(shadow_read_only_fields[i],
3480                           vmx_vmread_bitmap);
3481 }
3482
3483 static __init int alloc_kvm_area(void)
3484 {
3485         int cpu;
3486
3487         for_each_possible_cpu(cpu) {
3488                 struct vmcs *vmcs;
3489
3490                 vmcs = alloc_vmcs_cpu(cpu);
3491                 if (!vmcs) {
3492                         free_kvm_area();
3493                         return -ENOMEM;
3494                 }
3495
3496                 per_cpu(vmxarea, cpu) = vmcs;
3497         }
3498         return 0;
3499 }
3500
3501 static bool emulation_required(struct kvm_vcpu *vcpu)
3502 {
3503         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3504 }
3505
3506 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3507                 struct kvm_segment *save)
3508 {
3509         if (!emulate_invalid_guest_state) {
3510                 /*
3511                  * CS and SS RPL should be equal during guest entry according
3512                  * to VMX spec, but in reality it is not always so. Since vcpu
3513                  * is in the middle of the transition from real mode to
3514                  * protected mode it is safe to assume that RPL 0 is a good
3515                  * default value.
3516                  */
3517                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3518                         save->selector &= ~SEGMENT_RPL_MASK;
3519                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3520                 save->s = 1;
3521         }
3522         vmx_set_segment(vcpu, save, seg);
3523 }
3524
3525 static void enter_pmode(struct kvm_vcpu *vcpu)
3526 {
3527         unsigned long flags;
3528         struct vcpu_vmx *vmx = to_vmx(vcpu);
3529
3530         /*
3531          * Update real mode segment cache. It may be not up-to-date if sement
3532          * register was written while vcpu was in a guest mode.
3533          */
3534         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3535         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3536         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3537         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3538         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3539         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3540
3541         vmx->rmode.vm86_active = 0;
3542
3543         vmx_segment_cache_clear(vmx);
3544
3545         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3546
3547         flags = vmcs_readl(GUEST_RFLAGS);
3548         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3549         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3550         vmcs_writel(GUEST_RFLAGS, flags);
3551
3552         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3553                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3554
3555         update_exception_bitmap(vcpu);
3556
3557         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3558         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3559         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3560         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3561         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3562         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3563 }
3564
3565 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3566 {
3567         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3568         struct kvm_segment var = *save;
3569
3570         var.dpl = 0x3;
3571         if (seg == VCPU_SREG_CS)
3572                 var.type = 0x3;
3573
3574         if (!emulate_invalid_guest_state) {
3575                 var.selector = var.base >> 4;
3576                 var.base = var.base & 0xffff0;
3577                 var.limit = 0xffff;
3578                 var.g = 0;
3579                 var.db = 0;
3580                 var.present = 1;
3581                 var.s = 1;
3582                 var.l = 0;
3583                 var.unusable = 0;
3584                 var.type = 0x3;
3585                 var.avl = 0;
3586                 if (save->base & 0xf)
3587                         printk_once(KERN_WARNING "kvm: segment base is not "
3588                                         "paragraph aligned when entering "
3589                                         "protected mode (seg=%d)", seg);
3590         }
3591
3592         vmcs_write16(sf->selector, var.selector);
3593         vmcs_write32(sf->base, var.base);
3594         vmcs_write32(sf->limit, var.limit);
3595         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3596 }
3597
3598 static void enter_rmode(struct kvm_vcpu *vcpu)
3599 {
3600         unsigned long flags;
3601         struct vcpu_vmx *vmx = to_vmx(vcpu);
3602
3603         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3604         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3605         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3606         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3607         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3608         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3609         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3610
3611         vmx->rmode.vm86_active = 1;
3612
3613         /*
3614          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3615          * vcpu. Warn the user that an update is overdue.
3616          */
3617         if (!vcpu->kvm->arch.tss_addr)
3618                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3619                              "called before entering vcpu\n");
3620
3621         vmx_segment_cache_clear(vmx);
3622
3623         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3624         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3625         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3626
3627         flags = vmcs_readl(GUEST_RFLAGS);
3628         vmx->rmode.save_rflags = flags;
3629
3630         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3631
3632         vmcs_writel(GUEST_RFLAGS, flags);
3633         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3634         update_exception_bitmap(vcpu);
3635
3636         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3637         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3638         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3639         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3640         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3641         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3642
3643         kvm_mmu_reset_context(vcpu);
3644 }
3645
3646 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3647 {
3648         struct vcpu_vmx *vmx = to_vmx(vcpu);
3649         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3650
3651         if (!msr)
3652                 return;
3653
3654         /*
3655          * Force kernel_gs_base reloading before EFER changes, as control
3656          * of this msr depends on is_long_mode().
3657          */
3658         vmx_load_host_state(to_vmx(vcpu));
3659         vcpu->arch.efer = efer;
3660         if (efer & EFER_LMA) {
3661                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3662                 msr->data = efer;
3663         } else {
3664                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3665
3666                 msr->data = efer & ~EFER_LME;
3667         }
3668         setup_msrs(vmx);
3669 }
3670
3671 #ifdef CONFIG_X86_64
3672
3673 static void enter_lmode(struct kvm_vcpu *vcpu)
3674 {
3675         u32 guest_tr_ar;
3676
3677         vmx_segment_cache_clear(to_vmx(vcpu));
3678
3679         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3680         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
3681                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3682                                      __func__);
3683                 vmcs_write32(GUEST_TR_AR_BYTES,
3684                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3685                              | VMX_AR_TYPE_BUSY_64_TSS);
3686         }
3687         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3688 }
3689
3690 static void exit_lmode(struct kvm_vcpu *vcpu)
3691 {
3692         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3693         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3694 }
3695
3696 #endif
3697
3698 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
3699 {
3700         vpid_sync_context(vpid);
3701         if (enable_ept) {
3702                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3703                         return;
3704                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3705         }
3706 }
3707
3708 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3709 {
3710         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
3711 }
3712
3713 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3714 {
3715         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3716
3717         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3718         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3719 }
3720
3721 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3722 {
3723         if (enable_ept && is_paging(vcpu))
3724                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3725         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3726 }
3727
3728 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3729 {
3730         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3731
3732         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3733         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3734 }
3735
3736 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3737 {
3738         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3739
3740         if (!test_bit(VCPU_EXREG_PDPTR,
3741                       (unsigned long *)&vcpu->arch.regs_dirty))
3742                 return;
3743
3744         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3745                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3746                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3747                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3748                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3749         }
3750 }
3751
3752 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3753 {
3754         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3755
3756         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3757                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3758                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3759                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3760                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3761         }
3762
3763         __set_bit(VCPU_EXREG_PDPTR,
3764                   (unsigned long *)&vcpu->arch.regs_avail);
3765         __set_bit(VCPU_EXREG_PDPTR,
3766                   (unsigned long *)&vcpu->arch.regs_dirty);
3767 }
3768
3769 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3770
3771 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3772                                         unsigned long cr0,
3773                                         struct kvm_vcpu *vcpu)
3774 {
3775         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3776                 vmx_decache_cr3(vcpu);
3777         if (!(cr0 & X86_CR0_PG)) {
3778                 /* From paging/starting to nonpaging */
3779                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3780                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3781                              (CPU_BASED_CR3_LOAD_EXITING |
3782                               CPU_BASED_CR3_STORE_EXITING));
3783                 vcpu->arch.cr0 = cr0;
3784                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3785         } else if (!is_paging(vcpu)) {
3786                 /* From nonpaging to paging */
3787                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3788                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3789                              ~(CPU_BASED_CR3_LOAD_EXITING |
3790                                CPU_BASED_CR3_STORE_EXITING));
3791                 vcpu->arch.cr0 = cr0;
3792                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3793         }
3794
3795         if (!(cr0 & X86_CR0_WP))
3796                 *hw_cr0 &= ~X86_CR0_WP;
3797 }
3798
3799 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3800 {
3801         struct vcpu_vmx *vmx = to_vmx(vcpu);
3802         unsigned long hw_cr0;
3803
3804         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3805         if (enable_unrestricted_guest)
3806                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3807         else {
3808                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3809
3810                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3811                         enter_pmode(vcpu);
3812
3813                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3814                         enter_rmode(vcpu);
3815         }
3816
3817 #ifdef CONFIG_X86_64
3818         if (vcpu->arch.efer & EFER_LME) {
3819                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3820                         enter_lmode(vcpu);
3821                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3822                         exit_lmode(vcpu);
3823         }
3824 #endif
3825
3826         if (enable_ept)
3827                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3828
3829         if (!vcpu->fpu_active)
3830                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3831
3832         vmcs_writel(CR0_READ_SHADOW, cr0);
3833         vmcs_writel(GUEST_CR0, hw_cr0);
3834         vcpu->arch.cr0 = cr0;
3835
3836         /* depends on vcpu->arch.cr0 to be set to a new value */
3837         vmx->emulation_required = emulation_required(vcpu);
3838 }
3839
3840 static u64 construct_eptp(unsigned long root_hpa)
3841 {
3842         u64 eptp;
3843
3844         /* TODO write the value reading from MSR */
3845         eptp = VMX_EPT_DEFAULT_MT |
3846                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3847         if (enable_ept_ad_bits)
3848                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3849         eptp |= (root_hpa & PAGE_MASK);
3850
3851         return eptp;
3852 }
3853
3854 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3855 {
3856         unsigned long guest_cr3;
3857         u64 eptp;
3858
3859         guest_cr3 = cr3;
3860         if (enable_ept) {
3861                 eptp = construct_eptp(cr3);
3862                 vmcs_write64(EPT_POINTER, eptp);
3863                 if (is_paging(vcpu) || is_guest_mode(vcpu))
3864                         guest_cr3 = kvm_read_cr3(vcpu);
3865                 else
3866                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3867                 ept_load_pdptrs(vcpu);
3868         }
3869
3870         vmx_flush_tlb(vcpu);
3871         vmcs_writel(GUEST_CR3, guest_cr3);
3872 }
3873
3874 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3875 {
3876         /*
3877          * Pass through host's Machine Check Enable value to hw_cr4, which
3878          * is in force while we are in guest mode.  Do not let guests control
3879          * this bit, even if host CR4.MCE == 0.
3880          */
3881         unsigned long hw_cr4 =
3882                 (cr4_read_shadow() & X86_CR4_MCE) |
3883                 (cr4 & ~X86_CR4_MCE) |
3884                 (to_vmx(vcpu)->rmode.vm86_active ?
3885                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3886
3887         if (cr4 & X86_CR4_VMXE) {
3888                 /*
3889                  * To use VMXON (and later other VMX instructions), a guest
3890                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3891                  * So basically the check on whether to allow nested VMX
3892                  * is here.
3893                  */
3894                 if (!nested_vmx_allowed(vcpu))
3895                         return 1;
3896         }
3897         if (to_vmx(vcpu)->nested.vmxon &&
3898             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3899                 return 1;
3900
3901         vcpu->arch.cr4 = cr4;
3902         if (enable_ept) {
3903                 if (!is_paging(vcpu)) {
3904                         hw_cr4 &= ~X86_CR4_PAE;
3905                         hw_cr4 |= X86_CR4_PSE;
3906                 } else if (!(cr4 & X86_CR4_PAE)) {
3907                         hw_cr4 &= ~X86_CR4_PAE;
3908                 }
3909         }
3910
3911         if (!enable_unrestricted_guest && !is_paging(vcpu))
3912                 /*
3913                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
3914                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
3915                  * to be manually disabled when guest switches to non-paging
3916                  * mode.
3917                  *
3918                  * If !enable_unrestricted_guest, the CPU is always running
3919                  * with CR0.PG=1 and CR4 needs to be modified.
3920                  * If enable_unrestricted_guest, the CPU automatically
3921                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
3922                  */
3923                 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
3924
3925         vmcs_writel(CR4_READ_SHADOW, cr4);
3926         vmcs_writel(GUEST_CR4, hw_cr4);
3927         return 0;
3928 }
3929
3930 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3931                             struct kvm_segment *var, int seg)
3932 {
3933         struct vcpu_vmx *vmx = to_vmx(vcpu);
3934         u32 ar;
3935
3936         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3937                 *var = vmx->rmode.segs[seg];
3938                 if (seg == VCPU_SREG_TR
3939                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3940                         return;
3941                 var->base = vmx_read_guest_seg_base(vmx, seg);
3942                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3943                 return;
3944         }
3945         var->base = vmx_read_guest_seg_base(vmx, seg);
3946         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3947         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3948         ar = vmx_read_guest_seg_ar(vmx, seg);
3949         var->unusable = (ar >> 16) & 1;
3950         var->type = ar & 15;
3951         var->s = (ar >> 4) & 1;
3952         var->dpl = (ar >> 5) & 3;
3953         /*
3954          * Some userspaces do not preserve unusable property. Since usable
3955          * segment has to be present according to VMX spec we can use present
3956          * property to amend userspace bug by making unusable segment always
3957          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3958          * segment as unusable.
3959          */
3960         var->present = !var->unusable;
3961         var->avl = (ar >> 12) & 1;
3962         var->l = (ar >> 13) & 1;
3963         var->db = (ar >> 14) & 1;
3964         var->g = (ar >> 15) & 1;
3965 }
3966
3967 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3968 {
3969         struct kvm_segment s;
3970
3971         if (to_vmx(vcpu)->rmode.vm86_active) {
3972                 vmx_get_segment(vcpu, &s, seg);
3973                 return s.base;
3974         }
3975         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3976 }
3977
3978 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3979 {
3980         struct vcpu_vmx *vmx = to_vmx(vcpu);
3981
3982         if (unlikely(vmx->rmode.vm86_active))
3983                 return 0;
3984         else {
3985                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3986                 return VMX_AR_DPL(ar);
3987         }
3988 }
3989
3990 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3991 {
3992         u32 ar;
3993
3994         if (var->unusable || !var->present)
3995                 ar = 1 << 16;
3996         else {
3997                 ar = var->type & 15;
3998                 ar |= (var->s & 1) << 4;
3999                 ar |= (var->dpl & 3) << 5;
4000                 ar |= (var->present & 1) << 7;
4001                 ar |= (var->avl & 1) << 12;
4002                 ar |= (var->l & 1) << 13;
4003                 ar |= (var->db & 1) << 14;
4004                 ar |= (var->g & 1) << 15;
4005         }
4006
4007         return ar;
4008 }
4009
4010 static void vmx_set_segment(struct kvm_vcpu *vcpu,
4011                             struct kvm_segment *var, int seg)
4012 {
4013         struct vcpu_vmx *vmx = to_vmx(vcpu);
4014         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4015
4016         vmx_segment_cache_clear(vmx);
4017
4018         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4019                 vmx->rmode.segs[seg] = *var;
4020                 if (seg == VCPU_SREG_TR)
4021                         vmcs_write16(sf->selector, var->selector);
4022                 else if (var->s)
4023                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
4024                 goto out;
4025         }
4026
4027         vmcs_writel(sf->base, var->base);
4028         vmcs_write32(sf->limit, var->limit);
4029         vmcs_write16(sf->selector, var->selector);
4030
4031         /*
4032          *   Fix the "Accessed" bit in AR field of segment registers for older
4033          * qemu binaries.
4034          *   IA32 arch specifies that at the time of processor reset the
4035          * "Accessed" bit in the AR field of segment registers is 1. And qemu
4036          * is setting it to 0 in the userland code. This causes invalid guest
4037          * state vmexit when "unrestricted guest" mode is turned on.
4038          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
4039          * tree. Newer qemu binaries with that qemu fix would not need this
4040          * kvm hack.
4041          */
4042         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
4043                 var->type |= 0x1; /* Accessed */
4044
4045         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
4046
4047 out:
4048         vmx->emulation_required = emulation_required(vcpu);
4049 }
4050
4051 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4052 {
4053         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4054
4055         *db = (ar >> 14) & 1;
4056         *l = (ar >> 13) & 1;
4057 }
4058
4059 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4060 {
4061         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4062         dt->address = vmcs_readl(GUEST_IDTR_BASE);
4063 }
4064
4065 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4066 {
4067         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4068         vmcs_writel(GUEST_IDTR_BASE, dt->address);
4069 }
4070
4071 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4072 {
4073         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4074         dt->address = vmcs_readl(GUEST_GDTR_BASE);
4075 }
4076
4077 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4078 {
4079         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4080         vmcs_writel(GUEST_GDTR_BASE, dt->address);
4081 }
4082
4083 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4084 {
4085         struct kvm_segment var;
4086         u32 ar;
4087
4088         vmx_get_segment(vcpu, &var, seg);
4089         var.dpl = 0x3;
4090         if (seg == VCPU_SREG_CS)
4091                 var.type = 0x3;
4092         ar = vmx_segment_access_rights(&var);
4093
4094         if (var.base != (var.selector << 4))
4095                 return false;
4096         if (var.limit != 0xffff)
4097                 return false;
4098         if (ar != 0xf3)
4099                 return false;
4100
4101         return true;
4102 }
4103
4104 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4105 {
4106         struct kvm_segment cs;
4107         unsigned int cs_rpl;
4108
4109         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4110         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4111
4112         if (cs.unusable)
4113                 return false;
4114         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4115                 return false;
4116         if (!cs.s)
4117                 return false;
4118         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4119                 if (cs.dpl > cs_rpl)
4120                         return false;
4121         } else {
4122                 if (cs.dpl != cs_rpl)
4123                         return false;
4124         }
4125         if (!cs.present)
4126                 return false;
4127
4128         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4129         return true;
4130 }
4131
4132 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4133 {
4134         struct kvm_segment ss;
4135         unsigned int ss_rpl;
4136
4137         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4138         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4139
4140         if (ss.unusable)
4141                 return true;
4142         if (ss.type != 3 && ss.type != 7)
4143                 return false;
4144         if (!ss.s)
4145                 return false;
4146         if (ss.dpl != ss_rpl) /* DPL != RPL */
4147                 return false;
4148         if (!ss.present)
4149                 return false;
4150
4151         return true;
4152 }
4153
4154 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4155 {
4156         struct kvm_segment var;
4157         unsigned int rpl;
4158
4159         vmx_get_segment(vcpu, &var, seg);
4160         rpl = var.selector & SEGMENT_RPL_MASK;
4161
4162         if (var.unusable)
4163                 return true;
4164         if (!var.s)
4165                 return false;
4166         if (!var.present)
4167                 return false;
4168         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4169                 if (var.dpl < rpl) /* DPL < RPL */
4170                         return false;
4171         }
4172
4173         /* TODO: Add other members to kvm_segment_field to allow checking for other access
4174          * rights flags
4175          */
4176         return true;
4177 }
4178
4179 static bool tr_valid(struct kvm_vcpu *vcpu)
4180 {
4181         struct kvm_segment tr;
4182
4183         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4184
4185         if (tr.unusable)
4186                 return false;
4187         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
4188                 return false;
4189         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4190                 return false;
4191         if (!tr.present)
4192                 return false;
4193
4194         return true;
4195 }
4196
4197 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4198 {
4199         struct kvm_segment ldtr;
4200
4201         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4202
4203         if (ldtr.unusable)
4204                 return true;
4205         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
4206                 return false;
4207         if (ldtr.type != 2)
4208                 return false;
4209         if (!ldtr.present)
4210                 return false;
4211
4212         return true;
4213 }
4214
4215 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4216 {
4217         struct kvm_segment cs, ss;
4218
4219         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4220         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4221
4222         return ((cs.selector & SEGMENT_RPL_MASK) ==
4223                  (ss.selector & SEGMENT_RPL_MASK));
4224 }
4225
4226 /*
4227  * Check if guest state is valid. Returns true if valid, false if
4228  * not.
4229  * We assume that registers are always usable
4230  */
4231 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4232 {
4233         if (enable_unrestricted_guest)
4234                 return true;
4235
4236         /* real mode guest state checks */
4237         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4238                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4239                         return false;
4240                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4241                         return false;
4242                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4243                         return false;
4244                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4245                         return false;
4246                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4247                         return false;
4248                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4249                         return false;
4250         } else {
4251         /* protected mode guest state checks */
4252                 if (!cs_ss_rpl_check(vcpu))
4253                         return false;
4254                 if (!code_segment_valid(vcpu))
4255                         return false;
4256                 if (!stack_segment_valid(vcpu))
4257                         return false;
4258                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4259                         return false;
4260                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4261                         return false;
4262                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4263                         return false;
4264                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4265                         return false;
4266                 if (!tr_valid(vcpu))
4267                         return false;
4268                 if (!ldtr_valid(vcpu))
4269                         return false;
4270         }
4271         /* TODO:
4272          * - Add checks on RIP
4273          * - Add checks on RFLAGS
4274          */
4275
4276         return true;
4277 }
4278
4279 static int init_rmode_tss(struct kvm *kvm)
4280 {
4281         gfn_t fn;
4282         u16 data = 0;
4283         int idx, r;
4284
4285         idx = srcu_read_lock(&kvm->srcu);
4286         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4287         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4288         if (r < 0)
4289                 goto out;
4290         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4291         r = kvm_write_guest_page(kvm, fn++, &data,
4292                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4293         if (r < 0)
4294                 goto out;
4295         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4296         if (r < 0)
4297                 goto out;
4298         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4299         if (r < 0)
4300                 goto out;
4301         data = ~0;
4302         r = kvm_write_guest_page(kvm, fn, &data,
4303                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4304                                  sizeof(u8));
4305 out:
4306         srcu_read_unlock(&kvm->srcu, idx);
4307         return r;
4308 }
4309
4310 static int init_rmode_identity_map(struct kvm *kvm)
4311 {
4312         int i, idx, r = 0;
4313         kvm_pfn_t identity_map_pfn;
4314         u32 tmp;
4315
4316         if (!enable_ept)
4317                 return 0;
4318
4319         /* Protect kvm->arch.ept_identity_pagetable_done. */
4320         mutex_lock(&kvm->slots_lock);
4321
4322         if (likely(kvm->arch.ept_identity_pagetable_done))
4323                 goto out2;
4324
4325         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4326
4327         r = alloc_identity_pagetable(kvm);
4328         if (r < 0)
4329                 goto out2;
4330
4331         idx = srcu_read_lock(&kvm->srcu);
4332         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4333         if (r < 0)
4334                 goto out;
4335         /* Set up identity-mapping pagetable for EPT in real mode */
4336         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4337                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4338                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4339                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4340                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4341                 if (r < 0)
4342                         goto out;
4343         }
4344         kvm->arch.ept_identity_pagetable_done = true;
4345
4346 out:
4347         srcu_read_unlock(&kvm->srcu, idx);
4348
4349 out2:
4350         mutex_unlock(&kvm->slots_lock);
4351         return r;
4352 }
4353
4354 static void seg_setup(int seg)
4355 {
4356         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4357         unsigned int ar;
4358
4359         vmcs_write16(sf->selector, 0);
4360         vmcs_writel(sf->base, 0);
4361         vmcs_write32(sf->limit, 0xffff);
4362         ar = 0x93;
4363         if (seg == VCPU_SREG_CS)
4364                 ar |= 0x08; /* code segment */
4365
4366         vmcs_write32(sf->ar_bytes, ar);
4367 }
4368
4369 static int alloc_apic_access_page(struct kvm *kvm)
4370 {
4371         struct page *page;
4372         int r = 0;
4373
4374         mutex_lock(&kvm->slots_lock);
4375         if (kvm->arch.apic_access_page_done)
4376                 goto out;
4377         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4378                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4379         if (r)
4380                 goto out;
4381
4382         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4383         if (is_error_page(page)) {
4384                 r = -EFAULT;
4385                 goto out;
4386         }
4387
4388         /*
4389          * Do not pin the page in memory, so that memory hot-unplug
4390          * is able to migrate it.
4391          */
4392         put_page(page);
4393         kvm->arch.apic_access_page_done = true;
4394 out:
4395         mutex_unlock(&kvm->slots_lock);
4396         return r;
4397 }
4398
4399 static int alloc_identity_pagetable(struct kvm *kvm)
4400 {
4401         /* Called with kvm->slots_lock held. */
4402
4403         int r = 0;
4404
4405         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4406
4407         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4408                                     kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4409
4410         return r;
4411 }
4412
4413 static int allocate_vpid(void)
4414 {
4415         int vpid;
4416
4417         if (!enable_vpid)
4418                 return 0;
4419         spin_lock(&vmx_vpid_lock);
4420         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4421         if (vpid < VMX_NR_VPIDS)
4422                 __set_bit(vpid, vmx_vpid_bitmap);
4423         else
4424                 vpid = 0;
4425         spin_unlock(&vmx_vpid_lock);
4426         return vpid;
4427 }
4428
4429 static void free_vpid(int vpid)
4430 {
4431         if (!enable_vpid || vpid == 0)
4432                 return;
4433         spin_lock(&vmx_vpid_lock);
4434         __clear_bit(vpid, vmx_vpid_bitmap);
4435         spin_unlock(&vmx_vpid_lock);
4436 }
4437
4438 #define MSR_TYPE_R      1
4439 #define MSR_TYPE_W      2
4440 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4441                                                 u32 msr, int type)
4442 {
4443         int f = sizeof(unsigned long);
4444
4445         if (!cpu_has_vmx_msr_bitmap())
4446                 return;
4447
4448         /*
4449          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4450          * have the write-low and read-high bitmap offsets the wrong way round.
4451          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4452          */
4453         if (msr <= 0x1fff) {
4454                 if (type & MSR_TYPE_R)
4455                         /* read-low */
4456                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4457
4458                 if (type & MSR_TYPE_W)
4459                         /* write-low */
4460                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4461
4462         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4463                 msr &= 0x1fff;
4464                 if (type & MSR_TYPE_R)
4465                         /* read-high */
4466                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4467
4468                 if (type & MSR_TYPE_W)
4469                         /* write-high */
4470                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4471
4472         }
4473 }
4474
4475 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4476                                                 u32 msr, int type)
4477 {
4478         int f = sizeof(unsigned long);
4479
4480         if (!cpu_has_vmx_msr_bitmap())
4481                 return;
4482
4483         /*
4484          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4485          * have the write-low and read-high bitmap offsets the wrong way round.
4486          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4487          */
4488         if (msr <= 0x1fff) {
4489                 if (type & MSR_TYPE_R)
4490                         /* read-low */
4491                         __set_bit(msr, msr_bitmap + 0x000 / f);
4492
4493                 if (type & MSR_TYPE_W)
4494                         /* write-low */
4495                         __set_bit(msr, msr_bitmap + 0x800 / f);
4496
4497         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4498                 msr &= 0x1fff;
4499                 if (type & MSR_TYPE_R)
4500                         /* read-high */
4501                         __set_bit(msr, msr_bitmap + 0x400 / f);
4502
4503                 if (type & MSR_TYPE_W)
4504                         /* write-high */
4505                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4506
4507         }
4508 }
4509
4510 /*
4511  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4512  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4513  */
4514 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4515                                                unsigned long *msr_bitmap_nested,
4516                                                u32 msr, int type)
4517 {
4518         int f = sizeof(unsigned long);
4519
4520         if (!cpu_has_vmx_msr_bitmap()) {
4521                 WARN_ON(1);
4522                 return;
4523         }
4524
4525         /*
4526          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4527          * have the write-low and read-high bitmap offsets the wrong way round.
4528          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4529          */
4530         if (msr <= 0x1fff) {
4531                 if (type & MSR_TYPE_R &&
4532                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4533                         /* read-low */
4534                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4535
4536                 if (type & MSR_TYPE_W &&
4537                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4538                         /* write-low */
4539                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4540
4541         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4542                 msr &= 0x1fff;
4543                 if (type & MSR_TYPE_R &&
4544                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4545                         /* read-high */
4546                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4547
4548                 if (type & MSR_TYPE_W &&
4549                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4550                         /* write-high */
4551                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4552
4553         }
4554 }
4555
4556 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4557 {
4558         if (!longmode_only)
4559                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4560                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4561         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4562                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4563 }
4564
4565 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4566 {
4567         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4568                         msr, MSR_TYPE_R);
4569         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4570                         msr, MSR_TYPE_R);
4571 }
4572
4573 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4574 {
4575         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4576                         msr, MSR_TYPE_R);
4577         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4578                         msr, MSR_TYPE_R);
4579 }
4580
4581 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4582 {
4583         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4584                         msr, MSR_TYPE_W);
4585         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4586                         msr, MSR_TYPE_W);
4587 }
4588
4589 static bool vmx_get_enable_apicv(void)
4590 {
4591         return enable_apicv;
4592 }
4593
4594 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4595 {
4596         struct vcpu_vmx *vmx = to_vmx(vcpu);
4597         int max_irr;
4598         void *vapic_page;
4599         u16 status;
4600
4601         if (vmx->nested.pi_desc &&
4602             vmx->nested.pi_pending) {
4603                 vmx->nested.pi_pending = false;
4604                 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4605                         return 0;
4606
4607                 max_irr = find_last_bit(
4608                         (unsigned long *)vmx->nested.pi_desc->pir, 256);
4609
4610                 if (max_irr == 256)
4611                         return 0;
4612
4613                 vapic_page = kmap(vmx->nested.virtual_apic_page);
4614                 if (!vapic_page) {
4615                         WARN_ON(1);
4616                         return -ENOMEM;
4617                 }
4618                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4619                 kunmap(vmx->nested.virtual_apic_page);
4620
4621                 status = vmcs_read16(GUEST_INTR_STATUS);
4622                 if ((u8)max_irr > ((u8)status & 0xff)) {
4623                         status &= ~0xff;
4624                         status |= (u8)max_irr;
4625                         vmcs_write16(GUEST_INTR_STATUS, status);
4626                 }
4627         }
4628         return 0;
4629 }
4630
4631 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4632 {
4633 #ifdef CONFIG_SMP
4634         if (vcpu->mode == IN_GUEST_MODE) {
4635                 struct vcpu_vmx *vmx = to_vmx(vcpu);
4636
4637                 /*
4638                  * Currently, we don't support urgent interrupt,
4639                  * all interrupts are recognized as non-urgent
4640                  * interrupt, so we cannot post interrupts when
4641                  * 'SN' is set.
4642                  *
4643                  * If the vcpu is in guest mode, it means it is
4644                  * running instead of being scheduled out and
4645                  * waiting in the run queue, and that's the only
4646                  * case when 'SN' is set currently, warning if
4647                  * 'SN' is set.
4648                  */
4649                 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4650
4651                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4652                                 POSTED_INTR_VECTOR);
4653                 return true;
4654         }
4655 #endif
4656         return false;
4657 }
4658
4659 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4660                                                 int vector)
4661 {
4662         struct vcpu_vmx *vmx = to_vmx(vcpu);
4663
4664         if (is_guest_mode(vcpu) &&
4665             vector == vmx->nested.posted_intr_nv) {
4666                 /* the PIR and ON have been set by L1. */
4667                 kvm_vcpu_trigger_posted_interrupt(vcpu);
4668                 /*
4669                  * If a posted intr is not recognized by hardware,
4670                  * we will accomplish it in the next vmentry.
4671                  */
4672                 vmx->nested.pi_pending = true;
4673                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4674                 return 0;
4675         }
4676         return -1;
4677 }
4678 /*
4679  * Send interrupt to vcpu via posted interrupt way.
4680  * 1. If target vcpu is running(non-root mode), send posted interrupt
4681  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4682  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4683  * interrupt from PIR in next vmentry.
4684  */
4685 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4686 {
4687         struct vcpu_vmx *vmx = to_vmx(vcpu);
4688         int r;
4689
4690         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4691         if (!r)
4692                 return;
4693
4694         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4695                 return;
4696
4697         r = pi_test_and_set_on(&vmx->pi_desc);
4698         kvm_make_request(KVM_REQ_EVENT, vcpu);
4699         if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
4700                 kvm_vcpu_kick(vcpu);
4701 }
4702
4703 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4704 {
4705         struct vcpu_vmx *vmx = to_vmx(vcpu);
4706
4707         if (!pi_test_and_clear_on(&vmx->pi_desc))
4708                 return;
4709
4710         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4711 }
4712
4713 /*
4714  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4715  * will not change in the lifetime of the guest.
4716  * Note that host-state that does change is set elsewhere. E.g., host-state
4717  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4718  */
4719 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4720 {
4721         u32 low32, high32;
4722         unsigned long tmpl;
4723         struct desc_ptr dt;
4724         unsigned long cr4;
4725
4726         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4727         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4728
4729         /* Save the most likely value for this task's CR4 in the VMCS. */
4730         cr4 = cr4_read_shadow();
4731         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
4732         vmx->host_state.vmcs_host_cr4 = cr4;
4733
4734         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4735 #ifdef CONFIG_X86_64
4736         /*
4737          * Load null selectors, so we can avoid reloading them in
4738          * __vmx_load_host_state(), in case userspace uses the null selectors
4739          * too (the expected case).
4740          */
4741         vmcs_write16(HOST_DS_SELECTOR, 0);
4742         vmcs_write16(HOST_ES_SELECTOR, 0);
4743 #else
4744         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4745         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4746 #endif
4747         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4748         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4749
4750         native_store_idt(&dt);
4751         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4752         vmx->host_idt_base = dt.address;
4753
4754         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4755
4756         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4757         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4758         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4759         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4760
4761         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4762                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4763                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4764         }
4765 }
4766
4767 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4768 {
4769         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4770         if (enable_ept)
4771                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4772         if (is_guest_mode(&vmx->vcpu))
4773                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4774                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4775         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4776 }
4777
4778 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4779 {
4780         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4781
4782         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4783                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4784         return pin_based_exec_ctrl;
4785 }
4786
4787 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4788 {
4789         struct vcpu_vmx *vmx = to_vmx(vcpu);
4790
4791         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4792         if (cpu_has_secondary_exec_ctrls()) {
4793                 if (kvm_vcpu_apicv_active(vcpu))
4794                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
4795                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
4796                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4797                 else
4798                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
4799                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
4800                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4801         }
4802
4803         if (cpu_has_vmx_msr_bitmap())
4804                 vmx_set_msr_bitmap(vcpu);
4805 }
4806
4807 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4808 {
4809         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4810
4811         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4812                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4813
4814         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4815                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4816 #ifdef CONFIG_X86_64
4817                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4818                                 CPU_BASED_CR8_LOAD_EXITING;
4819 #endif
4820         }
4821         if (!enable_ept)
4822                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4823                                 CPU_BASED_CR3_LOAD_EXITING  |
4824                                 CPU_BASED_INVLPG_EXITING;
4825         return exec_control;
4826 }
4827
4828 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4829 {
4830         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4831         if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
4832                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4833         if (vmx->vpid == 0)
4834                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4835         if (!enable_ept) {
4836                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4837                 enable_unrestricted_guest = 0;
4838                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4839                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4840         }
4841         if (!enable_unrestricted_guest)
4842                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4843         if (!ple_gap)
4844                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4845         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4846                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4847                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4848         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4849         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4850            (handle_vmptrld).
4851            We can NOT enable shadow_vmcs here because we don't have yet
4852            a current VMCS12
4853         */
4854         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4855
4856         if (!enable_pml)
4857                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4858
4859         return exec_control;
4860 }
4861
4862 static void ept_set_mmio_spte_mask(void)
4863 {
4864         /*
4865          * EPT Misconfigurations can be generated if the value of bits 2:0
4866          * of an EPT paging-structure entry is 110b (write/execute).
4867          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4868          * spte.
4869          */
4870         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4871 }
4872
4873 #define VMX_XSS_EXIT_BITMAP 0
4874 /*
4875  * Sets up the vmcs for emulated real mode.
4876  */
4877 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4878 {
4879 #ifdef CONFIG_X86_64
4880         unsigned long a;
4881 #endif
4882         int i;
4883
4884         /* I/O */
4885         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4886         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4887
4888         if (enable_shadow_vmcs) {
4889                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4890                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4891         }
4892         if (cpu_has_vmx_msr_bitmap())
4893                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4894
4895         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4896
4897         /* Control */
4898         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4899
4900         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4901
4902         if (cpu_has_secondary_exec_ctrls()) {
4903                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4904                                 vmx_secondary_exec_control(vmx));
4905         }
4906
4907         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4908                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4909                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4910                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4911                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4912
4913                 vmcs_write16(GUEST_INTR_STATUS, 0);
4914
4915                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4916                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4917         }
4918
4919         if (ple_gap) {
4920                 vmcs_write32(PLE_GAP, ple_gap);
4921                 vmx->ple_window = ple_window;
4922                 vmx->ple_window_dirty = true;
4923         }
4924
4925         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4926         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4927         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4928
4929         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4930         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4931         vmx_set_constant_host_state(vmx);
4932 #ifdef CONFIG_X86_64
4933         rdmsrl(MSR_FS_BASE, a);
4934         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4935         rdmsrl(MSR_GS_BASE, a);
4936         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4937 #else
4938         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4939         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4940 #endif
4941
4942         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4943         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4944         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4945         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4946         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4947
4948         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4949                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4950
4951         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4952                 u32 index = vmx_msr_index[i];
4953                 u32 data_low, data_high;
4954                 int j = vmx->nmsrs;
4955
4956                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4957                         continue;
4958                 if (wrmsr_safe(index, data_low, data_high) < 0)
4959                         continue;
4960                 vmx->guest_msrs[j].index = i;
4961                 vmx->guest_msrs[j].data = 0;
4962                 vmx->guest_msrs[j].mask = -1ull;
4963                 ++vmx->nmsrs;
4964         }
4965
4966
4967         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
4968
4969         /* 22.2.1, 20.8.1 */
4970         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
4971
4972         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4973         set_cr4_guest_host_mask(vmx);
4974
4975         if (vmx_xsaves_supported())
4976                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4977
4978         if (enable_pml) {
4979                 ASSERT(vmx->pml_pg);
4980                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
4981                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
4982         }
4983
4984         return 0;
4985 }
4986
4987 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4988 {
4989         struct vcpu_vmx *vmx = to_vmx(vcpu);
4990         struct msr_data apic_base_msr;
4991         u64 cr0;
4992
4993         vmx->rmode.vm86_active = 0;
4994
4995         vmx->soft_vnmi_blocked = 0;
4996
4997         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4998         kvm_set_cr8(vcpu, 0);
4999
5000         if (!init_event) {
5001                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
5002                                      MSR_IA32_APICBASE_ENABLE;
5003                 if (kvm_vcpu_is_reset_bsp(vcpu))
5004                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
5005                 apic_base_msr.host_initiated = true;
5006                 kvm_set_apic_base(vcpu, &apic_base_msr);
5007         }
5008
5009         vmx_segment_cache_clear(vmx);
5010
5011         seg_setup(VCPU_SREG_CS);
5012         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
5013         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
5014
5015         seg_setup(VCPU_SREG_DS);
5016         seg_setup(VCPU_SREG_ES);
5017         seg_setup(VCPU_SREG_FS);
5018         seg_setup(VCPU_SREG_GS);
5019         seg_setup(VCPU_SREG_SS);
5020
5021         vmcs_write16(GUEST_TR_SELECTOR, 0);
5022         vmcs_writel(GUEST_TR_BASE, 0);
5023         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5024         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5025
5026         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5027         vmcs_writel(GUEST_LDTR_BASE, 0);
5028         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5029         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5030
5031         if (!init_event) {
5032                 vmcs_write32(GUEST_SYSENTER_CS, 0);
5033                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5034                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5035                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5036         }
5037
5038         vmcs_writel(GUEST_RFLAGS, 0x02);
5039         kvm_rip_write(vcpu, 0xfff0);
5040
5041         vmcs_writel(GUEST_GDTR_BASE, 0);
5042         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5043
5044         vmcs_writel(GUEST_IDTR_BASE, 0);
5045         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5046
5047         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
5048         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
5049         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
5050
5051         setup_msrs(vmx);
5052
5053         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
5054
5055         if (cpu_has_vmx_tpr_shadow() && !init_event) {
5056                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
5057                 if (cpu_need_tpr_shadow(vcpu))
5058                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
5059                                      __pa(vcpu->arch.apic->regs));
5060                 vmcs_write32(TPR_THRESHOLD, 0);
5061         }
5062
5063         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
5064
5065         if (kvm_vcpu_apicv_active(vcpu))
5066                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5067
5068         if (vmx->vpid != 0)
5069                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5070
5071         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5072         vmx->vcpu.arch.cr0 = cr0;
5073         vmx_set_cr0(vcpu, cr0); /* enter rmode */
5074         vmx_set_cr4(vcpu, 0);
5075         vmx_set_efer(vcpu, 0);
5076         vmx_fpu_activate(vcpu);
5077         update_exception_bitmap(vcpu);
5078
5079         vpid_sync_context(vmx->vpid);
5080 }
5081
5082 /*
5083  * In nested virtualization, check if L1 asked to exit on external interrupts.
5084  * For most existing hypervisors, this will always return true.
5085  */
5086 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5087 {
5088         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5089                 PIN_BASED_EXT_INTR_MASK;
5090 }
5091
5092 /*
5093  * In nested virtualization, check if L1 has set
5094  * VM_EXIT_ACK_INTR_ON_EXIT
5095  */
5096 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5097 {
5098         return get_vmcs12(vcpu)->vm_exit_controls &
5099                 VM_EXIT_ACK_INTR_ON_EXIT;
5100 }
5101
5102 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5103 {
5104         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5105                 PIN_BASED_NMI_EXITING;
5106 }
5107
5108 static void enable_irq_window(struct kvm_vcpu *vcpu)
5109 {
5110         u32 cpu_based_vm_exec_control;
5111
5112         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5113         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
5114         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5115 }
5116
5117 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5118 {
5119         u32 cpu_based_vm_exec_control;
5120
5121         if (!cpu_has_virtual_nmis() ||
5122             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5123                 enable_irq_window(vcpu);
5124                 return;
5125         }
5126
5127         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5128         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
5129         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5130 }
5131
5132 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5133 {
5134         struct vcpu_vmx *vmx = to_vmx(vcpu);
5135         uint32_t intr;
5136         int irq = vcpu->arch.interrupt.nr;
5137
5138         trace_kvm_inj_virq(irq);
5139
5140         ++vcpu->stat.irq_injections;
5141         if (vmx->rmode.vm86_active) {
5142                 int inc_eip = 0;
5143                 if (vcpu->arch.interrupt.soft)
5144                         inc_eip = vcpu->arch.event_exit_inst_len;
5145                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5146                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5147                 return;
5148         }
5149         intr = irq | INTR_INFO_VALID_MASK;
5150         if (vcpu->arch.interrupt.soft) {
5151                 intr |= INTR_TYPE_SOFT_INTR;
5152                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5153                              vmx->vcpu.arch.event_exit_inst_len);
5154         } else
5155                 intr |= INTR_TYPE_EXT_INTR;
5156         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5157 }
5158
5159 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5160 {
5161         struct vcpu_vmx *vmx = to_vmx(vcpu);
5162
5163         if (is_guest_mode(vcpu))
5164                 return;
5165
5166         if (!cpu_has_virtual_nmis()) {
5167                 /*
5168                  * Tracking the NMI-blocked state in software is built upon
5169                  * finding the next open IRQ window. This, in turn, depends on
5170                  * well-behaving guests: They have to keep IRQs disabled at
5171                  * least as long as the NMI handler runs. Otherwise we may
5172                  * cause NMI nesting, maybe breaking the guest. But as this is
5173                  * highly unlikely, we can live with the residual risk.
5174                  */
5175                 vmx->soft_vnmi_blocked = 1;
5176                 vmx->vnmi_blocked_time = 0;
5177         }
5178
5179         ++vcpu->stat.nmi_injections;
5180         vmx->nmi_known_unmasked = false;
5181         if (vmx->rmode.vm86_active) {
5182                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5183                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5184                 return;
5185         }
5186         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5187                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5188 }
5189
5190 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5191 {
5192         if (!cpu_has_virtual_nmis())
5193                 return to_vmx(vcpu)->soft_vnmi_blocked;
5194         if (to_vmx(vcpu)->nmi_known_unmasked)
5195                 return false;
5196         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5197 }
5198
5199 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5200 {
5201         struct vcpu_vmx *vmx = to_vmx(vcpu);
5202
5203         if (!cpu_has_virtual_nmis()) {
5204                 if (vmx->soft_vnmi_blocked != masked) {
5205                         vmx->soft_vnmi_blocked = masked;
5206                         vmx->vnmi_blocked_time = 0;
5207                 }
5208         } else {
5209                 vmx->nmi_known_unmasked = !masked;
5210                 if (masked)
5211                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5212                                       GUEST_INTR_STATE_NMI);
5213                 else
5214                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5215                                         GUEST_INTR_STATE_NMI);
5216         }
5217 }
5218
5219 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5220 {
5221         if (to_vmx(vcpu)->nested.nested_run_pending)
5222                 return 0;
5223
5224         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
5225                 return 0;
5226
5227         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5228                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5229                    | GUEST_INTR_STATE_NMI));
5230 }
5231
5232 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5233 {
5234         return (!to_vmx(vcpu)->nested.nested_run_pending &&
5235                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5236                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5237                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5238 }
5239
5240 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5241 {
5242         int ret;
5243
5244         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5245                                     PAGE_SIZE * 3);
5246         if (ret)
5247                 return ret;
5248         kvm->arch.tss_addr = addr;
5249         return init_rmode_tss(kvm);
5250 }
5251
5252 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5253 {
5254         switch (vec) {
5255         case BP_VECTOR:
5256                 /*
5257                  * Update instruction length as we may reinject the exception
5258                  * from user space while in guest debugging mode.
5259                  */
5260                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5261                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5262                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5263                         return false;
5264                 /* fall through */
5265         case DB_VECTOR:
5266                 if (vcpu->guest_debug &
5267                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5268                         return false;
5269                 /* fall through */
5270         case DE_VECTOR:
5271         case OF_VECTOR:
5272         case BR_VECTOR:
5273         case UD_VECTOR:
5274         case DF_VECTOR:
5275         case SS_VECTOR:
5276         case GP_VECTOR:
5277         case MF_VECTOR:
5278                 return true;
5279         break;
5280         }
5281         return false;
5282 }
5283
5284 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5285                                   int vec, u32 err_code)
5286 {
5287         /*
5288          * Instruction with address size override prefix opcode 0x67
5289          * Cause the #SS fault with 0 error code in VM86 mode.
5290          */
5291         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5292                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5293                         if (vcpu->arch.halt_request) {
5294                                 vcpu->arch.halt_request = 0;
5295                                 return kvm_vcpu_halt(vcpu);
5296                         }
5297                         return 1;
5298                 }
5299                 return 0;
5300         }
5301
5302         /*
5303          * Forward all other exceptions that are valid in real mode.
5304          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5305          *        the required debugging infrastructure rework.
5306          */
5307         kvm_queue_exception(vcpu, vec);
5308         return 1;
5309 }
5310
5311 /*
5312  * Trigger machine check on the host. We assume all the MSRs are already set up
5313  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5314  * We pass a fake environment to the machine check handler because we want
5315  * the guest to be always treated like user space, no matter what context
5316  * it used internally.
5317  */
5318 static void kvm_machine_check(void)
5319 {
5320 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5321         struct pt_regs regs = {
5322                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5323                 .flags = X86_EFLAGS_IF,
5324         };
5325
5326         do_machine_check(&regs, 0);
5327 #endif
5328 }
5329
5330 static int handle_machine_check(struct kvm_vcpu *vcpu)
5331 {
5332         /* already handled by vcpu_run */
5333         return 1;
5334 }
5335
5336 static int handle_exception(struct kvm_vcpu *vcpu)
5337 {
5338         struct vcpu_vmx *vmx = to_vmx(vcpu);
5339         struct kvm_run *kvm_run = vcpu->run;
5340         u32 intr_info, ex_no, error_code;
5341         unsigned long cr2, rip, dr6;
5342         u32 vect_info;
5343         enum emulation_result er;
5344
5345         vect_info = vmx->idt_vectoring_info;
5346         intr_info = vmx->exit_intr_info;
5347
5348         if (is_machine_check(intr_info))
5349                 return handle_machine_check(vcpu);
5350
5351         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
5352                 return 1;  /* already handled by vmx_vcpu_run() */
5353
5354         if (is_no_device(intr_info)) {
5355                 vmx_fpu_activate(vcpu);
5356                 return 1;
5357         }
5358
5359         if (is_invalid_opcode(intr_info)) {
5360                 if (is_guest_mode(vcpu)) {
5361                         kvm_queue_exception(vcpu, UD_VECTOR);
5362                         return 1;
5363                 }
5364                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5365                 if (er != EMULATE_DONE)
5366                         kvm_queue_exception(vcpu, UD_VECTOR);
5367                 return 1;
5368         }
5369
5370         error_code = 0;
5371         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5372                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5373
5374         /*
5375          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5376          * MMIO, it is better to report an internal error.
5377          * See the comments in vmx_handle_exit.
5378          */
5379         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5380             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5381                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5382                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5383                 vcpu->run->internal.ndata = 3;
5384                 vcpu->run->internal.data[0] = vect_info;
5385                 vcpu->run->internal.data[1] = intr_info;
5386                 vcpu->run->internal.data[2] = error_code;
5387                 return 0;
5388         }
5389
5390         if (is_page_fault(intr_info)) {
5391                 /* EPT won't cause page fault directly */
5392                 BUG_ON(enable_ept);
5393                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5394                 trace_kvm_page_fault(cr2, error_code);
5395
5396                 if (kvm_event_needs_reinjection(vcpu))
5397                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
5398                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5399         }
5400
5401         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5402
5403         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5404                 return handle_rmode_exception(vcpu, ex_no, error_code);
5405
5406         switch (ex_no) {
5407         case AC_VECTOR:
5408                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5409                 return 1;
5410         case DB_VECTOR:
5411                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5412                 if (!(vcpu->guest_debug &
5413                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5414                         vcpu->arch.dr6 &= ~15;
5415                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5416                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5417                                 skip_emulated_instruction(vcpu);
5418
5419                         kvm_queue_exception(vcpu, DB_VECTOR);
5420                         return 1;
5421                 }
5422                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5423                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5424                 /* fall through */
5425         case BP_VECTOR:
5426                 /*
5427                  * Update instruction length as we may reinject #BP from
5428                  * user space while in guest debugging mode. Reading it for
5429                  * #DB as well causes no harm, it is not used in that case.
5430                  */
5431                 vmx->vcpu.arch.event_exit_inst_len =
5432                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5433                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5434                 rip = kvm_rip_read(vcpu);
5435                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5436                 kvm_run->debug.arch.exception = ex_no;
5437                 break;
5438         default:
5439                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5440                 kvm_run->ex.exception = ex_no;
5441                 kvm_run->ex.error_code = error_code;
5442                 break;
5443         }
5444         return 0;
5445 }
5446
5447 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5448 {
5449         ++vcpu->stat.irq_exits;
5450         return 1;
5451 }
5452
5453 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5454 {
5455         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5456         return 0;
5457 }
5458
5459 static int handle_io(struct kvm_vcpu *vcpu)
5460 {
5461         unsigned long exit_qualification;
5462         int size, in, string;
5463         unsigned port;
5464
5465         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5466         string = (exit_qualification & 16) != 0;
5467         in = (exit_qualification & 8) != 0;
5468
5469         ++vcpu->stat.io_exits;
5470
5471         if (string || in)
5472                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5473
5474         port = exit_qualification >> 16;
5475         size = (exit_qualification & 7) + 1;
5476         skip_emulated_instruction(vcpu);
5477
5478         return kvm_fast_pio_out(vcpu, size, port);
5479 }
5480
5481 static void
5482 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5483 {
5484         /*
5485          * Patch in the VMCALL instruction:
5486          */
5487         hypercall[0] = 0x0f;
5488         hypercall[1] = 0x01;
5489         hypercall[2] = 0xc1;
5490 }
5491
5492 static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5493 {
5494         unsigned long always_on = VMXON_CR0_ALWAYSON;
5495         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5496
5497         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
5498                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5499             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5500                 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5501         return (val & always_on) == always_on;
5502 }
5503
5504 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5505 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5506 {
5507         if (is_guest_mode(vcpu)) {
5508                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5509                 unsigned long orig_val = val;
5510
5511                 /*
5512                  * We get here when L2 changed cr0 in a way that did not change
5513                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5514                  * but did change L0 shadowed bits. So we first calculate the
5515                  * effective cr0 value that L1 would like to write into the
5516                  * hardware. It consists of the L2-owned bits from the new
5517                  * value combined with the L1-owned bits from L1's guest_cr0.
5518                  */
5519                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5520                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5521
5522                 if (!nested_cr0_valid(vcpu, val))
5523                         return 1;
5524
5525                 if (kvm_set_cr0(vcpu, val))
5526                         return 1;
5527                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5528                 return 0;
5529         } else {
5530                 if (to_vmx(vcpu)->nested.vmxon &&
5531                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5532                         return 1;
5533                 return kvm_set_cr0(vcpu, val);
5534         }
5535 }
5536
5537 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5538 {
5539         if (is_guest_mode(vcpu)) {
5540                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5541                 unsigned long orig_val = val;
5542
5543                 /* analogously to handle_set_cr0 */
5544                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5545                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5546                 if (kvm_set_cr4(vcpu, val))
5547                         return 1;
5548                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5549                 return 0;
5550         } else
5551                 return kvm_set_cr4(vcpu, val);
5552 }
5553
5554 /* called to set cr0 as appropriate for clts instruction exit. */
5555 static void handle_clts(struct kvm_vcpu *vcpu)
5556 {
5557         if (is_guest_mode(vcpu)) {
5558                 /*
5559                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5560                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5561                  * just pretend it's off (also in arch.cr0 for fpu_activate).
5562                  */
5563                 vmcs_writel(CR0_READ_SHADOW,
5564                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5565                 vcpu->arch.cr0 &= ~X86_CR0_TS;
5566         } else
5567                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5568 }
5569
5570 static int handle_cr(struct kvm_vcpu *vcpu)
5571 {
5572         unsigned long exit_qualification, val;
5573         int cr;
5574         int reg;
5575         int err;
5576
5577         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5578         cr = exit_qualification & 15;
5579         reg = (exit_qualification >> 8) & 15;
5580         switch ((exit_qualification >> 4) & 3) {
5581         case 0: /* mov to cr */
5582                 val = kvm_register_readl(vcpu, reg);
5583                 trace_kvm_cr_write(cr, val);
5584                 switch (cr) {
5585                 case 0:
5586                         err = handle_set_cr0(vcpu, val);
5587                         kvm_complete_insn_gp(vcpu, err);
5588                         return 1;
5589                 case 3:
5590                         err = kvm_set_cr3(vcpu, val);
5591                         kvm_complete_insn_gp(vcpu, err);
5592                         return 1;
5593                 case 4:
5594                         err = handle_set_cr4(vcpu, val);
5595                         kvm_complete_insn_gp(vcpu, err);
5596                         return 1;
5597                 case 8: {
5598                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5599                                 u8 cr8 = (u8)val;
5600                                 err = kvm_set_cr8(vcpu, cr8);
5601                                 kvm_complete_insn_gp(vcpu, err);
5602                                 if (lapic_in_kernel(vcpu))
5603                                         return 1;
5604                                 if (cr8_prev <= cr8)
5605                                         return 1;
5606                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5607                                 return 0;
5608                         }
5609                 }
5610                 break;
5611         case 2: /* clts */
5612                 handle_clts(vcpu);
5613                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5614                 skip_emulated_instruction(vcpu);
5615                 vmx_fpu_activate(vcpu);
5616                 return 1;
5617         case 1: /*mov from cr*/
5618                 switch (cr) {
5619                 case 3:
5620                         val = kvm_read_cr3(vcpu);
5621                         kvm_register_write(vcpu, reg, val);
5622                         trace_kvm_cr_read(cr, val);
5623                         skip_emulated_instruction(vcpu);
5624                         return 1;
5625                 case 8:
5626                         val = kvm_get_cr8(vcpu);
5627                         kvm_register_write(vcpu, reg, val);
5628                         trace_kvm_cr_read(cr, val);
5629                         skip_emulated_instruction(vcpu);
5630                         return 1;
5631                 }
5632                 break;
5633         case 3: /* lmsw */
5634                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5635                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5636                 kvm_lmsw(vcpu, val);
5637
5638                 skip_emulated_instruction(vcpu);
5639                 return 1;
5640         default:
5641                 break;
5642         }
5643         vcpu->run->exit_reason = 0;
5644         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5645                (int)(exit_qualification >> 4) & 3, cr);
5646         return 0;
5647 }
5648
5649 static int handle_dr(struct kvm_vcpu *vcpu)
5650 {
5651         unsigned long exit_qualification;
5652         int dr, dr7, reg;
5653
5654         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5655         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5656
5657         /* First, if DR does not exist, trigger UD */
5658         if (!kvm_require_dr(vcpu, dr))
5659                 return 1;
5660
5661         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5662         if (!kvm_require_cpl(vcpu, 0))
5663                 return 1;
5664         dr7 = vmcs_readl(GUEST_DR7);
5665         if (dr7 & DR7_GD) {
5666                 /*
5667                  * As the vm-exit takes precedence over the debug trap, we
5668                  * need to emulate the latter, either for the host or the
5669                  * guest debugging itself.
5670                  */
5671                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5672                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5673                         vcpu->run->debug.arch.dr7 = dr7;
5674                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5675                         vcpu->run->debug.arch.exception = DB_VECTOR;
5676                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5677                         return 0;
5678                 } else {
5679                         vcpu->arch.dr6 &= ~15;
5680                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5681                         kvm_queue_exception(vcpu, DB_VECTOR);
5682                         return 1;
5683                 }
5684         }
5685
5686         if (vcpu->guest_debug == 0) {
5687                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
5688                                 CPU_BASED_MOV_DR_EXITING);
5689
5690                 /*
5691                  * No more DR vmexits; force a reload of the debug registers
5692                  * and reenter on this instruction.  The next vmexit will
5693                  * retrieve the full state of the debug registers.
5694                  */
5695                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5696                 return 1;
5697         }
5698
5699         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5700         if (exit_qualification & TYPE_MOV_FROM_DR) {
5701                 unsigned long val;
5702
5703                 if (kvm_get_dr(vcpu, dr, &val))
5704                         return 1;
5705                 kvm_register_write(vcpu, reg, val);
5706         } else
5707                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5708                         return 1;
5709
5710         skip_emulated_instruction(vcpu);
5711         return 1;
5712 }
5713
5714 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5715 {
5716         return vcpu->arch.dr6;
5717 }
5718
5719 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5720 {
5721 }
5722
5723 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5724 {
5725         get_debugreg(vcpu->arch.db[0], 0);
5726         get_debugreg(vcpu->arch.db[1], 1);
5727         get_debugreg(vcpu->arch.db[2], 2);
5728         get_debugreg(vcpu->arch.db[3], 3);
5729         get_debugreg(vcpu->arch.dr6, 6);
5730         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5731
5732         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5733         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
5734 }
5735
5736 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5737 {
5738         vmcs_writel(GUEST_DR7, val);
5739 }
5740
5741 static int handle_cpuid(struct kvm_vcpu *vcpu)
5742 {
5743         kvm_emulate_cpuid(vcpu);
5744         return 1;
5745 }
5746
5747 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5748 {
5749         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5750         struct msr_data msr_info;
5751
5752         msr_info.index = ecx;
5753         msr_info.host_initiated = false;
5754         if (vmx_get_msr(vcpu, &msr_info)) {
5755                 trace_kvm_msr_read_ex(ecx);
5756                 kvm_inject_gp(vcpu, 0);
5757                 return 1;
5758         }
5759
5760         trace_kvm_msr_read(ecx, msr_info.data);
5761
5762         /* FIXME: handling of bits 32:63 of rax, rdx */
5763         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
5764         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
5765         skip_emulated_instruction(vcpu);
5766         return 1;
5767 }
5768
5769 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5770 {
5771         struct msr_data msr;
5772         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5773         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5774                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5775
5776         msr.data = data;
5777         msr.index = ecx;
5778         msr.host_initiated = false;
5779         if (kvm_set_msr(vcpu, &msr) != 0) {
5780                 trace_kvm_msr_write_ex(ecx, data);
5781                 kvm_inject_gp(vcpu, 0);
5782                 return 1;
5783         }
5784
5785         trace_kvm_msr_write(ecx, data);
5786         skip_emulated_instruction(vcpu);
5787         return 1;
5788 }
5789
5790 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5791 {
5792         kvm_make_request(KVM_REQ_EVENT, vcpu);
5793         return 1;
5794 }
5795
5796 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5797 {
5798         u32 cpu_based_vm_exec_control;
5799
5800         /* clear pending irq */
5801         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5802         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5803         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5804
5805         kvm_make_request(KVM_REQ_EVENT, vcpu);
5806
5807         ++vcpu->stat.irq_window_exits;
5808         return 1;
5809 }
5810
5811 static int handle_halt(struct kvm_vcpu *vcpu)
5812 {
5813         return kvm_emulate_halt(vcpu);
5814 }
5815
5816 static int handle_vmcall(struct kvm_vcpu *vcpu)
5817 {
5818         return kvm_emulate_hypercall(vcpu);
5819 }
5820
5821 static int handle_invd(struct kvm_vcpu *vcpu)
5822 {
5823         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5824 }
5825
5826 static int handle_invlpg(struct kvm_vcpu *vcpu)
5827 {
5828         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5829
5830         kvm_mmu_invlpg(vcpu, exit_qualification);
5831         skip_emulated_instruction(vcpu);
5832         return 1;
5833 }
5834
5835 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5836 {
5837         int err;
5838
5839         err = kvm_rdpmc(vcpu);
5840         kvm_complete_insn_gp(vcpu, err);
5841
5842         return 1;
5843 }
5844
5845 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5846 {
5847         kvm_emulate_wbinvd(vcpu);
5848         return 1;
5849 }
5850
5851 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5852 {
5853         u64 new_bv = kvm_read_edx_eax(vcpu);
5854         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5855
5856         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5857                 skip_emulated_instruction(vcpu);
5858         return 1;
5859 }
5860
5861 static int handle_xsaves(struct kvm_vcpu *vcpu)
5862 {
5863         skip_emulated_instruction(vcpu);
5864         WARN(1, "this should never happen\n");
5865         return 1;
5866 }
5867
5868 static int handle_xrstors(struct kvm_vcpu *vcpu)
5869 {
5870         skip_emulated_instruction(vcpu);
5871         WARN(1, "this should never happen\n");
5872         return 1;
5873 }
5874
5875 static int handle_apic_access(struct kvm_vcpu *vcpu)
5876 {
5877         if (likely(fasteoi)) {
5878                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5879                 int access_type, offset;
5880
5881                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5882                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5883                 /*
5884                  * Sane guest uses MOV to write EOI, with written value
5885                  * not cared. So make a short-circuit here by avoiding
5886                  * heavy instruction emulation.
5887                  */
5888                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5889                     (offset == APIC_EOI)) {
5890                         kvm_lapic_set_eoi(vcpu);
5891                         skip_emulated_instruction(vcpu);
5892                         return 1;
5893                 }
5894         }
5895         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5896 }
5897
5898 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5899 {
5900         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5901         int vector = exit_qualification & 0xff;
5902
5903         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5904         kvm_apic_set_eoi_accelerated(vcpu, vector);
5905         return 1;
5906 }
5907
5908 static int handle_apic_write(struct kvm_vcpu *vcpu)
5909 {
5910         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5911         u32 offset = exit_qualification & 0xfff;
5912
5913         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5914         kvm_apic_write_nodecode(vcpu, offset);
5915         return 1;
5916 }
5917
5918 static int handle_task_switch(struct kvm_vcpu *vcpu)
5919 {
5920         struct vcpu_vmx *vmx = to_vmx(vcpu);
5921         unsigned long exit_qualification;
5922         bool has_error_code = false;
5923         u32 error_code = 0;
5924         u16 tss_selector;
5925         int reason, type, idt_v, idt_index;
5926
5927         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5928         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5929         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5930
5931         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5932
5933         reason = (u32)exit_qualification >> 30;
5934         if (reason == TASK_SWITCH_GATE && idt_v) {
5935                 switch (type) {
5936                 case INTR_TYPE_NMI_INTR:
5937                         vcpu->arch.nmi_injected = false;
5938                         vmx_set_nmi_mask(vcpu, true);
5939                         break;
5940                 case INTR_TYPE_EXT_INTR:
5941                 case INTR_TYPE_SOFT_INTR:
5942                         kvm_clear_interrupt_queue(vcpu);
5943                         break;
5944                 case INTR_TYPE_HARD_EXCEPTION:
5945                         if (vmx->idt_vectoring_info &
5946                             VECTORING_INFO_DELIVER_CODE_MASK) {
5947                                 has_error_code = true;
5948                                 error_code =
5949                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5950                         }
5951                         /* fall through */
5952                 case INTR_TYPE_SOFT_EXCEPTION:
5953                         kvm_clear_exception_queue(vcpu);
5954                         break;
5955                 default:
5956                         break;
5957                 }
5958         }
5959         tss_selector = exit_qualification;
5960
5961         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5962                        type != INTR_TYPE_EXT_INTR &&
5963                        type != INTR_TYPE_NMI_INTR))
5964                 skip_emulated_instruction(vcpu);
5965
5966         if (kvm_task_switch(vcpu, tss_selector,
5967                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5968                             has_error_code, error_code) == EMULATE_FAIL) {
5969                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5970                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5971                 vcpu->run->internal.ndata = 0;
5972                 return 0;
5973         }
5974
5975         /*
5976          * TODO: What about debug traps on tss switch?
5977          *       Are we supposed to inject them and update dr6?
5978          */
5979
5980         return 1;
5981 }
5982
5983 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5984 {
5985         unsigned long exit_qualification;
5986         gpa_t gpa;
5987         u32 error_code;
5988         int gla_validity;
5989
5990         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5991
5992         gla_validity = (exit_qualification >> 7) & 0x3;
5993         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5994                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5995                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5996                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5997                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5998                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5999                         (long unsigned int)exit_qualification);
6000                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6001                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
6002                 return 0;
6003         }
6004
6005         /*
6006          * EPT violation happened while executing iret from NMI,
6007          * "blocked by NMI" bit has to be set before next VM entry.
6008          * There are errata that may cause this bit to not be set:
6009          * AAK134, BY25.
6010          */
6011         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
6012                         cpu_has_virtual_nmis() &&
6013                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
6014                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
6015
6016         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6017         trace_kvm_page_fault(gpa, exit_qualification);
6018
6019         /* It is a write fault? */
6020         error_code = exit_qualification & PFERR_WRITE_MASK;
6021         /* It is a fetch fault? */
6022         error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
6023         /* ept page table is present? */
6024         error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
6025
6026         vcpu->arch.exit_qualification = exit_qualification;
6027
6028         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
6029 }
6030
6031 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
6032 {
6033         int ret;
6034         gpa_t gpa;
6035
6036         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6037         if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
6038                 skip_emulated_instruction(vcpu);
6039                 trace_kvm_fast_mmio(gpa);
6040                 return 1;
6041         }
6042
6043         ret = handle_mmio_page_fault(vcpu, gpa, true);
6044         if (likely(ret == RET_MMIO_PF_EMULATE))
6045                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
6046                                               EMULATE_DONE;
6047
6048         if (unlikely(ret == RET_MMIO_PF_INVALID))
6049                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
6050
6051         if (unlikely(ret == RET_MMIO_PF_RETRY))
6052                 return 1;
6053
6054         /* It is the real ept misconfig */
6055         WARN_ON(1);
6056
6057         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6058         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
6059
6060         return 0;
6061 }
6062
6063 static int handle_nmi_window(struct kvm_vcpu *vcpu)
6064 {
6065         u32 cpu_based_vm_exec_control;
6066
6067         /* clear pending NMI */
6068         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6069         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6070         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
6071         ++vcpu->stat.nmi_window_exits;
6072         kvm_make_request(KVM_REQ_EVENT, vcpu);
6073
6074         return 1;
6075 }
6076
6077 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6078 {
6079         struct vcpu_vmx *vmx = to_vmx(vcpu);
6080         enum emulation_result err = EMULATE_DONE;
6081         int ret = 1;
6082         u32 cpu_exec_ctrl;
6083         bool intr_window_requested;
6084         unsigned count = 130;
6085
6086         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6087         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6088
6089         while (vmx->emulation_required && count-- != 0) {
6090                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6091                         return handle_interrupt_window(&vmx->vcpu);
6092
6093                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
6094                         return 1;
6095
6096                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
6097
6098                 if (err == EMULATE_USER_EXIT) {
6099                         ++vcpu->stat.mmio_exits;
6100                         ret = 0;
6101                         goto out;
6102                 }
6103
6104                 if (err != EMULATE_DONE) {
6105                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6106                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6107                         vcpu->run->internal.ndata = 0;
6108                         return 0;
6109                 }
6110
6111                 if (vcpu->arch.halt_request) {
6112                         vcpu->arch.halt_request = 0;
6113                         ret = kvm_vcpu_halt(vcpu);
6114                         goto out;
6115                 }
6116
6117                 if (signal_pending(current))
6118                         goto out;
6119                 if (need_resched())
6120                         schedule();
6121         }
6122
6123 out:
6124         return ret;
6125 }
6126
6127 static int __grow_ple_window(int val)
6128 {
6129         if (ple_window_grow < 1)
6130                 return ple_window;
6131
6132         val = min(val, ple_window_actual_max);
6133
6134         if (ple_window_grow < ple_window)
6135                 val *= ple_window_grow;
6136         else
6137                 val += ple_window_grow;
6138
6139         return val;
6140 }
6141
6142 static int __shrink_ple_window(int val, int modifier, int minimum)
6143 {
6144         if (modifier < 1)
6145                 return ple_window;
6146
6147         if (modifier < ple_window)
6148                 val /= modifier;
6149         else
6150                 val -= modifier;
6151
6152         return max(val, minimum);
6153 }
6154
6155 static void grow_ple_window(struct kvm_vcpu *vcpu)
6156 {
6157         struct vcpu_vmx *vmx = to_vmx(vcpu);
6158         int old = vmx->ple_window;
6159
6160         vmx->ple_window = __grow_ple_window(old);
6161
6162         if (vmx->ple_window != old)
6163                 vmx->ple_window_dirty = true;
6164
6165         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6166 }
6167
6168 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6169 {
6170         struct vcpu_vmx *vmx = to_vmx(vcpu);
6171         int old = vmx->ple_window;
6172
6173         vmx->ple_window = __shrink_ple_window(old,
6174                                               ple_window_shrink, ple_window);
6175
6176         if (vmx->ple_window != old)
6177                 vmx->ple_window_dirty = true;
6178
6179         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6180 }
6181
6182 /*
6183  * ple_window_actual_max is computed to be one grow_ple_window() below
6184  * ple_window_max. (See __grow_ple_window for the reason.)
6185  * This prevents overflows, because ple_window_max is int.
6186  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6187  * this process.
6188  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6189  */
6190 static void update_ple_window_actual_max(void)
6191 {
6192         ple_window_actual_max =
6193                         __shrink_ple_window(max(ple_window_max, ple_window),
6194                                             ple_window_grow, INT_MIN);
6195 }
6196
6197 /*
6198  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6199  */
6200 static void wakeup_handler(void)
6201 {
6202         struct kvm_vcpu *vcpu;
6203         int cpu = smp_processor_id();
6204
6205         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6206         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6207                         blocked_vcpu_list) {
6208                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6209
6210                 if (pi_test_on(pi_desc) == 1)
6211                         kvm_vcpu_kick(vcpu);
6212         }
6213         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6214 }
6215
6216 static __init int hardware_setup(void)
6217 {
6218         int r = -ENOMEM, i, msr;
6219
6220         rdmsrl_safe(MSR_EFER, &host_efer);
6221
6222         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6223                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6224
6225         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6226         if (!vmx_io_bitmap_a)
6227                 return r;
6228
6229         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6230         if (!vmx_io_bitmap_b)
6231                 goto out;
6232
6233         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6234         if (!vmx_msr_bitmap_legacy)
6235                 goto out1;
6236
6237         vmx_msr_bitmap_legacy_x2apic =
6238                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6239         if (!vmx_msr_bitmap_legacy_x2apic)
6240                 goto out2;
6241
6242         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6243         if (!vmx_msr_bitmap_longmode)
6244                 goto out3;
6245
6246         vmx_msr_bitmap_longmode_x2apic =
6247                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6248         if (!vmx_msr_bitmap_longmode_x2apic)
6249                 goto out4;
6250
6251         if (nested) {
6252                 vmx_msr_bitmap_nested =
6253                         (unsigned long *)__get_free_page(GFP_KERNEL);
6254                 if (!vmx_msr_bitmap_nested)
6255                         goto out5;
6256         }
6257
6258         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6259         if (!vmx_vmread_bitmap)
6260                 goto out6;
6261
6262         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6263         if (!vmx_vmwrite_bitmap)
6264                 goto out7;
6265
6266         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6267         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6268
6269         /*
6270          * Allow direct access to the PC debug port (it is often used for I/O
6271          * delays, but the vmexits simply slow things down).
6272          */
6273         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6274         clear_bit(0x80, vmx_io_bitmap_a);
6275
6276         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6277
6278         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6279         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6280         if (nested)
6281                 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
6282
6283         if (setup_vmcs_config(&vmcs_config) < 0) {
6284                 r = -EIO;
6285                 goto out8;
6286         }
6287
6288         if (boot_cpu_has(X86_FEATURE_NX))
6289                 kvm_enable_efer_bits(EFER_NX);
6290
6291         if (!cpu_has_vmx_vpid())
6292                 enable_vpid = 0;
6293         if (!cpu_has_vmx_shadow_vmcs())
6294                 enable_shadow_vmcs = 0;
6295         if (enable_shadow_vmcs)
6296                 init_vmcs_shadow_fields();
6297
6298         if (!cpu_has_vmx_ept() ||
6299             !cpu_has_vmx_ept_4levels()) {
6300                 enable_ept = 0;
6301                 enable_unrestricted_guest = 0;
6302                 enable_ept_ad_bits = 0;
6303         }
6304
6305         if (!cpu_has_vmx_ept_ad_bits())
6306                 enable_ept_ad_bits = 0;
6307
6308         if (!cpu_has_vmx_unrestricted_guest())
6309                 enable_unrestricted_guest = 0;
6310
6311         if (!cpu_has_vmx_flexpriority())
6312                 flexpriority_enabled = 0;
6313
6314         /*
6315          * set_apic_access_page_addr() is used to reload apic access
6316          * page upon invalidation.  No need to do anything if not
6317          * using the APIC_ACCESS_ADDR VMCS field.
6318          */
6319         if (!flexpriority_enabled)
6320                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6321
6322         if (!cpu_has_vmx_tpr_shadow())
6323                 kvm_x86_ops->update_cr8_intercept = NULL;
6324
6325         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6326                 kvm_disable_largepages();
6327
6328         if (!cpu_has_vmx_ple())
6329                 ple_gap = 0;
6330
6331         if (!cpu_has_vmx_apicv())
6332                 enable_apicv = 0;
6333
6334         if (cpu_has_vmx_tsc_scaling()) {
6335                 kvm_has_tsc_control = true;
6336                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6337                 kvm_tsc_scaling_ratio_frac_bits = 48;
6338         }
6339
6340         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6341         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6342         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6343         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6344         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6345         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6346         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6347
6348         memcpy(vmx_msr_bitmap_legacy_x2apic,
6349                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6350         memcpy(vmx_msr_bitmap_longmode_x2apic,
6351                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6352
6353         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6354
6355         for (msr = 0x800; msr <= 0x8ff; msr++)
6356                 vmx_disable_intercept_msr_read_x2apic(msr);
6357
6358         /* According SDM, in x2apic mode, the whole id reg is used.  But in
6359          * KVM, it only use the highest eight bits. Need to intercept it */
6360         vmx_enable_intercept_msr_read_x2apic(0x802);
6361         /* TMCCT */
6362         vmx_enable_intercept_msr_read_x2apic(0x839);
6363         /* TPR */
6364         vmx_disable_intercept_msr_write_x2apic(0x808);
6365         /* EOI */
6366         vmx_disable_intercept_msr_write_x2apic(0x80b);
6367         /* SELF-IPI */
6368         vmx_disable_intercept_msr_write_x2apic(0x83f);
6369
6370         if (enable_ept) {
6371                 kvm_mmu_set_mask_ptes(0ull,
6372                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6373                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6374                         0ull, VMX_EPT_EXECUTABLE_MASK);
6375                 ept_set_mmio_spte_mask();
6376                 kvm_enable_tdp();
6377         } else
6378                 kvm_disable_tdp();
6379
6380         update_ple_window_actual_max();
6381
6382         /*
6383          * Only enable PML when hardware supports PML feature, and both EPT
6384          * and EPT A/D bit features are enabled -- PML depends on them to work.
6385          */
6386         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6387                 enable_pml = 0;
6388
6389         if (!enable_pml) {
6390                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6391                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6392                 kvm_x86_ops->flush_log_dirty = NULL;
6393                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6394         }
6395
6396         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6397
6398         return alloc_kvm_area();
6399
6400 out8:
6401         free_page((unsigned long)vmx_vmwrite_bitmap);
6402 out7:
6403         free_page((unsigned long)vmx_vmread_bitmap);
6404 out6:
6405         if (nested)
6406                 free_page((unsigned long)vmx_msr_bitmap_nested);
6407 out5:
6408         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6409 out4:
6410         free_page((unsigned long)vmx_msr_bitmap_longmode);
6411 out3:
6412         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6413 out2:
6414         free_page((unsigned long)vmx_msr_bitmap_legacy);
6415 out1:
6416         free_page((unsigned long)vmx_io_bitmap_b);
6417 out:
6418         free_page((unsigned long)vmx_io_bitmap_a);
6419
6420     return r;
6421 }
6422
6423 static __exit void hardware_unsetup(void)
6424 {
6425         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6426         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6427         free_page((unsigned long)vmx_msr_bitmap_legacy);
6428         free_page((unsigned long)vmx_msr_bitmap_longmode);
6429         free_page((unsigned long)vmx_io_bitmap_b);
6430         free_page((unsigned long)vmx_io_bitmap_a);
6431         free_page((unsigned long)vmx_vmwrite_bitmap);
6432         free_page((unsigned long)vmx_vmread_bitmap);
6433         if (nested)
6434                 free_page((unsigned long)vmx_msr_bitmap_nested);
6435
6436         free_kvm_area();
6437 }
6438
6439 /*
6440  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6441  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6442  */
6443 static int handle_pause(struct kvm_vcpu *vcpu)
6444 {
6445         if (ple_gap)
6446                 grow_ple_window(vcpu);
6447
6448         skip_emulated_instruction(vcpu);
6449         kvm_vcpu_on_spin(vcpu);
6450
6451         return 1;
6452 }
6453
6454 static int handle_nop(struct kvm_vcpu *vcpu)
6455 {
6456         skip_emulated_instruction(vcpu);
6457         return 1;
6458 }
6459
6460 static int handle_mwait(struct kvm_vcpu *vcpu)
6461 {
6462         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6463         return handle_nop(vcpu);
6464 }
6465
6466 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6467 {
6468         return 1;
6469 }
6470
6471 static int handle_monitor(struct kvm_vcpu *vcpu)
6472 {
6473         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6474         return handle_nop(vcpu);
6475 }
6476
6477 /*
6478  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6479  * We could reuse a single VMCS for all the L2 guests, but we also want the
6480  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6481  * allows keeping them loaded on the processor, and in the future will allow
6482  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6483  * every entry if they never change.
6484  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6485  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6486  *
6487  * The following functions allocate and free a vmcs02 in this pool.
6488  */
6489
6490 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6491 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6492 {
6493         struct vmcs02_list *item;
6494         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6495                 if (item->vmptr == vmx->nested.current_vmptr) {
6496                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6497                         return &item->vmcs02;
6498                 }
6499
6500         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6501                 /* Recycle the least recently used VMCS. */
6502                 item = list_last_entry(&vmx->nested.vmcs02_pool,
6503                                        struct vmcs02_list, list);
6504                 item->vmptr = vmx->nested.current_vmptr;
6505                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6506                 return &item->vmcs02;
6507         }
6508
6509         /* Create a new VMCS */
6510         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6511         if (!item)
6512                 return NULL;
6513         item->vmcs02.vmcs = alloc_vmcs();
6514         if (!item->vmcs02.vmcs) {
6515                 kfree(item);
6516                 return NULL;
6517         }
6518         loaded_vmcs_init(&item->vmcs02);
6519         item->vmptr = vmx->nested.current_vmptr;
6520         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6521         vmx->nested.vmcs02_num++;
6522         return &item->vmcs02;
6523 }
6524
6525 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6526 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6527 {
6528         struct vmcs02_list *item;
6529         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6530                 if (item->vmptr == vmptr) {
6531                         free_loaded_vmcs(&item->vmcs02);
6532                         list_del(&item->list);
6533                         kfree(item);
6534                         vmx->nested.vmcs02_num--;
6535                         return;
6536                 }
6537 }
6538
6539 /*
6540  * Free all VMCSs saved for this vcpu, except the one pointed by
6541  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6542  * must be &vmx->vmcs01.
6543  */
6544 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6545 {
6546         struct vmcs02_list *item, *n;
6547
6548         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6549         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6550                 /*
6551                  * Something will leak if the above WARN triggers.  Better than
6552                  * a use-after-free.
6553                  */
6554                 if (vmx->loaded_vmcs == &item->vmcs02)
6555                         continue;
6556
6557                 free_loaded_vmcs(&item->vmcs02);
6558                 list_del(&item->list);
6559                 kfree(item);
6560                 vmx->nested.vmcs02_num--;
6561         }
6562 }
6563
6564 /*
6565  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6566  * set the success or error code of an emulated VMX instruction, as specified
6567  * by Vol 2B, VMX Instruction Reference, "Conventions".
6568  */
6569 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6570 {
6571         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6572                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6573                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6574 }
6575
6576 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6577 {
6578         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6579                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6580                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6581                         | X86_EFLAGS_CF);
6582 }
6583
6584 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6585                                         u32 vm_instruction_error)
6586 {
6587         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6588                 /*
6589                  * failValid writes the error number to the current VMCS, which
6590                  * can't be done there isn't a current VMCS.
6591                  */
6592                 nested_vmx_failInvalid(vcpu);
6593                 return;
6594         }
6595         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6596                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6597                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6598                         | X86_EFLAGS_ZF);
6599         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6600         /*
6601          * We don't need to force a shadow sync because
6602          * VM_INSTRUCTION_ERROR is not shadowed
6603          */
6604 }
6605
6606 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6607 {
6608         /* TODO: not to reset guest simply here. */
6609         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6610         pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6611 }
6612
6613 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6614 {
6615         struct vcpu_vmx *vmx =
6616                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6617
6618         vmx->nested.preemption_timer_expired = true;
6619         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6620         kvm_vcpu_kick(&vmx->vcpu);
6621
6622         return HRTIMER_NORESTART;
6623 }
6624
6625 /*
6626  * Decode the memory-address operand of a vmx instruction, as recorded on an
6627  * exit caused by such an instruction (run by a guest hypervisor).
6628  * On success, returns 0. When the operand is invalid, returns 1 and throws
6629  * #UD or #GP.
6630  */
6631 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6632                                  unsigned long exit_qualification,
6633                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
6634 {
6635         gva_t off;
6636         bool exn;
6637         struct kvm_segment s;
6638
6639         /*
6640          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6641          * Execution", on an exit, vmx_instruction_info holds most of the
6642          * addressing components of the operand. Only the displacement part
6643          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6644          * For how an actual address is calculated from all these components,
6645          * refer to Vol. 1, "Operand Addressing".
6646          */
6647         int  scaling = vmx_instruction_info & 3;
6648         int  addr_size = (vmx_instruction_info >> 7) & 7;
6649         bool is_reg = vmx_instruction_info & (1u << 10);
6650         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6651         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6652         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6653         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6654         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6655
6656         if (is_reg) {
6657                 kvm_queue_exception(vcpu, UD_VECTOR);
6658                 return 1;
6659         }
6660
6661         /* Addr = segment_base + offset */
6662         /* offset = base + [index * scale] + displacement */
6663         off = exit_qualification; /* holds the displacement */
6664         if (base_is_valid)
6665                 off += kvm_register_read(vcpu, base_reg);
6666         if (index_is_valid)
6667                 off += kvm_register_read(vcpu, index_reg)<<scaling;
6668         vmx_get_segment(vcpu, &s, seg_reg);
6669         *ret = s.base + off;
6670
6671         if (addr_size == 1) /* 32 bit */
6672                 *ret &= 0xffffffff;
6673
6674         /* Checks for #GP/#SS exceptions. */
6675         exn = false;
6676         if (is_long_mode(vcpu)) {
6677                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6678                  * non-canonical form. This is the only check on the memory
6679                  * destination for long mode!
6680                  */
6681                 exn = is_noncanonical_address(*ret);
6682         } else if (is_protmode(vcpu)) {
6683                 /* Protected mode: apply checks for segment validity in the
6684                  * following order:
6685                  * - segment type check (#GP(0) may be thrown)
6686                  * - usability check (#GP(0)/#SS(0))
6687                  * - limit check (#GP(0)/#SS(0))
6688                  */
6689                 if (wr)
6690                         /* #GP(0) if the destination operand is located in a
6691                          * read-only data segment or any code segment.
6692                          */
6693                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
6694                 else
6695                         /* #GP(0) if the source operand is located in an
6696                          * execute-only code segment
6697                          */
6698                         exn = ((s.type & 0xa) == 8);
6699                 if (exn) {
6700                         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6701                         return 1;
6702                 }
6703                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6704                  */
6705                 exn = (s.unusable != 0);
6706                 /* Protected mode: #GP(0)/#SS(0) if the memory
6707                  * operand is outside the segment limit.
6708                  */
6709                 exn = exn || (off + sizeof(u64) > s.limit);
6710         }
6711         if (exn) {
6712                 kvm_queue_exception_e(vcpu,
6713                                       seg_reg == VCPU_SREG_SS ?
6714                                                 SS_VECTOR : GP_VECTOR,
6715                                       0);
6716                 return 1;
6717         }
6718
6719         return 0;
6720 }
6721
6722 /*
6723  * This function performs the various checks including
6724  * - if it's 4KB aligned
6725  * - No bits beyond the physical address width are set
6726  * - Returns 0 on success or else 1
6727  * (Intel SDM Section 30.3)
6728  */
6729 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6730                                   gpa_t *vmpointer)
6731 {
6732         gva_t gva;
6733         gpa_t vmptr;
6734         struct x86_exception e;
6735         struct page *page;
6736         struct vcpu_vmx *vmx = to_vmx(vcpu);
6737         int maxphyaddr = cpuid_maxphyaddr(vcpu);
6738
6739         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6740                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6741                 return 1;
6742
6743         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6744                                 sizeof(vmptr), &e)) {
6745                 kvm_inject_page_fault(vcpu, &e);
6746                 return 1;
6747         }
6748
6749         switch (exit_reason) {
6750         case EXIT_REASON_VMON:
6751                 /*
6752                  * SDM 3: 24.11.5
6753                  * The first 4 bytes of VMXON region contain the supported
6754                  * VMCS revision identifier
6755                  *
6756                  * Note - IA32_VMX_BASIC[48] will never be 1
6757                  * for the nested case;
6758                  * which replaces physical address width with 32
6759                  *
6760                  */
6761                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6762                         nested_vmx_failInvalid(vcpu);
6763                         skip_emulated_instruction(vcpu);
6764                         return 1;
6765                 }
6766
6767                 page = nested_get_page(vcpu, vmptr);
6768                 if (page == NULL ||
6769                     *(u32 *)kmap(page) != VMCS12_REVISION) {
6770                         nested_vmx_failInvalid(vcpu);
6771                         kunmap(page);
6772                         skip_emulated_instruction(vcpu);
6773                         return 1;
6774                 }
6775                 kunmap(page);
6776                 vmx->nested.vmxon_ptr = vmptr;
6777                 break;
6778         case EXIT_REASON_VMCLEAR:
6779                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6780                         nested_vmx_failValid(vcpu,
6781                                              VMXERR_VMCLEAR_INVALID_ADDRESS);
6782                         skip_emulated_instruction(vcpu);
6783                         return 1;
6784                 }
6785
6786                 if (vmptr == vmx->nested.vmxon_ptr) {
6787                         nested_vmx_failValid(vcpu,
6788                                              VMXERR_VMCLEAR_VMXON_POINTER);
6789                         skip_emulated_instruction(vcpu);
6790                         return 1;
6791                 }
6792                 break;
6793         case EXIT_REASON_VMPTRLD:
6794                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6795                         nested_vmx_failValid(vcpu,
6796                                              VMXERR_VMPTRLD_INVALID_ADDRESS);
6797                         skip_emulated_instruction(vcpu);
6798                         return 1;
6799                 }
6800
6801                 if (vmptr == vmx->nested.vmxon_ptr) {
6802                         nested_vmx_failValid(vcpu,
6803                                              VMXERR_VMCLEAR_VMXON_POINTER);
6804                         skip_emulated_instruction(vcpu);
6805                         return 1;
6806                 }
6807                 break;
6808         default:
6809                 return 1; /* shouldn't happen */
6810         }
6811
6812         if (vmpointer)
6813                 *vmpointer = vmptr;
6814         return 0;
6815 }
6816
6817 /*
6818  * Emulate the VMXON instruction.
6819  * Currently, we just remember that VMX is active, and do not save or even
6820  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6821  * do not currently need to store anything in that guest-allocated memory
6822  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6823  * argument is different from the VMXON pointer (which the spec says they do).
6824  */
6825 static int handle_vmon(struct kvm_vcpu *vcpu)
6826 {
6827         struct kvm_segment cs;
6828         struct vcpu_vmx *vmx = to_vmx(vcpu);
6829         struct vmcs *shadow_vmcs;
6830         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6831                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6832
6833         /* The Intel VMX Instruction Reference lists a bunch of bits that
6834          * are prerequisite to running VMXON, most notably cr4.VMXE must be
6835          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6836          * Otherwise, we should fail with #UD. We test these now:
6837          */
6838         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6839             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6840             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6841                 kvm_queue_exception(vcpu, UD_VECTOR);
6842                 return 1;
6843         }
6844
6845         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6846         if (is_long_mode(vcpu) && !cs.l) {
6847                 kvm_queue_exception(vcpu, UD_VECTOR);
6848                 return 1;
6849         }
6850
6851         if (vmx_get_cpl(vcpu)) {
6852                 kvm_inject_gp(vcpu, 0);
6853                 return 1;
6854         }
6855
6856         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
6857                 return 1;
6858
6859         if (vmx->nested.vmxon) {
6860                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6861                 skip_emulated_instruction(vcpu);
6862                 return 1;
6863         }
6864
6865         if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6866                         != VMXON_NEEDED_FEATURES) {
6867                 kvm_inject_gp(vcpu, 0);
6868                 return 1;
6869         }
6870
6871         if (enable_shadow_vmcs) {
6872                 shadow_vmcs = alloc_vmcs();
6873                 if (!shadow_vmcs)
6874                         return -ENOMEM;
6875                 /* mark vmcs as shadow */
6876                 shadow_vmcs->revision_id |= (1u << 31);
6877                 /* init shadow vmcs */
6878                 vmcs_clear(shadow_vmcs);
6879                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6880         }
6881
6882         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6883         vmx->nested.vmcs02_num = 0;
6884
6885         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6886                      HRTIMER_MODE_REL);
6887         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6888
6889         vmx->nested.vmxon = true;
6890
6891         skip_emulated_instruction(vcpu);
6892         nested_vmx_succeed(vcpu);
6893         return 1;
6894 }
6895
6896 /*
6897  * Intel's VMX Instruction Reference specifies a common set of prerequisites
6898  * for running VMX instructions (except VMXON, whose prerequisites are
6899  * slightly different). It also specifies what exception to inject otherwise.
6900  */
6901 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6902 {
6903         struct kvm_segment cs;
6904         struct vcpu_vmx *vmx = to_vmx(vcpu);
6905
6906         if (!vmx->nested.vmxon) {
6907                 kvm_queue_exception(vcpu, UD_VECTOR);
6908                 return 0;
6909         }
6910
6911         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6912         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6913             (is_long_mode(vcpu) && !cs.l)) {
6914                 kvm_queue_exception(vcpu, UD_VECTOR);
6915                 return 0;
6916         }
6917
6918         if (vmx_get_cpl(vcpu)) {
6919                 kvm_inject_gp(vcpu, 0);
6920                 return 0;
6921         }
6922
6923         return 1;
6924 }
6925
6926 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6927 {
6928         if (vmx->nested.current_vmptr == -1ull)
6929                 return;
6930
6931         /* current_vmptr and current_vmcs12 are always set/reset together */
6932         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6933                 return;
6934
6935         if (enable_shadow_vmcs) {
6936                 /* copy to memory all shadowed fields in case
6937                    they were modified */
6938                 copy_shadow_to_vmcs12(vmx);
6939                 vmx->nested.sync_shadow_vmcs = false;
6940                 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
6941                                 SECONDARY_EXEC_SHADOW_VMCS);
6942                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6943         }
6944         vmx->nested.posted_intr_nv = -1;
6945         kunmap(vmx->nested.current_vmcs12_page);
6946         nested_release_page(vmx->nested.current_vmcs12_page);
6947         vmx->nested.current_vmptr = -1ull;
6948         vmx->nested.current_vmcs12 = NULL;
6949 }
6950
6951 /*
6952  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6953  * just stops using VMX.
6954  */
6955 static void free_nested(struct vcpu_vmx *vmx)
6956 {
6957         if (!vmx->nested.vmxon)
6958                 return;
6959
6960         vmx->nested.vmxon = false;
6961         free_vpid(vmx->nested.vpid02);
6962         nested_release_vmcs12(vmx);
6963         if (enable_shadow_vmcs)
6964                 free_vmcs(vmx->nested.current_shadow_vmcs);
6965         /* Unpin physical memory we referred to in current vmcs02 */
6966         if (vmx->nested.apic_access_page) {
6967                 nested_release_page(vmx->nested.apic_access_page);
6968                 vmx->nested.apic_access_page = NULL;
6969         }
6970         if (vmx->nested.virtual_apic_page) {
6971                 nested_release_page(vmx->nested.virtual_apic_page);
6972                 vmx->nested.virtual_apic_page = NULL;
6973         }
6974         if (vmx->nested.pi_desc_page) {
6975                 kunmap(vmx->nested.pi_desc_page);
6976                 nested_release_page(vmx->nested.pi_desc_page);
6977                 vmx->nested.pi_desc_page = NULL;
6978                 vmx->nested.pi_desc = NULL;
6979         }
6980
6981         nested_free_all_saved_vmcss(vmx);
6982 }
6983
6984 /* Emulate the VMXOFF instruction */
6985 static int handle_vmoff(struct kvm_vcpu *vcpu)
6986 {
6987         if (!nested_vmx_check_permission(vcpu))
6988                 return 1;
6989         free_nested(to_vmx(vcpu));
6990         skip_emulated_instruction(vcpu);
6991         nested_vmx_succeed(vcpu);
6992         return 1;
6993 }
6994
6995 /* Emulate the VMCLEAR instruction */
6996 static int handle_vmclear(struct kvm_vcpu *vcpu)
6997 {
6998         struct vcpu_vmx *vmx = to_vmx(vcpu);
6999         gpa_t vmptr;
7000         struct vmcs12 *vmcs12;
7001         struct page *page;
7002
7003         if (!nested_vmx_check_permission(vcpu))
7004                 return 1;
7005
7006         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
7007                 return 1;
7008
7009         if (vmptr == vmx->nested.current_vmptr)
7010                 nested_release_vmcs12(vmx);
7011
7012         page = nested_get_page(vcpu, vmptr);
7013         if (page == NULL) {
7014                 /*
7015                  * For accurate processor emulation, VMCLEAR beyond available
7016                  * physical memory should do nothing at all. However, it is
7017                  * possible that a nested vmx bug, not a guest hypervisor bug,
7018                  * resulted in this case, so let's shut down before doing any
7019                  * more damage:
7020                  */
7021                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7022                 return 1;
7023         }
7024         vmcs12 = kmap(page);
7025         vmcs12->launch_state = 0;
7026         kunmap(page);
7027         nested_release_page(page);
7028
7029         nested_free_vmcs02(vmx, vmptr);
7030
7031         skip_emulated_instruction(vcpu);
7032         nested_vmx_succeed(vcpu);
7033         return 1;
7034 }
7035
7036 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7037
7038 /* Emulate the VMLAUNCH instruction */
7039 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7040 {
7041         return nested_vmx_run(vcpu, true);
7042 }
7043
7044 /* Emulate the VMRESUME instruction */
7045 static int handle_vmresume(struct kvm_vcpu *vcpu)
7046 {
7047
7048         return nested_vmx_run(vcpu, false);
7049 }
7050
7051 enum vmcs_field_type {
7052         VMCS_FIELD_TYPE_U16 = 0,
7053         VMCS_FIELD_TYPE_U64 = 1,
7054         VMCS_FIELD_TYPE_U32 = 2,
7055         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
7056 };
7057
7058 static inline int vmcs_field_type(unsigned long field)
7059 {
7060         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
7061                 return VMCS_FIELD_TYPE_U32;
7062         return (field >> 13) & 0x3 ;
7063 }
7064
7065 static inline int vmcs_field_readonly(unsigned long field)
7066 {
7067         return (((field >> 10) & 0x3) == 1);
7068 }
7069
7070 /*
7071  * Read a vmcs12 field. Since these can have varying lengths and we return
7072  * one type, we chose the biggest type (u64) and zero-extend the return value
7073  * to that size. Note that the caller, handle_vmread, might need to use only
7074  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7075  * 64-bit fields are to be returned).
7076  */
7077 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7078                                   unsigned long field, u64 *ret)
7079 {
7080         short offset = vmcs_field_to_offset(field);
7081         char *p;
7082
7083         if (offset < 0)
7084                 return offset;
7085
7086         p = ((char *)(get_vmcs12(vcpu))) + offset;
7087
7088         switch (vmcs_field_type(field)) {
7089         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7090                 *ret = *((natural_width *)p);
7091                 return 0;
7092         case VMCS_FIELD_TYPE_U16:
7093                 *ret = *((u16 *)p);
7094                 return 0;
7095         case VMCS_FIELD_TYPE_U32:
7096                 *ret = *((u32 *)p);
7097                 return 0;
7098         case VMCS_FIELD_TYPE_U64:
7099                 *ret = *((u64 *)p);
7100                 return 0;
7101         default:
7102                 WARN_ON(1);
7103                 return -ENOENT;
7104         }
7105 }
7106
7107
7108 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7109                                    unsigned long field, u64 field_value){
7110         short offset = vmcs_field_to_offset(field);
7111         char *p = ((char *) get_vmcs12(vcpu)) + offset;
7112         if (offset < 0)
7113                 return offset;
7114
7115         switch (vmcs_field_type(field)) {
7116         case VMCS_FIELD_TYPE_U16:
7117                 *(u16 *)p = field_value;
7118                 return 0;
7119         case VMCS_FIELD_TYPE_U32:
7120                 *(u32 *)p = field_value;
7121                 return 0;
7122         case VMCS_FIELD_TYPE_U64:
7123                 *(u64 *)p = field_value;
7124                 return 0;
7125         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7126                 *(natural_width *)p = field_value;
7127                 return 0;
7128         default:
7129                 WARN_ON(1);
7130                 return -ENOENT;
7131         }
7132
7133 }
7134
7135 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7136 {
7137         int i;
7138         unsigned long field;
7139         u64 field_value;
7140         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7141         const unsigned long *fields = shadow_read_write_fields;
7142         const int num_fields = max_shadow_read_write_fields;
7143
7144         preempt_disable();
7145
7146         vmcs_load(shadow_vmcs);
7147
7148         for (i = 0; i < num_fields; i++) {
7149                 field = fields[i];
7150                 switch (vmcs_field_type(field)) {
7151                 case VMCS_FIELD_TYPE_U16:
7152                         field_value = vmcs_read16(field);
7153                         break;
7154                 case VMCS_FIELD_TYPE_U32:
7155                         field_value = vmcs_read32(field);
7156                         break;
7157                 case VMCS_FIELD_TYPE_U64:
7158                         field_value = vmcs_read64(field);
7159                         break;
7160                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7161                         field_value = vmcs_readl(field);
7162                         break;
7163                 default:
7164                         WARN_ON(1);
7165                         continue;
7166                 }
7167                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7168         }
7169
7170         vmcs_clear(shadow_vmcs);
7171         vmcs_load(vmx->loaded_vmcs->vmcs);
7172
7173         preempt_enable();
7174 }
7175
7176 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7177 {
7178         const unsigned long *fields[] = {
7179                 shadow_read_write_fields,
7180                 shadow_read_only_fields
7181         };
7182         const int max_fields[] = {
7183                 max_shadow_read_write_fields,
7184                 max_shadow_read_only_fields
7185         };
7186         int i, q;
7187         unsigned long field;
7188         u64 field_value = 0;
7189         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7190
7191         vmcs_load(shadow_vmcs);
7192
7193         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7194                 for (i = 0; i < max_fields[q]; i++) {
7195                         field = fields[q][i];
7196                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7197
7198                         switch (vmcs_field_type(field)) {
7199                         case VMCS_FIELD_TYPE_U16:
7200                                 vmcs_write16(field, (u16)field_value);
7201                                 break;
7202                         case VMCS_FIELD_TYPE_U32:
7203                                 vmcs_write32(field, (u32)field_value);
7204                                 break;
7205                         case VMCS_FIELD_TYPE_U64:
7206                                 vmcs_write64(field, (u64)field_value);
7207                                 break;
7208                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7209                                 vmcs_writel(field, (long)field_value);
7210                                 break;
7211                         default:
7212                                 WARN_ON(1);
7213                                 break;
7214                         }
7215                 }
7216         }
7217
7218         vmcs_clear(shadow_vmcs);
7219         vmcs_load(vmx->loaded_vmcs->vmcs);
7220 }
7221
7222 /*
7223  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7224  * used before) all generate the same failure when it is missing.
7225  */
7226 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7227 {
7228         struct vcpu_vmx *vmx = to_vmx(vcpu);
7229         if (vmx->nested.current_vmptr == -1ull) {
7230                 nested_vmx_failInvalid(vcpu);
7231                 skip_emulated_instruction(vcpu);
7232                 return 0;
7233         }
7234         return 1;
7235 }
7236
7237 static int handle_vmread(struct kvm_vcpu *vcpu)
7238 {
7239         unsigned long field;
7240         u64 field_value;
7241         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7242         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7243         gva_t gva = 0;
7244
7245         if (!nested_vmx_check_permission(vcpu) ||
7246             !nested_vmx_check_vmcs12(vcpu))
7247                 return 1;
7248
7249         /* Decode instruction info and find the field to read */
7250         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7251         /* Read the field, zero-extended to a u64 field_value */
7252         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7253                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7254                 skip_emulated_instruction(vcpu);
7255                 return 1;
7256         }
7257         /*
7258          * Now copy part of this value to register or memory, as requested.
7259          * Note that the number of bits actually copied is 32 or 64 depending
7260          * on the guest's mode (32 or 64 bit), not on the given field's length.
7261          */
7262         if (vmx_instruction_info & (1u << 10)) {
7263                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7264                         field_value);
7265         } else {
7266                 if (get_vmx_mem_address(vcpu, exit_qualification,
7267                                 vmx_instruction_info, true, &gva))
7268                         return 1;
7269                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7270                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7271                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7272         }
7273
7274         nested_vmx_succeed(vcpu);
7275         skip_emulated_instruction(vcpu);
7276         return 1;
7277 }
7278
7279
7280 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7281 {
7282         unsigned long field;
7283         gva_t gva;
7284         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7285         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7286         /* The value to write might be 32 or 64 bits, depending on L1's long
7287          * mode, and eventually we need to write that into a field of several
7288          * possible lengths. The code below first zero-extends the value to 64
7289          * bit (field_value), and then copies only the appropriate number of
7290          * bits into the vmcs12 field.
7291          */
7292         u64 field_value = 0;
7293         struct x86_exception e;
7294
7295         if (!nested_vmx_check_permission(vcpu) ||
7296             !nested_vmx_check_vmcs12(vcpu))
7297                 return 1;
7298
7299         if (vmx_instruction_info & (1u << 10))
7300                 field_value = kvm_register_readl(vcpu,
7301                         (((vmx_instruction_info) >> 3) & 0xf));
7302         else {
7303                 if (get_vmx_mem_address(vcpu, exit_qualification,
7304                                 vmx_instruction_info, false, &gva))
7305                         return 1;
7306                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7307                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7308                         kvm_inject_page_fault(vcpu, &e);
7309                         return 1;
7310                 }
7311         }
7312
7313
7314         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7315         if (vmcs_field_readonly(field)) {
7316                 nested_vmx_failValid(vcpu,
7317                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7318                 skip_emulated_instruction(vcpu);
7319                 return 1;
7320         }
7321
7322         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7323                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7324                 skip_emulated_instruction(vcpu);
7325                 return 1;
7326         }
7327
7328         nested_vmx_succeed(vcpu);
7329         skip_emulated_instruction(vcpu);
7330         return 1;
7331 }
7332
7333 /* Emulate the VMPTRLD instruction */
7334 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7335 {
7336         struct vcpu_vmx *vmx = to_vmx(vcpu);
7337         gpa_t vmptr;
7338
7339         if (!nested_vmx_check_permission(vcpu))
7340                 return 1;
7341
7342         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7343                 return 1;
7344
7345         if (vmx->nested.current_vmptr != vmptr) {
7346                 struct vmcs12 *new_vmcs12;
7347                 struct page *page;
7348                 page = nested_get_page(vcpu, vmptr);
7349                 if (page == NULL) {
7350                         nested_vmx_failInvalid(vcpu);
7351                         skip_emulated_instruction(vcpu);
7352                         return 1;
7353                 }
7354                 new_vmcs12 = kmap(page);
7355                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7356                         kunmap(page);
7357                         nested_release_page_clean(page);
7358                         nested_vmx_failValid(vcpu,
7359                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7360                         skip_emulated_instruction(vcpu);
7361                         return 1;
7362                 }
7363
7364                 nested_release_vmcs12(vmx);
7365                 vmx->nested.current_vmptr = vmptr;
7366                 vmx->nested.current_vmcs12 = new_vmcs12;
7367                 vmx->nested.current_vmcs12_page = page;
7368                 if (enable_shadow_vmcs) {
7369                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7370                                       SECONDARY_EXEC_SHADOW_VMCS);
7371                         vmcs_write64(VMCS_LINK_POINTER,
7372                                      __pa(vmx->nested.current_shadow_vmcs));
7373                         vmx->nested.sync_shadow_vmcs = true;
7374                 }
7375         }
7376
7377         nested_vmx_succeed(vcpu);
7378         skip_emulated_instruction(vcpu);
7379         return 1;
7380 }
7381
7382 /* Emulate the VMPTRST instruction */
7383 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7384 {
7385         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7386         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7387         gva_t vmcs_gva;
7388         struct x86_exception e;
7389
7390         if (!nested_vmx_check_permission(vcpu))
7391                 return 1;
7392
7393         if (get_vmx_mem_address(vcpu, exit_qualification,
7394                         vmx_instruction_info, true, &vmcs_gva))
7395                 return 1;
7396         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7397         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7398                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7399                                  sizeof(u64), &e)) {
7400                 kvm_inject_page_fault(vcpu, &e);
7401                 return 1;
7402         }
7403         nested_vmx_succeed(vcpu);
7404         skip_emulated_instruction(vcpu);
7405         return 1;
7406 }
7407
7408 /* Emulate the INVEPT instruction */
7409 static int handle_invept(struct kvm_vcpu *vcpu)
7410 {
7411         struct vcpu_vmx *vmx = to_vmx(vcpu);
7412         u32 vmx_instruction_info, types;
7413         unsigned long type;
7414         gva_t gva;
7415         struct x86_exception e;
7416         struct {
7417                 u64 eptp, gpa;
7418         } operand;
7419
7420         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7421               SECONDARY_EXEC_ENABLE_EPT) ||
7422             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7423                 kvm_queue_exception(vcpu, UD_VECTOR);
7424                 return 1;
7425         }
7426
7427         if (!nested_vmx_check_permission(vcpu))
7428                 return 1;
7429
7430         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7431                 kvm_queue_exception(vcpu, UD_VECTOR);
7432                 return 1;
7433         }
7434
7435         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7436         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7437
7438         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7439
7440         if (!(types & (1UL << type))) {
7441                 nested_vmx_failValid(vcpu,
7442                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7443                 skip_emulated_instruction(vcpu);
7444                 return 1;
7445         }
7446
7447         /* According to the Intel VMX instruction reference, the memory
7448          * operand is read even if it isn't needed (e.g., for type==global)
7449          */
7450         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7451                         vmx_instruction_info, false, &gva))
7452                 return 1;
7453         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7454                                 sizeof(operand), &e)) {
7455                 kvm_inject_page_fault(vcpu, &e);
7456                 return 1;
7457         }
7458
7459         switch (type) {
7460         case VMX_EPT_EXTENT_GLOBAL:
7461                 kvm_mmu_sync_roots(vcpu);
7462                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7463                 nested_vmx_succeed(vcpu);
7464                 break;
7465         default:
7466                 /* Trap single context invalidation invept calls */
7467                 BUG_ON(1);
7468                 break;
7469         }
7470
7471         skip_emulated_instruction(vcpu);
7472         return 1;
7473 }
7474
7475 static int handle_invvpid(struct kvm_vcpu *vcpu)
7476 {
7477         struct vcpu_vmx *vmx = to_vmx(vcpu);
7478         u32 vmx_instruction_info;
7479         unsigned long type, types;
7480         gva_t gva;
7481         struct x86_exception e;
7482         int vpid;
7483
7484         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7485               SECONDARY_EXEC_ENABLE_VPID) ||
7486                         !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7487                 kvm_queue_exception(vcpu, UD_VECTOR);
7488                 return 1;
7489         }
7490
7491         if (!nested_vmx_check_permission(vcpu))
7492                 return 1;
7493
7494         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7495         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7496
7497         types = (vmx->nested.nested_vmx_vpid_caps >> 8) & 0x7;
7498
7499         if (!(types & (1UL << type))) {
7500                 nested_vmx_failValid(vcpu,
7501                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7502                 skip_emulated_instruction(vcpu);
7503                 return 1;
7504         }
7505
7506         /* according to the intel vmx instruction reference, the memory
7507          * operand is read even if it isn't needed (e.g., for type==global)
7508          */
7509         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7510                         vmx_instruction_info, false, &gva))
7511                 return 1;
7512         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7513                                 sizeof(u32), &e)) {
7514                 kvm_inject_page_fault(vcpu, &e);
7515                 return 1;
7516         }
7517
7518         switch (type) {
7519         case VMX_VPID_EXTENT_SINGLE_CONTEXT:
7520                 /*
7521                  * Old versions of KVM use the single-context version so we
7522                  * have to support it; just treat it the same as all-context.
7523                  */
7524         case VMX_VPID_EXTENT_ALL_CONTEXT:
7525                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
7526                 nested_vmx_succeed(vcpu);
7527                 break;
7528         default:
7529                 /* Trap individual address invalidation invvpid calls */
7530                 BUG_ON(1);
7531                 break;
7532         }
7533
7534         skip_emulated_instruction(vcpu);
7535         return 1;
7536 }
7537
7538 static int handle_pml_full(struct kvm_vcpu *vcpu)
7539 {
7540         unsigned long exit_qualification;
7541
7542         trace_kvm_pml_full(vcpu->vcpu_id);
7543
7544         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7545
7546         /*
7547          * PML buffer FULL happened while executing iret from NMI,
7548          * "blocked by NMI" bit has to be set before next VM entry.
7549          */
7550         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7551                         cpu_has_virtual_nmis() &&
7552                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7553                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7554                                 GUEST_INTR_STATE_NMI);
7555
7556         /*
7557          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7558          * here.., and there's no userspace involvement needed for PML.
7559          */
7560         return 1;
7561 }
7562
7563 /*
7564  * The exit handlers return 1 if the exit was handled fully and guest execution
7565  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
7566  * to be done to userspace and return 0.
7567  */
7568 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7569         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
7570         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
7571         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
7572         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
7573         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
7574         [EXIT_REASON_CR_ACCESS]               = handle_cr,
7575         [EXIT_REASON_DR_ACCESS]               = handle_dr,
7576         [EXIT_REASON_CPUID]                   = handle_cpuid,
7577         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
7578         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
7579         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
7580         [EXIT_REASON_HLT]                     = handle_halt,
7581         [EXIT_REASON_INVD]                    = handle_invd,
7582         [EXIT_REASON_INVLPG]                  = handle_invlpg,
7583         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
7584         [EXIT_REASON_VMCALL]                  = handle_vmcall,
7585         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
7586         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
7587         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
7588         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
7589         [EXIT_REASON_VMREAD]                  = handle_vmread,
7590         [EXIT_REASON_VMRESUME]                = handle_vmresume,
7591         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
7592         [EXIT_REASON_VMOFF]                   = handle_vmoff,
7593         [EXIT_REASON_VMON]                    = handle_vmon,
7594         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
7595         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
7596         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
7597         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
7598         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
7599         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
7600         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
7601         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
7602         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
7603         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
7604         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
7605         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
7606         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
7607         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
7608         [EXIT_REASON_INVEPT]                  = handle_invept,
7609         [EXIT_REASON_INVVPID]                 = handle_invvpid,
7610         [EXIT_REASON_XSAVES]                  = handle_xsaves,
7611         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
7612         [EXIT_REASON_PML_FULL]                = handle_pml_full,
7613 };
7614
7615 static const int kvm_vmx_max_exit_handlers =
7616         ARRAY_SIZE(kvm_vmx_exit_handlers);
7617
7618 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7619                                        struct vmcs12 *vmcs12)
7620 {
7621         unsigned long exit_qualification;
7622         gpa_t bitmap, last_bitmap;
7623         unsigned int port;
7624         int size;
7625         u8 b;
7626
7627         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7628                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7629
7630         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7631
7632         port = exit_qualification >> 16;
7633         size = (exit_qualification & 7) + 1;
7634
7635         last_bitmap = (gpa_t)-1;
7636         b = -1;
7637
7638         while (size > 0) {
7639                 if (port < 0x8000)
7640                         bitmap = vmcs12->io_bitmap_a;
7641                 else if (port < 0x10000)
7642                         bitmap = vmcs12->io_bitmap_b;
7643                 else
7644                         return true;
7645                 bitmap += (port & 0x7fff) / 8;
7646
7647                 if (last_bitmap != bitmap)
7648                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7649                                 return true;
7650                 if (b & (1 << (port & 7)))
7651                         return true;
7652
7653                 port++;
7654                 size--;
7655                 last_bitmap = bitmap;
7656         }
7657
7658         return false;
7659 }
7660
7661 /*
7662  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7663  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7664  * disinterest in the current event (read or write a specific MSR) by using an
7665  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7666  */
7667 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7668         struct vmcs12 *vmcs12, u32 exit_reason)
7669 {
7670         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7671         gpa_t bitmap;
7672
7673         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7674                 return true;
7675
7676         /*
7677          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7678          * for the four combinations of read/write and low/high MSR numbers.
7679          * First we need to figure out which of the four to use:
7680          */
7681         bitmap = vmcs12->msr_bitmap;
7682         if (exit_reason == EXIT_REASON_MSR_WRITE)
7683                 bitmap += 2048;
7684         if (msr_index >= 0xc0000000) {
7685                 msr_index -= 0xc0000000;
7686                 bitmap += 1024;
7687         }
7688
7689         /* Then read the msr_index'th bit from this bitmap: */
7690         if (msr_index < 1024*8) {
7691                 unsigned char b;
7692                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7693                         return true;
7694                 return 1 & (b >> (msr_index & 7));
7695         } else
7696                 return true; /* let L1 handle the wrong parameter */
7697 }
7698
7699 /*
7700  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7701  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7702  * intercept (via guest_host_mask etc.) the current event.
7703  */
7704 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7705         struct vmcs12 *vmcs12)
7706 {
7707         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7708         int cr = exit_qualification & 15;
7709         int reg = (exit_qualification >> 8) & 15;
7710         unsigned long val = kvm_register_readl(vcpu, reg);
7711
7712         switch ((exit_qualification >> 4) & 3) {
7713         case 0: /* mov to cr */
7714                 switch (cr) {
7715                 case 0:
7716                         if (vmcs12->cr0_guest_host_mask &
7717                             (val ^ vmcs12->cr0_read_shadow))
7718                                 return true;
7719                         break;
7720                 case 3:
7721                         if ((vmcs12->cr3_target_count >= 1 &&
7722                                         vmcs12->cr3_target_value0 == val) ||
7723                                 (vmcs12->cr3_target_count >= 2 &&
7724                                         vmcs12->cr3_target_value1 == val) ||
7725                                 (vmcs12->cr3_target_count >= 3 &&
7726                                         vmcs12->cr3_target_value2 == val) ||
7727                                 (vmcs12->cr3_target_count >= 4 &&
7728                                         vmcs12->cr3_target_value3 == val))
7729                                 return false;
7730                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7731                                 return true;
7732                         break;
7733                 case 4:
7734                         if (vmcs12->cr4_guest_host_mask &
7735                             (vmcs12->cr4_read_shadow ^ val))
7736                                 return true;
7737                         break;
7738                 case 8:
7739                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7740                                 return true;
7741                         break;
7742                 }
7743                 break;
7744         case 2: /* clts */
7745                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7746                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
7747                         return true;
7748                 break;
7749         case 1: /* mov from cr */
7750                 switch (cr) {
7751                 case 3:
7752                         if (vmcs12->cpu_based_vm_exec_control &
7753                             CPU_BASED_CR3_STORE_EXITING)
7754                                 return true;
7755                         break;
7756                 case 8:
7757                         if (vmcs12->cpu_based_vm_exec_control &
7758                             CPU_BASED_CR8_STORE_EXITING)
7759                                 return true;
7760                         break;
7761                 }
7762                 break;
7763         case 3: /* lmsw */
7764                 /*
7765                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7766                  * cr0. Other attempted changes are ignored, with no exit.
7767                  */
7768                 if (vmcs12->cr0_guest_host_mask & 0xe &
7769                     (val ^ vmcs12->cr0_read_shadow))
7770                         return true;
7771                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7772                     !(vmcs12->cr0_read_shadow & 0x1) &&
7773                     (val & 0x1))
7774                         return true;
7775                 break;
7776         }
7777         return false;
7778 }
7779
7780 /*
7781  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7782  * should handle it ourselves in L0 (and then continue L2). Only call this
7783  * when in is_guest_mode (L2).
7784  */
7785 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7786 {
7787         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7788         struct vcpu_vmx *vmx = to_vmx(vcpu);
7789         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7790         u32 exit_reason = vmx->exit_reason;
7791
7792         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7793                                 vmcs_readl(EXIT_QUALIFICATION),
7794                                 vmx->idt_vectoring_info,
7795                                 intr_info,
7796                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7797                                 KVM_ISA_VMX);
7798
7799         if (vmx->nested.nested_run_pending)
7800                 return false;
7801
7802         if (unlikely(vmx->fail)) {
7803                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7804                                     vmcs_read32(VM_INSTRUCTION_ERROR));
7805                 return true;
7806         }
7807
7808         switch (exit_reason) {
7809         case EXIT_REASON_EXCEPTION_NMI:
7810                 if (!is_exception(intr_info))
7811                         return false;
7812                 else if (is_page_fault(intr_info))
7813                         return enable_ept;
7814                 else if (is_no_device(intr_info) &&
7815                          !(vmcs12->guest_cr0 & X86_CR0_TS))
7816                         return false;
7817                 else if (is_debug(intr_info) &&
7818                          vcpu->guest_debug &
7819                          (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
7820                         return false;
7821                 else if (is_breakpoint(intr_info) &&
7822                          vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
7823                         return false;
7824                 return vmcs12->exception_bitmap &
7825                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7826         case EXIT_REASON_EXTERNAL_INTERRUPT:
7827                 return false;
7828         case EXIT_REASON_TRIPLE_FAULT:
7829                 return true;
7830         case EXIT_REASON_PENDING_INTERRUPT:
7831                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
7832         case EXIT_REASON_NMI_WINDOW:
7833                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
7834         case EXIT_REASON_TASK_SWITCH:
7835                 return true;
7836         case EXIT_REASON_CPUID:
7837                 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7838                         return false;
7839                 return true;
7840         case EXIT_REASON_HLT:
7841                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7842         case EXIT_REASON_INVD:
7843                 return true;
7844         case EXIT_REASON_INVLPG:
7845                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7846         case EXIT_REASON_RDPMC:
7847                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7848         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
7849                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7850         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7851         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7852         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7853         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7854         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
7855         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
7856                 /*
7857                  * VMX instructions trap unconditionally. This allows L1 to
7858                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
7859                  */
7860                 return true;
7861         case EXIT_REASON_CR_ACCESS:
7862                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7863         case EXIT_REASON_DR_ACCESS:
7864                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7865         case EXIT_REASON_IO_INSTRUCTION:
7866                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
7867         case EXIT_REASON_MSR_READ:
7868         case EXIT_REASON_MSR_WRITE:
7869                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7870         case EXIT_REASON_INVALID_STATE:
7871                 return true;
7872         case EXIT_REASON_MWAIT_INSTRUCTION:
7873                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7874         case EXIT_REASON_MONITOR_TRAP_FLAG:
7875                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
7876         case EXIT_REASON_MONITOR_INSTRUCTION:
7877                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7878         case EXIT_REASON_PAUSE_INSTRUCTION:
7879                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7880                         nested_cpu_has2(vmcs12,
7881                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7882         case EXIT_REASON_MCE_DURING_VMENTRY:
7883                 return false;
7884         case EXIT_REASON_TPR_BELOW_THRESHOLD:
7885                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
7886         case EXIT_REASON_APIC_ACCESS:
7887                 return nested_cpu_has2(vmcs12,
7888                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7889         case EXIT_REASON_APIC_WRITE:
7890         case EXIT_REASON_EOI_INDUCED:
7891                 /* apic_write and eoi_induced should exit unconditionally. */
7892                 return true;
7893         case EXIT_REASON_EPT_VIOLATION:
7894                 /*
7895                  * L0 always deals with the EPT violation. If nested EPT is
7896                  * used, and the nested mmu code discovers that the address is
7897                  * missing in the guest EPT table (EPT12), the EPT violation
7898                  * will be injected with nested_ept_inject_page_fault()
7899                  */
7900                 return false;
7901         case EXIT_REASON_EPT_MISCONFIG:
7902                 /*
7903                  * L2 never uses directly L1's EPT, but rather L0's own EPT
7904                  * table (shadow on EPT) or a merged EPT table that L0 built
7905                  * (EPT on EPT). So any problems with the structure of the
7906                  * table is L0's fault.
7907                  */
7908                 return false;
7909         case EXIT_REASON_WBINVD:
7910                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7911         case EXIT_REASON_XSETBV:
7912                 return true;
7913         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7914                 /*
7915                  * This should never happen, since it is not possible to
7916                  * set XSS to a non-zero value---neither in L1 nor in L2.
7917                  * If if it were, XSS would have to be checked against
7918                  * the XSS exit bitmap in vmcs12.
7919                  */
7920                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
7921         default:
7922                 return true;
7923         }
7924 }
7925
7926 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7927 {
7928         *info1 = vmcs_readl(EXIT_QUALIFICATION);
7929         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7930 }
7931
7932 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
7933 {
7934         if (vmx->pml_pg) {
7935                 __free_page(vmx->pml_pg);
7936                 vmx->pml_pg = NULL;
7937         }
7938 }
7939
7940 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
7941 {
7942         struct vcpu_vmx *vmx = to_vmx(vcpu);
7943         u64 *pml_buf;
7944         u16 pml_idx;
7945
7946         pml_idx = vmcs_read16(GUEST_PML_INDEX);
7947
7948         /* Do nothing if PML buffer is empty */
7949         if (pml_idx == (PML_ENTITY_NUM - 1))
7950                 return;
7951
7952         /* PML index always points to next available PML buffer entity */
7953         if (pml_idx >= PML_ENTITY_NUM)
7954                 pml_idx = 0;
7955         else
7956                 pml_idx++;
7957
7958         pml_buf = page_address(vmx->pml_pg);
7959         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7960                 u64 gpa;
7961
7962                 gpa = pml_buf[pml_idx];
7963                 WARN_ON(gpa & (PAGE_SIZE - 1));
7964                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
7965         }
7966
7967         /* reset PML index */
7968         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7969 }
7970
7971 /*
7972  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7973  * Called before reporting dirty_bitmap to userspace.
7974  */
7975 static void kvm_flush_pml_buffers(struct kvm *kvm)
7976 {
7977         int i;
7978         struct kvm_vcpu *vcpu;
7979         /*
7980          * We only need to kick vcpu out of guest mode here, as PML buffer
7981          * is flushed at beginning of all VMEXITs, and it's obvious that only
7982          * vcpus running in guest are possible to have unflushed GPAs in PML
7983          * buffer.
7984          */
7985         kvm_for_each_vcpu(i, vcpu, kvm)
7986                 kvm_vcpu_kick(vcpu);
7987 }
7988
7989 static void vmx_dump_sel(char *name, uint32_t sel)
7990 {
7991         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
7992                name, vmcs_read32(sel),
7993                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
7994                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
7995                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
7996 }
7997
7998 static void vmx_dump_dtsel(char *name, uint32_t limit)
7999 {
8000         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
8001                name, vmcs_read32(limit),
8002                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8003 }
8004
8005 static void dump_vmcs(void)
8006 {
8007         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8008         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8009         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8010         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8011         u32 secondary_exec_control = 0;
8012         unsigned long cr4 = vmcs_readl(GUEST_CR4);
8013         u64 efer = vmcs_read64(GUEST_IA32_EFER);
8014         int i, n;
8015
8016         if (cpu_has_secondary_exec_ctrls())
8017                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8018
8019         pr_err("*** Guest State ***\n");
8020         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8021                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8022                vmcs_readl(CR0_GUEST_HOST_MASK));
8023         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8024                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8025         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8026         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8027             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8028         {
8029                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
8030                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8031                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
8032                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
8033         }
8034         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
8035                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8036         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
8037                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8038         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8039                vmcs_readl(GUEST_SYSENTER_ESP),
8040                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8041         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
8042         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
8043         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
8044         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
8045         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
8046         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
8047         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8048         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8049         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8050         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
8051         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8052             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
8053                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
8054                        efer, vmcs_read64(GUEST_IA32_PAT));
8055         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
8056                vmcs_read64(GUEST_IA32_DEBUGCTL),
8057                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8058         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
8059                 pr_err("PerfGlobCtl = 0x%016llx\n",
8060                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
8061         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
8062                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
8063         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
8064                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8065                vmcs_read32(GUEST_ACTIVITY_STATE));
8066         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8067                 pr_err("InterruptStatus = %04x\n",
8068                        vmcs_read16(GUEST_INTR_STATUS));
8069
8070         pr_err("*** Host State ***\n");
8071         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
8072                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8073         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8074                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8075                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8076                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8077                vmcs_read16(HOST_TR_SELECTOR));
8078         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8079                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8080                vmcs_readl(HOST_TR_BASE));
8081         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8082                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8083         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8084                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8085                vmcs_readl(HOST_CR4));
8086         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8087                vmcs_readl(HOST_IA32_SYSENTER_ESP),
8088                vmcs_read32(HOST_IA32_SYSENTER_CS),
8089                vmcs_readl(HOST_IA32_SYSENTER_EIP));
8090         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8091                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
8092                        vmcs_read64(HOST_IA32_EFER),
8093                        vmcs_read64(HOST_IA32_PAT));
8094         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8095                 pr_err("PerfGlobCtl = 0x%016llx\n",
8096                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
8097
8098         pr_err("*** Control State ***\n");
8099         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8100                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8101         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8102         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8103                vmcs_read32(EXCEPTION_BITMAP),
8104                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8105                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8106         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8107                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8108                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8109                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8110         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8111                vmcs_read32(VM_EXIT_INTR_INFO),
8112                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8113                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8114         pr_err("        reason=%08x qualification=%016lx\n",
8115                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8116         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8117                vmcs_read32(IDT_VECTORING_INFO_FIELD),
8118                vmcs_read32(IDT_VECTORING_ERROR_CODE));
8119         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8120         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8121                 pr_err("TSC Multiplier = 0x%016llx\n",
8122                        vmcs_read64(TSC_MULTIPLIER));
8123         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8124                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8125         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8126                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8127         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8128                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8129         n = vmcs_read32(CR3_TARGET_COUNT);
8130         for (i = 0; i + 1 < n; i += 4)
8131                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8132                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8133                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8134         if (i < n)
8135                 pr_err("CR3 target%u=%016lx\n",
8136                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8137         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8138                 pr_err("PLE Gap=%08x Window=%08x\n",
8139                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8140         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8141                 pr_err("Virtual processor ID = 0x%04x\n",
8142                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
8143 }
8144
8145 /*
8146  * The guest has exited.  See if we can fix it or if we need userspace
8147  * assistance.
8148  */
8149 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8150 {
8151         struct vcpu_vmx *vmx = to_vmx(vcpu);
8152         u32 exit_reason = vmx->exit_reason;
8153         u32 vectoring_info = vmx->idt_vectoring_info;
8154
8155         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8156
8157         /*
8158          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8159          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8160          * querying dirty_bitmap, we only need to kick all vcpus out of guest
8161          * mode as if vcpus is in root mode, the PML buffer must has been
8162          * flushed already.
8163          */
8164         if (enable_pml)
8165                 vmx_flush_pml_buffer(vcpu);
8166
8167         /* If guest state is invalid, start emulating */
8168         if (vmx->emulation_required)
8169                 return handle_invalid_guest_state(vcpu);
8170
8171         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8172                 nested_vmx_vmexit(vcpu, exit_reason,
8173                                   vmcs_read32(VM_EXIT_INTR_INFO),
8174                                   vmcs_readl(EXIT_QUALIFICATION));
8175                 return 1;
8176         }
8177
8178         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8179                 dump_vmcs();
8180                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8181                 vcpu->run->fail_entry.hardware_entry_failure_reason
8182                         = exit_reason;
8183                 return 0;
8184         }
8185
8186         if (unlikely(vmx->fail)) {
8187                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8188                 vcpu->run->fail_entry.hardware_entry_failure_reason
8189                         = vmcs_read32(VM_INSTRUCTION_ERROR);
8190                 return 0;
8191         }
8192
8193         /*
8194          * Note:
8195          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8196          * delivery event since it indicates guest is accessing MMIO.
8197          * The vm-exit can be triggered again after return to guest that
8198          * will cause infinite loop.
8199          */
8200         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8201                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8202                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
8203                         exit_reason != EXIT_REASON_PML_FULL &&
8204                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
8205                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8206                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8207                 vcpu->run->internal.ndata = 2;
8208                 vcpu->run->internal.data[0] = vectoring_info;
8209                 vcpu->run->internal.data[1] = exit_reason;
8210                 return 0;
8211         }
8212
8213         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
8214             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
8215                                         get_vmcs12(vcpu))))) {
8216                 if (vmx_interrupt_allowed(vcpu)) {
8217                         vmx->soft_vnmi_blocked = 0;
8218                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
8219                            vcpu->arch.nmi_pending) {
8220                         /*
8221                          * This CPU don't support us in finding the end of an
8222                          * NMI-blocked window if the guest runs with IRQs
8223                          * disabled. So we pull the trigger after 1 s of
8224                          * futile waiting, but inform the user about this.
8225                          */
8226                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8227                                "state on VCPU %d after 1 s timeout\n",
8228                                __func__, vcpu->vcpu_id);
8229                         vmx->soft_vnmi_blocked = 0;
8230                 }
8231         }
8232
8233         if (exit_reason < kvm_vmx_max_exit_handlers
8234             && kvm_vmx_exit_handlers[exit_reason])
8235                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8236         else {
8237                 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
8238                 kvm_queue_exception(vcpu, UD_VECTOR);
8239                 return 1;
8240         }
8241 }
8242
8243 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8244 {
8245         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8246
8247         if (is_guest_mode(vcpu) &&
8248                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8249                 return;
8250
8251         if (irr == -1 || tpr < irr) {
8252                 vmcs_write32(TPR_THRESHOLD, 0);
8253                 return;
8254         }
8255
8256         vmcs_write32(TPR_THRESHOLD, irr);
8257 }
8258
8259 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8260 {
8261         u32 sec_exec_control;
8262
8263         /*
8264          * There is not point to enable virtualize x2apic without enable
8265          * apicv
8266          */
8267         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
8268                                 !kvm_vcpu_apicv_active(vcpu))
8269                 return;
8270
8271         if (!cpu_need_tpr_shadow(vcpu))
8272                 return;
8273
8274         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8275
8276         if (set) {
8277                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8278                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8279         } else {
8280                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8281                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8282         }
8283         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8284
8285         vmx_set_msr_bitmap(vcpu);
8286 }
8287
8288 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8289 {
8290         struct vcpu_vmx *vmx = to_vmx(vcpu);
8291
8292         /*
8293          * Currently we do not handle the nested case where L2 has an
8294          * APIC access page of its own; that page is still pinned.
8295          * Hence, we skip the case where the VCPU is in guest mode _and_
8296          * L1 prepared an APIC access page for L2.
8297          *
8298          * For the case where L1 and L2 share the same APIC access page
8299          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8300          * in the vmcs12), this function will only update either the vmcs01
8301          * or the vmcs02.  If the former, the vmcs02 will be updated by
8302          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
8303          * the next L2->L1 exit.
8304          */
8305         if (!is_guest_mode(vcpu) ||
8306             !nested_cpu_has2(vmx->nested.current_vmcs12,
8307                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8308                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8309 }
8310
8311 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
8312 {
8313         u16 status;
8314         u8 old;
8315
8316         if (max_isr == -1)
8317                 max_isr = 0;
8318
8319         status = vmcs_read16(GUEST_INTR_STATUS);
8320         old = status >> 8;
8321         if (max_isr != old) {
8322                 status &= 0xff;
8323                 status |= max_isr << 8;
8324                 vmcs_write16(GUEST_INTR_STATUS, status);
8325         }
8326 }
8327
8328 static void vmx_set_rvi(int vector)
8329 {
8330         u16 status;
8331         u8 old;
8332
8333         if (vector == -1)
8334                 vector = 0;
8335
8336         status = vmcs_read16(GUEST_INTR_STATUS);
8337         old = (u8)status & 0xff;
8338         if ((u8)vector != old) {
8339                 status &= ~0xff;
8340                 status |= (u8)vector;
8341                 vmcs_write16(GUEST_INTR_STATUS, status);
8342         }
8343 }
8344
8345 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8346 {
8347         if (!is_guest_mode(vcpu)) {
8348                 vmx_set_rvi(max_irr);
8349                 return;
8350         }
8351
8352         if (max_irr == -1)
8353                 return;
8354
8355         /*
8356          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
8357          * handles it.
8358          */
8359         if (nested_exit_on_intr(vcpu))
8360                 return;
8361
8362         /*
8363          * Else, fall back to pre-APICv interrupt injection since L2
8364          * is run without virtual interrupt delivery.
8365          */
8366         if (!kvm_event_needs_reinjection(vcpu) &&
8367             vmx_interrupt_allowed(vcpu)) {
8368                 kvm_queue_interrupt(vcpu, max_irr, false);
8369                 vmx_inject_irq(vcpu);
8370         }
8371 }
8372
8373 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
8374 {
8375         if (!kvm_vcpu_apicv_active(vcpu))
8376                 return;
8377
8378         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8379         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8380         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8381         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8382 }
8383
8384 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8385 {
8386         u32 exit_intr_info;
8387
8388         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8389               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8390                 return;
8391
8392         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8393         exit_intr_info = vmx->exit_intr_info;
8394
8395         /* Handle machine checks before interrupts are enabled */
8396         if (is_machine_check(exit_intr_info))
8397                 kvm_machine_check();
8398
8399         /* We need to handle NMIs before interrupts are enabled */
8400         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
8401             (exit_intr_info & INTR_INFO_VALID_MASK)) {
8402                 kvm_before_handle_nmi(&vmx->vcpu);
8403                 asm("int $2");
8404                 kvm_after_handle_nmi(&vmx->vcpu);
8405         }
8406 }
8407
8408 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8409 {
8410         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8411         register void *__sp asm(_ASM_SP);
8412
8413         /*
8414          * If external interrupt exists, IF bit is set in rflags/eflags on the
8415          * interrupt stack frame, and interrupt will be enabled on a return
8416          * from interrupt handler.
8417          */
8418         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8419                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8420                 unsigned int vector;
8421                 unsigned long entry;
8422                 gate_desc *desc;
8423                 struct vcpu_vmx *vmx = to_vmx(vcpu);
8424 #ifdef CONFIG_X86_64
8425                 unsigned long tmp;
8426 #endif
8427
8428                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
8429                 desc = (gate_desc *)vmx->host_idt_base + vector;
8430                 entry = gate_offset(*desc);
8431                 asm volatile(
8432 #ifdef CONFIG_X86_64
8433                         "mov %%" _ASM_SP ", %[sp]\n\t"
8434                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8435                         "push $%c[ss]\n\t"
8436                         "push %[sp]\n\t"
8437 #endif
8438                         "pushf\n\t"
8439                         "orl $0x200, (%%" _ASM_SP ")\n\t"
8440                         __ASM_SIZE(push) " $%c[cs]\n\t"
8441                         "call *%[entry]\n\t"
8442                         :
8443 #ifdef CONFIG_X86_64
8444                         [sp]"=&r"(tmp),
8445 #endif
8446                         "+r"(__sp)
8447                         :
8448                         [entry]"r"(entry),
8449                         [ss]"i"(__KERNEL_DS),
8450                         [cs]"i"(__KERNEL_CS)
8451                         );
8452         } else
8453                 local_irq_enable();
8454 }
8455
8456 static bool vmx_has_high_real_mode_segbase(void)
8457 {
8458         return enable_unrestricted_guest || emulate_invalid_guest_state;
8459 }
8460
8461 static bool vmx_mpx_supported(void)
8462 {
8463         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8464                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8465 }
8466
8467 static bool vmx_xsaves_supported(void)
8468 {
8469         return vmcs_config.cpu_based_2nd_exec_ctrl &
8470                 SECONDARY_EXEC_XSAVES;
8471 }
8472
8473 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8474 {
8475         u32 exit_intr_info;
8476         bool unblock_nmi;
8477         u8 vector;
8478         bool idtv_info_valid;
8479
8480         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8481
8482         if (cpu_has_virtual_nmis()) {
8483                 if (vmx->nmi_known_unmasked)
8484                         return;
8485                 /*
8486                  * Can't use vmx->exit_intr_info since we're not sure what
8487                  * the exit reason is.
8488                  */
8489                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8490                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8491                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8492                 /*
8493                  * SDM 3: 27.7.1.2 (September 2008)
8494                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
8495                  * a guest IRET fault.
8496                  * SDM 3: 23.2.2 (September 2008)
8497                  * Bit 12 is undefined in any of the following cases:
8498                  *  If the VM exit sets the valid bit in the IDT-vectoring
8499                  *   information field.
8500                  *  If the VM exit is due to a double fault.
8501                  */
8502                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8503                     vector != DF_VECTOR && !idtv_info_valid)
8504                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8505                                       GUEST_INTR_STATE_NMI);
8506                 else
8507                         vmx->nmi_known_unmasked =
8508                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8509                                   & GUEST_INTR_STATE_NMI);
8510         } else if (unlikely(vmx->soft_vnmi_blocked))
8511                 vmx->vnmi_blocked_time +=
8512                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8513 }
8514
8515 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8516                                       u32 idt_vectoring_info,
8517                                       int instr_len_field,
8518                                       int error_code_field)
8519 {
8520         u8 vector;
8521         int type;
8522         bool idtv_info_valid;
8523
8524         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8525
8526         vcpu->arch.nmi_injected = false;
8527         kvm_clear_exception_queue(vcpu);
8528         kvm_clear_interrupt_queue(vcpu);
8529
8530         if (!idtv_info_valid)
8531                 return;
8532
8533         kvm_make_request(KVM_REQ_EVENT, vcpu);
8534
8535         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8536         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8537
8538         switch (type) {
8539         case INTR_TYPE_NMI_INTR:
8540                 vcpu->arch.nmi_injected = true;
8541                 /*
8542                  * SDM 3: 27.7.1.2 (September 2008)
8543                  * Clear bit "block by NMI" before VM entry if a NMI
8544                  * delivery faulted.
8545                  */
8546                 vmx_set_nmi_mask(vcpu, false);
8547                 break;
8548         case INTR_TYPE_SOFT_EXCEPTION:
8549                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8550                 /* fall through */
8551         case INTR_TYPE_HARD_EXCEPTION:
8552                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8553                         u32 err = vmcs_read32(error_code_field);
8554                         kvm_requeue_exception_e(vcpu, vector, err);
8555                 } else
8556                         kvm_requeue_exception(vcpu, vector);
8557                 break;
8558         case INTR_TYPE_SOFT_INTR:
8559                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8560                 /* fall through */
8561         case INTR_TYPE_EXT_INTR:
8562                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8563                 break;
8564         default:
8565                 break;
8566         }
8567 }
8568
8569 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8570 {
8571         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8572                                   VM_EXIT_INSTRUCTION_LEN,
8573                                   IDT_VECTORING_ERROR_CODE);
8574 }
8575
8576 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8577 {
8578         __vmx_complete_interrupts(vcpu,
8579                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8580                                   VM_ENTRY_INSTRUCTION_LEN,
8581                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
8582
8583         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8584 }
8585
8586 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8587 {
8588         int i, nr_msrs;
8589         struct perf_guest_switch_msr *msrs;
8590
8591         msrs = perf_guest_get_msrs(&nr_msrs);
8592
8593         if (!msrs)
8594                 return;
8595
8596         for (i = 0; i < nr_msrs; i++)
8597                 if (msrs[i].host == msrs[i].guest)
8598                         clear_atomic_switch_msr(vmx, msrs[i].msr);
8599                 else
8600                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8601                                         msrs[i].host);
8602 }
8603
8604 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8605 {
8606         struct vcpu_vmx *vmx = to_vmx(vcpu);
8607         unsigned long debugctlmsr, cr4;
8608
8609         /* Record the guest's net vcpu time for enforced NMI injections. */
8610         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8611                 vmx->entry_time = ktime_get();
8612
8613         /* Don't enter VMX if guest state is invalid, let the exit handler
8614            start emulation until we arrive back to a valid state */
8615         if (vmx->emulation_required)
8616                 return;
8617
8618         if (vmx->ple_window_dirty) {
8619                 vmx->ple_window_dirty = false;
8620                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8621         }
8622
8623         if (vmx->nested.sync_shadow_vmcs) {
8624                 copy_vmcs12_to_shadow(vmx);
8625                 vmx->nested.sync_shadow_vmcs = false;
8626         }
8627
8628         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8629                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8630         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8631                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8632
8633         cr4 = cr4_read_shadow();
8634         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8635                 vmcs_writel(HOST_CR4, cr4);
8636                 vmx->host_state.vmcs_host_cr4 = cr4;
8637         }
8638
8639         /* When single-stepping over STI and MOV SS, we must clear the
8640          * corresponding interruptibility bits in the guest state. Otherwise
8641          * vmentry fails as it then expects bit 14 (BS) in pending debug
8642          * exceptions being set, but that's not correct for the guest debugging
8643          * case. */
8644         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8645                 vmx_set_interrupt_shadow(vcpu, 0);
8646
8647         if (vmx->guest_pkru_valid)
8648                 __write_pkru(vmx->guest_pkru);
8649
8650         atomic_switch_perf_msrs(vmx);
8651         debugctlmsr = get_debugctlmsr();
8652
8653         vmx->__launched = vmx->loaded_vmcs->launched;
8654         asm(
8655                 /* Store host registers */
8656                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8657                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8658                 "push %%" _ASM_CX " \n\t"
8659                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8660                 "je 1f \n\t"
8661                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8662                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8663                 "1: \n\t"
8664                 /* Reload cr2 if changed */
8665                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8666                 "mov %%cr2, %%" _ASM_DX " \n\t"
8667                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8668                 "je 2f \n\t"
8669                 "mov %%" _ASM_AX", %%cr2 \n\t"
8670                 "2: \n\t"
8671                 /* Check if vmlaunch of vmresume is needed */
8672                 "cmpl $0, %c[launched](%0) \n\t"
8673                 /* Load guest registers.  Don't clobber flags. */
8674                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8675                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8676                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8677                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8678                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8679                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8680 #ifdef CONFIG_X86_64
8681                 "mov %c[r8](%0),  %%r8  \n\t"
8682                 "mov %c[r9](%0),  %%r9  \n\t"
8683                 "mov %c[r10](%0), %%r10 \n\t"
8684                 "mov %c[r11](%0), %%r11 \n\t"
8685                 "mov %c[r12](%0), %%r12 \n\t"
8686                 "mov %c[r13](%0), %%r13 \n\t"
8687                 "mov %c[r14](%0), %%r14 \n\t"
8688                 "mov %c[r15](%0), %%r15 \n\t"
8689 #endif
8690                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8691
8692                 /* Enter guest mode */
8693                 "jne 1f \n\t"
8694                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8695                 "jmp 2f \n\t"
8696                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8697                 "2: "
8698                 /* Save guest registers, load host registers, keep flags */
8699                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8700                 "pop %0 \n\t"
8701                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8702                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8703                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8704                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8705                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8706                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8707                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8708 #ifdef CONFIG_X86_64
8709                 "mov %%r8,  %c[r8](%0) \n\t"
8710                 "mov %%r9,  %c[r9](%0) \n\t"
8711                 "mov %%r10, %c[r10](%0) \n\t"
8712                 "mov %%r11, %c[r11](%0) \n\t"
8713                 "mov %%r12, %c[r12](%0) \n\t"
8714                 "mov %%r13, %c[r13](%0) \n\t"
8715                 "mov %%r14, %c[r14](%0) \n\t"
8716                 "mov %%r15, %c[r15](%0) \n\t"
8717 #endif
8718                 "mov %%cr2, %%" _ASM_AX "   \n\t"
8719                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
8720
8721                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
8722                 "setbe %c[fail](%0) \n\t"
8723                 ".pushsection .rodata \n\t"
8724                 ".global vmx_return \n\t"
8725                 "vmx_return: " _ASM_PTR " 2b \n\t"
8726                 ".popsection"
8727               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
8728                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
8729                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
8730                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
8731                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8732                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8733                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8734                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8735                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8736                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8737                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
8738 #ifdef CONFIG_X86_64
8739                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8740                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8741                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8742                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8743                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8744                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8745                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8746                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
8747 #endif
8748                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8749                 [wordsize]"i"(sizeof(ulong))
8750               : "cc", "memory"
8751 #ifdef CONFIG_X86_64
8752                 , "rax", "rbx", "rdi", "rsi"
8753                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8754 #else
8755                 , "eax", "ebx", "edi", "esi"
8756 #endif
8757               );
8758
8759         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8760         if (debugctlmsr)
8761                 update_debugctlmsr(debugctlmsr);
8762
8763 #ifndef CONFIG_X86_64
8764         /*
8765          * The sysexit path does not restore ds/es, so we must set them to
8766          * a reasonable value ourselves.
8767          *
8768          * We can't defer this to vmx_load_host_state() since that function
8769          * may be executed in interrupt context, which saves and restore segments
8770          * around it, nullifying its effect.
8771          */
8772         loadsegment(ds, __USER_DS);
8773         loadsegment(es, __USER_DS);
8774 #endif
8775
8776         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
8777                                   | (1 << VCPU_EXREG_RFLAGS)
8778                                   | (1 << VCPU_EXREG_PDPTR)
8779                                   | (1 << VCPU_EXREG_SEGMENTS)
8780                                   | (1 << VCPU_EXREG_CR3));
8781         vcpu->arch.regs_dirty = 0;
8782
8783         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8784
8785         vmx->loaded_vmcs->launched = 1;
8786
8787         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
8788
8789         /*
8790          * eager fpu is enabled if PKEY is supported and CR4 is switched
8791          * back on host, so it is safe to read guest PKRU from current
8792          * XSAVE.
8793          */
8794         if (boot_cpu_has(X86_FEATURE_OSPKE)) {
8795                 vmx->guest_pkru = __read_pkru();
8796                 if (vmx->guest_pkru != vmx->host_pkru) {
8797                         vmx->guest_pkru_valid = true;
8798                         __write_pkru(vmx->host_pkru);
8799                 } else
8800                         vmx->guest_pkru_valid = false;
8801         }
8802
8803         /*
8804          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8805          * we did not inject a still-pending event to L1 now because of
8806          * nested_run_pending, we need to re-enable this bit.
8807          */
8808         if (vmx->nested.nested_run_pending)
8809                 kvm_make_request(KVM_REQ_EVENT, vcpu);
8810
8811         vmx->nested.nested_run_pending = 0;
8812
8813         vmx_complete_atomic_exit(vmx);
8814         vmx_recover_nmi_blocking(vmx);
8815         vmx_complete_interrupts(vmx);
8816 }
8817
8818 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8819 {
8820         struct vcpu_vmx *vmx = to_vmx(vcpu);
8821         int cpu;
8822
8823         if (vmx->loaded_vmcs == &vmx->vmcs01)
8824                 return;
8825
8826         cpu = get_cpu();
8827         vmx->loaded_vmcs = &vmx->vmcs01;
8828         vmx_vcpu_put(vcpu);
8829         vmx_vcpu_load(vcpu, cpu);
8830         vcpu->cpu = cpu;
8831         put_cpu();
8832 }
8833
8834 /*
8835  * Ensure that the current vmcs of the logical processor is the
8836  * vmcs01 of the vcpu before calling free_nested().
8837  */
8838 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
8839 {
8840        struct vcpu_vmx *vmx = to_vmx(vcpu);
8841        int r;
8842
8843        r = vcpu_load(vcpu);
8844        BUG_ON(r);
8845        vmx_load_vmcs01(vcpu);
8846        free_nested(vmx);
8847        vcpu_put(vcpu);
8848 }
8849
8850 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8851 {
8852         struct vcpu_vmx *vmx = to_vmx(vcpu);
8853
8854         if (enable_pml)
8855                 vmx_destroy_pml_buffer(vmx);
8856         free_vpid(vmx->vpid);
8857         leave_guest_mode(vcpu);
8858         vmx_free_vcpu_nested(vcpu);
8859         free_loaded_vmcs(vmx->loaded_vmcs);
8860         kfree(vmx->guest_msrs);
8861         kvm_vcpu_uninit(vcpu);
8862         kmem_cache_free(kvm_vcpu_cache, vmx);
8863 }
8864
8865 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
8866 {
8867         int err;
8868         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
8869         int cpu;
8870
8871         if (!vmx)
8872                 return ERR_PTR(-ENOMEM);
8873
8874         vmx->vpid = allocate_vpid();
8875
8876         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8877         if (err)
8878                 goto free_vcpu;
8879
8880         err = -ENOMEM;
8881
8882         /*
8883          * If PML is turned on, failure on enabling PML just results in failure
8884          * of creating the vcpu, therefore we can simplify PML logic (by
8885          * avoiding dealing with cases, such as enabling PML partially on vcpus
8886          * for the guest, etc.
8887          */
8888         if (enable_pml) {
8889                 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
8890                 if (!vmx->pml_pg)
8891                         goto uninit_vcpu;
8892         }
8893
8894         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
8895         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8896                      > PAGE_SIZE);
8897
8898         if (!vmx->guest_msrs)
8899                 goto free_pml;
8900
8901         vmx->loaded_vmcs = &vmx->vmcs01;
8902         vmx->loaded_vmcs->vmcs = alloc_vmcs();
8903         if (!vmx->loaded_vmcs->vmcs)
8904                 goto free_msrs;
8905         if (!vmm_exclusive)
8906                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8907         loaded_vmcs_init(vmx->loaded_vmcs);
8908         if (!vmm_exclusive)
8909                 kvm_cpu_vmxoff();
8910
8911         cpu = get_cpu();
8912         vmx_vcpu_load(&vmx->vcpu, cpu);
8913         vmx->vcpu.cpu = cpu;
8914         err = vmx_vcpu_setup(vmx);
8915         vmx_vcpu_put(&vmx->vcpu);
8916         put_cpu();
8917         if (err)
8918                 goto free_vmcs;
8919         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
8920                 err = alloc_apic_access_page(kvm);
8921                 if (err)
8922                         goto free_vmcs;
8923         }
8924
8925         if (enable_ept) {
8926                 if (!kvm->arch.ept_identity_map_addr)
8927                         kvm->arch.ept_identity_map_addr =
8928                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
8929                 err = init_rmode_identity_map(kvm);
8930                 if (err)
8931                         goto free_vmcs;
8932         }
8933
8934         if (nested) {
8935                 nested_vmx_setup_ctls_msrs(vmx);
8936                 vmx->nested.vpid02 = allocate_vpid();
8937         }
8938
8939         vmx->nested.posted_intr_nv = -1;
8940         vmx->nested.current_vmptr = -1ull;
8941         vmx->nested.current_vmcs12 = NULL;
8942
8943         return &vmx->vcpu;
8944
8945 free_vmcs:
8946         free_vpid(vmx->nested.vpid02);
8947         free_loaded_vmcs(vmx->loaded_vmcs);
8948 free_msrs:
8949         kfree(vmx->guest_msrs);
8950 free_pml:
8951         vmx_destroy_pml_buffer(vmx);
8952 uninit_vcpu:
8953         kvm_vcpu_uninit(&vmx->vcpu);
8954 free_vcpu:
8955         free_vpid(vmx->vpid);
8956         kmem_cache_free(kvm_vcpu_cache, vmx);
8957         return ERR_PTR(err);
8958 }
8959
8960 static void __init vmx_check_processor_compat(void *rtn)
8961 {
8962         struct vmcs_config vmcs_conf;
8963
8964         *(int *)rtn = 0;
8965         if (setup_vmcs_config(&vmcs_conf) < 0)
8966                 *(int *)rtn = -EIO;
8967         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8968                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8969                                 smp_processor_id());
8970                 *(int *)rtn = -EIO;
8971         }
8972 }
8973
8974 static int get_ept_level(void)
8975 {
8976         return VMX_EPT_DEFAULT_GAW + 1;
8977 }
8978
8979 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
8980 {
8981         u8 cache;
8982         u64 ipat = 0;
8983
8984         /* For VT-d and EPT combination
8985          * 1. MMIO: always map as UC
8986          * 2. EPT with VT-d:
8987          *   a. VT-d without snooping control feature: can't guarantee the
8988          *      result, try to trust guest.
8989          *   b. VT-d with snooping control feature: snooping control feature of
8990          *      VT-d engine can guarantee the cache correctness. Just set it
8991          *      to WB to keep consistent with host. So the same as item 3.
8992          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
8993          *    consistent with host MTRR
8994          */
8995         if (is_mmio) {
8996                 cache = MTRR_TYPE_UNCACHABLE;
8997                 goto exit;
8998         }
8999
9000         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
9001                 ipat = VMX_EPT_IPAT_BIT;
9002                 cache = MTRR_TYPE_WRBACK;
9003                 goto exit;
9004         }
9005
9006         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
9007                 ipat = VMX_EPT_IPAT_BIT;
9008                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
9009                         cache = MTRR_TYPE_WRBACK;
9010                 else
9011                         cache = MTRR_TYPE_UNCACHABLE;
9012                 goto exit;
9013         }
9014
9015         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
9016
9017 exit:
9018         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
9019 }
9020
9021 static int vmx_get_lpage_level(void)
9022 {
9023         if (enable_ept && !cpu_has_vmx_ept_1g_page())
9024                 return PT_DIRECTORY_LEVEL;
9025         else
9026                 /* For shadow and EPT supported 1GB page */
9027                 return PT_PDPE_LEVEL;
9028 }
9029
9030 static void vmcs_set_secondary_exec_control(u32 new_ctl)
9031 {
9032         /*
9033          * These bits in the secondary execution controls field
9034          * are dynamic, the others are mostly based on the hypervisor
9035          * architecture and the guest's CPUID.  Do not touch the
9036          * dynamic bits.
9037          */
9038         u32 mask =
9039                 SECONDARY_EXEC_SHADOW_VMCS |
9040                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9041                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9042
9043         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9044
9045         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9046                      (new_ctl & ~mask) | (cur_ctl & mask));
9047 }
9048
9049 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9050 {
9051         struct kvm_cpuid_entry2 *best;
9052         struct vcpu_vmx *vmx = to_vmx(vcpu);
9053         u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
9054
9055         if (vmx_rdtscp_supported()) {
9056                 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
9057                 if (!rdtscp_enabled)
9058                         secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
9059
9060                 if (nested) {
9061                         if (rdtscp_enabled)
9062                                 vmx->nested.nested_vmx_secondary_ctls_high |=
9063                                         SECONDARY_EXEC_RDTSCP;
9064                         else
9065                                 vmx->nested.nested_vmx_secondary_ctls_high &=
9066                                         ~SECONDARY_EXEC_RDTSCP;
9067                 }
9068         }
9069
9070         /* Exposing INVPCID only when PCID is exposed */
9071         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9072         if (vmx_invpcid_supported() &&
9073             (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
9074             !guest_cpuid_has_pcid(vcpu))) {
9075                 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
9076
9077                 if (best)
9078                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
9079         }
9080
9081         if (cpu_has_secondary_exec_ctrls())
9082                 vmcs_set_secondary_exec_control(secondary_exec_ctl);
9083 }
9084
9085 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9086 {
9087         if (func == 1 && nested)
9088                 entry->ecx |= bit(X86_FEATURE_VMX);
9089 }
9090
9091 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9092                 struct x86_exception *fault)
9093 {
9094         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9095         u32 exit_reason;
9096
9097         if (fault->error_code & PFERR_RSVD_MASK)
9098                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9099         else
9100                 exit_reason = EXIT_REASON_EPT_VIOLATION;
9101         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
9102         vmcs12->guest_physical_address = fault->address;
9103 }
9104
9105 /* Callbacks for nested_ept_init_mmu_context: */
9106
9107 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9108 {
9109         /* return the page table to be shadowed - in our case, EPT12 */
9110         return get_vmcs12(vcpu)->ept_pointer;
9111 }
9112
9113 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9114 {
9115         WARN_ON(mmu_is_nested(vcpu));
9116         kvm_init_shadow_ept_mmu(vcpu,
9117                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9118                         VMX_EPT_EXECUTE_ONLY_BIT);
9119         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
9120         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
9121         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9122
9123         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
9124 }
9125
9126 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9127 {
9128         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9129 }
9130
9131 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9132                                             u16 error_code)
9133 {
9134         bool inequality, bit;
9135
9136         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9137         inequality =
9138                 (error_code & vmcs12->page_fault_error_code_mask) !=
9139                  vmcs12->page_fault_error_code_match;
9140         return inequality ^ bit;
9141 }
9142
9143 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9144                 struct x86_exception *fault)
9145 {
9146         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9147
9148         WARN_ON(!is_guest_mode(vcpu));
9149
9150         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9151                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9152                                   vmcs_read32(VM_EXIT_INTR_INFO),
9153                                   vmcs_readl(EXIT_QUALIFICATION));
9154         else
9155                 kvm_inject_page_fault(vcpu, fault);
9156 }
9157
9158 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9159                                         struct vmcs12 *vmcs12)
9160 {
9161         struct vcpu_vmx *vmx = to_vmx(vcpu);
9162         int maxphyaddr = cpuid_maxphyaddr(vcpu);
9163
9164         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9165                 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
9166                     vmcs12->apic_access_addr >> maxphyaddr)
9167                         return false;
9168
9169                 /*
9170                  * Translate L1 physical address to host physical
9171                  * address for vmcs02. Keep the page pinned, so this
9172                  * physical address remains valid. We keep a reference
9173                  * to it so we can release it later.
9174                  */
9175                 if (vmx->nested.apic_access_page) /* shouldn't happen */
9176                         nested_release_page(vmx->nested.apic_access_page);
9177                 vmx->nested.apic_access_page =
9178                         nested_get_page(vcpu, vmcs12->apic_access_addr);
9179         }
9180
9181         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9182                 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
9183                     vmcs12->virtual_apic_page_addr >> maxphyaddr)
9184                         return false;
9185
9186                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9187                         nested_release_page(vmx->nested.virtual_apic_page);
9188                 vmx->nested.virtual_apic_page =
9189                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9190
9191                 /*
9192                  * Failing the vm entry is _not_ what the processor does
9193                  * but it's basically the only possibility we have.
9194                  * We could still enter the guest if CR8 load exits are
9195                  * enabled, CR8 store exits are enabled, and virtualize APIC
9196                  * access is disabled; in this case the processor would never
9197                  * use the TPR shadow and we could simply clear the bit from
9198                  * the execution control.  But such a configuration is useless,
9199                  * so let's keep the code simple.
9200                  */
9201                 if (!vmx->nested.virtual_apic_page)
9202                         return false;
9203         }
9204
9205         if (nested_cpu_has_posted_intr(vmcs12)) {
9206                 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
9207                     vmcs12->posted_intr_desc_addr >> maxphyaddr)
9208                         return false;
9209
9210                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9211                         kunmap(vmx->nested.pi_desc_page);
9212                         nested_release_page(vmx->nested.pi_desc_page);
9213                 }
9214                 vmx->nested.pi_desc_page =
9215                         nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9216                 if (!vmx->nested.pi_desc_page)
9217                         return false;
9218
9219                 vmx->nested.pi_desc =
9220                         (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9221                 if (!vmx->nested.pi_desc) {
9222                         nested_release_page_clean(vmx->nested.pi_desc_page);
9223                         return false;
9224                 }
9225                 vmx->nested.pi_desc =
9226                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
9227                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9228                         (PAGE_SIZE - 1)));
9229         }
9230
9231         return true;
9232 }
9233
9234 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9235 {
9236         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9237         struct vcpu_vmx *vmx = to_vmx(vcpu);
9238
9239         if (vcpu->arch.virtual_tsc_khz == 0)
9240                 return;
9241
9242         /* Make sure short timeouts reliably trigger an immediate vmexit.
9243          * hrtimer_start does not guarantee this. */
9244         if (preemption_timeout <= 1) {
9245                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9246                 return;
9247         }
9248
9249         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9250         preemption_timeout *= 1000000;
9251         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9252         hrtimer_start(&vmx->nested.preemption_timer,
9253                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9254 }
9255
9256 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9257                                                 struct vmcs12 *vmcs12)
9258 {
9259         int maxphyaddr;
9260         u64 addr;
9261
9262         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9263                 return 0;
9264
9265         if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9266                 WARN_ON(1);
9267                 return -EINVAL;
9268         }
9269         maxphyaddr = cpuid_maxphyaddr(vcpu);
9270
9271         if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9272            ((addr + PAGE_SIZE) >> maxphyaddr))
9273                 return -EINVAL;
9274
9275         return 0;
9276 }
9277
9278 /*
9279  * Merge L0's and L1's MSR bitmap, return false to indicate that
9280  * we do not use the hardware.
9281  */
9282 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9283                                                struct vmcs12 *vmcs12)
9284 {
9285         int msr;
9286         struct page *page;
9287         unsigned long *msr_bitmap;
9288
9289         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9290                 return false;
9291
9292         page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9293         if (!page) {
9294                 WARN_ON(1);
9295                 return false;
9296         }
9297         msr_bitmap = (unsigned long *)kmap(page);
9298         if (!msr_bitmap) {
9299                 nested_release_page_clean(page);
9300                 WARN_ON(1);
9301                 return false;
9302         }
9303
9304         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9305                 if (nested_cpu_has_apic_reg_virt(vmcs12))
9306                         for (msr = 0x800; msr <= 0x8ff; msr++)
9307                                 nested_vmx_disable_intercept_for_msr(
9308                                         msr_bitmap,
9309                                         vmx_msr_bitmap_nested,
9310                                         msr, MSR_TYPE_R);
9311                 /* TPR is allowed */
9312                 nested_vmx_disable_intercept_for_msr(msr_bitmap,
9313                                 vmx_msr_bitmap_nested,
9314                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9315                                 MSR_TYPE_R | MSR_TYPE_W);
9316                 if (nested_cpu_has_vid(vmcs12)) {
9317                         /* EOI and self-IPI are allowed */
9318                         nested_vmx_disable_intercept_for_msr(
9319                                 msr_bitmap,
9320                                 vmx_msr_bitmap_nested,
9321                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9322                                 MSR_TYPE_W);
9323                         nested_vmx_disable_intercept_for_msr(
9324                                 msr_bitmap,
9325                                 vmx_msr_bitmap_nested,
9326                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9327                                 MSR_TYPE_W);
9328                 }
9329         } else {
9330                 /*
9331                  * Enable reading intercept of all the x2apic
9332                  * MSRs. We should not rely on vmcs12 to do any
9333                  * optimizations here, it may have been modified
9334                  * by L1.
9335                  */
9336                 for (msr = 0x800; msr <= 0x8ff; msr++)
9337                         __vmx_enable_intercept_for_msr(
9338                                 vmx_msr_bitmap_nested,
9339                                 msr,
9340                                 MSR_TYPE_R);
9341
9342                 __vmx_enable_intercept_for_msr(
9343                                 vmx_msr_bitmap_nested,
9344                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9345                                 MSR_TYPE_W);
9346                 __vmx_enable_intercept_for_msr(
9347                                 vmx_msr_bitmap_nested,
9348                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9349                                 MSR_TYPE_W);
9350                 __vmx_enable_intercept_for_msr(
9351                                 vmx_msr_bitmap_nested,
9352                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9353                                 MSR_TYPE_W);
9354         }
9355         kunmap(page);
9356         nested_release_page_clean(page);
9357
9358         return true;
9359 }
9360
9361 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9362                                            struct vmcs12 *vmcs12)
9363 {
9364         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9365             !nested_cpu_has_apic_reg_virt(vmcs12) &&
9366             !nested_cpu_has_vid(vmcs12) &&
9367             !nested_cpu_has_posted_intr(vmcs12))
9368                 return 0;
9369
9370         /*
9371          * If virtualize x2apic mode is enabled,
9372          * virtualize apic access must be disabled.
9373          */
9374         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9375             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9376                 return -EINVAL;
9377
9378         /*
9379          * If virtual interrupt delivery is enabled,
9380          * we must exit on external interrupts.
9381          */
9382         if (nested_cpu_has_vid(vmcs12) &&
9383            !nested_exit_on_intr(vcpu))
9384                 return -EINVAL;
9385
9386         /*
9387          * bits 15:8 should be zero in posted_intr_nv,
9388          * the descriptor address has been already checked
9389          * in nested_get_vmcs12_pages.
9390          */
9391         if (nested_cpu_has_posted_intr(vmcs12) &&
9392            (!nested_cpu_has_vid(vmcs12) ||
9393             !nested_exit_intr_ack_set(vcpu) ||
9394             vmcs12->posted_intr_nv & 0xff00))
9395                 return -EINVAL;
9396
9397         /* tpr shadow is needed by all apicv features. */
9398         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9399                 return -EINVAL;
9400
9401         return 0;
9402 }
9403
9404 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9405                                        unsigned long count_field,
9406                                        unsigned long addr_field)
9407 {
9408         int maxphyaddr;
9409         u64 count, addr;
9410
9411         if (vmcs12_read_any(vcpu, count_field, &count) ||
9412             vmcs12_read_any(vcpu, addr_field, &addr)) {
9413                 WARN_ON(1);
9414                 return -EINVAL;
9415         }
9416         if (count == 0)
9417                 return 0;
9418         maxphyaddr = cpuid_maxphyaddr(vcpu);
9419         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9420             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9421                 pr_warn_ratelimited(
9422                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9423                         addr_field, maxphyaddr, count, addr);
9424                 return -EINVAL;
9425         }
9426         return 0;
9427 }
9428
9429 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9430                                                 struct vmcs12 *vmcs12)
9431 {
9432         if (vmcs12->vm_exit_msr_load_count == 0 &&
9433             vmcs12->vm_exit_msr_store_count == 0 &&
9434             vmcs12->vm_entry_msr_load_count == 0)
9435                 return 0; /* Fast path */
9436         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9437                                         VM_EXIT_MSR_LOAD_ADDR) ||
9438             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9439                                         VM_EXIT_MSR_STORE_ADDR) ||
9440             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9441                                         VM_ENTRY_MSR_LOAD_ADDR))
9442                 return -EINVAL;
9443         return 0;
9444 }
9445
9446 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9447                                        struct vmx_msr_entry *e)
9448 {
9449         /* x2APIC MSR accesses are not allowed */
9450         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9451                 return -EINVAL;
9452         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9453             e->index == MSR_IA32_UCODE_REV)
9454                 return -EINVAL;
9455         if (e->reserved != 0)
9456                 return -EINVAL;
9457         return 0;
9458 }
9459
9460 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9461                                      struct vmx_msr_entry *e)
9462 {
9463         if (e->index == MSR_FS_BASE ||
9464             e->index == MSR_GS_BASE ||
9465             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9466             nested_vmx_msr_check_common(vcpu, e))
9467                 return -EINVAL;
9468         return 0;
9469 }
9470
9471 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9472                                       struct vmx_msr_entry *e)
9473 {
9474         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9475             nested_vmx_msr_check_common(vcpu, e))
9476                 return -EINVAL;
9477         return 0;
9478 }
9479
9480 /*
9481  * Load guest's/host's msr at nested entry/exit.
9482  * return 0 for success, entry index for failure.
9483  */
9484 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9485 {
9486         u32 i;
9487         struct vmx_msr_entry e;
9488         struct msr_data msr;
9489
9490         msr.host_initiated = false;
9491         for (i = 0; i < count; i++) {
9492                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9493                                         &e, sizeof(e))) {
9494                         pr_warn_ratelimited(
9495                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9496                                 __func__, i, gpa + i * sizeof(e));
9497                         goto fail;
9498                 }
9499                 if (nested_vmx_load_msr_check(vcpu, &e)) {
9500                         pr_warn_ratelimited(
9501                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9502                                 __func__, i, e.index, e.reserved);
9503                         goto fail;
9504                 }
9505                 msr.index = e.index;
9506                 msr.data = e.value;
9507                 if (kvm_set_msr(vcpu, &msr)) {
9508                         pr_warn_ratelimited(
9509                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9510                                 __func__, i, e.index, e.value);
9511                         goto fail;
9512                 }
9513         }
9514         return 0;
9515 fail:
9516         return i + 1;
9517 }
9518
9519 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9520 {
9521         u32 i;
9522         struct vmx_msr_entry e;
9523
9524         for (i = 0; i < count; i++) {
9525                 struct msr_data msr_info;
9526                 if (kvm_vcpu_read_guest(vcpu,
9527                                         gpa + i * sizeof(e),
9528                                         &e, 2 * sizeof(u32))) {
9529                         pr_warn_ratelimited(
9530                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9531                                 __func__, i, gpa + i * sizeof(e));
9532                         return -EINVAL;
9533                 }
9534                 if (nested_vmx_store_msr_check(vcpu, &e)) {
9535                         pr_warn_ratelimited(
9536                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9537                                 __func__, i, e.index, e.reserved);
9538                         return -EINVAL;
9539                 }
9540                 msr_info.host_initiated = false;
9541                 msr_info.index = e.index;
9542                 if (kvm_get_msr(vcpu, &msr_info)) {
9543                         pr_warn_ratelimited(
9544                                 "%s cannot read MSR (%u, 0x%x)\n",
9545                                 __func__, i, e.index);
9546                         return -EINVAL;
9547                 }
9548                 if (kvm_vcpu_write_guest(vcpu,
9549                                          gpa + i * sizeof(e) +
9550                                              offsetof(struct vmx_msr_entry, value),
9551                                          &msr_info.data, sizeof(msr_info.data))) {
9552                         pr_warn_ratelimited(
9553                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9554                                 __func__, i, e.index, msr_info.data);
9555                         return -EINVAL;
9556                 }
9557         }
9558         return 0;
9559 }
9560
9561 /*
9562  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9563  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9564  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9565  * guest in a way that will both be appropriate to L1's requests, and our
9566  * needs. In addition to modifying the active vmcs (which is vmcs02), this
9567  * function also has additional necessary side-effects, like setting various
9568  * vcpu->arch fields.
9569  */
9570 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9571 {
9572         struct vcpu_vmx *vmx = to_vmx(vcpu);
9573         u32 exec_control;
9574
9575         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9576         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9577         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9578         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9579         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9580         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9581         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9582         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9583         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9584         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9585         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9586         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9587         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9588         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9589         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9590         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9591         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9592         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9593         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9594         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9595         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9596         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9597         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9598         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9599         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9600         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9601         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9602         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9603         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9604         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9605         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9606         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9607         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9608         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9609         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9610         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9611
9612         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9613                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9614                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9615         } else {
9616                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9617                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9618         }
9619         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9620                 vmcs12->vm_entry_intr_info_field);
9621         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9622                 vmcs12->vm_entry_exception_error_code);
9623         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9624                 vmcs12->vm_entry_instruction_len);
9625         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9626                 vmcs12->guest_interruptibility_info);
9627         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
9628         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
9629         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9630                 vmcs12->guest_pending_dbg_exceptions);
9631         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9632         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9633
9634         if (nested_cpu_has_xsaves(vmcs12))
9635                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
9636         vmcs_write64(VMCS_LINK_POINTER, -1ull);
9637
9638         exec_control = vmcs12->pin_based_vm_exec_control;
9639         exec_control |= vmcs_config.pin_based_exec_ctrl;
9640         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9641
9642         if (nested_cpu_has_posted_intr(vmcs12)) {
9643                 /*
9644                  * Note that we use L0's vector here and in
9645                  * vmx_deliver_nested_posted_interrupt.
9646                  */
9647                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9648                 vmx->nested.pi_pending = false;
9649                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9650                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9651                         page_to_phys(vmx->nested.pi_desc_page) +
9652                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9653                         (PAGE_SIZE - 1)));
9654         } else
9655                 exec_control &= ~PIN_BASED_POSTED_INTR;
9656
9657         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
9658
9659         vmx->nested.preemption_timer_expired = false;
9660         if (nested_cpu_has_preemption_timer(vmcs12))
9661                 vmx_start_preemption_timer(vcpu);
9662
9663         /*
9664          * Whether page-faults are trapped is determined by a combination of
9665          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9666          * If enable_ept, L0 doesn't care about page faults and we should
9667          * set all of these to L1's desires. However, if !enable_ept, L0 does
9668          * care about (at least some) page faults, and because it is not easy
9669          * (if at all possible?) to merge L0 and L1's desires, we simply ask
9670          * to exit on each and every L2 page fault. This is done by setting
9671          * MASK=MATCH=0 and (see below) EB.PF=1.
9672          * Note that below we don't need special code to set EB.PF beyond the
9673          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9674          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9675          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9676          *
9677          * A problem with this approach (when !enable_ept) is that L1 may be
9678          * injected with more page faults than it asked for. This could have
9679          * caused problems, but in practice existing hypervisors don't care.
9680          * To fix this, we will need to emulate the PFEC checking (on the L1
9681          * page tables), using walk_addr(), when injecting PFs to L1.
9682          */
9683         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9684                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9685         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9686                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9687
9688         if (cpu_has_secondary_exec_ctrls()) {
9689                 exec_control = vmx_secondary_exec_control(vmx);
9690
9691                 /* Take the following fields only from vmcs12 */
9692                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9693                                   SECONDARY_EXEC_RDTSCP |
9694                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
9695                                   SECONDARY_EXEC_APIC_REGISTER_VIRT);
9696                 if (nested_cpu_has(vmcs12,
9697                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9698                         exec_control |= vmcs12->secondary_vm_exec_control;
9699
9700                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
9701                         /*
9702                          * If translation failed, no matter: This feature asks
9703                          * to exit when accessing the given address, and if it
9704                          * can never be accessed, this feature won't do
9705                          * anything anyway.
9706                          */
9707                         if (!vmx->nested.apic_access_page)
9708                                 exec_control &=
9709                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9710                         else
9711                                 vmcs_write64(APIC_ACCESS_ADDR,
9712                                   page_to_phys(vmx->nested.apic_access_page));
9713                 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9714                             cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9715                         exec_control |=
9716                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9717                         kvm_vcpu_reload_apic_access_page(vcpu);
9718                 }
9719
9720                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9721                         vmcs_write64(EOI_EXIT_BITMAP0,
9722                                 vmcs12->eoi_exit_bitmap0);
9723                         vmcs_write64(EOI_EXIT_BITMAP1,
9724                                 vmcs12->eoi_exit_bitmap1);
9725                         vmcs_write64(EOI_EXIT_BITMAP2,
9726                                 vmcs12->eoi_exit_bitmap2);
9727                         vmcs_write64(EOI_EXIT_BITMAP3,
9728                                 vmcs12->eoi_exit_bitmap3);
9729                         vmcs_write16(GUEST_INTR_STATUS,
9730                                 vmcs12->guest_intr_status);
9731                 }
9732
9733                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9734         }
9735
9736
9737         /*
9738          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9739          * Some constant fields are set here by vmx_set_constant_host_state().
9740          * Other fields are different per CPU, and will be set later when
9741          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9742          */
9743         vmx_set_constant_host_state(vmx);
9744
9745         /*
9746          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9747          * entry, but only if the current (host) sp changed from the value
9748          * we wrote last (vmx->host_rsp). This cache is no longer relevant
9749          * if we switch vmcs, and rather than hold a separate cache per vmcs,
9750          * here we just force the write to happen on entry.
9751          */
9752         vmx->host_rsp = 0;
9753
9754         exec_control = vmx_exec_control(vmx); /* L0's desires */
9755         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9756         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9757         exec_control &= ~CPU_BASED_TPR_SHADOW;
9758         exec_control |= vmcs12->cpu_based_vm_exec_control;
9759
9760         if (exec_control & CPU_BASED_TPR_SHADOW) {
9761                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9762                                 page_to_phys(vmx->nested.virtual_apic_page));
9763                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9764         }
9765
9766         if (cpu_has_vmx_msr_bitmap() &&
9767             exec_control & CPU_BASED_USE_MSR_BITMAPS) {
9768                 nested_vmx_merge_msr_bitmap(vcpu, vmcs12);
9769                 /* MSR_BITMAP will be set by following vmx_set_efer. */
9770         } else
9771                 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9772
9773         /*
9774          * Merging of IO bitmap not currently supported.
9775          * Rather, exit every time.
9776          */
9777         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9778         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9779
9780         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9781
9782         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9783          * bitwise-or of what L1 wants to trap for L2, and what we want to
9784          * trap. Note that CR0.TS also needs updating - we do this later.
9785          */
9786         update_exception_bitmap(vcpu);
9787         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9788         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9789
9790         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9791          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9792          * bits are further modified by vmx_set_efer() below.
9793          */
9794         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
9795
9796         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9797          * emulated by vmx_set_efer(), below.
9798          */
9799         vm_entry_controls_init(vmx,
9800                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9801                         ~VM_ENTRY_IA32E_MODE) |
9802                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9803
9804         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
9805                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
9806                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9807         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
9808                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9809
9810
9811         set_cr4_guest_host_mask(vmx);
9812
9813         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9814                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9815
9816         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9817                 vmcs_write64(TSC_OFFSET,
9818                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9819         else
9820                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
9821
9822         if (enable_vpid) {
9823                 /*
9824                  * There is no direct mapping between vpid02 and vpid12, the
9825                  * vpid02 is per-vCPU for L0 and reused while the value of
9826                  * vpid12 is changed w/ one invvpid during nested vmentry.
9827                  * The vpid12 is allocated by L1 for L2, so it will not
9828                  * influence global bitmap(for vpid01 and vpid02 allocation)
9829                  * even if spawn a lot of nested vCPUs.
9830                  */
9831                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
9832                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
9833                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
9834                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
9835                                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
9836                         }
9837                 } else {
9838                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9839                         vmx_flush_tlb(vcpu);
9840                 }
9841
9842         }
9843
9844         if (nested_cpu_has_ept(vmcs12)) {
9845                 kvm_mmu_unload(vcpu);
9846                 nested_ept_init_mmu_context(vcpu);
9847         }
9848
9849         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9850                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
9851         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
9852                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9853         else
9854                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9855         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9856         vmx_set_efer(vcpu, vcpu->arch.efer);
9857
9858         /*
9859          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9860          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9861          * The CR0_READ_SHADOW is what L2 should have expected to read given
9862          * the specifications by L1; It's not enough to take
9863          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9864          * have more bits than L1 expected.
9865          */
9866         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9867         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9868
9869         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9870         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9871
9872         /* shadow page tables on either EPT or shadow page tables */
9873         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9874         kvm_mmu_reset_context(vcpu);
9875
9876         if (!enable_ept)
9877                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
9878
9879         /*
9880          * L1 may access the L2's PDPTR, so save them to construct vmcs12
9881          */
9882         if (enable_ept) {
9883                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
9884                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
9885                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
9886                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
9887         }
9888
9889         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
9890         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
9891 }
9892
9893 /*
9894  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9895  * for running an L2 nested guest.
9896  */
9897 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
9898 {
9899         struct vmcs12 *vmcs12;
9900         struct vcpu_vmx *vmx = to_vmx(vcpu);
9901         int cpu;
9902         struct loaded_vmcs *vmcs02;
9903         bool ia32e;
9904         u32 msr_entry_idx;
9905
9906         if (!nested_vmx_check_permission(vcpu) ||
9907             !nested_vmx_check_vmcs12(vcpu))
9908                 return 1;
9909
9910         skip_emulated_instruction(vcpu);
9911         vmcs12 = get_vmcs12(vcpu);
9912
9913         if (enable_shadow_vmcs)
9914                 copy_shadow_to_vmcs12(vmx);
9915
9916         /*
9917          * The nested entry process starts with enforcing various prerequisites
9918          * on vmcs12 as required by the Intel SDM, and act appropriately when
9919          * they fail: As the SDM explains, some conditions should cause the
9920          * instruction to fail, while others will cause the instruction to seem
9921          * to succeed, but return an EXIT_REASON_INVALID_STATE.
9922          * To speed up the normal (success) code path, we should avoid checking
9923          * for misconfigurations which will anyway be caught by the processor
9924          * when using the merged vmcs02.
9925          */
9926         if (vmcs12->launch_state == launch) {
9927                 nested_vmx_failValid(vcpu,
9928                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9929                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
9930                 return 1;
9931         }
9932
9933         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
9934             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
9935                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9936                 return 1;
9937         }
9938
9939         if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
9940                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9941                 return 1;
9942         }
9943
9944         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
9945                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9946                 return 1;
9947         }
9948
9949         if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
9950                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9951                 return 1;
9952         }
9953
9954         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
9955                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9956                 return 1;
9957         }
9958
9959         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
9960                                 vmx->nested.nested_vmx_true_procbased_ctls_low,
9961                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
9962             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
9963                                 vmx->nested.nested_vmx_secondary_ctls_low,
9964                                 vmx->nested.nested_vmx_secondary_ctls_high) ||
9965             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
9966                                 vmx->nested.nested_vmx_pinbased_ctls_low,
9967                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
9968             !vmx_control_verify(vmcs12->vm_exit_controls,
9969                                 vmx->nested.nested_vmx_true_exit_ctls_low,
9970                                 vmx->nested.nested_vmx_exit_ctls_high) ||
9971             !vmx_control_verify(vmcs12->vm_entry_controls,
9972                                 vmx->nested.nested_vmx_true_entry_ctls_low,
9973                                 vmx->nested.nested_vmx_entry_ctls_high))
9974         {
9975                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9976                 return 1;
9977         }
9978
9979         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
9980             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9981                 nested_vmx_failValid(vcpu,
9982                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
9983                 return 1;
9984         }
9985
9986         if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
9987             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9988                 nested_vmx_entry_failure(vcpu, vmcs12,
9989                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9990                 return 1;
9991         }
9992         if (vmcs12->vmcs_link_pointer != -1ull) {
9993                 nested_vmx_entry_failure(vcpu, vmcs12,
9994                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
9995                 return 1;
9996         }
9997
9998         /*
9999          * If the load IA32_EFER VM-entry control is 1, the following checks
10000          * are performed on the field for the IA32_EFER MSR:
10001          * - Bits reserved in the IA32_EFER MSR must be 0.
10002          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10003          *   the IA-32e mode guest VM-exit control. It must also be identical
10004          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10005          *   CR0.PG) is 1.
10006          */
10007         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
10008                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
10009                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
10010                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
10011                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
10012                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
10013                         nested_vmx_entry_failure(vcpu, vmcs12,
10014                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
10015                         return 1;
10016                 }
10017         }
10018
10019         /*
10020          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10021          * IA32_EFER MSR must be 0 in the field for that register. In addition,
10022          * the values of the LMA and LME bits in the field must each be that of
10023          * the host address-space size VM-exit control.
10024          */
10025         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
10026                 ia32e = (vmcs12->vm_exit_controls &
10027                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
10028                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
10029                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
10030                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
10031                         nested_vmx_entry_failure(vcpu, vmcs12,
10032                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
10033                         return 1;
10034                 }
10035         }
10036
10037         /*
10038          * We're finally done with prerequisite checking, and can start with
10039          * the nested entry.
10040          */
10041
10042         vmcs02 = nested_get_current_vmcs02(vmx);
10043         if (!vmcs02)
10044                 return -ENOMEM;
10045
10046         enter_guest_mode(vcpu);
10047
10048         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
10049
10050         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
10051                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10052
10053         cpu = get_cpu();
10054         vmx->loaded_vmcs = vmcs02;
10055         vmx_vcpu_put(vcpu);
10056         vmx_vcpu_load(vcpu, cpu);
10057         vcpu->cpu = cpu;
10058         put_cpu();
10059
10060         vmx_segment_cache_clear(vmx);
10061
10062         prepare_vmcs02(vcpu, vmcs12);
10063
10064         msr_entry_idx = nested_vmx_load_msr(vcpu,
10065                                             vmcs12->vm_entry_msr_load_addr,
10066                                             vmcs12->vm_entry_msr_load_count);
10067         if (msr_entry_idx) {
10068                 leave_guest_mode(vcpu);
10069                 vmx_load_vmcs01(vcpu);
10070                 nested_vmx_entry_failure(vcpu, vmcs12,
10071                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10072                 return 1;
10073         }
10074
10075         vmcs12->launch_state = 1;
10076
10077         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
10078                 return kvm_vcpu_halt(vcpu);
10079
10080         vmx->nested.nested_run_pending = 1;
10081
10082         /*
10083          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10084          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10085          * returned as far as L1 is concerned. It will only return (and set
10086          * the success flag) when L2 exits (see nested_vmx_vmexit()).
10087          */
10088         return 1;
10089 }
10090
10091 /*
10092  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10093  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10094  * This function returns the new value we should put in vmcs12.guest_cr0.
10095  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10096  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10097  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10098  *     didn't trap the bit, because if L1 did, so would L0).
10099  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10100  *     been modified by L2, and L1 knows it. So just leave the old value of
10101  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10102  *     isn't relevant, because if L0 traps this bit it can set it to anything.
10103  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10104  *     changed these bits, and therefore they need to be updated, but L0
10105  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10106  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10107  */
10108 static inline unsigned long
10109 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10110 {
10111         return
10112         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10113         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10114         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10115                         vcpu->arch.cr0_guest_owned_bits));
10116 }
10117
10118 static inline unsigned long
10119 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10120 {
10121         return
10122         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10123         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10124         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10125                         vcpu->arch.cr4_guest_owned_bits));
10126 }
10127
10128 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10129                                        struct vmcs12 *vmcs12)
10130 {
10131         u32 idt_vectoring;
10132         unsigned int nr;
10133
10134         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10135                 nr = vcpu->arch.exception.nr;
10136                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10137
10138                 if (kvm_exception_is_soft(nr)) {
10139                         vmcs12->vm_exit_instruction_len =
10140                                 vcpu->arch.event_exit_inst_len;
10141                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10142                 } else
10143                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10144
10145                 if (vcpu->arch.exception.has_error_code) {
10146                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10147                         vmcs12->idt_vectoring_error_code =
10148                                 vcpu->arch.exception.error_code;
10149                 }
10150
10151                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10152         } else if (vcpu->arch.nmi_injected) {
10153                 vmcs12->idt_vectoring_info_field =
10154                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10155         } else if (vcpu->arch.interrupt.pending) {
10156                 nr = vcpu->arch.interrupt.nr;
10157                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10158
10159                 if (vcpu->arch.interrupt.soft) {
10160                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
10161                         vmcs12->vm_entry_instruction_len =
10162                                 vcpu->arch.event_exit_inst_len;
10163                 } else
10164                         idt_vectoring |= INTR_TYPE_EXT_INTR;
10165
10166                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10167         }
10168 }
10169
10170 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10171 {
10172         struct vcpu_vmx *vmx = to_vmx(vcpu);
10173
10174         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10175             vmx->nested.preemption_timer_expired) {
10176                 if (vmx->nested.nested_run_pending)
10177                         return -EBUSY;
10178                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10179                 return 0;
10180         }
10181
10182         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10183                 if (vmx->nested.nested_run_pending ||
10184                     vcpu->arch.interrupt.pending)
10185                         return -EBUSY;
10186                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10187                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
10188                                   INTR_INFO_VALID_MASK, 0);
10189                 /*
10190                  * The NMI-triggered VM exit counts as injection:
10191                  * clear this one and block further NMIs.
10192                  */
10193                 vcpu->arch.nmi_pending = 0;
10194                 vmx_set_nmi_mask(vcpu, true);
10195                 return 0;
10196         }
10197
10198         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10199             nested_exit_on_intr(vcpu)) {
10200                 if (vmx->nested.nested_run_pending)
10201                         return -EBUSY;
10202                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10203                 return 0;
10204         }
10205
10206         return vmx_complete_nested_posted_interrupt(vcpu);
10207 }
10208
10209 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10210 {
10211         ktime_t remaining =
10212                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10213         u64 value;
10214
10215         if (ktime_to_ns(remaining) <= 0)
10216                 return 0;
10217
10218         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10219         do_div(value, 1000000);
10220         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10221 }
10222
10223 /*
10224  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10225  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10226  * and this function updates it to reflect the changes to the guest state while
10227  * L2 was running (and perhaps made some exits which were handled directly by L0
10228  * without going back to L1), and to reflect the exit reason.
10229  * Note that we do not have to copy here all VMCS fields, just those that
10230  * could have changed by the L2 guest or the exit - i.e., the guest-state and
10231  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10232  * which already writes to vmcs12 directly.
10233  */
10234 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10235                            u32 exit_reason, u32 exit_intr_info,
10236                            unsigned long exit_qualification)
10237 {
10238         /* update guest state fields: */
10239         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10240         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10241
10242         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10243         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10244         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10245
10246         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10247         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10248         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10249         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10250         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10251         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10252         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10253         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10254         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10255         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10256         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10257         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10258         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10259         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10260         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10261         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10262         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10263         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10264         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10265         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10266         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10267         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10268         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10269         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10270         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10271         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10272         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10273         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10274         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10275         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10276         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10277         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10278         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10279         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10280         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10281         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10282
10283         vmcs12->guest_interruptibility_info =
10284                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10285         vmcs12->guest_pending_dbg_exceptions =
10286                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10287         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10288                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10289         else
10290                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10291
10292         if (nested_cpu_has_preemption_timer(vmcs12)) {
10293                 if (vmcs12->vm_exit_controls &
10294                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10295                         vmcs12->vmx_preemption_timer_value =
10296                                 vmx_get_preemption_timer_value(vcpu);
10297                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10298         }
10299
10300         /*
10301          * In some cases (usually, nested EPT), L2 is allowed to change its
10302          * own CR3 without exiting. If it has changed it, we must keep it.
10303          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10304          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10305          *
10306          * Additionally, restore L2's PDPTR to vmcs12.
10307          */
10308         if (enable_ept) {
10309                 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
10310                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10311                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10312                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10313                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10314         }
10315
10316         if (nested_cpu_has_vid(vmcs12))
10317                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10318
10319         vmcs12->vm_entry_controls =
10320                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10321                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10322
10323         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10324                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10325                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10326         }
10327
10328         /* TODO: These cannot have changed unless we have MSR bitmaps and
10329          * the relevant bit asks not to trap the change */
10330         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10331                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10332         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10333                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10334         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10335         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10336         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10337         if (kvm_mpx_supported())
10338                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10339         if (nested_cpu_has_xsaves(vmcs12))
10340                 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
10341
10342         /* update exit information fields: */
10343
10344         vmcs12->vm_exit_reason = exit_reason;
10345         vmcs12->exit_qualification = exit_qualification;
10346
10347         vmcs12->vm_exit_intr_info = exit_intr_info;
10348         if ((vmcs12->vm_exit_intr_info &
10349              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10350             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10351                 vmcs12->vm_exit_intr_error_code =
10352                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10353         vmcs12->idt_vectoring_info_field = 0;
10354         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10355         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10356
10357         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10358                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10359                  * instead of reading the real value. */
10360                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10361
10362                 /*
10363                  * Transfer the event that L0 or L1 may wanted to inject into
10364                  * L2 to IDT_VECTORING_INFO_FIELD.
10365                  */
10366                 vmcs12_save_pending_event(vcpu, vmcs12);
10367         }
10368
10369         /*
10370          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10371          * preserved above and would only end up incorrectly in L1.
10372          */
10373         vcpu->arch.nmi_injected = false;
10374         kvm_clear_exception_queue(vcpu);
10375         kvm_clear_interrupt_queue(vcpu);
10376 }
10377
10378 /*
10379  * A part of what we need to when the nested L2 guest exits and we want to
10380  * run its L1 parent, is to reset L1's guest state to the host state specified
10381  * in vmcs12.
10382  * This function is to be called not only on normal nested exit, but also on
10383  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10384  * Failures During or After Loading Guest State").
10385  * This function should be called when the active VMCS is L1's (vmcs01).
10386  */
10387 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10388                                    struct vmcs12 *vmcs12)
10389 {
10390         struct kvm_segment seg;
10391
10392         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10393                 vcpu->arch.efer = vmcs12->host_ia32_efer;
10394         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10395                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10396         else
10397                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10398         vmx_set_efer(vcpu, vcpu->arch.efer);
10399
10400         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10401         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10402         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10403         /*
10404          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10405          * actually changed, because it depends on the current state of
10406          * fpu_active (which may have changed).
10407          * Note that vmx_set_cr0 refers to efer set above.
10408          */
10409         vmx_set_cr0(vcpu, vmcs12->host_cr0);
10410         /*
10411          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10412          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10413          * but we also need to update cr0_guest_host_mask and exception_bitmap.
10414          */
10415         update_exception_bitmap(vcpu);
10416         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
10417         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10418
10419         /*
10420          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10421          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10422          */
10423         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10424         kvm_set_cr4(vcpu, vmcs12->host_cr4);
10425
10426         nested_ept_uninit_mmu_context(vcpu);
10427
10428         kvm_set_cr3(vcpu, vmcs12->host_cr3);
10429         kvm_mmu_reset_context(vcpu);
10430
10431         if (!enable_ept)
10432                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10433
10434         if (enable_vpid) {
10435                 /*
10436                  * Trivially support vpid by letting L2s share their parent
10437                  * L1's vpid. TODO: move to a more elaborate solution, giving
10438                  * each L2 its own vpid and exposing the vpid feature to L1.
10439                  */
10440                 vmx_flush_tlb(vcpu);
10441         }
10442
10443
10444         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10445         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10446         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10447         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10448         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10449
10450         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
10451         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10452                 vmcs_write64(GUEST_BNDCFGS, 0);
10453
10454         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10455                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10456                 vcpu->arch.pat = vmcs12->host_ia32_pat;
10457         }
10458         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10459                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10460                         vmcs12->host_ia32_perf_global_ctrl);
10461
10462         /* Set L1 segment info according to Intel SDM
10463             27.5.2 Loading Host Segment and Descriptor-Table Registers */
10464         seg = (struct kvm_segment) {
10465                 .base = 0,
10466                 .limit = 0xFFFFFFFF,
10467                 .selector = vmcs12->host_cs_selector,
10468                 .type = 11,
10469                 .present = 1,
10470                 .s = 1,
10471                 .g = 1
10472         };
10473         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10474                 seg.l = 1;
10475         else
10476                 seg.db = 1;
10477         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10478         seg = (struct kvm_segment) {
10479                 .base = 0,
10480                 .limit = 0xFFFFFFFF,
10481                 .type = 3,
10482                 .present = 1,
10483                 .s = 1,
10484                 .db = 1,
10485                 .g = 1
10486         };
10487         seg.selector = vmcs12->host_ds_selector;
10488         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10489         seg.selector = vmcs12->host_es_selector;
10490         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10491         seg.selector = vmcs12->host_ss_selector;
10492         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10493         seg.selector = vmcs12->host_fs_selector;
10494         seg.base = vmcs12->host_fs_base;
10495         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10496         seg.selector = vmcs12->host_gs_selector;
10497         seg.base = vmcs12->host_gs_base;
10498         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10499         seg = (struct kvm_segment) {
10500                 .base = vmcs12->host_tr_base,
10501                 .limit = 0x67,
10502                 .selector = vmcs12->host_tr_selector,
10503                 .type = 11,
10504                 .present = 1
10505         };
10506         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10507
10508         kvm_set_dr(vcpu, 7, 0x400);
10509         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
10510
10511         if (cpu_has_vmx_msr_bitmap())
10512                 vmx_set_msr_bitmap(vcpu);
10513
10514         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10515                                 vmcs12->vm_exit_msr_load_count))
10516                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
10517 }
10518
10519 /*
10520  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10521  * and modify vmcs12 to make it see what it would expect to see there if
10522  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10523  */
10524 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10525                               u32 exit_intr_info,
10526                               unsigned long exit_qualification)
10527 {
10528         struct vcpu_vmx *vmx = to_vmx(vcpu);
10529         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10530
10531         /* trying to cancel vmlaunch/vmresume is a bug */
10532         WARN_ON_ONCE(vmx->nested.nested_run_pending);
10533
10534         leave_guest_mode(vcpu);
10535         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10536                        exit_qualification);
10537
10538         if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10539                                  vmcs12->vm_exit_msr_store_count))
10540                 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10541
10542         vmx_load_vmcs01(vcpu);
10543
10544         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10545             && nested_exit_intr_ack_set(vcpu)) {
10546                 int irq = kvm_cpu_get_interrupt(vcpu);
10547                 WARN_ON(irq < 0);
10548                 vmcs12->vm_exit_intr_info = irq |
10549                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10550         }
10551
10552         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10553                                        vmcs12->exit_qualification,
10554                                        vmcs12->idt_vectoring_info_field,
10555                                        vmcs12->vm_exit_intr_info,
10556                                        vmcs12->vm_exit_intr_error_code,
10557                                        KVM_ISA_VMX);
10558
10559         vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
10560         vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
10561         vmx_segment_cache_clear(vmx);
10562
10563         /* if no vmcs02 cache requested, remove the one we used */
10564         if (VMCS02_POOL_SIZE == 0)
10565                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10566
10567         load_vmcs12_host_state(vcpu, vmcs12);
10568
10569         /* Update TSC_OFFSET if TSC was changed while L2 ran */
10570         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10571
10572         /* This is needed for same reason as it was needed in prepare_vmcs02 */
10573         vmx->host_rsp = 0;
10574
10575         /* Unpin physical memory we referred to in vmcs02 */
10576         if (vmx->nested.apic_access_page) {
10577                 nested_release_page(vmx->nested.apic_access_page);
10578                 vmx->nested.apic_access_page = NULL;
10579         }
10580         if (vmx->nested.virtual_apic_page) {
10581                 nested_release_page(vmx->nested.virtual_apic_page);
10582                 vmx->nested.virtual_apic_page = NULL;
10583         }
10584         if (vmx->nested.pi_desc_page) {
10585                 kunmap(vmx->nested.pi_desc_page);
10586                 nested_release_page(vmx->nested.pi_desc_page);
10587                 vmx->nested.pi_desc_page = NULL;
10588                 vmx->nested.pi_desc = NULL;
10589         }
10590
10591         /*
10592          * We are now running in L2, mmu_notifier will force to reload the
10593          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10594          */
10595         kvm_vcpu_reload_apic_access_page(vcpu);
10596
10597         /*
10598          * Exiting from L2 to L1, we're now back to L1 which thinks it just
10599          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10600          * success or failure flag accordingly.
10601          */
10602         if (unlikely(vmx->fail)) {
10603                 vmx->fail = 0;
10604                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10605         } else
10606                 nested_vmx_succeed(vcpu);
10607         if (enable_shadow_vmcs)
10608                 vmx->nested.sync_shadow_vmcs = true;
10609
10610         /* in case we halted in L2 */
10611         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10612 }
10613
10614 /*
10615  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10616  */
10617 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10618 {
10619         if (is_guest_mode(vcpu))
10620                 nested_vmx_vmexit(vcpu, -1, 0, 0);
10621         free_nested(to_vmx(vcpu));
10622 }
10623
10624 /*
10625  * L1's failure to enter L2 is a subset of a normal exit, as explained in
10626  * 23.7 "VM-entry failures during or after loading guest state" (this also
10627  * lists the acceptable exit-reason and exit-qualification parameters).
10628  * It should only be called before L2 actually succeeded to run, and when
10629  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10630  */
10631 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10632                         struct vmcs12 *vmcs12,
10633                         u32 reason, unsigned long qualification)
10634 {
10635         load_vmcs12_host_state(vcpu, vmcs12);
10636         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10637         vmcs12->exit_qualification = qualification;
10638         nested_vmx_succeed(vcpu);
10639         if (enable_shadow_vmcs)
10640                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
10641 }
10642
10643 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10644                                struct x86_instruction_info *info,
10645                                enum x86_intercept_stage stage)
10646 {
10647         return X86EMUL_CONTINUE;
10648 }
10649
10650 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
10651 {
10652         if (ple_gap)
10653                 shrink_ple_window(vcpu);
10654 }
10655
10656 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10657                                      struct kvm_memory_slot *slot)
10658 {
10659         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10660         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10661 }
10662
10663 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10664                                        struct kvm_memory_slot *slot)
10665 {
10666         kvm_mmu_slot_set_dirty(kvm, slot);
10667 }
10668
10669 static void vmx_flush_log_dirty(struct kvm *kvm)
10670 {
10671         kvm_flush_pml_buffers(kvm);
10672 }
10673
10674 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10675                                            struct kvm_memory_slot *memslot,
10676                                            gfn_t offset, unsigned long mask)
10677 {
10678         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10679 }
10680
10681 /*
10682  * This routine does the following things for vCPU which is going
10683  * to be blocked if VT-d PI is enabled.
10684  * - Store the vCPU to the wakeup list, so when interrupts happen
10685  *   we can find the right vCPU to wake up.
10686  * - Change the Posted-interrupt descriptor as below:
10687  *      'NDST' <-- vcpu->pre_pcpu
10688  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
10689  * - If 'ON' is set during this process, which means at least one
10690  *   interrupt is posted for this vCPU, we cannot block it, in
10691  *   this case, return 1, otherwise, return 0.
10692  *
10693  */
10694 static int vmx_pre_block(struct kvm_vcpu *vcpu)
10695 {
10696         unsigned long flags;
10697         unsigned int dest;
10698         struct pi_desc old, new;
10699         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10700
10701         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10702                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
10703                 !kvm_vcpu_apicv_active(vcpu))
10704                 return 0;
10705
10706         vcpu->pre_pcpu = vcpu->cpu;
10707         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10708                           vcpu->pre_pcpu), flags);
10709         list_add_tail(&vcpu->blocked_vcpu_list,
10710                       &per_cpu(blocked_vcpu_on_cpu,
10711                       vcpu->pre_pcpu));
10712         spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
10713                                vcpu->pre_pcpu), flags);
10714
10715         do {
10716                 old.control = new.control = pi_desc->control;
10717
10718                 /*
10719                  * We should not block the vCPU if
10720                  * an interrupt is posted for it.
10721                  */
10722                 if (pi_test_on(pi_desc) == 1) {
10723                         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10724                                           vcpu->pre_pcpu), flags);
10725                         list_del(&vcpu->blocked_vcpu_list);
10726                         spin_unlock_irqrestore(
10727                                         &per_cpu(blocked_vcpu_on_cpu_lock,
10728                                         vcpu->pre_pcpu), flags);
10729                         vcpu->pre_pcpu = -1;
10730
10731                         return 1;
10732                 }
10733
10734                 WARN((pi_desc->sn == 1),
10735                      "Warning: SN field of posted-interrupts "
10736                      "is set before blocking\n");
10737
10738                 /*
10739                  * Since vCPU can be preempted during this process,
10740                  * vcpu->cpu could be different with pre_pcpu, we
10741                  * need to set pre_pcpu as the destination of wakeup
10742                  * notification event, then we can find the right vCPU
10743                  * to wakeup in wakeup handler if interrupts happen
10744                  * when the vCPU is in blocked state.
10745                  */
10746                 dest = cpu_physical_id(vcpu->pre_pcpu);
10747
10748                 if (x2apic_enabled())
10749                         new.ndst = dest;
10750                 else
10751                         new.ndst = (dest << 8) & 0xFF00;
10752
10753                 /* set 'NV' to 'wakeup vector' */
10754                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
10755         } while (cmpxchg(&pi_desc->control, old.control,
10756                         new.control) != old.control);
10757
10758         return 0;
10759 }
10760
10761 static void vmx_post_block(struct kvm_vcpu *vcpu)
10762 {
10763         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10764         struct pi_desc old, new;
10765         unsigned int dest;
10766         unsigned long flags;
10767
10768         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10769                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
10770                 !kvm_vcpu_apicv_active(vcpu))
10771                 return;
10772
10773         do {
10774                 old.control = new.control = pi_desc->control;
10775
10776                 dest = cpu_physical_id(vcpu->cpu);
10777
10778                 if (x2apic_enabled())
10779                         new.ndst = dest;
10780                 else
10781                         new.ndst = (dest << 8) & 0xFF00;
10782
10783                 /* Allow posting non-urgent interrupts */
10784                 new.sn = 0;
10785
10786                 /* set 'NV' to 'notification vector' */
10787                 new.nv = POSTED_INTR_VECTOR;
10788         } while (cmpxchg(&pi_desc->control, old.control,
10789                         new.control) != old.control);
10790
10791         if(vcpu->pre_pcpu != -1) {
10792                 spin_lock_irqsave(
10793                         &per_cpu(blocked_vcpu_on_cpu_lock,
10794                         vcpu->pre_pcpu), flags);
10795                 list_del(&vcpu->blocked_vcpu_list);
10796                 spin_unlock_irqrestore(
10797                         &per_cpu(blocked_vcpu_on_cpu_lock,
10798                         vcpu->pre_pcpu), flags);
10799                 vcpu->pre_pcpu = -1;
10800         }
10801 }
10802
10803 /*
10804  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
10805  *
10806  * @kvm: kvm
10807  * @host_irq: host irq of the interrupt
10808  * @guest_irq: gsi of the interrupt
10809  * @set: set or unset PI
10810  * returns 0 on success, < 0 on failure
10811  */
10812 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
10813                               uint32_t guest_irq, bool set)
10814 {
10815         struct kvm_kernel_irq_routing_entry *e;
10816         struct kvm_irq_routing_table *irq_rt;
10817         struct kvm_lapic_irq irq;
10818         struct kvm_vcpu *vcpu;
10819         struct vcpu_data vcpu_info;
10820         int idx, ret = -EINVAL;
10821
10822         if (!kvm_arch_has_assigned_device(kvm) ||
10823                 !irq_remapping_cap(IRQ_POSTING_CAP) ||
10824                 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
10825                 return 0;
10826
10827         idx = srcu_read_lock(&kvm->irq_srcu);
10828         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
10829         BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
10830
10831         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
10832                 if (e->type != KVM_IRQ_ROUTING_MSI)
10833                         continue;
10834                 /*
10835                  * VT-d PI cannot support posting multicast/broadcast
10836                  * interrupts to a vCPU, we still use interrupt remapping
10837                  * for these kind of interrupts.
10838                  *
10839                  * For lowest-priority interrupts, we only support
10840                  * those with single CPU as the destination, e.g. user
10841                  * configures the interrupts via /proc/irq or uses
10842                  * irqbalance to make the interrupts single-CPU.
10843                  *
10844                  * We will support full lowest-priority interrupt later.
10845                  */
10846
10847                 kvm_set_msi_irq(e, &irq);
10848                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
10849                         /*
10850                          * Make sure the IRTE is in remapped mode if
10851                          * we don't handle it in posted mode.
10852                          */
10853                         ret = irq_set_vcpu_affinity(host_irq, NULL);
10854                         if (ret < 0) {
10855                                 printk(KERN_INFO
10856                                    "failed to back to remapped mode, irq: %u\n",
10857                                    host_irq);
10858                                 goto out;
10859                         }
10860
10861                         continue;
10862                 }
10863
10864                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
10865                 vcpu_info.vector = irq.vector;
10866
10867                 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
10868                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
10869
10870                 if (set)
10871                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
10872                 else {
10873                         /* suppress notification event before unposting */
10874                         pi_set_sn(vcpu_to_pi_desc(vcpu));
10875                         ret = irq_set_vcpu_affinity(host_irq, NULL);
10876                         pi_clear_sn(vcpu_to_pi_desc(vcpu));
10877                 }
10878
10879                 if (ret < 0) {
10880                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
10881                                         __func__);
10882                         goto out;
10883                 }
10884         }
10885
10886         ret = 0;
10887 out:
10888         srcu_read_unlock(&kvm->irq_srcu, idx);
10889         return ret;
10890 }
10891
10892 static struct kvm_x86_ops vmx_x86_ops = {
10893         .cpu_has_kvm_support = cpu_has_kvm_support,
10894         .disabled_by_bios = vmx_disabled_by_bios,
10895         .hardware_setup = hardware_setup,
10896         .hardware_unsetup = hardware_unsetup,
10897         .check_processor_compatibility = vmx_check_processor_compat,
10898         .hardware_enable = hardware_enable,
10899         .hardware_disable = hardware_disable,
10900         .cpu_has_accelerated_tpr = report_flexpriority,
10901         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
10902
10903         .vcpu_create = vmx_create_vcpu,
10904         .vcpu_free = vmx_free_vcpu,
10905         .vcpu_reset = vmx_vcpu_reset,
10906
10907         .prepare_guest_switch = vmx_save_host_state,
10908         .vcpu_load = vmx_vcpu_load,
10909         .vcpu_put = vmx_vcpu_put,
10910
10911         .update_bp_intercept = update_exception_bitmap,
10912         .get_msr = vmx_get_msr,
10913         .set_msr = vmx_set_msr,
10914         .get_segment_base = vmx_get_segment_base,
10915         .get_segment = vmx_get_segment,
10916         .set_segment = vmx_set_segment,
10917         .get_cpl = vmx_get_cpl,
10918         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
10919         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
10920         .decache_cr3 = vmx_decache_cr3,
10921         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
10922         .set_cr0 = vmx_set_cr0,
10923         .set_cr3 = vmx_set_cr3,
10924         .set_cr4 = vmx_set_cr4,
10925         .set_efer = vmx_set_efer,
10926         .get_idt = vmx_get_idt,
10927         .set_idt = vmx_set_idt,
10928         .get_gdt = vmx_get_gdt,
10929         .set_gdt = vmx_set_gdt,
10930         .get_dr6 = vmx_get_dr6,
10931         .set_dr6 = vmx_set_dr6,
10932         .set_dr7 = vmx_set_dr7,
10933         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
10934         .cache_reg = vmx_cache_reg,
10935         .get_rflags = vmx_get_rflags,
10936         .set_rflags = vmx_set_rflags,
10937
10938         .get_pkru = vmx_get_pkru,
10939
10940         .fpu_activate = vmx_fpu_activate,
10941         .fpu_deactivate = vmx_fpu_deactivate,
10942
10943         .tlb_flush = vmx_flush_tlb,
10944
10945         .run = vmx_vcpu_run,
10946         .handle_exit = vmx_handle_exit,
10947         .skip_emulated_instruction = skip_emulated_instruction,
10948         .set_interrupt_shadow = vmx_set_interrupt_shadow,
10949         .get_interrupt_shadow = vmx_get_interrupt_shadow,
10950         .patch_hypercall = vmx_patch_hypercall,
10951         .set_irq = vmx_inject_irq,
10952         .set_nmi = vmx_inject_nmi,
10953         .queue_exception = vmx_queue_exception,
10954         .cancel_injection = vmx_cancel_injection,
10955         .interrupt_allowed = vmx_interrupt_allowed,
10956         .nmi_allowed = vmx_nmi_allowed,
10957         .get_nmi_mask = vmx_get_nmi_mask,
10958         .set_nmi_mask = vmx_set_nmi_mask,
10959         .enable_nmi_window = enable_nmi_window,
10960         .enable_irq_window = enable_irq_window,
10961         .update_cr8_intercept = update_cr8_intercept,
10962         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
10963         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
10964         .get_enable_apicv = vmx_get_enable_apicv,
10965         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
10966         .load_eoi_exitmap = vmx_load_eoi_exitmap,
10967         .hwapic_irr_update = vmx_hwapic_irr_update,
10968         .hwapic_isr_update = vmx_hwapic_isr_update,
10969         .sync_pir_to_irr = vmx_sync_pir_to_irr,
10970         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
10971
10972         .set_tss_addr = vmx_set_tss_addr,
10973         .get_tdp_level = get_ept_level,
10974         .get_mt_mask = vmx_get_mt_mask,
10975
10976         .get_exit_info = vmx_get_exit_info,
10977
10978         .get_lpage_level = vmx_get_lpage_level,
10979
10980         .cpuid_update = vmx_cpuid_update,
10981
10982         .rdtscp_supported = vmx_rdtscp_supported,
10983         .invpcid_supported = vmx_invpcid_supported,
10984
10985         .set_supported_cpuid = vmx_set_supported_cpuid,
10986
10987         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
10988
10989         .read_tsc_offset = vmx_read_tsc_offset,
10990         .write_tsc_offset = vmx_write_tsc_offset,
10991         .adjust_tsc_offset_guest = vmx_adjust_tsc_offset_guest,
10992         .read_l1_tsc = vmx_read_l1_tsc,
10993
10994         .set_tdp_cr3 = vmx_set_cr3,
10995
10996         .check_intercept = vmx_check_intercept,
10997         .handle_external_intr = vmx_handle_external_intr,
10998         .mpx_supported = vmx_mpx_supported,
10999         .xsaves_supported = vmx_xsaves_supported,
11000
11001         .check_nested_events = vmx_check_nested_events,
11002
11003         .sched_in = vmx_sched_in,
11004
11005         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
11006         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
11007         .flush_log_dirty = vmx_flush_log_dirty,
11008         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
11009
11010         .pre_block = vmx_pre_block,
11011         .post_block = vmx_post_block,
11012
11013         .pmu_ops = &intel_pmu_ops,
11014
11015         .update_pi_irte = vmx_update_pi_irte,
11016 };
11017
11018 static int __init vmx_init(void)
11019 {
11020         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
11021                      __alignof__(struct vcpu_vmx), THIS_MODULE);
11022         if (r)
11023                 return r;
11024
11025 #ifdef CONFIG_KEXEC_CORE
11026         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
11027                            crash_vmclear_local_loaded_vmcss);
11028 #endif
11029
11030         return 0;
11031 }
11032
11033 static void __exit vmx_exit(void)
11034 {
11035 #ifdef CONFIG_KEXEC_CORE
11036         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
11037         synchronize_rcu();
11038 #endif
11039
11040         kvm_exit();
11041 }
11042
11043 module_init(vmx_init)
11044 module_exit(vmx_exit)