arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22 #include "lapic.h"
  23
  24 #include <linux/kvm_host.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/mod_devicetable.h>
  32 #include <linux/trace_events.h>
  33 #include <linux/slab.h>
  34 #include <linux/tboot.h>
  35 #include <linux/hrtimer.h>
  36 #include "kvm_cache_regs.h"
  37 #include "x86.h"
  38
  39 #include <asm/cpu.h>
  40 #include <asm/io.h>
  41 #include <asm/desc.h>
  42 #include <asm/vmx.h>
  43 #include <asm/virtext.h>
  44 #include <asm/mce.h>
  45 #include <asm/fpu/internal.h>
  46 #include <asm/perf_event.h>
  47 #include <asm/debugreg.h>
  48 #include <asm/kexec.h>
  49 #include <asm/apic.h>
  50 #include <asm/irq_remapping.h>
  51
  52 #include "trace.h"
  53 #include "pmu.h"
  54
  55 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  56 #define __ex_clear(x, reg) \
  57         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  58
  59 MODULE_AUTHOR("Qumranet");
  60 MODULE_LICENSE("GPL");
  61
  62 static const struct x86_cpu_id vmx_cpu_id[] = {
  63         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  64         {}
  65 };
  66 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  67
  68 static bool __read_mostly enable_vpid = 1;
  69 module_param_named(vpid, enable_vpid, bool, 0444);
  70
  71 static bool __read_mostly flexpriority_enabled = 1;
  72 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  73
  74 static bool __read_mostly enable_ept = 1;
  75 module_param_named(ept, enable_ept, bool, S_IRUGO);
  76
  77 static bool __read_mostly enable_unrestricted_guest = 1;
  78 module_param_named(unrestricted_guest,
  79                         enable_unrestricted_guest, bool, S_IRUGO);
  80
  81 static bool __read_mostly enable_ept_ad_bits = 1;
  82 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  83
  84 static bool __read_mostly emulate_invalid_guest_state = true;
  85 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  86
  87 static bool __read_mostly vmm_exclusive = 1;
  88 module_param(vmm_exclusive, bool, S_IRUGO);
  89
  90 static bool __read_mostly fasteoi = 1;
  91 module_param(fasteoi, bool, S_IRUGO);
  92
  93 static bool __read_mostly enable_apicv = 1;
  94 module_param(enable_apicv, bool, S_IRUGO);
  95
  96 static bool __read_mostly enable_shadow_vmcs = 1;
  97 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  98 /*
  99  * If nested=1, nested virtualization is supported, i.e., guests may use
 100  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 101  * use VMX instructions.
 102  */
 103 static bool __read_mostly nested = 0;
 104 module_param(nested, bool, S_IRUGO);
 105
 106 static u64 __read_mostly host_xss;
 107
 108 static bool __read_mostly enable_pml = 1;
 109 module_param_named(pml, enable_pml, bool, S_IRUGO);
 110
 111 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 112
 113 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 114 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 115 #define KVM_VM_CR0_ALWAYS_ON                                            \
 116         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 117 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 118         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 119          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 120
 121 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 122 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 123
 124 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 125
 126 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 127
 128 /*
 129  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 130  * ple_gap:    upper bound on the amount of time between two successive
 131  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 132  *             According to test, this time is usually smaller than 128 cycles.
 133  * ple_window: upper bound on the amount of time a guest is allowed to execute
 134  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 135  *             less than 2^12 cycles
 136  * Time is measured based on a counter that runs at the same rate as the TSC,
 137  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 138  */
 139 #define KVM_VMX_DEFAULT_PLE_GAP           128
 140 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 141 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 142 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 143 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 144                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 145
 146 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 147 module_param(ple_gap, int, S_IRUGO);
 148
 149 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 150 module_param(ple_window, int, S_IRUGO);
 151
 152 /* Default doubles per-vcpu window every exit. */
 153 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 154 module_param(ple_window_grow, int, S_IRUGO);
 155
 156 /* Default resets per-vcpu window every exit to ple_window. */
 157 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 158 module_param(ple_window_shrink, int, S_IRUGO);
 159
 160 /* Default is to compute the maximum so we can never overflow. */
 161 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 162 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 163 module_param(ple_window_max, int, S_IRUGO);
 164
 165 extern const ulong vmx_return;
 166
 167 #define NR_AUTOLOAD_MSRS 8
 168 #define VMCS02_POOL_SIZE 1
 169
 170 struct vmcs {
 171         u32 revision_id;
 172         u32 abort;
 173         char data[0];
 174 };
 175
 176 /*
 177  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 178  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 179  * loaded on this CPU (so we can clear them if the CPU goes down).
 180  */
 181 struct loaded_vmcs {
 182         struct vmcs *vmcs;
 183         int cpu;
 184         int launched;
 185         struct list_head loaded_vmcss_on_cpu_link;
 186 };
 187
 188 struct shared_msr_entry {
 189         unsigned index;
 190         u64 data;
 191         u64 mask;
 192 };
 193
 194 /*
 195  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 196  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 197  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 198  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 199  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 200  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 201  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 202  * underlying hardware which will be used to run L2.
 203  * This structure is packed to ensure that its layout is identical across
 204  * machines (necessary for live migration).
 205  * If there are changes in this struct, VMCS12_REVISION must be changed.
 206  */
 207 typedef u64 natural_width;
 208 struct __packed vmcs12 {
 209         /* According to the Intel spec, a VMCS region must start with the
 210          * following two fields. Then follow implementation-specific data.
 211          */
 212         u32 revision_id;
 213         u32 abort;
 214
 215         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 216         u32 padding[7]; /* room for future expansion */
 217
 218         u64 io_bitmap_a;
 219         u64 io_bitmap_b;
 220         u64 msr_bitmap;
 221         u64 vm_exit_msr_store_addr;
 222         u64 vm_exit_msr_load_addr;
 223         u64 vm_entry_msr_load_addr;
 224         u64 tsc_offset;
 225         u64 virtual_apic_page_addr;
 226         u64 apic_access_addr;
 227         u64 posted_intr_desc_addr;
 228         u64 ept_pointer;
 229         u64 eoi_exit_bitmap0;
 230         u64 eoi_exit_bitmap1;
 231         u64 eoi_exit_bitmap2;
 232         u64 eoi_exit_bitmap3;
 233         u64 xss_exit_bitmap;
 234         u64 guest_physical_address;
 235         u64 vmcs_link_pointer;
 236         u64 guest_ia32_debugctl;
 237         u64 guest_ia32_pat;
 238         u64 guest_ia32_efer;
 239         u64 guest_ia32_perf_global_ctrl;
 240         u64 guest_pdptr0;
 241         u64 guest_pdptr1;
 242         u64 guest_pdptr2;
 243         u64 guest_pdptr3;
 244         u64 guest_bndcfgs;
 245         u64 host_ia32_pat;
 246         u64 host_ia32_efer;
 247         u64 host_ia32_perf_global_ctrl;
 248         u64 padding64[8]; /* room for future expansion */
 249         /*
 250          * To allow migration of L1 (complete with its L2 guests) between
 251          * machines of different natural widths (32 or 64 bit), we cannot have
 252          * unsigned long fields with no explict size. We use u64 (aliased
 253          * natural_width) instead. Luckily, x86 is little-endian.
 254          */
 255         natural_width cr0_guest_host_mask;
 256         natural_width cr4_guest_host_mask;
 257         natural_width cr0_read_shadow;
 258         natural_width cr4_read_shadow;
 259         natural_width cr3_target_value0;
 260         natural_width cr3_target_value1;
 261         natural_width cr3_target_value2;
 262         natural_width cr3_target_value3;
 263         natural_width exit_qualification;
 264         natural_width guest_linear_address;
 265         natural_width guest_cr0;
 266         natural_width guest_cr3;
 267         natural_width guest_cr4;
 268         natural_width guest_es_base;
 269         natural_width guest_cs_base;
 270         natural_width guest_ss_base;
 271         natural_width guest_ds_base;
 272         natural_width guest_fs_base;
 273         natural_width guest_gs_base;
 274         natural_width guest_ldtr_base;
 275         natural_width guest_tr_base;
 276         natural_width guest_gdtr_base;
 277         natural_width guest_idtr_base;
 278         natural_width guest_dr7;
 279         natural_width guest_rsp;
 280         natural_width guest_rip;
 281         natural_width guest_rflags;
 282         natural_width guest_pending_dbg_exceptions;
 283         natural_width guest_sysenter_esp;
 284         natural_width guest_sysenter_eip;
 285         natural_width host_cr0;
 286         natural_width host_cr3;
 287         natural_width host_cr4;
 288         natural_width host_fs_base;
 289         natural_width host_gs_base;
 290         natural_width host_tr_base;
 291         natural_width host_gdtr_base;
 292         natural_width host_idtr_base;
 293         natural_width host_ia32_sysenter_esp;
 294         natural_width host_ia32_sysenter_eip;
 295         natural_width host_rsp;
 296         natural_width host_rip;
 297         natural_width paddingl[8]; /* room for future expansion */
 298         u32 pin_based_vm_exec_control;
 299         u32 cpu_based_vm_exec_control;
 300         u32 exception_bitmap;
 301         u32 page_fault_error_code_mask;
 302         u32 page_fault_error_code_match;
 303         u32 cr3_target_count;
 304         u32 vm_exit_controls;
 305         u32 vm_exit_msr_store_count;
 306         u32 vm_exit_msr_load_count;
 307         u32 vm_entry_controls;
 308         u32 vm_entry_msr_load_count;
 309         u32 vm_entry_intr_info_field;
 310         u32 vm_entry_exception_error_code;
 311         u32 vm_entry_instruction_len;
 312         u32 tpr_threshold;
 313         u32 secondary_vm_exec_control;
 314         u32 vm_instruction_error;
 315         u32 vm_exit_reason;
 316         u32 vm_exit_intr_info;
 317         u32 vm_exit_intr_error_code;
 318         u32 idt_vectoring_info_field;
 319         u32 idt_vectoring_error_code;
 320         u32 vm_exit_instruction_len;
 321         u32 vmx_instruction_info;
 322         u32 guest_es_limit;
 323         u32 guest_cs_limit;
 324         u32 guest_ss_limit;
 325         u32 guest_ds_limit;
 326         u32 guest_fs_limit;
 327         u32 guest_gs_limit;
 328         u32 guest_ldtr_limit;
 329         u32 guest_tr_limit;
 330         u32 guest_gdtr_limit;
 331         u32 guest_idtr_limit;
 332         u32 guest_es_ar_bytes;
 333         u32 guest_cs_ar_bytes;
 334         u32 guest_ss_ar_bytes;
 335         u32 guest_ds_ar_bytes;
 336         u32 guest_fs_ar_bytes;
 337         u32 guest_gs_ar_bytes;
 338         u32 guest_ldtr_ar_bytes;
 339         u32 guest_tr_ar_bytes;
 340         u32 guest_interruptibility_info;
 341         u32 guest_activity_state;
 342         u32 guest_sysenter_cs;
 343         u32 host_ia32_sysenter_cs;
 344         u32 vmx_preemption_timer_value;
 345         u32 padding32[7]; /* room for future expansion */
 346         u16 virtual_processor_id;
 347         u16 posted_intr_nv;
 348         u16 guest_es_selector;
 349         u16 guest_cs_selector;
 350         u16 guest_ss_selector;
 351         u16 guest_ds_selector;
 352         u16 guest_fs_selector;
 353         u16 guest_gs_selector;
 354         u16 guest_ldtr_selector;
 355         u16 guest_tr_selector;
 356         u16 guest_intr_status;
 357         u16 host_es_selector;
 358         u16 host_cs_selector;
 359         u16 host_ss_selector;
 360         u16 host_ds_selector;
 361         u16 host_fs_selector;
 362         u16 host_gs_selector;
 363         u16 host_tr_selector;
 364 };
 365
 366 /*
 367  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 368  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 369  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 370  */
 371 #define VMCS12_REVISION 0x11e57ed0
 372
 373 /*
 374  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 375  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 376  * current implementation, 4K are reserved to avoid future complications.
 377  */
 378 #define VMCS12_SIZE 0x1000
 379
 380 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 381 struct vmcs02_list {
 382         struct list_head list;
 383         gpa_t vmptr;
 384         struct loaded_vmcs vmcs02;
 385 };
 386
 387 /*
 388  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 389  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 390  */
 391 struct nested_vmx {
 392         /* Has the level1 guest done vmxon? */
 393         bool vmxon;
 394         gpa_t vmxon_ptr;
 395
 396         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 397         gpa_t current_vmptr;
 398         /* The host-usable pointer to the above */
 399         struct page *current_vmcs12_page;
 400         struct vmcs12 *current_vmcs12;
 401         struct vmcs *current_shadow_vmcs;
 402         /*
 403          * Indicates if the shadow vmcs must be updated with the
 404          * data hold by vmcs12
 405          */
 406         bool sync_shadow_vmcs;
 407
 408         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 409         struct list_head vmcs02_pool;
 410         int vmcs02_num;
 411         u64 vmcs01_tsc_offset;
 412         /* L2 must run next, and mustn't decide to exit to L1. */
 413         bool nested_run_pending;
 414         /*
 415          * Guest pages referred to in vmcs02 with host-physical pointers, so
 416          * we must keep them pinned while L2 runs.
 417          */
 418         struct page *apic_access_page;
 419         struct page *virtual_apic_page;
 420         struct page *pi_desc_page;
 421         struct pi_desc *pi_desc;
 422         bool pi_pending;
 423         u16 posted_intr_nv;
 424         u64 msr_ia32_feature_control;
 425
 426         struct hrtimer preemption_timer;
 427         bool preemption_timer_expired;
 428
 429         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 430         u64 vmcs01_debugctl;
 431
 432         u16 vpid02;
 433         u16 last_vpid;
 434
 435         u32 nested_vmx_procbased_ctls_low;
 436         u32 nested_vmx_procbased_ctls_high;
 437         u32 nested_vmx_true_procbased_ctls_low;
 438         u32 nested_vmx_secondary_ctls_low;
 439         u32 nested_vmx_secondary_ctls_high;
 440         u32 nested_vmx_pinbased_ctls_low;
 441         u32 nested_vmx_pinbased_ctls_high;
 442         u32 nested_vmx_exit_ctls_low;
 443         u32 nested_vmx_exit_ctls_high;
 444         u32 nested_vmx_true_exit_ctls_low;
 445         u32 nested_vmx_entry_ctls_low;
 446         u32 nested_vmx_entry_ctls_high;
 447         u32 nested_vmx_true_entry_ctls_low;
 448         u32 nested_vmx_misc_low;
 449         u32 nested_vmx_misc_high;
 450         u32 nested_vmx_ept_caps;
 451         u32 nested_vmx_vpid_caps;
 452 };
 453
 454 #define POSTED_INTR_ON  0
 455 #define POSTED_INTR_SN  1
 456
 457 /* Posted-Interrupt Descriptor */
 458 struct pi_desc {
 459         u32 pir[8];     /* Posted interrupt requested */
 460         union {
 461                 struct {
 462                                 /* bit 256 - Outstanding Notification */
 463                         u16     on      : 1,
 464                                 /* bit 257 - Suppress Notification */
 465                                 sn      : 1,
 466                                 /* bit 271:258 - Reserved */
 467                                 rsvd_1  : 14;
 468                                 /* bit 279:272 - Notification Vector */
 469                         u8      nv;
 470                                 /* bit 287:280 - Reserved */
 471                         u8      rsvd_2;
 472                                 /* bit 319:288 - Notification Destination */
 473                         u32     ndst;
 474                 };
 475                 u64 control;
 476         };
 477         u32 rsvd[6];
 478 } __aligned(64);
 479
 480 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 481 {
 482         return test_and_set_bit(POSTED_INTR_ON,
 483                         (unsigned long *)&pi_desc->control);
 484 }
 485
 486 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 487 {
 488         return test_and_clear_bit(POSTED_INTR_ON,
 489                         (unsigned long *)&pi_desc->control);
 490 }
 491
 492 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 493 {
 494         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 495 }
 496
 497 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 498 {
 499         return clear_bit(POSTED_INTR_SN,
 500                         (unsigned long *)&pi_desc->control);
 501 }
 502
 503 static inline void pi_set_sn(struct pi_desc *pi_desc)
 504 {
 505         return set_bit(POSTED_INTR_SN,
 506                         (unsigned long *)&pi_desc->control);
 507 }
 508
 509 static inline int pi_test_on(struct pi_desc *pi_desc)
 510 {
 511         return test_bit(POSTED_INTR_ON,
 512                         (unsigned long *)&pi_desc->control);
 513 }
 514
 515 static inline int pi_test_sn(struct pi_desc *pi_desc)
 516 {
 517         return test_bit(POSTED_INTR_SN,
 518                         (unsigned long *)&pi_desc->control);
 519 }
 520
 521 struct vcpu_vmx {
 522         struct kvm_vcpu       vcpu;
 523         unsigned long         host_rsp;
 524         u8                    fail;
 525         bool                  nmi_known_unmasked;
 526         u32                   exit_intr_info;
 527         u32                   idt_vectoring_info;
 528         ulong                 rflags;
 529         struct shared_msr_entry *guest_msrs;
 530         int                   nmsrs;
 531         int                   save_nmsrs;
 532         unsigned long         host_idt_base;
 533 #ifdef CONFIG_X86_64
 534         u64                   msr_host_kernel_gs_base;
 535         u64                   msr_guest_kernel_gs_base;
 536 #endif
 537         u32 vm_entry_controls_shadow;
 538         u32 vm_exit_controls_shadow;
 539         /*
 540          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 541          * non-nested (L1) guest, it always points to vmcs01. For a nested
 542          * guest (L2), it points to a different VMCS.
 543          */
 544         struct loaded_vmcs    vmcs01;
 545         struct loaded_vmcs   *loaded_vmcs;
 546         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 547         struct msr_autoload {
 548                 unsigned nr;
 549                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 550                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 551         } msr_autoload;
 552         struct {
 553                 int           loaded;
 554                 u16           fs_sel, gs_sel, ldt_sel;
 555 #ifdef CONFIG_X86_64
 556                 u16           ds_sel, es_sel;
 557 #endif
 558                 int           gs_ldt_reload_needed;
 559                 int           fs_reload_needed;
 560                 u64           msr_host_bndcfgs;
 561                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 562         } host_state;
 563         struct {
 564                 int vm86_active;
 565                 ulong save_rflags;
 566                 struct kvm_segment segs[8];
 567         } rmode;
 568         struct {
 569                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 570                 struct kvm_save_segment {
 571                         u16 selector;
 572                         unsigned long base;
 573                         u32 limit;
 574                         u32 ar;
 575                 } seg[8];
 576         } segment_cache;
 577         int vpid;
 578         bool emulation_required;
 579
 580         /* Support for vnmi-less CPUs */
 581         int soft_vnmi_blocked;
 582         ktime_t entry_time;
 583         s64 vnmi_blocked_time;
 584         u32 exit_reason;
 585
 586         /* Posted interrupt descriptor */
 587         struct pi_desc pi_desc;
 588
 589         /* Support for a guest hypervisor (nested VMX) */
 590         struct nested_vmx nested;
 591
 592         /* Dynamic PLE window. */
 593         int ple_window;
 594         bool ple_window_dirty;
 595
 596         /* Support for PML */
 597 #define PML_ENTITY_NUM          512
 598         struct page *pml_pg;
 599
 600         u64 current_tsc_ratio;
 601
 602         bool guest_pkru_valid;
 603         u32 guest_pkru;
 604         u32 host_pkru;
 605 };
 606
 607 enum segment_cache_field {
 608         SEG_FIELD_SEL = 0,
 609         SEG_FIELD_BASE = 1,
 610         SEG_FIELD_LIMIT = 2,
 611         SEG_FIELD_AR = 3,
 612
 613         SEG_FIELD_NR = 4
 614 };
 615
 616 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 617 {
 618         return container_of(vcpu, struct vcpu_vmx, vcpu);
 619 }
 620
 621 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 622 {
 623         return &(to_vmx(vcpu)->pi_desc);
 624 }
 625
 626 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 627 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 628 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 629                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 630
 631
 632 static unsigned long shadow_read_only_fields[] = {
 633         /*
 634          * We do NOT shadow fields that are modified when L0
 635          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 636          * VMXON...) executed by L1.
 637          * For example, VM_INSTRUCTION_ERROR is read
 638          * by L1 if a vmx instruction fails (part of the error path).
 639          * Note the code assumes this logic. If for some reason
 640          * we start shadowing these fields then we need to
 641          * force a shadow sync when L0 emulates vmx instructions
 642          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 643          * by nested_vmx_failValid)
 644          */
 645         VM_EXIT_REASON,
 646         VM_EXIT_INTR_INFO,
 647         VM_EXIT_INSTRUCTION_LEN,
 648         IDT_VECTORING_INFO_FIELD,
 649         IDT_VECTORING_ERROR_CODE,
 650         VM_EXIT_INTR_ERROR_CODE,
 651         EXIT_QUALIFICATION,
 652         GUEST_LINEAR_ADDRESS,
 653         GUEST_PHYSICAL_ADDRESS
 654 };
 655 static int max_shadow_read_only_fields =
 656         ARRAY_SIZE(shadow_read_only_fields);
 657
 658 static unsigned long shadow_read_write_fields[] = {
 659         TPR_THRESHOLD,
 660         GUEST_RIP,
 661         GUEST_RSP,
 662         GUEST_CR0,
 663         GUEST_CR3,
 664         GUEST_CR4,
 665         GUEST_INTERRUPTIBILITY_INFO,
 666         GUEST_RFLAGS,
 667         GUEST_CS_SELECTOR,
 668         GUEST_CS_AR_BYTES,
 669         GUEST_CS_LIMIT,
 670         GUEST_CS_BASE,
 671         GUEST_ES_BASE,
 672         GUEST_BNDCFGS,
 673         CR0_GUEST_HOST_MASK,
 674         CR0_READ_SHADOW,
 675         CR4_READ_SHADOW,
 676         TSC_OFFSET,
 677         EXCEPTION_BITMAP,
 678         CPU_BASED_VM_EXEC_CONTROL,
 679         VM_ENTRY_EXCEPTION_ERROR_CODE,
 680         VM_ENTRY_INTR_INFO_FIELD,
 681         VM_ENTRY_INSTRUCTION_LEN,
 682         VM_ENTRY_EXCEPTION_ERROR_CODE,
 683         HOST_FS_BASE,
 684         HOST_GS_BASE,
 685         HOST_FS_SELECTOR,
 686         HOST_GS_SELECTOR
 687 };
 688 static int max_shadow_read_write_fields =
 689         ARRAY_SIZE(shadow_read_write_fields);
 690
 691 static const unsigned short vmcs_field_to_offset_table[] = {
 692         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 693         FIELD(POSTED_INTR_NV, posted_intr_nv),
 694         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 695         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 696         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 697         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 698         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 699         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 700         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 701         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 702         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 703         FIELD(HOST_ES_SELECTOR, host_es_selector),
 704         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 705         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 706         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 707         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 708         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 709         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 710         FIELD64(IO_BITMAP_A, io_bitmap_a),
 711         FIELD64(IO_BITMAP_B, io_bitmap_b),
 712         FIELD64(MSR_BITMAP, msr_bitmap),
 713         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 714         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 715         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 716         FIELD64(TSC_OFFSET, tsc_offset),
 717         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 718         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 719         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 720         FIELD64(EPT_POINTER, ept_pointer),
 721         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 722         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 723         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 724         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 725         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 726         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 727         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 728         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 729         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 730         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 731         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 732         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 733         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 734         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 735         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 736         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 737         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 738         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 739         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 740         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 741         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 742         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 743         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 744         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 745         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 746         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 747         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 748         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 749         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 750         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 751         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 752         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 753         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 754         FIELD(TPR_THRESHOLD, tpr_threshold),
 755         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 756         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 757         FIELD(VM_EXIT_REASON, vm_exit_reason),
 758         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 759         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 760         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 761         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 762         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 763         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 764         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 765         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 766         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 767         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 768         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 769         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 770         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 771         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 772         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 773         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 774         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 775         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 776         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 777         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 778         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 779         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 780         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 781         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 782         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 783         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 784         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 785         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 786         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 787         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 788         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 789         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 790         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 791         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 792         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 793         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 794         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 795         FIELD(EXIT_QUALIFICATION, exit_qualification),
 796         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 797         FIELD(GUEST_CR0, guest_cr0),
 798         FIELD(GUEST_CR3, guest_cr3),
 799         FIELD(GUEST_CR4, guest_cr4),
 800         FIELD(GUEST_ES_BASE, guest_es_base),
 801         FIELD(GUEST_CS_BASE, guest_cs_base),
 802         FIELD(GUEST_SS_BASE, guest_ss_base),
 803         FIELD(GUEST_DS_BASE, guest_ds_base),
 804         FIELD(GUEST_FS_BASE, guest_fs_base),
 805         FIELD(GUEST_GS_BASE, guest_gs_base),
 806         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 807         FIELD(GUEST_TR_BASE, guest_tr_base),
 808         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 809         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 810         FIELD(GUEST_DR7, guest_dr7),
 811         FIELD(GUEST_RSP, guest_rsp),
 812         FIELD(GUEST_RIP, guest_rip),
 813         FIELD(GUEST_RFLAGS, guest_rflags),
 814         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 815         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 816         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 817         FIELD(HOST_CR0, host_cr0),
 818         FIELD(HOST_CR3, host_cr3),
 819         FIELD(HOST_CR4, host_cr4),
 820         FIELD(HOST_FS_BASE, host_fs_base),
 821         FIELD(HOST_GS_BASE, host_gs_base),
 822         FIELD(HOST_TR_BASE, host_tr_base),
 823         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 824         FIELD(HOST_IDTR_BASE, host_idtr_base),
 825         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 826         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 827         FIELD(HOST_RSP, host_rsp),
 828         FIELD(HOST_RIP, host_rip),
 829 };
 830
 831 static inline short vmcs_field_to_offset(unsigned long field)
 832 {
 833         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 834
 835         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 836             vmcs_field_to_offset_table[field] == 0)
 837                 return -ENOENT;
 838
 839         return vmcs_field_to_offset_table[field];
 840 }
 841
 842 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 843 {
 844         return to_vmx(vcpu)->nested.current_vmcs12;
 845 }
 846
 847 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 848 {
 849         struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
 850         if (is_error_page(page))
 851                 return NULL;
 852
 853         return page;
 854 }
 855
 856 static void nested_release_page(struct page *page)
 857 {
 858         kvm_release_page_dirty(page);
 859 }
 860
 861 static void nested_release_page_clean(struct page *page)
 862 {
 863         kvm_release_page_clean(page);
 864 }
 865
 866 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 867 static u64 construct_eptp(unsigned long root_hpa);
 868 static void kvm_cpu_vmxon(u64 addr);
 869 static void kvm_cpu_vmxoff(void);
 870 static bool vmx_xsaves_supported(void);
 871 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 872 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 873                             struct kvm_segment *var, int seg);
 874 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 875                             struct kvm_segment *var, int seg);
 876 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 877 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 878 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 879 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 880 static int alloc_identity_pagetable(struct kvm *kvm);
 881
 882 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 883 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 884 /*
 885  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 886  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 887  */
 888 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 889 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 890
 891 /*
 892  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 893  * can find which vCPU should be waken up.
 894  */
 895 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 896 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 897
 898 static unsigned long *vmx_io_bitmap_a;
 899 static unsigned long *vmx_io_bitmap_b;
 900 static unsigned long *vmx_msr_bitmap_legacy;
 901 static unsigned long *vmx_msr_bitmap_longmode;
 902 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 903 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 904 static unsigned long *vmx_msr_bitmap_nested;
 905 static unsigned long *vmx_vmread_bitmap;
 906 static unsigned long *vmx_vmwrite_bitmap;
 907
 908 static bool cpu_has_load_ia32_efer;
 909 static bool cpu_has_load_perf_global_ctrl;
 910
 911 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 912 static DEFINE_SPINLOCK(vmx_vpid_lock);
 913
 914 static struct vmcs_config {
 915         int size;
 916         int order;
 917         u32 revision_id;
 918         u32 pin_based_exec_ctrl;
 919         u32 cpu_based_exec_ctrl;
 920         u32 cpu_based_2nd_exec_ctrl;
 921         u32 vmexit_ctrl;
 922         u32 vmentry_ctrl;
 923 } vmcs_config;
 924
 925 static struct vmx_capability {
 926         u32 ept;
 927         u32 vpid;
 928 } vmx_capability;
 929
 930 #define VMX_SEGMENT_FIELD(seg)                                  \
 931         [VCPU_SREG_##seg] = {                                   \
 932                 .selector = GUEST_##seg##_SELECTOR,             \
 933                 .base = GUEST_##seg##_BASE,                     \
 934                 .limit = GUEST_##seg##_LIMIT,                   \
 935                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 936         }
 937
 938 static const struct kvm_vmx_segment_field {
 939         unsigned selector;
 940         unsigned base;
 941         unsigned limit;
 942         unsigned ar_bytes;
 943 } kvm_vmx_segment_fields[] = {
 944         VMX_SEGMENT_FIELD(CS),
 945         VMX_SEGMENT_FIELD(DS),
 946         VMX_SEGMENT_FIELD(ES),
 947         VMX_SEGMENT_FIELD(FS),
 948         VMX_SEGMENT_FIELD(GS),
 949         VMX_SEGMENT_FIELD(SS),
 950         VMX_SEGMENT_FIELD(TR),
 951         VMX_SEGMENT_FIELD(LDTR),
 952 };
 953
 954 static u64 host_efer;
 955
 956 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 957
 958 /*
 959  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 960  * away by decrementing the array size.
 961  */
 962 static const u32 vmx_msr_index[] = {
 963 #ifdef CONFIG_X86_64
 964         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 965 #endif
 966         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 967 };
 968
 969 static inline bool is_exception_n(u32 intr_info, u8 vector)
 970 {
 971         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 972                              INTR_INFO_VALID_MASK)) ==
 973                 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
 974 }
 975
 976 static inline bool is_debug(u32 intr_info)
 977 {
 978         return is_exception_n(intr_info, DB_VECTOR);
 979 }
 980
 981 static inline bool is_breakpoint(u32 intr_info)
 982 {
 983         return is_exception_n(intr_info, BP_VECTOR);
 984 }
 985
 986 static inline bool is_page_fault(u32 intr_info)
 987 {
 988         return is_exception_n(intr_info, PF_VECTOR);
 989 }
 990
 991 static inline bool is_no_device(u32 intr_info)
 992 {
 993         return is_exception_n(intr_info, NM_VECTOR);
 994 }
 995
 996 static inline bool is_invalid_opcode(u32 intr_info)
 997 {
 998         return is_exception_n(intr_info, UD_VECTOR);
 999 }
1000
1001 static inline bool is_external_interrupt(u32 intr_info)
1002 {
1003         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1004                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1005 }
1006
1007 static inline bool is_machine_check(u32 intr_info)
1008 {
1009         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1010                              INTR_INFO_VALID_MASK)) ==
1011                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1012 }
1013
1014 static inline bool cpu_has_vmx_msr_bitmap(void)
1015 {
1016         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1017 }
1018
1019 static inline bool cpu_has_vmx_tpr_shadow(void)
1020 {
1021         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1022 }
1023
1024 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1025 {
1026         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1027 }
1028
1029 static inline bool cpu_has_secondary_exec_ctrls(void)
1030 {
1031         return vmcs_config.cpu_based_exec_ctrl &
1032                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1033 }
1034
1035 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1036 {
1037         return vmcs_config.cpu_based_2nd_exec_ctrl &
1038                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1039 }
1040
1041 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1042 {
1043         return vmcs_config.cpu_based_2nd_exec_ctrl &
1044                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1045 }
1046
1047 static inline bool cpu_has_vmx_apic_register_virt(void)
1048 {
1049         return vmcs_config.cpu_based_2nd_exec_ctrl &
1050                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1051 }
1052
1053 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1054 {
1055         return vmcs_config.cpu_based_2nd_exec_ctrl &
1056                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1057 }
1058
1059 static inline bool cpu_has_vmx_posted_intr(void)
1060 {
1061         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1062                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1063 }
1064
1065 static inline bool cpu_has_vmx_apicv(void)
1066 {
1067         return cpu_has_vmx_apic_register_virt() &&
1068                 cpu_has_vmx_virtual_intr_delivery() &&
1069                 cpu_has_vmx_posted_intr();
1070 }
1071
1072 static inline bool cpu_has_vmx_flexpriority(void)
1073 {
1074         return cpu_has_vmx_tpr_shadow() &&
1075                 cpu_has_vmx_virtualize_apic_accesses();
1076 }
1077
1078 static inline bool cpu_has_vmx_ept_execute_only(void)
1079 {
1080         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1081 }
1082
1083 static inline bool cpu_has_vmx_ept_2m_page(void)
1084 {
1085         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1086 }
1087
1088 static inline bool cpu_has_vmx_ept_1g_page(void)
1089 {
1090         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1091 }
1092
1093 static inline bool cpu_has_vmx_ept_4levels(void)
1094 {
1095         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1096 }
1097
1098 static inline bool cpu_has_vmx_ept_ad_bits(void)
1099 {
1100         return vmx_capability.ept & VMX_EPT_AD_BIT;
1101 }
1102
1103 static inline bool cpu_has_vmx_invept_context(void)
1104 {
1105         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1106 }
1107
1108 static inline bool cpu_has_vmx_invept_global(void)
1109 {
1110         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1111 }
1112
1113 static inline bool cpu_has_vmx_invvpid_single(void)
1114 {
1115         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1116 }
1117
1118 static inline bool cpu_has_vmx_invvpid_global(void)
1119 {
1120         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1121 }
1122
1123 static inline bool cpu_has_vmx_ept(void)
1124 {
1125         return vmcs_config.cpu_based_2nd_exec_ctrl &
1126                 SECONDARY_EXEC_ENABLE_EPT;
1127 }
1128
1129 static inline bool cpu_has_vmx_unrestricted_guest(void)
1130 {
1131         return vmcs_config.cpu_based_2nd_exec_ctrl &
1132                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1133 }
1134
1135 static inline bool cpu_has_vmx_ple(void)
1136 {
1137         return vmcs_config.cpu_based_2nd_exec_ctrl &
1138                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1139 }
1140
1141 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1142 {
1143         return flexpriority_enabled && lapic_in_kernel(vcpu);
1144 }
1145
1146 static inline bool cpu_has_vmx_vpid(void)
1147 {
1148         return vmcs_config.cpu_based_2nd_exec_ctrl &
1149                 SECONDARY_EXEC_ENABLE_VPID;
1150 }
1151
1152 static inline bool cpu_has_vmx_rdtscp(void)
1153 {
1154         return vmcs_config.cpu_based_2nd_exec_ctrl &
1155                 SECONDARY_EXEC_RDTSCP;
1156 }
1157
1158 static inline bool cpu_has_vmx_invpcid(void)
1159 {
1160         return vmcs_config.cpu_based_2nd_exec_ctrl &
1161                 SECONDARY_EXEC_ENABLE_INVPCID;
1162 }
1163
1164 static inline bool cpu_has_virtual_nmis(void)
1165 {
1166         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1167 }
1168
1169 static inline bool cpu_has_vmx_wbinvd_exit(void)
1170 {
1171         return vmcs_config.cpu_based_2nd_exec_ctrl &
1172                 SECONDARY_EXEC_WBINVD_EXITING;
1173 }
1174
1175 static inline bool cpu_has_vmx_shadow_vmcs(void)
1176 {
1177         u64 vmx_msr;
1178         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1179         /* check if the cpu supports writing r/o exit information fields */
1180         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1181                 return false;
1182
1183         return vmcs_config.cpu_based_2nd_exec_ctrl &
1184                 SECONDARY_EXEC_SHADOW_VMCS;
1185 }
1186
1187 static inline bool cpu_has_vmx_pml(void)
1188 {
1189         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1190 }
1191
1192 static inline bool cpu_has_vmx_tsc_scaling(void)
1193 {
1194         return vmcs_config.cpu_based_2nd_exec_ctrl &
1195                 SECONDARY_EXEC_TSC_SCALING;
1196 }
1197
1198 static inline bool report_flexpriority(void)
1199 {
1200         return flexpriority_enabled;
1201 }
1202
1203 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1204 {
1205         return vmcs12->cpu_based_vm_exec_control & bit;
1206 }
1207
1208 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1209 {
1210         return (vmcs12->cpu_based_vm_exec_control &
1211                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1212                 (vmcs12->secondary_vm_exec_control & bit);
1213 }
1214
1215 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1216 {
1217         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1218 }
1219
1220 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1221 {
1222         return vmcs12->pin_based_vm_exec_control &
1223                 PIN_BASED_VMX_PREEMPTION_TIMER;
1224 }
1225
1226 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1227 {
1228         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1229 }
1230
1231 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1232 {
1233         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1234                 vmx_xsaves_supported();
1235 }
1236
1237 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1238 {
1239         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1240 }
1241
1242 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1243 {
1244         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1245 }
1246
1247 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1248 {
1249         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1250 }
1251
1252 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1253 {
1254         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1255 }
1256
1257 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1258 {
1259         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1260 }
1261
1262 static inline bool is_exception(u32 intr_info)
1263 {
1264         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1265                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1266 }
1267
1268 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1269                               u32 exit_intr_info,
1270                               unsigned long exit_qualification);
1271 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1272                         struct vmcs12 *vmcs12,
1273                         u32 reason, unsigned long qualification);
1274
1275 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1276 {
1277         int i;
1278
1279         for (i = 0; i < vmx->nmsrs; ++i)
1280                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1281                         return i;
1282         return -1;
1283 }
1284
1285 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1286 {
1287     struct {
1288         u64 vpid : 16;
1289         u64 rsvd : 48;
1290         u64 gva;
1291     } operand = { vpid, 0, gva };
1292
1293     asm volatile (__ex(ASM_VMX_INVVPID)
1294                   /* CF==1 or ZF==1 --> rc = -1 */
1295                   "; ja 1f ; ud2 ; 1:"
1296                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1297 }
1298
1299 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1300 {
1301         struct {
1302                 u64 eptp, gpa;
1303         } operand = {eptp, gpa};
1304
1305         asm volatile (__ex(ASM_VMX_INVEPT)
1306                         /* CF==1 or ZF==1 --> rc = -1 */
1307                         "; ja 1f ; ud2 ; 1:\n"
1308                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1309 }
1310
1311 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1312 {
1313         int i;
1314
1315         i = __find_msr_index(vmx, msr);
1316         if (i >= 0)
1317                 return &vmx->guest_msrs[i];
1318         return NULL;
1319 }
1320
1321 static void vmcs_clear(struct vmcs *vmcs)
1322 {
1323         u64 phys_addr = __pa(vmcs);
1324         u8 error;
1325
1326         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1327                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1328                       : "cc", "memory");
1329         if (error)
1330                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1331                        vmcs, phys_addr);
1332 }
1333
1334 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1335 {
1336         vmcs_clear(loaded_vmcs->vmcs);
1337         loaded_vmcs->cpu = -1;
1338         loaded_vmcs->launched = 0;
1339 }
1340
1341 static void vmcs_load(struct vmcs *vmcs)
1342 {
1343         u64 phys_addr = __pa(vmcs);
1344         u8 error;
1345
1346         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1347                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1348                         : "cc", "memory");
1349         if (error)
1350                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1351                        vmcs, phys_addr);
1352 }
1353
1354 #ifdef CONFIG_KEXEC_CORE
1355 /*
1356  * This bitmap is used to indicate whether the vmclear
1357  * operation is enabled on all cpus. All disabled by
1358  * default.
1359  */
1360 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1361
1362 static inline void crash_enable_local_vmclear(int cpu)
1363 {
1364         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1365 }
1366
1367 static inline void crash_disable_local_vmclear(int cpu)
1368 {
1369         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1370 }
1371
1372 static inline int crash_local_vmclear_enabled(int cpu)
1373 {
1374         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1375 }
1376
1377 static void crash_vmclear_local_loaded_vmcss(void)
1378 {
1379         int cpu = raw_smp_processor_id();
1380         struct loaded_vmcs *v;
1381
1382         if (!crash_local_vmclear_enabled(cpu))
1383                 return;
1384
1385         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1386                             loaded_vmcss_on_cpu_link)
1387                 vmcs_clear(v->vmcs);
1388 }
1389 #else
1390 static inline void crash_enable_local_vmclear(int cpu) { }
1391 static inline void crash_disable_local_vmclear(int cpu) { }
1392 #endif /* CONFIG_KEXEC_CORE */
1393
1394 static void __loaded_vmcs_clear(void *arg)
1395 {
1396         struct loaded_vmcs *loaded_vmcs = arg;
1397         int cpu = raw_smp_processor_id();
1398
1399         if (loaded_vmcs->cpu != cpu)
1400                 return; /* vcpu migration can race with cpu offline */
1401         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1402                 per_cpu(current_vmcs, cpu) = NULL;
1403         crash_disable_local_vmclear(cpu);
1404         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1405
1406         /*
1407          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1408          * is before setting loaded_vmcs->vcpu to -1 which is done in
1409          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1410          * then adds the vmcs into percpu list before it is deleted.
1411          */
1412         smp_wmb();
1413
1414         loaded_vmcs_init(loaded_vmcs);
1415         crash_enable_local_vmclear(cpu);
1416 }
1417
1418 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1419 {
1420         int cpu = loaded_vmcs->cpu;
1421
1422         if (cpu != -1)
1423                 smp_call_function_single(cpu,
1424                          __loaded_vmcs_clear, loaded_vmcs, 1);
1425 }
1426
1427 static inline void vpid_sync_vcpu_single(int vpid)
1428 {
1429         if (vpid == 0)
1430                 return;
1431
1432         if (cpu_has_vmx_invvpid_single())
1433                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1434 }
1435
1436 static inline void vpid_sync_vcpu_global(void)
1437 {
1438         if (cpu_has_vmx_invvpid_global())
1439                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1440 }
1441
1442 static inline void vpid_sync_context(int vpid)
1443 {
1444         if (cpu_has_vmx_invvpid_single())
1445                 vpid_sync_vcpu_single(vpid);
1446         else
1447                 vpid_sync_vcpu_global();
1448 }
1449
1450 static inline void ept_sync_global(void)
1451 {
1452         if (cpu_has_vmx_invept_global())
1453                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1454 }
1455
1456 static inline void ept_sync_context(u64 eptp)
1457 {
1458         if (enable_ept) {
1459                 if (cpu_has_vmx_invept_context())
1460                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1461                 else
1462                         ept_sync_global();
1463         }
1464 }
1465
1466 static __always_inline void vmcs_check16(unsigned long field)
1467 {
1468         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1469                          "16-bit accessor invalid for 64-bit field");
1470         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1471                          "16-bit accessor invalid for 64-bit high field");
1472         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1473                          "16-bit accessor invalid for 32-bit high field");
1474         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1475                          "16-bit accessor invalid for natural width field");
1476 }
1477
1478 static __always_inline void vmcs_check32(unsigned long field)
1479 {
1480         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1481                          "32-bit accessor invalid for 16-bit field");
1482         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1483                          "32-bit accessor invalid for natural width field");
1484 }
1485
1486 static __always_inline void vmcs_check64(unsigned long field)
1487 {
1488         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1489                          "64-bit accessor invalid for 16-bit field");
1490         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1491                          "64-bit accessor invalid for 64-bit high field");
1492         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1493                          "64-bit accessor invalid for 32-bit field");
1494         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1495                          "64-bit accessor invalid for natural width field");
1496 }
1497
1498 static __always_inline void vmcs_checkl(unsigned long field)
1499 {
1500         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1501                          "Natural width accessor invalid for 16-bit field");
1502         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1503                          "Natural width accessor invalid for 64-bit field");
1504         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1505                          "Natural width accessor invalid for 64-bit high field");
1506         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1507                          "Natural width accessor invalid for 32-bit field");
1508 }
1509
1510 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1511 {
1512         unsigned long value;
1513
1514         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1515                       : "=a"(value) : "d"(field) : "cc");
1516         return value;
1517 }
1518
1519 static __always_inline u16 vmcs_read16(unsigned long field)
1520 {
1521         vmcs_check16(field);
1522         return __vmcs_readl(field);
1523 }
1524
1525 static __always_inline u32 vmcs_read32(unsigned long field)
1526 {
1527         vmcs_check32(field);
1528         return __vmcs_readl(field);
1529 }
1530
1531 static __always_inline u64 vmcs_read64(unsigned long field)
1532 {
1533         vmcs_check64(field);
1534 #ifdef CONFIG_X86_64
1535         return __vmcs_readl(field);
1536 #else
1537         return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1538 #endif
1539 }
1540
1541 static __always_inline unsigned long vmcs_readl(unsigned long field)
1542 {
1543         vmcs_checkl(field);
1544         return __vmcs_readl(field);
1545 }
1546
1547 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1548 {
1549         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1550                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1551         dump_stack();
1552 }
1553
1554 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1555 {
1556         u8 error;
1557
1558         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1559                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1560         if (unlikely(error))
1561                 vmwrite_error(field, value);
1562 }
1563
1564 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1565 {
1566         vmcs_check16(field);
1567         __vmcs_writel(field, value);
1568 }
1569
1570 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1571 {
1572         vmcs_check32(field);
1573         __vmcs_writel(field, value);
1574 }
1575
1576 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1577 {
1578         vmcs_check64(field);
1579         __vmcs_writel(field, value);
1580 #ifndef CONFIG_X86_64
1581         asm volatile ("");
1582         __vmcs_writel(field+1, value >> 32);
1583 #endif
1584 }
1585
1586 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1587 {
1588         vmcs_checkl(field);
1589         __vmcs_writel(field, value);
1590 }
1591
1592 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1593 {
1594         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1595                          "vmcs_clear_bits does not support 64-bit fields");
1596         __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1597 }
1598
1599 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1600 {
1601         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1602                          "vmcs_set_bits does not support 64-bit fields");
1603         __vmcs_writel(field, __vmcs_readl(field) | mask);
1604 }
1605
1606 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1607 {
1608         vmcs_write32(VM_ENTRY_CONTROLS, val);
1609         vmx->vm_entry_controls_shadow = val;
1610 }
1611
1612 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1613 {
1614         if (vmx->vm_entry_controls_shadow != val)
1615                 vm_entry_controls_init(vmx, val);
1616 }
1617
1618 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1619 {
1620         return vmx->vm_entry_controls_shadow;
1621 }
1622
1623
1624 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1625 {
1626         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1627 }
1628
1629 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1630 {
1631         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1632 }
1633
1634 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1635 {
1636         vmcs_write32(VM_EXIT_CONTROLS, val);
1637         vmx->vm_exit_controls_shadow = val;
1638 }
1639
1640 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1641 {
1642         if (vmx->vm_exit_controls_shadow != val)
1643                 vm_exit_controls_init(vmx, val);
1644 }
1645
1646 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1647 {
1648         return vmx->vm_exit_controls_shadow;
1649 }
1650
1651
1652 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1653 {
1654         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1655 }
1656
1657 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1658 {
1659         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1660 }
1661
1662 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1663 {
1664         vmx->segment_cache.bitmask = 0;
1665 }
1666
1667 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1668                                        unsigned field)
1669 {
1670         bool ret;
1671         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1672
1673         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1674                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1675                 vmx->segment_cache.bitmask = 0;
1676         }
1677         ret = vmx->segment_cache.bitmask & mask;
1678         vmx->segment_cache.bitmask |= mask;
1679         return ret;
1680 }
1681
1682 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1683 {
1684         u16 *p = &vmx->segment_cache.seg[seg].selector;
1685
1686         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1687                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1688         return *p;
1689 }
1690
1691 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1692 {
1693         ulong *p = &vmx->segment_cache.seg[seg].base;
1694
1695         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1696                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1697         return *p;
1698 }
1699
1700 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1701 {
1702         u32 *p = &vmx->segment_cache.seg[seg].limit;
1703
1704         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1705                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1706         return *p;
1707 }
1708
1709 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1710 {
1711         u32 *p = &vmx->segment_cache.seg[seg].ar;
1712
1713         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1714                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1715         return *p;
1716 }
1717
1718 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1719 {
1720         u32 eb;
1721
1722         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1723              (1u << NM_VECTOR) | (1u << DB_VECTOR) | (1u << AC_VECTOR);
1724         if ((vcpu->guest_debug &
1725              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1726             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1727                 eb |= 1u << BP_VECTOR;
1728         if (to_vmx(vcpu)->rmode.vm86_active)
1729                 eb = ~0;
1730         if (enable_ept)
1731                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1732         if (vcpu->fpu_active)
1733                 eb &= ~(1u << NM_VECTOR);
1734
1735         /* When we are running a nested L2 guest and L1 specified for it a
1736          * certain exception bitmap, we must trap the same exceptions and pass
1737          * them to L1. When running L2, we will only handle the exceptions
1738          * specified above if L1 did not want them.
1739          */
1740         if (is_guest_mode(vcpu))
1741                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1742
1743         vmcs_write32(EXCEPTION_BITMAP, eb);
1744 }
1745
1746 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1747                 unsigned long entry, unsigned long exit)
1748 {
1749         vm_entry_controls_clearbit(vmx, entry);
1750         vm_exit_controls_clearbit(vmx, exit);
1751 }
1752
1753 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1754 {
1755         unsigned i;
1756         struct msr_autoload *m = &vmx->msr_autoload;
1757
1758         switch (msr) {
1759         case MSR_EFER:
1760                 if (cpu_has_load_ia32_efer) {
1761                         clear_atomic_switch_msr_special(vmx,
1762                                         VM_ENTRY_LOAD_IA32_EFER,
1763                                         VM_EXIT_LOAD_IA32_EFER);
1764                         return;
1765                 }
1766                 break;
1767         case MSR_CORE_PERF_GLOBAL_CTRL:
1768                 if (cpu_has_load_perf_global_ctrl) {
1769                         clear_atomic_switch_msr_special(vmx,
1770                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1771                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1772                         return;
1773                 }
1774                 break;
1775         }
1776
1777         for (i = 0; i < m->nr; ++i)
1778                 if (m->guest[i].index == msr)
1779                         break;
1780
1781         if (i == m->nr)
1782                 return;
1783         --m->nr;
1784         m->guest[i] = m->guest[m->nr];
1785         m->host[i] = m->host[m->nr];
1786         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1787         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1788 }
1789
1790 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1791                 unsigned long entry, unsigned long exit,
1792                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1793                 u64 guest_val, u64 host_val)
1794 {
1795         vmcs_write64(guest_val_vmcs, guest_val);
1796         vmcs_write64(host_val_vmcs, host_val);
1797         vm_entry_controls_setbit(vmx, entry);
1798         vm_exit_controls_setbit(vmx, exit);
1799 }
1800
1801 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1802                                   u64 guest_val, u64 host_val)
1803 {
1804         unsigned i;
1805         struct msr_autoload *m = &vmx->msr_autoload;
1806
1807         switch (msr) {
1808         case MSR_EFER:
1809                 if (cpu_has_load_ia32_efer) {
1810                         add_atomic_switch_msr_special(vmx,
1811                                         VM_ENTRY_LOAD_IA32_EFER,
1812                                         VM_EXIT_LOAD_IA32_EFER,
1813                                         GUEST_IA32_EFER,
1814                                         HOST_IA32_EFER,
1815                                         guest_val, host_val);
1816                         return;
1817                 }
1818                 break;
1819         case MSR_CORE_PERF_GLOBAL_CTRL:
1820                 if (cpu_has_load_perf_global_ctrl) {
1821                         add_atomic_switch_msr_special(vmx,
1822                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1823                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1824                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1825                                         HOST_IA32_PERF_GLOBAL_CTRL,
1826                                         guest_val, host_val);
1827                         return;
1828                 }
1829                 break;
1830         case MSR_IA32_PEBS_ENABLE:
1831                 /* PEBS needs a quiescent period after being disabled (to write
1832                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
1833                  * provide that period, so a CPU could write host's record into
1834                  * guest's memory.
1835                  */
1836                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1837         }
1838
1839         for (i = 0; i < m->nr; ++i)
1840                 if (m->guest[i].index == msr)
1841                         break;
1842
1843         if (i == NR_AUTOLOAD_MSRS) {
1844                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1845                                 "Can't add msr %x\n", msr);
1846                 return;
1847         } else if (i == m->nr) {
1848                 ++m->nr;
1849                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1850                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1851         }
1852
1853         m->guest[i].index = msr;
1854         m->guest[i].value = guest_val;
1855         m->host[i].index = msr;
1856         m->host[i].value = host_val;
1857 }
1858
1859 static void reload_tss(void)
1860 {
1861         /*
1862          * VT restores TR but not its size.  Useless.
1863          */
1864         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1865         struct desc_struct *descs;
1866
1867         descs = (void *)gdt->address;
1868         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1869         load_TR_desc();
1870 }
1871
1872 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1873 {
1874         u64 guest_efer = vmx->vcpu.arch.efer;
1875         u64 ignore_bits = 0;
1876
1877         if (!enable_ept) {
1878                 /*
1879                  * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
1880                  * host CPUID is more efficient than testing guest CPUID
1881                  * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
1882                  */
1883                 if (boot_cpu_has(X86_FEATURE_SMEP))
1884                         guest_efer |= EFER_NX;
1885                 else if (!(guest_efer & EFER_NX))
1886                         ignore_bits |= EFER_NX;
1887         }
1888
1889         /*
1890          * LMA and LME handled by hardware; SCE meaningless outside long mode.
1891          */
1892         ignore_bits |= EFER_SCE;
1893 #ifdef CONFIG_X86_64
1894         ignore_bits |= EFER_LMA | EFER_LME;
1895         /* SCE is meaningful only in long mode on Intel */
1896         if (guest_efer & EFER_LMA)
1897                 ignore_bits &= ~(u64)EFER_SCE;
1898 #endif
1899
1900         clear_atomic_switch_msr(vmx, MSR_EFER);
1901
1902         /*
1903          * On EPT, we can't emulate NX, so we must switch EFER atomically.
1904          * On CPUs that support "load IA32_EFER", always switch EFER
1905          * atomically, since it's faster than switching it manually.
1906          */
1907         if (cpu_has_load_ia32_efer ||
1908             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1909                 if (!(guest_efer & EFER_LMA))
1910                         guest_efer &= ~EFER_LME;
1911                 if (guest_efer != host_efer)
1912                         add_atomic_switch_msr(vmx, MSR_EFER,
1913                                               guest_efer, host_efer);
1914                 return false;
1915         } else {
1916                 guest_efer &= ~ignore_bits;
1917                 guest_efer |= host_efer & ignore_bits;
1918
1919                 vmx->guest_msrs[efer_offset].data = guest_efer;
1920                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1921
1922                 return true;
1923         }
1924 }
1925
1926 static unsigned long segment_base(u16 selector)
1927 {
1928         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1929         struct desc_struct *d;
1930         unsigned long table_base;
1931         unsigned long v;
1932
1933         if (!(selector & ~3))
1934                 return 0;
1935
1936         table_base = gdt->address;
1937
1938         if (selector & 4) {           /* from ldt */
1939                 u16 ldt_selector = kvm_read_ldt();
1940
1941                 if (!(ldt_selector & ~3))
1942                         return 0;
1943
1944                 table_base = segment_base(ldt_selector);
1945         }
1946         d = (struct desc_struct *)(table_base + (selector & ~7));
1947         v = get_desc_base(d);
1948 #ifdef CONFIG_X86_64
1949        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1950                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1951 #endif
1952         return v;
1953 }
1954
1955 static inline unsigned long kvm_read_tr_base(void)
1956 {
1957         u16 tr;
1958         asm("str %0" : "=g"(tr));
1959         return segment_base(tr);
1960 }
1961
1962 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1963 {
1964         struct vcpu_vmx *vmx = to_vmx(vcpu);
1965         int i;
1966
1967         if (vmx->host_state.loaded)
1968                 return;
1969
1970         vmx->host_state.loaded = 1;
1971         /*
1972          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1973          * allow segment selectors with cpl > 0 or ti == 1.
1974          */
1975         vmx->host_state.ldt_sel = kvm_read_ldt();
1976         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1977         savesegment(fs, vmx->host_state.fs_sel);
1978         if (!(vmx->host_state.fs_sel & 7)) {
1979                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1980                 vmx->host_state.fs_reload_needed = 0;
1981         } else {
1982                 vmcs_write16(HOST_FS_SELECTOR, 0);
1983                 vmx->host_state.fs_reload_needed = 1;
1984         }
1985         savesegment(gs, vmx->host_state.gs_sel);
1986         if (!(vmx->host_state.gs_sel & 7))
1987                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1988         else {
1989                 vmcs_write16(HOST_GS_SELECTOR, 0);
1990                 vmx->host_state.gs_ldt_reload_needed = 1;
1991         }
1992
1993 #ifdef CONFIG_X86_64
1994         savesegment(ds, vmx->host_state.ds_sel);
1995         savesegment(es, vmx->host_state.es_sel);
1996 #endif
1997
1998 #ifdef CONFIG_X86_64
1999         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2000         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2001 #else
2002         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2003         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2004 #endif
2005
2006 #ifdef CONFIG_X86_64
2007         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2008         if (is_long_mode(&vmx->vcpu))
2009                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2010 #endif
2011         if (boot_cpu_has(X86_FEATURE_MPX))
2012                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2013         for (i = 0; i < vmx->save_nmsrs; ++i)
2014                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2015                                    vmx->guest_msrs[i].data,
2016                                    vmx->guest_msrs[i].mask);
2017 }
2018
2019 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2020 {
2021         if (!vmx->host_state.loaded)
2022                 return;
2023
2024         ++vmx->vcpu.stat.host_state_reload;
2025         vmx->host_state.loaded = 0;
2026 #ifdef CONFIG_X86_64
2027         if (is_long_mode(&vmx->vcpu))
2028                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2029 #endif
2030         if (vmx->host_state.gs_ldt_reload_needed) {
2031                 kvm_load_ldt(vmx->host_state.ldt_sel);
2032 #ifdef CONFIG_X86_64
2033                 load_gs_index(vmx->host_state.gs_sel);
2034 #else
2035                 loadsegment(gs, vmx->host_state.gs_sel);
2036 #endif
2037         }
2038         if (vmx->host_state.fs_reload_needed)
2039                 loadsegment(fs, vmx->host_state.fs_sel);
2040 #ifdef CONFIG_X86_64
2041         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2042                 loadsegment(ds, vmx->host_state.ds_sel);
2043                 loadsegment(es, vmx->host_state.es_sel);
2044         }
2045 #endif
2046         reload_tss();
2047 #ifdef CONFIG_X86_64
2048         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2049 #endif
2050         if (vmx->host_state.msr_host_bndcfgs)
2051                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2052         /*
2053          * If the FPU is not active (through the host task or
2054          * the guest vcpu), then restore the cr0.TS bit.
2055          */
2056         if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded)
2057                 stts();
2058         load_gdt(this_cpu_ptr(&host_gdt));
2059 }
2060
2061 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2062 {
2063         preempt_disable();
2064         __vmx_load_host_state(vmx);
2065         preempt_enable();
2066 }
2067
2068 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2069 {
2070         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2071         struct pi_desc old, new;
2072         unsigned int dest;
2073
2074         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2075                 !irq_remapping_cap(IRQ_POSTING_CAP))
2076                 return;
2077
2078         do {
2079                 old.control = new.control = pi_desc->control;
2080
2081                 /*
2082                  * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2083                  * are two possible cases:
2084                  * 1. After running 'pre_block', context switch
2085                  *    happened. For this case, 'sn' was set in
2086                  *    vmx_vcpu_put(), so we need to clear it here.
2087                  * 2. After running 'pre_block', we were blocked,
2088                  *    and woken up by some other guy. For this case,
2089                  *    we don't need to do anything, 'pi_post_block'
2090                  *    will do everything for us. However, we cannot
2091                  *    check whether it is case #1 or case #2 here
2092                  *    (maybe, not needed), so we also clear sn here,
2093                  *    I think it is not a big deal.
2094                  */
2095                 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2096                         if (vcpu->cpu != cpu) {
2097                                 dest = cpu_physical_id(cpu);
2098
2099                                 if (x2apic_enabled())
2100                                         new.ndst = dest;
2101                                 else
2102                                         new.ndst = (dest << 8) & 0xFF00;
2103                         }
2104
2105                         /* set 'NV' to 'notification vector' */
2106                         new.nv = POSTED_INTR_VECTOR;
2107                 }
2108
2109                 /* Allow posting non-urgent interrupts */
2110                 new.sn = 0;
2111         } while (cmpxchg(&pi_desc->control, old.control,
2112                         new.control) != old.control);
2113 }
2114
2115 /*
2116  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2117  * vcpu mutex is already taken.
2118  */
2119 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2120 {
2121         struct vcpu_vmx *vmx = to_vmx(vcpu);
2122         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2123
2124         if (!vmm_exclusive)
2125                 kvm_cpu_vmxon(phys_addr);
2126         else if (vmx->loaded_vmcs->cpu != cpu)
2127                 loaded_vmcs_clear(vmx->loaded_vmcs);
2128
2129         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2130                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2131                 vmcs_load(vmx->loaded_vmcs->vmcs);
2132         }
2133
2134         if (vmx->loaded_vmcs->cpu != cpu) {
2135                 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2136                 unsigned long sysenter_esp;
2137
2138                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2139                 local_irq_disable();
2140                 crash_disable_local_vmclear(cpu);
2141
2142                 /*
2143                  * Read loaded_vmcs->cpu should be before fetching
2144                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2145                  * See the comments in __loaded_vmcs_clear().
2146                  */
2147                 smp_rmb();
2148
2149                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2150                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2151                 crash_enable_local_vmclear(cpu);
2152                 local_irq_enable();
2153
2154                 /*
2155                  * Linux uses per-cpu TSS and GDT, so set these when switching
2156                  * processors.
2157                  */
2158                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
2159                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
2160
2161                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2162                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2163
2164                 vmx->loaded_vmcs->cpu = cpu;
2165         }
2166
2167         /* Setup TSC multiplier */
2168         if (kvm_has_tsc_control &&
2169             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio) {
2170                 vmx->current_tsc_ratio = vcpu->arch.tsc_scaling_ratio;
2171                 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2172         }
2173
2174         vmx_vcpu_pi_load(vcpu, cpu);
2175         vmx->host_pkru = read_pkru();
2176 }
2177
2178 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2179 {
2180         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2181
2182         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2183                 !irq_remapping_cap(IRQ_POSTING_CAP))
2184                 return;
2185
2186         /* Set SN when the vCPU is preempted */
2187         if (vcpu->preempted)
2188                 pi_set_sn(pi_desc);
2189 }
2190
2191 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2192 {
2193         vmx_vcpu_pi_put(vcpu);
2194
2195         __vmx_load_host_state(to_vmx(vcpu));
2196         if (!vmm_exclusive) {
2197                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2198                 vcpu->cpu = -1;
2199                 kvm_cpu_vmxoff();
2200         }
2201 }
2202
2203 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
2204 {
2205         ulong cr0;
2206
2207         if (vcpu->fpu_active)
2208                 return;
2209         vcpu->fpu_active = 1;
2210         cr0 = vmcs_readl(GUEST_CR0);
2211         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
2212         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
2213         vmcs_writel(GUEST_CR0, cr0);
2214         update_exception_bitmap(vcpu);
2215         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
2216         if (is_guest_mode(vcpu))
2217                 vcpu->arch.cr0_guest_owned_bits &=
2218                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
2219         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2220 }
2221
2222 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2223
2224 /*
2225  * Return the cr0 value that a nested guest would read. This is a combination
2226  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2227  * its hypervisor (cr0_read_shadow).
2228  */
2229 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2230 {
2231         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2232                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2233 }
2234 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2235 {
2236         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2237                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2238 }
2239
2240 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
2241 {
2242         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2243          * set this *before* calling this function.
2244          */
2245         vmx_decache_cr0_guest_bits(vcpu);
2246         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
2247         update_exception_bitmap(vcpu);
2248         vcpu->arch.cr0_guest_owned_bits = 0;
2249         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2250         if (is_guest_mode(vcpu)) {
2251                 /*
2252                  * L1's specified read shadow might not contain the TS bit,
2253                  * so now that we turned on shadowing of this bit, we need to
2254                  * set this bit of the shadow. Like in nested_vmx_run we need
2255                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2256                  * up-to-date here because we just decached cr0.TS (and we'll
2257                  * only update vmcs12->guest_cr0 on nested exit).
2258                  */
2259                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2260                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2261                         (vcpu->arch.cr0 & X86_CR0_TS);
2262                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2263         } else
2264                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2265 }
2266
2267 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2268 {
2269         unsigned long rflags, save_rflags;
2270
2271         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2272                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2273                 rflags = vmcs_readl(GUEST_RFLAGS);
2274                 if (to_vmx(vcpu)->rmode.vm86_active) {
2275                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2276                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2277                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2278                 }
2279                 to_vmx(vcpu)->rflags = rflags;
2280         }
2281         return to_vmx(vcpu)->rflags;
2282 }
2283
2284 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2285 {
2286         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2287         to_vmx(vcpu)->rflags = rflags;
2288         if (to_vmx(vcpu)->rmode.vm86_active) {
2289                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2290                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2291         }
2292         vmcs_writel(GUEST_RFLAGS, rflags);
2293 }
2294
2295 static u32 vmx_get_pkru(struct kvm_vcpu *vcpu)
2296 {
2297         return to_vmx(vcpu)->guest_pkru;
2298 }
2299
2300 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2301 {
2302         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2303         int ret = 0;
2304
2305         if (interruptibility & GUEST_INTR_STATE_STI)
2306                 ret |= KVM_X86_SHADOW_INT_STI;
2307         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2308                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2309
2310         return ret;
2311 }
2312
2313 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2314 {
2315         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2316         u32 interruptibility = interruptibility_old;
2317
2318         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2319
2320         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2321                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2322         else if (mask & KVM_X86_SHADOW_INT_STI)
2323                 interruptibility |= GUEST_INTR_STATE_STI;
2324
2325         if ((interruptibility != interruptibility_old))
2326                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2327 }
2328
2329 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2330 {
2331         unsigned long rip;
2332
2333         rip = kvm_rip_read(vcpu);
2334         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2335         kvm_rip_write(vcpu, rip);
2336
2337         /* skipping an emulated instruction also counts */
2338         vmx_set_interrupt_shadow(vcpu, 0);
2339 }
2340
2341 /*
2342  * KVM wants to inject page-faults which it got to the guest. This function
2343  * checks whether in a nested guest, we need to inject them to L1 or L2.
2344  */
2345 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2346 {
2347         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2348
2349         if (!(vmcs12->exception_bitmap & (1u << nr)))
2350                 return 0;
2351
2352         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2353                           vmcs_read32(VM_EXIT_INTR_INFO),
2354                           vmcs_readl(EXIT_QUALIFICATION));
2355         return 1;
2356 }
2357
2358 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2359                                 bool has_error_code, u32 error_code,
2360                                 bool reinject)
2361 {
2362         struct vcpu_vmx *vmx = to_vmx(vcpu);
2363         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2364
2365         if (!reinject && is_guest_mode(vcpu) &&
2366             nested_vmx_check_exception(vcpu, nr))
2367                 return;
2368
2369         if (has_error_code) {
2370                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2371                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2372         }
2373
2374         if (vmx->rmode.vm86_active) {
2375                 int inc_eip = 0;
2376                 if (kvm_exception_is_soft(nr))
2377                         inc_eip = vcpu->arch.event_exit_inst_len;
2378                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2379                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2380                 return;
2381         }
2382
2383         if (kvm_exception_is_soft(nr)) {
2384                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2385                              vmx->vcpu.arch.event_exit_inst_len);
2386                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2387         } else
2388                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2389
2390         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2391 }
2392
2393 static bool vmx_rdtscp_supported(void)
2394 {
2395         return cpu_has_vmx_rdtscp();
2396 }
2397
2398 static bool vmx_invpcid_supported(void)
2399 {
2400         return cpu_has_vmx_invpcid() && enable_ept;
2401 }
2402
2403 /*
2404  * Swap MSR entry in host/guest MSR entry array.
2405  */
2406 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2407 {
2408         struct shared_msr_entry tmp;
2409
2410         tmp = vmx->guest_msrs[to];
2411         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2412         vmx->guest_msrs[from] = tmp;
2413 }
2414
2415 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2416 {
2417         unsigned long *msr_bitmap;
2418
2419         if (is_guest_mode(vcpu))
2420                 msr_bitmap = vmx_msr_bitmap_nested;
2421         else if (vcpu->arch.apic_base & X2APIC_ENABLE) {
2422                 if (is_long_mode(vcpu))
2423                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2424                 else
2425                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2426         } else {
2427                 if (is_long_mode(vcpu))
2428                         msr_bitmap = vmx_msr_bitmap_longmode;
2429                 else
2430                         msr_bitmap = vmx_msr_bitmap_legacy;
2431         }
2432
2433         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2434 }
2435
2436 /*
2437  * Set up the vmcs to automatically save and restore system
2438  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2439  * mode, as fiddling with msrs is very expensive.
2440  */
2441 static void setup_msrs(struct vcpu_vmx *vmx)
2442 {
2443         int save_nmsrs, index;
2444
2445         save_nmsrs = 0;
2446 #ifdef CONFIG_X86_64
2447         if (is_long_mode(&vmx->vcpu)) {
2448                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2449                 if (index >= 0)
2450                         move_msr_up(vmx, index, save_nmsrs++);
2451                 index = __find_msr_index(vmx, MSR_LSTAR);
2452                 if (index >= 0)
2453                         move_msr_up(vmx, index, save_nmsrs++);
2454                 index = __find_msr_index(vmx, MSR_CSTAR);
2455                 if (index >= 0)
2456                         move_msr_up(vmx, index, save_nmsrs++);
2457                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2458                 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2459                         move_msr_up(vmx, index, save_nmsrs++);
2460                 /*
2461                  * MSR_STAR is only needed on long mode guests, and only
2462                  * if efer.sce is enabled.
2463                  */
2464                 index = __find_msr_index(vmx, MSR_STAR);
2465                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2466                         move_msr_up(vmx, index, save_nmsrs++);
2467         }
2468 #endif
2469         index = __find_msr_index(vmx, MSR_EFER);
2470         if (index >= 0 && update_transition_efer(vmx, index))
2471                 move_msr_up(vmx, index, save_nmsrs++);
2472
2473         vmx->save_nmsrs = save_nmsrs;
2474
2475         if (cpu_has_vmx_msr_bitmap())
2476                 vmx_set_msr_bitmap(&vmx->vcpu);
2477 }
2478
2479 /*
2480  * reads and returns guest's timestamp counter "register"
2481  * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2482  * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2483  */
2484 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2485 {
2486         u64 host_tsc, tsc_offset;
2487
2488         host_tsc = rdtsc();
2489         tsc_offset = vmcs_read64(TSC_OFFSET);
2490         return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2491 }
2492
2493 /*
2494  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2495  * counter, even if a nested guest (L2) is currently running.
2496  */
2497 static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2498 {
2499         u64 tsc_offset;
2500
2501         tsc_offset = is_guest_mode(vcpu) ?
2502                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2503                 vmcs_read64(TSC_OFFSET);
2504         return host_tsc + tsc_offset;
2505 }
2506
2507 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2508 {
2509         return vmcs_read64(TSC_OFFSET);
2510 }
2511
2512 /*
2513  * writes 'offset' into guest's timestamp counter offset register
2514  */
2515 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2516 {
2517         if (is_guest_mode(vcpu)) {
2518                 /*
2519                  * We're here if L1 chose not to trap WRMSR to TSC. According
2520                  * to the spec, this should set L1's TSC; The offset that L1
2521                  * set for L2 remains unchanged, and still needs to be added
2522                  * to the newly set TSC to get L2's TSC.
2523                  */
2524                 struct vmcs12 *vmcs12;
2525                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2526                 /* recalculate vmcs02.TSC_OFFSET: */
2527                 vmcs12 = get_vmcs12(vcpu);
2528                 vmcs_write64(TSC_OFFSET, offset +
2529                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2530                          vmcs12->tsc_offset : 0));
2531         } else {
2532                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2533                                            vmcs_read64(TSC_OFFSET), offset);
2534                 vmcs_write64(TSC_OFFSET, offset);
2535         }
2536 }
2537
2538 static void vmx_adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, s64 adjustment)
2539 {
2540         u64 offset = vmcs_read64(TSC_OFFSET);
2541
2542         vmcs_write64(TSC_OFFSET, offset + adjustment);
2543         if (is_guest_mode(vcpu)) {
2544                 /* Even when running L2, the adjustment needs to apply to L1 */
2545                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2546         } else
2547                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2548                                            offset + adjustment);
2549 }
2550
2551 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2552 {
2553         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2554         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2555 }
2556
2557 /*
2558  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2559  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2560  * all guests if the "nested" module option is off, and can also be disabled
2561  * for a single guest by disabling its VMX cpuid bit.
2562  */
2563 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2564 {
2565         return nested && guest_cpuid_has_vmx(vcpu);
2566 }
2567
2568 /*
2569  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2570  * returned for the various VMX controls MSRs when nested VMX is enabled.
2571  * The same values should also be used to verify that vmcs12 control fields are
2572  * valid during nested entry from L1 to L2.
2573  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2574  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2575  * bit in the high half is on if the corresponding bit in the control field
2576  * may be on. See also vmx_control_verify().
2577  */
2578 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2579 {
2580         /*
2581          * Note that as a general rule, the high half of the MSRs (bits in
2582          * the control fields which may be 1) should be initialized by the
2583          * intersection of the underlying hardware's MSR (i.e., features which
2584          * can be supported) and the list of features we want to expose -
2585          * because they are known to be properly supported in our code.
2586          * Also, usually, the low half of the MSRs (bits which must be 1) can
2587          * be set to 0, meaning that L1 may turn off any of these bits. The
2588          * reason is that if one of these bits is necessary, it will appear
2589          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2590          * fields of vmcs01 and vmcs02, will turn these bits off - and
2591          * nested_vmx_exit_handled() will not pass related exits to L1.
2592          * These rules have exceptions below.
2593          */
2594
2595         /* pin-based controls */
2596         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2597                 vmx->nested.nested_vmx_pinbased_ctls_low,
2598                 vmx->nested.nested_vmx_pinbased_ctls_high);
2599         vmx->nested.nested_vmx_pinbased_ctls_low |=
2600                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2601         vmx->nested.nested_vmx_pinbased_ctls_high &=
2602                 PIN_BASED_EXT_INTR_MASK |
2603                 PIN_BASED_NMI_EXITING |
2604                 PIN_BASED_VIRTUAL_NMIS;
2605         vmx->nested.nested_vmx_pinbased_ctls_high |=
2606                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2607                 PIN_BASED_VMX_PREEMPTION_TIMER;
2608         if (kvm_vcpu_apicv_active(&vmx->vcpu))
2609                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2610                         PIN_BASED_POSTED_INTR;
2611
2612         /* exit controls */
2613         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2614                 vmx->nested.nested_vmx_exit_ctls_low,
2615                 vmx->nested.nested_vmx_exit_ctls_high);
2616         vmx->nested.nested_vmx_exit_ctls_low =
2617                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2618
2619         vmx->nested.nested_vmx_exit_ctls_high &=
2620 #ifdef CONFIG_X86_64
2621                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2622 #endif
2623                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2624         vmx->nested.nested_vmx_exit_ctls_high |=
2625                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2626                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2627                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2628
2629         if (kvm_mpx_supported())
2630                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2631
2632         /* We support free control of debug control saving. */
2633         vmx->nested.nested_vmx_true_exit_ctls_low =
2634                 vmx->nested.nested_vmx_exit_ctls_low &
2635                 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2636
2637         /* entry controls */
2638         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2639                 vmx->nested.nested_vmx_entry_ctls_low,
2640                 vmx->nested.nested_vmx_entry_ctls_high);
2641         vmx->nested.nested_vmx_entry_ctls_low =
2642                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2643         vmx->nested.nested_vmx_entry_ctls_high &=
2644 #ifdef CONFIG_X86_64
2645                 VM_ENTRY_IA32E_MODE |
2646 #endif
2647                 VM_ENTRY_LOAD_IA32_PAT;
2648         vmx->nested.nested_vmx_entry_ctls_high |=
2649                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2650         if (kvm_mpx_supported())
2651                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2652
2653         /* We support free control of debug control loading. */
2654         vmx->nested.nested_vmx_true_entry_ctls_low =
2655                 vmx->nested.nested_vmx_entry_ctls_low &
2656                 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2657
2658         /* cpu-based controls */
2659         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2660                 vmx->nested.nested_vmx_procbased_ctls_low,
2661                 vmx->nested.nested_vmx_procbased_ctls_high);
2662         vmx->nested.nested_vmx_procbased_ctls_low =
2663                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2664         vmx->nested.nested_vmx_procbased_ctls_high &=
2665                 CPU_BASED_VIRTUAL_INTR_PENDING |
2666                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2667                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2668                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2669                 CPU_BASED_CR3_STORE_EXITING |
2670 #ifdef CONFIG_X86_64
2671                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2672 #endif
2673                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2674                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2675                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2676                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2677                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2678         /*
2679          * We can allow some features even when not supported by the
2680          * hardware. For example, L1 can specify an MSR bitmap - and we
2681          * can use it to avoid exits to L1 - even when L0 runs L2
2682          * without MSR bitmaps.
2683          */
2684         vmx->nested.nested_vmx_procbased_ctls_high |=
2685                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2686                 CPU_BASED_USE_MSR_BITMAPS;
2687
2688         /* We support free control of CR3 access interception. */
2689         vmx->nested.nested_vmx_true_procbased_ctls_low =
2690                 vmx->nested.nested_vmx_procbased_ctls_low &
2691                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2692
2693         /* secondary cpu-based controls */
2694         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2695                 vmx->nested.nested_vmx_secondary_ctls_low,
2696                 vmx->nested.nested_vmx_secondary_ctls_high);
2697         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2698         vmx->nested.nested_vmx_secondary_ctls_high &=
2699                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2700                 SECONDARY_EXEC_RDTSCP |
2701                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2702                 SECONDARY_EXEC_ENABLE_VPID |
2703                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2704                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2705                 SECONDARY_EXEC_WBINVD_EXITING |
2706                 SECONDARY_EXEC_XSAVES |
2707                 SECONDARY_EXEC_PCOMMIT;
2708
2709         if (enable_ept) {
2710                 /* nested EPT: emulate EPT also to L1 */
2711                 vmx->nested.nested_vmx_secondary_ctls_high |=
2712                         SECONDARY_EXEC_ENABLE_EPT;
2713                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2714                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2715                          VMX_EPT_INVEPT_BIT;
2716                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2717                 /*
2718                  * For nested guests, we don't do anything specific
2719                  * for single context invalidation. Hence, only advertise
2720                  * support for global context invalidation.
2721                  */
2722                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
2723         } else
2724                 vmx->nested.nested_vmx_ept_caps = 0;
2725
2726         /*
2727          * Old versions of KVM use the single-context version without
2728          * checking for support, so declare that it is supported even
2729          * though it is treated as global context.  The alternative is
2730          * not failing the single-context invvpid, and it is worse.
2731          */
2732         if (enable_vpid)
2733                 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2734                                 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |
2735                                 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
2736         else
2737                 vmx->nested.nested_vmx_vpid_caps = 0;
2738
2739         if (enable_unrestricted_guest)
2740                 vmx->nested.nested_vmx_secondary_ctls_high |=
2741                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2742
2743         /* miscellaneous data */
2744         rdmsr(MSR_IA32_VMX_MISC,
2745                 vmx->nested.nested_vmx_misc_low,
2746                 vmx->nested.nested_vmx_misc_high);
2747         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2748         vmx->nested.nested_vmx_misc_low |=
2749                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2750                 VMX_MISC_ACTIVITY_HLT;
2751         vmx->nested.nested_vmx_misc_high = 0;
2752 }
2753
2754 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2755 {
2756         /*
2757          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2758          */
2759         return ((control & high) | low) == control;
2760 }
2761
2762 static inline u64 vmx_control_msr(u32 low, u32 high)
2763 {
2764         return low | ((u64)high << 32);
2765 }
2766
2767 /* Returns 0 on success, non-0 otherwise. */
2768 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2769 {
2770         struct vcpu_vmx *vmx = to_vmx(vcpu);
2771
2772         switch (msr_index) {
2773         case MSR_IA32_VMX_BASIC:
2774                 /*
2775                  * This MSR reports some information about VMX support. We
2776                  * should return information about the VMX we emulate for the
2777                  * guest, and the VMCS structure we give it - not about the
2778                  * VMX support of the underlying hardware.
2779                  */
2780                 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2781                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2782                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2783                 break;
2784         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2785         case MSR_IA32_VMX_PINBASED_CTLS:
2786                 *pdata = vmx_control_msr(
2787                         vmx->nested.nested_vmx_pinbased_ctls_low,
2788                         vmx->nested.nested_vmx_pinbased_ctls_high);
2789                 break;
2790         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2791                 *pdata = vmx_control_msr(
2792                         vmx->nested.nested_vmx_true_procbased_ctls_low,
2793                         vmx->nested.nested_vmx_procbased_ctls_high);
2794                 break;
2795         case MSR_IA32_VMX_PROCBASED_CTLS:
2796                 *pdata = vmx_control_msr(
2797                         vmx->nested.nested_vmx_procbased_ctls_low,
2798                         vmx->nested.nested_vmx_procbased_ctls_high);
2799                 break;
2800         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2801                 *pdata = vmx_control_msr(
2802                         vmx->nested.nested_vmx_true_exit_ctls_low,
2803                         vmx->nested.nested_vmx_exit_ctls_high);
2804                 break;
2805         case MSR_IA32_VMX_EXIT_CTLS:
2806                 *pdata = vmx_control_msr(
2807                         vmx->nested.nested_vmx_exit_ctls_low,
2808                         vmx->nested.nested_vmx_exit_ctls_high);
2809                 break;
2810         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2811                 *pdata = vmx_control_msr(
2812                         vmx->nested.nested_vmx_true_entry_ctls_low,
2813                         vmx->nested.nested_vmx_entry_ctls_high);
2814                 break;
2815         case MSR_IA32_VMX_ENTRY_CTLS:
2816                 *pdata = vmx_control_msr(
2817                         vmx->nested.nested_vmx_entry_ctls_low,
2818                         vmx->nested.nested_vmx_entry_ctls_high);
2819                 break;
2820         case MSR_IA32_VMX_MISC:
2821                 *pdata = vmx_control_msr(
2822                         vmx->nested.nested_vmx_misc_low,
2823                         vmx->nested.nested_vmx_misc_high);
2824                 break;
2825         /*
2826          * These MSRs specify bits which the guest must keep fixed (on or off)
2827          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2828          * We picked the standard core2 setting.
2829          */
2830 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2831 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2832         case MSR_IA32_VMX_CR0_FIXED0:
2833                 *pdata = VMXON_CR0_ALWAYSON;
2834                 break;
2835         case MSR_IA32_VMX_CR0_FIXED1:
2836                 *pdata = -1ULL;
2837                 break;
2838         case MSR_IA32_VMX_CR4_FIXED0:
2839                 *pdata = VMXON_CR4_ALWAYSON;
2840                 break;
2841         case MSR_IA32_VMX_CR4_FIXED1:
2842                 *pdata = -1ULL;
2843                 break;
2844         case MSR_IA32_VMX_VMCS_ENUM:
2845                 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2846                 break;
2847         case MSR_IA32_VMX_PROCBASED_CTLS2:
2848                 *pdata = vmx_control_msr(
2849                         vmx->nested.nested_vmx_secondary_ctls_low,
2850                         vmx->nested.nested_vmx_secondary_ctls_high);
2851                 break;
2852         case MSR_IA32_VMX_EPT_VPID_CAP:
2853                 /* Currently, no nested vpid support */
2854                 *pdata = vmx->nested.nested_vmx_ept_caps |
2855                         ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
2856                 break;
2857         default:
2858                 return 1;
2859         }
2860
2861         return 0;
2862 }
2863
2864 /*
2865  * Reads an msr value (of 'msr_index') into 'pdata'.
2866  * Returns 0 on success, non-0 otherwise.
2867  * Assumes vcpu_load() was already called.
2868  */
2869 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2870 {
2871         struct shared_msr_entry *msr;
2872
2873         switch (msr_info->index) {
2874 #ifdef CONFIG_X86_64
2875         case MSR_FS_BASE:
2876                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
2877                 break;
2878         case MSR_GS_BASE:
2879                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
2880                 break;
2881         case MSR_KERNEL_GS_BASE:
2882                 vmx_load_host_state(to_vmx(vcpu));
2883                 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2884                 break;
2885 #endif
2886         case MSR_EFER:
2887                 return kvm_get_msr_common(vcpu, msr_info);
2888         case MSR_IA32_TSC:
2889                 msr_info->data = guest_read_tsc(vcpu);
2890                 break;
2891         case MSR_IA32_SYSENTER_CS:
2892                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
2893                 break;
2894         case MSR_IA32_SYSENTER_EIP:
2895                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
2896                 break;
2897         case MSR_IA32_SYSENTER_ESP:
2898                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
2899                 break;
2900         case MSR_IA32_BNDCFGS:
2901                 if (!kvm_mpx_supported())
2902                         return 1;
2903                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
2904                 break;
2905         case MSR_IA32_FEATURE_CONTROL:
2906                 if (!nested_vmx_allowed(vcpu))
2907                         return 1;
2908                 msr_info->data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2909                 break;
2910         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2911                 if (!nested_vmx_allowed(vcpu))
2912                         return 1;
2913                 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
2914         case MSR_IA32_XSS:
2915                 if (!vmx_xsaves_supported())
2916                         return 1;
2917                 msr_info->data = vcpu->arch.ia32_xss;
2918                 break;
2919         case MSR_TSC_AUX:
2920                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
2921                         return 1;
2922                 /* Otherwise falls through */
2923         default:
2924                 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
2925                 if (msr) {
2926                         msr_info->data = msr->data;
2927                         break;
2928                 }
2929                 return kvm_get_msr_common(vcpu, msr_info);
2930         }
2931
2932         return 0;
2933 }
2934
2935 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2936
2937 /*
2938  * Writes msr value into into the appropriate "register".
2939  * Returns 0 on success, non-0 otherwise.
2940  * Assumes vcpu_load() was already called.
2941  */
2942 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2943 {
2944         struct vcpu_vmx *vmx = to_vmx(vcpu);
2945         struct shared_msr_entry *msr;
2946         int ret = 0;
2947         u32 msr_index = msr_info->index;
2948         u64 data = msr_info->data;
2949
2950         switch (msr_index) {
2951         case MSR_EFER:
2952                 ret = kvm_set_msr_common(vcpu, msr_info);
2953                 break;
2954 #ifdef CONFIG_X86_64
2955         case MSR_FS_BASE:
2956                 vmx_segment_cache_clear(vmx);
2957                 vmcs_writel(GUEST_FS_BASE, data);
2958                 break;
2959         case MSR_GS_BASE:
2960                 vmx_segment_cache_clear(vmx);
2961                 vmcs_writel(GUEST_GS_BASE, data);
2962                 break;
2963         case MSR_KERNEL_GS_BASE:
2964                 vmx_load_host_state(vmx);
2965                 vmx->msr_guest_kernel_gs_base = data;
2966                 break;
2967 #endif
2968         case MSR_IA32_SYSENTER_CS:
2969                 vmcs_write32(GUEST_SYSENTER_CS, data);
2970                 break;
2971         case MSR_IA32_SYSENTER_EIP:
2972                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2973                 break;
2974         case MSR_IA32_SYSENTER_ESP:
2975                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2976                 break;
2977         case MSR_IA32_BNDCFGS:
2978                 if (!kvm_mpx_supported())
2979                         return 1;
2980                 vmcs_write64(GUEST_BNDCFGS, data);
2981                 break;
2982         case MSR_IA32_TSC:
2983                 kvm_write_tsc(vcpu, msr_info);
2984                 break;
2985         case MSR_IA32_CR_PAT:
2986                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2987                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2988                                 return 1;
2989                         vmcs_write64(GUEST_IA32_PAT, data);
2990                         vcpu->arch.pat = data;
2991                         break;
2992                 }
2993                 ret = kvm_set_msr_common(vcpu, msr_info);
2994                 break;
2995         case MSR_IA32_TSC_ADJUST:
2996                 ret = kvm_set_msr_common(vcpu, msr_info);
2997                 break;
2998         case MSR_IA32_FEATURE_CONTROL:
2999                 if (!nested_vmx_allowed(vcpu) ||
3000                     (to_vmx(vcpu)->nested.msr_ia32_feature_control &
3001                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3002                         return 1;
3003                 vmx->nested.msr_ia32_feature_control = data;
3004                 if (msr_info->host_initiated && data == 0)
3005                         vmx_leave_nested(vcpu);
3006                 break;
3007         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3008                 return 1; /* they are read-only */
3009         case MSR_IA32_XSS:
3010                 if (!vmx_xsaves_supported())
3011                         return 1;
3012                 /*
3013                  * The only supported bit as of Skylake is bit 8, but
3014                  * it is not supported on KVM.
3015                  */
3016                 if (data != 0)
3017                         return 1;
3018                 vcpu->arch.ia32_xss = data;
3019                 if (vcpu->arch.ia32_xss != host_xss)
3020                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3021                                 vcpu->arch.ia32_xss, host_xss);
3022                 else
3023                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3024                 break;
3025         case MSR_TSC_AUX:
3026                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3027                         return 1;
3028                 /* Check reserved bit, higher 32 bits should be zero */
3029                 if ((data >> 32) != 0)
3030                         return 1;
3031                 /* Otherwise falls through */
3032         default:
3033                 msr = find_msr_entry(vmx, msr_index);
3034                 if (msr) {
3035                         u64 old_msr_data = msr->data;
3036                         msr->data = data;
3037                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3038                                 preempt_disable();
3039                                 ret = kvm_set_shared_msr(msr->index, msr->data,
3040                                                          msr->mask);
3041                                 preempt_enable();
3042                                 if (ret)
3043                                         msr->data = old_msr_data;
3044                         }
3045                         break;
3046                 }
3047                 ret = kvm_set_msr_common(vcpu, msr_info);
3048         }
3049
3050         return ret;
3051 }
3052
3053 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3054 {
3055         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3056         switch (reg) {
3057         case VCPU_REGS_RSP:
3058                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3059                 break;
3060         case VCPU_REGS_RIP:
3061                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3062                 break;
3063         case VCPU_EXREG_PDPTR:
3064                 if (enable_ept)
3065                         ept_save_pdptrs(vcpu);
3066                 break;
3067         default:
3068                 break;
3069         }
3070 }
3071
3072 static __init int cpu_has_kvm_support(void)
3073 {
3074         return cpu_has_vmx();
3075 }
3076
3077 static __init int vmx_disabled_by_bios(void)
3078 {
3079         u64 msr;
3080
3081         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3082         if (msr & FEATURE_CONTROL_LOCKED) {
3083                 /* launched w/ TXT and VMX disabled */
3084                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3085                         && tboot_enabled())
3086                         return 1;
3087                 /* launched w/o TXT and VMX only enabled w/ TXT */
3088                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3089                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3090                         && !tboot_enabled()) {
3091                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3092                                 "activate TXT before enabling KVM\n");
3093                         return 1;
3094                 }
3095                 /* launched w/o TXT and VMX disabled */
3096                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3097                         && !tboot_enabled())
3098                         return 1;
3099         }
3100
3101         return 0;
3102 }
3103
3104 static void kvm_cpu_vmxon(u64 addr)
3105 {
3106         asm volatile (ASM_VMX_VMXON_RAX
3107                         : : "a"(&addr), "m"(addr)
3108                         : "memory", "cc");
3109 }
3110
3111 static int hardware_enable(void)
3112 {
3113         int cpu = raw_smp_processor_id();
3114         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3115         u64 old, test_bits;
3116
3117         if (cr4_read_shadow() & X86_CR4_VMXE)
3118                 return -EBUSY;
3119
3120         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3121         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3122         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3123
3124         /*
3125          * Now we can enable the vmclear operation in kdump
3126          * since the loaded_vmcss_on_cpu list on this cpu
3127          * has been initialized.
3128          *
3129          * Though the cpu is not in VMX operation now, there
3130          * is no problem to enable the vmclear operation
3131          * for the loaded_vmcss_on_cpu list is empty!
3132          */
3133         crash_enable_local_vmclear(cpu);
3134
3135         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3136
3137         test_bits = FEATURE_CONTROL_LOCKED;
3138         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3139         if (tboot_enabled())
3140                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3141
3142         if ((old & test_bits) != test_bits) {
3143                 /* enable and lock */
3144                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3145         }
3146         cr4_set_bits(X86_CR4_VMXE);
3147
3148         if (vmm_exclusive) {
3149                 kvm_cpu_vmxon(phys_addr);
3150                 ept_sync_global();
3151         }
3152
3153         native_store_gdt(this_cpu_ptr(&host_gdt));
3154
3155         return 0;
3156 }
3157
3158 static void vmclear_local_loaded_vmcss(void)
3159 {
3160         int cpu = raw_smp_processor_id();
3161         struct loaded_vmcs *v, *n;
3162
3163         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3164                                  loaded_vmcss_on_cpu_link)
3165                 __loaded_vmcs_clear(v);
3166 }
3167
3168
3169 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3170  * tricks.
3171  */
3172 static void kvm_cpu_vmxoff(void)
3173 {
3174         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3175 }
3176
3177 static void hardware_disable(void)
3178 {
3179         if (vmm_exclusive) {
3180                 vmclear_local_loaded_vmcss();
3181                 kvm_cpu_vmxoff();
3182         }
3183         cr4_clear_bits(X86_CR4_VMXE);
3184 }
3185
3186 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3187                                       u32 msr, u32 *result)
3188 {
3189         u32 vmx_msr_low, vmx_msr_high;
3190         u32 ctl = ctl_min | ctl_opt;
3191
3192         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3193
3194         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3195         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3196
3197         /* Ensure minimum (required) set of control bits are supported. */
3198         if (ctl_min & ~ctl)
3199                 return -EIO;
3200
3201         *result = ctl;
3202         return 0;
3203 }
3204
3205 static __init bool allow_1_setting(u32 msr, u32 ctl)
3206 {
3207         u32 vmx_msr_low, vmx_msr_high;
3208
3209         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3210         return vmx_msr_high & ctl;
3211 }
3212
3213 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3214 {
3215         u32 vmx_msr_low, vmx_msr_high;
3216         u32 min, opt, min2, opt2;
3217         u32 _pin_based_exec_control = 0;
3218         u32 _cpu_based_exec_control = 0;
3219         u32 _cpu_based_2nd_exec_control = 0;
3220         u32 _vmexit_control = 0;
3221         u32 _vmentry_control = 0;
3222
3223         min = CPU_BASED_HLT_EXITING |
3224 #ifdef CONFIG_X86_64
3225               CPU_BASED_CR8_LOAD_EXITING |
3226               CPU_BASED_CR8_STORE_EXITING |
3227 #endif
3228               CPU_BASED_CR3_LOAD_EXITING |
3229               CPU_BASED_CR3_STORE_EXITING |
3230               CPU_BASED_USE_IO_BITMAPS |
3231               CPU_BASED_MOV_DR_EXITING |
3232               CPU_BASED_USE_TSC_OFFSETING |
3233               CPU_BASED_MWAIT_EXITING |
3234               CPU_BASED_MONITOR_EXITING |
3235               CPU_BASED_INVLPG_EXITING |
3236               CPU_BASED_RDPMC_EXITING;
3237
3238         opt = CPU_BASED_TPR_SHADOW |
3239               CPU_BASED_USE_MSR_BITMAPS |
3240               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3241         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3242                                 &_cpu_based_exec_control) < 0)
3243                 return -EIO;
3244 #ifdef CONFIG_X86_64
3245         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3246                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3247                                            ~CPU_BASED_CR8_STORE_EXITING;
3248 #endif
3249         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3250                 min2 = 0;
3251                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3252                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3253                         SECONDARY_EXEC_WBINVD_EXITING |
3254                         SECONDARY_EXEC_ENABLE_VPID |
3255                         SECONDARY_EXEC_ENABLE_EPT |
3256                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3257                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3258                         SECONDARY_EXEC_RDTSCP |
3259                         SECONDARY_EXEC_ENABLE_INVPCID |
3260                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3261                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3262                         SECONDARY_EXEC_SHADOW_VMCS |
3263                         SECONDARY_EXEC_XSAVES |
3264                         SECONDARY_EXEC_ENABLE_PML |
3265                         SECONDARY_EXEC_PCOMMIT |
3266                         SECONDARY_EXEC_TSC_SCALING;
3267                 if (adjust_vmx_controls(min2, opt2,
3268                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3269                                         &_cpu_based_2nd_exec_control) < 0)
3270                         return -EIO;
3271         }
3272 #ifndef CONFIG_X86_64
3273         if (!(_cpu_based_2nd_exec_control &
3274                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3275                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3276 #endif
3277
3278         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3279                 _cpu_based_2nd_exec_control &= ~(
3280                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3281                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3282                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3283
3284         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3285                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3286                    enabled */
3287                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3288                                              CPU_BASED_CR3_STORE_EXITING |
3289                                              CPU_BASED_INVLPG_EXITING);
3290                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3291                       vmx_capability.ept, vmx_capability.vpid);
3292         }
3293
3294         min = VM_EXIT_SAVE_DEBUG_CONTROLS;
3295 #ifdef CONFIG_X86_64
3296         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3297 #endif
3298         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3299                 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
3300         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3301                                 &_vmexit_control) < 0)
3302                 return -EIO;
3303
3304         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3305         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3306         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3307                                 &_pin_based_exec_control) < 0)
3308                 return -EIO;
3309
3310         if (!(_cpu_based_2nd_exec_control &
3311                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3312                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3313                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3314
3315         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3316         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3317         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3318                                 &_vmentry_control) < 0)
3319                 return -EIO;
3320
3321         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3322
3323         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3324         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3325                 return -EIO;
3326
3327 #ifdef CONFIG_X86_64
3328         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3329         if (vmx_msr_high & (1u<<16))
3330                 return -EIO;
3331 #endif
3332
3333         /* Require Write-Back (WB) memory type for VMCS accesses. */
3334         if (((vmx_msr_high >> 18) & 15) != 6)
3335                 return -EIO;
3336
3337         vmcs_conf->size = vmx_msr_high & 0x1fff;
3338         vmcs_conf->order = get_order(vmcs_config.size);
3339         vmcs_conf->revision_id = vmx_msr_low;
3340
3341         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3342         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3343         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3344         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3345         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3346
3347         cpu_has_load_ia32_efer =
3348                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3349                                 VM_ENTRY_LOAD_IA32_EFER)
3350                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3351                                    VM_EXIT_LOAD_IA32_EFER);
3352
3353         cpu_has_load_perf_global_ctrl =
3354                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3355                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3356                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3357                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3358
3359         /*
3360          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3361          * but due to arrata below it can't be used. Workaround is to use
3362          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3363          *
3364          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3365          *
3366          * AAK155             (model 26)
3367          * AAP115             (model 30)
3368          * AAT100             (model 37)
3369          * BC86,AAY89,BD102   (model 44)
3370          * BA97               (model 46)
3371          *
3372          */
3373         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3374                 switch (boot_cpu_data.x86_model) {
3375                 case 26:
3376                 case 30:
3377                 case 37:
3378                 case 44:
3379                 case 46:
3380                         cpu_has_load_perf_global_ctrl = false;
3381                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3382                                         "does not work properly. Using workaround\n");
3383                         break;
3384                 default:
3385                         break;
3386                 }
3387         }
3388
3389         if (cpu_has_xsaves)
3390                 rdmsrl(MSR_IA32_XSS, host_xss);
3391
3392         return 0;
3393 }
3394
3395 static struct vmcs *alloc_vmcs_cpu(int cpu)
3396 {
3397         int node = cpu_to_node(cpu);
3398         struct page *pages;
3399         struct vmcs *vmcs;
3400
3401         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3402         if (!pages)
3403                 return NULL;
3404         vmcs = page_address(pages);
3405         memset(vmcs, 0, vmcs_config.size);
3406         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3407         return vmcs;
3408 }
3409
3410 static struct vmcs *alloc_vmcs(void)
3411 {
3412         return alloc_vmcs_cpu(raw_smp_processor_id());
3413 }
3414
3415 static void free_vmcs(struct vmcs *vmcs)
3416 {
3417         free_pages((unsigned long)vmcs, vmcs_config.order);
3418 }
3419
3420 /*
3421  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3422  */
3423 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3424 {
3425         if (!loaded_vmcs->vmcs)
3426                 return;
3427         loaded_vmcs_clear(loaded_vmcs);
3428         free_vmcs(loaded_vmcs->vmcs);
3429         loaded_vmcs->vmcs = NULL;
3430 }
3431
3432 static void free_kvm_area(void)
3433 {
3434         int cpu;
3435
3436         for_each_possible_cpu(cpu) {
3437                 free_vmcs(per_cpu(vmxarea, cpu));
3438                 per_cpu(vmxarea, cpu) = NULL;
3439         }
3440 }
3441
3442 static void init_vmcs_shadow_fields(void)
3443 {
3444         int i, j;
3445
3446         /* No checks for read only fields yet */
3447
3448         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3449                 switch (shadow_read_write_fields[i]) {
3450                 case GUEST_BNDCFGS:
3451                         if (!kvm_mpx_supported())
3452                                 continue;
3453                         break;
3454                 default:
3455                         break;
3456                 }
3457
3458                 if (j < i)
3459                         shadow_read_write_fields[j] =
3460                                 shadow_read_write_fields[i];
3461                 j++;
3462         }
3463         max_shadow_read_write_fields = j;
3464
3465         /* shadowed fields guest access without vmexit */
3466         for (i = 0; i < max_shadow_read_write_fields; i++) {
3467                 clear_bit(shadow_read_write_fields[i],
3468                           vmx_vmwrite_bitmap);
3469                 clear_bit(shadow_read_write_fields[i],
3470                           vmx_vmread_bitmap);
3471         }
3472         for (i = 0; i < max_shadow_read_only_fields; i++)
3473                 clear_bit(shadow_read_only_fields[i],
3474                           vmx_vmread_bitmap);
3475 }
3476
3477 static __init int alloc_kvm_area(void)
3478 {
3479         int cpu;
3480
3481         for_each_possible_cpu(cpu) {
3482                 struct vmcs *vmcs;
3483
3484                 vmcs = alloc_vmcs_cpu(cpu);
3485                 if (!vmcs) {
3486                         free_kvm_area();
3487                         return -ENOMEM;
3488                 }
3489
3490                 per_cpu(vmxarea, cpu) = vmcs;
3491         }
3492         return 0;
3493 }
3494
3495 static bool emulation_required(struct kvm_vcpu *vcpu)
3496 {
3497         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3498 }
3499
3500 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3501                 struct kvm_segment *save)
3502 {
3503         if (!emulate_invalid_guest_state) {
3504                 /*
3505                  * CS and SS RPL should be equal during guest entry according
3506                  * to VMX spec, but in reality it is not always so. Since vcpu
3507                  * is in the middle of the transition from real mode to
3508                  * protected mode it is safe to assume that RPL 0 is a good
3509                  * default value.
3510                  */
3511                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3512                         save->selector &= ~SEGMENT_RPL_MASK;
3513                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3514                 save->s = 1;
3515         }
3516         vmx_set_segment(vcpu, save, seg);
3517 }
3518
3519 static void enter_pmode(struct kvm_vcpu *vcpu)
3520 {
3521         unsigned long flags;
3522         struct vcpu_vmx *vmx = to_vmx(vcpu);
3523
3524         /*
3525          * Update real mode segment cache. It may be not up-to-date if sement
3526          * register was written while vcpu was in a guest mode.
3527          */
3528         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3529         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3530         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3531         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3532         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3533         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3534
3535         vmx->rmode.vm86_active = 0;
3536
3537         vmx_segment_cache_clear(vmx);
3538
3539         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3540
3541         flags = vmcs_readl(GUEST_RFLAGS);
3542         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3543         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3544         vmcs_writel(GUEST_RFLAGS, flags);
3545
3546         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3547                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3548
3549         update_exception_bitmap(vcpu);
3550
3551         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3552         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3553         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3554         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3555         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3556         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3557 }
3558
3559 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3560 {
3561         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3562         struct kvm_segment var = *save;
3563
3564         var.dpl = 0x3;
3565         if (seg == VCPU_SREG_CS)
3566                 var.type = 0x3;
3567
3568         if (!emulate_invalid_guest_state) {
3569                 var.selector = var.base >> 4;
3570                 var.base = var.base & 0xffff0;
3571                 var.limit = 0xffff;
3572                 var.g = 0;
3573                 var.db = 0;
3574                 var.present = 1;
3575                 var.s = 1;
3576                 var.l = 0;
3577                 var.unusable = 0;
3578                 var.type = 0x3;
3579                 var.avl = 0;
3580                 if (save->base & 0xf)
3581                         printk_once(KERN_WARNING "kvm: segment base is not "
3582                                         "paragraph aligned when entering "
3583                                         "protected mode (seg=%d)", seg);
3584         }
3585
3586         vmcs_write16(sf->selector, var.selector);
3587         vmcs_write32(sf->base, var.base);
3588         vmcs_write32(sf->limit, var.limit);
3589         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3590 }
3591
3592 static void enter_rmode(struct kvm_vcpu *vcpu)
3593 {
3594         unsigned long flags;
3595         struct vcpu_vmx *vmx = to_vmx(vcpu);
3596
3597         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3598         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3599         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3600         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3601         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3602         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3603         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3604
3605         vmx->rmode.vm86_active = 1;
3606
3607         /*
3608          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3609          * vcpu. Warn the user that an update is overdue.
3610          */
3611         if (!vcpu->kvm->arch.tss_addr)
3612                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3613                              "called before entering vcpu\n");
3614
3615         vmx_segment_cache_clear(vmx);
3616
3617         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3618         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3619         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3620
3621         flags = vmcs_readl(GUEST_RFLAGS);
3622         vmx->rmode.save_rflags = flags;
3623
3624         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3625
3626         vmcs_writel(GUEST_RFLAGS, flags);
3627         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3628         update_exception_bitmap(vcpu);
3629
3630         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3631         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3632         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3633         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3634         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3635         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3636
3637         kvm_mmu_reset_context(vcpu);
3638 }
3639
3640 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3641 {
3642         struct vcpu_vmx *vmx = to_vmx(vcpu);
3643         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3644
3645         if (!msr)
3646                 return;
3647
3648         /*
3649          * Force kernel_gs_base reloading before EFER changes, as control
3650          * of this msr depends on is_long_mode().
3651          */
3652         vmx_load_host_state(to_vmx(vcpu));
3653         vcpu->arch.efer = efer;
3654         if (efer & EFER_LMA) {
3655                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3656                 msr->data = efer;
3657         } else {
3658                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3659
3660                 msr->data = efer & ~EFER_LME;
3661         }
3662         setup_msrs(vmx);
3663 }
3664
3665 #ifdef CONFIG_X86_64
3666
3667 static void enter_lmode(struct kvm_vcpu *vcpu)
3668 {
3669         u32 guest_tr_ar;
3670
3671         vmx_segment_cache_clear(to_vmx(vcpu));
3672
3673         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3674         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
3675                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3676                                      __func__);
3677                 vmcs_write32(GUEST_TR_AR_BYTES,
3678                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3679                              | VMX_AR_TYPE_BUSY_64_TSS);
3680         }
3681         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3682 }
3683
3684 static void exit_lmode(struct kvm_vcpu *vcpu)
3685 {
3686         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3687         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3688 }
3689
3690 #endif
3691
3692 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
3693 {
3694         vpid_sync_context(vpid);
3695         if (enable_ept) {
3696                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3697                         return;
3698                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3699         }
3700 }
3701
3702 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3703 {
3704         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
3705 }
3706
3707 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3708 {
3709         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3710
3711         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3712         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3713 }
3714
3715 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3716 {
3717         if (enable_ept && is_paging(vcpu))
3718                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3719         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3720 }
3721
3722 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3723 {
3724         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3725
3726         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3727         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3728 }
3729
3730 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3731 {
3732         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3733
3734         if (!test_bit(VCPU_EXREG_PDPTR,
3735                       (unsigned long *)&vcpu->arch.regs_dirty))
3736                 return;
3737
3738         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3739                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3740                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3741                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3742                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3743         }
3744 }
3745
3746 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3747 {
3748         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3749
3750         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3751                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3752                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3753                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3754                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3755         }
3756
3757         __set_bit(VCPU_EXREG_PDPTR,
3758                   (unsigned long *)&vcpu->arch.regs_avail);
3759         __set_bit(VCPU_EXREG_PDPTR,
3760                   (unsigned long *)&vcpu->arch.regs_dirty);
3761 }
3762
3763 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3764
3765 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3766                                         unsigned long cr0,
3767                                         struct kvm_vcpu *vcpu)
3768 {
3769         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3770                 vmx_decache_cr3(vcpu);
3771         if (!(cr0 & X86_CR0_PG)) {
3772                 /* From paging/starting to nonpaging */
3773                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3774                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3775                              (CPU_BASED_CR3_LOAD_EXITING |
3776                               CPU_BASED_CR3_STORE_EXITING));
3777                 vcpu->arch.cr0 = cr0;
3778                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3779         } else if (!is_paging(vcpu)) {
3780                 /* From nonpaging to paging */
3781                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3782                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3783                              ~(CPU_BASED_CR3_LOAD_EXITING |
3784                                CPU_BASED_CR3_STORE_EXITING));
3785                 vcpu->arch.cr0 = cr0;
3786                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3787         }
3788
3789         if (!(cr0 & X86_CR0_WP))
3790                 *hw_cr0 &= ~X86_CR0_WP;
3791 }
3792
3793 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3794 {
3795         struct vcpu_vmx *vmx = to_vmx(vcpu);
3796         unsigned long hw_cr0;
3797
3798         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3799         if (enable_unrestricted_guest)
3800                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3801         else {
3802                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3803
3804                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3805                         enter_pmode(vcpu);
3806
3807                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3808                         enter_rmode(vcpu);
3809         }
3810
3811 #ifdef CONFIG_X86_64
3812         if (vcpu->arch.efer & EFER_LME) {
3813                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3814                         enter_lmode(vcpu);
3815                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3816                         exit_lmode(vcpu);
3817         }
3818 #endif
3819
3820         if (enable_ept)
3821                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3822
3823         if (!vcpu->fpu_active)
3824                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3825
3826         vmcs_writel(CR0_READ_SHADOW, cr0);
3827         vmcs_writel(GUEST_CR0, hw_cr0);
3828         vcpu->arch.cr0 = cr0;
3829
3830         /* depends on vcpu->arch.cr0 to be set to a new value */
3831         vmx->emulation_required = emulation_required(vcpu);
3832 }
3833
3834 static u64 construct_eptp(unsigned long root_hpa)
3835 {
3836         u64 eptp;
3837
3838         /* TODO write the value reading from MSR */
3839         eptp = VMX_EPT_DEFAULT_MT |
3840                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3841         if (enable_ept_ad_bits)
3842                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3843         eptp |= (root_hpa & PAGE_MASK);
3844
3845         return eptp;
3846 }
3847
3848 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3849 {
3850         unsigned long guest_cr3;
3851         u64 eptp;
3852
3853         guest_cr3 = cr3;
3854         if (enable_ept) {
3855                 eptp = construct_eptp(cr3);
3856                 vmcs_write64(EPT_POINTER, eptp);
3857                 if (is_paging(vcpu) || is_guest_mode(vcpu))
3858                         guest_cr3 = kvm_read_cr3(vcpu);
3859                 else
3860                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3861                 ept_load_pdptrs(vcpu);
3862         }
3863
3864         vmx_flush_tlb(vcpu);
3865         vmcs_writel(GUEST_CR3, guest_cr3);
3866 }
3867
3868 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3869 {
3870         /*
3871          * Pass through host's Machine Check Enable value to hw_cr4, which
3872          * is in force while we are in guest mode.  Do not let guests control
3873          * this bit, even if host CR4.MCE == 0.
3874          */
3875         unsigned long hw_cr4 =
3876                 (cr4_read_shadow() & X86_CR4_MCE) |
3877                 (cr4 & ~X86_CR4_MCE) |
3878                 (to_vmx(vcpu)->rmode.vm86_active ?
3879                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3880
3881         if (cr4 & X86_CR4_VMXE) {
3882                 /*
3883                  * To use VMXON (and later other VMX instructions), a guest
3884                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3885                  * So basically the check on whether to allow nested VMX
3886                  * is here.
3887                  */
3888                 if (!nested_vmx_allowed(vcpu))
3889                         return 1;
3890         }
3891         if (to_vmx(vcpu)->nested.vmxon &&
3892             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3893                 return 1;
3894
3895         vcpu->arch.cr4 = cr4;
3896         if (enable_ept) {
3897                 if (!is_paging(vcpu)) {
3898                         hw_cr4 &= ~X86_CR4_PAE;
3899                         hw_cr4 |= X86_CR4_PSE;
3900                 } else if (!(cr4 & X86_CR4_PAE)) {
3901                         hw_cr4 &= ~X86_CR4_PAE;
3902                 }
3903         }
3904
3905         if (!enable_unrestricted_guest && !is_paging(vcpu))
3906                 /*
3907                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
3908                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
3909                  * to be manually disabled when guest switches to non-paging
3910                  * mode.
3911                  *
3912                  * If !enable_unrestricted_guest, the CPU is always running
3913                  * with CR0.PG=1 and CR4 needs to be modified.
3914                  * If enable_unrestricted_guest, the CPU automatically
3915                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
3916                  */
3917                 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
3918
3919         vmcs_writel(CR4_READ_SHADOW, cr4);
3920         vmcs_writel(GUEST_CR4, hw_cr4);
3921         return 0;
3922 }
3923
3924 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3925                             struct kvm_segment *var, int seg)
3926 {
3927         struct vcpu_vmx *vmx = to_vmx(vcpu);
3928         u32 ar;
3929
3930         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3931                 *var = vmx->rmode.segs[seg];
3932                 if (seg == VCPU_SREG_TR
3933                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3934                         return;
3935                 var->base = vmx_read_guest_seg_base(vmx, seg);
3936                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3937                 return;
3938         }
3939         var->base = vmx_read_guest_seg_base(vmx, seg);
3940         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3941         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3942         ar = vmx_read_guest_seg_ar(vmx, seg);
3943         var->unusable = (ar >> 16) & 1;
3944         var->type = ar & 15;
3945         var->s = (ar >> 4) & 1;
3946         var->dpl = (ar >> 5) & 3;
3947         /*
3948          * Some userspaces do not preserve unusable property. Since usable
3949          * segment has to be present according to VMX spec we can use present
3950          * property to amend userspace bug by making unusable segment always
3951          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3952          * segment as unusable.
3953          */
3954         var->present = !var->unusable;
3955         var->avl = (ar >> 12) & 1;
3956         var->l = (ar >> 13) & 1;
3957         var->db = (ar >> 14) & 1;
3958         var->g = (ar >> 15) & 1;
3959 }
3960
3961 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3962 {
3963         struct kvm_segment s;
3964
3965         if (to_vmx(vcpu)->rmode.vm86_active) {
3966                 vmx_get_segment(vcpu, &s, seg);
3967                 return s.base;
3968         }
3969         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3970 }
3971
3972 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3973 {
3974         struct vcpu_vmx *vmx = to_vmx(vcpu);
3975
3976         if (unlikely(vmx->rmode.vm86_active))
3977                 return 0;
3978         else {
3979                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3980                 return VMX_AR_DPL(ar);
3981         }
3982 }
3983
3984 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3985 {
3986         u32 ar;
3987
3988         if (var->unusable || !var->present)
3989                 ar = 1 << 16;
3990         else {
3991                 ar = var->type & 15;
3992                 ar |= (var->s & 1) << 4;
3993                 ar |= (var->dpl & 3) << 5;
3994                 ar |= (var->present & 1) << 7;
3995                 ar |= (var->avl & 1) << 12;
3996                 ar |= (var->l & 1) << 13;
3997                 ar |= (var->db & 1) << 14;
3998                 ar |= (var->g & 1) << 15;
3999         }
4000
4001         return ar;
4002 }
4003
4004 static void vmx_set_segment(struct kvm_vcpu *vcpu,
4005                             struct kvm_segment *var, int seg)
4006 {
4007         struct vcpu_vmx *vmx = to_vmx(vcpu);
4008         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4009
4010         vmx_segment_cache_clear(vmx);
4011
4012         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4013                 vmx->rmode.segs[seg] = *var;
4014                 if (seg == VCPU_SREG_TR)
4015                         vmcs_write16(sf->selector, var->selector);
4016                 else if (var->s)
4017                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
4018                 goto out;
4019         }
4020
4021         vmcs_writel(sf->base, var->base);
4022         vmcs_write32(sf->limit, var->limit);
4023         vmcs_write16(sf->selector, var->selector);
4024
4025         /*
4026          *   Fix the "Accessed" bit in AR field of segment registers for older
4027          * qemu binaries.
4028          *   IA32 arch specifies that at the time of processor reset the
4029          * "Accessed" bit in the AR field of segment registers is 1. And qemu
4030          * is setting it to 0 in the userland code. This causes invalid guest
4031          * state vmexit when "unrestricted guest" mode is turned on.
4032          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
4033          * tree. Newer qemu binaries with that qemu fix would not need this
4034          * kvm hack.
4035          */
4036         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
4037                 var->type |= 0x1; /* Accessed */
4038
4039         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
4040
4041 out:
4042         vmx->emulation_required = emulation_required(vcpu);
4043 }
4044
4045 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4046 {
4047         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4048
4049         *db = (ar >> 14) & 1;
4050         *l = (ar >> 13) & 1;
4051 }
4052
4053 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4054 {
4055         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4056         dt->address = vmcs_readl(GUEST_IDTR_BASE);
4057 }
4058
4059 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4060 {
4061         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4062         vmcs_writel(GUEST_IDTR_BASE, dt->address);
4063 }
4064
4065 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4066 {
4067         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4068         dt->address = vmcs_readl(GUEST_GDTR_BASE);
4069 }
4070
4071 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4072 {
4073         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4074         vmcs_writel(GUEST_GDTR_BASE, dt->address);
4075 }
4076
4077 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4078 {
4079         struct kvm_segment var;
4080         u32 ar;
4081
4082         vmx_get_segment(vcpu, &var, seg);
4083         var.dpl = 0x3;
4084         if (seg == VCPU_SREG_CS)
4085                 var.type = 0x3;
4086         ar = vmx_segment_access_rights(&var);
4087
4088         if (var.base != (var.selector << 4))
4089                 return false;
4090         if (var.limit != 0xffff)
4091                 return false;
4092         if (ar != 0xf3)
4093                 return false;
4094
4095         return true;
4096 }
4097
4098 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4099 {
4100         struct kvm_segment cs;
4101         unsigned int cs_rpl;
4102
4103         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4104         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4105
4106         if (cs.unusable)
4107                 return false;
4108         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4109                 return false;
4110         if (!cs.s)
4111                 return false;
4112         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4113                 if (cs.dpl > cs_rpl)
4114                         return false;
4115         } else {
4116                 if (cs.dpl != cs_rpl)
4117                         return false;
4118         }
4119         if (!cs.present)
4120                 return false;
4121
4122         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4123         return true;
4124 }
4125
4126 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4127 {
4128         struct kvm_segment ss;
4129         unsigned int ss_rpl;
4130
4131         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4132         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4133
4134         if (ss.unusable)
4135                 return true;
4136         if (ss.type != 3 && ss.type != 7)
4137                 return false;
4138         if (!ss.s)
4139                 return false;
4140         if (ss.dpl != ss_rpl) /* DPL != RPL */
4141                 return false;
4142         if (!ss.present)
4143                 return false;
4144
4145         return true;
4146 }
4147
4148 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4149 {
4150         struct kvm_segment var;
4151         unsigned int rpl;
4152
4153         vmx_get_segment(vcpu, &var, seg);
4154         rpl = var.selector & SEGMENT_RPL_MASK;
4155
4156         if (var.unusable)
4157                 return true;
4158         if (!var.s)
4159                 return false;
4160         if (!var.present)
4161                 return false;
4162         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4163                 if (var.dpl < rpl) /* DPL < RPL */
4164                         return false;
4165         }
4166
4167         /* TODO: Add other members to kvm_segment_field to allow checking for other access
4168          * rights flags
4169          */
4170         return true;
4171 }
4172
4173 static bool tr_valid(struct kvm_vcpu *vcpu)
4174 {
4175         struct kvm_segment tr;
4176
4177         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4178
4179         if (tr.unusable)
4180                 return false;
4181         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
4182                 return false;
4183         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4184                 return false;
4185         if (!tr.present)
4186                 return false;
4187
4188         return true;
4189 }
4190
4191 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4192 {
4193         struct kvm_segment ldtr;
4194
4195         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4196
4197         if (ldtr.unusable)
4198                 return true;
4199         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
4200                 return false;
4201         if (ldtr.type != 2)
4202                 return false;
4203         if (!ldtr.present)
4204                 return false;
4205
4206         return true;
4207 }
4208
4209 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4210 {
4211         struct kvm_segment cs, ss;
4212
4213         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4214         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4215
4216         return ((cs.selector & SEGMENT_RPL_MASK) ==
4217                  (ss.selector & SEGMENT_RPL_MASK));
4218 }
4219
4220 /*
4221  * Check if guest state is valid. Returns true if valid, false if
4222  * not.
4223  * We assume that registers are always usable
4224  */
4225 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4226 {
4227         if (enable_unrestricted_guest)
4228                 return true;
4229
4230         /* real mode guest state checks */
4231         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4232                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4233                         return false;
4234                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4235                         return false;
4236                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4237                         return false;
4238                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4239                         return false;
4240                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4241                         return false;
4242                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4243                         return false;
4244         } else {
4245         /* protected mode guest state checks */
4246                 if (!cs_ss_rpl_check(vcpu))
4247                         return false;
4248                 if (!code_segment_valid(vcpu))
4249                         return false;
4250                 if (!stack_segment_valid(vcpu))
4251                         return false;
4252                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4253                         return false;
4254                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4255                         return false;
4256                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4257                         return false;
4258                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4259                         return false;
4260                 if (!tr_valid(vcpu))
4261                         return false;
4262                 if (!ldtr_valid(vcpu))
4263                         return false;
4264         }
4265         /* TODO:
4266          * - Add checks on RIP
4267          * - Add checks on RFLAGS
4268          */
4269
4270         return true;
4271 }
4272
4273 static int init_rmode_tss(struct kvm *kvm)
4274 {
4275         gfn_t fn;
4276         u16 data = 0;
4277         int idx, r;
4278
4279         idx = srcu_read_lock(&kvm->srcu);
4280         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4281         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4282         if (r < 0)
4283                 goto out;
4284         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4285         r = kvm_write_guest_page(kvm, fn++, &data,
4286                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4287         if (r < 0)
4288                 goto out;
4289         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4290         if (r < 0)
4291                 goto out;
4292         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4293         if (r < 0)
4294                 goto out;
4295         data = ~0;
4296         r = kvm_write_guest_page(kvm, fn, &data,
4297                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4298                                  sizeof(u8));
4299 out:
4300         srcu_read_unlock(&kvm->srcu, idx);
4301         return r;
4302 }
4303
4304 static int init_rmode_identity_map(struct kvm *kvm)
4305 {
4306         int i, idx, r = 0;
4307         kvm_pfn_t identity_map_pfn;
4308         u32 tmp;
4309
4310         if (!enable_ept)
4311                 return 0;
4312
4313         /* Protect kvm->arch.ept_identity_pagetable_done. */
4314         mutex_lock(&kvm->slots_lock);
4315
4316         if (likely(kvm->arch.ept_identity_pagetable_done))
4317                 goto out2;
4318
4319         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4320
4321         r = alloc_identity_pagetable(kvm);
4322         if (r < 0)
4323                 goto out2;
4324
4325         idx = srcu_read_lock(&kvm->srcu);
4326         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4327         if (r < 0)
4328                 goto out;
4329         /* Set up identity-mapping pagetable for EPT in real mode */
4330         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4331                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4332                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4333                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4334                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4335                 if (r < 0)
4336                         goto out;
4337         }
4338         kvm->arch.ept_identity_pagetable_done = true;
4339
4340 out:
4341         srcu_read_unlock(&kvm->srcu, idx);
4342
4343 out2:
4344         mutex_unlock(&kvm->slots_lock);
4345         return r;
4346 }
4347
4348 static void seg_setup(int seg)
4349 {
4350         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4351         unsigned int ar;
4352
4353         vmcs_write16(sf->selector, 0);
4354         vmcs_writel(sf->base, 0);
4355         vmcs_write32(sf->limit, 0xffff);
4356         ar = 0x93;
4357         if (seg == VCPU_SREG_CS)
4358                 ar |= 0x08; /* code segment */
4359
4360         vmcs_write32(sf->ar_bytes, ar);
4361 }
4362
4363 static int alloc_apic_access_page(struct kvm *kvm)
4364 {
4365         struct page *page;
4366         int r = 0;
4367
4368         mutex_lock(&kvm->slots_lock);
4369         if (kvm->arch.apic_access_page_done)
4370                 goto out;
4371         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4372                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4373         if (r)
4374                 goto out;
4375
4376         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4377         if (is_error_page(page)) {
4378                 r = -EFAULT;
4379                 goto out;
4380         }
4381
4382         /*
4383          * Do not pin the page in memory, so that memory hot-unplug
4384          * is able to migrate it.
4385          */
4386         put_page(page);
4387         kvm->arch.apic_access_page_done = true;
4388 out:
4389         mutex_unlock(&kvm->slots_lock);
4390         return r;
4391 }
4392
4393 static int alloc_identity_pagetable(struct kvm *kvm)
4394 {
4395         /* Called with kvm->slots_lock held. */
4396
4397         int r = 0;
4398
4399         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4400
4401         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4402                                     kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4403
4404         return r;
4405 }
4406
4407 static int allocate_vpid(void)
4408 {
4409         int vpid;
4410
4411         if (!enable_vpid)
4412                 return 0;
4413         spin_lock(&vmx_vpid_lock);
4414         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4415         if (vpid < VMX_NR_VPIDS)
4416                 __set_bit(vpid, vmx_vpid_bitmap);
4417         else
4418                 vpid = 0;
4419         spin_unlock(&vmx_vpid_lock);
4420         return vpid;
4421 }
4422
4423 static void free_vpid(int vpid)
4424 {
4425         if (!enable_vpid || vpid == 0)
4426                 return;
4427         spin_lock(&vmx_vpid_lock);
4428         __clear_bit(vpid, vmx_vpid_bitmap);
4429         spin_unlock(&vmx_vpid_lock);
4430 }
4431
4432 #define MSR_TYPE_R      1
4433 #define MSR_TYPE_W      2
4434 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4435                                                 u32 msr, int type)
4436 {
4437         int f = sizeof(unsigned long);
4438
4439         if (!cpu_has_vmx_msr_bitmap())
4440                 return;
4441
4442         /*
4443          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4444          * have the write-low and read-high bitmap offsets the wrong way round.
4445          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4446          */
4447         if (msr <= 0x1fff) {
4448                 if (type & MSR_TYPE_R)
4449                         /* read-low */
4450                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4451
4452                 if (type & MSR_TYPE_W)
4453                         /* write-low */
4454                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4455
4456         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4457                 msr &= 0x1fff;
4458                 if (type & MSR_TYPE_R)
4459                         /* read-high */
4460                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4461
4462                 if (type & MSR_TYPE_W)
4463                         /* write-high */
4464                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4465
4466         }
4467 }
4468
4469 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4470                                                 u32 msr, int type)
4471 {
4472         int f = sizeof(unsigned long);
4473
4474         if (!cpu_has_vmx_msr_bitmap())
4475                 return;
4476
4477         /*
4478          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4479          * have the write-low and read-high bitmap offsets the wrong way round.
4480          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4481          */
4482         if (msr <= 0x1fff) {
4483                 if (type & MSR_TYPE_R)
4484                         /* read-low */
4485                         __set_bit(msr, msr_bitmap + 0x000 / f);
4486
4487                 if (type & MSR_TYPE_W)
4488                         /* write-low */
4489                         __set_bit(msr, msr_bitmap + 0x800 / f);
4490
4491         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4492                 msr &= 0x1fff;
4493                 if (type & MSR_TYPE_R)
4494                         /* read-high */
4495                         __set_bit(msr, msr_bitmap + 0x400 / f);
4496
4497                 if (type & MSR_TYPE_W)
4498                         /* write-high */
4499                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4500
4501         }
4502 }
4503
4504 /*
4505  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4506  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4507  */
4508 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4509                                                unsigned long *msr_bitmap_nested,
4510                                                u32 msr, int type)
4511 {
4512         int f = sizeof(unsigned long);
4513
4514         if (!cpu_has_vmx_msr_bitmap()) {
4515                 WARN_ON(1);
4516                 return;
4517         }
4518
4519         /*
4520          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4521          * have the write-low and read-high bitmap offsets the wrong way round.
4522          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4523          */
4524         if (msr <= 0x1fff) {
4525                 if (type & MSR_TYPE_R &&
4526                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4527                         /* read-low */
4528                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4529
4530                 if (type & MSR_TYPE_W &&
4531                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4532                         /* write-low */
4533                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4534
4535         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4536                 msr &= 0x1fff;
4537                 if (type & MSR_TYPE_R &&
4538                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4539                         /* read-high */
4540                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4541
4542                 if (type & MSR_TYPE_W &&
4543                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4544                         /* write-high */
4545                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4546
4547         }
4548 }
4549
4550 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4551 {
4552         if (!longmode_only)
4553                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4554                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4555         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4556                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4557 }
4558
4559 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4560 {
4561         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4562                         msr, MSR_TYPE_R);
4563         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4564                         msr, MSR_TYPE_R);
4565 }
4566
4567 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4568 {
4569         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4570                         msr, MSR_TYPE_R);
4571         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4572                         msr, MSR_TYPE_R);
4573 }
4574
4575 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4576 {
4577         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4578                         msr, MSR_TYPE_W);
4579         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4580                         msr, MSR_TYPE_W);
4581 }
4582
4583 static bool vmx_get_enable_apicv(void)
4584 {
4585         return enable_apicv;
4586 }
4587
4588 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4589 {
4590         struct vcpu_vmx *vmx = to_vmx(vcpu);
4591         int max_irr;
4592         void *vapic_page;
4593         u16 status;
4594
4595         if (vmx->nested.pi_desc &&
4596             vmx->nested.pi_pending) {
4597                 vmx->nested.pi_pending = false;
4598                 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4599                         return 0;
4600
4601                 max_irr = find_last_bit(
4602                         (unsigned long *)vmx->nested.pi_desc->pir, 256);
4603
4604                 if (max_irr == 256)
4605                         return 0;
4606
4607                 vapic_page = kmap(vmx->nested.virtual_apic_page);
4608                 if (!vapic_page) {
4609                         WARN_ON(1);
4610                         return -ENOMEM;
4611                 }
4612                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4613                 kunmap(vmx->nested.virtual_apic_page);
4614
4615                 status = vmcs_read16(GUEST_INTR_STATUS);
4616                 if ((u8)max_irr > ((u8)status & 0xff)) {
4617                         status &= ~0xff;
4618                         status |= (u8)max_irr;
4619                         vmcs_write16(GUEST_INTR_STATUS, status);
4620                 }
4621         }
4622         return 0;
4623 }
4624
4625 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4626 {
4627 #ifdef CONFIG_SMP
4628         if (vcpu->mode == IN_GUEST_MODE) {
4629                 struct vcpu_vmx *vmx = to_vmx(vcpu);
4630
4631                 /*
4632                  * Currently, we don't support urgent interrupt,
4633                  * all interrupts are recognized as non-urgent
4634                  * interrupt, so we cannot post interrupts when
4635                  * 'SN' is set.
4636                  *
4637                  * If the vcpu is in guest mode, it means it is
4638                  * running instead of being scheduled out and
4639                  * waiting in the run queue, and that's the only
4640                  * case when 'SN' is set currently, warning if
4641                  * 'SN' is set.
4642                  */
4643                 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4644
4645                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4646                                 POSTED_INTR_VECTOR);
4647                 return true;
4648         }
4649 #endif
4650         return false;
4651 }
4652
4653 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4654                                                 int vector)
4655 {
4656         struct vcpu_vmx *vmx = to_vmx(vcpu);
4657
4658         if (is_guest_mode(vcpu) &&
4659             vector == vmx->nested.posted_intr_nv) {
4660                 /* the PIR and ON have been set by L1. */
4661                 kvm_vcpu_trigger_posted_interrupt(vcpu);
4662                 /*
4663                  * If a posted intr is not recognized by hardware,
4664                  * we will accomplish it in the next vmentry.
4665                  */
4666                 vmx->nested.pi_pending = true;
4667                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4668                 return 0;
4669         }
4670         return -1;
4671 }
4672 /*
4673  * Send interrupt to vcpu via posted interrupt way.
4674  * 1. If target vcpu is running(non-root mode), send posted interrupt
4675  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4676  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4677  * interrupt from PIR in next vmentry.
4678  */
4679 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4680 {
4681         struct vcpu_vmx *vmx = to_vmx(vcpu);
4682         int r;
4683
4684         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4685         if (!r)
4686                 return;
4687
4688         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4689                 return;
4690
4691         r = pi_test_and_set_on(&vmx->pi_desc);
4692         kvm_make_request(KVM_REQ_EVENT, vcpu);
4693         if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
4694                 kvm_vcpu_kick(vcpu);
4695 }
4696
4697 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4698 {
4699         struct vcpu_vmx *vmx = to_vmx(vcpu);
4700
4701         if (!pi_test_and_clear_on(&vmx->pi_desc))
4702                 return;
4703
4704         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4705 }
4706
4707 /*
4708  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4709  * will not change in the lifetime of the guest.
4710  * Note that host-state that does change is set elsewhere. E.g., host-state
4711  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4712  */
4713 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4714 {
4715         u32 low32, high32;
4716         unsigned long tmpl;
4717         struct desc_ptr dt;
4718         unsigned long cr4;
4719
4720         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4721         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4722
4723         /* Save the most likely value for this task's CR4 in the VMCS. */
4724         cr4 = cr4_read_shadow();
4725         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
4726         vmx->host_state.vmcs_host_cr4 = cr4;
4727
4728         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4729 #ifdef CONFIG_X86_64
4730         /*
4731          * Load null selectors, so we can avoid reloading them in
4732          * __vmx_load_host_state(), in case userspace uses the null selectors
4733          * too (the expected case).
4734          */
4735         vmcs_write16(HOST_DS_SELECTOR, 0);
4736         vmcs_write16(HOST_ES_SELECTOR, 0);
4737 #else
4738         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4739         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4740 #endif
4741         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4742         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4743
4744         native_store_idt(&dt);
4745         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4746         vmx->host_idt_base = dt.address;
4747
4748         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4749
4750         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4751         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4752         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4753         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4754
4755         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4756                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4757                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4758         }
4759 }
4760
4761 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4762 {
4763         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4764         if (enable_ept)
4765                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4766         if (is_guest_mode(&vmx->vcpu))
4767                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4768                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4769         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4770 }
4771
4772 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4773 {
4774         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4775
4776         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4777                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4778         return pin_based_exec_ctrl;
4779 }
4780
4781 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4782 {
4783         struct vcpu_vmx *vmx = to_vmx(vcpu);
4784
4785         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4786 }
4787
4788 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4789 {
4790         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4791
4792         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4793                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4794
4795         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4796                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4797 #ifdef CONFIG_X86_64
4798                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4799                                 CPU_BASED_CR8_LOAD_EXITING;
4800 #endif
4801         }
4802         if (!enable_ept)
4803                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4804                                 CPU_BASED_CR3_LOAD_EXITING  |
4805                                 CPU_BASED_INVLPG_EXITING;
4806         return exec_control;
4807 }
4808
4809 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4810 {
4811         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4812         if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
4813                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4814         if (vmx->vpid == 0)
4815                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4816         if (!enable_ept) {
4817                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4818                 enable_unrestricted_guest = 0;
4819                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4820                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4821         }
4822         if (!enable_unrestricted_guest)
4823                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4824         if (!ple_gap)
4825                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4826         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4827                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4828                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4829         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4830         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4831            (handle_vmptrld).
4832            We can NOT enable shadow_vmcs here because we don't have yet
4833            a current VMCS12
4834         */
4835         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4836
4837         if (!enable_pml)
4838                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4839
4840         /* Currently, we allow L1 guest to directly run pcommit instruction. */
4841         exec_control &= ~SECONDARY_EXEC_PCOMMIT;
4842
4843         return exec_control;
4844 }
4845
4846 static void ept_set_mmio_spte_mask(void)
4847 {
4848         /*
4849          * EPT Misconfigurations can be generated if the value of bits 2:0
4850          * of an EPT paging-structure entry is 110b (write/execute).
4851          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4852          * spte.
4853          */
4854         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4855 }
4856
4857 #define VMX_XSS_EXIT_BITMAP 0
4858 /*
4859  * Sets up the vmcs for emulated real mode.
4860  */
4861 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4862 {
4863 #ifdef CONFIG_X86_64
4864         unsigned long a;
4865 #endif
4866         int i;
4867
4868         /* I/O */
4869         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4870         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4871
4872         if (enable_shadow_vmcs) {
4873                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4874                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4875         }
4876         if (cpu_has_vmx_msr_bitmap())
4877                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4878
4879         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4880
4881         /* Control */
4882         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4883
4884         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4885
4886         if (cpu_has_secondary_exec_ctrls())
4887                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4888                                 vmx_secondary_exec_control(vmx));
4889
4890         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4891                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4892                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4893                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4894                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4895
4896                 vmcs_write16(GUEST_INTR_STATUS, 0);
4897
4898                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4899                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4900         }
4901
4902         if (ple_gap) {
4903                 vmcs_write32(PLE_GAP, ple_gap);
4904                 vmx->ple_window = ple_window;
4905                 vmx->ple_window_dirty = true;
4906         }
4907
4908         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4909         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4910         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4911
4912         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4913         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4914         vmx_set_constant_host_state(vmx);
4915 #ifdef CONFIG_X86_64
4916         rdmsrl(MSR_FS_BASE, a);
4917         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4918         rdmsrl(MSR_GS_BASE, a);
4919         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4920 #else
4921         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4922         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4923 #endif
4924
4925         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4926         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4927         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4928         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4929         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4930
4931         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4932                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4933
4934         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4935                 u32 index = vmx_msr_index[i];
4936                 u32 data_low, data_high;
4937                 int j = vmx->nmsrs;
4938
4939                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4940                         continue;
4941                 if (wrmsr_safe(index, data_low, data_high) < 0)
4942                         continue;
4943                 vmx->guest_msrs[j].index = i;
4944                 vmx->guest_msrs[j].data = 0;
4945                 vmx->guest_msrs[j].mask = -1ull;
4946                 ++vmx->nmsrs;
4947         }
4948
4949
4950         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
4951
4952         /* 22.2.1, 20.8.1 */
4953         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
4954
4955         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4956         set_cr4_guest_host_mask(vmx);
4957
4958         if (vmx_xsaves_supported())
4959                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4960
4961         return 0;
4962 }
4963
4964 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4965 {
4966         struct vcpu_vmx *vmx = to_vmx(vcpu);
4967         struct msr_data apic_base_msr;
4968         u64 cr0;
4969
4970         vmx->rmode.vm86_active = 0;
4971
4972         vmx->soft_vnmi_blocked = 0;
4973
4974         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4975         kvm_set_cr8(vcpu, 0);
4976
4977         if (!init_event) {
4978                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4979                                      MSR_IA32_APICBASE_ENABLE;
4980                 if (kvm_vcpu_is_reset_bsp(vcpu))
4981                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4982                 apic_base_msr.host_initiated = true;
4983                 kvm_set_apic_base(vcpu, &apic_base_msr);
4984         }
4985
4986         vmx_segment_cache_clear(vmx);
4987
4988         seg_setup(VCPU_SREG_CS);
4989         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4990         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
4991
4992         seg_setup(VCPU_SREG_DS);
4993         seg_setup(VCPU_SREG_ES);
4994         seg_setup(VCPU_SREG_FS);
4995         seg_setup(VCPU_SREG_GS);
4996         seg_setup(VCPU_SREG_SS);
4997
4998         vmcs_write16(GUEST_TR_SELECTOR, 0);
4999         vmcs_writel(GUEST_TR_BASE, 0);
5000         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5001         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5002
5003         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5004         vmcs_writel(GUEST_LDTR_BASE, 0);
5005         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5006         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5007
5008         if (!init_event) {
5009                 vmcs_write32(GUEST_SYSENTER_CS, 0);
5010                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5011                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5012                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5013         }
5014
5015         vmcs_writel(GUEST_RFLAGS, 0x02);
5016         kvm_rip_write(vcpu, 0xfff0);
5017
5018         vmcs_writel(GUEST_GDTR_BASE, 0);
5019         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5020
5021         vmcs_writel(GUEST_IDTR_BASE, 0);
5022         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5023
5024         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
5025         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
5026         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
5027
5028         setup_msrs(vmx);
5029
5030         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
5031
5032         if (cpu_has_vmx_tpr_shadow() && !init_event) {
5033                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
5034                 if (cpu_need_tpr_shadow(vcpu))
5035                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
5036                                      __pa(vcpu->arch.apic->regs));
5037                 vmcs_write32(TPR_THRESHOLD, 0);
5038         }
5039
5040         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
5041
5042         if (kvm_vcpu_apicv_active(vcpu))
5043                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5044
5045         if (vmx->vpid != 0)
5046                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5047
5048         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5049         vmx_set_cr0(vcpu, cr0); /* enter rmode */
5050         vmx->vcpu.arch.cr0 = cr0;
5051         vmx_set_cr4(vcpu, 0);
5052         vmx_set_efer(vcpu, 0);
5053         vmx_fpu_activate(vcpu);
5054         update_exception_bitmap(vcpu);
5055
5056         vpid_sync_context(vmx->vpid);
5057 }
5058
5059 /*
5060  * In nested virtualization, check if L1 asked to exit on external interrupts.
5061  * For most existing hypervisors, this will always return true.
5062  */
5063 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5064 {
5065         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5066                 PIN_BASED_EXT_INTR_MASK;
5067 }
5068
5069 /*
5070  * In nested virtualization, check if L1 has set
5071  * VM_EXIT_ACK_INTR_ON_EXIT
5072  */
5073 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5074 {
5075         return get_vmcs12(vcpu)->vm_exit_controls &
5076                 VM_EXIT_ACK_INTR_ON_EXIT;
5077 }
5078
5079 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5080 {
5081         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5082                 PIN_BASED_NMI_EXITING;
5083 }
5084
5085 static void enable_irq_window(struct kvm_vcpu *vcpu)
5086 {
5087         u32 cpu_based_vm_exec_control;
5088
5089         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5090         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
5091         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5092 }
5093
5094 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5095 {
5096         u32 cpu_based_vm_exec_control;
5097
5098         if (!cpu_has_virtual_nmis() ||
5099             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5100                 enable_irq_window(vcpu);
5101                 return;
5102         }
5103
5104         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5105         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
5106         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5107 }
5108
5109 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5110 {
5111         struct vcpu_vmx *vmx = to_vmx(vcpu);
5112         uint32_t intr;
5113         int irq = vcpu->arch.interrupt.nr;
5114
5115         trace_kvm_inj_virq(irq);
5116
5117         ++vcpu->stat.irq_injections;
5118         if (vmx->rmode.vm86_active) {
5119                 int inc_eip = 0;
5120                 if (vcpu->arch.interrupt.soft)
5121                         inc_eip = vcpu->arch.event_exit_inst_len;
5122                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5123                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5124                 return;
5125         }
5126         intr = irq | INTR_INFO_VALID_MASK;
5127         if (vcpu->arch.interrupt.soft) {
5128                 intr |= INTR_TYPE_SOFT_INTR;
5129                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5130                              vmx->vcpu.arch.event_exit_inst_len);
5131         } else
5132                 intr |= INTR_TYPE_EXT_INTR;
5133         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5134 }
5135
5136 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5137 {
5138         struct vcpu_vmx *vmx = to_vmx(vcpu);
5139
5140         if (is_guest_mode(vcpu))
5141                 return;
5142
5143         if (!cpu_has_virtual_nmis()) {
5144                 /*
5145                  * Tracking the NMI-blocked state in software is built upon
5146                  * finding the next open IRQ window. This, in turn, depends on
5147                  * well-behaving guests: They have to keep IRQs disabled at
5148                  * least as long as the NMI handler runs. Otherwise we may
5149                  * cause NMI nesting, maybe breaking the guest. But as this is
5150                  * highly unlikely, we can live with the residual risk.
5151                  */
5152                 vmx->soft_vnmi_blocked = 1;
5153                 vmx->vnmi_blocked_time = 0;
5154         }
5155
5156         ++vcpu->stat.nmi_injections;
5157         vmx->nmi_known_unmasked = false;
5158         if (vmx->rmode.vm86_active) {
5159                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5160                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5161                 return;
5162         }
5163         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5164                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5165 }
5166
5167 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5168 {
5169         if (!cpu_has_virtual_nmis())
5170                 return to_vmx(vcpu)->soft_vnmi_blocked;
5171         if (to_vmx(vcpu)->nmi_known_unmasked)
5172                 return false;
5173         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5174 }
5175
5176 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5177 {
5178         struct vcpu_vmx *vmx = to_vmx(vcpu);
5179
5180         if (!cpu_has_virtual_nmis()) {
5181                 if (vmx->soft_vnmi_blocked != masked) {
5182                         vmx->soft_vnmi_blocked = masked;
5183                         vmx->vnmi_blocked_time = 0;
5184                 }
5185         } else {
5186                 vmx->nmi_known_unmasked = !masked;
5187                 if (masked)
5188                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5189                                       GUEST_INTR_STATE_NMI);
5190                 else
5191                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5192                                         GUEST_INTR_STATE_NMI);
5193         }
5194 }
5195
5196 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5197 {
5198         if (to_vmx(vcpu)->nested.nested_run_pending)
5199                 return 0;
5200
5201         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
5202                 return 0;
5203
5204         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5205                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5206                    | GUEST_INTR_STATE_NMI));
5207 }
5208
5209 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5210 {
5211         return (!to_vmx(vcpu)->nested.nested_run_pending &&
5212                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5213                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5214                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5215 }
5216
5217 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5218 {
5219         int ret;
5220
5221         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5222                                     PAGE_SIZE * 3);
5223         if (ret)
5224                 return ret;
5225         kvm->arch.tss_addr = addr;
5226         return init_rmode_tss(kvm);
5227 }
5228
5229 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5230 {
5231         switch (vec) {
5232         case BP_VECTOR:
5233                 /*
5234                  * Update instruction length as we may reinject the exception
5235                  * from user space while in guest debugging mode.
5236                  */
5237                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5238                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5239                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5240                         return false;
5241                 /* fall through */
5242         case DB_VECTOR:
5243                 if (vcpu->guest_debug &
5244                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5245                         return false;
5246                 /* fall through */
5247         case DE_VECTOR:
5248         case OF_VECTOR:
5249         case BR_VECTOR:
5250         case UD_VECTOR:
5251         case DF_VECTOR:
5252         case SS_VECTOR:
5253         case GP_VECTOR:
5254         case MF_VECTOR:
5255                 return true;
5256         break;
5257         }
5258         return false;
5259 }
5260
5261 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5262                                   int vec, u32 err_code)
5263 {
5264         /*
5265          * Instruction with address size override prefix opcode 0x67
5266          * Cause the #SS fault with 0 error code in VM86 mode.
5267          */
5268         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5269                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5270                         if (vcpu->arch.halt_request) {
5271                                 vcpu->arch.halt_request = 0;
5272                                 return kvm_vcpu_halt(vcpu);
5273                         }
5274                         return 1;
5275                 }
5276                 return 0;
5277         }
5278
5279         /*
5280          * Forward all other exceptions that are valid in real mode.
5281          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5282          *        the required debugging infrastructure rework.
5283          */
5284         kvm_queue_exception(vcpu, vec);
5285         return 1;
5286 }
5287
5288 /*
5289  * Trigger machine check on the host. We assume all the MSRs are already set up
5290  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5291  * We pass a fake environment to the machine check handler because we want
5292  * the guest to be always treated like user space, no matter what context
5293  * it used internally.
5294  */
5295 static void kvm_machine_check(void)
5296 {
5297 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5298         struct pt_regs regs = {
5299                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5300                 .flags = X86_EFLAGS_IF,
5301         };
5302
5303         do_machine_check(&regs, 0);
5304 #endif
5305 }
5306
5307 static int handle_machine_check(struct kvm_vcpu *vcpu)
5308 {
5309         /* already handled by vcpu_run */
5310         return 1;
5311 }
5312
5313 static int handle_exception(struct kvm_vcpu *vcpu)
5314 {
5315         struct vcpu_vmx *vmx = to_vmx(vcpu);
5316         struct kvm_run *kvm_run = vcpu->run;
5317         u32 intr_info, ex_no, error_code;
5318         unsigned long cr2, rip, dr6;
5319         u32 vect_info;
5320         enum emulation_result er;
5321
5322         vect_info = vmx->idt_vectoring_info;
5323         intr_info = vmx->exit_intr_info;
5324
5325         if (is_machine_check(intr_info))
5326                 return handle_machine_check(vcpu);
5327
5328         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
5329                 return 1;  /* already handled by vmx_vcpu_run() */
5330
5331         if (is_no_device(intr_info)) {
5332                 vmx_fpu_activate(vcpu);
5333                 return 1;
5334         }
5335
5336         if (is_invalid_opcode(intr_info)) {
5337                 if (is_guest_mode(vcpu)) {
5338                         kvm_queue_exception(vcpu, UD_VECTOR);
5339                         return 1;
5340                 }
5341                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5342                 if (er != EMULATE_DONE)
5343                         kvm_queue_exception(vcpu, UD_VECTOR);
5344                 return 1;
5345         }
5346
5347         error_code = 0;
5348         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5349                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5350
5351         /*
5352          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5353          * MMIO, it is better to report an internal error.
5354          * See the comments in vmx_handle_exit.
5355          */
5356         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5357             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5358                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5359                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5360                 vcpu->run->internal.ndata = 3;
5361                 vcpu->run->internal.data[0] = vect_info;
5362                 vcpu->run->internal.data[1] = intr_info;
5363                 vcpu->run->internal.data[2] = error_code;
5364                 return 0;
5365         }
5366
5367         if (is_page_fault(intr_info)) {
5368                 /* EPT won't cause page fault directly */
5369                 BUG_ON(enable_ept);
5370                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5371                 trace_kvm_page_fault(cr2, error_code);
5372
5373                 if (kvm_event_needs_reinjection(vcpu))
5374                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
5375                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5376         }
5377
5378         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5379
5380         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5381                 return handle_rmode_exception(vcpu, ex_no, error_code);
5382
5383         switch (ex_no) {
5384         case AC_VECTOR:
5385                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5386                 return 1;
5387         case DB_VECTOR:
5388                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5389                 if (!(vcpu->guest_debug &
5390                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5391                         vcpu->arch.dr6 &= ~15;
5392                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5393                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5394                                 skip_emulated_instruction(vcpu);
5395
5396                         kvm_queue_exception(vcpu, DB_VECTOR);
5397                         return 1;
5398                 }
5399                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5400                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5401                 /* fall through */
5402         case BP_VECTOR:
5403                 /*
5404                  * Update instruction length as we may reinject #BP from
5405                  * user space while in guest debugging mode. Reading it for
5406                  * #DB as well causes no harm, it is not used in that case.
5407                  */
5408                 vmx->vcpu.arch.event_exit_inst_len =
5409                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5410                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5411                 rip = kvm_rip_read(vcpu);
5412                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5413                 kvm_run->debug.arch.exception = ex_no;
5414                 break;
5415         default:
5416                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5417                 kvm_run->ex.exception = ex_no;
5418                 kvm_run->ex.error_code = error_code;
5419                 break;
5420         }
5421         return 0;
5422 }
5423
5424 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5425 {
5426         ++vcpu->stat.irq_exits;
5427         return 1;
5428 }
5429
5430 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5431 {
5432         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5433         return 0;
5434 }
5435
5436 static int handle_io(struct kvm_vcpu *vcpu)
5437 {
5438         unsigned long exit_qualification;
5439         int size, in, string;
5440         unsigned port;
5441
5442         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5443         string = (exit_qualification & 16) != 0;
5444         in = (exit_qualification & 8) != 0;
5445
5446         ++vcpu->stat.io_exits;
5447
5448         if (string || in)
5449                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5450
5451         port = exit_qualification >> 16;
5452         size = (exit_qualification & 7) + 1;
5453         skip_emulated_instruction(vcpu);
5454
5455         return kvm_fast_pio_out(vcpu, size, port);
5456 }
5457
5458 static void
5459 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5460 {
5461         /*
5462          * Patch in the VMCALL instruction:
5463          */
5464         hypercall[0] = 0x0f;
5465         hypercall[1] = 0x01;
5466         hypercall[2] = 0xc1;
5467 }
5468
5469 static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5470 {
5471         unsigned long always_on = VMXON_CR0_ALWAYSON;
5472         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5473
5474         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
5475                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5476             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5477                 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5478         return (val & always_on) == always_on;
5479 }
5480
5481 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5482 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5483 {
5484         if (is_guest_mode(vcpu)) {
5485                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5486                 unsigned long orig_val = val;
5487
5488                 /*
5489                  * We get here when L2 changed cr0 in a way that did not change
5490                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5491                  * but did change L0 shadowed bits. So we first calculate the
5492                  * effective cr0 value that L1 would like to write into the
5493                  * hardware. It consists of the L2-owned bits from the new
5494                  * value combined with the L1-owned bits from L1's guest_cr0.
5495                  */
5496                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5497                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5498
5499                 if (!nested_cr0_valid(vcpu, val))
5500                         return 1;
5501
5502                 if (kvm_set_cr0(vcpu, val))
5503                         return 1;
5504                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5505                 return 0;
5506         } else {
5507                 if (to_vmx(vcpu)->nested.vmxon &&
5508                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5509                         return 1;
5510                 return kvm_set_cr0(vcpu, val);
5511         }
5512 }
5513
5514 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5515 {
5516         if (is_guest_mode(vcpu)) {
5517                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5518                 unsigned long orig_val = val;
5519
5520                 /* analogously to handle_set_cr0 */
5521                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5522                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5523                 if (kvm_set_cr4(vcpu, val))
5524                         return 1;
5525                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5526                 return 0;
5527         } else
5528                 return kvm_set_cr4(vcpu, val);
5529 }
5530
5531 /* called to set cr0 as appropriate for clts instruction exit. */
5532 static void handle_clts(struct kvm_vcpu *vcpu)
5533 {
5534         if (is_guest_mode(vcpu)) {
5535                 /*
5536                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5537                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5538                  * just pretend it's off (also in arch.cr0 for fpu_activate).
5539                  */
5540                 vmcs_writel(CR0_READ_SHADOW,
5541                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5542                 vcpu->arch.cr0 &= ~X86_CR0_TS;
5543         } else
5544                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5545 }
5546
5547 static int handle_cr(struct kvm_vcpu *vcpu)
5548 {
5549         unsigned long exit_qualification, val;
5550         int cr;
5551         int reg;
5552         int err;
5553
5554         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5555         cr = exit_qualification & 15;
5556         reg = (exit_qualification >> 8) & 15;
5557         switch ((exit_qualification >> 4) & 3) {
5558         case 0: /* mov to cr */
5559                 val = kvm_register_readl(vcpu, reg);
5560                 trace_kvm_cr_write(cr, val);
5561                 switch (cr) {
5562                 case 0:
5563                         err = handle_set_cr0(vcpu, val);
5564                         kvm_complete_insn_gp(vcpu, err);
5565                         return 1;
5566                 case 3:
5567                         err = kvm_set_cr3(vcpu, val);
5568                         kvm_complete_insn_gp(vcpu, err);
5569                         return 1;
5570                 case 4:
5571                         err = handle_set_cr4(vcpu, val);
5572                         kvm_complete_insn_gp(vcpu, err);
5573                         return 1;
5574                 case 8: {
5575                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5576                                 u8 cr8 = (u8)val;
5577                                 err = kvm_set_cr8(vcpu, cr8);
5578                                 kvm_complete_insn_gp(vcpu, err);
5579                                 if (lapic_in_kernel(vcpu))
5580                                         return 1;
5581                                 if (cr8_prev <= cr8)
5582                                         return 1;
5583                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5584                                 return 0;
5585                         }
5586                 }
5587                 break;
5588         case 2: /* clts */
5589                 handle_clts(vcpu);
5590                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5591                 skip_emulated_instruction(vcpu);
5592                 vmx_fpu_activate(vcpu);
5593                 return 1;
5594         case 1: /*mov from cr*/
5595                 switch (cr) {
5596                 case 3:
5597                         val = kvm_read_cr3(vcpu);
5598                         kvm_register_write(vcpu, reg, val);
5599                         trace_kvm_cr_read(cr, val);
5600                         skip_emulated_instruction(vcpu);
5601                         return 1;
5602                 case 8:
5603                         val = kvm_get_cr8(vcpu);
5604                         kvm_register_write(vcpu, reg, val);
5605                         trace_kvm_cr_read(cr, val);
5606                         skip_emulated_instruction(vcpu);
5607                         return 1;
5608                 }
5609                 break;
5610         case 3: /* lmsw */
5611                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5612                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5613                 kvm_lmsw(vcpu, val);
5614
5615                 skip_emulated_instruction(vcpu);
5616                 return 1;
5617         default:
5618                 break;
5619         }
5620         vcpu->run->exit_reason = 0;
5621         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5622                (int)(exit_qualification >> 4) & 3, cr);
5623         return 0;
5624 }
5625
5626 static int handle_dr(struct kvm_vcpu *vcpu)
5627 {
5628         unsigned long exit_qualification;
5629         int dr, dr7, reg;
5630
5631         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5632         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5633
5634         /* First, if DR does not exist, trigger UD */
5635         if (!kvm_require_dr(vcpu, dr))
5636                 return 1;
5637
5638         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5639         if (!kvm_require_cpl(vcpu, 0))
5640                 return 1;
5641         dr7 = vmcs_readl(GUEST_DR7);
5642         if (dr7 & DR7_GD) {
5643                 /*
5644                  * As the vm-exit takes precedence over the debug trap, we
5645                  * need to emulate the latter, either for the host or the
5646                  * guest debugging itself.
5647                  */
5648                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5649                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5650                         vcpu->run->debug.arch.dr7 = dr7;
5651                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5652                         vcpu->run->debug.arch.exception = DB_VECTOR;
5653                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5654                         return 0;
5655                 } else {
5656                         vcpu->arch.dr6 &= ~15;
5657                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5658                         kvm_queue_exception(vcpu, DB_VECTOR);
5659                         return 1;
5660                 }
5661         }
5662
5663         if (vcpu->guest_debug == 0) {
5664                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
5665                                 CPU_BASED_MOV_DR_EXITING);
5666
5667                 /*
5668                  * No more DR vmexits; force a reload of the debug registers
5669                  * and reenter on this instruction.  The next vmexit will
5670                  * retrieve the full state of the debug registers.
5671                  */
5672                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5673                 return 1;
5674         }
5675
5676         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5677         if (exit_qualification & TYPE_MOV_FROM_DR) {
5678                 unsigned long val;
5679
5680                 if (kvm_get_dr(vcpu, dr, &val))
5681                         return 1;
5682                 kvm_register_write(vcpu, reg, val);
5683         } else
5684                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5685                         return 1;
5686
5687         skip_emulated_instruction(vcpu);
5688         return 1;
5689 }
5690
5691 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5692 {
5693         return vcpu->arch.dr6;
5694 }
5695
5696 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5697 {
5698 }
5699
5700 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5701 {
5702         get_debugreg(vcpu->arch.db[0], 0);
5703         get_debugreg(vcpu->arch.db[1], 1);
5704         get_debugreg(vcpu->arch.db[2], 2);
5705         get_debugreg(vcpu->arch.db[3], 3);
5706         get_debugreg(vcpu->arch.dr6, 6);
5707         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5708
5709         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5710         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
5711 }
5712
5713 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5714 {
5715         vmcs_writel(GUEST_DR7, val);
5716 }
5717
5718 static int handle_cpuid(struct kvm_vcpu *vcpu)
5719 {
5720         kvm_emulate_cpuid(vcpu);
5721         return 1;
5722 }
5723
5724 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5725 {
5726         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5727         struct msr_data msr_info;
5728
5729         msr_info.index = ecx;
5730         msr_info.host_initiated = false;
5731         if (vmx_get_msr(vcpu, &msr_info)) {
5732                 trace_kvm_msr_read_ex(ecx);
5733                 kvm_inject_gp(vcpu, 0);
5734                 return 1;
5735         }
5736
5737         trace_kvm_msr_read(ecx, msr_info.data);
5738
5739         /* FIXME: handling of bits 32:63 of rax, rdx */
5740         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
5741         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
5742         skip_emulated_instruction(vcpu);
5743         return 1;
5744 }
5745
5746 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5747 {
5748         struct msr_data msr;
5749         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5750         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5751                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5752
5753         msr.data = data;
5754         msr.index = ecx;
5755         msr.host_initiated = false;
5756         if (kvm_set_msr(vcpu, &msr) != 0) {
5757                 trace_kvm_msr_write_ex(ecx, data);
5758                 kvm_inject_gp(vcpu, 0);
5759                 return 1;
5760         }
5761
5762         trace_kvm_msr_write(ecx, data);
5763         skip_emulated_instruction(vcpu);
5764         return 1;
5765 }
5766
5767 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5768 {
5769         kvm_make_request(KVM_REQ_EVENT, vcpu);
5770         return 1;
5771 }
5772
5773 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5774 {
5775         u32 cpu_based_vm_exec_control;
5776
5777         /* clear pending irq */
5778         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5779         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5780         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5781
5782         kvm_make_request(KVM_REQ_EVENT, vcpu);
5783
5784         ++vcpu->stat.irq_window_exits;
5785         return 1;
5786 }
5787
5788 static int handle_halt(struct kvm_vcpu *vcpu)
5789 {
5790         return kvm_emulate_halt(vcpu);
5791 }
5792
5793 static int handle_vmcall(struct kvm_vcpu *vcpu)
5794 {
5795         return kvm_emulate_hypercall(vcpu);
5796 }
5797
5798 static int handle_invd(struct kvm_vcpu *vcpu)
5799 {
5800         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5801 }
5802
5803 static int handle_invlpg(struct kvm_vcpu *vcpu)
5804 {
5805         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5806
5807         kvm_mmu_invlpg(vcpu, exit_qualification);
5808         skip_emulated_instruction(vcpu);
5809         return 1;
5810 }
5811
5812 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5813 {
5814         int err;
5815
5816         err = kvm_rdpmc(vcpu);
5817         kvm_complete_insn_gp(vcpu, err);
5818
5819         return 1;
5820 }
5821
5822 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5823 {
5824         kvm_emulate_wbinvd(vcpu);
5825         return 1;
5826 }
5827
5828 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5829 {
5830         u64 new_bv = kvm_read_edx_eax(vcpu);
5831         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5832
5833         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5834                 skip_emulated_instruction(vcpu);
5835         return 1;
5836 }
5837
5838 static int handle_xsaves(struct kvm_vcpu *vcpu)
5839 {
5840         skip_emulated_instruction(vcpu);
5841         WARN(1, "this should never happen\n");
5842         return 1;
5843 }
5844
5845 static int handle_xrstors(struct kvm_vcpu *vcpu)
5846 {
5847         skip_emulated_instruction(vcpu);
5848         WARN(1, "this should never happen\n");
5849         return 1;
5850 }
5851
5852 static int handle_apic_access(struct kvm_vcpu *vcpu)
5853 {
5854         if (likely(fasteoi)) {
5855                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5856                 int access_type, offset;
5857
5858                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5859                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5860                 /*
5861                  * Sane guest uses MOV to write EOI, with written value
5862                  * not cared. So make a short-circuit here by avoiding
5863                  * heavy instruction emulation.
5864                  */
5865                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5866                     (offset == APIC_EOI)) {
5867                         kvm_lapic_set_eoi(vcpu);
5868                         skip_emulated_instruction(vcpu);
5869                         return 1;
5870                 }
5871         }
5872         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5873 }
5874
5875 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5876 {
5877         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5878         int vector = exit_qualification & 0xff;
5879
5880         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5881         kvm_apic_set_eoi_accelerated(vcpu, vector);
5882         return 1;
5883 }
5884
5885 static int handle_apic_write(struct kvm_vcpu *vcpu)
5886 {
5887         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5888         u32 offset = exit_qualification & 0xfff;
5889
5890         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5891         kvm_apic_write_nodecode(vcpu, offset);
5892         return 1;
5893 }
5894
5895 static int handle_task_switch(struct kvm_vcpu *vcpu)
5896 {
5897         struct vcpu_vmx *vmx = to_vmx(vcpu);
5898         unsigned long exit_qualification;
5899         bool has_error_code = false;
5900         u32 error_code = 0;
5901         u16 tss_selector;
5902         int reason, type, idt_v, idt_index;
5903
5904         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5905         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5906         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5907
5908         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5909
5910         reason = (u32)exit_qualification >> 30;
5911         if (reason == TASK_SWITCH_GATE && idt_v) {
5912                 switch (type) {
5913                 case INTR_TYPE_NMI_INTR:
5914                         vcpu->arch.nmi_injected = false;
5915                         vmx_set_nmi_mask(vcpu, true);
5916                         break;
5917                 case INTR_TYPE_EXT_INTR:
5918                 case INTR_TYPE_SOFT_INTR:
5919                         kvm_clear_interrupt_queue(vcpu);
5920                         break;
5921                 case INTR_TYPE_HARD_EXCEPTION:
5922                         if (vmx->idt_vectoring_info &
5923                             VECTORING_INFO_DELIVER_CODE_MASK) {
5924                                 has_error_code = true;
5925                                 error_code =
5926                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5927                         }
5928                         /* fall through */
5929                 case INTR_TYPE_SOFT_EXCEPTION:
5930                         kvm_clear_exception_queue(vcpu);
5931                         break;
5932                 default:
5933                         break;
5934                 }
5935         }
5936         tss_selector = exit_qualification;
5937
5938         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5939                        type != INTR_TYPE_EXT_INTR &&
5940                        type != INTR_TYPE_NMI_INTR))
5941                 skip_emulated_instruction(vcpu);
5942
5943         if (kvm_task_switch(vcpu, tss_selector,
5944                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5945                             has_error_code, error_code) == EMULATE_FAIL) {
5946                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5947                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5948                 vcpu->run->internal.ndata = 0;
5949                 return 0;
5950         }
5951
5952         /*
5953          * TODO: What about debug traps on tss switch?
5954          *       Are we supposed to inject them and update dr6?
5955          */
5956
5957         return 1;
5958 }
5959
5960 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5961 {
5962         unsigned long exit_qualification;
5963         gpa_t gpa;
5964         u32 error_code;
5965         int gla_validity;
5966
5967         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5968
5969         gla_validity = (exit_qualification >> 7) & 0x3;
5970         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5971                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5972                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5973                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5974                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5975                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5976                         (long unsigned int)exit_qualification);
5977                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5978                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5979                 return 0;
5980         }
5981
5982         /*
5983          * EPT violation happened while executing iret from NMI,
5984          * "blocked by NMI" bit has to be set before next VM entry.
5985          * There are errata that may cause this bit to not be set:
5986          * AAK134, BY25.
5987          */
5988         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5989                         cpu_has_virtual_nmis() &&
5990                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5991                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5992
5993         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5994         trace_kvm_page_fault(gpa, exit_qualification);
5995
5996         /* It is a write fault? */
5997         error_code = exit_qualification & PFERR_WRITE_MASK;
5998         /* It is a fetch fault? */
5999         error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
6000         /* ept page table is present? */
6001         error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
6002
6003         vcpu->arch.exit_qualification = exit_qualification;
6004
6005         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
6006 }
6007
6008 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
6009 {
6010         int ret;
6011         gpa_t gpa;
6012
6013         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6014         if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
6015                 skip_emulated_instruction(vcpu);
6016                 trace_kvm_fast_mmio(gpa);
6017                 return 1;
6018         }
6019
6020         ret = handle_mmio_page_fault(vcpu, gpa, true);
6021         if (likely(ret == RET_MMIO_PF_EMULATE))
6022                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
6023                                               EMULATE_DONE;
6024
6025         if (unlikely(ret == RET_MMIO_PF_INVALID))
6026                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
6027
6028         if (unlikely(ret == RET_MMIO_PF_RETRY))
6029                 return 1;
6030
6031         /* It is the real ept misconfig */
6032         WARN_ON(1);
6033
6034         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6035         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
6036
6037         return 0;
6038 }
6039
6040 static int handle_nmi_window(struct kvm_vcpu *vcpu)
6041 {
6042         u32 cpu_based_vm_exec_control;
6043
6044         /* clear pending NMI */
6045         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6046         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6047         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
6048         ++vcpu->stat.nmi_window_exits;
6049         kvm_make_request(KVM_REQ_EVENT, vcpu);
6050
6051         return 1;
6052 }
6053
6054 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6055 {
6056         struct vcpu_vmx *vmx = to_vmx(vcpu);
6057         enum emulation_result err = EMULATE_DONE;
6058         int ret = 1;
6059         u32 cpu_exec_ctrl;
6060         bool intr_window_requested;
6061         unsigned count = 130;
6062
6063         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6064         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6065
6066         while (vmx->emulation_required && count-- != 0) {
6067                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6068                         return handle_interrupt_window(&vmx->vcpu);
6069
6070                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
6071                         return 1;
6072
6073                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
6074
6075                 if (err == EMULATE_USER_EXIT) {
6076                         ++vcpu->stat.mmio_exits;
6077                         ret = 0;
6078                         goto out;
6079                 }
6080
6081                 if (err != EMULATE_DONE) {
6082                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6083                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6084                         vcpu->run->internal.ndata = 0;
6085                         return 0;
6086                 }
6087
6088                 if (vcpu->arch.halt_request) {
6089                         vcpu->arch.halt_request = 0;
6090                         ret = kvm_vcpu_halt(vcpu);
6091                         goto out;
6092                 }
6093
6094                 if (signal_pending(current))
6095                         goto out;
6096                 if (need_resched())
6097                         schedule();
6098         }
6099
6100 out:
6101         return ret;
6102 }
6103
6104 static int __grow_ple_window(int val)
6105 {
6106         if (ple_window_grow < 1)
6107                 return ple_window;
6108
6109         val = min(val, ple_window_actual_max);
6110
6111         if (ple_window_grow < ple_window)
6112                 val *= ple_window_grow;
6113         else
6114                 val += ple_window_grow;
6115
6116         return val;
6117 }
6118
6119 static int __shrink_ple_window(int val, int modifier, int minimum)
6120 {
6121         if (modifier < 1)
6122                 return ple_window;
6123
6124         if (modifier < ple_window)
6125                 val /= modifier;
6126         else
6127                 val -= modifier;
6128
6129         return max(val, minimum);
6130 }
6131
6132 static void grow_ple_window(struct kvm_vcpu *vcpu)
6133 {
6134         struct vcpu_vmx *vmx = to_vmx(vcpu);
6135         int old = vmx->ple_window;
6136
6137         vmx->ple_window = __grow_ple_window(old);
6138
6139         if (vmx->ple_window != old)
6140                 vmx->ple_window_dirty = true;
6141
6142         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6143 }
6144
6145 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6146 {
6147         struct vcpu_vmx *vmx = to_vmx(vcpu);
6148         int old = vmx->ple_window;
6149
6150         vmx->ple_window = __shrink_ple_window(old,
6151                                               ple_window_shrink, ple_window);
6152
6153         if (vmx->ple_window != old)
6154                 vmx->ple_window_dirty = true;
6155
6156         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6157 }
6158
6159 /*
6160  * ple_window_actual_max is computed to be one grow_ple_window() below
6161  * ple_window_max. (See __grow_ple_window for the reason.)
6162  * This prevents overflows, because ple_window_max is int.
6163  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6164  * this process.
6165  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6166  */
6167 static void update_ple_window_actual_max(void)
6168 {
6169         ple_window_actual_max =
6170                         __shrink_ple_window(max(ple_window_max, ple_window),
6171                                             ple_window_grow, INT_MIN);
6172 }
6173
6174 /*
6175  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6176  */
6177 static void wakeup_handler(void)
6178 {
6179         struct kvm_vcpu *vcpu;
6180         int cpu = smp_processor_id();
6181
6182         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6183         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6184                         blocked_vcpu_list) {
6185                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6186
6187                 if (pi_test_on(pi_desc) == 1)
6188                         kvm_vcpu_kick(vcpu);
6189         }
6190         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6191 }
6192
6193 static __init int hardware_setup(void)
6194 {
6195         int r = -ENOMEM, i, msr;
6196
6197         rdmsrl_safe(MSR_EFER, &host_efer);
6198
6199         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6200                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6201
6202         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6203         if (!vmx_io_bitmap_a)
6204                 return r;
6205
6206         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6207         if (!vmx_io_bitmap_b)
6208                 goto out;
6209
6210         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6211         if (!vmx_msr_bitmap_legacy)
6212                 goto out1;
6213
6214         vmx_msr_bitmap_legacy_x2apic =
6215                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6216         if (!vmx_msr_bitmap_legacy_x2apic)
6217                 goto out2;
6218
6219         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6220         if (!vmx_msr_bitmap_longmode)
6221                 goto out3;
6222
6223         vmx_msr_bitmap_longmode_x2apic =
6224                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6225         if (!vmx_msr_bitmap_longmode_x2apic)
6226                 goto out4;
6227
6228         if (nested) {
6229                 vmx_msr_bitmap_nested =
6230                         (unsigned long *)__get_free_page(GFP_KERNEL);
6231                 if (!vmx_msr_bitmap_nested)
6232                         goto out5;
6233         }
6234
6235         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6236         if (!vmx_vmread_bitmap)
6237                 goto out6;
6238
6239         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6240         if (!vmx_vmwrite_bitmap)
6241                 goto out7;
6242
6243         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6244         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6245
6246         /*
6247          * Allow direct access to the PC debug port (it is often used for I/O
6248          * delays, but the vmexits simply slow things down).
6249          */
6250         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6251         clear_bit(0x80, vmx_io_bitmap_a);
6252
6253         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6254
6255         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6256         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6257         if (nested)
6258                 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
6259
6260         if (setup_vmcs_config(&vmcs_config) < 0) {
6261                 r = -EIO;
6262                 goto out8;
6263         }
6264
6265         if (boot_cpu_has(X86_FEATURE_NX))
6266                 kvm_enable_efer_bits(EFER_NX);
6267
6268         if (!cpu_has_vmx_vpid())
6269                 enable_vpid = 0;
6270         if (!cpu_has_vmx_shadow_vmcs())
6271                 enable_shadow_vmcs = 0;
6272         if (enable_shadow_vmcs)
6273                 init_vmcs_shadow_fields();
6274
6275         if (!cpu_has_vmx_ept() ||
6276             !cpu_has_vmx_ept_4levels()) {
6277                 enable_ept = 0;
6278                 enable_unrestricted_guest = 0;
6279                 enable_ept_ad_bits = 0;
6280         }
6281
6282         if (!cpu_has_vmx_ept_ad_bits())
6283                 enable_ept_ad_bits = 0;
6284
6285         if (!cpu_has_vmx_unrestricted_guest())
6286                 enable_unrestricted_guest = 0;
6287
6288         if (!cpu_has_vmx_flexpriority())
6289                 flexpriority_enabled = 0;
6290
6291         /*
6292          * set_apic_access_page_addr() is used to reload apic access
6293          * page upon invalidation.  No need to do anything if not
6294          * using the APIC_ACCESS_ADDR VMCS field.
6295          */
6296         if (!flexpriority_enabled)
6297                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6298
6299         if (!cpu_has_vmx_tpr_shadow())
6300                 kvm_x86_ops->update_cr8_intercept = NULL;
6301
6302         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6303                 kvm_disable_largepages();
6304
6305         if (!cpu_has_vmx_ple())
6306                 ple_gap = 0;
6307
6308         if (!cpu_has_vmx_apicv())
6309                 enable_apicv = 0;
6310
6311         if (cpu_has_vmx_tsc_scaling()) {
6312                 kvm_has_tsc_control = true;
6313                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6314                 kvm_tsc_scaling_ratio_frac_bits = 48;
6315         }
6316
6317         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6318         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6319         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6320         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6321         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6322         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6323         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6324
6325         memcpy(vmx_msr_bitmap_legacy_x2apic,
6326                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6327         memcpy(vmx_msr_bitmap_longmode_x2apic,
6328                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6329
6330         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6331
6332         if (enable_apicv) {
6333                 for (msr = 0x800; msr <= 0x8ff; msr++)
6334                         vmx_disable_intercept_msr_read_x2apic(msr);
6335
6336                 /* According SDM, in x2apic mode, the whole id reg is used.
6337                  * But in KVM, it only use the highest eight bits. Need to
6338                  * intercept it */
6339                 vmx_enable_intercept_msr_read_x2apic(0x802);
6340                 /* TMCCT */
6341                 vmx_enable_intercept_msr_read_x2apic(0x839);
6342                 /* TPR */
6343                 vmx_disable_intercept_msr_write_x2apic(0x808);
6344                 /* EOI */
6345                 vmx_disable_intercept_msr_write_x2apic(0x80b);
6346                 /* SELF-IPI */
6347                 vmx_disable_intercept_msr_write_x2apic(0x83f);
6348         }
6349
6350         if (enable_ept) {
6351                 kvm_mmu_set_mask_ptes(0ull,
6352                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6353                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6354                         0ull, VMX_EPT_EXECUTABLE_MASK);
6355                 ept_set_mmio_spte_mask();
6356                 kvm_enable_tdp();
6357         } else
6358                 kvm_disable_tdp();
6359
6360         update_ple_window_actual_max();
6361
6362         /*
6363          * Only enable PML when hardware supports PML feature, and both EPT
6364          * and EPT A/D bit features are enabled -- PML depends on them to work.
6365          */
6366         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6367                 enable_pml = 0;
6368
6369         if (!enable_pml) {
6370                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6371                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6372                 kvm_x86_ops->flush_log_dirty = NULL;
6373                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6374         }
6375
6376         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6377
6378         return alloc_kvm_area();
6379
6380 out8:
6381         free_page((unsigned long)vmx_vmwrite_bitmap);
6382 out7:
6383         free_page((unsigned long)vmx_vmread_bitmap);
6384 out6:
6385         if (nested)
6386                 free_page((unsigned long)vmx_msr_bitmap_nested);
6387 out5:
6388         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6389 out4:
6390         free_page((unsigned long)vmx_msr_bitmap_longmode);
6391 out3:
6392         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6393 out2:
6394         free_page((unsigned long)vmx_msr_bitmap_legacy);
6395 out1:
6396         free_page((unsigned long)vmx_io_bitmap_b);
6397 out:
6398         free_page((unsigned long)vmx_io_bitmap_a);
6399
6400     return r;
6401 }
6402
6403 static __exit void hardware_unsetup(void)
6404 {
6405         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6406         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6407         free_page((unsigned long)vmx_msr_bitmap_legacy);
6408         free_page((unsigned long)vmx_msr_bitmap_longmode);
6409         free_page((unsigned long)vmx_io_bitmap_b);
6410         free_page((unsigned long)vmx_io_bitmap_a);
6411         free_page((unsigned long)vmx_vmwrite_bitmap);
6412         free_page((unsigned long)vmx_vmread_bitmap);
6413         if (nested)
6414                 free_page((unsigned long)vmx_msr_bitmap_nested);
6415
6416         free_kvm_area();
6417 }
6418
6419 /*
6420  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6421  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6422  */
6423 static int handle_pause(struct kvm_vcpu *vcpu)
6424 {
6425         if (ple_gap)
6426                 grow_ple_window(vcpu);
6427
6428         skip_emulated_instruction(vcpu);
6429         kvm_vcpu_on_spin(vcpu);
6430
6431         return 1;
6432 }
6433
6434 static int handle_nop(struct kvm_vcpu *vcpu)
6435 {
6436         skip_emulated_instruction(vcpu);
6437         return 1;
6438 }
6439
6440 static int handle_mwait(struct kvm_vcpu *vcpu)
6441 {
6442         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6443         return handle_nop(vcpu);
6444 }
6445
6446 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6447 {
6448         return 1;
6449 }
6450
6451 static int handle_monitor(struct kvm_vcpu *vcpu)
6452 {
6453         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6454         return handle_nop(vcpu);
6455 }
6456
6457 /*
6458  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6459  * We could reuse a single VMCS for all the L2 guests, but we also want the
6460  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6461  * allows keeping them loaded on the processor, and in the future will allow
6462  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6463  * every entry if they never change.
6464  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6465  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6466  *
6467  * The following functions allocate and free a vmcs02 in this pool.
6468  */
6469
6470 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6471 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6472 {
6473         struct vmcs02_list *item;
6474         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6475                 if (item->vmptr == vmx->nested.current_vmptr) {
6476                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6477                         return &item->vmcs02;
6478                 }
6479
6480         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6481                 /* Recycle the least recently used VMCS. */
6482                 item = list_last_entry(&vmx->nested.vmcs02_pool,
6483                                        struct vmcs02_list, list);
6484                 item->vmptr = vmx->nested.current_vmptr;
6485                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6486                 return &item->vmcs02;
6487         }
6488
6489         /* Create a new VMCS */
6490         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6491         if (!item)
6492                 return NULL;
6493         item->vmcs02.vmcs = alloc_vmcs();
6494         if (!item->vmcs02.vmcs) {
6495                 kfree(item);
6496                 return NULL;
6497         }
6498         loaded_vmcs_init(&item->vmcs02);
6499         item->vmptr = vmx->nested.current_vmptr;
6500         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6501         vmx->nested.vmcs02_num++;
6502         return &item->vmcs02;
6503 }
6504
6505 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6506 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6507 {
6508         struct vmcs02_list *item;
6509         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6510                 if (item->vmptr == vmptr) {
6511                         free_loaded_vmcs(&item->vmcs02);
6512                         list_del(&item->list);
6513                         kfree(item);
6514                         vmx->nested.vmcs02_num--;
6515                         return;
6516                 }
6517 }
6518
6519 /*
6520  * Free all VMCSs saved for this vcpu, except the one pointed by
6521  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6522  * must be &vmx->vmcs01.
6523  */
6524 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6525 {
6526         struct vmcs02_list *item, *n;
6527
6528         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6529         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6530                 /*
6531                  * Something will leak if the above WARN triggers.  Better than
6532                  * a use-after-free.
6533                  */
6534                 if (vmx->loaded_vmcs == &item->vmcs02)
6535                         continue;
6536
6537                 free_loaded_vmcs(&item->vmcs02);
6538                 list_del(&item->list);
6539                 kfree(item);
6540                 vmx->nested.vmcs02_num--;
6541         }
6542 }
6543
6544 /*
6545  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6546  * set the success or error code of an emulated VMX instruction, as specified
6547  * by Vol 2B, VMX Instruction Reference, "Conventions".
6548  */
6549 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6550 {
6551         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6552                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6553                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6554 }
6555
6556 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6557 {
6558         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6559                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6560                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6561                         | X86_EFLAGS_CF);
6562 }
6563
6564 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6565                                         u32 vm_instruction_error)
6566 {
6567         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6568                 /*
6569                  * failValid writes the error number to the current VMCS, which
6570                  * can't be done there isn't a current VMCS.
6571                  */
6572                 nested_vmx_failInvalid(vcpu);
6573                 return;
6574         }
6575         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6576                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6577                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6578                         | X86_EFLAGS_ZF);
6579         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6580         /*
6581          * We don't need to force a shadow sync because
6582          * VM_INSTRUCTION_ERROR is not shadowed
6583          */
6584 }
6585
6586 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6587 {
6588         /* TODO: not to reset guest simply here. */
6589         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6590         pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6591 }
6592
6593 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6594 {
6595         struct vcpu_vmx *vmx =
6596                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6597
6598         vmx->nested.preemption_timer_expired = true;
6599         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6600         kvm_vcpu_kick(&vmx->vcpu);
6601
6602         return HRTIMER_NORESTART;
6603 }
6604
6605 /*
6606  * Decode the memory-address operand of a vmx instruction, as recorded on an
6607  * exit caused by such an instruction (run by a guest hypervisor).
6608  * On success, returns 0. When the operand is invalid, returns 1 and throws
6609  * #UD or #GP.
6610  */
6611 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6612                                  unsigned long exit_qualification,
6613                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
6614 {
6615         gva_t off;
6616         bool exn;
6617         struct kvm_segment s;
6618
6619         /*
6620          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6621          * Execution", on an exit, vmx_instruction_info holds most of the
6622          * addressing components of the operand. Only the displacement part
6623          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6624          * For how an actual address is calculated from all these components,
6625          * refer to Vol. 1, "Operand Addressing".
6626          */
6627         int  scaling = vmx_instruction_info & 3;
6628         int  addr_size = (vmx_instruction_info >> 7) & 7;
6629         bool is_reg = vmx_instruction_info & (1u << 10);
6630         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6631         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6632         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6633         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6634         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6635
6636         if (is_reg) {
6637                 kvm_queue_exception(vcpu, UD_VECTOR);
6638                 return 1;
6639         }
6640
6641         /* Addr = segment_base + offset */
6642         /* offset = base + [index * scale] + displacement */
6643         off = exit_qualification; /* holds the displacement */
6644         if (base_is_valid)
6645                 off += kvm_register_read(vcpu, base_reg);
6646         if (index_is_valid)
6647                 off += kvm_register_read(vcpu, index_reg)<<scaling;
6648         vmx_get_segment(vcpu, &s, seg_reg);
6649         *ret = s.base + off;
6650
6651         if (addr_size == 1) /* 32 bit */
6652                 *ret &= 0xffffffff;
6653
6654         /* Checks for #GP/#SS exceptions. */
6655         exn = false;
6656         if (is_protmode(vcpu)) {
6657                 /* Protected mode: apply checks for segment validity in the
6658                  * following order:
6659                  * - segment type check (#GP(0) may be thrown)
6660                  * - usability check (#GP(0)/#SS(0))
6661                  * - limit check (#GP(0)/#SS(0))
6662                  */
6663                 if (wr)
6664                         /* #GP(0) if the destination operand is located in a
6665                          * read-only data segment or any code segment.
6666                          */
6667                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
6668                 else
6669                         /* #GP(0) if the source operand is located in an
6670                          * execute-only code segment
6671                          */
6672                         exn = ((s.type & 0xa) == 8);
6673         }
6674         if (exn) {
6675                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6676                 return 1;
6677         }
6678         if (is_long_mode(vcpu)) {
6679                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6680                  * non-canonical form. This is an only check for long mode.
6681                  */
6682                 exn = is_noncanonical_address(*ret);
6683         } else if (is_protmode(vcpu)) {
6684                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6685                  */
6686                 exn = (s.unusable != 0);
6687                 /* Protected mode: #GP(0)/#SS(0) if the memory
6688                  * operand is outside the segment limit.
6689                  */
6690                 exn = exn || (off + sizeof(u64) > s.limit);
6691         }
6692         if (exn) {
6693                 kvm_queue_exception_e(vcpu,
6694                                       seg_reg == VCPU_SREG_SS ?
6695                                                 SS_VECTOR : GP_VECTOR,
6696                                       0);
6697                 return 1;
6698         }
6699
6700         return 0;
6701 }
6702
6703 /*
6704  * This function performs the various checks including
6705  * - if it's 4KB aligned
6706  * - No bits beyond the physical address width are set
6707  * - Returns 0 on success or else 1
6708  * (Intel SDM Section 30.3)
6709  */
6710 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6711                                   gpa_t *vmpointer)
6712 {
6713         gva_t gva;
6714         gpa_t vmptr;
6715         struct x86_exception e;
6716         struct page *page;
6717         struct vcpu_vmx *vmx = to_vmx(vcpu);
6718         int maxphyaddr = cpuid_maxphyaddr(vcpu);
6719
6720         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6721                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6722                 return 1;
6723
6724         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6725                                 sizeof(vmptr), &e)) {
6726                 kvm_inject_page_fault(vcpu, &e);
6727                 return 1;
6728         }
6729
6730         switch (exit_reason) {
6731         case EXIT_REASON_VMON:
6732                 /*
6733                  * SDM 3: 24.11.5
6734                  * The first 4 bytes of VMXON region contain the supported
6735                  * VMCS revision identifier
6736                  *
6737                  * Note - IA32_VMX_BASIC[48] will never be 1
6738                  * for the nested case;
6739                  * which replaces physical address width with 32
6740                  *
6741                  */
6742                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6743                         nested_vmx_failInvalid(vcpu);
6744                         skip_emulated_instruction(vcpu);
6745                         return 1;
6746                 }
6747
6748                 page = nested_get_page(vcpu, vmptr);
6749                 if (page == NULL ||
6750                     *(u32 *)kmap(page) != VMCS12_REVISION) {
6751                         nested_vmx_failInvalid(vcpu);
6752                         kunmap(page);
6753                         skip_emulated_instruction(vcpu);
6754                         return 1;
6755                 }
6756                 kunmap(page);
6757                 vmx->nested.vmxon_ptr = vmptr;
6758                 break;
6759         case EXIT_REASON_VMCLEAR:
6760                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6761                         nested_vmx_failValid(vcpu,
6762                                              VMXERR_VMCLEAR_INVALID_ADDRESS);
6763                         skip_emulated_instruction(vcpu);
6764                         return 1;
6765                 }
6766
6767                 if (vmptr == vmx->nested.vmxon_ptr) {
6768                         nested_vmx_failValid(vcpu,
6769                                              VMXERR_VMCLEAR_VMXON_POINTER);
6770                         skip_emulated_instruction(vcpu);
6771                         return 1;
6772                 }
6773                 break;
6774         case EXIT_REASON_VMPTRLD:
6775                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6776                         nested_vmx_failValid(vcpu,
6777                                              VMXERR_VMPTRLD_INVALID_ADDRESS);
6778                         skip_emulated_instruction(vcpu);
6779                         return 1;
6780                 }
6781
6782                 if (vmptr == vmx->nested.vmxon_ptr) {
6783                         nested_vmx_failValid(vcpu,
6784                                              VMXERR_VMCLEAR_VMXON_POINTER);
6785                         skip_emulated_instruction(vcpu);
6786                         return 1;
6787                 }
6788                 break;
6789         default:
6790                 return 1; /* shouldn't happen */
6791         }
6792
6793         if (vmpointer)
6794                 *vmpointer = vmptr;
6795         return 0;
6796 }
6797
6798 /*
6799  * Emulate the VMXON instruction.
6800  * Currently, we just remember that VMX is active, and do not save or even
6801  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6802  * do not currently need to store anything in that guest-allocated memory
6803  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6804  * argument is different from the VMXON pointer (which the spec says they do).
6805  */
6806 static int handle_vmon(struct kvm_vcpu *vcpu)
6807 {
6808         struct kvm_segment cs;
6809         struct vcpu_vmx *vmx = to_vmx(vcpu);
6810         struct vmcs *shadow_vmcs;
6811         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6812                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6813
6814         /* The Intel VMX Instruction Reference lists a bunch of bits that
6815          * are prerequisite to running VMXON, most notably cr4.VMXE must be
6816          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6817          * Otherwise, we should fail with #UD. We test these now:
6818          */
6819         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6820             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6821             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6822                 kvm_queue_exception(vcpu, UD_VECTOR);
6823                 return 1;
6824         }
6825
6826         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6827         if (is_long_mode(vcpu) && !cs.l) {
6828                 kvm_queue_exception(vcpu, UD_VECTOR);
6829                 return 1;
6830         }
6831
6832         if (vmx_get_cpl(vcpu)) {
6833                 kvm_inject_gp(vcpu, 0);
6834                 return 1;
6835         }
6836
6837         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
6838                 return 1;
6839
6840         if (vmx->nested.vmxon) {
6841                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6842                 skip_emulated_instruction(vcpu);
6843                 return 1;
6844         }
6845
6846         if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6847                         != VMXON_NEEDED_FEATURES) {
6848                 kvm_inject_gp(vcpu, 0);
6849                 return 1;
6850         }
6851
6852         if (enable_shadow_vmcs) {
6853                 shadow_vmcs = alloc_vmcs();
6854                 if (!shadow_vmcs)
6855                         return -ENOMEM;
6856                 /* mark vmcs as shadow */
6857                 shadow_vmcs->revision_id |= (1u << 31);
6858                 /* init shadow vmcs */
6859                 vmcs_clear(shadow_vmcs);
6860                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6861         }
6862
6863         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6864         vmx->nested.vmcs02_num = 0;
6865
6866         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6867                      HRTIMER_MODE_REL);
6868         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6869
6870         vmx->nested.vmxon = true;
6871
6872         skip_emulated_instruction(vcpu);
6873         nested_vmx_succeed(vcpu);
6874         return 1;
6875 }
6876
6877 /*
6878  * Intel's VMX Instruction Reference specifies a common set of prerequisites
6879  * for running VMX instructions (except VMXON, whose prerequisites are
6880  * slightly different). It also specifies what exception to inject otherwise.
6881  */
6882 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6883 {
6884         struct kvm_segment cs;
6885         struct vcpu_vmx *vmx = to_vmx(vcpu);
6886
6887         if (!vmx->nested.vmxon) {
6888                 kvm_queue_exception(vcpu, UD_VECTOR);
6889                 return 0;
6890         }
6891
6892         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6893         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6894             (is_long_mode(vcpu) && !cs.l)) {
6895                 kvm_queue_exception(vcpu, UD_VECTOR);
6896                 return 0;
6897         }
6898
6899         if (vmx_get_cpl(vcpu)) {
6900                 kvm_inject_gp(vcpu, 0);
6901                 return 0;
6902         }
6903
6904         return 1;
6905 }
6906
6907 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6908 {
6909         if (vmx->nested.current_vmptr == -1ull)
6910                 return;
6911
6912         /* current_vmptr and current_vmcs12 are always set/reset together */
6913         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6914                 return;
6915
6916         if (enable_shadow_vmcs) {
6917                 /* copy to memory all shadowed fields in case
6918                    they were modified */
6919                 copy_shadow_to_vmcs12(vmx);
6920                 vmx->nested.sync_shadow_vmcs = false;
6921                 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
6922                                 SECONDARY_EXEC_SHADOW_VMCS);
6923                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6924         }
6925         vmx->nested.posted_intr_nv = -1;
6926         kunmap(vmx->nested.current_vmcs12_page);
6927         nested_release_page(vmx->nested.current_vmcs12_page);
6928         vmx->nested.current_vmptr = -1ull;
6929         vmx->nested.current_vmcs12 = NULL;
6930 }
6931
6932 /*
6933  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6934  * just stops using VMX.
6935  */
6936 static void free_nested(struct vcpu_vmx *vmx)
6937 {
6938         if (!vmx->nested.vmxon)
6939                 return;
6940
6941         vmx->nested.vmxon = false;
6942         free_vpid(vmx->nested.vpid02);
6943         nested_release_vmcs12(vmx);
6944         if (enable_shadow_vmcs)
6945                 free_vmcs(vmx->nested.current_shadow_vmcs);
6946         /* Unpin physical memory we referred to in current vmcs02 */
6947         if (vmx->nested.apic_access_page) {
6948                 nested_release_page(vmx->nested.apic_access_page);
6949                 vmx->nested.apic_access_page = NULL;
6950         }
6951         if (vmx->nested.virtual_apic_page) {
6952                 nested_release_page(vmx->nested.virtual_apic_page);
6953                 vmx->nested.virtual_apic_page = NULL;
6954         }
6955         if (vmx->nested.pi_desc_page) {
6956                 kunmap(vmx->nested.pi_desc_page);
6957                 nested_release_page(vmx->nested.pi_desc_page);
6958                 vmx->nested.pi_desc_page = NULL;
6959                 vmx->nested.pi_desc = NULL;
6960         }
6961
6962         nested_free_all_saved_vmcss(vmx);
6963 }
6964
6965 /* Emulate the VMXOFF instruction */
6966 static int handle_vmoff(struct kvm_vcpu *vcpu)
6967 {
6968         if (!nested_vmx_check_permission(vcpu))
6969                 return 1;
6970         free_nested(to_vmx(vcpu));
6971         skip_emulated_instruction(vcpu);
6972         nested_vmx_succeed(vcpu);
6973         return 1;
6974 }
6975
6976 /* Emulate the VMCLEAR instruction */
6977 static int handle_vmclear(struct kvm_vcpu *vcpu)
6978 {
6979         struct vcpu_vmx *vmx = to_vmx(vcpu);
6980         gpa_t vmptr;
6981         struct vmcs12 *vmcs12;
6982         struct page *page;
6983
6984         if (!nested_vmx_check_permission(vcpu))
6985                 return 1;
6986
6987         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
6988                 return 1;
6989
6990         if (vmptr == vmx->nested.current_vmptr)
6991                 nested_release_vmcs12(vmx);
6992
6993         page = nested_get_page(vcpu, vmptr);
6994         if (page == NULL) {
6995                 /*
6996                  * For accurate processor emulation, VMCLEAR beyond available
6997                  * physical memory should do nothing at all. However, it is
6998                  * possible that a nested vmx bug, not a guest hypervisor bug,
6999                  * resulted in this case, so let's shut down before doing any
7000                  * more damage:
7001                  */
7002                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7003                 return 1;
7004         }
7005         vmcs12 = kmap(page);
7006         vmcs12->launch_state = 0;
7007         kunmap(page);
7008         nested_release_page(page);
7009
7010         nested_free_vmcs02(vmx, vmptr);
7011
7012         skip_emulated_instruction(vcpu);
7013         nested_vmx_succeed(vcpu);
7014         return 1;
7015 }
7016
7017 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7018
7019 /* Emulate the VMLAUNCH instruction */
7020 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7021 {
7022         return nested_vmx_run(vcpu, true);
7023 }
7024
7025 /* Emulate the VMRESUME instruction */
7026 static int handle_vmresume(struct kvm_vcpu *vcpu)
7027 {
7028
7029         return nested_vmx_run(vcpu, false);
7030 }
7031
7032 enum vmcs_field_type {
7033         VMCS_FIELD_TYPE_U16 = 0,
7034         VMCS_FIELD_TYPE_U64 = 1,
7035         VMCS_FIELD_TYPE_U32 = 2,
7036         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
7037 };
7038
7039 static inline int vmcs_field_type(unsigned long field)
7040 {
7041         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
7042                 return VMCS_FIELD_TYPE_U32;
7043         return (field >> 13) & 0x3 ;
7044 }
7045
7046 static inline int vmcs_field_readonly(unsigned long field)
7047 {
7048         return (((field >> 10) & 0x3) == 1);
7049 }
7050
7051 /*
7052  * Read a vmcs12 field. Since these can have varying lengths and we return
7053  * one type, we chose the biggest type (u64) and zero-extend the return value
7054  * to that size. Note that the caller, handle_vmread, might need to use only
7055  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7056  * 64-bit fields are to be returned).
7057  */
7058 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7059                                   unsigned long field, u64 *ret)
7060 {
7061         short offset = vmcs_field_to_offset(field);
7062         char *p;
7063
7064         if (offset < 0)
7065                 return offset;
7066
7067         p = ((char *)(get_vmcs12(vcpu))) + offset;
7068
7069         switch (vmcs_field_type(field)) {
7070         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7071                 *ret = *((natural_width *)p);
7072                 return 0;
7073         case VMCS_FIELD_TYPE_U16:
7074                 *ret = *((u16 *)p);
7075                 return 0;
7076         case VMCS_FIELD_TYPE_U32:
7077                 *ret = *((u32 *)p);
7078                 return 0;
7079         case VMCS_FIELD_TYPE_U64:
7080                 *ret = *((u64 *)p);
7081                 return 0;
7082         default:
7083                 WARN_ON(1);
7084                 return -ENOENT;
7085         }
7086 }
7087
7088
7089 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7090                                    unsigned long field, u64 field_value){
7091         short offset = vmcs_field_to_offset(field);
7092         char *p = ((char *) get_vmcs12(vcpu)) + offset;
7093         if (offset < 0)
7094                 return offset;
7095
7096         switch (vmcs_field_type(field)) {
7097         case VMCS_FIELD_TYPE_U16:
7098                 *(u16 *)p = field_value;
7099                 return 0;
7100         case VMCS_FIELD_TYPE_U32:
7101                 *(u32 *)p = field_value;
7102                 return 0;
7103         case VMCS_FIELD_TYPE_U64:
7104                 *(u64 *)p = field_value;
7105                 return 0;
7106         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7107                 *(natural_width *)p = field_value;
7108                 return 0;
7109         default:
7110                 WARN_ON(1);
7111                 return -ENOENT;
7112         }
7113
7114 }
7115
7116 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7117 {
7118         int i;
7119         unsigned long field;
7120         u64 field_value;
7121         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7122         const unsigned long *fields = shadow_read_write_fields;
7123         const int num_fields = max_shadow_read_write_fields;
7124
7125         preempt_disable();
7126
7127         vmcs_load(shadow_vmcs);
7128
7129         for (i = 0; i < num_fields; i++) {
7130                 field = fields[i];
7131                 switch (vmcs_field_type(field)) {
7132                 case VMCS_FIELD_TYPE_U16:
7133                         field_value = vmcs_read16(field);
7134                         break;
7135                 case VMCS_FIELD_TYPE_U32:
7136                         field_value = vmcs_read32(field);
7137                         break;
7138                 case VMCS_FIELD_TYPE_U64:
7139                         field_value = vmcs_read64(field);
7140                         break;
7141                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7142                         field_value = vmcs_readl(field);
7143                         break;
7144                 default:
7145                         WARN_ON(1);
7146                         continue;
7147                 }
7148                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7149         }
7150
7151         vmcs_clear(shadow_vmcs);
7152         vmcs_load(vmx->loaded_vmcs->vmcs);
7153
7154         preempt_enable();
7155 }
7156
7157 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7158 {
7159         const unsigned long *fields[] = {
7160                 shadow_read_write_fields,
7161                 shadow_read_only_fields
7162         };
7163         const int max_fields[] = {
7164                 max_shadow_read_write_fields,
7165                 max_shadow_read_only_fields
7166         };
7167         int i, q;
7168         unsigned long field;
7169         u64 field_value = 0;
7170         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7171
7172         vmcs_load(shadow_vmcs);
7173
7174         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7175                 for (i = 0; i < max_fields[q]; i++) {
7176                         field = fields[q][i];
7177                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7178
7179                         switch (vmcs_field_type(field)) {
7180                         case VMCS_FIELD_TYPE_U16:
7181                                 vmcs_write16(field, (u16)field_value);
7182                                 break;
7183                         case VMCS_FIELD_TYPE_U32:
7184                                 vmcs_write32(field, (u32)field_value);
7185                                 break;
7186                         case VMCS_FIELD_TYPE_U64:
7187                                 vmcs_write64(field, (u64)field_value);
7188                                 break;
7189                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7190                                 vmcs_writel(field, (long)field_value);
7191                                 break;
7192                         default:
7193                                 WARN_ON(1);
7194                                 break;
7195                         }
7196                 }
7197         }
7198
7199         vmcs_clear(shadow_vmcs);
7200         vmcs_load(vmx->loaded_vmcs->vmcs);
7201 }
7202
7203 /*
7204  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7205  * used before) all generate the same failure when it is missing.
7206  */
7207 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7208 {
7209         struct vcpu_vmx *vmx = to_vmx(vcpu);
7210         if (vmx->nested.current_vmptr == -1ull) {
7211                 nested_vmx_failInvalid(vcpu);
7212                 skip_emulated_instruction(vcpu);
7213                 return 0;
7214         }
7215         return 1;
7216 }
7217
7218 static int handle_vmread(struct kvm_vcpu *vcpu)
7219 {
7220         unsigned long field;
7221         u64 field_value;
7222         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7223         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7224         gva_t gva = 0;
7225
7226         if (!nested_vmx_check_permission(vcpu) ||
7227             !nested_vmx_check_vmcs12(vcpu))
7228                 return 1;
7229
7230         /* Decode instruction info and find the field to read */
7231         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7232         /* Read the field, zero-extended to a u64 field_value */
7233         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7234                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7235                 skip_emulated_instruction(vcpu);
7236                 return 1;
7237         }
7238         /*
7239          * Now copy part of this value to register or memory, as requested.
7240          * Note that the number of bits actually copied is 32 or 64 depending
7241          * on the guest's mode (32 or 64 bit), not on the given field's length.
7242          */
7243         if (vmx_instruction_info & (1u << 10)) {
7244                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7245                         field_value);
7246         } else {
7247                 if (get_vmx_mem_address(vcpu, exit_qualification,
7248                                 vmx_instruction_info, true, &gva))
7249                         return 1;
7250                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7251                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7252                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7253         }
7254
7255         nested_vmx_succeed(vcpu);
7256         skip_emulated_instruction(vcpu);
7257         return 1;
7258 }
7259
7260
7261 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7262 {
7263         unsigned long field;
7264         gva_t gva;
7265         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7266         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7267         /* The value to write might be 32 or 64 bits, depending on L1's long
7268          * mode, and eventually we need to write that into a field of several
7269          * possible lengths. The code below first zero-extends the value to 64
7270          * bit (field_value), and then copies only the appropriate number of
7271          * bits into the vmcs12 field.
7272          */
7273         u64 field_value = 0;
7274         struct x86_exception e;
7275
7276         if (!nested_vmx_check_permission(vcpu) ||
7277             !nested_vmx_check_vmcs12(vcpu))
7278                 return 1;
7279
7280         if (vmx_instruction_info & (1u << 10))
7281                 field_value = kvm_register_readl(vcpu,
7282                         (((vmx_instruction_info) >> 3) & 0xf));
7283         else {
7284                 if (get_vmx_mem_address(vcpu, exit_qualification,
7285                                 vmx_instruction_info, false, &gva))
7286                         return 1;
7287                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7288                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7289                         kvm_inject_page_fault(vcpu, &e);
7290                         return 1;
7291                 }
7292         }
7293
7294
7295         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7296         if (vmcs_field_readonly(field)) {
7297                 nested_vmx_failValid(vcpu,
7298                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7299                 skip_emulated_instruction(vcpu);
7300                 return 1;
7301         }
7302
7303         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7304                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7305                 skip_emulated_instruction(vcpu);
7306                 return 1;
7307         }
7308
7309         nested_vmx_succeed(vcpu);
7310         skip_emulated_instruction(vcpu);
7311         return 1;
7312 }
7313
7314 /* Emulate the VMPTRLD instruction */
7315 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7316 {
7317         struct vcpu_vmx *vmx = to_vmx(vcpu);
7318         gpa_t vmptr;
7319
7320         if (!nested_vmx_check_permission(vcpu))
7321                 return 1;
7322
7323         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7324                 return 1;
7325
7326         if (vmx->nested.current_vmptr != vmptr) {
7327                 struct vmcs12 *new_vmcs12;
7328                 struct page *page;
7329                 page = nested_get_page(vcpu, vmptr);
7330                 if (page == NULL) {
7331                         nested_vmx_failInvalid(vcpu);
7332                         skip_emulated_instruction(vcpu);
7333                         return 1;
7334                 }
7335                 new_vmcs12 = kmap(page);
7336                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7337                         kunmap(page);
7338                         nested_release_page_clean(page);
7339                         nested_vmx_failValid(vcpu,
7340                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7341                         skip_emulated_instruction(vcpu);
7342                         return 1;
7343                 }
7344
7345                 nested_release_vmcs12(vmx);
7346                 vmx->nested.current_vmptr = vmptr;
7347                 vmx->nested.current_vmcs12 = new_vmcs12;
7348                 vmx->nested.current_vmcs12_page = page;
7349                 if (enable_shadow_vmcs) {
7350                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7351                                       SECONDARY_EXEC_SHADOW_VMCS);
7352                         vmcs_write64(VMCS_LINK_POINTER,
7353                                      __pa(vmx->nested.current_shadow_vmcs));
7354                         vmx->nested.sync_shadow_vmcs = true;
7355                 }
7356         }
7357
7358         nested_vmx_succeed(vcpu);
7359         skip_emulated_instruction(vcpu);
7360         return 1;
7361 }
7362
7363 /* Emulate the VMPTRST instruction */
7364 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7365 {
7366         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7367         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7368         gva_t vmcs_gva;
7369         struct x86_exception e;
7370
7371         if (!nested_vmx_check_permission(vcpu))
7372                 return 1;
7373
7374         if (get_vmx_mem_address(vcpu, exit_qualification,
7375                         vmx_instruction_info, true, &vmcs_gva))
7376                 return 1;
7377         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7378         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7379                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7380                                  sizeof(u64), &e)) {
7381                 kvm_inject_page_fault(vcpu, &e);
7382                 return 1;
7383         }
7384         nested_vmx_succeed(vcpu);
7385         skip_emulated_instruction(vcpu);
7386         return 1;
7387 }
7388
7389 /* Emulate the INVEPT instruction */
7390 static int handle_invept(struct kvm_vcpu *vcpu)
7391 {
7392         struct vcpu_vmx *vmx = to_vmx(vcpu);
7393         u32 vmx_instruction_info, types;
7394         unsigned long type;
7395         gva_t gva;
7396         struct x86_exception e;
7397         struct {
7398                 u64 eptp, gpa;
7399         } operand;
7400
7401         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7402               SECONDARY_EXEC_ENABLE_EPT) ||
7403             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7404                 kvm_queue_exception(vcpu, UD_VECTOR);
7405                 return 1;
7406         }
7407
7408         if (!nested_vmx_check_permission(vcpu))
7409                 return 1;
7410
7411         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7412                 kvm_queue_exception(vcpu, UD_VECTOR);
7413                 return 1;
7414         }
7415
7416         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7417         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7418
7419         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7420
7421         if (!(types & (1UL << type))) {
7422                 nested_vmx_failValid(vcpu,
7423                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7424                 skip_emulated_instruction(vcpu);
7425                 return 1;
7426         }
7427
7428         /* According to the Intel VMX instruction reference, the memory
7429          * operand is read even if it isn't needed (e.g., for type==global)
7430          */
7431         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7432                         vmx_instruction_info, false, &gva))
7433                 return 1;
7434         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7435                                 sizeof(operand), &e)) {
7436                 kvm_inject_page_fault(vcpu, &e);
7437                 return 1;
7438         }
7439
7440         switch (type) {
7441         case VMX_EPT_EXTENT_GLOBAL:
7442                 kvm_mmu_sync_roots(vcpu);
7443                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7444                 nested_vmx_succeed(vcpu);
7445                 break;
7446         default:
7447                 /* Trap single context invalidation invept calls */
7448                 BUG_ON(1);
7449                 break;
7450         }
7451
7452         skip_emulated_instruction(vcpu);
7453         return 1;
7454 }
7455
7456 static int handle_invvpid(struct kvm_vcpu *vcpu)
7457 {
7458         struct vcpu_vmx *vmx = to_vmx(vcpu);
7459         u32 vmx_instruction_info;
7460         unsigned long type, types;
7461         gva_t gva;
7462         struct x86_exception e;
7463         int vpid;
7464
7465         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7466               SECONDARY_EXEC_ENABLE_VPID) ||
7467                         !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7468                 kvm_queue_exception(vcpu, UD_VECTOR);
7469                 return 1;
7470         }
7471
7472         if (!nested_vmx_check_permission(vcpu))
7473                 return 1;
7474
7475         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7476         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7477
7478         types = (vmx->nested.nested_vmx_vpid_caps >> 8) & 0x7;
7479
7480         if (!(types & (1UL << type))) {
7481                 nested_vmx_failValid(vcpu,
7482                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7483                 skip_emulated_instruction(vcpu);
7484                 return 1;
7485         }
7486
7487         /* according to the intel vmx instruction reference, the memory
7488          * operand is read even if it isn't needed (e.g., for type==global)
7489          */
7490         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7491                         vmx_instruction_info, false, &gva))
7492                 return 1;
7493         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7494                                 sizeof(u32), &e)) {
7495                 kvm_inject_page_fault(vcpu, &e);
7496                 return 1;
7497         }
7498
7499         switch (type) {
7500         case VMX_VPID_EXTENT_SINGLE_CONTEXT:
7501                 /*
7502                  * Old versions of KVM use the single-context version so we
7503                  * have to support it; just treat it the same as all-context.
7504                  */
7505         case VMX_VPID_EXTENT_ALL_CONTEXT:
7506                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
7507                 nested_vmx_succeed(vcpu);
7508                 break;
7509         default:
7510                 /* Trap individual address invalidation invvpid calls */
7511                 BUG_ON(1);
7512                 break;
7513         }
7514
7515         skip_emulated_instruction(vcpu);
7516         return 1;
7517 }
7518
7519 static int handle_pml_full(struct kvm_vcpu *vcpu)
7520 {
7521         unsigned long exit_qualification;
7522
7523         trace_kvm_pml_full(vcpu->vcpu_id);
7524
7525         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7526
7527         /*
7528          * PML buffer FULL happened while executing iret from NMI,
7529          * "blocked by NMI" bit has to be set before next VM entry.
7530          */
7531         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7532                         cpu_has_virtual_nmis() &&
7533                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7534                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7535                                 GUEST_INTR_STATE_NMI);
7536
7537         /*
7538          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7539          * here.., and there's no userspace involvement needed for PML.
7540          */
7541         return 1;
7542 }
7543
7544 static int handle_pcommit(struct kvm_vcpu *vcpu)
7545 {
7546         /* we never catch pcommit instruct for L1 guest. */
7547         WARN_ON(1);
7548         return 1;
7549 }
7550
7551 /*
7552  * The exit handlers return 1 if the exit was handled fully and guest execution
7553  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
7554  * to be done to userspace and return 0.
7555  */
7556 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7557         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
7558         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
7559         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
7560         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
7561         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
7562         [EXIT_REASON_CR_ACCESS]               = handle_cr,
7563         [EXIT_REASON_DR_ACCESS]               = handle_dr,
7564         [EXIT_REASON_CPUID]                   = handle_cpuid,
7565         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
7566         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
7567         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
7568         [EXIT_REASON_HLT]                     = handle_halt,
7569         [EXIT_REASON_INVD]                    = handle_invd,
7570         [EXIT_REASON_INVLPG]                  = handle_invlpg,
7571         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
7572         [EXIT_REASON_VMCALL]                  = handle_vmcall,
7573         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
7574         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
7575         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
7576         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
7577         [EXIT_REASON_VMREAD]                  = handle_vmread,
7578         [EXIT_REASON_VMRESUME]                = handle_vmresume,
7579         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
7580         [EXIT_REASON_VMOFF]                   = handle_vmoff,
7581         [EXIT_REASON_VMON]                    = handle_vmon,
7582         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
7583         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
7584         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
7585         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
7586         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
7587         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
7588         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
7589         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
7590         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
7591         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
7592         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
7593         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
7594         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
7595         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
7596         [EXIT_REASON_INVEPT]                  = handle_invept,
7597         [EXIT_REASON_INVVPID]                 = handle_invvpid,
7598         [EXIT_REASON_XSAVES]                  = handle_xsaves,
7599         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
7600         [EXIT_REASON_PML_FULL]                = handle_pml_full,
7601         [EXIT_REASON_PCOMMIT]                 = handle_pcommit,
7602 };
7603
7604 static const int kvm_vmx_max_exit_handlers =
7605         ARRAY_SIZE(kvm_vmx_exit_handlers);
7606
7607 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7608                                        struct vmcs12 *vmcs12)
7609 {
7610         unsigned long exit_qualification;
7611         gpa_t bitmap, last_bitmap;
7612         unsigned int port;
7613         int size;
7614         u8 b;
7615
7616         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7617                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7618
7619         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7620
7621         port = exit_qualification >> 16;
7622         size = (exit_qualification & 7) + 1;
7623
7624         last_bitmap = (gpa_t)-1;
7625         b = -1;
7626
7627         while (size > 0) {
7628                 if (port < 0x8000)
7629                         bitmap = vmcs12->io_bitmap_a;
7630                 else if (port < 0x10000)
7631                         bitmap = vmcs12->io_bitmap_b;
7632                 else
7633                         return true;
7634                 bitmap += (port & 0x7fff) / 8;
7635
7636                 if (last_bitmap != bitmap)
7637                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7638                                 return true;
7639                 if (b & (1 << (port & 7)))
7640                         return true;
7641
7642                 port++;
7643                 size--;
7644                 last_bitmap = bitmap;
7645         }
7646
7647         return false;
7648 }
7649
7650 /*
7651  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7652  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7653  * disinterest in the current event (read or write a specific MSR) by using an
7654  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7655  */
7656 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7657         struct vmcs12 *vmcs12, u32 exit_reason)
7658 {
7659         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7660         gpa_t bitmap;
7661
7662         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7663                 return true;
7664
7665         /*
7666          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7667          * for the four combinations of read/write and low/high MSR numbers.
7668          * First we need to figure out which of the four to use:
7669          */
7670         bitmap = vmcs12->msr_bitmap;
7671         if (exit_reason == EXIT_REASON_MSR_WRITE)
7672                 bitmap += 2048;
7673         if (msr_index >= 0xc0000000) {
7674                 msr_index -= 0xc0000000;
7675                 bitmap += 1024;
7676         }
7677
7678         /* Then read the msr_index'th bit from this bitmap: */
7679         if (msr_index < 1024*8) {
7680                 unsigned char b;
7681                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7682                         return true;
7683                 return 1 & (b >> (msr_index & 7));
7684         } else
7685                 return true; /* let L1 handle the wrong parameter */
7686 }
7687
7688 /*
7689  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7690  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7691  * intercept (via guest_host_mask etc.) the current event.
7692  */
7693 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7694         struct vmcs12 *vmcs12)
7695 {
7696         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7697         int cr = exit_qualification & 15;
7698         int reg = (exit_qualification >> 8) & 15;
7699         unsigned long val = kvm_register_readl(vcpu, reg);
7700
7701         switch ((exit_qualification >> 4) & 3) {
7702         case 0: /* mov to cr */
7703                 switch (cr) {
7704                 case 0:
7705                         if (vmcs12->cr0_guest_host_mask &
7706                             (val ^ vmcs12->cr0_read_shadow))
7707                                 return true;
7708                         break;
7709                 case 3:
7710                         if ((vmcs12->cr3_target_count >= 1 &&
7711                                         vmcs12->cr3_target_value0 == val) ||
7712                                 (vmcs12->cr3_target_count >= 2 &&
7713                                         vmcs12->cr3_target_value1 == val) ||
7714                                 (vmcs12->cr3_target_count >= 3 &&
7715                                         vmcs12->cr3_target_value2 == val) ||
7716                                 (vmcs12->cr3_target_count >= 4 &&
7717                                         vmcs12->cr3_target_value3 == val))
7718                                 return false;
7719                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7720                                 return true;
7721                         break;
7722                 case 4:
7723                         if (vmcs12->cr4_guest_host_mask &
7724                             (vmcs12->cr4_read_shadow ^ val))
7725                                 return true;
7726                         break;
7727                 case 8:
7728                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7729                                 return true;
7730                         break;
7731                 }
7732                 break;
7733         case 2: /* clts */
7734                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7735                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
7736                         return true;
7737                 break;
7738         case 1: /* mov from cr */
7739                 switch (cr) {
7740                 case 3:
7741                         if (vmcs12->cpu_based_vm_exec_control &
7742                             CPU_BASED_CR3_STORE_EXITING)
7743                                 return true;
7744                         break;
7745                 case 8:
7746                         if (vmcs12->cpu_based_vm_exec_control &
7747                             CPU_BASED_CR8_STORE_EXITING)
7748                                 return true;
7749                         break;
7750                 }
7751                 break;
7752         case 3: /* lmsw */
7753                 /*
7754                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7755                  * cr0. Other attempted changes are ignored, with no exit.
7756                  */
7757                 if (vmcs12->cr0_guest_host_mask & 0xe &
7758                     (val ^ vmcs12->cr0_read_shadow))
7759                         return true;
7760                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7761                     !(vmcs12->cr0_read_shadow & 0x1) &&
7762                     (val & 0x1))
7763                         return true;
7764                 break;
7765         }
7766         return false;
7767 }
7768
7769 /*
7770  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7771  * should handle it ourselves in L0 (and then continue L2). Only call this
7772  * when in is_guest_mode (L2).
7773  */
7774 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7775 {
7776         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7777         struct vcpu_vmx *vmx = to_vmx(vcpu);
7778         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7779         u32 exit_reason = vmx->exit_reason;
7780
7781         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7782                                 vmcs_readl(EXIT_QUALIFICATION),
7783                                 vmx->idt_vectoring_info,
7784                                 intr_info,
7785                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7786                                 KVM_ISA_VMX);
7787
7788         if (vmx->nested.nested_run_pending)
7789                 return false;
7790
7791         if (unlikely(vmx->fail)) {
7792                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7793                                     vmcs_read32(VM_INSTRUCTION_ERROR));
7794                 return true;
7795         }
7796
7797         switch (exit_reason) {
7798         case EXIT_REASON_EXCEPTION_NMI:
7799                 if (!is_exception(intr_info))
7800                         return false;
7801                 else if (is_page_fault(intr_info))
7802                         return enable_ept;
7803                 else if (is_no_device(intr_info) &&
7804                          !(vmcs12->guest_cr0 & X86_CR0_TS))
7805                         return false;
7806                 else if (is_debug(intr_info) &&
7807                          vcpu->guest_debug &
7808                          (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
7809                         return false;
7810                 else if (is_breakpoint(intr_info) &&
7811                          vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
7812                         return false;
7813                 return vmcs12->exception_bitmap &
7814                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7815         case EXIT_REASON_EXTERNAL_INTERRUPT:
7816                 return false;
7817         case EXIT_REASON_TRIPLE_FAULT:
7818                 return true;
7819         case EXIT_REASON_PENDING_INTERRUPT:
7820                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
7821         case EXIT_REASON_NMI_WINDOW:
7822                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
7823         case EXIT_REASON_TASK_SWITCH:
7824                 return true;
7825         case EXIT_REASON_CPUID:
7826                 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7827                         return false;
7828                 return true;
7829         case EXIT_REASON_HLT:
7830                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7831         case EXIT_REASON_INVD:
7832                 return true;
7833         case EXIT_REASON_INVLPG:
7834                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7835         case EXIT_REASON_RDPMC:
7836                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7837         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
7838                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7839         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7840         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7841         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7842         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7843         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
7844         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
7845                 /*
7846                  * VMX instructions trap unconditionally. This allows L1 to
7847                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
7848                  */
7849                 return true;
7850         case EXIT_REASON_CR_ACCESS:
7851                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7852         case EXIT_REASON_DR_ACCESS:
7853                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7854         case EXIT_REASON_IO_INSTRUCTION:
7855                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
7856         case EXIT_REASON_MSR_READ:
7857         case EXIT_REASON_MSR_WRITE:
7858                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7859         case EXIT_REASON_INVALID_STATE:
7860                 return true;
7861         case EXIT_REASON_MWAIT_INSTRUCTION:
7862                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7863         case EXIT_REASON_MONITOR_TRAP_FLAG:
7864                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
7865         case EXIT_REASON_MONITOR_INSTRUCTION:
7866                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7867         case EXIT_REASON_PAUSE_INSTRUCTION:
7868                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7869                         nested_cpu_has2(vmcs12,
7870                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7871         case EXIT_REASON_MCE_DURING_VMENTRY:
7872                 return false;
7873         case EXIT_REASON_TPR_BELOW_THRESHOLD:
7874                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
7875         case EXIT_REASON_APIC_ACCESS:
7876                 return nested_cpu_has2(vmcs12,
7877                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7878         case EXIT_REASON_APIC_WRITE:
7879         case EXIT_REASON_EOI_INDUCED:
7880                 /* apic_write and eoi_induced should exit unconditionally. */
7881                 return true;
7882         case EXIT_REASON_EPT_VIOLATION:
7883                 /*
7884                  * L0 always deals with the EPT violation. If nested EPT is
7885                  * used, and the nested mmu code discovers that the address is
7886                  * missing in the guest EPT table (EPT12), the EPT violation
7887                  * will be injected with nested_ept_inject_page_fault()
7888                  */
7889                 return false;
7890         case EXIT_REASON_EPT_MISCONFIG:
7891                 /*
7892                  * L2 never uses directly L1's EPT, but rather L0's own EPT
7893                  * table (shadow on EPT) or a merged EPT table that L0 built
7894                  * (EPT on EPT). So any problems with the structure of the
7895                  * table is L0's fault.
7896                  */
7897                 return false;
7898         case EXIT_REASON_WBINVD:
7899                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7900         case EXIT_REASON_XSETBV:
7901                 return true;
7902         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7903                 /*
7904                  * This should never happen, since it is not possible to
7905                  * set XSS to a non-zero value---neither in L1 nor in L2.
7906                  * If if it were, XSS would have to be checked against
7907                  * the XSS exit bitmap in vmcs12.
7908                  */
7909                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
7910         case EXIT_REASON_PCOMMIT:
7911                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_PCOMMIT);
7912         default:
7913                 return true;
7914         }
7915 }
7916
7917 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7918 {
7919         *info1 = vmcs_readl(EXIT_QUALIFICATION);
7920         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7921 }
7922
7923 static int vmx_create_pml_buffer(struct vcpu_vmx *vmx)
7924 {
7925         struct page *pml_pg;
7926
7927         pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
7928         if (!pml_pg)
7929                 return -ENOMEM;
7930
7931         vmx->pml_pg = pml_pg;
7932
7933         vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
7934         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7935
7936         return 0;
7937 }
7938
7939 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
7940 {
7941         if (vmx->pml_pg) {
7942                 __free_page(vmx->pml_pg);
7943                 vmx->pml_pg = NULL;
7944         }
7945 }
7946
7947 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
7948 {
7949         struct vcpu_vmx *vmx = to_vmx(vcpu);
7950         u64 *pml_buf;
7951         u16 pml_idx;
7952
7953         pml_idx = vmcs_read16(GUEST_PML_INDEX);
7954
7955         /* Do nothing if PML buffer is empty */
7956         if (pml_idx == (PML_ENTITY_NUM - 1))
7957                 return;
7958
7959         /* PML index always points to next available PML buffer entity */
7960         if (pml_idx >= PML_ENTITY_NUM)
7961                 pml_idx = 0;
7962         else
7963                 pml_idx++;
7964
7965         pml_buf = page_address(vmx->pml_pg);
7966         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7967                 u64 gpa;
7968
7969                 gpa = pml_buf[pml_idx];
7970                 WARN_ON(gpa & (PAGE_SIZE - 1));
7971                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
7972         }
7973
7974         /* reset PML index */
7975         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7976 }
7977
7978 /*
7979  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7980  * Called before reporting dirty_bitmap to userspace.
7981  */
7982 static void kvm_flush_pml_buffers(struct kvm *kvm)
7983 {
7984         int i;
7985         struct kvm_vcpu *vcpu;
7986         /*
7987          * We only need to kick vcpu out of guest mode here, as PML buffer
7988          * is flushed at beginning of all VMEXITs, and it's obvious that only
7989          * vcpus running in guest are possible to have unflushed GPAs in PML
7990          * buffer.
7991          */
7992         kvm_for_each_vcpu(i, vcpu, kvm)
7993                 kvm_vcpu_kick(vcpu);
7994 }
7995
7996 static void vmx_dump_sel(char *name, uint32_t sel)
7997 {
7998         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
7999                name, vmcs_read32(sel),
8000                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8001                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8002                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8003 }
8004
8005 static void vmx_dump_dtsel(char *name, uint32_t limit)
8006 {
8007         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
8008                name, vmcs_read32(limit),
8009                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8010 }
8011
8012 static void dump_vmcs(void)
8013 {
8014         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8015         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8016         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8017         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8018         u32 secondary_exec_control = 0;
8019         unsigned long cr4 = vmcs_readl(GUEST_CR4);
8020         u64 efer = vmcs_read64(GUEST_IA32_EFER);
8021         int i, n;
8022
8023         if (cpu_has_secondary_exec_ctrls())
8024                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8025
8026         pr_err("*** Guest State ***\n");
8027         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8028                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8029                vmcs_readl(CR0_GUEST_HOST_MASK));
8030         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8031                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8032         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8033         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8034             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8035         {
8036                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
8037                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8038                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
8039                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
8040         }
8041         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
8042                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8043         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
8044                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8045         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8046                vmcs_readl(GUEST_SYSENTER_ESP),
8047                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8048         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
8049         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
8050         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
8051         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
8052         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
8053         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
8054         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8055         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8056         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8057         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
8058         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8059             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
8060                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
8061                        efer, vmcs_read64(GUEST_IA32_PAT));
8062         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
8063                vmcs_read64(GUEST_IA32_DEBUGCTL),
8064                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8065         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
8066                 pr_err("PerfGlobCtl = 0x%016llx\n",
8067                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
8068         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
8069                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
8070         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
8071                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8072                vmcs_read32(GUEST_ACTIVITY_STATE));
8073         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8074                 pr_err("InterruptStatus = %04x\n",
8075                        vmcs_read16(GUEST_INTR_STATUS));
8076
8077         pr_err("*** Host State ***\n");
8078         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
8079                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8080         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8081                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8082                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8083                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8084                vmcs_read16(HOST_TR_SELECTOR));
8085         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8086                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8087                vmcs_readl(HOST_TR_BASE));
8088         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8089                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8090         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8091                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8092                vmcs_readl(HOST_CR4));
8093         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8094                vmcs_readl(HOST_IA32_SYSENTER_ESP),
8095                vmcs_read32(HOST_IA32_SYSENTER_CS),
8096                vmcs_readl(HOST_IA32_SYSENTER_EIP));
8097         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8098                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
8099                        vmcs_read64(HOST_IA32_EFER),
8100                        vmcs_read64(HOST_IA32_PAT));
8101         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8102                 pr_err("PerfGlobCtl = 0x%016llx\n",
8103                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
8104
8105         pr_err("*** Control State ***\n");
8106         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8107                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8108         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8109         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8110                vmcs_read32(EXCEPTION_BITMAP),
8111                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8112                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8113         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8114                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8115                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8116                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8117         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8118                vmcs_read32(VM_EXIT_INTR_INFO),
8119                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8120                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8121         pr_err("        reason=%08x qualification=%016lx\n",
8122                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8123         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8124                vmcs_read32(IDT_VECTORING_INFO_FIELD),
8125                vmcs_read32(IDT_VECTORING_ERROR_CODE));
8126         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8127         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8128                 pr_err("TSC Multiplier = 0x%016llx\n",
8129                        vmcs_read64(TSC_MULTIPLIER));
8130         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8131                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8132         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8133                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8134         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8135                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8136         n = vmcs_read32(CR3_TARGET_COUNT);
8137         for (i = 0; i + 1 < n; i += 4)
8138                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8139                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8140                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8141         if (i < n)
8142                 pr_err("CR3 target%u=%016lx\n",
8143                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8144         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8145                 pr_err("PLE Gap=%08x Window=%08x\n",
8146                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8147         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8148                 pr_err("Virtual processor ID = 0x%04x\n",
8149                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
8150 }
8151
8152 /*
8153  * The guest has exited.  See if we can fix it or if we need userspace
8154  * assistance.
8155  */
8156 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8157 {
8158         struct vcpu_vmx *vmx = to_vmx(vcpu);
8159         u32 exit_reason = vmx->exit_reason;
8160         u32 vectoring_info = vmx->idt_vectoring_info;
8161
8162         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8163
8164         /*
8165          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8166          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8167          * querying dirty_bitmap, we only need to kick all vcpus out of guest
8168          * mode as if vcpus is in root mode, the PML buffer must has been
8169          * flushed already.
8170          */
8171         if (enable_pml)
8172                 vmx_flush_pml_buffer(vcpu);
8173
8174         /* If guest state is invalid, start emulating */
8175         if (vmx->emulation_required)
8176                 return handle_invalid_guest_state(vcpu);
8177
8178         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8179                 nested_vmx_vmexit(vcpu, exit_reason,
8180                                   vmcs_read32(VM_EXIT_INTR_INFO),
8181                                   vmcs_readl(EXIT_QUALIFICATION));
8182                 return 1;
8183         }
8184
8185         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8186                 dump_vmcs();
8187                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8188                 vcpu->run->fail_entry.hardware_entry_failure_reason
8189                         = exit_reason;
8190                 return 0;
8191         }
8192
8193         if (unlikely(vmx->fail)) {
8194                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8195                 vcpu->run->fail_entry.hardware_entry_failure_reason
8196                         = vmcs_read32(VM_INSTRUCTION_ERROR);
8197                 return 0;
8198         }
8199
8200         /*
8201          * Note:
8202          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8203          * delivery event since it indicates guest is accessing MMIO.
8204          * The vm-exit can be triggered again after return to guest that
8205          * will cause infinite loop.
8206          */
8207         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8208                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8209                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
8210                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
8211                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8212                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8213                 vcpu->run->internal.ndata = 2;
8214                 vcpu->run->internal.data[0] = vectoring_info;
8215                 vcpu->run->internal.data[1] = exit_reason;
8216                 return 0;
8217         }
8218
8219         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
8220             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
8221                                         get_vmcs12(vcpu))))) {
8222                 if (vmx_interrupt_allowed(vcpu)) {
8223                         vmx->soft_vnmi_blocked = 0;
8224                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
8225                            vcpu->arch.nmi_pending) {
8226                         /*
8227                          * This CPU don't support us in finding the end of an
8228                          * NMI-blocked window if the guest runs with IRQs
8229                          * disabled. So we pull the trigger after 1 s of
8230                          * futile waiting, but inform the user about this.
8231                          */
8232                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8233                                "state on VCPU %d after 1 s timeout\n",
8234                                __func__, vcpu->vcpu_id);
8235                         vmx->soft_vnmi_blocked = 0;
8236                 }
8237         }
8238
8239         if (exit_reason < kvm_vmx_max_exit_handlers
8240             && kvm_vmx_exit_handlers[exit_reason])
8241                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8242         else {
8243                 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
8244                 kvm_queue_exception(vcpu, UD_VECTOR);
8245                 return 1;
8246         }
8247 }
8248
8249 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8250 {
8251         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8252
8253         if (is_guest_mode(vcpu) &&
8254                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8255                 return;
8256
8257         if (irr == -1 || tpr < irr) {
8258                 vmcs_write32(TPR_THRESHOLD, 0);
8259                 return;
8260         }
8261
8262         vmcs_write32(TPR_THRESHOLD, irr);
8263 }
8264
8265 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8266 {
8267         u32 sec_exec_control;
8268
8269         /*
8270          * There is not point to enable virtualize x2apic without enable
8271          * apicv
8272          */
8273         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
8274                                 !kvm_vcpu_apicv_active(vcpu))
8275                 return;
8276
8277         if (!cpu_need_tpr_shadow(vcpu))
8278                 return;
8279
8280         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8281
8282         if (set) {
8283                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8284                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8285         } else {
8286                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8287                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8288         }
8289         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8290
8291         vmx_set_msr_bitmap(vcpu);
8292 }
8293
8294 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8295 {
8296         struct vcpu_vmx *vmx = to_vmx(vcpu);
8297
8298         /*
8299          * Currently we do not handle the nested case where L2 has an
8300          * APIC access page of its own; that page is still pinned.
8301          * Hence, we skip the case where the VCPU is in guest mode _and_
8302          * L1 prepared an APIC access page for L2.
8303          *
8304          * For the case where L1 and L2 share the same APIC access page
8305          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8306          * in the vmcs12), this function will only update either the vmcs01
8307          * or the vmcs02.  If the former, the vmcs02 will be updated by
8308          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
8309          * the next L2->L1 exit.
8310          */
8311         if (!is_guest_mode(vcpu) ||
8312             !nested_cpu_has2(vmx->nested.current_vmcs12,
8313                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8314                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8315 }
8316
8317 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
8318 {
8319         u16 status;
8320         u8 old;
8321
8322         if (isr == -1)
8323                 isr = 0;
8324
8325         status = vmcs_read16(GUEST_INTR_STATUS);
8326         old = status >> 8;
8327         if (isr != old) {
8328                 status &= 0xff;
8329                 status |= isr << 8;
8330                 vmcs_write16(GUEST_INTR_STATUS, status);
8331         }
8332 }
8333
8334 static void vmx_set_rvi(int vector)
8335 {
8336         u16 status;
8337         u8 old;
8338
8339         if (vector == -1)
8340                 vector = 0;
8341
8342         status = vmcs_read16(GUEST_INTR_STATUS);
8343         old = (u8)status & 0xff;
8344         if ((u8)vector != old) {
8345                 status &= ~0xff;
8346                 status |= (u8)vector;
8347                 vmcs_write16(GUEST_INTR_STATUS, status);
8348         }
8349 }
8350
8351 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8352 {
8353         if (!is_guest_mode(vcpu)) {
8354                 vmx_set_rvi(max_irr);
8355                 return;
8356         }
8357
8358         if (max_irr == -1)
8359                 return;
8360
8361         /*
8362          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
8363          * handles it.
8364          */
8365         if (nested_exit_on_intr(vcpu))
8366                 return;
8367
8368         /*
8369          * Else, fall back to pre-APICv interrupt injection since L2
8370          * is run without virtual interrupt delivery.
8371          */
8372         if (!kvm_event_needs_reinjection(vcpu) &&
8373             vmx_interrupt_allowed(vcpu)) {
8374                 kvm_queue_interrupt(vcpu, max_irr, false);
8375                 vmx_inject_irq(vcpu);
8376         }
8377 }
8378
8379 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
8380 {
8381         if (!kvm_vcpu_apicv_active(vcpu))
8382                 return;
8383
8384         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8385         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8386         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8387         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8388 }
8389
8390 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8391 {
8392         u32 exit_intr_info;
8393
8394         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8395               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8396                 return;
8397
8398         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8399         exit_intr_info = vmx->exit_intr_info;
8400
8401         /* Handle machine checks before interrupts are enabled */
8402         if (is_machine_check(exit_intr_info))
8403                 kvm_machine_check();
8404
8405         /* We need to handle NMIs before interrupts are enabled */
8406         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
8407             (exit_intr_info & INTR_INFO_VALID_MASK)) {
8408                 kvm_before_handle_nmi(&vmx->vcpu);
8409                 asm("int $2");
8410                 kvm_after_handle_nmi(&vmx->vcpu);
8411         }
8412 }
8413
8414 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8415 {
8416         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8417         register void *__sp asm(_ASM_SP);
8418
8419         /*
8420          * If external interrupt exists, IF bit is set in rflags/eflags on the
8421          * interrupt stack frame, and interrupt will be enabled on a return
8422          * from interrupt handler.
8423          */
8424         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8425                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8426                 unsigned int vector;
8427                 unsigned long entry;
8428                 gate_desc *desc;
8429                 struct vcpu_vmx *vmx = to_vmx(vcpu);
8430 #ifdef CONFIG_X86_64
8431                 unsigned long tmp;
8432 #endif
8433
8434                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
8435                 desc = (gate_desc *)vmx->host_idt_base + vector;
8436                 entry = gate_offset(*desc);
8437                 asm volatile(
8438 #ifdef CONFIG_X86_64
8439                         "mov %%" _ASM_SP ", %[sp]\n\t"
8440                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8441                         "push $%c[ss]\n\t"
8442                         "push %[sp]\n\t"
8443 #endif
8444                         "pushf\n\t"
8445                         "orl $0x200, (%%" _ASM_SP ")\n\t"
8446                         __ASM_SIZE(push) " $%c[cs]\n\t"
8447                         "call *%[entry]\n\t"
8448                         :
8449 #ifdef CONFIG_X86_64
8450                         [sp]"=&r"(tmp),
8451 #endif
8452                         "+r"(__sp)
8453                         :
8454                         [entry]"r"(entry),
8455                         [ss]"i"(__KERNEL_DS),
8456                         [cs]"i"(__KERNEL_CS)
8457                         );
8458         } else
8459                 local_irq_enable();
8460 }
8461
8462 static bool vmx_has_high_real_mode_segbase(void)
8463 {
8464         return enable_unrestricted_guest || emulate_invalid_guest_state;
8465 }
8466
8467 static bool vmx_mpx_supported(void)
8468 {
8469         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8470                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8471 }
8472
8473 static bool vmx_xsaves_supported(void)
8474 {
8475         return vmcs_config.cpu_based_2nd_exec_ctrl &
8476                 SECONDARY_EXEC_XSAVES;
8477 }
8478
8479 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8480 {
8481         u32 exit_intr_info;
8482         bool unblock_nmi;
8483         u8 vector;
8484         bool idtv_info_valid;
8485
8486         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8487
8488         if (cpu_has_virtual_nmis()) {
8489                 if (vmx->nmi_known_unmasked)
8490                         return;
8491                 /*
8492                  * Can't use vmx->exit_intr_info since we're not sure what
8493                  * the exit reason is.
8494                  */
8495                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8496                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8497                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8498                 /*
8499                  * SDM 3: 27.7.1.2 (September 2008)
8500                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
8501                  * a guest IRET fault.
8502                  * SDM 3: 23.2.2 (September 2008)
8503                  * Bit 12 is undefined in any of the following cases:
8504                  *  If the VM exit sets the valid bit in the IDT-vectoring
8505                  *   information field.
8506                  *  If the VM exit is due to a double fault.
8507                  */
8508                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8509                     vector != DF_VECTOR && !idtv_info_valid)
8510                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8511                                       GUEST_INTR_STATE_NMI);
8512                 else
8513                         vmx->nmi_known_unmasked =
8514                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8515                                   & GUEST_INTR_STATE_NMI);
8516         } else if (unlikely(vmx->soft_vnmi_blocked))
8517                 vmx->vnmi_blocked_time +=
8518                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8519 }
8520
8521 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8522                                       u32 idt_vectoring_info,
8523                                       int instr_len_field,
8524                                       int error_code_field)
8525 {
8526         u8 vector;
8527         int type;
8528         bool idtv_info_valid;
8529
8530         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8531
8532         vcpu->arch.nmi_injected = false;
8533         kvm_clear_exception_queue(vcpu);
8534         kvm_clear_interrupt_queue(vcpu);
8535
8536         if (!idtv_info_valid)
8537                 return;
8538
8539         kvm_make_request(KVM_REQ_EVENT, vcpu);
8540
8541         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8542         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8543
8544         switch (type) {
8545         case INTR_TYPE_NMI_INTR:
8546                 vcpu->arch.nmi_injected = true;
8547                 /*
8548                  * SDM 3: 27.7.1.2 (September 2008)
8549                  * Clear bit "block by NMI" before VM entry if a NMI
8550                  * delivery faulted.
8551                  */
8552                 vmx_set_nmi_mask(vcpu, false);
8553                 break;
8554         case INTR_TYPE_SOFT_EXCEPTION:
8555                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8556                 /* fall through */
8557         case INTR_TYPE_HARD_EXCEPTION:
8558                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8559                         u32 err = vmcs_read32(error_code_field);
8560                         kvm_requeue_exception_e(vcpu, vector, err);
8561                 } else
8562                         kvm_requeue_exception(vcpu, vector);
8563                 break;
8564         case INTR_TYPE_SOFT_INTR:
8565                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8566                 /* fall through */
8567         case INTR_TYPE_EXT_INTR:
8568                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8569                 break;
8570         default:
8571                 break;
8572         }
8573 }
8574
8575 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8576 {
8577         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8578                                   VM_EXIT_INSTRUCTION_LEN,
8579                                   IDT_VECTORING_ERROR_CODE);
8580 }
8581
8582 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8583 {
8584         __vmx_complete_interrupts(vcpu,
8585                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8586                                   VM_ENTRY_INSTRUCTION_LEN,
8587                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
8588
8589         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8590 }
8591
8592 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8593 {
8594         int i, nr_msrs;
8595         struct perf_guest_switch_msr *msrs;
8596
8597         msrs = perf_guest_get_msrs(&nr_msrs);
8598
8599         if (!msrs)
8600                 return;
8601
8602         for (i = 0; i < nr_msrs; i++)
8603                 if (msrs[i].host == msrs[i].guest)
8604                         clear_atomic_switch_msr(vmx, msrs[i].msr);
8605                 else
8606                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8607                                         msrs[i].host);
8608 }
8609
8610 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8611 {
8612         struct vcpu_vmx *vmx = to_vmx(vcpu);
8613         unsigned long debugctlmsr, cr4;
8614
8615         /* Record the guest's net vcpu time for enforced NMI injections. */
8616         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8617                 vmx->entry_time = ktime_get();
8618
8619         /* Don't enter VMX if guest state is invalid, let the exit handler
8620            start emulation until we arrive back to a valid state */
8621         if (vmx->emulation_required)
8622                 return;
8623
8624         if (vmx->ple_window_dirty) {
8625                 vmx->ple_window_dirty = false;
8626                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8627         }
8628
8629         if (vmx->nested.sync_shadow_vmcs) {
8630                 copy_vmcs12_to_shadow(vmx);
8631                 vmx->nested.sync_shadow_vmcs = false;
8632         }
8633
8634         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8635                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8636         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8637                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8638
8639         cr4 = cr4_read_shadow();
8640         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8641                 vmcs_writel(HOST_CR4, cr4);
8642                 vmx->host_state.vmcs_host_cr4 = cr4;
8643         }
8644
8645         /* When single-stepping over STI and MOV SS, we must clear the
8646          * corresponding interruptibility bits in the guest state. Otherwise
8647          * vmentry fails as it then expects bit 14 (BS) in pending debug
8648          * exceptions being set, but that's not correct for the guest debugging
8649          * case. */
8650         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8651                 vmx_set_interrupt_shadow(vcpu, 0);
8652
8653         if (vmx->guest_pkru_valid)
8654                 __write_pkru(vmx->guest_pkru);
8655
8656         atomic_switch_perf_msrs(vmx);
8657         debugctlmsr = get_debugctlmsr();
8658
8659         vmx->__launched = vmx->loaded_vmcs->launched;
8660         asm(
8661                 /* Store host registers */
8662                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8663                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8664                 "push %%" _ASM_CX " \n\t"
8665                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8666                 "je 1f \n\t"
8667                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8668                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8669                 "1: \n\t"
8670                 /* Reload cr2 if changed */
8671                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8672                 "mov %%cr2, %%" _ASM_DX " \n\t"
8673                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8674                 "je 2f \n\t"
8675                 "mov %%" _ASM_AX", %%cr2 \n\t"
8676                 "2: \n\t"
8677                 /* Check if vmlaunch of vmresume is needed */
8678                 "cmpl $0, %c[launched](%0) \n\t"
8679                 /* Load guest registers.  Don't clobber flags. */
8680                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8681                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8682                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8683                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8684                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8685                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8686 #ifdef CONFIG_X86_64
8687                 "mov %c[r8](%0),  %%r8  \n\t"
8688                 "mov %c[r9](%0),  %%r9  \n\t"
8689                 "mov %c[r10](%0), %%r10 \n\t"
8690                 "mov %c[r11](%0), %%r11 \n\t"
8691                 "mov %c[r12](%0), %%r12 \n\t"
8692                 "mov %c[r13](%0), %%r13 \n\t"
8693                 "mov %c[r14](%0), %%r14 \n\t"
8694                 "mov %c[r15](%0), %%r15 \n\t"
8695 #endif
8696                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8697
8698                 /* Enter guest mode */
8699                 "jne 1f \n\t"
8700                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8701                 "jmp 2f \n\t"
8702                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8703                 "2: "
8704                 /* Save guest registers, load host registers, keep flags */
8705                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8706                 "pop %0 \n\t"
8707                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8708                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8709                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8710                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8711                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8712                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8713                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8714 #ifdef CONFIG_X86_64
8715                 "mov %%r8,  %c[r8](%0) \n\t"
8716                 "mov %%r9,  %c[r9](%0) \n\t"
8717                 "mov %%r10, %c[r10](%0) \n\t"
8718                 "mov %%r11, %c[r11](%0) \n\t"
8719                 "mov %%r12, %c[r12](%0) \n\t"
8720                 "mov %%r13, %c[r13](%0) \n\t"
8721                 "mov %%r14, %c[r14](%0) \n\t"
8722                 "mov %%r15, %c[r15](%0) \n\t"
8723 #endif
8724                 "mov %%cr2, %%" _ASM_AX "   \n\t"
8725                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
8726
8727                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
8728                 "setbe %c[fail](%0) \n\t"
8729                 ".pushsection .rodata \n\t"
8730                 ".global vmx_return \n\t"
8731                 "vmx_return: " _ASM_PTR " 2b \n\t"
8732                 ".popsection"
8733               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
8734                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
8735                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
8736                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
8737                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8738                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8739                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8740                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8741                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8742                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8743                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
8744 #ifdef CONFIG_X86_64
8745                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8746                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8747                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8748                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8749                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8750                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8751                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8752                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
8753 #endif
8754                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8755                 [wordsize]"i"(sizeof(ulong))
8756               : "cc", "memory"
8757 #ifdef CONFIG_X86_64
8758                 , "rax", "rbx", "rdi", "rsi"
8759                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8760 #else
8761                 , "eax", "ebx", "edi", "esi"
8762 #endif
8763               );
8764
8765         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8766         if (debugctlmsr)
8767                 update_debugctlmsr(debugctlmsr);
8768
8769 #ifndef CONFIG_X86_64
8770         /*
8771          * The sysexit path does not restore ds/es, so we must set them to
8772          * a reasonable value ourselves.
8773          *
8774          * We can't defer this to vmx_load_host_state() since that function
8775          * may be executed in interrupt context, which saves and restore segments
8776          * around it, nullifying its effect.
8777          */
8778         loadsegment(ds, __USER_DS);
8779         loadsegment(es, __USER_DS);
8780 #endif
8781
8782         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
8783                                   | (1 << VCPU_EXREG_RFLAGS)
8784                                   | (1 << VCPU_EXREG_PDPTR)
8785                                   | (1 << VCPU_EXREG_SEGMENTS)
8786                                   | (1 << VCPU_EXREG_CR3));
8787         vcpu->arch.regs_dirty = 0;
8788
8789         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8790
8791         vmx->loaded_vmcs->launched = 1;
8792
8793         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
8794
8795         /*
8796          * eager fpu is enabled if PKEY is supported and CR4 is switched
8797          * back on host, so it is safe to read guest PKRU from current
8798          * XSAVE.
8799          */
8800         if (boot_cpu_has(X86_FEATURE_OSPKE)) {
8801                 vmx->guest_pkru = __read_pkru();
8802                 if (vmx->guest_pkru != vmx->host_pkru) {
8803                         vmx->guest_pkru_valid = true;
8804                         __write_pkru(vmx->host_pkru);
8805                 } else
8806                         vmx->guest_pkru_valid = false;
8807         }
8808
8809         /*
8810          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8811          * we did not inject a still-pending event to L1 now because of
8812          * nested_run_pending, we need to re-enable this bit.
8813          */
8814         if (vmx->nested.nested_run_pending)
8815                 kvm_make_request(KVM_REQ_EVENT, vcpu);
8816
8817         vmx->nested.nested_run_pending = 0;
8818
8819         vmx_complete_atomic_exit(vmx);
8820         vmx_recover_nmi_blocking(vmx);
8821         vmx_complete_interrupts(vmx);
8822 }
8823
8824 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8825 {
8826         struct vcpu_vmx *vmx = to_vmx(vcpu);
8827         int cpu;
8828
8829         if (vmx->loaded_vmcs == &vmx->vmcs01)
8830                 return;
8831
8832         cpu = get_cpu();
8833         vmx->loaded_vmcs = &vmx->vmcs01;
8834         vmx_vcpu_put(vcpu);
8835         vmx_vcpu_load(vcpu, cpu);
8836         vcpu->cpu = cpu;
8837         put_cpu();
8838 }
8839
8840 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8841 {
8842         struct vcpu_vmx *vmx = to_vmx(vcpu);
8843
8844         if (enable_pml)
8845                 vmx_destroy_pml_buffer(vmx);
8846         free_vpid(vmx->vpid);
8847         leave_guest_mode(vcpu);
8848         vmx_load_vmcs01(vcpu);
8849         free_nested(vmx);
8850         free_loaded_vmcs(vmx->loaded_vmcs);
8851         kfree(vmx->guest_msrs);
8852         kvm_vcpu_uninit(vcpu);
8853         kmem_cache_free(kvm_vcpu_cache, vmx);
8854 }
8855
8856 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
8857 {
8858         int err;
8859         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
8860         int cpu;
8861
8862         if (!vmx)
8863                 return ERR_PTR(-ENOMEM);
8864
8865         vmx->vpid = allocate_vpid();
8866
8867         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8868         if (err)
8869                 goto free_vcpu;
8870
8871         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
8872         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8873                      > PAGE_SIZE);
8874
8875         err = -ENOMEM;
8876         if (!vmx->guest_msrs) {
8877                 goto uninit_vcpu;
8878         }
8879
8880         vmx->loaded_vmcs = &vmx->vmcs01;
8881         vmx->loaded_vmcs->vmcs = alloc_vmcs();
8882         if (!vmx->loaded_vmcs->vmcs)
8883                 goto free_msrs;
8884         if (!vmm_exclusive)
8885                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8886         loaded_vmcs_init(vmx->loaded_vmcs);
8887         if (!vmm_exclusive)
8888                 kvm_cpu_vmxoff();
8889
8890         cpu = get_cpu();
8891         vmx_vcpu_load(&vmx->vcpu, cpu);
8892         vmx->vcpu.cpu = cpu;
8893         err = vmx_vcpu_setup(vmx);
8894         vmx_vcpu_put(&vmx->vcpu);
8895         put_cpu();
8896         if (err)
8897                 goto free_vmcs;
8898         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
8899                 err = alloc_apic_access_page(kvm);
8900                 if (err)
8901                         goto free_vmcs;
8902         }
8903
8904         if (enable_ept) {
8905                 if (!kvm->arch.ept_identity_map_addr)
8906                         kvm->arch.ept_identity_map_addr =
8907                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
8908                 err = init_rmode_identity_map(kvm);
8909                 if (err)
8910                         goto free_vmcs;
8911         }
8912
8913         if (nested) {
8914                 nested_vmx_setup_ctls_msrs(vmx);
8915                 vmx->nested.vpid02 = allocate_vpid();
8916         }
8917
8918         vmx->nested.posted_intr_nv = -1;
8919         vmx->nested.current_vmptr = -1ull;
8920         vmx->nested.current_vmcs12 = NULL;
8921
8922         /*
8923          * If PML is turned on, failure on enabling PML just results in failure
8924          * of creating the vcpu, therefore we can simplify PML logic (by
8925          * avoiding dealing with cases, such as enabling PML partially on vcpus
8926          * for the guest, etc.
8927          */
8928         if (enable_pml) {
8929                 err = vmx_create_pml_buffer(vmx);
8930                 if (err)
8931                         goto free_vmcs;
8932         }
8933
8934         return &vmx->vcpu;
8935
8936 free_vmcs:
8937         free_vpid(vmx->nested.vpid02);
8938         free_loaded_vmcs(vmx->loaded_vmcs);
8939 free_msrs:
8940         kfree(vmx->guest_msrs);
8941 uninit_vcpu:
8942         kvm_vcpu_uninit(&vmx->vcpu);
8943 free_vcpu:
8944         free_vpid(vmx->vpid);
8945         kmem_cache_free(kvm_vcpu_cache, vmx);
8946         return ERR_PTR(err);
8947 }
8948
8949 static void __init vmx_check_processor_compat(void *rtn)
8950 {
8951         struct vmcs_config vmcs_conf;
8952
8953         *(int *)rtn = 0;
8954         if (setup_vmcs_config(&vmcs_conf) < 0)
8955                 *(int *)rtn = -EIO;
8956         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8957                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8958                                 smp_processor_id());
8959                 *(int *)rtn = -EIO;
8960         }
8961 }
8962
8963 static int get_ept_level(void)
8964 {
8965         return VMX_EPT_DEFAULT_GAW + 1;
8966 }
8967
8968 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
8969 {
8970         u8 cache;
8971         u64 ipat = 0;
8972
8973         /* For VT-d and EPT combination
8974          * 1. MMIO: always map as UC
8975          * 2. EPT with VT-d:
8976          *   a. VT-d without snooping control feature: can't guarantee the
8977          *      result, try to trust guest.
8978          *   b. VT-d with snooping control feature: snooping control feature of
8979          *      VT-d engine can guarantee the cache correctness. Just set it
8980          *      to WB to keep consistent with host. So the same as item 3.
8981          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
8982          *    consistent with host MTRR
8983          */
8984         if (is_mmio) {
8985                 cache = MTRR_TYPE_UNCACHABLE;
8986                 goto exit;
8987         }
8988
8989         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
8990                 ipat = VMX_EPT_IPAT_BIT;
8991                 cache = MTRR_TYPE_WRBACK;
8992                 goto exit;
8993         }
8994
8995         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
8996                 ipat = VMX_EPT_IPAT_BIT;
8997                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
8998                         cache = MTRR_TYPE_WRBACK;
8999                 else
9000                         cache = MTRR_TYPE_UNCACHABLE;
9001                 goto exit;
9002         }
9003
9004         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
9005
9006 exit:
9007         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
9008 }
9009
9010 static int vmx_get_lpage_level(void)
9011 {
9012         if (enable_ept && !cpu_has_vmx_ept_1g_page())
9013                 return PT_DIRECTORY_LEVEL;
9014         else
9015                 /* For shadow and EPT supported 1GB page */
9016                 return PT_PDPE_LEVEL;
9017 }
9018
9019 static void vmcs_set_secondary_exec_control(u32 new_ctl)
9020 {
9021         /*
9022          * These bits in the secondary execution controls field
9023          * are dynamic, the others are mostly based on the hypervisor
9024          * architecture and the guest's CPUID.  Do not touch the
9025          * dynamic bits.
9026          */
9027         u32 mask =
9028                 SECONDARY_EXEC_SHADOW_VMCS |
9029                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9030                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9031
9032         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9033
9034         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9035                      (new_ctl & ~mask) | (cur_ctl & mask));
9036 }
9037
9038 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9039 {
9040         struct kvm_cpuid_entry2 *best;
9041         struct vcpu_vmx *vmx = to_vmx(vcpu);
9042         u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
9043
9044         if (vmx_rdtscp_supported()) {
9045                 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
9046                 if (!rdtscp_enabled)
9047                         secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
9048
9049                 if (nested) {
9050                         if (rdtscp_enabled)
9051                                 vmx->nested.nested_vmx_secondary_ctls_high |=
9052                                         SECONDARY_EXEC_RDTSCP;
9053                         else
9054                                 vmx->nested.nested_vmx_secondary_ctls_high &=
9055                                         ~SECONDARY_EXEC_RDTSCP;
9056                 }
9057         }
9058
9059         /* Exposing INVPCID only when PCID is exposed */
9060         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9061         if (vmx_invpcid_supported() &&
9062             (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
9063             !guest_cpuid_has_pcid(vcpu))) {
9064                 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
9065
9066                 if (best)
9067                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
9068         }
9069
9070         if (cpu_has_secondary_exec_ctrls())
9071                 vmcs_set_secondary_exec_control(secondary_exec_ctl);
9072
9073         if (static_cpu_has(X86_FEATURE_PCOMMIT) && nested) {
9074                 if (guest_cpuid_has_pcommit(vcpu))
9075                         vmx->nested.nested_vmx_secondary_ctls_high |=
9076                                 SECONDARY_EXEC_PCOMMIT;
9077                 else
9078                         vmx->nested.nested_vmx_secondary_ctls_high &=
9079                                 ~SECONDARY_EXEC_PCOMMIT;
9080         }
9081 }
9082
9083 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9084 {
9085         if (func == 1 && nested)
9086                 entry->ecx |= bit(X86_FEATURE_VMX);
9087 }
9088
9089 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9090                 struct x86_exception *fault)
9091 {
9092         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9093         u32 exit_reason;
9094
9095         if (fault->error_code & PFERR_RSVD_MASK)
9096                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9097         else
9098                 exit_reason = EXIT_REASON_EPT_VIOLATION;
9099         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
9100         vmcs12->guest_physical_address = fault->address;
9101 }
9102
9103 /* Callbacks for nested_ept_init_mmu_context: */
9104
9105 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9106 {
9107         /* return the page table to be shadowed - in our case, EPT12 */
9108         return get_vmcs12(vcpu)->ept_pointer;
9109 }
9110
9111 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9112 {
9113         WARN_ON(mmu_is_nested(vcpu));
9114         kvm_init_shadow_ept_mmu(vcpu,
9115                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9116                         VMX_EPT_EXECUTE_ONLY_BIT);
9117         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
9118         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
9119         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9120
9121         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
9122 }
9123
9124 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9125 {
9126         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9127 }
9128
9129 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9130                                             u16 error_code)
9131 {
9132         bool inequality, bit;
9133
9134         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9135         inequality =
9136                 (error_code & vmcs12->page_fault_error_code_mask) !=
9137                  vmcs12->page_fault_error_code_match;
9138         return inequality ^ bit;
9139 }
9140
9141 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9142                 struct x86_exception *fault)
9143 {
9144         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9145
9146         WARN_ON(!is_guest_mode(vcpu));
9147
9148         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9149                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9150                                   vmcs_read32(VM_EXIT_INTR_INFO),
9151                                   vmcs_readl(EXIT_QUALIFICATION));
9152         else
9153                 kvm_inject_page_fault(vcpu, fault);
9154 }
9155
9156 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9157                                         struct vmcs12 *vmcs12)
9158 {
9159         struct vcpu_vmx *vmx = to_vmx(vcpu);
9160         int maxphyaddr = cpuid_maxphyaddr(vcpu);
9161
9162         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9163                 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
9164                     vmcs12->apic_access_addr >> maxphyaddr)
9165                         return false;
9166
9167                 /*
9168                  * Translate L1 physical address to host physical
9169                  * address for vmcs02. Keep the page pinned, so this
9170                  * physical address remains valid. We keep a reference
9171                  * to it so we can release it later.
9172                  */
9173                 if (vmx->nested.apic_access_page) /* shouldn't happen */
9174                         nested_release_page(vmx->nested.apic_access_page);
9175                 vmx->nested.apic_access_page =
9176                         nested_get_page(vcpu, vmcs12->apic_access_addr);
9177         }
9178
9179         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9180                 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
9181                     vmcs12->virtual_apic_page_addr >> maxphyaddr)
9182                         return false;
9183
9184                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9185                         nested_release_page(vmx->nested.virtual_apic_page);
9186                 vmx->nested.virtual_apic_page =
9187                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9188
9189                 /*
9190                  * Failing the vm entry is _not_ what the processor does
9191                  * but it's basically the only possibility we have.
9192                  * We could still enter the guest if CR8 load exits are
9193                  * enabled, CR8 store exits are enabled, and virtualize APIC
9194                  * access is disabled; in this case the processor would never
9195                  * use the TPR shadow and we could simply clear the bit from
9196                  * the execution control.  But such a configuration is useless,
9197                  * so let's keep the code simple.
9198                  */
9199                 if (!vmx->nested.virtual_apic_page)
9200                         return false;
9201         }
9202
9203         if (nested_cpu_has_posted_intr(vmcs12)) {
9204                 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
9205                     vmcs12->posted_intr_desc_addr >> maxphyaddr)
9206                         return false;
9207
9208                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9209                         kunmap(vmx->nested.pi_desc_page);
9210                         nested_release_page(vmx->nested.pi_desc_page);
9211                 }
9212                 vmx->nested.pi_desc_page =
9213                         nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9214                 if (!vmx->nested.pi_desc_page)
9215                         return false;
9216
9217                 vmx->nested.pi_desc =
9218                         (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9219                 if (!vmx->nested.pi_desc) {
9220                         nested_release_page_clean(vmx->nested.pi_desc_page);
9221                         return false;
9222                 }
9223                 vmx->nested.pi_desc =
9224                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
9225                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9226                         (PAGE_SIZE - 1)));
9227         }
9228
9229         return true;
9230 }
9231
9232 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9233 {
9234         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9235         struct vcpu_vmx *vmx = to_vmx(vcpu);
9236
9237         if (vcpu->arch.virtual_tsc_khz == 0)
9238                 return;
9239
9240         /* Make sure short timeouts reliably trigger an immediate vmexit.
9241          * hrtimer_start does not guarantee this. */
9242         if (preemption_timeout <= 1) {
9243                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9244                 return;
9245         }
9246
9247         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9248         preemption_timeout *= 1000000;
9249         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9250         hrtimer_start(&vmx->nested.preemption_timer,
9251                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9252 }
9253
9254 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9255                                                 struct vmcs12 *vmcs12)
9256 {
9257         int maxphyaddr;
9258         u64 addr;
9259
9260         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9261                 return 0;
9262
9263         if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9264                 WARN_ON(1);
9265                 return -EINVAL;
9266         }
9267         maxphyaddr = cpuid_maxphyaddr(vcpu);
9268
9269         if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9270            ((addr + PAGE_SIZE) >> maxphyaddr))
9271                 return -EINVAL;
9272
9273         return 0;
9274 }
9275
9276 /*
9277  * Merge L0's and L1's MSR bitmap, return false to indicate that
9278  * we do not use the hardware.
9279  */
9280 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9281                                                struct vmcs12 *vmcs12)
9282 {
9283         int msr;
9284         struct page *page;
9285         unsigned long *msr_bitmap;
9286
9287         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9288                 return false;
9289
9290         page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9291         if (!page) {
9292                 WARN_ON(1);
9293                 return false;
9294         }
9295         msr_bitmap = (unsigned long *)kmap(page);
9296         if (!msr_bitmap) {
9297                 nested_release_page_clean(page);
9298                 WARN_ON(1);
9299                 return false;
9300         }
9301
9302         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9303                 if (nested_cpu_has_apic_reg_virt(vmcs12))
9304                         for (msr = 0x800; msr <= 0x8ff; msr++)
9305                                 nested_vmx_disable_intercept_for_msr(
9306                                         msr_bitmap,
9307                                         vmx_msr_bitmap_nested,
9308                                         msr, MSR_TYPE_R);
9309                 /* TPR is allowed */
9310                 nested_vmx_disable_intercept_for_msr(msr_bitmap,
9311                                 vmx_msr_bitmap_nested,
9312                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9313                                 MSR_TYPE_R | MSR_TYPE_W);
9314                 if (nested_cpu_has_vid(vmcs12)) {
9315                         /* EOI and self-IPI are allowed */
9316                         nested_vmx_disable_intercept_for_msr(
9317                                 msr_bitmap,
9318                                 vmx_msr_bitmap_nested,
9319                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9320                                 MSR_TYPE_W);
9321                         nested_vmx_disable_intercept_for_msr(
9322                                 msr_bitmap,
9323                                 vmx_msr_bitmap_nested,
9324                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9325                                 MSR_TYPE_W);
9326                 }
9327         } else {
9328                 /*
9329                  * Enable reading intercept of all the x2apic
9330                  * MSRs. We should not rely on vmcs12 to do any
9331                  * optimizations here, it may have been modified
9332                  * by L1.
9333                  */
9334                 for (msr = 0x800; msr <= 0x8ff; msr++)
9335                         __vmx_enable_intercept_for_msr(
9336                                 vmx_msr_bitmap_nested,
9337                                 msr,
9338                                 MSR_TYPE_R);
9339
9340                 __vmx_enable_intercept_for_msr(
9341                                 vmx_msr_bitmap_nested,
9342                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9343                                 MSR_TYPE_W);
9344                 __vmx_enable_intercept_for_msr(
9345                                 vmx_msr_bitmap_nested,
9346                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9347                                 MSR_TYPE_W);
9348                 __vmx_enable_intercept_for_msr(
9349                                 vmx_msr_bitmap_nested,
9350                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9351                                 MSR_TYPE_W);
9352         }
9353         kunmap(page);
9354         nested_release_page_clean(page);
9355
9356         return true;
9357 }
9358
9359 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9360                                            struct vmcs12 *vmcs12)
9361 {
9362         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9363             !nested_cpu_has_apic_reg_virt(vmcs12) &&
9364             !nested_cpu_has_vid(vmcs12) &&
9365             !nested_cpu_has_posted_intr(vmcs12))
9366                 return 0;
9367
9368         /*
9369          * If virtualize x2apic mode is enabled,
9370          * virtualize apic access must be disabled.
9371          */
9372         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9373             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9374                 return -EINVAL;
9375
9376         /*
9377          * If virtual interrupt delivery is enabled,
9378          * we must exit on external interrupts.
9379          */
9380         if (nested_cpu_has_vid(vmcs12) &&
9381            !nested_exit_on_intr(vcpu))
9382                 return -EINVAL;
9383
9384         /*
9385          * bits 15:8 should be zero in posted_intr_nv,
9386          * the descriptor address has been already checked
9387          * in nested_get_vmcs12_pages.
9388          */
9389         if (nested_cpu_has_posted_intr(vmcs12) &&
9390            (!nested_cpu_has_vid(vmcs12) ||
9391             !nested_exit_intr_ack_set(vcpu) ||
9392             vmcs12->posted_intr_nv & 0xff00))
9393                 return -EINVAL;
9394
9395         /* tpr shadow is needed by all apicv features. */
9396         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9397                 return -EINVAL;
9398
9399         return 0;
9400 }
9401
9402 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9403                                        unsigned long count_field,
9404                                        unsigned long addr_field)
9405 {
9406         int maxphyaddr;
9407         u64 count, addr;
9408
9409         if (vmcs12_read_any(vcpu, count_field, &count) ||
9410             vmcs12_read_any(vcpu, addr_field, &addr)) {
9411                 WARN_ON(1);
9412                 return -EINVAL;
9413         }
9414         if (count == 0)
9415                 return 0;
9416         maxphyaddr = cpuid_maxphyaddr(vcpu);
9417         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9418             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9419                 pr_warn_ratelimited(
9420                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9421                         addr_field, maxphyaddr, count, addr);
9422                 return -EINVAL;
9423         }
9424         return 0;
9425 }
9426
9427 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9428                                                 struct vmcs12 *vmcs12)
9429 {
9430         if (vmcs12->vm_exit_msr_load_count == 0 &&
9431             vmcs12->vm_exit_msr_store_count == 0 &&
9432             vmcs12->vm_entry_msr_load_count == 0)
9433                 return 0; /* Fast path */
9434         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9435                                         VM_EXIT_MSR_LOAD_ADDR) ||
9436             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9437                                         VM_EXIT_MSR_STORE_ADDR) ||
9438             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9439                                         VM_ENTRY_MSR_LOAD_ADDR))
9440                 return -EINVAL;
9441         return 0;
9442 }
9443
9444 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9445                                        struct vmx_msr_entry *e)
9446 {
9447         /* x2APIC MSR accesses are not allowed */
9448         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9449                 return -EINVAL;
9450         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9451             e->index == MSR_IA32_UCODE_REV)
9452                 return -EINVAL;
9453         if (e->reserved != 0)
9454                 return -EINVAL;
9455         return 0;
9456 }
9457
9458 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9459                                      struct vmx_msr_entry *e)
9460 {
9461         if (e->index == MSR_FS_BASE ||
9462             e->index == MSR_GS_BASE ||
9463             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9464             nested_vmx_msr_check_common(vcpu, e))
9465                 return -EINVAL;
9466         return 0;
9467 }
9468
9469 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9470                                       struct vmx_msr_entry *e)
9471 {
9472         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9473             nested_vmx_msr_check_common(vcpu, e))
9474                 return -EINVAL;
9475         return 0;
9476 }
9477
9478 /*
9479  * Load guest's/host's msr at nested entry/exit.
9480  * return 0 for success, entry index for failure.
9481  */
9482 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9483 {
9484         u32 i;
9485         struct vmx_msr_entry e;
9486         struct msr_data msr;
9487
9488         msr.host_initiated = false;
9489         for (i = 0; i < count; i++) {
9490                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9491                                         &e, sizeof(e))) {
9492                         pr_warn_ratelimited(
9493                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9494                                 __func__, i, gpa + i * sizeof(e));
9495                         goto fail;
9496                 }
9497                 if (nested_vmx_load_msr_check(vcpu, &e)) {
9498                         pr_warn_ratelimited(
9499                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9500                                 __func__, i, e.index, e.reserved);
9501                         goto fail;
9502                 }
9503                 msr.index = e.index;
9504                 msr.data = e.value;
9505                 if (kvm_set_msr(vcpu, &msr)) {
9506                         pr_warn_ratelimited(
9507                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9508                                 __func__, i, e.index, e.value);
9509                         goto fail;
9510                 }
9511         }
9512         return 0;
9513 fail:
9514         return i + 1;
9515 }
9516
9517 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9518 {
9519         u32 i;
9520         struct vmx_msr_entry e;
9521
9522         for (i = 0; i < count; i++) {
9523                 struct msr_data msr_info;
9524                 if (kvm_vcpu_read_guest(vcpu,
9525                                         gpa + i * sizeof(e),
9526                                         &e, 2 * sizeof(u32))) {
9527                         pr_warn_ratelimited(
9528                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9529                                 __func__, i, gpa + i * sizeof(e));
9530                         return -EINVAL;
9531                 }
9532                 if (nested_vmx_store_msr_check(vcpu, &e)) {
9533                         pr_warn_ratelimited(
9534                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9535                                 __func__, i, e.index, e.reserved);
9536                         return -EINVAL;
9537                 }
9538                 msr_info.host_initiated = false;
9539                 msr_info.index = e.index;
9540                 if (kvm_get_msr(vcpu, &msr_info)) {
9541                         pr_warn_ratelimited(
9542                                 "%s cannot read MSR (%u, 0x%x)\n",
9543                                 __func__, i, e.index);
9544                         return -EINVAL;
9545                 }
9546                 if (kvm_vcpu_write_guest(vcpu,
9547                                          gpa + i * sizeof(e) +
9548                                              offsetof(struct vmx_msr_entry, value),
9549                                          &msr_info.data, sizeof(msr_info.data))) {
9550                         pr_warn_ratelimited(
9551                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9552                                 __func__, i, e.index, msr_info.data);
9553                         return -EINVAL;
9554                 }
9555         }
9556         return 0;
9557 }
9558
9559 /*
9560  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9561  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9562  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9563  * guest in a way that will both be appropriate to L1's requests, and our
9564  * needs. In addition to modifying the active vmcs (which is vmcs02), this
9565  * function also has additional necessary side-effects, like setting various
9566  * vcpu->arch fields.
9567  */
9568 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9569 {
9570         struct vcpu_vmx *vmx = to_vmx(vcpu);
9571         u32 exec_control;
9572
9573         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9574         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9575         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9576         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9577         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9578         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9579         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9580         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9581         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9582         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9583         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9584         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9585         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9586         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9587         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9588         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9589         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9590         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9591         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9592         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9593         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9594         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9595         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9596         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9597         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9598         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9599         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9600         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9601         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9602         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9603         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9604         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9605         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9606         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9607         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9608         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9609
9610         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9611                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9612                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9613         } else {
9614                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9615                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9616         }
9617         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9618                 vmcs12->vm_entry_intr_info_field);
9619         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9620                 vmcs12->vm_entry_exception_error_code);
9621         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9622                 vmcs12->vm_entry_instruction_len);
9623         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9624                 vmcs12->guest_interruptibility_info);
9625         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
9626         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
9627         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9628                 vmcs12->guest_pending_dbg_exceptions);
9629         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9630         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9631
9632         if (nested_cpu_has_xsaves(vmcs12))
9633                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
9634         vmcs_write64(VMCS_LINK_POINTER, -1ull);
9635
9636         exec_control = vmcs12->pin_based_vm_exec_control;
9637         exec_control |= vmcs_config.pin_based_exec_ctrl;
9638         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9639
9640         if (nested_cpu_has_posted_intr(vmcs12)) {
9641                 /*
9642                  * Note that we use L0's vector here and in
9643                  * vmx_deliver_nested_posted_interrupt.
9644                  */
9645                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9646                 vmx->nested.pi_pending = false;
9647                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9648                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9649                         page_to_phys(vmx->nested.pi_desc_page) +
9650                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9651                         (PAGE_SIZE - 1)));
9652         } else
9653                 exec_control &= ~PIN_BASED_POSTED_INTR;
9654
9655         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
9656
9657         vmx->nested.preemption_timer_expired = false;
9658         if (nested_cpu_has_preemption_timer(vmcs12))
9659                 vmx_start_preemption_timer(vcpu);
9660
9661         /*
9662          * Whether page-faults are trapped is determined by a combination of
9663          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9664          * If enable_ept, L0 doesn't care about page faults and we should
9665          * set all of these to L1's desires. However, if !enable_ept, L0 does
9666          * care about (at least some) page faults, and because it is not easy
9667          * (if at all possible?) to merge L0 and L1's desires, we simply ask
9668          * to exit on each and every L2 page fault. This is done by setting
9669          * MASK=MATCH=0 and (see below) EB.PF=1.
9670          * Note that below we don't need special code to set EB.PF beyond the
9671          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9672          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9673          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9674          *
9675          * A problem with this approach (when !enable_ept) is that L1 may be
9676          * injected with more page faults than it asked for. This could have
9677          * caused problems, but in practice existing hypervisors don't care.
9678          * To fix this, we will need to emulate the PFEC checking (on the L1
9679          * page tables), using walk_addr(), when injecting PFs to L1.
9680          */
9681         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9682                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9683         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9684                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9685
9686         if (cpu_has_secondary_exec_ctrls()) {
9687                 exec_control = vmx_secondary_exec_control(vmx);
9688
9689                 /* Take the following fields only from vmcs12 */
9690                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9691                                   SECONDARY_EXEC_RDTSCP |
9692                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
9693                                   SECONDARY_EXEC_APIC_REGISTER_VIRT |
9694                                   SECONDARY_EXEC_PCOMMIT);
9695                 if (nested_cpu_has(vmcs12,
9696                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9697                         exec_control |= vmcs12->secondary_vm_exec_control;
9698
9699                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
9700                         /*
9701                          * If translation failed, no matter: This feature asks
9702                          * to exit when accessing the given address, and if it
9703                          * can never be accessed, this feature won't do
9704                          * anything anyway.
9705                          */
9706                         if (!vmx->nested.apic_access_page)
9707                                 exec_control &=
9708                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9709                         else
9710                                 vmcs_write64(APIC_ACCESS_ADDR,
9711                                   page_to_phys(vmx->nested.apic_access_page));
9712                 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9713                             cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9714                         exec_control |=
9715                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9716                         kvm_vcpu_reload_apic_access_page(vcpu);
9717                 }
9718
9719                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9720                         vmcs_write64(EOI_EXIT_BITMAP0,
9721                                 vmcs12->eoi_exit_bitmap0);
9722                         vmcs_write64(EOI_EXIT_BITMAP1,
9723                                 vmcs12->eoi_exit_bitmap1);
9724                         vmcs_write64(EOI_EXIT_BITMAP2,
9725                                 vmcs12->eoi_exit_bitmap2);
9726                         vmcs_write64(EOI_EXIT_BITMAP3,
9727                                 vmcs12->eoi_exit_bitmap3);
9728                         vmcs_write16(GUEST_INTR_STATUS,
9729                                 vmcs12->guest_intr_status);
9730                 }
9731
9732                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9733         }
9734
9735
9736         /*
9737          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9738          * Some constant fields are set here by vmx_set_constant_host_state().
9739          * Other fields are different per CPU, and will be set later when
9740          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9741          */
9742         vmx_set_constant_host_state(vmx);
9743
9744         /*
9745          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9746          * entry, but only if the current (host) sp changed from the value
9747          * we wrote last (vmx->host_rsp). This cache is no longer relevant
9748          * if we switch vmcs, and rather than hold a separate cache per vmcs,
9749          * here we just force the write to happen on entry.
9750          */
9751         vmx->host_rsp = 0;
9752
9753         exec_control = vmx_exec_control(vmx); /* L0's desires */
9754         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9755         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9756         exec_control &= ~CPU_BASED_TPR_SHADOW;
9757         exec_control |= vmcs12->cpu_based_vm_exec_control;
9758
9759         if (exec_control & CPU_BASED_TPR_SHADOW) {
9760                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9761                                 page_to_phys(vmx->nested.virtual_apic_page));
9762                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9763         }
9764
9765         if (cpu_has_vmx_msr_bitmap() &&
9766             exec_control & CPU_BASED_USE_MSR_BITMAPS) {
9767                 nested_vmx_merge_msr_bitmap(vcpu, vmcs12);
9768                 /* MSR_BITMAP will be set by following vmx_set_efer. */
9769         } else
9770                 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9771
9772         /*
9773          * Merging of IO bitmap not currently supported.
9774          * Rather, exit every time.
9775          */
9776         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9777         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9778
9779         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9780
9781         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9782          * bitwise-or of what L1 wants to trap for L2, and what we want to
9783          * trap. Note that CR0.TS also needs updating - we do this later.
9784          */
9785         update_exception_bitmap(vcpu);
9786         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9787         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9788
9789         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9790          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9791          * bits are further modified by vmx_set_efer() below.
9792          */
9793         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
9794
9795         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9796          * emulated by vmx_set_efer(), below.
9797          */
9798         vm_entry_controls_init(vmx,
9799                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9800                         ~VM_ENTRY_IA32E_MODE) |
9801                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9802
9803         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
9804                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
9805                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9806         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
9807                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9808
9809
9810         set_cr4_guest_host_mask(vmx);
9811
9812         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9813                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9814
9815         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9816                 vmcs_write64(TSC_OFFSET,
9817                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9818         else
9819                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
9820
9821         if (enable_vpid) {
9822                 /*
9823                  * There is no direct mapping between vpid02 and vpid12, the
9824                  * vpid02 is per-vCPU for L0 and reused while the value of
9825                  * vpid12 is changed w/ one invvpid during nested vmentry.
9826                  * The vpid12 is allocated by L1 for L2, so it will not
9827                  * influence global bitmap(for vpid01 and vpid02 allocation)
9828                  * even if spawn a lot of nested vCPUs.
9829                  */
9830                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
9831                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
9832                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
9833                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
9834                                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
9835                         }
9836                 } else {
9837                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9838                         vmx_flush_tlb(vcpu);
9839                 }
9840
9841         }
9842
9843         if (nested_cpu_has_ept(vmcs12)) {
9844                 kvm_mmu_unload(vcpu);
9845                 nested_ept_init_mmu_context(vcpu);
9846         }
9847
9848         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9849                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
9850         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
9851                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9852         else
9853                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9854         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9855         vmx_set_efer(vcpu, vcpu->arch.efer);
9856
9857         /*
9858          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9859          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9860          * The CR0_READ_SHADOW is what L2 should have expected to read given
9861          * the specifications by L1; It's not enough to take
9862          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9863          * have more bits than L1 expected.
9864          */
9865         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9866         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9867
9868         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9869         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9870
9871         /* shadow page tables on either EPT or shadow page tables */
9872         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9873         kvm_mmu_reset_context(vcpu);
9874
9875         if (!enable_ept)
9876                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
9877
9878         /*
9879          * L1 may access the L2's PDPTR, so save them to construct vmcs12
9880          */
9881         if (enable_ept) {
9882                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
9883                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
9884                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
9885                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
9886         }
9887
9888         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
9889         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
9890 }
9891
9892 /*
9893  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9894  * for running an L2 nested guest.
9895  */
9896 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
9897 {
9898         struct vmcs12 *vmcs12;
9899         struct vcpu_vmx *vmx = to_vmx(vcpu);
9900         int cpu;
9901         struct loaded_vmcs *vmcs02;
9902         bool ia32e;
9903         u32 msr_entry_idx;
9904
9905         if (!nested_vmx_check_permission(vcpu) ||
9906             !nested_vmx_check_vmcs12(vcpu))
9907                 return 1;
9908
9909         skip_emulated_instruction(vcpu);
9910         vmcs12 = get_vmcs12(vcpu);
9911
9912         if (enable_shadow_vmcs)
9913                 copy_shadow_to_vmcs12(vmx);
9914
9915         /*
9916          * The nested entry process starts with enforcing various prerequisites
9917          * on vmcs12 as required by the Intel SDM, and act appropriately when
9918          * they fail: As the SDM explains, some conditions should cause the
9919          * instruction to fail, while others will cause the instruction to seem
9920          * to succeed, but return an EXIT_REASON_INVALID_STATE.
9921          * To speed up the normal (success) code path, we should avoid checking
9922          * for misconfigurations which will anyway be caught by the processor
9923          * when using the merged vmcs02.
9924          */
9925         if (vmcs12->launch_state == launch) {
9926                 nested_vmx_failValid(vcpu,
9927                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9928                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
9929                 return 1;
9930         }
9931
9932         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
9933             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
9934                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9935                 return 1;
9936         }
9937
9938         if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
9939                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9940                 return 1;
9941         }
9942
9943         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
9944                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9945                 return 1;
9946         }
9947
9948         if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
9949                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9950                 return 1;
9951         }
9952
9953         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
9954                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9955                 return 1;
9956         }
9957
9958         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
9959                                 vmx->nested.nested_vmx_true_procbased_ctls_low,
9960                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
9961             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
9962                                 vmx->nested.nested_vmx_secondary_ctls_low,
9963                                 vmx->nested.nested_vmx_secondary_ctls_high) ||
9964             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
9965                                 vmx->nested.nested_vmx_pinbased_ctls_low,
9966                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
9967             !vmx_control_verify(vmcs12->vm_exit_controls,
9968                                 vmx->nested.nested_vmx_true_exit_ctls_low,
9969                                 vmx->nested.nested_vmx_exit_ctls_high) ||
9970             !vmx_control_verify(vmcs12->vm_entry_controls,
9971                                 vmx->nested.nested_vmx_true_entry_ctls_low,
9972                                 vmx->nested.nested_vmx_entry_ctls_high))
9973         {
9974                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9975                 return 1;
9976         }
9977
9978         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
9979             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9980                 nested_vmx_failValid(vcpu,
9981                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
9982                 return 1;
9983         }
9984
9985         if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
9986             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9987                 nested_vmx_entry_failure(vcpu, vmcs12,
9988                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9989                 return 1;
9990         }
9991         if (vmcs12->vmcs_link_pointer != -1ull) {
9992                 nested_vmx_entry_failure(vcpu, vmcs12,
9993                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
9994                 return 1;
9995         }
9996
9997         /*
9998          * If the load IA32_EFER VM-entry control is 1, the following checks
9999          * are performed on the field for the IA32_EFER MSR:
10000          * - Bits reserved in the IA32_EFER MSR must be 0.
10001          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10002          *   the IA-32e mode guest VM-exit control. It must also be identical
10003          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10004          *   CR0.PG) is 1.
10005          */
10006         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
10007                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
10008                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
10009                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
10010                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
10011                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
10012                         nested_vmx_entry_failure(vcpu, vmcs12,
10013                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
10014                         return 1;
10015                 }
10016         }
10017
10018         /*
10019          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10020          * IA32_EFER MSR must be 0 in the field for that register. In addition,
10021          * the values of the LMA and LME bits in the field must each be that of
10022          * the host address-space size VM-exit control.
10023          */
10024         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
10025                 ia32e = (vmcs12->vm_exit_controls &
10026                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
10027                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
10028                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
10029                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
10030                         nested_vmx_entry_failure(vcpu, vmcs12,
10031                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
10032                         return 1;
10033                 }
10034         }
10035
10036         /*
10037          * We're finally done with prerequisite checking, and can start with
10038          * the nested entry.
10039          */
10040
10041         vmcs02 = nested_get_current_vmcs02(vmx);
10042         if (!vmcs02)
10043                 return -ENOMEM;
10044
10045         enter_guest_mode(vcpu);
10046
10047         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
10048
10049         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
10050                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10051
10052         cpu = get_cpu();
10053         vmx->loaded_vmcs = vmcs02;
10054         vmx_vcpu_put(vcpu);
10055         vmx_vcpu_load(vcpu, cpu);
10056         vcpu->cpu = cpu;
10057         put_cpu();
10058
10059         vmx_segment_cache_clear(vmx);
10060
10061         prepare_vmcs02(vcpu, vmcs12);
10062
10063         msr_entry_idx = nested_vmx_load_msr(vcpu,
10064                                             vmcs12->vm_entry_msr_load_addr,
10065                                             vmcs12->vm_entry_msr_load_count);
10066         if (msr_entry_idx) {
10067                 leave_guest_mode(vcpu);
10068                 vmx_load_vmcs01(vcpu);
10069                 nested_vmx_entry_failure(vcpu, vmcs12,
10070                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10071                 return 1;
10072         }
10073
10074         vmcs12->launch_state = 1;
10075
10076         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
10077                 return kvm_vcpu_halt(vcpu);
10078
10079         vmx->nested.nested_run_pending = 1;
10080
10081         /*
10082          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10083          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10084          * returned as far as L1 is concerned. It will only return (and set
10085          * the success flag) when L2 exits (see nested_vmx_vmexit()).
10086          */
10087         return 1;
10088 }
10089
10090 /*
10091  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10092  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10093  * This function returns the new value we should put in vmcs12.guest_cr0.
10094  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10095  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10096  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10097  *     didn't trap the bit, because if L1 did, so would L0).
10098  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10099  *     been modified by L2, and L1 knows it. So just leave the old value of
10100  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10101  *     isn't relevant, because if L0 traps this bit it can set it to anything.
10102  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10103  *     changed these bits, and therefore they need to be updated, but L0
10104  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10105  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10106  */
10107 static inline unsigned long
10108 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10109 {
10110         return
10111         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10112         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10113         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10114                         vcpu->arch.cr0_guest_owned_bits));
10115 }
10116
10117 static inline unsigned long
10118 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10119 {
10120         return
10121         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10122         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10123         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10124                         vcpu->arch.cr4_guest_owned_bits));
10125 }
10126
10127 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10128                                        struct vmcs12 *vmcs12)
10129 {
10130         u32 idt_vectoring;
10131         unsigned int nr;
10132
10133         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10134                 nr = vcpu->arch.exception.nr;
10135                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10136
10137                 if (kvm_exception_is_soft(nr)) {
10138                         vmcs12->vm_exit_instruction_len =
10139                                 vcpu->arch.event_exit_inst_len;
10140                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10141                 } else
10142                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10143
10144                 if (vcpu->arch.exception.has_error_code) {
10145                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10146                         vmcs12->idt_vectoring_error_code =
10147                                 vcpu->arch.exception.error_code;
10148                 }
10149
10150                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10151         } else if (vcpu->arch.nmi_injected) {
10152                 vmcs12->idt_vectoring_info_field =
10153                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10154         } else if (vcpu->arch.interrupt.pending) {
10155                 nr = vcpu->arch.interrupt.nr;
10156                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10157
10158                 if (vcpu->arch.interrupt.soft) {
10159                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
10160                         vmcs12->vm_entry_instruction_len =
10161                                 vcpu->arch.event_exit_inst_len;
10162                 } else
10163                         idt_vectoring |= INTR_TYPE_EXT_INTR;
10164
10165                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10166         }
10167 }
10168
10169 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10170 {
10171         struct vcpu_vmx *vmx = to_vmx(vcpu);
10172
10173         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10174             vmx->nested.preemption_timer_expired) {
10175                 if (vmx->nested.nested_run_pending)
10176                         return -EBUSY;
10177                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10178                 return 0;
10179         }
10180
10181         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10182                 if (vmx->nested.nested_run_pending ||
10183                     vcpu->arch.interrupt.pending)
10184                         return -EBUSY;
10185                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10186                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
10187                                   INTR_INFO_VALID_MASK, 0);
10188                 /*
10189                  * The NMI-triggered VM exit counts as injection:
10190                  * clear this one and block further NMIs.
10191                  */
10192                 vcpu->arch.nmi_pending = 0;
10193                 vmx_set_nmi_mask(vcpu, true);
10194                 return 0;
10195         }
10196
10197         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10198             nested_exit_on_intr(vcpu)) {
10199                 if (vmx->nested.nested_run_pending)
10200                         return -EBUSY;
10201                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10202                 return 0;
10203         }
10204
10205         return vmx_complete_nested_posted_interrupt(vcpu);
10206 }
10207
10208 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10209 {
10210         ktime_t remaining =
10211                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10212         u64 value;
10213
10214         if (ktime_to_ns(remaining) <= 0)
10215                 return 0;
10216
10217         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10218         do_div(value, 1000000);
10219         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10220 }
10221
10222 /*
10223  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10224  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10225  * and this function updates it to reflect the changes to the guest state while
10226  * L2 was running (and perhaps made some exits which were handled directly by L0
10227  * without going back to L1), and to reflect the exit reason.
10228  * Note that we do not have to copy here all VMCS fields, just those that
10229  * could have changed by the L2 guest or the exit - i.e., the guest-state and
10230  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10231  * which already writes to vmcs12 directly.
10232  */
10233 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10234                            u32 exit_reason, u32 exit_intr_info,
10235                            unsigned long exit_qualification)
10236 {
10237         /* update guest state fields: */
10238         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10239         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10240
10241         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10242         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10243         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10244
10245         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10246         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10247         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10248         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10249         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10250         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10251         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10252         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10253         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10254         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10255         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10256         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10257         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10258         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10259         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10260         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10261         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10262         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10263         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10264         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10265         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10266         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10267         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10268         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10269         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10270         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10271         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10272         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10273         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10274         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10275         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10276         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10277         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10278         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10279         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10280         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10281
10282         vmcs12->guest_interruptibility_info =
10283                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10284         vmcs12->guest_pending_dbg_exceptions =
10285                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10286         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10287                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10288         else
10289                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10290
10291         if (nested_cpu_has_preemption_timer(vmcs12)) {
10292                 if (vmcs12->vm_exit_controls &
10293                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10294                         vmcs12->vmx_preemption_timer_value =
10295                                 vmx_get_preemption_timer_value(vcpu);
10296                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10297         }
10298
10299         /*
10300          * In some cases (usually, nested EPT), L2 is allowed to change its
10301          * own CR3 without exiting. If it has changed it, we must keep it.
10302          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10303          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10304          *
10305          * Additionally, restore L2's PDPTR to vmcs12.
10306          */
10307         if (enable_ept) {
10308                 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
10309                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10310                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10311                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10312                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10313         }
10314
10315         if (nested_cpu_has_vid(vmcs12))
10316                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10317
10318         vmcs12->vm_entry_controls =
10319                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10320                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10321
10322         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10323                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10324                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10325         }
10326
10327         /* TODO: These cannot have changed unless we have MSR bitmaps and
10328          * the relevant bit asks not to trap the change */
10329         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10330                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10331         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10332                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10333         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10334         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10335         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10336         if (kvm_mpx_supported())
10337                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10338         if (nested_cpu_has_xsaves(vmcs12))
10339                 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
10340
10341         /* update exit information fields: */
10342
10343         vmcs12->vm_exit_reason = exit_reason;
10344         vmcs12->exit_qualification = exit_qualification;
10345
10346         vmcs12->vm_exit_intr_info = exit_intr_info;
10347         if ((vmcs12->vm_exit_intr_info &
10348              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10349             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10350                 vmcs12->vm_exit_intr_error_code =
10351                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10352         vmcs12->idt_vectoring_info_field = 0;
10353         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10354         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10355
10356         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10357                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10358                  * instead of reading the real value. */
10359                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10360
10361                 /*
10362                  * Transfer the event that L0 or L1 may wanted to inject into
10363                  * L2 to IDT_VECTORING_INFO_FIELD.
10364                  */
10365                 vmcs12_save_pending_event(vcpu, vmcs12);
10366         }
10367
10368         /*
10369          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10370          * preserved above and would only end up incorrectly in L1.
10371          */
10372         vcpu->arch.nmi_injected = false;
10373         kvm_clear_exception_queue(vcpu);
10374         kvm_clear_interrupt_queue(vcpu);
10375 }
10376
10377 /*
10378  * A part of what we need to when the nested L2 guest exits and we want to
10379  * run its L1 parent, is to reset L1's guest state to the host state specified
10380  * in vmcs12.
10381  * This function is to be called not only on normal nested exit, but also on
10382  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10383  * Failures During or After Loading Guest State").
10384  * This function should be called when the active VMCS is L1's (vmcs01).
10385  */
10386 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10387                                    struct vmcs12 *vmcs12)
10388 {
10389         struct kvm_segment seg;
10390
10391         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10392                 vcpu->arch.efer = vmcs12->host_ia32_efer;
10393         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10394                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10395         else
10396                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10397         vmx_set_efer(vcpu, vcpu->arch.efer);
10398
10399         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10400         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10401         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10402         /*
10403          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10404          * actually changed, because it depends on the current state of
10405          * fpu_active (which may have changed).
10406          * Note that vmx_set_cr0 refers to efer set above.
10407          */
10408         vmx_set_cr0(vcpu, vmcs12->host_cr0);
10409         /*
10410          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10411          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10412          * but we also need to update cr0_guest_host_mask and exception_bitmap.
10413          */
10414         update_exception_bitmap(vcpu);
10415         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
10416         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10417
10418         /*
10419          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10420          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10421          */
10422         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10423         kvm_set_cr4(vcpu, vmcs12->host_cr4);
10424
10425         nested_ept_uninit_mmu_context(vcpu);
10426
10427         kvm_set_cr3(vcpu, vmcs12->host_cr3);
10428         kvm_mmu_reset_context(vcpu);
10429
10430         if (!enable_ept)
10431                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10432
10433         if (enable_vpid) {
10434                 /*
10435                  * Trivially support vpid by letting L2s share their parent
10436                  * L1's vpid. TODO: move to a more elaborate solution, giving
10437                  * each L2 its own vpid and exposing the vpid feature to L1.
10438                  */
10439                 vmx_flush_tlb(vcpu);
10440         }
10441
10442
10443         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10444         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10445         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10446         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10447         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10448
10449         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
10450         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10451                 vmcs_write64(GUEST_BNDCFGS, 0);
10452
10453         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10454                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10455                 vcpu->arch.pat = vmcs12->host_ia32_pat;
10456         }
10457         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10458                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10459                         vmcs12->host_ia32_perf_global_ctrl);
10460
10461         /* Set L1 segment info according to Intel SDM
10462             27.5.2 Loading Host Segment and Descriptor-Table Registers */
10463         seg = (struct kvm_segment) {
10464                 .base = 0,
10465                 .limit = 0xFFFFFFFF,
10466                 .selector = vmcs12->host_cs_selector,
10467                 .type = 11,
10468                 .present = 1,
10469                 .s = 1,
10470                 .g = 1
10471         };
10472         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10473                 seg.l = 1;
10474         else
10475                 seg.db = 1;
10476         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10477         seg = (struct kvm_segment) {
10478                 .base = 0,
10479                 .limit = 0xFFFFFFFF,
10480                 .type = 3,
10481                 .present = 1,
10482                 .s = 1,
10483                 .db = 1,
10484                 .g = 1
10485         };
10486         seg.selector = vmcs12->host_ds_selector;
10487         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10488         seg.selector = vmcs12->host_es_selector;
10489         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10490         seg.selector = vmcs12->host_ss_selector;
10491         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10492         seg.selector = vmcs12->host_fs_selector;
10493         seg.base = vmcs12->host_fs_base;
10494         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10495         seg.selector = vmcs12->host_gs_selector;
10496         seg.base = vmcs12->host_gs_base;
10497         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10498         seg = (struct kvm_segment) {
10499                 .base = vmcs12->host_tr_base,
10500                 .limit = 0x67,
10501                 .selector = vmcs12->host_tr_selector,
10502                 .type = 11,
10503                 .present = 1
10504         };
10505         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10506
10507         kvm_set_dr(vcpu, 7, 0x400);
10508         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
10509
10510         if (cpu_has_vmx_msr_bitmap())
10511                 vmx_set_msr_bitmap(vcpu);
10512
10513         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10514                                 vmcs12->vm_exit_msr_load_count))
10515                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
10516 }
10517
10518 /*
10519  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10520  * and modify vmcs12 to make it see what it would expect to see there if
10521  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10522  */
10523 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10524                               u32 exit_intr_info,
10525                               unsigned long exit_qualification)
10526 {
10527         struct vcpu_vmx *vmx = to_vmx(vcpu);
10528         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10529
10530         /* trying to cancel vmlaunch/vmresume is a bug */
10531         WARN_ON_ONCE(vmx->nested.nested_run_pending);
10532
10533         leave_guest_mode(vcpu);
10534         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10535                        exit_qualification);
10536
10537         if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10538                                  vmcs12->vm_exit_msr_store_count))
10539                 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10540
10541         vmx_load_vmcs01(vcpu);
10542
10543         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10544             && nested_exit_intr_ack_set(vcpu)) {
10545                 int irq = kvm_cpu_get_interrupt(vcpu);
10546                 WARN_ON(irq < 0);
10547                 vmcs12->vm_exit_intr_info = irq |
10548                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10549         }
10550
10551         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10552                                        vmcs12->exit_qualification,
10553                                        vmcs12->idt_vectoring_info_field,
10554                                        vmcs12->vm_exit_intr_info,
10555                                        vmcs12->vm_exit_intr_error_code,
10556                                        KVM_ISA_VMX);
10557
10558         vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
10559         vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
10560         vmx_segment_cache_clear(vmx);
10561
10562         /* if no vmcs02 cache requested, remove the one we used */
10563         if (VMCS02_POOL_SIZE == 0)
10564                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10565
10566         load_vmcs12_host_state(vcpu, vmcs12);
10567
10568         /* Update TSC_OFFSET if TSC was changed while L2 ran */
10569         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10570
10571         /* This is needed for same reason as it was needed in prepare_vmcs02 */
10572         vmx->host_rsp = 0;
10573
10574         /* Unpin physical memory we referred to in vmcs02 */
10575         if (vmx->nested.apic_access_page) {
10576                 nested_release_page(vmx->nested.apic_access_page);
10577                 vmx->nested.apic_access_page = NULL;
10578         }
10579         if (vmx->nested.virtual_apic_page) {
10580                 nested_release_page(vmx->nested.virtual_apic_page);
10581                 vmx->nested.virtual_apic_page = NULL;
10582         }
10583         if (vmx->nested.pi_desc_page) {
10584                 kunmap(vmx->nested.pi_desc_page);
10585                 nested_release_page(vmx->nested.pi_desc_page);
10586                 vmx->nested.pi_desc_page = NULL;
10587                 vmx->nested.pi_desc = NULL;
10588         }
10589
10590         /*
10591          * We are now running in L2, mmu_notifier will force to reload the
10592          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10593          */
10594         kvm_vcpu_reload_apic_access_page(vcpu);
10595
10596         /*
10597          * Exiting from L2 to L1, we're now back to L1 which thinks it just
10598          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10599          * success or failure flag accordingly.
10600          */
10601         if (unlikely(vmx->fail)) {
10602                 vmx->fail = 0;
10603                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10604         } else
10605                 nested_vmx_succeed(vcpu);
10606         if (enable_shadow_vmcs)
10607                 vmx->nested.sync_shadow_vmcs = true;
10608
10609         /* in case we halted in L2 */
10610         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10611 }
10612
10613 /*
10614  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10615  */
10616 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10617 {
10618         if (is_guest_mode(vcpu))
10619                 nested_vmx_vmexit(vcpu, -1, 0, 0);
10620         free_nested(to_vmx(vcpu));
10621 }
10622
10623 /*
10624  * L1's failure to enter L2 is a subset of a normal exit, as explained in
10625  * 23.7 "VM-entry failures during or after loading guest state" (this also
10626  * lists the acceptable exit-reason and exit-qualification parameters).
10627  * It should only be called before L2 actually succeeded to run, and when
10628  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10629  */
10630 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10631                         struct vmcs12 *vmcs12,
10632                         u32 reason, unsigned long qualification)
10633 {
10634         load_vmcs12_host_state(vcpu, vmcs12);
10635         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10636         vmcs12->exit_qualification = qualification;
10637         nested_vmx_succeed(vcpu);
10638         if (enable_shadow_vmcs)
10639                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
10640 }
10641
10642 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10643                                struct x86_instruction_info *info,
10644                                enum x86_intercept_stage stage)
10645 {
10646         return X86EMUL_CONTINUE;
10647 }
10648
10649 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
10650 {
10651         if (ple_gap)
10652                 shrink_ple_window(vcpu);
10653 }
10654
10655 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10656                                      struct kvm_memory_slot *slot)
10657 {
10658         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10659         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10660 }
10661
10662 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10663                                        struct kvm_memory_slot *slot)
10664 {
10665         kvm_mmu_slot_set_dirty(kvm, slot);
10666 }
10667
10668 static void vmx_flush_log_dirty(struct kvm *kvm)
10669 {
10670         kvm_flush_pml_buffers(kvm);
10671 }
10672
10673 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10674                                            struct kvm_memory_slot *memslot,
10675                                            gfn_t offset, unsigned long mask)
10676 {
10677         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10678 }
10679
10680 /*
10681  * This routine does the following things for vCPU which is going
10682  * to be blocked if VT-d PI is enabled.
10683  * - Store the vCPU to the wakeup list, so when interrupts happen
10684  *   we can find the right vCPU to wake up.
10685  * - Change the Posted-interrupt descriptor as below:
10686  *      'NDST' <-- vcpu->pre_pcpu
10687  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
10688  * - If 'ON' is set during this process, which means at least one
10689  *   interrupt is posted for this vCPU, we cannot block it, in
10690  *   this case, return 1, otherwise, return 0.
10691  *
10692  */
10693 static int vmx_pre_block(struct kvm_vcpu *vcpu)
10694 {
10695         unsigned long flags;
10696         unsigned int dest;
10697         struct pi_desc old, new;
10698         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10699
10700         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10701                 !irq_remapping_cap(IRQ_POSTING_CAP))
10702                 return 0;
10703
10704         vcpu->pre_pcpu = vcpu->cpu;
10705         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10706                           vcpu->pre_pcpu), flags);
10707         list_add_tail(&vcpu->blocked_vcpu_list,
10708                       &per_cpu(blocked_vcpu_on_cpu,
10709                       vcpu->pre_pcpu));
10710         spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
10711                                vcpu->pre_pcpu), flags);
10712
10713         do {
10714                 old.control = new.control = pi_desc->control;
10715
10716                 /*
10717                  * We should not block the vCPU if
10718                  * an interrupt is posted for it.
10719                  */
10720                 if (pi_test_on(pi_desc) == 1) {
10721                         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10722                                           vcpu->pre_pcpu), flags);
10723                         list_del(&vcpu->blocked_vcpu_list);
10724                         spin_unlock_irqrestore(
10725                                         &per_cpu(blocked_vcpu_on_cpu_lock,
10726                                         vcpu->pre_pcpu), flags);
10727                         vcpu->pre_pcpu = -1;
10728
10729                         return 1;
10730                 }
10731
10732                 WARN((pi_desc->sn == 1),
10733                      "Warning: SN field of posted-interrupts "
10734                      "is set before blocking\n");
10735
10736                 /*
10737                  * Since vCPU can be preempted during this process,
10738                  * vcpu->cpu could be different with pre_pcpu, we
10739                  * need to set pre_pcpu as the destination of wakeup
10740                  * notification event, then we can find the right vCPU
10741                  * to wakeup in wakeup handler if interrupts happen
10742                  * when the vCPU is in blocked state.
10743                  */
10744                 dest = cpu_physical_id(vcpu->pre_pcpu);
10745
10746                 if (x2apic_enabled())
10747                         new.ndst = dest;
10748                 else
10749                         new.ndst = (dest << 8) & 0xFF00;
10750
10751                 /* set 'NV' to 'wakeup vector' */
10752                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
10753         } while (cmpxchg(&pi_desc->control, old.control,
10754                         new.control) != old.control);
10755
10756         return 0;
10757 }
10758
10759 static void vmx_post_block(struct kvm_vcpu *vcpu)
10760 {
10761         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10762         struct pi_desc old, new;
10763         unsigned int dest;
10764         unsigned long flags;
10765
10766         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10767                 !irq_remapping_cap(IRQ_POSTING_CAP))
10768                 return;
10769
10770         do {
10771                 old.control = new.control = pi_desc->control;
10772
10773                 dest = cpu_physical_id(vcpu->cpu);
10774
10775                 if (x2apic_enabled())
10776                         new.ndst = dest;
10777                 else
10778                         new.ndst = (dest << 8) & 0xFF00;
10779
10780                 /* Allow posting non-urgent interrupts */
10781                 new.sn = 0;
10782
10783                 /* set 'NV' to 'notification vector' */
10784                 new.nv = POSTED_INTR_VECTOR;
10785         } while (cmpxchg(&pi_desc->control, old.control,
10786                         new.control) != old.control);
10787
10788         if(vcpu->pre_pcpu != -1) {
10789                 spin_lock_irqsave(
10790                         &per_cpu(blocked_vcpu_on_cpu_lock,
10791                         vcpu->pre_pcpu), flags);
10792                 list_del(&vcpu->blocked_vcpu_list);
10793                 spin_unlock_irqrestore(
10794                         &per_cpu(blocked_vcpu_on_cpu_lock,
10795                         vcpu->pre_pcpu), flags);
10796                 vcpu->pre_pcpu = -1;
10797         }
10798 }
10799
10800 /*
10801  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
10802  *
10803  * @kvm: kvm
10804  * @host_irq: host irq of the interrupt
10805  * @guest_irq: gsi of the interrupt
10806  * @set: set or unset PI
10807  * returns 0 on success, < 0 on failure
10808  */
10809 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
10810                               uint32_t guest_irq, bool set)
10811 {
10812         struct kvm_kernel_irq_routing_entry *e;
10813         struct kvm_irq_routing_table *irq_rt;
10814         struct kvm_lapic_irq irq;
10815         struct kvm_vcpu *vcpu;
10816         struct vcpu_data vcpu_info;
10817         int idx, ret = -EINVAL;
10818
10819         if (!kvm_arch_has_assigned_device(kvm) ||
10820                 !irq_remapping_cap(IRQ_POSTING_CAP))
10821                 return 0;
10822
10823         idx = srcu_read_lock(&kvm->irq_srcu);
10824         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
10825         BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
10826
10827         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
10828                 if (e->type != KVM_IRQ_ROUTING_MSI)
10829                         continue;
10830                 /*
10831                  * VT-d PI cannot support posting multicast/broadcast
10832                  * interrupts to a vCPU, we still use interrupt remapping
10833                  * for these kind of interrupts.
10834                  *
10835                  * For lowest-priority interrupts, we only support
10836                  * those with single CPU as the destination, e.g. user
10837                  * configures the interrupts via /proc/irq or uses
10838                  * irqbalance to make the interrupts single-CPU.
10839                  *
10840                  * We will support full lowest-priority interrupt later.
10841                  */
10842
10843                 kvm_set_msi_irq(e, &irq);
10844                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
10845                         /*
10846                          * Make sure the IRTE is in remapped mode if
10847                          * we don't handle it in posted mode.
10848                          */
10849                         ret = irq_set_vcpu_affinity(host_irq, NULL);
10850                         if (ret < 0) {
10851                                 printk(KERN_INFO
10852                                    "failed to back to remapped mode, irq: %u\n",
10853                                    host_irq);
10854                                 goto out;
10855                         }
10856
10857                         continue;
10858                 }
10859
10860                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
10861                 vcpu_info.vector = irq.vector;
10862
10863                 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
10864                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
10865
10866                 if (set)
10867                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
10868                 else {
10869                         /* suppress notification event before unposting */
10870                         pi_set_sn(vcpu_to_pi_desc(vcpu));
10871                         ret = irq_set_vcpu_affinity(host_irq, NULL);
10872                         pi_clear_sn(vcpu_to_pi_desc(vcpu));
10873                 }
10874
10875                 if (ret < 0) {
10876                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
10877                                         __func__);
10878                         goto out;
10879                 }
10880         }
10881
10882         ret = 0;
10883 out:
10884         srcu_read_unlock(&kvm->irq_srcu, idx);
10885         return ret;
10886 }
10887
10888 static struct kvm_x86_ops vmx_x86_ops = {
10889         .cpu_has_kvm_support = cpu_has_kvm_support,
10890         .disabled_by_bios = vmx_disabled_by_bios,
10891         .hardware_setup = hardware_setup,
10892         .hardware_unsetup = hardware_unsetup,
10893         .check_processor_compatibility = vmx_check_processor_compat,
10894         .hardware_enable = hardware_enable,
10895         .hardware_disable = hardware_disable,
10896         .cpu_has_accelerated_tpr = report_flexpriority,
10897         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
10898
10899         .vcpu_create = vmx_create_vcpu,
10900         .vcpu_free = vmx_free_vcpu,
10901         .vcpu_reset = vmx_vcpu_reset,
10902
10903         .prepare_guest_switch = vmx_save_host_state,
10904         .vcpu_load = vmx_vcpu_load,
10905         .vcpu_put = vmx_vcpu_put,
10906
10907         .update_bp_intercept = update_exception_bitmap,
10908         .get_msr = vmx_get_msr,
10909         .set_msr = vmx_set_msr,
10910         .get_segment_base = vmx_get_segment_base,
10911         .get_segment = vmx_get_segment,
10912         .set_segment = vmx_set_segment,
10913         .get_cpl = vmx_get_cpl,
10914         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
10915         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
10916         .decache_cr3 = vmx_decache_cr3,
10917         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
10918         .set_cr0 = vmx_set_cr0,
10919         .set_cr3 = vmx_set_cr3,
10920         .set_cr4 = vmx_set_cr4,
10921         .set_efer = vmx_set_efer,
10922         .get_idt = vmx_get_idt,
10923         .set_idt = vmx_set_idt,
10924         .get_gdt = vmx_get_gdt,
10925         .set_gdt = vmx_set_gdt,
10926         .get_dr6 = vmx_get_dr6,
10927         .set_dr6 = vmx_set_dr6,
10928         .set_dr7 = vmx_set_dr7,
10929         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
10930         .cache_reg = vmx_cache_reg,
10931         .get_rflags = vmx_get_rflags,
10932         .set_rflags = vmx_set_rflags,
10933
10934         .get_pkru = vmx_get_pkru,
10935
10936         .fpu_activate = vmx_fpu_activate,
10937         .fpu_deactivate = vmx_fpu_deactivate,
10938
10939         .tlb_flush = vmx_flush_tlb,
10940
10941         .run = vmx_vcpu_run,
10942         .handle_exit = vmx_handle_exit,
10943         .skip_emulated_instruction = skip_emulated_instruction,
10944         .set_interrupt_shadow = vmx_set_interrupt_shadow,
10945         .get_interrupt_shadow = vmx_get_interrupt_shadow,
10946         .patch_hypercall = vmx_patch_hypercall,
10947         .set_irq = vmx_inject_irq,
10948         .set_nmi = vmx_inject_nmi,
10949         .queue_exception = vmx_queue_exception,
10950         .cancel_injection = vmx_cancel_injection,
10951         .interrupt_allowed = vmx_interrupt_allowed,
10952         .nmi_allowed = vmx_nmi_allowed,
10953         .get_nmi_mask = vmx_get_nmi_mask,
10954         .set_nmi_mask = vmx_set_nmi_mask,
10955         .enable_nmi_window = enable_nmi_window,
10956         .enable_irq_window = enable_irq_window,
10957         .update_cr8_intercept = update_cr8_intercept,
10958         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
10959         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
10960         .get_enable_apicv = vmx_get_enable_apicv,
10961         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
10962         .load_eoi_exitmap = vmx_load_eoi_exitmap,
10963         .hwapic_irr_update = vmx_hwapic_irr_update,
10964         .hwapic_isr_update = vmx_hwapic_isr_update,
10965         .sync_pir_to_irr = vmx_sync_pir_to_irr,
10966         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
10967
10968         .set_tss_addr = vmx_set_tss_addr,
10969         .get_tdp_level = get_ept_level,
10970         .get_mt_mask = vmx_get_mt_mask,
10971
10972         .get_exit_info = vmx_get_exit_info,
10973
10974         .get_lpage_level = vmx_get_lpage_level,
10975
10976         .cpuid_update = vmx_cpuid_update,
10977
10978         .rdtscp_supported = vmx_rdtscp_supported,
10979         .invpcid_supported = vmx_invpcid_supported,
10980
10981         .set_supported_cpuid = vmx_set_supported_cpuid,
10982
10983         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
10984
10985         .read_tsc_offset = vmx_read_tsc_offset,
10986         .write_tsc_offset = vmx_write_tsc_offset,
10987         .adjust_tsc_offset_guest = vmx_adjust_tsc_offset_guest,
10988         .read_l1_tsc = vmx_read_l1_tsc,
10989
10990         .set_tdp_cr3 = vmx_set_cr3,
10991
10992         .check_intercept = vmx_check_intercept,
10993         .handle_external_intr = vmx_handle_external_intr,
10994         .mpx_supported = vmx_mpx_supported,
10995         .xsaves_supported = vmx_xsaves_supported,
10996
10997         .check_nested_events = vmx_check_nested_events,
10998
10999         .sched_in = vmx_sched_in,
11000
11001         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
11002         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
11003         .flush_log_dirty = vmx_flush_log_dirty,
11004         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
11005
11006         .pre_block = vmx_pre_block,
11007         .post_block = vmx_post_block,
11008
11009         .pmu_ops = &intel_pmu_ops,
11010
11011         .update_pi_irte = vmx_update_pi_irte,
11012 };
11013
11014 static int __init vmx_init(void)
11015 {
11016         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
11017                      __alignof__(struct vcpu_vmx), THIS_MODULE);
11018         if (r)
11019                 return r;
11020
11021 #ifdef CONFIG_KEXEC_CORE
11022         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
11023                            crash_vmclear_local_loaded_vmcss);
11024 #endif
11025
11026         return 0;
11027 }
11028
11029 static void __exit vmx_exit(void)
11030 {
11031 #ifdef CONFIG_KEXEC_CORE
11032         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
11033         synchronize_rcu();
11034 #endif
11035
11036         kvm_exit();
11037 }
11038
11039 module_init(vmx_init)
11040 module_exit(vmx_exit)