arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22 #include "lapic.h"
  23
  24 #include <linux/kvm_host.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/mod_devicetable.h>
  32 #include <linux/trace_events.h>
  33 #include <linux/slab.h>
  34 #include <linux/tboot.h>
  35 #include <linux/hrtimer.h>
  36 #include "kvm_cache_regs.h"
  37 #include "x86.h"
  38
  39 #include <asm/cpu.h>
  40 #include <asm/io.h>
  41 #include <asm/desc.h>
  42 #include <asm/vmx.h>
  43 #include <asm/virtext.h>
  44 #include <asm/mce.h>
  45 #include <asm/fpu/internal.h>
  46 #include <asm/perf_event.h>
  47 #include <asm/debugreg.h>
  48 #include <asm/kexec.h>
  49 #include <asm/apic.h>
  50 #include <asm/irq_remapping.h>
  51
  52 #include "trace.h"
  53 #include "pmu.h"
  54
  55 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  56 #define __ex_clear(x, reg) \
  57         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  58
  59 MODULE_AUTHOR("Qumranet");
  60 MODULE_LICENSE("GPL");
  61
  62 static const struct x86_cpu_id vmx_cpu_id[] = {
  63         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  64         {}
  65 };
  66 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  67
  68 static bool __read_mostly enable_vpid = 1;
  69 module_param_named(vpid, enable_vpid, bool, 0444);
  70
  71 static bool __read_mostly flexpriority_enabled = 1;
  72 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  73
  74 static bool __read_mostly enable_ept = 1;
  75 module_param_named(ept, enable_ept, bool, S_IRUGO);
  76
  77 static bool __read_mostly enable_unrestricted_guest = 1;
  78 module_param_named(unrestricted_guest,
  79                         enable_unrestricted_guest, bool, S_IRUGO);
  80
  81 static bool __read_mostly enable_ept_ad_bits = 1;
  82 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  83
  84 static bool __read_mostly emulate_invalid_guest_state = true;
  85 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  86
  87 static bool __read_mostly vmm_exclusive = 1;
  88 module_param(vmm_exclusive, bool, S_IRUGO);
  89
  90 static bool __read_mostly fasteoi = 1;
  91 module_param(fasteoi, bool, S_IRUGO);
  92
  93 static bool __read_mostly enable_apicv = 1;
  94 module_param(enable_apicv, bool, S_IRUGO);
  95
  96 static bool __read_mostly enable_shadow_vmcs = 1;
  97 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  98 /*
  99  * If nested=1, nested virtualization is supported, i.e., guests may use
 100  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 101  * use VMX instructions.
 102  */
 103 static bool __read_mostly nested = 0;
 104 module_param(nested, bool, S_IRUGO);
 105
 106 static u64 __read_mostly host_xss;
 107
 108 static bool __read_mostly enable_pml = 1;
 109 module_param_named(pml, enable_pml, bool, S_IRUGO);
 110
 111 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 112
 113 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 114 static int __read_mostly cpu_preemption_timer_multi;
 115 static bool __read_mostly enable_preemption_timer = 1;
 116 #ifdef CONFIG_X86_64
 117 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 118 #endif
 119
 120 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 121 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 122 #define KVM_VM_CR0_ALWAYS_ON                                            \
 123         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 124 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 125         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 126          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 127
 128 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 129 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 130
 131 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 132
 133 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 134
 135 /*
 136  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 137  * ple_gap:    upper bound on the amount of time between two successive
 138  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 139  *             According to test, this time is usually smaller than 128 cycles.
 140  * ple_window: upper bound on the amount of time a guest is allowed to execute
 141  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 142  *             less than 2^12 cycles
 143  * Time is measured based on a counter that runs at the same rate as the TSC,
 144  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 145  */
 146 #define KVM_VMX_DEFAULT_PLE_GAP           128
 147 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 148 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 149 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 150 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 151                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 152
 153 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 154 module_param(ple_gap, int, S_IRUGO);
 155
 156 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 157 module_param(ple_window, int, S_IRUGO);
 158
 159 /* Default doubles per-vcpu window every exit. */
 160 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 161 module_param(ple_window_grow, int, S_IRUGO);
 162
 163 /* Default resets per-vcpu window every exit to ple_window. */
 164 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 165 module_param(ple_window_shrink, int, S_IRUGO);
 166
 167 /* Default is to compute the maximum so we can never overflow. */
 168 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 169 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 170 module_param(ple_window_max, int, S_IRUGO);
 171
 172 extern const ulong vmx_return;
 173
 174 #define NR_AUTOLOAD_MSRS 8
 175 #define VMCS02_POOL_SIZE 1
 176
 177 struct vmcs {
 178         u32 revision_id;
 179         u32 abort;
 180         char data[0];
 181 };
 182
 183 /*
 184  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 185  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 186  * loaded on this CPU (so we can clear them if the CPU goes down).
 187  */
 188 struct loaded_vmcs {
 189         struct vmcs *vmcs;
 190         int cpu;
 191         int launched;
 192         struct list_head loaded_vmcss_on_cpu_link;
 193 };
 194
 195 struct shared_msr_entry {
 196         unsigned index;
 197         u64 data;
 198         u64 mask;
 199 };
 200
 201 /*
 202  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 203  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 204  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 205  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 206  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 207  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 208  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 209  * underlying hardware which will be used to run L2.
 210  * This structure is packed to ensure that its layout is identical across
 211  * machines (necessary for live migration).
 212  * If there are changes in this struct, VMCS12_REVISION must be changed.
 213  */
 214 typedef u64 natural_width;
 215 struct __packed vmcs12 {
 216         /* According to the Intel spec, a VMCS region must start with the
 217          * following two fields. Then follow implementation-specific data.
 218          */
 219         u32 revision_id;
 220         u32 abort;
 221
 222         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 223         u32 padding[7]; /* room for future expansion */
 224
 225         u64 io_bitmap_a;
 226         u64 io_bitmap_b;
 227         u64 msr_bitmap;
 228         u64 vm_exit_msr_store_addr;
 229         u64 vm_exit_msr_load_addr;
 230         u64 vm_entry_msr_load_addr;
 231         u64 tsc_offset;
 232         u64 virtual_apic_page_addr;
 233         u64 apic_access_addr;
 234         u64 posted_intr_desc_addr;
 235         u64 ept_pointer;
 236         u64 eoi_exit_bitmap0;
 237         u64 eoi_exit_bitmap1;
 238         u64 eoi_exit_bitmap2;
 239         u64 eoi_exit_bitmap3;
 240         u64 xss_exit_bitmap;
 241         u64 guest_physical_address;
 242         u64 vmcs_link_pointer;
 243         u64 guest_ia32_debugctl;
 244         u64 guest_ia32_pat;
 245         u64 guest_ia32_efer;
 246         u64 guest_ia32_perf_global_ctrl;
 247         u64 guest_pdptr0;
 248         u64 guest_pdptr1;
 249         u64 guest_pdptr2;
 250         u64 guest_pdptr3;
 251         u64 guest_bndcfgs;
 252         u64 host_ia32_pat;
 253         u64 host_ia32_efer;
 254         u64 host_ia32_perf_global_ctrl;
 255         u64 padding64[8]; /* room for future expansion */
 256         /*
 257          * To allow migration of L1 (complete with its L2 guests) between
 258          * machines of different natural widths (32 or 64 bit), we cannot have
 259          * unsigned long fields with no explict size. We use u64 (aliased
 260          * natural_width) instead. Luckily, x86 is little-endian.
 261          */
 262         natural_width cr0_guest_host_mask;
 263         natural_width cr4_guest_host_mask;
 264         natural_width cr0_read_shadow;
 265         natural_width cr4_read_shadow;
 266         natural_width cr3_target_value0;
 267         natural_width cr3_target_value1;
 268         natural_width cr3_target_value2;
 269         natural_width cr3_target_value3;
 270         natural_width exit_qualification;
 271         natural_width guest_linear_address;
 272         natural_width guest_cr0;
 273         natural_width guest_cr3;
 274         natural_width guest_cr4;
 275         natural_width guest_es_base;
 276         natural_width guest_cs_base;
 277         natural_width guest_ss_base;
 278         natural_width guest_ds_base;
 279         natural_width guest_fs_base;
 280         natural_width guest_gs_base;
 281         natural_width guest_ldtr_base;
 282         natural_width guest_tr_base;
 283         natural_width guest_gdtr_base;
 284         natural_width guest_idtr_base;
 285         natural_width guest_dr7;
 286         natural_width guest_rsp;
 287         natural_width guest_rip;
 288         natural_width guest_rflags;
 289         natural_width guest_pending_dbg_exceptions;
 290         natural_width guest_sysenter_esp;
 291         natural_width guest_sysenter_eip;
 292         natural_width host_cr0;
 293         natural_width host_cr3;
 294         natural_width host_cr4;
 295         natural_width host_fs_base;
 296         natural_width host_gs_base;
 297         natural_width host_tr_base;
 298         natural_width host_gdtr_base;
 299         natural_width host_idtr_base;
 300         natural_width host_ia32_sysenter_esp;
 301         natural_width host_ia32_sysenter_eip;
 302         natural_width host_rsp;
 303         natural_width host_rip;
 304         natural_width paddingl[8]; /* room for future expansion */
 305         u32 pin_based_vm_exec_control;
 306         u32 cpu_based_vm_exec_control;
 307         u32 exception_bitmap;
 308         u32 page_fault_error_code_mask;
 309         u32 page_fault_error_code_match;
 310         u32 cr3_target_count;
 311         u32 vm_exit_controls;
 312         u32 vm_exit_msr_store_count;
 313         u32 vm_exit_msr_load_count;
 314         u32 vm_entry_controls;
 315         u32 vm_entry_msr_load_count;
 316         u32 vm_entry_intr_info_field;
 317         u32 vm_entry_exception_error_code;
 318         u32 vm_entry_instruction_len;
 319         u32 tpr_threshold;
 320         u32 secondary_vm_exec_control;
 321         u32 vm_instruction_error;
 322         u32 vm_exit_reason;
 323         u32 vm_exit_intr_info;
 324         u32 vm_exit_intr_error_code;
 325         u32 idt_vectoring_info_field;
 326         u32 idt_vectoring_error_code;
 327         u32 vm_exit_instruction_len;
 328         u32 vmx_instruction_info;
 329         u32 guest_es_limit;
 330         u32 guest_cs_limit;
 331         u32 guest_ss_limit;
 332         u32 guest_ds_limit;
 333         u32 guest_fs_limit;
 334         u32 guest_gs_limit;
 335         u32 guest_ldtr_limit;
 336         u32 guest_tr_limit;
 337         u32 guest_gdtr_limit;
 338         u32 guest_idtr_limit;
 339         u32 guest_es_ar_bytes;
 340         u32 guest_cs_ar_bytes;
 341         u32 guest_ss_ar_bytes;
 342         u32 guest_ds_ar_bytes;
 343         u32 guest_fs_ar_bytes;
 344         u32 guest_gs_ar_bytes;
 345         u32 guest_ldtr_ar_bytes;
 346         u32 guest_tr_ar_bytes;
 347         u32 guest_interruptibility_info;
 348         u32 guest_activity_state;
 349         u32 guest_sysenter_cs;
 350         u32 host_ia32_sysenter_cs;
 351         u32 vmx_preemption_timer_value;
 352         u32 padding32[7]; /* room for future expansion */
 353         u16 virtual_processor_id;
 354         u16 posted_intr_nv;
 355         u16 guest_es_selector;
 356         u16 guest_cs_selector;
 357         u16 guest_ss_selector;
 358         u16 guest_ds_selector;
 359         u16 guest_fs_selector;
 360         u16 guest_gs_selector;
 361         u16 guest_ldtr_selector;
 362         u16 guest_tr_selector;
 363         u16 guest_intr_status;
 364         u16 host_es_selector;
 365         u16 host_cs_selector;
 366         u16 host_ss_selector;
 367         u16 host_ds_selector;
 368         u16 host_fs_selector;
 369         u16 host_gs_selector;
 370         u16 host_tr_selector;
 371 };
 372
 373 /*
 374  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 375  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 376  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 377  */
 378 #define VMCS12_REVISION 0x11e57ed0
 379
 380 /*
 381  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 382  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 383  * current implementation, 4K are reserved to avoid future complications.
 384  */
 385 #define VMCS12_SIZE 0x1000
 386
 387 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 388 struct vmcs02_list {
 389         struct list_head list;
 390         gpa_t vmptr;
 391         struct loaded_vmcs vmcs02;
 392 };
 393
 394 /*
 395  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 396  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 397  */
 398 struct nested_vmx {
 399         /* Has the level1 guest done vmxon? */
 400         bool vmxon;
 401         gpa_t vmxon_ptr;
 402
 403         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 404         gpa_t current_vmptr;
 405         /* The host-usable pointer to the above */
 406         struct page *current_vmcs12_page;
 407         struct vmcs12 *current_vmcs12;
 408         /*
 409          * Cache of the guest's VMCS, existing outside of guest memory.
 410          * Loaded from guest memory during VMPTRLD. Flushed to guest
 411          * memory during VMXOFF, VMCLEAR, VMPTRLD.
 412          */
 413         struct vmcs12 *cached_vmcs12;
 414         struct vmcs *current_shadow_vmcs;
 415         /*
 416          * Indicates if the shadow vmcs must be updated with the
 417          * data hold by vmcs12
 418          */
 419         bool sync_shadow_vmcs;
 420
 421         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 422         struct list_head vmcs02_pool;
 423         int vmcs02_num;
 424         u64 vmcs01_tsc_offset;
 425         bool change_vmcs01_virtual_x2apic_mode;
 426         /* L2 must run next, and mustn't decide to exit to L1. */
 427         bool nested_run_pending;
 428         /*
 429          * Guest pages referred to in vmcs02 with host-physical pointers, so
 430          * we must keep them pinned while L2 runs.
 431          */
 432         struct page *apic_access_page;
 433         struct page *virtual_apic_page;
 434         struct page *pi_desc_page;
 435         struct pi_desc *pi_desc;
 436         bool pi_pending;
 437         u16 posted_intr_nv;
 438
 439         unsigned long *msr_bitmap;
 440
 441         struct hrtimer preemption_timer;
 442         bool preemption_timer_expired;
 443
 444         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 445         u64 vmcs01_debugctl;
 446
 447         u16 vpid02;
 448         u16 last_vpid;
 449
 450         u32 nested_vmx_procbased_ctls_low;
 451         u32 nested_vmx_procbased_ctls_high;
 452         u32 nested_vmx_true_procbased_ctls_low;
 453         u32 nested_vmx_secondary_ctls_low;
 454         u32 nested_vmx_secondary_ctls_high;
 455         u32 nested_vmx_pinbased_ctls_low;
 456         u32 nested_vmx_pinbased_ctls_high;
 457         u32 nested_vmx_exit_ctls_low;
 458         u32 nested_vmx_exit_ctls_high;
 459         u32 nested_vmx_true_exit_ctls_low;
 460         u32 nested_vmx_entry_ctls_low;
 461         u32 nested_vmx_entry_ctls_high;
 462         u32 nested_vmx_true_entry_ctls_low;
 463         u32 nested_vmx_misc_low;
 464         u32 nested_vmx_misc_high;
 465         u32 nested_vmx_ept_caps;
 466         u32 nested_vmx_vpid_caps;
 467 };
 468
 469 #define POSTED_INTR_ON  0
 470 #define POSTED_INTR_SN  1
 471
 472 /* Posted-Interrupt Descriptor */
 473 struct pi_desc {
 474         u32 pir[8];     /* Posted interrupt requested */
 475         union {
 476                 struct {
 477                                 /* bit 256 - Outstanding Notification */
 478                         u16     on      : 1,
 479                                 /* bit 257 - Suppress Notification */
 480                                 sn      : 1,
 481                                 /* bit 271:258 - Reserved */
 482                                 rsvd_1  : 14;
 483                                 /* bit 279:272 - Notification Vector */
 484                         u8      nv;
 485                                 /* bit 287:280 - Reserved */
 486                         u8      rsvd_2;
 487                                 /* bit 319:288 - Notification Destination */
 488                         u32     ndst;
 489                 };
 490                 u64 control;
 491         };
 492         u32 rsvd[6];
 493 } __aligned(64);
 494
 495 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 496 {
 497         return test_and_set_bit(POSTED_INTR_ON,
 498                         (unsigned long *)&pi_desc->control);
 499 }
 500
 501 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 502 {
 503         return test_and_clear_bit(POSTED_INTR_ON,
 504                         (unsigned long *)&pi_desc->control);
 505 }
 506
 507 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 508 {
 509         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 510 }
 511
 512 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 513 {
 514         return clear_bit(POSTED_INTR_SN,
 515                         (unsigned long *)&pi_desc->control);
 516 }
 517
 518 static inline void pi_set_sn(struct pi_desc *pi_desc)
 519 {
 520         return set_bit(POSTED_INTR_SN,
 521                         (unsigned long *)&pi_desc->control);
 522 }
 523
 524 static inline int pi_test_on(struct pi_desc *pi_desc)
 525 {
 526         return test_bit(POSTED_INTR_ON,
 527                         (unsigned long *)&pi_desc->control);
 528 }
 529
 530 static inline int pi_test_sn(struct pi_desc *pi_desc)
 531 {
 532         return test_bit(POSTED_INTR_SN,
 533                         (unsigned long *)&pi_desc->control);
 534 }
 535
 536 struct vcpu_vmx {
 537         struct kvm_vcpu       vcpu;
 538         unsigned long         host_rsp;
 539         u8                    fail;
 540         bool                  nmi_known_unmasked;
 541         u32                   exit_intr_info;
 542         u32                   idt_vectoring_info;
 543         ulong                 rflags;
 544         struct shared_msr_entry *guest_msrs;
 545         int                   nmsrs;
 546         int                   save_nmsrs;
 547         unsigned long         host_idt_base;
 548 #ifdef CONFIG_X86_64
 549         u64                   msr_host_kernel_gs_base;
 550         u64                   msr_guest_kernel_gs_base;
 551 #endif
 552         u32 vm_entry_controls_shadow;
 553         u32 vm_exit_controls_shadow;
 554         /*
 555          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 556          * non-nested (L1) guest, it always points to vmcs01. For a nested
 557          * guest (L2), it points to a different VMCS.
 558          */
 559         struct loaded_vmcs    vmcs01;
 560         struct loaded_vmcs   *loaded_vmcs;
 561         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 562         struct msr_autoload {
 563                 unsigned nr;
 564                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 565                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 566         } msr_autoload;
 567         struct {
 568                 int           loaded;
 569                 u16           fs_sel, gs_sel, ldt_sel;
 570 #ifdef CONFIG_X86_64
 571                 u16           ds_sel, es_sel;
 572 #endif
 573                 int           gs_ldt_reload_needed;
 574                 int           fs_reload_needed;
 575                 u64           msr_host_bndcfgs;
 576                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 577         } host_state;
 578         struct {
 579                 int vm86_active;
 580                 ulong save_rflags;
 581                 struct kvm_segment segs[8];
 582         } rmode;
 583         struct {
 584                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 585                 struct kvm_save_segment {
 586                         u16 selector;
 587                         unsigned long base;
 588                         u32 limit;
 589                         u32 ar;
 590                 } seg[8];
 591         } segment_cache;
 592         int vpid;
 593         bool emulation_required;
 594
 595         /* Support for vnmi-less CPUs */
 596         int soft_vnmi_blocked;
 597         ktime_t entry_time;
 598         s64 vnmi_blocked_time;
 599         u32 exit_reason;
 600
 601         /* Posted interrupt descriptor */
 602         struct pi_desc pi_desc;
 603
 604         /* Support for a guest hypervisor (nested VMX) */
 605         struct nested_vmx nested;
 606
 607         /* Dynamic PLE window. */
 608         int ple_window;
 609         bool ple_window_dirty;
 610
 611         /* Support for PML */
 612 #define PML_ENTITY_NUM          512
 613         struct page *pml_pg;
 614
 615         /* apic deadline value in host tsc */
 616         u64 hv_deadline_tsc;
 617
 618         u64 current_tsc_ratio;
 619
 620         bool guest_pkru_valid;
 621         u32 guest_pkru;
 622         u32 host_pkru;
 623
 624         /*
 625          * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
 626          * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
 627          * in msr_ia32_feature_control_valid_bits.
 628          */
 629         u64 msr_ia32_feature_control;
 630         u64 msr_ia32_feature_control_valid_bits;
 631 };
 632
 633 enum segment_cache_field {
 634         SEG_FIELD_SEL = 0,
 635         SEG_FIELD_BASE = 1,
 636         SEG_FIELD_LIMIT = 2,
 637         SEG_FIELD_AR = 3,
 638
 639         SEG_FIELD_NR = 4
 640 };
 641
 642 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 643 {
 644         return container_of(vcpu, struct vcpu_vmx, vcpu);
 645 }
 646
 647 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 648 {
 649         return &(to_vmx(vcpu)->pi_desc);
 650 }
 651
 652 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 653 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 654 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 655                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 656
 657
 658 static unsigned long shadow_read_only_fields[] = {
 659         /*
 660          * We do NOT shadow fields that are modified when L0
 661          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 662          * VMXON...) executed by L1.
 663          * For example, VM_INSTRUCTION_ERROR is read
 664          * by L1 if a vmx instruction fails (part of the error path).
 665          * Note the code assumes this logic. If for some reason
 666          * we start shadowing these fields then we need to
 667          * force a shadow sync when L0 emulates vmx instructions
 668          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 669          * by nested_vmx_failValid)
 670          */
 671         VM_EXIT_REASON,
 672         VM_EXIT_INTR_INFO,
 673         VM_EXIT_INSTRUCTION_LEN,
 674         IDT_VECTORING_INFO_FIELD,
 675         IDT_VECTORING_ERROR_CODE,
 676         VM_EXIT_INTR_ERROR_CODE,
 677         EXIT_QUALIFICATION,
 678         GUEST_LINEAR_ADDRESS,
 679         GUEST_PHYSICAL_ADDRESS
 680 };
 681 static int max_shadow_read_only_fields =
 682         ARRAY_SIZE(shadow_read_only_fields);
 683
 684 static unsigned long shadow_read_write_fields[] = {
 685         TPR_THRESHOLD,
 686         GUEST_RIP,
 687         GUEST_RSP,
 688         GUEST_CR0,
 689         GUEST_CR3,
 690         GUEST_CR4,
 691         GUEST_INTERRUPTIBILITY_INFO,
 692         GUEST_RFLAGS,
 693         GUEST_CS_SELECTOR,
 694         GUEST_CS_AR_BYTES,
 695         GUEST_CS_LIMIT,
 696         GUEST_CS_BASE,
 697         GUEST_ES_BASE,
 698         GUEST_BNDCFGS,
 699         CR0_GUEST_HOST_MASK,
 700         CR0_READ_SHADOW,
 701         CR4_READ_SHADOW,
 702         TSC_OFFSET,
 703         EXCEPTION_BITMAP,
 704         CPU_BASED_VM_EXEC_CONTROL,
 705         VM_ENTRY_EXCEPTION_ERROR_CODE,
 706         VM_ENTRY_INTR_INFO_FIELD,
 707         VM_ENTRY_INSTRUCTION_LEN,
 708         VM_ENTRY_EXCEPTION_ERROR_CODE,
 709         HOST_FS_BASE,
 710         HOST_GS_BASE,
 711         HOST_FS_SELECTOR,
 712         HOST_GS_SELECTOR
 713 };
 714 static int max_shadow_read_write_fields =
 715         ARRAY_SIZE(shadow_read_write_fields);
 716
 717 static const unsigned short vmcs_field_to_offset_table[] = {
 718         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 719         FIELD(POSTED_INTR_NV, posted_intr_nv),
 720         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 721         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 722         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 723         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 724         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 725         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 726         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 727         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 728         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 729         FIELD(HOST_ES_SELECTOR, host_es_selector),
 730         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 731         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 732         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 733         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 734         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 735         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 736         FIELD64(IO_BITMAP_A, io_bitmap_a),
 737         FIELD64(IO_BITMAP_B, io_bitmap_b),
 738         FIELD64(MSR_BITMAP, msr_bitmap),
 739         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 740         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 741         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 742         FIELD64(TSC_OFFSET, tsc_offset),
 743         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 744         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 745         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 746         FIELD64(EPT_POINTER, ept_pointer),
 747         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 748         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 749         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 750         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 751         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 752         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 753         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 754         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 755         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 756         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 757         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 758         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 759         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 760         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 761         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 762         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 763         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 764         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 765         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 766         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 767         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 768         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 769         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 770         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 771         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 772         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 773         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 774         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 775         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 776         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 777         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 778         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 779         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 780         FIELD(TPR_THRESHOLD, tpr_threshold),
 781         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 782         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 783         FIELD(VM_EXIT_REASON, vm_exit_reason),
 784         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 785         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 786         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 787         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 788         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 789         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 790         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 791         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 792         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 793         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 794         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 795         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 796         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 797         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 798         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 799         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 800         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 801         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 802         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 803         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 804         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 805         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 806         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 807         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 808         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 809         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 810         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 811         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 812         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 813         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 814         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 815         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 816         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 817         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 818         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 819         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 820         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 821         FIELD(EXIT_QUALIFICATION, exit_qualification),
 822         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 823         FIELD(GUEST_CR0, guest_cr0),
 824         FIELD(GUEST_CR3, guest_cr3),
 825         FIELD(GUEST_CR4, guest_cr4),
 826         FIELD(GUEST_ES_BASE, guest_es_base),
 827         FIELD(GUEST_CS_BASE, guest_cs_base),
 828         FIELD(GUEST_SS_BASE, guest_ss_base),
 829         FIELD(GUEST_DS_BASE, guest_ds_base),
 830         FIELD(GUEST_FS_BASE, guest_fs_base),
 831         FIELD(GUEST_GS_BASE, guest_gs_base),
 832         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 833         FIELD(GUEST_TR_BASE, guest_tr_base),
 834         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 835         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 836         FIELD(GUEST_DR7, guest_dr7),
 837         FIELD(GUEST_RSP, guest_rsp),
 838         FIELD(GUEST_RIP, guest_rip),
 839         FIELD(GUEST_RFLAGS, guest_rflags),
 840         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 841         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 842         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 843         FIELD(HOST_CR0, host_cr0),
 844         FIELD(HOST_CR3, host_cr3),
 845         FIELD(HOST_CR4, host_cr4),
 846         FIELD(HOST_FS_BASE, host_fs_base),
 847         FIELD(HOST_GS_BASE, host_gs_base),
 848         FIELD(HOST_TR_BASE, host_tr_base),
 849         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 850         FIELD(HOST_IDTR_BASE, host_idtr_base),
 851         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 852         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 853         FIELD(HOST_RSP, host_rsp),
 854         FIELD(HOST_RIP, host_rip),
 855 };
 856
 857 static inline short vmcs_field_to_offset(unsigned long field)
 858 {
 859         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 860
 861         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 862             vmcs_field_to_offset_table[field] == 0)
 863                 return -ENOENT;
 864
 865         return vmcs_field_to_offset_table[field];
 866 }
 867
 868 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 869 {
 870         return to_vmx(vcpu)->nested.cached_vmcs12;
 871 }
 872
 873 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 874 {
 875         struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
 876         if (is_error_page(page))
 877                 return NULL;
 878
 879         return page;
 880 }
 881
 882 static void nested_release_page(struct page *page)
 883 {
 884         kvm_release_page_dirty(page);
 885 }
 886
 887 static void nested_release_page_clean(struct page *page)
 888 {
 889         kvm_release_page_clean(page);
 890 }
 891
 892 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 893 static u64 construct_eptp(unsigned long root_hpa);
 894 static void kvm_cpu_vmxon(u64 addr);
 895 static void kvm_cpu_vmxoff(void);
 896 static bool vmx_xsaves_supported(void);
 897 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 898 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 899                             struct kvm_segment *var, int seg);
 900 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 901                             struct kvm_segment *var, int seg);
 902 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 903 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 904 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 905 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 906 static int alloc_identity_pagetable(struct kvm *kvm);
 907
 908 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 909 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 910 /*
 911  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 912  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 913  */
 914 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 915 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 916
 917 /*
 918  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 919  * can find which vCPU should be waken up.
 920  */
 921 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 922 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 923
 924 static unsigned long *vmx_io_bitmap_a;
 925 static unsigned long *vmx_io_bitmap_b;
 926 static unsigned long *vmx_msr_bitmap_legacy;
 927 static unsigned long *vmx_msr_bitmap_longmode;
 928 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 929 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 930 static unsigned long *vmx_vmread_bitmap;
 931 static unsigned long *vmx_vmwrite_bitmap;
 932
 933 static bool cpu_has_load_ia32_efer;
 934 static bool cpu_has_load_perf_global_ctrl;
 935
 936 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 937 static DEFINE_SPINLOCK(vmx_vpid_lock);
 938
 939 static struct vmcs_config {
 940         int size;
 941         int order;
 942         u32 revision_id;
 943         u32 pin_based_exec_ctrl;
 944         u32 cpu_based_exec_ctrl;
 945         u32 cpu_based_2nd_exec_ctrl;
 946         u32 vmexit_ctrl;
 947         u32 vmentry_ctrl;
 948 } vmcs_config;
 949
 950 static struct vmx_capability {
 951         u32 ept;
 952         u32 vpid;
 953 } vmx_capability;
 954
 955 #define VMX_SEGMENT_FIELD(seg)                                  \
 956         [VCPU_SREG_##seg] = {                                   \
 957                 .selector = GUEST_##seg##_SELECTOR,             \
 958                 .base = GUEST_##seg##_BASE,                     \
 959                 .limit = GUEST_##seg##_LIMIT,                   \
 960                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 961         }
 962
 963 static const struct kvm_vmx_segment_field {
 964         unsigned selector;
 965         unsigned base;
 966         unsigned limit;
 967         unsigned ar_bytes;
 968 } kvm_vmx_segment_fields[] = {
 969         VMX_SEGMENT_FIELD(CS),
 970         VMX_SEGMENT_FIELD(DS),
 971         VMX_SEGMENT_FIELD(ES),
 972         VMX_SEGMENT_FIELD(FS),
 973         VMX_SEGMENT_FIELD(GS),
 974         VMX_SEGMENT_FIELD(SS),
 975         VMX_SEGMENT_FIELD(TR),
 976         VMX_SEGMENT_FIELD(LDTR),
 977 };
 978
 979 static u64 host_efer;
 980
 981 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 982
 983 /*
 984  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 985  * away by decrementing the array size.
 986  */
 987 static const u32 vmx_msr_index[] = {
 988 #ifdef CONFIG_X86_64
 989         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 990 #endif
 991         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 992 };
 993
 994 static inline bool is_exception_n(u32 intr_info, u8 vector)
 995 {
 996         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 997                              INTR_INFO_VALID_MASK)) ==
 998                 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
 999 }
1000
1001 static inline bool is_debug(u32 intr_info)
1002 {
1003         return is_exception_n(intr_info, DB_VECTOR);
1004 }
1005
1006 static inline bool is_breakpoint(u32 intr_info)
1007 {
1008         return is_exception_n(intr_info, BP_VECTOR);
1009 }
1010
1011 static inline bool is_page_fault(u32 intr_info)
1012 {
1013         return is_exception_n(intr_info, PF_VECTOR);
1014 }
1015
1016 static inline bool is_no_device(u32 intr_info)
1017 {
1018         return is_exception_n(intr_info, NM_VECTOR);
1019 }
1020
1021 static inline bool is_invalid_opcode(u32 intr_info)
1022 {
1023         return is_exception_n(intr_info, UD_VECTOR);
1024 }
1025
1026 static inline bool is_external_interrupt(u32 intr_info)
1027 {
1028         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1029                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1030 }
1031
1032 static inline bool is_machine_check(u32 intr_info)
1033 {
1034         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1035                              INTR_INFO_VALID_MASK)) ==
1036                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1037 }
1038
1039 static inline bool cpu_has_vmx_msr_bitmap(void)
1040 {
1041         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1042 }
1043
1044 static inline bool cpu_has_vmx_tpr_shadow(void)
1045 {
1046         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1047 }
1048
1049 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1050 {
1051         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1052 }
1053
1054 static inline bool cpu_has_secondary_exec_ctrls(void)
1055 {
1056         return vmcs_config.cpu_based_exec_ctrl &
1057                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1058 }
1059
1060 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1061 {
1062         return vmcs_config.cpu_based_2nd_exec_ctrl &
1063                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1064 }
1065
1066 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1067 {
1068         return vmcs_config.cpu_based_2nd_exec_ctrl &
1069                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1070 }
1071
1072 static inline bool cpu_has_vmx_apic_register_virt(void)
1073 {
1074         return vmcs_config.cpu_based_2nd_exec_ctrl &
1075                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1076 }
1077
1078 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1079 {
1080         return vmcs_config.cpu_based_2nd_exec_ctrl &
1081                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1082 }
1083
1084 /*
1085  * Comment's format: document - errata name - stepping - processor name.
1086  * Refer from
1087  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1088  */
1089 static u32 vmx_preemption_cpu_tfms[] = {
1090 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
1091 0x000206E6,
1092 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
1093 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1094 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1095 0x00020652,
1096 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1097 0x00020655,
1098 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
1099 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
1100 /*
1101  * 320767.pdf - AAP86  - B1 -
1102  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1103  */
1104 0x000106E5,
1105 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1106 0x000106A0,
1107 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1108 0x000106A1,
1109 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1110 0x000106A4,
1111  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1112  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1113  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1114 0x000106A5,
1115 };
1116
1117 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1118 {
1119         u32 eax = cpuid_eax(0x00000001), i;
1120
1121         /* Clear the reserved bits */
1122         eax &= ~(0x3U << 14 | 0xfU << 28);
1123         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1124                 if (eax == vmx_preemption_cpu_tfms[i])
1125                         return true;
1126
1127         return false;
1128 }
1129
1130 static inline bool cpu_has_vmx_preemption_timer(void)
1131 {
1132         return vmcs_config.pin_based_exec_ctrl &
1133                 PIN_BASED_VMX_PREEMPTION_TIMER;
1134 }
1135
1136 static inline bool cpu_has_vmx_posted_intr(void)
1137 {
1138         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1139                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1140 }
1141
1142 static inline bool cpu_has_vmx_apicv(void)
1143 {
1144         return cpu_has_vmx_apic_register_virt() &&
1145                 cpu_has_vmx_virtual_intr_delivery() &&
1146                 cpu_has_vmx_posted_intr();
1147 }
1148
1149 static inline bool cpu_has_vmx_flexpriority(void)
1150 {
1151         return cpu_has_vmx_tpr_shadow() &&
1152                 cpu_has_vmx_virtualize_apic_accesses();
1153 }
1154
1155 static inline bool cpu_has_vmx_ept_execute_only(void)
1156 {
1157         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1158 }
1159
1160 static inline bool cpu_has_vmx_ept_2m_page(void)
1161 {
1162         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1163 }
1164
1165 static inline bool cpu_has_vmx_ept_1g_page(void)
1166 {
1167         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1168 }
1169
1170 static inline bool cpu_has_vmx_ept_4levels(void)
1171 {
1172         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1173 }
1174
1175 static inline bool cpu_has_vmx_ept_ad_bits(void)
1176 {
1177         return vmx_capability.ept & VMX_EPT_AD_BIT;
1178 }
1179
1180 static inline bool cpu_has_vmx_invept_context(void)
1181 {
1182         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1183 }
1184
1185 static inline bool cpu_has_vmx_invept_global(void)
1186 {
1187         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1188 }
1189
1190 static inline bool cpu_has_vmx_invvpid_single(void)
1191 {
1192         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1193 }
1194
1195 static inline bool cpu_has_vmx_invvpid_global(void)
1196 {
1197         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1198 }
1199
1200 static inline bool cpu_has_vmx_ept(void)
1201 {
1202         return vmcs_config.cpu_based_2nd_exec_ctrl &
1203                 SECONDARY_EXEC_ENABLE_EPT;
1204 }
1205
1206 static inline bool cpu_has_vmx_unrestricted_guest(void)
1207 {
1208         return vmcs_config.cpu_based_2nd_exec_ctrl &
1209                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1210 }
1211
1212 static inline bool cpu_has_vmx_ple(void)
1213 {
1214         return vmcs_config.cpu_based_2nd_exec_ctrl &
1215                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1216 }
1217
1218 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1219 {
1220         return flexpriority_enabled && lapic_in_kernel(vcpu);
1221 }
1222
1223 static inline bool cpu_has_vmx_vpid(void)
1224 {
1225         return vmcs_config.cpu_based_2nd_exec_ctrl &
1226                 SECONDARY_EXEC_ENABLE_VPID;
1227 }
1228
1229 static inline bool cpu_has_vmx_rdtscp(void)
1230 {
1231         return vmcs_config.cpu_based_2nd_exec_ctrl &
1232                 SECONDARY_EXEC_RDTSCP;
1233 }
1234
1235 static inline bool cpu_has_vmx_invpcid(void)
1236 {
1237         return vmcs_config.cpu_based_2nd_exec_ctrl &
1238                 SECONDARY_EXEC_ENABLE_INVPCID;
1239 }
1240
1241 static inline bool cpu_has_virtual_nmis(void)
1242 {
1243         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1244 }
1245
1246 static inline bool cpu_has_vmx_wbinvd_exit(void)
1247 {
1248         return vmcs_config.cpu_based_2nd_exec_ctrl &
1249                 SECONDARY_EXEC_WBINVD_EXITING;
1250 }
1251
1252 static inline bool cpu_has_vmx_shadow_vmcs(void)
1253 {
1254         u64 vmx_msr;
1255         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1256         /* check if the cpu supports writing r/o exit information fields */
1257         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1258                 return false;
1259
1260         return vmcs_config.cpu_based_2nd_exec_ctrl &
1261                 SECONDARY_EXEC_SHADOW_VMCS;
1262 }
1263
1264 static inline bool cpu_has_vmx_pml(void)
1265 {
1266         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1267 }
1268
1269 static inline bool cpu_has_vmx_tsc_scaling(void)
1270 {
1271         return vmcs_config.cpu_based_2nd_exec_ctrl &
1272                 SECONDARY_EXEC_TSC_SCALING;
1273 }
1274
1275 static inline bool report_flexpriority(void)
1276 {
1277         return flexpriority_enabled;
1278 }
1279
1280 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1281 {
1282         return vmcs12->cpu_based_vm_exec_control & bit;
1283 }
1284
1285 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1286 {
1287         return (vmcs12->cpu_based_vm_exec_control &
1288                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1289                 (vmcs12->secondary_vm_exec_control & bit);
1290 }
1291
1292 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1293 {
1294         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1295 }
1296
1297 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1298 {
1299         return vmcs12->pin_based_vm_exec_control &
1300                 PIN_BASED_VMX_PREEMPTION_TIMER;
1301 }
1302
1303 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1304 {
1305         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1306 }
1307
1308 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1309 {
1310         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1311                 vmx_xsaves_supported();
1312 }
1313
1314 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1315 {
1316         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1317 }
1318
1319 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1320 {
1321         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1322 }
1323
1324 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1325 {
1326         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1327 }
1328
1329 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1330 {
1331         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1332 }
1333
1334 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1335 {
1336         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1337 }
1338
1339 static inline bool is_exception(u32 intr_info)
1340 {
1341         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1342                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1343 }
1344
1345 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1346                               u32 exit_intr_info,
1347                               unsigned long exit_qualification);
1348 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1349                         struct vmcs12 *vmcs12,
1350                         u32 reason, unsigned long qualification);
1351
1352 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1353 {
1354         int i;
1355
1356         for (i = 0; i < vmx->nmsrs; ++i)
1357                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1358                         return i;
1359         return -1;
1360 }
1361
1362 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1363 {
1364     struct {
1365         u64 vpid : 16;
1366         u64 rsvd : 48;
1367         u64 gva;
1368     } operand = { vpid, 0, gva };
1369
1370     asm volatile (__ex(ASM_VMX_INVVPID)
1371                   /* CF==1 or ZF==1 --> rc = -1 */
1372                   "; ja 1f ; ud2 ; 1:"
1373                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1374 }
1375
1376 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1377 {
1378         struct {
1379                 u64 eptp, gpa;
1380         } operand = {eptp, gpa};
1381
1382         asm volatile (__ex(ASM_VMX_INVEPT)
1383                         /* CF==1 or ZF==1 --> rc = -1 */
1384                         "; ja 1f ; ud2 ; 1:\n"
1385                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1386 }
1387
1388 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1389 {
1390         int i;
1391
1392         i = __find_msr_index(vmx, msr);
1393         if (i >= 0)
1394                 return &vmx->guest_msrs[i];
1395         return NULL;
1396 }
1397
1398 static void vmcs_clear(struct vmcs *vmcs)
1399 {
1400         u64 phys_addr = __pa(vmcs);
1401         u8 error;
1402
1403         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1404                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1405                       : "cc", "memory");
1406         if (error)
1407                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1408                        vmcs, phys_addr);
1409 }
1410
1411 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1412 {
1413         vmcs_clear(loaded_vmcs->vmcs);
1414         loaded_vmcs->cpu = -1;
1415         loaded_vmcs->launched = 0;
1416 }
1417
1418 static void vmcs_load(struct vmcs *vmcs)
1419 {
1420         u64 phys_addr = __pa(vmcs);
1421         u8 error;
1422
1423         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1424                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1425                         : "cc", "memory");
1426         if (error)
1427                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1428                        vmcs, phys_addr);
1429 }
1430
1431 #ifdef CONFIG_KEXEC_CORE
1432 /*
1433  * This bitmap is used to indicate whether the vmclear
1434  * operation is enabled on all cpus. All disabled by
1435  * default.
1436  */
1437 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1438
1439 static inline void crash_enable_local_vmclear(int cpu)
1440 {
1441         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1442 }
1443
1444 static inline void crash_disable_local_vmclear(int cpu)
1445 {
1446         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1447 }
1448
1449 static inline int crash_local_vmclear_enabled(int cpu)
1450 {
1451         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1452 }
1453
1454 static void crash_vmclear_local_loaded_vmcss(void)
1455 {
1456         int cpu = raw_smp_processor_id();
1457         struct loaded_vmcs *v;
1458
1459         if (!crash_local_vmclear_enabled(cpu))
1460                 return;
1461
1462         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1463                             loaded_vmcss_on_cpu_link)
1464                 vmcs_clear(v->vmcs);
1465 }
1466 #else
1467 static inline void crash_enable_local_vmclear(int cpu) { }
1468 static inline void crash_disable_local_vmclear(int cpu) { }
1469 #endif /* CONFIG_KEXEC_CORE */
1470
1471 static void __loaded_vmcs_clear(void *arg)
1472 {
1473         struct loaded_vmcs *loaded_vmcs = arg;
1474         int cpu = raw_smp_processor_id();
1475
1476         if (loaded_vmcs->cpu != cpu)
1477                 return; /* vcpu migration can race with cpu offline */
1478         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1479                 per_cpu(current_vmcs, cpu) = NULL;
1480         crash_disable_local_vmclear(cpu);
1481         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1482
1483         /*
1484          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1485          * is before setting loaded_vmcs->vcpu to -1 which is done in
1486          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1487          * then adds the vmcs into percpu list before it is deleted.
1488          */
1489         smp_wmb();
1490
1491         loaded_vmcs_init(loaded_vmcs);
1492         crash_enable_local_vmclear(cpu);
1493 }
1494
1495 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1496 {
1497         int cpu = loaded_vmcs->cpu;
1498
1499         if (cpu != -1)
1500                 smp_call_function_single(cpu,
1501                          __loaded_vmcs_clear, loaded_vmcs, 1);
1502 }
1503
1504 static inline void vpid_sync_vcpu_single(int vpid)
1505 {
1506         if (vpid == 0)
1507                 return;
1508
1509         if (cpu_has_vmx_invvpid_single())
1510                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1511 }
1512
1513 static inline void vpid_sync_vcpu_global(void)
1514 {
1515         if (cpu_has_vmx_invvpid_global())
1516                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1517 }
1518
1519 static inline void vpid_sync_context(int vpid)
1520 {
1521         if (cpu_has_vmx_invvpid_single())
1522                 vpid_sync_vcpu_single(vpid);
1523         else
1524                 vpid_sync_vcpu_global();
1525 }
1526
1527 static inline void ept_sync_global(void)
1528 {
1529         if (cpu_has_vmx_invept_global())
1530                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1531 }
1532
1533 static inline void ept_sync_context(u64 eptp)
1534 {
1535         if (enable_ept) {
1536                 if (cpu_has_vmx_invept_context())
1537                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1538                 else
1539                         ept_sync_global();
1540         }
1541 }
1542
1543 static __always_inline void vmcs_check16(unsigned long field)
1544 {
1545         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1546                          "16-bit accessor invalid for 64-bit field");
1547         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1548                          "16-bit accessor invalid for 64-bit high field");
1549         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1550                          "16-bit accessor invalid for 32-bit high field");
1551         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1552                          "16-bit accessor invalid for natural width field");
1553 }
1554
1555 static __always_inline void vmcs_check32(unsigned long field)
1556 {
1557         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1558                          "32-bit accessor invalid for 16-bit field");
1559         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1560                          "32-bit accessor invalid for natural width field");
1561 }
1562
1563 static __always_inline void vmcs_check64(unsigned long field)
1564 {
1565         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1566                          "64-bit accessor invalid for 16-bit field");
1567         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1568                          "64-bit accessor invalid for 64-bit high field");
1569         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1570                          "64-bit accessor invalid for 32-bit field");
1571         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1572                          "64-bit accessor invalid for natural width field");
1573 }
1574
1575 static __always_inline void vmcs_checkl(unsigned long field)
1576 {
1577         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1578                          "Natural width accessor invalid for 16-bit field");
1579         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1580                          "Natural width accessor invalid for 64-bit field");
1581         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1582                          "Natural width accessor invalid for 64-bit high field");
1583         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1584                          "Natural width accessor invalid for 32-bit field");
1585 }
1586
1587 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1588 {
1589         unsigned long value;
1590
1591         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1592                       : "=a"(value) : "d"(field) : "cc");
1593         return value;
1594 }
1595
1596 static __always_inline u16 vmcs_read16(unsigned long field)
1597 {
1598         vmcs_check16(field);
1599         return __vmcs_readl(field);
1600 }
1601
1602 static __always_inline u32 vmcs_read32(unsigned long field)
1603 {
1604         vmcs_check32(field);
1605         return __vmcs_readl(field);
1606 }
1607
1608 static __always_inline u64 vmcs_read64(unsigned long field)
1609 {
1610         vmcs_check64(field);
1611 #ifdef CONFIG_X86_64
1612         return __vmcs_readl(field);
1613 #else
1614         return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1615 #endif
1616 }
1617
1618 static __always_inline unsigned long vmcs_readl(unsigned long field)
1619 {
1620         vmcs_checkl(field);
1621         return __vmcs_readl(field);
1622 }
1623
1624 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1625 {
1626         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1627                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1628         dump_stack();
1629 }
1630
1631 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1632 {
1633         u8 error;
1634
1635         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1636                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1637         if (unlikely(error))
1638                 vmwrite_error(field, value);
1639 }
1640
1641 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1642 {
1643         vmcs_check16(field);
1644         __vmcs_writel(field, value);
1645 }
1646
1647 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1648 {
1649         vmcs_check32(field);
1650         __vmcs_writel(field, value);
1651 }
1652
1653 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1654 {
1655         vmcs_check64(field);
1656         __vmcs_writel(field, value);
1657 #ifndef CONFIG_X86_64
1658         asm volatile ("");
1659         __vmcs_writel(field+1, value >> 32);
1660 #endif
1661 }
1662
1663 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1664 {
1665         vmcs_checkl(field);
1666         __vmcs_writel(field, value);
1667 }
1668
1669 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1670 {
1671         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1672                          "vmcs_clear_bits does not support 64-bit fields");
1673         __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1674 }
1675
1676 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1677 {
1678         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1679                          "vmcs_set_bits does not support 64-bit fields");
1680         __vmcs_writel(field, __vmcs_readl(field) | mask);
1681 }
1682
1683 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
1684 {
1685         vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
1686 }
1687
1688 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1689 {
1690         vmcs_write32(VM_ENTRY_CONTROLS, val);
1691         vmx->vm_entry_controls_shadow = val;
1692 }
1693
1694 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1695 {
1696         if (vmx->vm_entry_controls_shadow != val)
1697                 vm_entry_controls_init(vmx, val);
1698 }
1699
1700 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1701 {
1702         return vmx->vm_entry_controls_shadow;
1703 }
1704
1705
1706 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1707 {
1708         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1709 }
1710
1711 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1712 {
1713         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1714 }
1715
1716 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
1717 {
1718         vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
1719 }
1720
1721 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1722 {
1723         vmcs_write32(VM_EXIT_CONTROLS, val);
1724         vmx->vm_exit_controls_shadow = val;
1725 }
1726
1727 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1728 {
1729         if (vmx->vm_exit_controls_shadow != val)
1730                 vm_exit_controls_init(vmx, val);
1731 }
1732
1733 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1734 {
1735         return vmx->vm_exit_controls_shadow;
1736 }
1737
1738
1739 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1740 {
1741         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1742 }
1743
1744 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1745 {
1746         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1747 }
1748
1749 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1750 {
1751         vmx->segment_cache.bitmask = 0;
1752 }
1753
1754 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1755                                        unsigned field)
1756 {
1757         bool ret;
1758         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1759
1760         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1761                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1762                 vmx->segment_cache.bitmask = 0;
1763         }
1764         ret = vmx->segment_cache.bitmask & mask;
1765         vmx->segment_cache.bitmask |= mask;
1766         return ret;
1767 }
1768
1769 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1770 {
1771         u16 *p = &vmx->segment_cache.seg[seg].selector;
1772
1773         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1774                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1775         return *p;
1776 }
1777
1778 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1779 {
1780         ulong *p = &vmx->segment_cache.seg[seg].base;
1781
1782         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1783                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1784         return *p;
1785 }
1786
1787 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1788 {
1789         u32 *p = &vmx->segment_cache.seg[seg].limit;
1790
1791         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1792                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1793         return *p;
1794 }
1795
1796 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1797 {
1798         u32 *p = &vmx->segment_cache.seg[seg].ar;
1799
1800         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1801                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1802         return *p;
1803 }
1804
1805 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1806 {
1807         u32 eb;
1808
1809         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1810              (1u << NM_VECTOR) | (1u << DB_VECTOR) | (1u << AC_VECTOR);
1811         if ((vcpu->guest_debug &
1812              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1813             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1814                 eb |= 1u << BP_VECTOR;
1815         if (to_vmx(vcpu)->rmode.vm86_active)
1816                 eb = ~0;
1817         if (enable_ept)
1818                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1819         if (vcpu->fpu_active)
1820                 eb &= ~(1u << NM_VECTOR);
1821
1822         /* When we are running a nested L2 guest and L1 specified for it a
1823          * certain exception bitmap, we must trap the same exceptions and pass
1824          * them to L1. When running L2, we will only handle the exceptions
1825          * specified above if L1 did not want them.
1826          */
1827         if (is_guest_mode(vcpu))
1828                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1829
1830         vmcs_write32(EXCEPTION_BITMAP, eb);
1831 }
1832
1833 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1834                 unsigned long entry, unsigned long exit)
1835 {
1836         vm_entry_controls_clearbit(vmx, entry);
1837         vm_exit_controls_clearbit(vmx, exit);
1838 }
1839
1840 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1841 {
1842         unsigned i;
1843         struct msr_autoload *m = &vmx->msr_autoload;
1844
1845         switch (msr) {
1846         case MSR_EFER:
1847                 if (cpu_has_load_ia32_efer) {
1848                         clear_atomic_switch_msr_special(vmx,
1849                                         VM_ENTRY_LOAD_IA32_EFER,
1850                                         VM_EXIT_LOAD_IA32_EFER);
1851                         return;
1852                 }
1853                 break;
1854         case MSR_CORE_PERF_GLOBAL_CTRL:
1855                 if (cpu_has_load_perf_global_ctrl) {
1856                         clear_atomic_switch_msr_special(vmx,
1857                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1858                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1859                         return;
1860                 }
1861                 break;
1862         }
1863
1864         for (i = 0; i < m->nr; ++i)
1865                 if (m->guest[i].index == msr)
1866                         break;
1867
1868         if (i == m->nr)
1869                 return;
1870         --m->nr;
1871         m->guest[i] = m->guest[m->nr];
1872         m->host[i] = m->host[m->nr];
1873         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1874         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1875 }
1876
1877 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1878                 unsigned long entry, unsigned long exit,
1879                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1880                 u64 guest_val, u64 host_val)
1881 {
1882         vmcs_write64(guest_val_vmcs, guest_val);
1883         vmcs_write64(host_val_vmcs, host_val);
1884         vm_entry_controls_setbit(vmx, entry);
1885         vm_exit_controls_setbit(vmx, exit);
1886 }
1887
1888 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1889                                   u64 guest_val, u64 host_val)
1890 {
1891         unsigned i;
1892         struct msr_autoload *m = &vmx->msr_autoload;
1893
1894         switch (msr) {
1895         case MSR_EFER:
1896                 if (cpu_has_load_ia32_efer) {
1897                         add_atomic_switch_msr_special(vmx,
1898                                         VM_ENTRY_LOAD_IA32_EFER,
1899                                         VM_EXIT_LOAD_IA32_EFER,
1900                                         GUEST_IA32_EFER,
1901                                         HOST_IA32_EFER,
1902                                         guest_val, host_val);
1903                         return;
1904                 }
1905                 break;
1906         case MSR_CORE_PERF_GLOBAL_CTRL:
1907                 if (cpu_has_load_perf_global_ctrl) {
1908                         add_atomic_switch_msr_special(vmx,
1909                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1910                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1911                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1912                                         HOST_IA32_PERF_GLOBAL_CTRL,
1913                                         guest_val, host_val);
1914                         return;
1915                 }
1916                 break;
1917         case MSR_IA32_PEBS_ENABLE:
1918                 /* PEBS needs a quiescent period after being disabled (to write
1919                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
1920                  * provide that period, so a CPU could write host's record into
1921                  * guest's memory.
1922                  */
1923                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1924         }
1925
1926         for (i = 0; i < m->nr; ++i)
1927                 if (m->guest[i].index == msr)
1928                         break;
1929
1930         if (i == NR_AUTOLOAD_MSRS) {
1931                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1932                                 "Can't add msr %x\n", msr);
1933                 return;
1934         } else if (i == m->nr) {
1935                 ++m->nr;
1936                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1937                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1938         }
1939
1940         m->guest[i].index = msr;
1941         m->guest[i].value = guest_val;
1942         m->host[i].index = msr;
1943         m->host[i].value = host_val;
1944 }
1945
1946 static void reload_tss(void)
1947 {
1948         /*
1949          * VT restores TR but not its size.  Useless.
1950          */
1951         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1952         struct desc_struct *descs;
1953
1954         descs = (void *)gdt->address;
1955         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1956         load_TR_desc();
1957 }
1958
1959 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1960 {
1961         u64 guest_efer = vmx->vcpu.arch.efer;
1962         u64 ignore_bits = 0;
1963
1964         if (!enable_ept) {
1965                 /*
1966                  * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
1967                  * host CPUID is more efficient than testing guest CPUID
1968                  * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
1969                  */
1970                 if (boot_cpu_has(X86_FEATURE_SMEP))
1971                         guest_efer |= EFER_NX;
1972                 else if (!(guest_efer & EFER_NX))
1973                         ignore_bits |= EFER_NX;
1974         }
1975
1976         /*
1977          * LMA and LME handled by hardware; SCE meaningless outside long mode.
1978          */
1979         ignore_bits |= EFER_SCE;
1980 #ifdef CONFIG_X86_64
1981         ignore_bits |= EFER_LMA | EFER_LME;
1982         /* SCE is meaningful only in long mode on Intel */
1983         if (guest_efer & EFER_LMA)
1984                 ignore_bits &= ~(u64)EFER_SCE;
1985 #endif
1986
1987         clear_atomic_switch_msr(vmx, MSR_EFER);
1988
1989         /*
1990          * On EPT, we can't emulate NX, so we must switch EFER atomically.
1991          * On CPUs that support "load IA32_EFER", always switch EFER
1992          * atomically, since it's faster than switching it manually.
1993          */
1994         if (cpu_has_load_ia32_efer ||
1995             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1996                 if (!(guest_efer & EFER_LMA))
1997                         guest_efer &= ~EFER_LME;
1998                 if (guest_efer != host_efer)
1999                         add_atomic_switch_msr(vmx, MSR_EFER,
2000                                               guest_efer, host_efer);
2001                 return false;
2002         } else {
2003                 guest_efer &= ~ignore_bits;
2004                 guest_efer |= host_efer & ignore_bits;
2005
2006                 vmx->guest_msrs[efer_offset].data = guest_efer;
2007                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2008
2009                 return true;
2010         }
2011 }
2012
2013 static unsigned long segment_base(u16 selector)
2014 {
2015         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2016         struct desc_struct *d;
2017         unsigned long table_base;
2018         unsigned long v;
2019
2020         if (!(selector & ~3))
2021                 return 0;
2022
2023         table_base = gdt->address;
2024
2025         if (selector & 4) {           /* from ldt */
2026                 u16 ldt_selector = kvm_read_ldt();
2027
2028                 if (!(ldt_selector & ~3))
2029                         return 0;
2030
2031                 table_base = segment_base(ldt_selector);
2032         }
2033         d = (struct desc_struct *)(table_base + (selector & ~7));
2034         v = get_desc_base(d);
2035 #ifdef CONFIG_X86_64
2036        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
2037                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
2038 #endif
2039         return v;
2040 }
2041
2042 static inline unsigned long kvm_read_tr_base(void)
2043 {
2044         u16 tr;
2045         asm("str %0" : "=g"(tr));
2046         return segment_base(tr);
2047 }
2048
2049 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
2050 {
2051         struct vcpu_vmx *vmx = to_vmx(vcpu);
2052         int i;
2053
2054         if (vmx->host_state.loaded)
2055                 return;
2056
2057         vmx->host_state.loaded = 1;
2058         /*
2059          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
2060          * allow segment selectors with cpl > 0 or ti == 1.
2061          */
2062         vmx->host_state.ldt_sel = kvm_read_ldt();
2063         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
2064         savesegment(fs, vmx->host_state.fs_sel);
2065         if (!(vmx->host_state.fs_sel & 7)) {
2066                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
2067                 vmx->host_state.fs_reload_needed = 0;
2068         } else {
2069                 vmcs_write16(HOST_FS_SELECTOR, 0);
2070                 vmx->host_state.fs_reload_needed = 1;
2071         }
2072         savesegment(gs, vmx->host_state.gs_sel);
2073         if (!(vmx->host_state.gs_sel & 7))
2074                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
2075         else {
2076                 vmcs_write16(HOST_GS_SELECTOR, 0);
2077                 vmx->host_state.gs_ldt_reload_needed = 1;
2078         }
2079
2080 #ifdef CONFIG_X86_64
2081         savesegment(ds, vmx->host_state.ds_sel);
2082         savesegment(es, vmx->host_state.es_sel);
2083 #endif
2084
2085 #ifdef CONFIG_X86_64
2086         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2087         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2088 #else
2089         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2090         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2091 #endif
2092
2093 #ifdef CONFIG_X86_64
2094         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2095         if (is_long_mode(&vmx->vcpu))
2096                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2097 #endif
2098         if (boot_cpu_has(X86_FEATURE_MPX))
2099                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2100         for (i = 0; i < vmx->save_nmsrs; ++i)
2101                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2102                                    vmx->guest_msrs[i].data,
2103                                    vmx->guest_msrs[i].mask);
2104 }
2105
2106 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2107 {
2108         if (!vmx->host_state.loaded)
2109                 return;
2110
2111         ++vmx->vcpu.stat.host_state_reload;
2112         vmx->host_state.loaded = 0;
2113 #ifdef CONFIG_X86_64
2114         if (is_long_mode(&vmx->vcpu))
2115                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2116 #endif
2117         if (vmx->host_state.gs_ldt_reload_needed) {
2118                 kvm_load_ldt(vmx->host_state.ldt_sel);
2119 #ifdef CONFIG_X86_64
2120                 load_gs_index(vmx->host_state.gs_sel);
2121 #else
2122                 loadsegment(gs, vmx->host_state.gs_sel);
2123 #endif
2124         }
2125         if (vmx->host_state.fs_reload_needed)
2126                 loadsegment(fs, vmx->host_state.fs_sel);
2127 #ifdef CONFIG_X86_64
2128         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2129                 loadsegment(ds, vmx->host_state.ds_sel);
2130                 loadsegment(es, vmx->host_state.es_sel);
2131         }
2132 #endif
2133         reload_tss();
2134 #ifdef CONFIG_X86_64
2135         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2136 #endif
2137         if (vmx->host_state.msr_host_bndcfgs)
2138                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2139         /*
2140          * If the FPU is not active (through the host task or
2141          * the guest vcpu), then restore the cr0.TS bit.
2142          */
2143         if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded)
2144                 stts();
2145         load_gdt(this_cpu_ptr(&host_gdt));
2146 }
2147
2148 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2149 {
2150         preempt_disable();
2151         __vmx_load_host_state(vmx);
2152         preempt_enable();
2153 }
2154
2155 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2156 {
2157         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2158         struct pi_desc old, new;
2159         unsigned int dest;
2160
2161         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2162                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2163                 !kvm_vcpu_apicv_active(vcpu))
2164                 return;
2165
2166         do {
2167                 old.control = new.control = pi_desc->control;
2168
2169                 /*
2170                  * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2171                  * are two possible cases:
2172                  * 1. After running 'pre_block', context switch
2173                  *    happened. For this case, 'sn' was set in
2174                  *    vmx_vcpu_put(), so we need to clear it here.
2175                  * 2. After running 'pre_block', we were blocked,
2176                  *    and woken up by some other guy. For this case,
2177                  *    we don't need to do anything, 'pi_post_block'
2178                  *    will do everything for us. However, we cannot
2179                  *    check whether it is case #1 or case #2 here
2180                  *    (maybe, not needed), so we also clear sn here,
2181                  *    I think it is not a big deal.
2182                  */
2183                 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2184                         if (vcpu->cpu != cpu) {
2185                                 dest = cpu_physical_id(cpu);
2186
2187                                 if (x2apic_enabled())
2188                                         new.ndst = dest;
2189                                 else
2190                                         new.ndst = (dest << 8) & 0xFF00;
2191                         }
2192
2193                         /* set 'NV' to 'notification vector' */
2194                         new.nv = POSTED_INTR_VECTOR;
2195                 }
2196
2197                 /* Allow posting non-urgent interrupts */
2198                 new.sn = 0;
2199         } while (cmpxchg(&pi_desc->control, old.control,
2200                         new.control) != old.control);
2201 }
2202
2203 static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2204 {
2205         vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2206         vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2207 }
2208
2209 /*
2210  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2211  * vcpu mutex is already taken.
2212  */
2213 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2214 {
2215         struct vcpu_vmx *vmx = to_vmx(vcpu);
2216         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2217         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
2218
2219         if (!vmm_exclusive)
2220                 kvm_cpu_vmxon(phys_addr);
2221         else if (!already_loaded)
2222                 loaded_vmcs_clear(vmx->loaded_vmcs);
2223
2224         if (!already_loaded) {
2225                 local_irq_disable();
2226                 crash_disable_local_vmclear(cpu);
2227
2228                 /*
2229                  * Read loaded_vmcs->cpu should be before fetching
2230                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2231                  * See the comments in __loaded_vmcs_clear().
2232                  */
2233                 smp_rmb();
2234
2235                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2236                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2237                 crash_enable_local_vmclear(cpu);
2238                 local_irq_enable();
2239         }
2240
2241         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2242                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2243                 vmcs_load(vmx->loaded_vmcs->vmcs);
2244         }
2245
2246         if (!already_loaded) {
2247                 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2248                 unsigned long sysenter_esp;
2249
2250                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2251
2252                 /*
2253                  * Linux uses per-cpu TSS and GDT, so set these when switching
2254                  * processors.
2255                  */
2256                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
2257                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
2258
2259                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2260                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2261
2262                 vmx->loaded_vmcs->cpu = cpu;
2263         }
2264
2265         /* Setup TSC multiplier */
2266         if (kvm_has_tsc_control &&
2267             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2268                 decache_tsc_multiplier(vmx);
2269
2270         vmx_vcpu_pi_load(vcpu, cpu);
2271         vmx->host_pkru = read_pkru();
2272 }
2273
2274 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2275 {
2276         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2277
2278         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2279                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2280                 !kvm_vcpu_apicv_active(vcpu))
2281                 return;
2282
2283         /* Set SN when the vCPU is preempted */
2284         if (vcpu->preempted)
2285                 pi_set_sn(pi_desc);
2286 }
2287
2288 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2289 {
2290         vmx_vcpu_pi_put(vcpu);
2291
2292         __vmx_load_host_state(to_vmx(vcpu));
2293         if (!vmm_exclusive) {
2294                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2295                 vcpu->cpu = -1;
2296                 kvm_cpu_vmxoff();
2297         }
2298 }
2299
2300 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
2301 {
2302         ulong cr0;
2303
2304         if (vcpu->fpu_active)
2305                 return;
2306         vcpu->fpu_active = 1;
2307         cr0 = vmcs_readl(GUEST_CR0);
2308         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
2309         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
2310         vmcs_writel(GUEST_CR0, cr0);
2311         update_exception_bitmap(vcpu);
2312         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
2313         if (is_guest_mode(vcpu))
2314                 vcpu->arch.cr0_guest_owned_bits &=
2315                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
2316         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2317 }
2318
2319 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2320
2321 /*
2322  * Return the cr0 value that a nested guest would read. This is a combination
2323  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2324  * its hypervisor (cr0_read_shadow).
2325  */
2326 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2327 {
2328         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2329                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2330 }
2331 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2332 {
2333         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2334                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2335 }
2336
2337 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
2338 {
2339         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2340          * set this *before* calling this function.
2341          */
2342         vmx_decache_cr0_guest_bits(vcpu);
2343         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
2344         update_exception_bitmap(vcpu);
2345         vcpu->arch.cr0_guest_owned_bits = 0;
2346         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2347         if (is_guest_mode(vcpu)) {
2348                 /*
2349                  * L1's specified read shadow might not contain the TS bit,
2350                  * so now that we turned on shadowing of this bit, we need to
2351                  * set this bit of the shadow. Like in nested_vmx_run we need
2352                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2353                  * up-to-date here because we just decached cr0.TS (and we'll
2354                  * only update vmcs12->guest_cr0 on nested exit).
2355                  */
2356                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2357                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2358                         (vcpu->arch.cr0 & X86_CR0_TS);
2359                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2360         } else
2361                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2362 }
2363
2364 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2365 {
2366         unsigned long rflags, save_rflags;
2367
2368         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2369                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2370                 rflags = vmcs_readl(GUEST_RFLAGS);
2371                 if (to_vmx(vcpu)->rmode.vm86_active) {
2372                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2373                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2374                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2375                 }
2376                 to_vmx(vcpu)->rflags = rflags;
2377         }
2378         return to_vmx(vcpu)->rflags;
2379 }
2380
2381 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2382 {
2383         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2384         to_vmx(vcpu)->rflags = rflags;
2385         if (to_vmx(vcpu)->rmode.vm86_active) {
2386                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2387                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2388         }
2389         vmcs_writel(GUEST_RFLAGS, rflags);
2390 }
2391
2392 static u32 vmx_get_pkru(struct kvm_vcpu *vcpu)
2393 {
2394         return to_vmx(vcpu)->guest_pkru;
2395 }
2396
2397 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2398 {
2399         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2400         int ret = 0;
2401
2402         if (interruptibility & GUEST_INTR_STATE_STI)
2403                 ret |= KVM_X86_SHADOW_INT_STI;
2404         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2405                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2406
2407         return ret;
2408 }
2409
2410 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2411 {
2412         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2413         u32 interruptibility = interruptibility_old;
2414
2415         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2416
2417         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2418                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2419         else if (mask & KVM_X86_SHADOW_INT_STI)
2420                 interruptibility |= GUEST_INTR_STATE_STI;
2421
2422         if ((interruptibility != interruptibility_old))
2423                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2424 }
2425
2426 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2427 {
2428         unsigned long rip;
2429
2430         rip = kvm_rip_read(vcpu);
2431         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2432         kvm_rip_write(vcpu, rip);
2433
2434         /* skipping an emulated instruction also counts */
2435         vmx_set_interrupt_shadow(vcpu, 0);
2436 }
2437
2438 /*
2439  * KVM wants to inject page-faults which it got to the guest. This function
2440  * checks whether in a nested guest, we need to inject them to L1 or L2.
2441  */
2442 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2443 {
2444         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2445
2446         if (!(vmcs12->exception_bitmap & (1u << nr)))
2447                 return 0;
2448
2449         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2450                           vmcs_read32(VM_EXIT_INTR_INFO),
2451                           vmcs_readl(EXIT_QUALIFICATION));
2452         return 1;
2453 }
2454
2455 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2456                                 bool has_error_code, u32 error_code,
2457                                 bool reinject)
2458 {
2459         struct vcpu_vmx *vmx = to_vmx(vcpu);
2460         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2461
2462         if (!reinject && is_guest_mode(vcpu) &&
2463             nested_vmx_check_exception(vcpu, nr))
2464                 return;
2465
2466         if (has_error_code) {
2467                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2468                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2469         }
2470
2471         if (vmx->rmode.vm86_active) {
2472                 int inc_eip = 0;
2473                 if (kvm_exception_is_soft(nr))
2474                         inc_eip = vcpu->arch.event_exit_inst_len;
2475                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2476                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2477                 return;
2478         }
2479
2480         if (kvm_exception_is_soft(nr)) {
2481                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2482                              vmx->vcpu.arch.event_exit_inst_len);
2483                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2484         } else
2485                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2486
2487         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2488 }
2489
2490 static bool vmx_rdtscp_supported(void)
2491 {
2492         return cpu_has_vmx_rdtscp();
2493 }
2494
2495 static bool vmx_invpcid_supported(void)
2496 {
2497         return cpu_has_vmx_invpcid() && enable_ept;
2498 }
2499
2500 /*
2501  * Swap MSR entry in host/guest MSR entry array.
2502  */
2503 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2504 {
2505         struct shared_msr_entry tmp;
2506
2507         tmp = vmx->guest_msrs[to];
2508         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2509         vmx->guest_msrs[from] = tmp;
2510 }
2511
2512 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2513 {
2514         unsigned long *msr_bitmap;
2515
2516         if (is_guest_mode(vcpu))
2517                 msr_bitmap = to_vmx(vcpu)->nested.msr_bitmap;
2518         else if (cpu_has_secondary_exec_ctrls() &&
2519                  (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
2520                   SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
2521                 if (is_long_mode(vcpu))
2522                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2523                 else
2524                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2525         } else {
2526                 if (is_long_mode(vcpu))
2527                         msr_bitmap = vmx_msr_bitmap_longmode;
2528                 else
2529                         msr_bitmap = vmx_msr_bitmap_legacy;
2530         }
2531
2532         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2533 }
2534
2535 /*
2536  * Set up the vmcs to automatically save and restore system
2537  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2538  * mode, as fiddling with msrs is very expensive.
2539  */
2540 static void setup_msrs(struct vcpu_vmx *vmx)
2541 {
2542         int save_nmsrs, index;
2543
2544         save_nmsrs = 0;
2545 #ifdef CONFIG_X86_64
2546         if (is_long_mode(&vmx->vcpu)) {
2547                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2548                 if (index >= 0)
2549                         move_msr_up(vmx, index, save_nmsrs++);
2550                 index = __find_msr_index(vmx, MSR_LSTAR);
2551                 if (index >= 0)
2552                         move_msr_up(vmx, index, save_nmsrs++);
2553                 index = __find_msr_index(vmx, MSR_CSTAR);
2554                 if (index >= 0)
2555                         move_msr_up(vmx, index, save_nmsrs++);
2556                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2557                 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2558                         move_msr_up(vmx, index, save_nmsrs++);
2559                 /*
2560                  * MSR_STAR is only needed on long mode guests, and only
2561                  * if efer.sce is enabled.
2562                  */
2563                 index = __find_msr_index(vmx, MSR_STAR);
2564                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2565                         move_msr_up(vmx, index, save_nmsrs++);
2566         }
2567 #endif
2568         index = __find_msr_index(vmx, MSR_EFER);
2569         if (index >= 0 && update_transition_efer(vmx, index))
2570                 move_msr_up(vmx, index, save_nmsrs++);
2571
2572         vmx->save_nmsrs = save_nmsrs;
2573
2574         if (cpu_has_vmx_msr_bitmap())
2575                 vmx_set_msr_bitmap(&vmx->vcpu);
2576 }
2577
2578 /*
2579  * reads and returns guest's timestamp counter "register"
2580  * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2581  * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2582  */
2583 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2584 {
2585         u64 host_tsc, tsc_offset;
2586
2587         host_tsc = rdtsc();
2588         tsc_offset = vmcs_read64(TSC_OFFSET);
2589         return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2590 }
2591
2592 /*
2593  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2594  * counter, even if a nested guest (L2) is currently running.
2595  */
2596 static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2597 {
2598         u64 tsc_offset;
2599
2600         tsc_offset = is_guest_mode(vcpu) ?
2601                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2602                 vmcs_read64(TSC_OFFSET);
2603         return host_tsc + tsc_offset;
2604 }
2605
2606 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2607 {
2608         return vmcs_read64(TSC_OFFSET);
2609 }
2610
2611 /*
2612  * writes 'offset' into guest's timestamp counter offset register
2613  */
2614 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2615 {
2616         if (is_guest_mode(vcpu)) {
2617                 /*
2618                  * We're here if L1 chose not to trap WRMSR to TSC. According
2619                  * to the spec, this should set L1's TSC; The offset that L1
2620                  * set for L2 remains unchanged, and still needs to be added
2621                  * to the newly set TSC to get L2's TSC.
2622                  */
2623                 struct vmcs12 *vmcs12;
2624                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2625                 /* recalculate vmcs02.TSC_OFFSET: */
2626                 vmcs12 = get_vmcs12(vcpu);
2627                 vmcs_write64(TSC_OFFSET, offset +
2628                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2629                          vmcs12->tsc_offset : 0));
2630         } else {
2631                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2632                                            vmcs_read64(TSC_OFFSET), offset);
2633                 vmcs_write64(TSC_OFFSET, offset);
2634         }
2635 }
2636
2637 static void vmx_adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, s64 adjustment)
2638 {
2639         u64 offset = vmcs_read64(TSC_OFFSET);
2640
2641         vmcs_write64(TSC_OFFSET, offset + adjustment);
2642         if (is_guest_mode(vcpu)) {
2643                 /* Even when running L2, the adjustment needs to apply to L1 */
2644                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2645         } else
2646                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2647                                            offset + adjustment);
2648 }
2649
2650 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2651 {
2652         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2653         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2654 }
2655
2656 /*
2657  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2658  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2659  * all guests if the "nested" module option is off, and can also be disabled
2660  * for a single guest by disabling its VMX cpuid bit.
2661  */
2662 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2663 {
2664         return nested && guest_cpuid_has_vmx(vcpu);
2665 }
2666
2667 /*
2668  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2669  * returned for the various VMX controls MSRs when nested VMX is enabled.
2670  * The same values should also be used to verify that vmcs12 control fields are
2671  * valid during nested entry from L1 to L2.
2672  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2673  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2674  * bit in the high half is on if the corresponding bit in the control field
2675  * may be on. See also vmx_control_verify().
2676  */
2677 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2678 {
2679         /*
2680          * Note that as a general rule, the high half of the MSRs (bits in
2681          * the control fields which may be 1) should be initialized by the
2682          * intersection of the underlying hardware's MSR (i.e., features which
2683          * can be supported) and the list of features we want to expose -
2684          * because they are known to be properly supported in our code.
2685          * Also, usually, the low half of the MSRs (bits which must be 1) can
2686          * be set to 0, meaning that L1 may turn off any of these bits. The
2687          * reason is that if one of these bits is necessary, it will appear
2688          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2689          * fields of vmcs01 and vmcs02, will turn these bits off - and
2690          * nested_vmx_exit_handled() will not pass related exits to L1.
2691          * These rules have exceptions below.
2692          */
2693
2694         /* pin-based controls */
2695         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2696                 vmx->nested.nested_vmx_pinbased_ctls_low,
2697                 vmx->nested.nested_vmx_pinbased_ctls_high);
2698         vmx->nested.nested_vmx_pinbased_ctls_low |=
2699                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2700         vmx->nested.nested_vmx_pinbased_ctls_high &=
2701                 PIN_BASED_EXT_INTR_MASK |
2702                 PIN_BASED_NMI_EXITING |
2703                 PIN_BASED_VIRTUAL_NMIS;
2704         vmx->nested.nested_vmx_pinbased_ctls_high |=
2705                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2706                 PIN_BASED_VMX_PREEMPTION_TIMER;
2707         if (kvm_vcpu_apicv_active(&vmx->vcpu))
2708                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2709                         PIN_BASED_POSTED_INTR;
2710
2711         /* exit controls */
2712         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2713                 vmx->nested.nested_vmx_exit_ctls_low,
2714                 vmx->nested.nested_vmx_exit_ctls_high);
2715         vmx->nested.nested_vmx_exit_ctls_low =
2716                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2717
2718         vmx->nested.nested_vmx_exit_ctls_high &=
2719 #ifdef CONFIG_X86_64
2720                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2721 #endif
2722                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2723         vmx->nested.nested_vmx_exit_ctls_high |=
2724                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2725                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2726                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2727
2728         if (kvm_mpx_supported())
2729                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2730
2731         /* We support free control of debug control saving. */
2732         vmx->nested.nested_vmx_true_exit_ctls_low =
2733                 vmx->nested.nested_vmx_exit_ctls_low &
2734                 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2735
2736         /* entry controls */
2737         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2738                 vmx->nested.nested_vmx_entry_ctls_low,
2739                 vmx->nested.nested_vmx_entry_ctls_high);
2740         vmx->nested.nested_vmx_entry_ctls_low =
2741                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2742         vmx->nested.nested_vmx_entry_ctls_high &=
2743 #ifdef CONFIG_X86_64
2744                 VM_ENTRY_IA32E_MODE |
2745 #endif
2746                 VM_ENTRY_LOAD_IA32_PAT;
2747         vmx->nested.nested_vmx_entry_ctls_high |=
2748                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2749         if (kvm_mpx_supported())
2750                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2751
2752         /* We support free control of debug control loading. */
2753         vmx->nested.nested_vmx_true_entry_ctls_low =
2754                 vmx->nested.nested_vmx_entry_ctls_low &
2755                 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2756
2757         /* cpu-based controls */
2758         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2759                 vmx->nested.nested_vmx_procbased_ctls_low,
2760                 vmx->nested.nested_vmx_procbased_ctls_high);
2761         vmx->nested.nested_vmx_procbased_ctls_low =
2762                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2763         vmx->nested.nested_vmx_procbased_ctls_high &=
2764                 CPU_BASED_VIRTUAL_INTR_PENDING |
2765                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2766                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2767                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2768                 CPU_BASED_CR3_STORE_EXITING |
2769 #ifdef CONFIG_X86_64
2770                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2771 #endif
2772                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2773                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2774                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2775                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2776                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2777         /*
2778          * We can allow some features even when not supported by the
2779          * hardware. For example, L1 can specify an MSR bitmap - and we
2780          * can use it to avoid exits to L1 - even when L0 runs L2
2781          * without MSR bitmaps.
2782          */
2783         vmx->nested.nested_vmx_procbased_ctls_high |=
2784                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2785                 CPU_BASED_USE_MSR_BITMAPS;
2786
2787         /* We support free control of CR3 access interception. */
2788         vmx->nested.nested_vmx_true_procbased_ctls_low =
2789                 vmx->nested.nested_vmx_procbased_ctls_low &
2790                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2791
2792         /* secondary cpu-based controls */
2793         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2794                 vmx->nested.nested_vmx_secondary_ctls_low,
2795                 vmx->nested.nested_vmx_secondary_ctls_high);
2796         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2797         vmx->nested.nested_vmx_secondary_ctls_high &=
2798                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2799                 SECONDARY_EXEC_RDTSCP |
2800                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2801                 SECONDARY_EXEC_ENABLE_VPID |
2802                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2803                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2804                 SECONDARY_EXEC_WBINVD_EXITING |
2805                 SECONDARY_EXEC_XSAVES;
2806
2807         if (enable_ept) {
2808                 /* nested EPT: emulate EPT also to L1 */
2809                 vmx->nested.nested_vmx_secondary_ctls_high |=
2810                         SECONDARY_EXEC_ENABLE_EPT;
2811                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2812                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2813                          VMX_EPT_INVEPT_BIT;
2814                 if (cpu_has_vmx_ept_execute_only())
2815                         vmx->nested.nested_vmx_ept_caps |=
2816                                 VMX_EPT_EXECUTE_ONLY_BIT;
2817                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2818                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2819                         VMX_EPT_EXTENT_CONTEXT_BIT;
2820         } else
2821                 vmx->nested.nested_vmx_ept_caps = 0;
2822
2823         /*
2824          * Old versions of KVM use the single-context version without
2825          * checking for support, so declare that it is supported even
2826          * though it is treated as global context.  The alternative is
2827          * not failing the single-context invvpid, and it is worse.
2828          */
2829         if (enable_vpid)
2830                 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2831                                 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |
2832                                 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
2833         else
2834                 vmx->nested.nested_vmx_vpid_caps = 0;
2835
2836         if (enable_unrestricted_guest)
2837                 vmx->nested.nested_vmx_secondary_ctls_high |=
2838                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2839
2840         /* miscellaneous data */
2841         rdmsr(MSR_IA32_VMX_MISC,
2842                 vmx->nested.nested_vmx_misc_low,
2843                 vmx->nested.nested_vmx_misc_high);
2844         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2845         vmx->nested.nested_vmx_misc_low |=
2846                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2847                 VMX_MISC_ACTIVITY_HLT;
2848         vmx->nested.nested_vmx_misc_high = 0;
2849 }
2850
2851 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2852 {
2853         /*
2854          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2855          */
2856         return ((control & high) | low) == control;
2857 }
2858
2859 static inline u64 vmx_control_msr(u32 low, u32 high)
2860 {
2861         return low | ((u64)high << 32);
2862 }
2863
2864 /* Returns 0 on success, non-0 otherwise. */
2865 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2866 {
2867         struct vcpu_vmx *vmx = to_vmx(vcpu);
2868
2869         switch (msr_index) {
2870         case MSR_IA32_VMX_BASIC:
2871                 /*
2872                  * This MSR reports some information about VMX support. We
2873                  * should return information about the VMX we emulate for the
2874                  * guest, and the VMCS structure we give it - not about the
2875                  * VMX support of the underlying hardware.
2876                  */
2877                 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2878                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2879                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2880                 break;
2881         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2882         case MSR_IA32_VMX_PINBASED_CTLS:
2883                 *pdata = vmx_control_msr(
2884                         vmx->nested.nested_vmx_pinbased_ctls_low,
2885                         vmx->nested.nested_vmx_pinbased_ctls_high);
2886                 break;
2887         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2888                 *pdata = vmx_control_msr(
2889                         vmx->nested.nested_vmx_true_procbased_ctls_low,
2890                         vmx->nested.nested_vmx_procbased_ctls_high);
2891                 break;
2892         case MSR_IA32_VMX_PROCBASED_CTLS:
2893                 *pdata = vmx_control_msr(
2894                         vmx->nested.nested_vmx_procbased_ctls_low,
2895                         vmx->nested.nested_vmx_procbased_ctls_high);
2896                 break;
2897         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2898                 *pdata = vmx_control_msr(
2899                         vmx->nested.nested_vmx_true_exit_ctls_low,
2900                         vmx->nested.nested_vmx_exit_ctls_high);
2901                 break;
2902         case MSR_IA32_VMX_EXIT_CTLS:
2903                 *pdata = vmx_control_msr(
2904                         vmx->nested.nested_vmx_exit_ctls_low,
2905                         vmx->nested.nested_vmx_exit_ctls_high);
2906                 break;
2907         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2908                 *pdata = vmx_control_msr(
2909                         vmx->nested.nested_vmx_true_entry_ctls_low,
2910                         vmx->nested.nested_vmx_entry_ctls_high);
2911                 break;
2912         case MSR_IA32_VMX_ENTRY_CTLS:
2913                 *pdata = vmx_control_msr(
2914                         vmx->nested.nested_vmx_entry_ctls_low,
2915                         vmx->nested.nested_vmx_entry_ctls_high);
2916                 break;
2917         case MSR_IA32_VMX_MISC:
2918                 *pdata = vmx_control_msr(
2919                         vmx->nested.nested_vmx_misc_low,
2920                         vmx->nested.nested_vmx_misc_high);
2921                 break;
2922         /*
2923          * These MSRs specify bits which the guest must keep fixed (on or off)
2924          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2925          * We picked the standard core2 setting.
2926          */
2927 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2928 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2929         case MSR_IA32_VMX_CR0_FIXED0:
2930                 *pdata = VMXON_CR0_ALWAYSON;
2931                 break;
2932         case MSR_IA32_VMX_CR0_FIXED1:
2933                 *pdata = -1ULL;
2934                 break;
2935         case MSR_IA32_VMX_CR4_FIXED0:
2936                 *pdata = VMXON_CR4_ALWAYSON;
2937                 break;
2938         case MSR_IA32_VMX_CR4_FIXED1:
2939                 *pdata = -1ULL;
2940                 break;
2941         case MSR_IA32_VMX_VMCS_ENUM:
2942                 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2943                 break;
2944         case MSR_IA32_VMX_PROCBASED_CTLS2:
2945                 *pdata = vmx_control_msr(
2946                         vmx->nested.nested_vmx_secondary_ctls_low,
2947                         vmx->nested.nested_vmx_secondary_ctls_high);
2948                 break;
2949         case MSR_IA32_VMX_EPT_VPID_CAP:
2950                 *pdata = vmx->nested.nested_vmx_ept_caps |
2951                         ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
2952                 break;
2953         default:
2954                 return 1;
2955         }
2956
2957         return 0;
2958 }
2959
2960 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
2961                                                  uint64_t val)
2962 {
2963         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
2964
2965         return !(val & ~valid_bits);
2966 }
2967
2968 /*
2969  * Reads an msr value (of 'msr_index') into 'pdata'.
2970  * Returns 0 on success, non-0 otherwise.
2971  * Assumes vcpu_load() was already called.
2972  */
2973 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2974 {
2975         struct shared_msr_entry *msr;
2976
2977         switch (msr_info->index) {
2978 #ifdef CONFIG_X86_64
2979         case MSR_FS_BASE:
2980                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
2981                 break;
2982         case MSR_GS_BASE:
2983                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
2984                 break;
2985         case MSR_KERNEL_GS_BASE:
2986                 vmx_load_host_state(to_vmx(vcpu));
2987                 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2988                 break;
2989 #endif
2990         case MSR_EFER:
2991                 return kvm_get_msr_common(vcpu, msr_info);
2992         case MSR_IA32_TSC:
2993                 msr_info->data = guest_read_tsc(vcpu);
2994                 break;
2995         case MSR_IA32_SYSENTER_CS:
2996                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
2997                 break;
2998         case MSR_IA32_SYSENTER_EIP:
2999                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
3000                 break;
3001         case MSR_IA32_SYSENTER_ESP:
3002                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
3003                 break;
3004         case MSR_IA32_BNDCFGS:
3005                 if (!kvm_mpx_supported())
3006                         return 1;
3007                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
3008                 break;
3009         case MSR_IA32_MCG_EXT_CTL:
3010                 if (!msr_info->host_initiated &&
3011                     !(to_vmx(vcpu)->msr_ia32_feature_control &
3012                       FEATURE_CONTROL_LMCE))
3013                         return 1;
3014                 msr_info->data = vcpu->arch.mcg_ext_ctl;
3015                 break;
3016         case MSR_IA32_FEATURE_CONTROL:
3017                 msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control;
3018                 break;
3019         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3020                 if (!nested_vmx_allowed(vcpu))
3021                         return 1;
3022                 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
3023         case MSR_IA32_XSS:
3024                 if (!vmx_xsaves_supported())
3025                         return 1;
3026                 msr_info->data = vcpu->arch.ia32_xss;
3027                 break;
3028         case MSR_TSC_AUX:
3029                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3030                         return 1;
3031                 /* Otherwise falls through */
3032         default:
3033                 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3034                 if (msr) {
3035                         msr_info->data = msr->data;
3036                         break;
3037                 }
3038                 return kvm_get_msr_common(vcpu, msr_info);
3039         }
3040
3041         return 0;
3042 }
3043
3044 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3045
3046 /*
3047  * Writes msr value into into the appropriate "register".
3048  * Returns 0 on success, non-0 otherwise.
3049  * Assumes vcpu_load() was already called.
3050  */
3051 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3052 {
3053         struct vcpu_vmx *vmx = to_vmx(vcpu);
3054         struct shared_msr_entry *msr;
3055         int ret = 0;
3056         u32 msr_index = msr_info->index;
3057         u64 data = msr_info->data;
3058
3059         switch (msr_index) {
3060         case MSR_EFER:
3061                 ret = kvm_set_msr_common(vcpu, msr_info);
3062                 break;
3063 #ifdef CONFIG_X86_64
3064         case MSR_FS_BASE:
3065                 vmx_segment_cache_clear(vmx);
3066                 vmcs_writel(GUEST_FS_BASE, data);
3067                 break;
3068         case MSR_GS_BASE:
3069                 vmx_segment_cache_clear(vmx);
3070                 vmcs_writel(GUEST_GS_BASE, data);
3071                 break;
3072         case MSR_KERNEL_GS_BASE:
3073                 vmx_load_host_state(vmx);
3074                 vmx->msr_guest_kernel_gs_base = data;
3075                 break;
3076 #endif
3077         case MSR_IA32_SYSENTER_CS:
3078                 vmcs_write32(GUEST_SYSENTER_CS, data);
3079                 break;
3080         case MSR_IA32_SYSENTER_EIP:
3081                 vmcs_writel(GUEST_SYSENTER_EIP, data);
3082                 break;
3083         case MSR_IA32_SYSENTER_ESP:
3084                 vmcs_writel(GUEST_SYSENTER_ESP, data);
3085                 break;
3086         case MSR_IA32_BNDCFGS:
3087                 if (!kvm_mpx_supported())
3088                         return 1;
3089                 vmcs_write64(GUEST_BNDCFGS, data);
3090                 break;
3091         case MSR_IA32_TSC:
3092                 kvm_write_tsc(vcpu, msr_info);
3093                 break;
3094         case MSR_IA32_CR_PAT:
3095                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3096                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3097                                 return 1;
3098                         vmcs_write64(GUEST_IA32_PAT, data);
3099                         vcpu->arch.pat = data;
3100                         break;
3101                 }
3102                 ret = kvm_set_msr_common(vcpu, msr_info);
3103                 break;
3104         case MSR_IA32_TSC_ADJUST:
3105                 ret = kvm_set_msr_common(vcpu, msr_info);
3106                 break;
3107         case MSR_IA32_MCG_EXT_CTL:
3108                 if ((!msr_info->host_initiated &&
3109                      !(to_vmx(vcpu)->msr_ia32_feature_control &
3110                        FEATURE_CONTROL_LMCE)) ||
3111                     (data & ~MCG_EXT_CTL_LMCE_EN))
3112                         return 1;
3113                 vcpu->arch.mcg_ext_ctl = data;
3114                 break;
3115         case MSR_IA32_FEATURE_CONTROL:
3116                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3117                     (to_vmx(vcpu)->msr_ia32_feature_control &
3118                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3119                         return 1;
3120                 vmx->msr_ia32_feature_control = data;
3121                 if (msr_info->host_initiated && data == 0)
3122                         vmx_leave_nested(vcpu);
3123                 break;
3124         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3125                 return 1; /* they are read-only */
3126         case MSR_IA32_XSS:
3127                 if (!vmx_xsaves_supported())
3128                         return 1;
3129                 /*
3130                  * The only supported bit as of Skylake is bit 8, but
3131                  * it is not supported on KVM.
3132                  */
3133                 if (data != 0)
3134                         return 1;
3135                 vcpu->arch.ia32_xss = data;
3136                 if (vcpu->arch.ia32_xss != host_xss)
3137                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3138                                 vcpu->arch.ia32_xss, host_xss);
3139                 else
3140                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3141                 break;
3142         case MSR_TSC_AUX:
3143                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3144                         return 1;
3145                 /* Check reserved bit, higher 32 bits should be zero */
3146                 if ((data >> 32) != 0)
3147                         return 1;
3148                 /* Otherwise falls through */
3149         default:
3150                 msr = find_msr_entry(vmx, msr_index);
3151                 if (msr) {
3152                         u64 old_msr_data = msr->data;
3153                         msr->data = data;
3154                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3155                                 preempt_disable();
3156                                 ret = kvm_set_shared_msr(msr->index, msr->data,
3157                                                          msr->mask);
3158                                 preempt_enable();
3159                                 if (ret)
3160                                         msr->data = old_msr_data;
3161                         }
3162                         break;
3163                 }
3164                 ret = kvm_set_msr_common(vcpu, msr_info);
3165         }
3166
3167         return ret;
3168 }
3169
3170 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3171 {
3172         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3173         switch (reg) {
3174         case VCPU_REGS_RSP:
3175                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3176                 break;
3177         case VCPU_REGS_RIP:
3178                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3179                 break;
3180         case VCPU_EXREG_PDPTR:
3181                 if (enable_ept)
3182                         ept_save_pdptrs(vcpu);
3183                 break;
3184         default:
3185                 break;
3186         }
3187 }
3188
3189 static __init int cpu_has_kvm_support(void)
3190 {
3191         return cpu_has_vmx();
3192 }
3193
3194 static __init int vmx_disabled_by_bios(void)
3195 {
3196         u64 msr;
3197
3198         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3199         if (msr & FEATURE_CONTROL_LOCKED) {
3200                 /* launched w/ TXT and VMX disabled */
3201                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3202                         && tboot_enabled())
3203                         return 1;
3204                 /* launched w/o TXT and VMX only enabled w/ TXT */
3205                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3206                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3207                         && !tboot_enabled()) {
3208                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3209                                 "activate TXT before enabling KVM\n");
3210                         return 1;
3211                 }
3212                 /* launched w/o TXT and VMX disabled */
3213                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3214                         && !tboot_enabled())
3215                         return 1;
3216         }
3217
3218         return 0;
3219 }
3220
3221 static void kvm_cpu_vmxon(u64 addr)
3222 {
3223         intel_pt_handle_vmx(1);
3224
3225         asm volatile (ASM_VMX_VMXON_RAX
3226                         : : "a"(&addr), "m"(addr)
3227                         : "memory", "cc");
3228 }
3229
3230 static int hardware_enable(void)
3231 {
3232         int cpu = raw_smp_processor_id();
3233         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3234         u64 old, test_bits;
3235
3236         if (cr4_read_shadow() & X86_CR4_VMXE)
3237                 return -EBUSY;
3238
3239         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3240         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3241         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3242
3243         /*
3244          * Now we can enable the vmclear operation in kdump
3245          * since the loaded_vmcss_on_cpu list on this cpu
3246          * has been initialized.
3247          *
3248          * Though the cpu is not in VMX operation now, there
3249          * is no problem to enable the vmclear operation
3250          * for the loaded_vmcss_on_cpu list is empty!
3251          */
3252         crash_enable_local_vmclear(cpu);
3253
3254         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3255
3256         test_bits = FEATURE_CONTROL_LOCKED;
3257         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3258         if (tboot_enabled())
3259                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3260
3261         if ((old & test_bits) != test_bits) {
3262                 /* enable and lock */
3263                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3264         }
3265         cr4_set_bits(X86_CR4_VMXE);
3266
3267         if (vmm_exclusive) {
3268                 kvm_cpu_vmxon(phys_addr);
3269                 ept_sync_global();
3270         }
3271
3272         native_store_gdt(this_cpu_ptr(&host_gdt));
3273
3274         return 0;
3275 }
3276
3277 static void vmclear_local_loaded_vmcss(void)
3278 {
3279         int cpu = raw_smp_processor_id();
3280         struct loaded_vmcs *v, *n;
3281
3282         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3283                                  loaded_vmcss_on_cpu_link)
3284                 __loaded_vmcs_clear(v);
3285 }
3286
3287
3288 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3289  * tricks.
3290  */
3291 static void kvm_cpu_vmxoff(void)
3292 {
3293         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3294
3295         intel_pt_handle_vmx(0);
3296 }
3297
3298 static void hardware_disable(void)
3299 {
3300         if (vmm_exclusive) {
3301                 vmclear_local_loaded_vmcss();
3302                 kvm_cpu_vmxoff();
3303         }
3304         cr4_clear_bits(X86_CR4_VMXE);
3305 }
3306
3307 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3308                                       u32 msr, u32 *result)
3309 {
3310         u32 vmx_msr_low, vmx_msr_high;
3311         u32 ctl = ctl_min | ctl_opt;
3312
3313         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3314
3315         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3316         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3317
3318         /* Ensure minimum (required) set of control bits are supported. */
3319         if (ctl_min & ~ctl)
3320                 return -EIO;
3321
3322         *result = ctl;
3323         return 0;
3324 }
3325
3326 static __init bool allow_1_setting(u32 msr, u32 ctl)
3327 {
3328         u32 vmx_msr_low, vmx_msr_high;
3329
3330         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3331         return vmx_msr_high & ctl;
3332 }
3333
3334 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3335 {
3336         u32 vmx_msr_low, vmx_msr_high;
3337         u32 min, opt, min2, opt2;
3338         u32 _pin_based_exec_control = 0;
3339         u32 _cpu_based_exec_control = 0;
3340         u32 _cpu_based_2nd_exec_control = 0;
3341         u32 _vmexit_control = 0;
3342         u32 _vmentry_control = 0;
3343
3344         min = CPU_BASED_HLT_EXITING |
3345 #ifdef CONFIG_X86_64
3346               CPU_BASED_CR8_LOAD_EXITING |
3347               CPU_BASED_CR8_STORE_EXITING |
3348 #endif
3349               CPU_BASED_CR3_LOAD_EXITING |
3350               CPU_BASED_CR3_STORE_EXITING |
3351               CPU_BASED_USE_IO_BITMAPS |
3352               CPU_BASED_MOV_DR_EXITING |
3353               CPU_BASED_USE_TSC_OFFSETING |
3354               CPU_BASED_MWAIT_EXITING |
3355               CPU_BASED_MONITOR_EXITING |
3356               CPU_BASED_INVLPG_EXITING |
3357               CPU_BASED_RDPMC_EXITING;
3358
3359         opt = CPU_BASED_TPR_SHADOW |
3360               CPU_BASED_USE_MSR_BITMAPS |
3361               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3362         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3363                                 &_cpu_based_exec_control) < 0)
3364                 return -EIO;
3365 #ifdef CONFIG_X86_64
3366         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3367                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3368                                            ~CPU_BASED_CR8_STORE_EXITING;
3369 #endif
3370         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3371                 min2 = 0;
3372                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3373                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3374                         SECONDARY_EXEC_WBINVD_EXITING |
3375                         SECONDARY_EXEC_ENABLE_VPID |
3376                         SECONDARY_EXEC_ENABLE_EPT |
3377                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3378                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3379                         SECONDARY_EXEC_RDTSCP |
3380                         SECONDARY_EXEC_ENABLE_INVPCID |
3381                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3382                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3383                         SECONDARY_EXEC_SHADOW_VMCS |
3384                         SECONDARY_EXEC_XSAVES |
3385                         SECONDARY_EXEC_ENABLE_PML |
3386                         SECONDARY_EXEC_TSC_SCALING;
3387                 if (adjust_vmx_controls(min2, opt2,
3388                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3389                                         &_cpu_based_2nd_exec_control) < 0)
3390                         return -EIO;
3391         }
3392 #ifndef CONFIG_X86_64
3393         if (!(_cpu_based_2nd_exec_control &
3394                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3395                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3396 #endif
3397
3398         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3399                 _cpu_based_2nd_exec_control &= ~(
3400                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3401                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3402                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3403
3404         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3405                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3406                    enabled */
3407                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3408                                              CPU_BASED_CR3_STORE_EXITING |
3409                                              CPU_BASED_INVLPG_EXITING);
3410                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3411                       vmx_capability.ept, vmx_capability.vpid);
3412         }
3413
3414         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
3415 #ifdef CONFIG_X86_64
3416         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3417 #endif
3418         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3419                 VM_EXIT_CLEAR_BNDCFGS;
3420         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3421                                 &_vmexit_control) < 0)
3422                 return -EIO;
3423
3424         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3425         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
3426                  PIN_BASED_VMX_PREEMPTION_TIMER;
3427         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3428                                 &_pin_based_exec_control) < 0)
3429                 return -EIO;
3430
3431         if (cpu_has_broken_vmx_preemption_timer())
3432                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3433         if (!(_cpu_based_2nd_exec_control &
3434                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
3435                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3436
3437         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3438         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3439         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3440                                 &_vmentry_control) < 0)
3441                 return -EIO;
3442
3443         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3444
3445         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3446         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3447                 return -EIO;
3448
3449 #ifdef CONFIG_X86_64
3450         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3451         if (vmx_msr_high & (1u<<16))
3452                 return -EIO;
3453 #endif
3454
3455         /* Require Write-Back (WB) memory type for VMCS accesses. */
3456         if (((vmx_msr_high >> 18) & 15) != 6)
3457                 return -EIO;
3458
3459         vmcs_conf->size = vmx_msr_high & 0x1fff;
3460         vmcs_conf->order = get_order(vmcs_config.size);
3461         vmcs_conf->revision_id = vmx_msr_low;
3462
3463         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3464         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3465         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3466         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3467         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3468
3469         cpu_has_load_ia32_efer =
3470                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3471                                 VM_ENTRY_LOAD_IA32_EFER)
3472                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3473                                    VM_EXIT_LOAD_IA32_EFER);
3474
3475         cpu_has_load_perf_global_ctrl =
3476                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3477                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3478                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3479                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3480
3481         /*
3482          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3483          * but due to errata below it can't be used. Workaround is to use
3484          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3485          *
3486          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3487          *
3488          * AAK155             (model 26)
3489          * AAP115             (model 30)
3490          * AAT100             (model 37)
3491          * BC86,AAY89,BD102   (model 44)
3492          * BA97               (model 46)
3493          *
3494          */
3495         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3496                 switch (boot_cpu_data.x86_model) {
3497                 case 26:
3498                 case 30:
3499                 case 37:
3500                 case 44:
3501                 case 46:
3502                         cpu_has_load_perf_global_ctrl = false;
3503                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3504                                         "does not work properly. Using workaround\n");
3505                         break;
3506                 default:
3507                         break;
3508                 }
3509         }
3510
3511         if (boot_cpu_has(X86_FEATURE_XSAVES))
3512                 rdmsrl(MSR_IA32_XSS, host_xss);
3513
3514         return 0;
3515 }
3516
3517 static struct vmcs *alloc_vmcs_cpu(int cpu)
3518 {
3519         int node = cpu_to_node(cpu);
3520         struct page *pages;
3521         struct vmcs *vmcs;
3522
3523         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3524         if (!pages)
3525                 return NULL;
3526         vmcs = page_address(pages);
3527         memset(vmcs, 0, vmcs_config.size);
3528         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3529         return vmcs;
3530 }
3531
3532 static struct vmcs *alloc_vmcs(void)
3533 {
3534         return alloc_vmcs_cpu(raw_smp_processor_id());
3535 }
3536
3537 static void free_vmcs(struct vmcs *vmcs)
3538 {
3539         free_pages((unsigned long)vmcs, vmcs_config.order);
3540 }
3541
3542 /*
3543  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3544  */
3545 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3546 {
3547         if (!loaded_vmcs->vmcs)
3548                 return;
3549         loaded_vmcs_clear(loaded_vmcs);
3550         free_vmcs(loaded_vmcs->vmcs);
3551         loaded_vmcs->vmcs = NULL;
3552 }
3553
3554 static void free_kvm_area(void)
3555 {
3556         int cpu;
3557
3558         for_each_possible_cpu(cpu) {
3559                 free_vmcs(per_cpu(vmxarea, cpu));
3560                 per_cpu(vmxarea, cpu) = NULL;
3561         }
3562 }
3563
3564 static void init_vmcs_shadow_fields(void)
3565 {
3566         int i, j;
3567
3568         /* No checks for read only fields yet */
3569
3570         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3571                 switch (shadow_read_write_fields[i]) {
3572                 case GUEST_BNDCFGS:
3573                         if (!kvm_mpx_supported())
3574                                 continue;
3575                         break;
3576                 default:
3577                         break;
3578                 }
3579
3580                 if (j < i)
3581                         shadow_read_write_fields[j] =
3582                                 shadow_read_write_fields[i];
3583                 j++;
3584         }
3585         max_shadow_read_write_fields = j;
3586
3587         /* shadowed fields guest access without vmexit */
3588         for (i = 0; i < max_shadow_read_write_fields; i++) {
3589                 clear_bit(shadow_read_write_fields[i],
3590                           vmx_vmwrite_bitmap);
3591                 clear_bit(shadow_read_write_fields[i],
3592                           vmx_vmread_bitmap);
3593         }
3594         for (i = 0; i < max_shadow_read_only_fields; i++)
3595                 clear_bit(shadow_read_only_fields[i],
3596                           vmx_vmread_bitmap);
3597 }
3598
3599 static __init int alloc_kvm_area(void)
3600 {
3601         int cpu;
3602
3603         for_each_possible_cpu(cpu) {
3604                 struct vmcs *vmcs;
3605
3606                 vmcs = alloc_vmcs_cpu(cpu);
3607                 if (!vmcs) {
3608                         free_kvm_area();
3609                         return -ENOMEM;
3610                 }
3611
3612                 per_cpu(vmxarea, cpu) = vmcs;
3613         }
3614         return 0;
3615 }
3616
3617 static bool emulation_required(struct kvm_vcpu *vcpu)
3618 {
3619         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3620 }
3621
3622 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3623                 struct kvm_segment *save)
3624 {
3625         if (!emulate_invalid_guest_state) {
3626                 /*
3627                  * CS and SS RPL should be equal during guest entry according
3628                  * to VMX spec, but in reality it is not always so. Since vcpu
3629                  * is in the middle of the transition from real mode to
3630                  * protected mode it is safe to assume that RPL 0 is a good
3631                  * default value.
3632                  */
3633                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3634                         save->selector &= ~SEGMENT_RPL_MASK;
3635                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3636                 save->s = 1;
3637         }
3638         vmx_set_segment(vcpu, save, seg);
3639 }
3640
3641 static void enter_pmode(struct kvm_vcpu *vcpu)
3642 {
3643         unsigned long flags;
3644         struct vcpu_vmx *vmx = to_vmx(vcpu);
3645
3646         /*
3647          * Update real mode segment cache. It may be not up-to-date if sement
3648          * register was written while vcpu was in a guest mode.
3649          */
3650         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3651         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3652         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3653         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3654         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3655         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3656
3657         vmx->rmode.vm86_active = 0;
3658
3659         vmx_segment_cache_clear(vmx);
3660
3661         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3662
3663         flags = vmcs_readl(GUEST_RFLAGS);
3664         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3665         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3666         vmcs_writel(GUEST_RFLAGS, flags);
3667
3668         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3669                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3670
3671         update_exception_bitmap(vcpu);
3672
3673         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3674         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3675         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3676         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3677         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3678         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3679 }
3680
3681 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3682 {
3683         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3684         struct kvm_segment var = *save;
3685
3686         var.dpl = 0x3;
3687         if (seg == VCPU_SREG_CS)
3688                 var.type = 0x3;
3689
3690         if (!emulate_invalid_guest_state) {
3691                 var.selector = var.base >> 4;
3692                 var.base = var.base & 0xffff0;
3693                 var.limit = 0xffff;
3694                 var.g = 0;
3695                 var.db = 0;
3696                 var.present = 1;
3697                 var.s = 1;
3698                 var.l = 0;
3699                 var.unusable = 0;
3700                 var.type = 0x3;
3701                 var.avl = 0;
3702                 if (save->base & 0xf)
3703                         printk_once(KERN_WARNING "kvm: segment base is not "
3704                                         "paragraph aligned when entering "
3705                                         "protected mode (seg=%d)", seg);
3706         }
3707
3708         vmcs_write16(sf->selector, var.selector);
3709         vmcs_write32(sf->base, var.base);
3710         vmcs_write32(sf->limit, var.limit);
3711         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3712 }
3713
3714 static void enter_rmode(struct kvm_vcpu *vcpu)
3715 {
3716         unsigned long flags;
3717         struct vcpu_vmx *vmx = to_vmx(vcpu);
3718
3719         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3720         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3721         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3722         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3723         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3724         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3725         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3726
3727         vmx->rmode.vm86_active = 1;
3728
3729         /*
3730          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3731          * vcpu. Warn the user that an update is overdue.
3732          */
3733         if (!vcpu->kvm->arch.tss_addr)
3734                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3735                              "called before entering vcpu\n");
3736
3737         vmx_segment_cache_clear(vmx);
3738
3739         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3740         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3741         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3742
3743         flags = vmcs_readl(GUEST_RFLAGS);
3744         vmx->rmode.save_rflags = flags;
3745
3746         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3747
3748         vmcs_writel(GUEST_RFLAGS, flags);
3749         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3750         update_exception_bitmap(vcpu);
3751
3752         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3753         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3754         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3755         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3756         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3757         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3758
3759         kvm_mmu_reset_context(vcpu);
3760 }
3761
3762 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3763 {
3764         struct vcpu_vmx *vmx = to_vmx(vcpu);
3765         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3766
3767         if (!msr)
3768                 return;
3769
3770         /*
3771          * Force kernel_gs_base reloading before EFER changes, as control
3772          * of this msr depends on is_long_mode().
3773          */
3774         vmx_load_host_state(to_vmx(vcpu));
3775         vcpu->arch.efer = efer;
3776         if (efer & EFER_LMA) {
3777                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3778                 msr->data = efer;
3779         } else {
3780                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3781
3782                 msr->data = efer & ~EFER_LME;
3783         }
3784         setup_msrs(vmx);
3785 }
3786
3787 #ifdef CONFIG_X86_64
3788
3789 static void enter_lmode(struct kvm_vcpu *vcpu)
3790 {
3791         u32 guest_tr_ar;
3792
3793         vmx_segment_cache_clear(to_vmx(vcpu));
3794
3795         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3796         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
3797                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3798                                      __func__);
3799                 vmcs_write32(GUEST_TR_AR_BYTES,
3800                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3801                              | VMX_AR_TYPE_BUSY_64_TSS);
3802         }
3803         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3804 }
3805
3806 static void exit_lmode(struct kvm_vcpu *vcpu)
3807 {
3808         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3809         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3810 }
3811
3812 #endif
3813
3814 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
3815 {
3816         vpid_sync_context(vpid);
3817         if (enable_ept) {
3818                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3819                         return;
3820                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3821         }
3822 }
3823
3824 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3825 {
3826         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
3827 }
3828
3829 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3830 {
3831         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3832
3833         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3834         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3835 }
3836
3837 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3838 {
3839         if (enable_ept && is_paging(vcpu))
3840                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3841         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3842 }
3843
3844 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3845 {
3846         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3847
3848         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3849         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3850 }
3851
3852 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3853 {
3854         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3855
3856         if (!test_bit(VCPU_EXREG_PDPTR,
3857                       (unsigned long *)&vcpu->arch.regs_dirty))
3858                 return;
3859
3860         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3861                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3862                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3863                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3864                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3865         }
3866 }
3867
3868 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3869 {
3870         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3871
3872         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3873                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3874                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3875                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3876                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3877         }
3878
3879         __set_bit(VCPU_EXREG_PDPTR,
3880                   (unsigned long *)&vcpu->arch.regs_avail);
3881         __set_bit(VCPU_EXREG_PDPTR,
3882                   (unsigned long *)&vcpu->arch.regs_dirty);
3883 }
3884
3885 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3886
3887 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3888                                         unsigned long cr0,
3889                                         struct kvm_vcpu *vcpu)
3890 {
3891         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3892                 vmx_decache_cr3(vcpu);
3893         if (!(cr0 & X86_CR0_PG)) {
3894                 /* From paging/starting to nonpaging */
3895                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3896                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3897                              (CPU_BASED_CR3_LOAD_EXITING |
3898                               CPU_BASED_CR3_STORE_EXITING));
3899                 vcpu->arch.cr0 = cr0;
3900                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3901         } else if (!is_paging(vcpu)) {
3902                 /* From nonpaging to paging */
3903                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3904                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3905                              ~(CPU_BASED_CR3_LOAD_EXITING |
3906                                CPU_BASED_CR3_STORE_EXITING));
3907                 vcpu->arch.cr0 = cr0;
3908                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3909         }
3910
3911         if (!(cr0 & X86_CR0_WP))
3912                 *hw_cr0 &= ~X86_CR0_WP;
3913 }
3914
3915 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3916 {
3917         struct vcpu_vmx *vmx = to_vmx(vcpu);
3918         unsigned long hw_cr0;
3919
3920         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3921         if (enable_unrestricted_guest)
3922                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3923         else {
3924                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3925
3926                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3927                         enter_pmode(vcpu);
3928
3929                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3930                         enter_rmode(vcpu);
3931         }
3932
3933 #ifdef CONFIG_X86_64
3934         if (vcpu->arch.efer & EFER_LME) {
3935                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3936                         enter_lmode(vcpu);
3937                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3938                         exit_lmode(vcpu);
3939         }
3940 #endif
3941
3942         if (enable_ept)
3943                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3944
3945         if (!vcpu->fpu_active)
3946                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3947
3948         vmcs_writel(CR0_READ_SHADOW, cr0);
3949         vmcs_writel(GUEST_CR0, hw_cr0);
3950         vcpu->arch.cr0 = cr0;
3951
3952         /* depends on vcpu->arch.cr0 to be set to a new value */
3953         vmx->emulation_required = emulation_required(vcpu);
3954 }
3955
3956 static u64 construct_eptp(unsigned long root_hpa)
3957 {
3958         u64 eptp;
3959
3960         /* TODO write the value reading from MSR */
3961         eptp = VMX_EPT_DEFAULT_MT |
3962                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3963         if (enable_ept_ad_bits)
3964                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3965         eptp |= (root_hpa & PAGE_MASK);
3966
3967         return eptp;
3968 }
3969
3970 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3971 {
3972         unsigned long guest_cr3;
3973         u64 eptp;
3974
3975         guest_cr3 = cr3;
3976         if (enable_ept) {
3977                 eptp = construct_eptp(cr3);
3978                 vmcs_write64(EPT_POINTER, eptp);
3979                 if (is_paging(vcpu) || is_guest_mode(vcpu))
3980                         guest_cr3 = kvm_read_cr3(vcpu);
3981                 else
3982                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3983                 ept_load_pdptrs(vcpu);
3984         }
3985
3986         vmx_flush_tlb(vcpu);
3987         vmcs_writel(GUEST_CR3, guest_cr3);
3988 }
3989
3990 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3991 {
3992         /*
3993          * Pass through host's Machine Check Enable value to hw_cr4, which
3994          * is in force while we are in guest mode.  Do not let guests control
3995          * this bit, even if host CR4.MCE == 0.
3996          */
3997         unsigned long hw_cr4 =
3998                 (cr4_read_shadow() & X86_CR4_MCE) |
3999                 (cr4 & ~X86_CR4_MCE) |
4000                 (to_vmx(vcpu)->rmode.vm86_active ?
4001                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
4002
4003         if (cr4 & X86_CR4_VMXE) {
4004                 /*
4005                  * To use VMXON (and later other VMX instructions), a guest
4006                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
4007                  * So basically the check on whether to allow nested VMX
4008                  * is here.
4009                  */
4010                 if (!nested_vmx_allowed(vcpu))
4011                         return 1;
4012         }
4013         if (to_vmx(vcpu)->nested.vmxon &&
4014             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
4015                 return 1;
4016
4017         vcpu->arch.cr4 = cr4;
4018         if (enable_ept) {
4019                 if (!is_paging(vcpu)) {
4020                         hw_cr4 &= ~X86_CR4_PAE;
4021                         hw_cr4 |= X86_CR4_PSE;
4022                 } else if (!(cr4 & X86_CR4_PAE)) {
4023                         hw_cr4 &= ~X86_CR4_PAE;
4024                 }
4025         }
4026
4027         if (!enable_unrestricted_guest && !is_paging(vcpu))
4028                 /*
4029                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4030                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
4031                  * to be manually disabled when guest switches to non-paging
4032                  * mode.
4033                  *
4034                  * If !enable_unrestricted_guest, the CPU is always running
4035                  * with CR0.PG=1 and CR4 needs to be modified.
4036                  * If enable_unrestricted_guest, the CPU automatically
4037                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4038                  */
4039                 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
4040
4041         vmcs_writel(CR4_READ_SHADOW, cr4);
4042         vmcs_writel(GUEST_CR4, hw_cr4);
4043         return 0;
4044 }
4045
4046 static void vmx_get_segment(struct kvm_vcpu *vcpu,
4047                             struct kvm_segment *var, int seg)
4048 {
4049         struct vcpu_vmx *vmx = to_vmx(vcpu);
4050         u32 ar;
4051
4052         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4053                 *var = vmx->rmode.segs[seg];
4054                 if (seg == VCPU_SREG_TR
4055                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
4056                         return;
4057                 var->base = vmx_read_guest_seg_base(vmx, seg);
4058                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4059                 return;
4060         }
4061         var->base = vmx_read_guest_seg_base(vmx, seg);
4062         var->limit = vmx_read_guest_seg_limit(vmx, seg);
4063         var->selector = vmx_read_guest_seg_selector(vmx, seg);
4064         ar = vmx_read_guest_seg_ar(vmx, seg);
4065         var->unusable = (ar >> 16) & 1;
4066         var->type = ar & 15;
4067         var->s = (ar >> 4) & 1;
4068         var->dpl = (ar >> 5) & 3;
4069         /*
4070          * Some userspaces do not preserve unusable property. Since usable
4071          * segment has to be present according to VMX spec we can use present
4072          * property to amend userspace bug by making unusable segment always
4073          * nonpresent. vmx_segment_access_rights() already marks nonpresent
4074          * segment as unusable.
4075          */
4076         var->present = !var->unusable;
4077         var->avl = (ar >> 12) & 1;
4078         var->l = (ar >> 13) & 1;
4079         var->db = (ar >> 14) & 1;
4080         var->g = (ar >> 15) & 1;
4081 }
4082
4083 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
4084 {
4085         struct kvm_segment s;
4086
4087         if (to_vmx(vcpu)->rmode.vm86_active) {
4088                 vmx_get_segment(vcpu, &s, seg);
4089                 return s.base;
4090         }
4091         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
4092 }
4093
4094 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
4095 {
4096         struct vcpu_vmx *vmx = to_vmx(vcpu);
4097
4098         if (unlikely(vmx->rmode.vm86_active))
4099                 return 0;
4100         else {
4101                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4102                 return VMX_AR_DPL(ar);
4103         }
4104 }
4105
4106 static u32 vmx_segment_access_rights(struct kvm_segment *var)
4107 {
4108         u32 ar;
4109
4110         if (var->unusable || !var->present)
4111                 ar = 1 << 16;
4112         else {
4113                 ar = var->type & 15;
4114                 ar |= (var->s & 1) << 4;
4115                 ar |= (var->dpl & 3) << 5;
4116                 ar |= (var->present & 1) << 7;
4117                 ar |= (var->avl & 1) << 12;
4118                 ar |= (var->l & 1) << 13;
4119                 ar |= (var->db & 1) << 14;
4120                 ar |= (var->g & 1) << 15;
4121         }
4122
4123         return ar;
4124 }
4125
4126 static void vmx_set_segment(struct kvm_vcpu *vcpu,
4127                             struct kvm_segment *var, int seg)
4128 {
4129         struct vcpu_vmx *vmx = to_vmx(vcpu);
4130         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4131
4132         vmx_segment_cache_clear(vmx);
4133
4134         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4135                 vmx->rmode.segs[seg] = *var;
4136                 if (seg == VCPU_SREG_TR)
4137                         vmcs_write16(sf->selector, var->selector);
4138                 else if (var->s)
4139                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
4140                 goto out;
4141         }
4142
4143         vmcs_writel(sf->base, var->base);
4144         vmcs_write32(sf->limit, var->limit);
4145         vmcs_write16(sf->selector, var->selector);
4146
4147         /*
4148          *   Fix the "Accessed" bit in AR field of segment registers for older
4149          * qemu binaries.
4150          *   IA32 arch specifies that at the time of processor reset the
4151          * "Accessed" bit in the AR field of segment registers is 1. And qemu
4152          * is setting it to 0 in the userland code. This causes invalid guest
4153          * state vmexit when "unrestricted guest" mode is turned on.
4154          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
4155          * tree. Newer qemu binaries with that qemu fix would not need this
4156          * kvm hack.
4157          */
4158         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
4159                 var->type |= 0x1; /* Accessed */
4160
4161         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
4162
4163 out:
4164         vmx->emulation_required = emulation_required(vcpu);
4165 }
4166
4167 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4168 {
4169         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4170
4171         *db = (ar >> 14) & 1;
4172         *l = (ar >> 13) & 1;
4173 }
4174
4175 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4176 {
4177         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4178         dt->address = vmcs_readl(GUEST_IDTR_BASE);
4179 }
4180
4181 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4182 {
4183         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4184         vmcs_writel(GUEST_IDTR_BASE, dt->address);
4185 }
4186
4187 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4188 {
4189         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4190         dt->address = vmcs_readl(GUEST_GDTR_BASE);
4191 }
4192
4193 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4194 {
4195         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4196         vmcs_writel(GUEST_GDTR_BASE, dt->address);
4197 }
4198
4199 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4200 {
4201         struct kvm_segment var;
4202         u32 ar;
4203
4204         vmx_get_segment(vcpu, &var, seg);
4205         var.dpl = 0x3;
4206         if (seg == VCPU_SREG_CS)
4207                 var.type = 0x3;
4208         ar = vmx_segment_access_rights(&var);
4209
4210         if (var.base != (var.selector << 4))
4211                 return false;
4212         if (var.limit != 0xffff)
4213                 return false;
4214         if (ar != 0xf3)
4215                 return false;
4216
4217         return true;
4218 }
4219
4220 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4221 {
4222         struct kvm_segment cs;
4223         unsigned int cs_rpl;
4224
4225         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4226         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4227
4228         if (cs.unusable)
4229                 return false;
4230         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4231                 return false;
4232         if (!cs.s)
4233                 return false;
4234         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4235                 if (cs.dpl > cs_rpl)
4236                         return false;
4237         } else {
4238                 if (cs.dpl != cs_rpl)
4239                         return false;
4240         }
4241         if (!cs.present)
4242                 return false;
4243
4244         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4245         return true;
4246 }
4247
4248 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4249 {
4250         struct kvm_segment ss;
4251         unsigned int ss_rpl;
4252
4253         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4254         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4255
4256         if (ss.unusable)
4257                 return true;
4258         if (ss.type != 3 && ss.type != 7)
4259                 return false;
4260         if (!ss.s)
4261                 return false;
4262         if (ss.dpl != ss_rpl) /* DPL != RPL */
4263                 return false;
4264         if (!ss.present)
4265                 return false;
4266
4267         return true;
4268 }
4269
4270 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4271 {
4272         struct kvm_segment var;
4273         unsigned int rpl;
4274
4275         vmx_get_segment(vcpu, &var, seg);
4276         rpl = var.selector & SEGMENT_RPL_MASK;
4277
4278         if (var.unusable)
4279                 return true;
4280         if (!var.s)
4281                 return false;
4282         if (!var.present)
4283                 return false;
4284         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4285                 if (var.dpl < rpl) /* DPL < RPL */
4286                         return false;
4287         }
4288
4289         /* TODO: Add other members to kvm_segment_field to allow checking for other access
4290          * rights flags
4291          */
4292         return true;
4293 }
4294
4295 static bool tr_valid(struct kvm_vcpu *vcpu)
4296 {
4297         struct kvm_segment tr;
4298
4299         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4300
4301         if (tr.unusable)
4302                 return false;
4303         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
4304                 return false;
4305         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4306                 return false;
4307         if (!tr.present)
4308                 return false;
4309
4310         return true;
4311 }
4312
4313 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4314 {
4315         struct kvm_segment ldtr;
4316
4317         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4318
4319         if (ldtr.unusable)
4320                 return true;
4321         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
4322                 return false;
4323         if (ldtr.type != 2)
4324                 return false;
4325         if (!ldtr.present)
4326                 return false;
4327
4328         return true;
4329 }
4330
4331 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4332 {
4333         struct kvm_segment cs, ss;
4334
4335         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4336         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4337
4338         return ((cs.selector & SEGMENT_RPL_MASK) ==
4339                  (ss.selector & SEGMENT_RPL_MASK));
4340 }
4341
4342 /*
4343  * Check if guest state is valid. Returns true if valid, false if
4344  * not.
4345  * We assume that registers are always usable
4346  */
4347 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4348 {
4349         if (enable_unrestricted_guest)
4350                 return true;
4351
4352         /* real mode guest state checks */
4353         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4354                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4355                         return false;
4356                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4357                         return false;
4358                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4359                         return false;
4360                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4361                         return false;
4362                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4363                         return false;
4364                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4365                         return false;
4366         } else {
4367         /* protected mode guest state checks */
4368                 if (!cs_ss_rpl_check(vcpu))
4369                         return false;
4370                 if (!code_segment_valid(vcpu))
4371                         return false;
4372                 if (!stack_segment_valid(vcpu))
4373                         return false;
4374                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4375                         return false;
4376                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4377                         return false;
4378                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4379                         return false;
4380                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4381                         return false;
4382                 if (!tr_valid(vcpu))
4383                         return false;
4384                 if (!ldtr_valid(vcpu))
4385                         return false;
4386         }
4387         /* TODO:
4388          * - Add checks on RIP
4389          * - Add checks on RFLAGS
4390          */
4391
4392         return true;
4393 }
4394
4395 static int init_rmode_tss(struct kvm *kvm)
4396 {
4397         gfn_t fn;
4398         u16 data = 0;
4399         int idx, r;
4400
4401         idx = srcu_read_lock(&kvm->srcu);
4402         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4403         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4404         if (r < 0)
4405                 goto out;
4406         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4407         r = kvm_write_guest_page(kvm, fn++, &data,
4408                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4409         if (r < 0)
4410                 goto out;
4411         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4412         if (r < 0)
4413                 goto out;
4414         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4415         if (r < 0)
4416                 goto out;
4417         data = ~0;
4418         r = kvm_write_guest_page(kvm, fn, &data,
4419                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4420                                  sizeof(u8));
4421 out:
4422         srcu_read_unlock(&kvm->srcu, idx);
4423         return r;
4424 }
4425
4426 static int init_rmode_identity_map(struct kvm *kvm)
4427 {
4428         int i, idx, r = 0;
4429         kvm_pfn_t identity_map_pfn;
4430         u32 tmp;
4431
4432         if (!enable_ept)
4433                 return 0;
4434
4435         /* Protect kvm->arch.ept_identity_pagetable_done. */
4436         mutex_lock(&kvm->slots_lock);
4437
4438         if (likely(kvm->arch.ept_identity_pagetable_done))
4439                 goto out2;
4440
4441         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4442
4443         r = alloc_identity_pagetable(kvm);
4444         if (r < 0)
4445                 goto out2;
4446
4447         idx = srcu_read_lock(&kvm->srcu);
4448         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4449         if (r < 0)
4450                 goto out;
4451         /* Set up identity-mapping pagetable for EPT in real mode */
4452         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4453                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4454                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4455                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4456                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4457                 if (r < 0)
4458                         goto out;
4459         }
4460         kvm->arch.ept_identity_pagetable_done = true;
4461
4462 out:
4463         srcu_read_unlock(&kvm->srcu, idx);
4464
4465 out2:
4466         mutex_unlock(&kvm->slots_lock);
4467         return r;
4468 }
4469
4470 static void seg_setup(int seg)
4471 {
4472         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4473         unsigned int ar;
4474
4475         vmcs_write16(sf->selector, 0);
4476         vmcs_writel(sf->base, 0);
4477         vmcs_write32(sf->limit, 0xffff);
4478         ar = 0x93;
4479         if (seg == VCPU_SREG_CS)
4480                 ar |= 0x08; /* code segment */
4481
4482         vmcs_write32(sf->ar_bytes, ar);
4483 }
4484
4485 static int alloc_apic_access_page(struct kvm *kvm)
4486 {
4487         struct page *page;
4488         int r = 0;
4489
4490         mutex_lock(&kvm->slots_lock);
4491         if (kvm->arch.apic_access_page_done)
4492                 goto out;
4493         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4494                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4495         if (r)
4496                 goto out;
4497
4498         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4499         if (is_error_page(page)) {
4500                 r = -EFAULT;
4501                 goto out;
4502         }
4503
4504         /*
4505          * Do not pin the page in memory, so that memory hot-unplug
4506          * is able to migrate it.
4507          */
4508         put_page(page);
4509         kvm->arch.apic_access_page_done = true;
4510 out:
4511         mutex_unlock(&kvm->slots_lock);
4512         return r;
4513 }
4514
4515 static int alloc_identity_pagetable(struct kvm *kvm)
4516 {
4517         /* Called with kvm->slots_lock held. */
4518
4519         int r = 0;
4520
4521         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4522
4523         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4524                                     kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4525
4526         return r;
4527 }
4528
4529 static int allocate_vpid(void)
4530 {
4531         int vpid;
4532
4533         if (!enable_vpid)
4534                 return 0;
4535         spin_lock(&vmx_vpid_lock);
4536         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4537         if (vpid < VMX_NR_VPIDS)
4538                 __set_bit(vpid, vmx_vpid_bitmap);
4539         else
4540                 vpid = 0;
4541         spin_unlock(&vmx_vpid_lock);
4542         return vpid;
4543 }
4544
4545 static void free_vpid(int vpid)
4546 {
4547         if (!enable_vpid || vpid == 0)
4548                 return;
4549         spin_lock(&vmx_vpid_lock);
4550         __clear_bit(vpid, vmx_vpid_bitmap);
4551         spin_unlock(&vmx_vpid_lock);
4552 }
4553
4554 #define MSR_TYPE_R      1
4555 #define MSR_TYPE_W      2
4556 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4557                                                 u32 msr, int type)
4558 {
4559         int f = sizeof(unsigned long);
4560
4561         if (!cpu_has_vmx_msr_bitmap())
4562                 return;
4563
4564         /*
4565          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4566          * have the write-low and read-high bitmap offsets the wrong way round.
4567          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4568          */
4569         if (msr <= 0x1fff) {
4570                 if (type & MSR_TYPE_R)
4571                         /* read-low */
4572                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4573
4574                 if (type & MSR_TYPE_W)
4575                         /* write-low */
4576                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4577
4578         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4579                 msr &= 0x1fff;
4580                 if (type & MSR_TYPE_R)
4581                         /* read-high */
4582                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4583
4584                 if (type & MSR_TYPE_W)
4585                         /* write-high */
4586                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4587
4588         }
4589 }
4590
4591 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4592                                                 u32 msr, int type)
4593 {
4594         int f = sizeof(unsigned long);
4595
4596         if (!cpu_has_vmx_msr_bitmap())
4597                 return;
4598
4599         /*
4600          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4601          * have the write-low and read-high bitmap offsets the wrong way round.
4602          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4603          */
4604         if (msr <= 0x1fff) {
4605                 if (type & MSR_TYPE_R)
4606                         /* read-low */
4607                         __set_bit(msr, msr_bitmap + 0x000 / f);
4608
4609                 if (type & MSR_TYPE_W)
4610                         /* write-low */
4611                         __set_bit(msr, msr_bitmap + 0x800 / f);
4612
4613         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4614                 msr &= 0x1fff;
4615                 if (type & MSR_TYPE_R)
4616                         /* read-high */
4617                         __set_bit(msr, msr_bitmap + 0x400 / f);
4618
4619                 if (type & MSR_TYPE_W)
4620                         /* write-high */
4621                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4622
4623         }
4624 }
4625
4626 /*
4627  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4628  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4629  */
4630 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4631                                                unsigned long *msr_bitmap_nested,
4632                                                u32 msr, int type)
4633 {
4634         int f = sizeof(unsigned long);
4635
4636         if (!cpu_has_vmx_msr_bitmap()) {
4637                 WARN_ON(1);
4638                 return;
4639         }
4640
4641         /*
4642          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4643          * have the write-low and read-high bitmap offsets the wrong way round.
4644          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4645          */
4646         if (msr <= 0x1fff) {
4647                 if (type & MSR_TYPE_R &&
4648                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4649                         /* read-low */
4650                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4651
4652                 if (type & MSR_TYPE_W &&
4653                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4654                         /* write-low */
4655                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4656
4657         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4658                 msr &= 0x1fff;
4659                 if (type & MSR_TYPE_R &&
4660                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4661                         /* read-high */
4662                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4663
4664                 if (type & MSR_TYPE_W &&
4665                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4666                         /* write-high */
4667                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4668
4669         }
4670 }
4671
4672 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4673 {
4674         if (!longmode_only)
4675                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4676                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4677         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4678                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4679 }
4680
4681 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4682 {
4683         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4684                         msr, MSR_TYPE_R);
4685         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4686                         msr, MSR_TYPE_R);
4687 }
4688
4689 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4690 {
4691         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4692                         msr, MSR_TYPE_R);
4693         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4694                         msr, MSR_TYPE_R);
4695 }
4696
4697 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4698 {
4699         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4700                         msr, MSR_TYPE_W);
4701         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4702                         msr, MSR_TYPE_W);
4703 }
4704
4705 static bool vmx_get_enable_apicv(void)
4706 {
4707         return enable_apicv;
4708 }
4709
4710 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4711 {
4712         struct vcpu_vmx *vmx = to_vmx(vcpu);
4713         int max_irr;
4714         void *vapic_page;
4715         u16 status;
4716
4717         if (vmx->nested.pi_desc &&
4718             vmx->nested.pi_pending) {
4719                 vmx->nested.pi_pending = false;
4720                 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4721                         return 0;
4722
4723                 max_irr = find_last_bit(
4724                         (unsigned long *)vmx->nested.pi_desc->pir, 256);
4725
4726                 if (max_irr == 256)
4727                         return 0;
4728
4729                 vapic_page = kmap(vmx->nested.virtual_apic_page);
4730                 if (!vapic_page) {
4731                         WARN_ON(1);
4732                         return -ENOMEM;
4733                 }
4734                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4735                 kunmap(vmx->nested.virtual_apic_page);
4736
4737                 status = vmcs_read16(GUEST_INTR_STATUS);
4738                 if ((u8)max_irr > ((u8)status & 0xff)) {
4739                         status &= ~0xff;
4740                         status |= (u8)max_irr;
4741                         vmcs_write16(GUEST_INTR_STATUS, status);
4742                 }
4743         }
4744         return 0;
4745 }
4746
4747 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4748 {
4749 #ifdef CONFIG_SMP
4750         if (vcpu->mode == IN_GUEST_MODE) {
4751                 struct vcpu_vmx *vmx = to_vmx(vcpu);
4752
4753                 /*
4754                  * Currently, we don't support urgent interrupt,
4755                  * all interrupts are recognized as non-urgent
4756                  * interrupt, so we cannot post interrupts when
4757                  * 'SN' is set.
4758                  *
4759                  * If the vcpu is in guest mode, it means it is
4760                  * running instead of being scheduled out and
4761                  * waiting in the run queue, and that's the only
4762                  * case when 'SN' is set currently, warning if
4763                  * 'SN' is set.
4764                  */
4765                 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4766
4767                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4768                                 POSTED_INTR_VECTOR);
4769                 return true;
4770         }
4771 #endif
4772         return false;
4773 }
4774
4775 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4776                                                 int vector)
4777 {
4778         struct vcpu_vmx *vmx = to_vmx(vcpu);
4779
4780         if (is_guest_mode(vcpu) &&
4781             vector == vmx->nested.posted_intr_nv) {
4782                 /* the PIR and ON have been set by L1. */
4783                 kvm_vcpu_trigger_posted_interrupt(vcpu);
4784                 /*
4785                  * If a posted intr is not recognized by hardware,
4786                  * we will accomplish it in the next vmentry.
4787                  */
4788                 vmx->nested.pi_pending = true;
4789                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4790                 return 0;
4791         }
4792         return -1;
4793 }
4794 /*
4795  * Send interrupt to vcpu via posted interrupt way.
4796  * 1. If target vcpu is running(non-root mode), send posted interrupt
4797  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4798  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4799  * interrupt from PIR in next vmentry.
4800  */
4801 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4802 {
4803         struct vcpu_vmx *vmx = to_vmx(vcpu);
4804         int r;
4805
4806         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4807         if (!r)
4808                 return;
4809
4810         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4811                 return;
4812
4813         r = pi_test_and_set_on(&vmx->pi_desc);
4814         kvm_make_request(KVM_REQ_EVENT, vcpu);
4815         if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
4816                 kvm_vcpu_kick(vcpu);
4817 }
4818
4819 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4820 {
4821         struct vcpu_vmx *vmx = to_vmx(vcpu);
4822
4823         if (!pi_test_and_clear_on(&vmx->pi_desc))
4824                 return;
4825
4826         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4827 }
4828
4829 /*
4830  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4831  * will not change in the lifetime of the guest.
4832  * Note that host-state that does change is set elsewhere. E.g., host-state
4833  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4834  */
4835 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4836 {
4837         u32 low32, high32;
4838         unsigned long tmpl;
4839         struct desc_ptr dt;
4840         unsigned long cr4;
4841
4842         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4843         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4844
4845         /* Save the most likely value for this task's CR4 in the VMCS. */
4846         cr4 = cr4_read_shadow();
4847         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
4848         vmx->host_state.vmcs_host_cr4 = cr4;
4849
4850         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4851 #ifdef CONFIG_X86_64
4852         /*
4853          * Load null selectors, so we can avoid reloading them in
4854          * __vmx_load_host_state(), in case userspace uses the null selectors
4855          * too (the expected case).
4856          */
4857         vmcs_write16(HOST_DS_SELECTOR, 0);
4858         vmcs_write16(HOST_ES_SELECTOR, 0);
4859 #else
4860         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4861         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4862 #endif
4863         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4864         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4865
4866         native_store_idt(&dt);
4867         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4868         vmx->host_idt_base = dt.address;
4869
4870         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4871
4872         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4873         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4874         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4875         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4876
4877         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4878                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4879                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4880         }
4881 }
4882
4883 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4884 {
4885         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4886         if (enable_ept)
4887                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4888         if (is_guest_mode(&vmx->vcpu))
4889                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4890                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4891         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4892 }
4893
4894 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4895 {
4896         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4897
4898         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4899                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4900         /* Enable the preemption timer dynamically */
4901         pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
4902         return pin_based_exec_ctrl;
4903 }
4904
4905 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4906 {
4907         struct vcpu_vmx *vmx = to_vmx(vcpu);
4908
4909         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4910         if (cpu_has_secondary_exec_ctrls()) {
4911                 if (kvm_vcpu_apicv_active(vcpu))
4912                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
4913                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
4914                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4915                 else
4916                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
4917                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
4918                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4919         }
4920
4921         if (cpu_has_vmx_msr_bitmap())
4922                 vmx_set_msr_bitmap(vcpu);
4923 }
4924
4925 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4926 {
4927         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4928
4929         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4930                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4931
4932         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4933                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4934 #ifdef CONFIG_X86_64
4935                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4936                                 CPU_BASED_CR8_LOAD_EXITING;
4937 #endif
4938         }
4939         if (!enable_ept)
4940                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4941                                 CPU_BASED_CR3_LOAD_EXITING  |
4942                                 CPU_BASED_INVLPG_EXITING;
4943         return exec_control;
4944 }
4945
4946 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4947 {
4948         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4949         if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
4950                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4951         if (vmx->vpid == 0)
4952                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4953         if (!enable_ept) {
4954                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4955                 enable_unrestricted_guest = 0;
4956                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4957                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4958         }
4959         if (!enable_unrestricted_guest)
4960                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4961         if (!ple_gap)
4962                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4963         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4964                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4965                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4966         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4967         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4968            (handle_vmptrld).
4969            We can NOT enable shadow_vmcs here because we don't have yet
4970            a current VMCS12
4971         */
4972         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4973
4974         if (!enable_pml)
4975                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4976
4977         return exec_control;
4978 }
4979
4980 static void ept_set_mmio_spte_mask(void)
4981 {
4982         /*
4983          * EPT Misconfigurations can be generated if the value of bits 2:0
4984          * of an EPT paging-structure entry is 110b (write/execute).
4985          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4986          * spte.
4987          */
4988         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4989 }
4990
4991 #define VMX_XSS_EXIT_BITMAP 0
4992 /*
4993  * Sets up the vmcs for emulated real mode.
4994  */
4995 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4996 {
4997 #ifdef CONFIG_X86_64
4998         unsigned long a;
4999 #endif
5000         int i;
5001
5002         /* I/O */
5003         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
5004         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
5005
5006         if (enable_shadow_vmcs) {
5007                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
5008                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
5009         }
5010         if (cpu_has_vmx_msr_bitmap())
5011                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
5012
5013         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
5014
5015         /* Control */
5016         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5017         vmx->hv_deadline_tsc = -1;
5018
5019         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
5020
5021         if (cpu_has_secondary_exec_ctrls()) {
5022                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5023                                 vmx_secondary_exec_control(vmx));
5024         }
5025
5026         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
5027                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
5028                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
5029                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
5030                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
5031
5032                 vmcs_write16(GUEST_INTR_STATUS, 0);
5033
5034                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
5035                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
5036         }
5037
5038         if (ple_gap) {
5039                 vmcs_write32(PLE_GAP, ple_gap);
5040                 vmx->ple_window = ple_window;
5041                 vmx->ple_window_dirty = true;
5042         }
5043
5044         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
5045         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
5046         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
5047
5048         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
5049         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
5050         vmx_set_constant_host_state(vmx);
5051 #ifdef CONFIG_X86_64
5052         rdmsrl(MSR_FS_BASE, a);
5053         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
5054         rdmsrl(MSR_GS_BASE, a);
5055         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
5056 #else
5057         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
5058         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
5059 #endif
5060
5061         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
5062         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
5063         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
5064         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
5065         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
5066
5067         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
5068                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
5069
5070         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
5071                 u32 index = vmx_msr_index[i];
5072                 u32 data_low, data_high;
5073                 int j = vmx->nmsrs;
5074
5075                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
5076                         continue;
5077                 if (wrmsr_safe(index, data_low, data_high) < 0)
5078                         continue;
5079                 vmx->guest_msrs[j].index = i;
5080                 vmx->guest_msrs[j].data = 0;
5081                 vmx->guest_msrs[j].mask = -1ull;
5082                 ++vmx->nmsrs;
5083         }
5084
5085
5086         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
5087
5088         /* 22.2.1, 20.8.1 */
5089         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
5090
5091         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
5092         set_cr4_guest_host_mask(vmx);
5093
5094         if (vmx_xsaves_supported())
5095                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
5096
5097         if (enable_pml) {
5098                 ASSERT(vmx->pml_pg);
5099                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
5100                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5101         }
5102
5103         return 0;
5104 }
5105
5106 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
5107 {
5108         struct vcpu_vmx *vmx = to_vmx(vcpu);
5109         struct msr_data apic_base_msr;
5110         u64 cr0;
5111
5112         vmx->rmode.vm86_active = 0;
5113
5114         vmx->soft_vnmi_blocked = 0;
5115
5116         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
5117         kvm_set_cr8(vcpu, 0);
5118
5119         if (!init_event) {
5120                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
5121                                      MSR_IA32_APICBASE_ENABLE;
5122                 if (kvm_vcpu_is_reset_bsp(vcpu))
5123                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
5124                 apic_base_msr.host_initiated = true;
5125                 kvm_set_apic_base(vcpu, &apic_base_msr);
5126         }
5127
5128         vmx_segment_cache_clear(vmx);
5129
5130         seg_setup(VCPU_SREG_CS);
5131         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
5132         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
5133
5134         seg_setup(VCPU_SREG_DS);
5135         seg_setup(VCPU_SREG_ES);
5136         seg_setup(VCPU_SREG_FS);
5137         seg_setup(VCPU_SREG_GS);
5138         seg_setup(VCPU_SREG_SS);
5139
5140         vmcs_write16(GUEST_TR_SELECTOR, 0);
5141         vmcs_writel(GUEST_TR_BASE, 0);
5142         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5143         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5144
5145         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5146         vmcs_writel(GUEST_LDTR_BASE, 0);
5147         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5148         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5149
5150         if (!init_event) {
5151                 vmcs_write32(GUEST_SYSENTER_CS, 0);
5152                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5153                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5154                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5155         }
5156
5157         vmcs_writel(GUEST_RFLAGS, 0x02);
5158         kvm_rip_write(vcpu, 0xfff0);
5159
5160         vmcs_writel(GUEST_GDTR_BASE, 0);
5161         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5162
5163         vmcs_writel(GUEST_IDTR_BASE, 0);
5164         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5165
5166         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
5167         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
5168         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
5169
5170         setup_msrs(vmx);
5171
5172         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
5173
5174         if (cpu_has_vmx_tpr_shadow() && !init_event) {
5175                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
5176                 if (cpu_need_tpr_shadow(vcpu))
5177                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
5178                                      __pa(vcpu->arch.apic->regs));
5179                 vmcs_write32(TPR_THRESHOLD, 0);
5180         }
5181
5182         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
5183
5184         if (kvm_vcpu_apicv_active(vcpu))
5185                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5186
5187         if (vmx->vpid != 0)
5188                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5189
5190         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5191         vmx->vcpu.arch.cr0 = cr0;
5192         vmx_set_cr0(vcpu, cr0); /* enter rmode */
5193         vmx_set_cr4(vcpu, 0);
5194         vmx_set_efer(vcpu, 0);
5195         vmx_fpu_activate(vcpu);
5196         update_exception_bitmap(vcpu);
5197
5198         vpid_sync_context(vmx->vpid);
5199 }
5200
5201 /*
5202  * In nested virtualization, check if L1 asked to exit on external interrupts.
5203  * For most existing hypervisors, this will always return true.
5204  */
5205 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5206 {
5207         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5208                 PIN_BASED_EXT_INTR_MASK;
5209 }
5210
5211 /*
5212  * In nested virtualization, check if L1 has set
5213  * VM_EXIT_ACK_INTR_ON_EXIT
5214  */
5215 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5216 {
5217         return get_vmcs12(vcpu)->vm_exit_controls &
5218                 VM_EXIT_ACK_INTR_ON_EXIT;
5219 }
5220
5221 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5222 {
5223         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5224                 PIN_BASED_NMI_EXITING;
5225 }
5226
5227 static void enable_irq_window(struct kvm_vcpu *vcpu)
5228 {
5229         u32 cpu_based_vm_exec_control;
5230
5231         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5232         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
5233         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5234 }
5235
5236 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5237 {
5238         u32 cpu_based_vm_exec_control;
5239
5240         if (!cpu_has_virtual_nmis() ||
5241             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5242                 enable_irq_window(vcpu);
5243                 return;
5244         }
5245
5246         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5247         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
5248         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5249 }
5250
5251 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5252 {
5253         struct vcpu_vmx *vmx = to_vmx(vcpu);
5254         uint32_t intr;
5255         int irq = vcpu->arch.interrupt.nr;
5256
5257         trace_kvm_inj_virq(irq);
5258
5259         ++vcpu->stat.irq_injections;
5260         if (vmx->rmode.vm86_active) {
5261                 int inc_eip = 0;
5262                 if (vcpu->arch.interrupt.soft)
5263                         inc_eip = vcpu->arch.event_exit_inst_len;
5264                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5265                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5266                 return;
5267         }
5268         intr = irq | INTR_INFO_VALID_MASK;
5269         if (vcpu->arch.interrupt.soft) {
5270                 intr |= INTR_TYPE_SOFT_INTR;
5271                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5272                              vmx->vcpu.arch.event_exit_inst_len);
5273         } else
5274                 intr |= INTR_TYPE_EXT_INTR;
5275         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5276 }
5277
5278 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5279 {
5280         struct vcpu_vmx *vmx = to_vmx(vcpu);
5281
5282         if (is_guest_mode(vcpu))
5283                 return;
5284
5285         if (!cpu_has_virtual_nmis()) {
5286                 /*
5287                  * Tracking the NMI-blocked state in software is built upon
5288                  * finding the next open IRQ window. This, in turn, depends on
5289                  * well-behaving guests: They have to keep IRQs disabled at
5290                  * least as long as the NMI handler runs. Otherwise we may
5291                  * cause NMI nesting, maybe breaking the guest. But as this is
5292                  * highly unlikely, we can live with the residual risk.
5293                  */
5294                 vmx->soft_vnmi_blocked = 1;
5295                 vmx->vnmi_blocked_time = 0;
5296         }
5297
5298         ++vcpu->stat.nmi_injections;
5299         vmx->nmi_known_unmasked = false;
5300         if (vmx->rmode.vm86_active) {
5301                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5302                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5303                 return;
5304         }
5305         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5306                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5307 }
5308
5309 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5310 {
5311         if (!cpu_has_virtual_nmis())
5312                 return to_vmx(vcpu)->soft_vnmi_blocked;
5313         if (to_vmx(vcpu)->nmi_known_unmasked)
5314                 return false;
5315         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5316 }
5317
5318 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5319 {
5320         struct vcpu_vmx *vmx = to_vmx(vcpu);
5321
5322         if (!cpu_has_virtual_nmis()) {
5323                 if (vmx->soft_vnmi_blocked != masked) {
5324                         vmx->soft_vnmi_blocked = masked;
5325                         vmx->vnmi_blocked_time = 0;
5326                 }
5327         } else {
5328                 vmx->nmi_known_unmasked = !masked;
5329                 if (masked)
5330                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5331                                       GUEST_INTR_STATE_NMI);
5332                 else
5333                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5334                                         GUEST_INTR_STATE_NMI);
5335         }
5336 }
5337
5338 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5339 {
5340         if (to_vmx(vcpu)->nested.nested_run_pending)
5341                 return 0;
5342
5343         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
5344                 return 0;
5345
5346         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5347                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5348                    | GUEST_INTR_STATE_NMI));
5349 }
5350
5351 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5352 {
5353         return (!to_vmx(vcpu)->nested.nested_run_pending &&
5354                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5355                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5356                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5357 }
5358
5359 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5360 {
5361         int ret;
5362
5363         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5364                                     PAGE_SIZE * 3);
5365         if (ret)
5366                 return ret;
5367         kvm->arch.tss_addr = addr;
5368         return init_rmode_tss(kvm);
5369 }
5370
5371 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5372 {
5373         switch (vec) {
5374         case BP_VECTOR:
5375                 /*
5376                  * Update instruction length as we may reinject the exception
5377                  * from user space while in guest debugging mode.
5378                  */
5379                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5380                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5381                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5382                         return false;
5383                 /* fall through */
5384         case DB_VECTOR:
5385                 if (vcpu->guest_debug &
5386                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5387                         return false;
5388                 /* fall through */
5389         case DE_VECTOR:
5390         case OF_VECTOR:
5391         case BR_VECTOR:
5392         case UD_VECTOR:
5393         case DF_VECTOR:
5394         case SS_VECTOR:
5395         case GP_VECTOR:
5396         case MF_VECTOR:
5397                 return true;
5398         break;
5399         }
5400         return false;
5401 }
5402
5403 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5404                                   int vec, u32 err_code)
5405 {
5406         /*
5407          * Instruction with address size override prefix opcode 0x67
5408          * Cause the #SS fault with 0 error code in VM86 mode.
5409          */
5410         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5411                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5412                         if (vcpu->arch.halt_request) {
5413                                 vcpu->arch.halt_request = 0;
5414                                 return kvm_vcpu_halt(vcpu);
5415                         }
5416                         return 1;
5417                 }
5418                 return 0;
5419         }
5420
5421         /*
5422          * Forward all other exceptions that are valid in real mode.
5423          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5424          *        the required debugging infrastructure rework.
5425          */
5426         kvm_queue_exception(vcpu, vec);
5427         return 1;
5428 }
5429
5430 /*
5431  * Trigger machine check on the host. We assume all the MSRs are already set up
5432  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5433  * We pass a fake environment to the machine check handler because we want
5434  * the guest to be always treated like user space, no matter what context
5435  * it used internally.
5436  */
5437 static void kvm_machine_check(void)
5438 {
5439 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5440         struct pt_regs regs = {
5441                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5442                 .flags = X86_EFLAGS_IF,
5443         };
5444
5445         do_machine_check(&regs, 0);
5446 #endif
5447 }
5448
5449 static int handle_machine_check(struct kvm_vcpu *vcpu)
5450 {
5451         /* already handled by vcpu_run */
5452         return 1;
5453 }
5454
5455 static int handle_exception(struct kvm_vcpu *vcpu)
5456 {
5457         struct vcpu_vmx *vmx = to_vmx(vcpu);
5458         struct kvm_run *kvm_run = vcpu->run;
5459         u32 intr_info, ex_no, error_code;
5460         unsigned long cr2, rip, dr6;
5461         u32 vect_info;
5462         enum emulation_result er;
5463
5464         vect_info = vmx->idt_vectoring_info;
5465         intr_info = vmx->exit_intr_info;
5466
5467         if (is_machine_check(intr_info))
5468                 return handle_machine_check(vcpu);
5469
5470         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
5471                 return 1;  /* already handled by vmx_vcpu_run() */
5472
5473         if (is_no_device(intr_info)) {
5474                 vmx_fpu_activate(vcpu);
5475                 return 1;
5476         }
5477
5478         if (is_invalid_opcode(intr_info)) {
5479                 if (is_guest_mode(vcpu)) {
5480                         kvm_queue_exception(vcpu, UD_VECTOR);
5481                         return 1;
5482                 }
5483                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5484                 if (er != EMULATE_DONE)
5485                         kvm_queue_exception(vcpu, UD_VECTOR);
5486                 return 1;
5487         }
5488
5489         error_code = 0;
5490         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5491                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5492
5493         /*
5494          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5495          * MMIO, it is better to report an internal error.
5496          * See the comments in vmx_handle_exit.
5497          */
5498         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5499             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5500                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5501                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5502                 vcpu->run->internal.ndata = 3;
5503                 vcpu->run->internal.data[0] = vect_info;
5504                 vcpu->run->internal.data[1] = intr_info;
5505                 vcpu->run->internal.data[2] = error_code;
5506                 return 0;
5507         }
5508
5509         if (is_page_fault(intr_info)) {
5510                 /* EPT won't cause page fault directly */
5511                 BUG_ON(enable_ept);
5512                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5513                 trace_kvm_page_fault(cr2, error_code);
5514
5515                 if (kvm_event_needs_reinjection(vcpu))
5516                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
5517                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5518         }
5519
5520         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5521
5522         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5523                 return handle_rmode_exception(vcpu, ex_no, error_code);
5524
5525         switch (ex_no) {
5526         case AC_VECTOR:
5527                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5528                 return 1;
5529         case DB_VECTOR:
5530                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5531                 if (!(vcpu->guest_debug &
5532                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5533                         vcpu->arch.dr6 &= ~15;
5534                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5535                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5536                                 skip_emulated_instruction(vcpu);
5537
5538                         kvm_queue_exception(vcpu, DB_VECTOR);
5539                         return 1;
5540                 }
5541                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5542                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5543                 /* fall through */
5544         case BP_VECTOR:
5545                 /*
5546                  * Update instruction length as we may reinject #BP from
5547                  * user space while in guest debugging mode. Reading it for
5548                  * #DB as well causes no harm, it is not used in that case.
5549                  */
5550                 vmx->vcpu.arch.event_exit_inst_len =
5551                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5552                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5553                 rip = kvm_rip_read(vcpu);
5554                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5555                 kvm_run->debug.arch.exception = ex_no;
5556                 break;
5557         default:
5558                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5559                 kvm_run->ex.exception = ex_no;
5560                 kvm_run->ex.error_code = error_code;
5561                 break;
5562         }
5563         return 0;
5564 }
5565
5566 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5567 {
5568         ++vcpu->stat.irq_exits;
5569         return 1;
5570 }
5571
5572 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5573 {
5574         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5575         return 0;
5576 }
5577
5578 static int handle_io(struct kvm_vcpu *vcpu)
5579 {
5580         unsigned long exit_qualification;
5581         int size, in, string;
5582         unsigned port;
5583
5584         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5585         string = (exit_qualification & 16) != 0;
5586         in = (exit_qualification & 8) != 0;
5587
5588         ++vcpu->stat.io_exits;
5589
5590         if (string || in)
5591                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5592
5593         port = exit_qualification >> 16;
5594         size = (exit_qualification & 7) + 1;
5595         skip_emulated_instruction(vcpu);
5596
5597         return kvm_fast_pio_out(vcpu, size, port);
5598 }
5599
5600 static void
5601 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5602 {
5603         /*
5604          * Patch in the VMCALL instruction:
5605          */
5606         hypercall[0] = 0x0f;
5607         hypercall[1] = 0x01;
5608         hypercall[2] = 0xc1;
5609 }
5610
5611 static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5612 {
5613         unsigned long always_on = VMXON_CR0_ALWAYSON;
5614         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5615
5616         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
5617                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5618             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5619                 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5620         return (val & always_on) == always_on;
5621 }
5622
5623 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5624 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5625 {
5626         if (is_guest_mode(vcpu)) {
5627                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5628                 unsigned long orig_val = val;
5629
5630                 /*
5631                  * We get here when L2 changed cr0 in a way that did not change
5632                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5633                  * but did change L0 shadowed bits. So we first calculate the
5634                  * effective cr0 value that L1 would like to write into the
5635                  * hardware. It consists of the L2-owned bits from the new
5636                  * value combined with the L1-owned bits from L1's guest_cr0.
5637                  */
5638                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5639                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5640
5641                 if (!nested_cr0_valid(vcpu, val))
5642                         return 1;
5643
5644                 if (kvm_set_cr0(vcpu, val))
5645                         return 1;
5646                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5647                 return 0;
5648         } else {
5649                 if (to_vmx(vcpu)->nested.vmxon &&
5650                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5651                         return 1;
5652                 return kvm_set_cr0(vcpu, val);
5653         }
5654 }
5655
5656 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5657 {
5658         if (is_guest_mode(vcpu)) {
5659                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5660                 unsigned long orig_val = val;
5661
5662                 /* analogously to handle_set_cr0 */
5663                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5664                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5665                 if (kvm_set_cr4(vcpu, val))
5666                         return 1;
5667                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5668                 return 0;
5669         } else
5670                 return kvm_set_cr4(vcpu, val);
5671 }
5672
5673 /* called to set cr0 as appropriate for clts instruction exit. */
5674 static void handle_clts(struct kvm_vcpu *vcpu)
5675 {
5676         if (is_guest_mode(vcpu)) {
5677                 /*
5678                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5679                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5680                  * just pretend it's off (also in arch.cr0 for fpu_activate).
5681                  */
5682                 vmcs_writel(CR0_READ_SHADOW,
5683                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5684                 vcpu->arch.cr0 &= ~X86_CR0_TS;
5685         } else
5686                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5687 }
5688
5689 static int handle_cr(struct kvm_vcpu *vcpu)
5690 {
5691         unsigned long exit_qualification, val;
5692         int cr;
5693         int reg;
5694         int err;
5695
5696         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5697         cr = exit_qualification & 15;
5698         reg = (exit_qualification >> 8) & 15;
5699         switch ((exit_qualification >> 4) & 3) {
5700         case 0: /* mov to cr */
5701                 val = kvm_register_readl(vcpu, reg);
5702                 trace_kvm_cr_write(cr, val);
5703                 switch (cr) {
5704                 case 0:
5705                         err = handle_set_cr0(vcpu, val);
5706                         kvm_complete_insn_gp(vcpu, err);
5707                         return 1;
5708                 case 3:
5709                         err = kvm_set_cr3(vcpu, val);
5710                         kvm_complete_insn_gp(vcpu, err);
5711                         return 1;
5712                 case 4:
5713                         err = handle_set_cr4(vcpu, val);
5714                         kvm_complete_insn_gp(vcpu, err);
5715                         return 1;
5716                 case 8: {
5717                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5718                                 u8 cr8 = (u8)val;
5719                                 err = kvm_set_cr8(vcpu, cr8);
5720                                 kvm_complete_insn_gp(vcpu, err);
5721                                 if (lapic_in_kernel(vcpu))
5722                                         return 1;
5723                                 if (cr8_prev <= cr8)
5724                                         return 1;
5725                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5726                                 return 0;
5727                         }
5728                 }
5729                 break;
5730         case 2: /* clts */
5731                 handle_clts(vcpu);
5732                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5733                 skip_emulated_instruction(vcpu);
5734                 vmx_fpu_activate(vcpu);
5735                 return 1;
5736         case 1: /*mov from cr*/
5737                 switch (cr) {
5738                 case 3:
5739                         val = kvm_read_cr3(vcpu);
5740                         kvm_register_write(vcpu, reg, val);
5741                         trace_kvm_cr_read(cr, val);
5742                         skip_emulated_instruction(vcpu);
5743                         return 1;
5744                 case 8:
5745                         val = kvm_get_cr8(vcpu);
5746                         kvm_register_write(vcpu, reg, val);
5747                         trace_kvm_cr_read(cr, val);
5748                         skip_emulated_instruction(vcpu);
5749                         return 1;
5750                 }
5751                 break;
5752         case 3: /* lmsw */
5753                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5754                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5755                 kvm_lmsw(vcpu, val);
5756
5757                 skip_emulated_instruction(vcpu);
5758                 return 1;
5759         default:
5760                 break;
5761         }
5762         vcpu->run->exit_reason = 0;
5763         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5764                (int)(exit_qualification >> 4) & 3, cr);
5765         return 0;
5766 }
5767
5768 static int handle_dr(struct kvm_vcpu *vcpu)
5769 {
5770         unsigned long exit_qualification;
5771         int dr, dr7, reg;
5772
5773         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5774         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5775
5776         /* First, if DR does not exist, trigger UD */
5777         if (!kvm_require_dr(vcpu, dr))
5778                 return 1;
5779
5780         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5781         if (!kvm_require_cpl(vcpu, 0))
5782                 return 1;
5783         dr7 = vmcs_readl(GUEST_DR7);
5784         if (dr7 & DR7_GD) {
5785                 /*
5786                  * As the vm-exit takes precedence over the debug trap, we
5787                  * need to emulate the latter, either for the host or the
5788                  * guest debugging itself.
5789                  */
5790                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5791                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5792                         vcpu->run->debug.arch.dr7 = dr7;
5793                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5794                         vcpu->run->debug.arch.exception = DB_VECTOR;
5795                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5796                         return 0;
5797                 } else {
5798                         vcpu->arch.dr6 &= ~15;
5799                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5800                         kvm_queue_exception(vcpu, DB_VECTOR);
5801                         return 1;
5802                 }
5803         }
5804
5805         if (vcpu->guest_debug == 0) {
5806                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
5807                                 CPU_BASED_MOV_DR_EXITING);
5808
5809                 /*
5810                  * No more DR vmexits; force a reload of the debug registers
5811                  * and reenter on this instruction.  The next vmexit will
5812                  * retrieve the full state of the debug registers.
5813                  */
5814                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5815                 return 1;
5816         }
5817
5818         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5819         if (exit_qualification & TYPE_MOV_FROM_DR) {
5820                 unsigned long val;
5821
5822                 if (kvm_get_dr(vcpu, dr, &val))
5823                         return 1;
5824                 kvm_register_write(vcpu, reg, val);
5825         } else
5826                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5827                         return 1;
5828
5829         skip_emulated_instruction(vcpu);
5830         return 1;
5831 }
5832
5833 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5834 {
5835         return vcpu->arch.dr6;
5836 }
5837
5838 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5839 {
5840 }
5841
5842 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5843 {
5844         get_debugreg(vcpu->arch.db[0], 0);
5845         get_debugreg(vcpu->arch.db[1], 1);
5846         get_debugreg(vcpu->arch.db[2], 2);
5847         get_debugreg(vcpu->arch.db[3], 3);
5848         get_debugreg(vcpu->arch.dr6, 6);
5849         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5850
5851         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5852         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
5853 }
5854
5855 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5856 {
5857         vmcs_writel(GUEST_DR7, val);
5858 }
5859
5860 static int handle_cpuid(struct kvm_vcpu *vcpu)
5861 {
5862         kvm_emulate_cpuid(vcpu);
5863         return 1;
5864 }
5865
5866 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5867 {
5868         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5869         struct msr_data msr_info;
5870
5871         msr_info.index = ecx;
5872         msr_info.host_initiated = false;
5873         if (vmx_get_msr(vcpu, &msr_info)) {
5874                 trace_kvm_msr_read_ex(ecx);
5875                 kvm_inject_gp(vcpu, 0);
5876                 return 1;
5877         }
5878
5879         trace_kvm_msr_read(ecx, msr_info.data);
5880
5881         /* FIXME: handling of bits 32:63 of rax, rdx */
5882         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
5883         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
5884         skip_emulated_instruction(vcpu);
5885         return 1;
5886 }
5887
5888 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5889 {
5890         struct msr_data msr;
5891         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5892         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5893                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5894
5895         msr.data = data;
5896         msr.index = ecx;
5897         msr.host_initiated = false;
5898         if (kvm_set_msr(vcpu, &msr) != 0) {
5899                 trace_kvm_msr_write_ex(ecx, data);
5900                 kvm_inject_gp(vcpu, 0);
5901                 return 1;
5902         }
5903
5904         trace_kvm_msr_write(ecx, data);
5905         skip_emulated_instruction(vcpu);
5906         return 1;
5907 }
5908
5909 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5910 {
5911         kvm_make_request(KVM_REQ_EVENT, vcpu);
5912         return 1;
5913 }
5914
5915 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5916 {
5917         u32 cpu_based_vm_exec_control;
5918
5919         /* clear pending irq */
5920         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5921         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5922         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5923
5924         kvm_make_request(KVM_REQ_EVENT, vcpu);
5925
5926         ++vcpu->stat.irq_window_exits;
5927         return 1;
5928 }
5929
5930 static int handle_halt(struct kvm_vcpu *vcpu)
5931 {
5932         return kvm_emulate_halt(vcpu);
5933 }
5934
5935 static int handle_vmcall(struct kvm_vcpu *vcpu)
5936 {
5937         return kvm_emulate_hypercall(vcpu);
5938 }
5939
5940 static int handle_invd(struct kvm_vcpu *vcpu)
5941 {
5942         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5943 }
5944
5945 static int handle_invlpg(struct kvm_vcpu *vcpu)
5946 {
5947         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5948
5949         kvm_mmu_invlpg(vcpu, exit_qualification);
5950         skip_emulated_instruction(vcpu);
5951         return 1;
5952 }
5953
5954 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5955 {
5956         int err;
5957
5958         err = kvm_rdpmc(vcpu);
5959         kvm_complete_insn_gp(vcpu, err);
5960
5961         return 1;
5962 }
5963
5964 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5965 {
5966         kvm_emulate_wbinvd(vcpu);
5967         return 1;
5968 }
5969
5970 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5971 {
5972         u64 new_bv = kvm_read_edx_eax(vcpu);
5973         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5974
5975         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5976                 skip_emulated_instruction(vcpu);
5977         return 1;
5978 }
5979
5980 static int handle_xsaves(struct kvm_vcpu *vcpu)
5981 {
5982         skip_emulated_instruction(vcpu);
5983         WARN(1, "this should never happen\n");
5984         return 1;
5985 }
5986
5987 static int handle_xrstors(struct kvm_vcpu *vcpu)
5988 {
5989         skip_emulated_instruction(vcpu);
5990         WARN(1, "this should never happen\n");
5991         return 1;
5992 }
5993
5994 static int handle_apic_access(struct kvm_vcpu *vcpu)
5995 {
5996         if (likely(fasteoi)) {
5997                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5998                 int access_type, offset;
5999
6000                 access_type = exit_qualification & APIC_ACCESS_TYPE;
6001                 offset = exit_qualification & APIC_ACCESS_OFFSET;
6002                 /*
6003                  * Sane guest uses MOV to write EOI, with written value
6004                  * not cared. So make a short-circuit here by avoiding
6005                  * heavy instruction emulation.
6006                  */
6007                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
6008                     (offset == APIC_EOI)) {
6009                         kvm_lapic_set_eoi(vcpu);
6010                         skip_emulated_instruction(vcpu);
6011                         return 1;
6012                 }
6013         }
6014         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6015 }
6016
6017 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
6018 {
6019         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6020         int vector = exit_qualification & 0xff;
6021
6022         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6023         kvm_apic_set_eoi_accelerated(vcpu, vector);
6024         return 1;
6025 }
6026
6027 static int handle_apic_write(struct kvm_vcpu *vcpu)
6028 {
6029         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6030         u32 offset = exit_qualification & 0xfff;
6031
6032         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6033         kvm_apic_write_nodecode(vcpu, offset);
6034         return 1;
6035 }
6036
6037 static int handle_task_switch(struct kvm_vcpu *vcpu)
6038 {
6039         struct vcpu_vmx *vmx = to_vmx(vcpu);
6040         unsigned long exit_qualification;
6041         bool has_error_code = false;
6042         u32 error_code = 0;
6043         u16 tss_selector;
6044         int reason, type, idt_v, idt_index;
6045
6046         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
6047         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
6048         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
6049
6050         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6051
6052         reason = (u32)exit_qualification >> 30;
6053         if (reason == TASK_SWITCH_GATE && idt_v) {
6054                 switch (type) {
6055                 case INTR_TYPE_NMI_INTR:
6056                         vcpu->arch.nmi_injected = false;
6057                         vmx_set_nmi_mask(vcpu, true);
6058                         break;
6059                 case INTR_TYPE_EXT_INTR:
6060                 case INTR_TYPE_SOFT_INTR:
6061                         kvm_clear_interrupt_queue(vcpu);
6062                         break;
6063                 case INTR_TYPE_HARD_EXCEPTION:
6064                         if (vmx->idt_vectoring_info &
6065                             VECTORING_INFO_DELIVER_CODE_MASK) {
6066                                 has_error_code = true;
6067                                 error_code =
6068                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
6069                         }
6070                         /* fall through */
6071                 case INTR_TYPE_SOFT_EXCEPTION:
6072                         kvm_clear_exception_queue(vcpu);
6073                         break;
6074                 default:
6075                         break;
6076                 }
6077         }
6078         tss_selector = exit_qualification;
6079
6080         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
6081                        type != INTR_TYPE_EXT_INTR &&
6082                        type != INTR_TYPE_NMI_INTR))
6083                 skip_emulated_instruction(vcpu);
6084
6085         if (kvm_task_switch(vcpu, tss_selector,
6086                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
6087                             has_error_code, error_code) == EMULATE_FAIL) {
6088                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6089                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6090                 vcpu->run->internal.ndata = 0;
6091                 return 0;
6092         }
6093
6094         /*
6095          * TODO: What about debug traps on tss switch?
6096          *       Are we supposed to inject them and update dr6?
6097          */
6098
6099         return 1;
6100 }
6101
6102 static int handle_ept_violation(struct kvm_vcpu *vcpu)
6103 {
6104         unsigned long exit_qualification;
6105         gpa_t gpa;
6106         u32 error_code;
6107         int gla_validity;
6108
6109         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6110
6111         gla_validity = (exit_qualification >> 7) & 0x3;
6112         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
6113                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
6114                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
6115                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
6116                         vmcs_readl(GUEST_LINEAR_ADDRESS));
6117                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
6118                         (long unsigned int)exit_qualification);
6119                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6120                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
6121                 return 0;
6122         }
6123
6124         /*
6125          * EPT violation happened while executing iret from NMI,
6126          * "blocked by NMI" bit has to be set before next VM entry.
6127          * There are errata that may cause this bit to not be set:
6128          * AAK134, BY25.
6129          */
6130         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
6131                         cpu_has_virtual_nmis() &&
6132                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
6133                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
6134
6135         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6136         trace_kvm_page_fault(gpa, exit_qualification);
6137
6138         /* it is a read fault? */
6139         error_code = (exit_qualification << 2) & PFERR_USER_MASK;
6140         /* it is a write fault? */
6141         error_code |= exit_qualification & PFERR_WRITE_MASK;
6142         /* It is a fetch fault? */
6143         error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
6144         /* ept page table is present? */
6145         error_code |= (exit_qualification & 0x38) != 0;
6146
6147         vcpu->arch.exit_qualification = exit_qualification;
6148
6149         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
6150 }
6151
6152 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
6153 {
6154         int ret;
6155         gpa_t gpa;
6156
6157         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6158         if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
6159                 skip_emulated_instruction(vcpu);
6160                 trace_kvm_fast_mmio(gpa);
6161                 return 1;
6162         }
6163
6164         ret = handle_mmio_page_fault(vcpu, gpa, true);
6165         if (likely(ret == RET_MMIO_PF_EMULATE))
6166                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
6167                                               EMULATE_DONE;
6168
6169         if (unlikely(ret == RET_MMIO_PF_INVALID))
6170                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
6171
6172         if (unlikely(ret == RET_MMIO_PF_RETRY))
6173                 return 1;
6174
6175         /* It is the real ept misconfig */
6176         WARN_ON(1);
6177
6178         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6179         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
6180
6181         return 0;
6182 }
6183
6184 static int handle_nmi_window(struct kvm_vcpu *vcpu)
6185 {
6186         u32 cpu_based_vm_exec_control;
6187
6188         /* clear pending NMI */
6189         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6190         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6191         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
6192         ++vcpu->stat.nmi_window_exits;
6193         kvm_make_request(KVM_REQ_EVENT, vcpu);
6194
6195         return 1;
6196 }
6197
6198 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6199 {
6200         struct vcpu_vmx *vmx = to_vmx(vcpu);
6201         enum emulation_result err = EMULATE_DONE;
6202         int ret = 1;
6203         u32 cpu_exec_ctrl;
6204         bool intr_window_requested;
6205         unsigned count = 130;
6206
6207         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6208         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6209
6210         while (vmx->emulation_required && count-- != 0) {
6211                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6212                         return handle_interrupt_window(&vmx->vcpu);
6213
6214                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
6215                         return 1;
6216
6217                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
6218
6219                 if (err == EMULATE_USER_EXIT) {
6220                         ++vcpu->stat.mmio_exits;
6221                         ret = 0;
6222                         goto out;
6223                 }
6224
6225                 if (err != EMULATE_DONE) {
6226                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6227                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6228                         vcpu->run->internal.ndata = 0;
6229                         return 0;
6230                 }
6231
6232                 if (vcpu->arch.halt_request) {
6233                         vcpu->arch.halt_request = 0;
6234                         ret = kvm_vcpu_halt(vcpu);
6235                         goto out;
6236                 }
6237
6238                 if (signal_pending(current))
6239                         goto out;
6240                 if (need_resched())
6241                         schedule();
6242         }
6243
6244 out:
6245         return ret;
6246 }
6247
6248 static int __grow_ple_window(int val)
6249 {
6250         if (ple_window_grow < 1)
6251                 return ple_window;
6252
6253         val = min(val, ple_window_actual_max);
6254
6255         if (ple_window_grow < ple_window)
6256                 val *= ple_window_grow;
6257         else
6258                 val += ple_window_grow;
6259
6260         return val;
6261 }
6262
6263 static int __shrink_ple_window(int val, int modifier, int minimum)
6264 {
6265         if (modifier < 1)
6266                 return ple_window;
6267
6268         if (modifier < ple_window)
6269                 val /= modifier;
6270         else
6271                 val -= modifier;
6272
6273         return max(val, minimum);
6274 }
6275
6276 static void grow_ple_window(struct kvm_vcpu *vcpu)
6277 {
6278         struct vcpu_vmx *vmx = to_vmx(vcpu);
6279         int old = vmx->ple_window;
6280
6281         vmx->ple_window = __grow_ple_window(old);
6282
6283         if (vmx->ple_window != old)
6284                 vmx->ple_window_dirty = true;
6285
6286         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6287 }
6288
6289 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6290 {
6291         struct vcpu_vmx *vmx = to_vmx(vcpu);
6292         int old = vmx->ple_window;
6293
6294         vmx->ple_window = __shrink_ple_window(old,
6295                                               ple_window_shrink, ple_window);
6296
6297         if (vmx->ple_window != old)
6298                 vmx->ple_window_dirty = true;
6299
6300         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6301 }
6302
6303 /*
6304  * ple_window_actual_max is computed to be one grow_ple_window() below
6305  * ple_window_max. (See __grow_ple_window for the reason.)
6306  * This prevents overflows, because ple_window_max is int.
6307  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6308  * this process.
6309  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6310  */
6311 static void update_ple_window_actual_max(void)
6312 {
6313         ple_window_actual_max =
6314                         __shrink_ple_window(max(ple_window_max, ple_window),
6315                                             ple_window_grow, INT_MIN);
6316 }
6317
6318 /*
6319  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6320  */
6321 static void wakeup_handler(void)
6322 {
6323         struct kvm_vcpu *vcpu;
6324         int cpu = smp_processor_id();
6325
6326         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6327         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6328                         blocked_vcpu_list) {
6329                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6330
6331                 if (pi_test_on(pi_desc) == 1)
6332                         kvm_vcpu_kick(vcpu);
6333         }
6334         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6335 }
6336
6337 static __init int hardware_setup(void)
6338 {
6339         int r = -ENOMEM, i, msr;
6340
6341         rdmsrl_safe(MSR_EFER, &host_efer);
6342
6343         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6344                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6345
6346         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6347         if (!vmx_io_bitmap_a)
6348                 return r;
6349
6350         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6351         if (!vmx_io_bitmap_b)
6352                 goto out;
6353
6354         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6355         if (!vmx_msr_bitmap_legacy)
6356                 goto out1;
6357
6358         vmx_msr_bitmap_legacy_x2apic =
6359                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6360         if (!vmx_msr_bitmap_legacy_x2apic)
6361                 goto out2;
6362
6363         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6364         if (!vmx_msr_bitmap_longmode)
6365                 goto out3;
6366
6367         vmx_msr_bitmap_longmode_x2apic =
6368                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6369         if (!vmx_msr_bitmap_longmode_x2apic)
6370                 goto out4;
6371
6372         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6373         if (!vmx_vmread_bitmap)
6374                 goto out6;
6375
6376         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6377         if (!vmx_vmwrite_bitmap)
6378                 goto out7;
6379
6380         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6381         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6382
6383         /*
6384          * Allow direct access to the PC debug port (it is often used for I/O
6385          * delays, but the vmexits simply slow things down).
6386          */
6387         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6388         clear_bit(0x80, vmx_io_bitmap_a);
6389
6390         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6391
6392         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6393         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6394
6395         if (setup_vmcs_config(&vmcs_config) < 0) {
6396                 r = -EIO;
6397                 goto out8;
6398         }
6399
6400         if (boot_cpu_has(X86_FEATURE_NX))
6401                 kvm_enable_efer_bits(EFER_NX);
6402
6403         if (!cpu_has_vmx_vpid())
6404                 enable_vpid = 0;
6405         if (!cpu_has_vmx_shadow_vmcs())
6406                 enable_shadow_vmcs = 0;
6407         if (enable_shadow_vmcs)
6408                 init_vmcs_shadow_fields();
6409
6410         if (!cpu_has_vmx_ept() ||
6411             !cpu_has_vmx_ept_4levels()) {
6412                 enable_ept = 0;
6413                 enable_unrestricted_guest = 0;
6414                 enable_ept_ad_bits = 0;
6415         }
6416
6417         if (!cpu_has_vmx_ept_ad_bits())
6418                 enable_ept_ad_bits = 0;
6419
6420         if (!cpu_has_vmx_unrestricted_guest())
6421                 enable_unrestricted_guest = 0;
6422
6423         if (!cpu_has_vmx_flexpriority())
6424                 flexpriority_enabled = 0;
6425
6426         /*
6427          * set_apic_access_page_addr() is used to reload apic access
6428          * page upon invalidation.  No need to do anything if not
6429          * using the APIC_ACCESS_ADDR VMCS field.
6430          */
6431         if (!flexpriority_enabled)
6432                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6433
6434         if (!cpu_has_vmx_tpr_shadow())
6435                 kvm_x86_ops->update_cr8_intercept = NULL;
6436
6437         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6438                 kvm_disable_largepages();
6439
6440         if (!cpu_has_vmx_ple())
6441                 ple_gap = 0;
6442
6443         if (!cpu_has_vmx_apicv())
6444                 enable_apicv = 0;
6445
6446         if (cpu_has_vmx_tsc_scaling()) {
6447                 kvm_has_tsc_control = true;
6448                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6449                 kvm_tsc_scaling_ratio_frac_bits = 48;
6450         }
6451
6452         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6453         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6454         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6455         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6456         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6457         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6458         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6459
6460         memcpy(vmx_msr_bitmap_legacy_x2apic,
6461                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6462         memcpy(vmx_msr_bitmap_longmode_x2apic,
6463                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6464
6465         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6466
6467         for (msr = 0x800; msr <= 0x8ff; msr++)
6468                 vmx_disable_intercept_msr_read_x2apic(msr);
6469
6470         /* TMCCT */
6471         vmx_enable_intercept_msr_read_x2apic(0x839);
6472         /* TPR */
6473         vmx_disable_intercept_msr_write_x2apic(0x808);
6474         /* EOI */
6475         vmx_disable_intercept_msr_write_x2apic(0x80b);
6476         /* SELF-IPI */
6477         vmx_disable_intercept_msr_write_x2apic(0x83f);
6478
6479         if (enable_ept) {
6480                 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
6481                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6482                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6483                         0ull, VMX_EPT_EXECUTABLE_MASK,
6484                         cpu_has_vmx_ept_execute_only() ?
6485                                       0ull : VMX_EPT_READABLE_MASK);
6486                 ept_set_mmio_spte_mask();
6487                 kvm_enable_tdp();
6488         } else
6489                 kvm_disable_tdp();
6490
6491         update_ple_window_actual_max();
6492
6493         /*
6494          * Only enable PML when hardware supports PML feature, and both EPT
6495          * and EPT A/D bit features are enabled -- PML depends on them to work.
6496          */
6497         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6498                 enable_pml = 0;
6499
6500         if (!enable_pml) {
6501                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6502                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6503                 kvm_x86_ops->flush_log_dirty = NULL;
6504                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6505         }
6506
6507         if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
6508                 u64 vmx_msr;
6509
6510                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
6511                 cpu_preemption_timer_multi =
6512                          vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
6513         } else {
6514                 kvm_x86_ops->set_hv_timer = NULL;
6515                 kvm_x86_ops->cancel_hv_timer = NULL;
6516         }
6517
6518         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6519
6520         kvm_mce_cap_supported |= MCG_LMCE_P;
6521
6522         return alloc_kvm_area();
6523
6524 out8:
6525         free_page((unsigned long)vmx_vmwrite_bitmap);
6526 out7:
6527         free_page((unsigned long)vmx_vmread_bitmap);
6528 out6:
6529         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6530 out4:
6531         free_page((unsigned long)vmx_msr_bitmap_longmode);
6532 out3:
6533         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6534 out2:
6535         free_page((unsigned long)vmx_msr_bitmap_legacy);
6536 out1:
6537         free_page((unsigned long)vmx_io_bitmap_b);
6538 out:
6539         free_page((unsigned long)vmx_io_bitmap_a);
6540
6541     return r;
6542 }
6543
6544 static __exit void hardware_unsetup(void)
6545 {
6546         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6547         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6548         free_page((unsigned long)vmx_msr_bitmap_legacy);
6549         free_page((unsigned long)vmx_msr_bitmap_longmode);
6550         free_page((unsigned long)vmx_io_bitmap_b);
6551         free_page((unsigned long)vmx_io_bitmap_a);
6552         free_page((unsigned long)vmx_vmwrite_bitmap);
6553         free_page((unsigned long)vmx_vmread_bitmap);
6554
6555         free_kvm_area();
6556 }
6557
6558 /*
6559  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6560  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6561  */
6562 static int handle_pause(struct kvm_vcpu *vcpu)
6563 {
6564         if (ple_gap)
6565                 grow_ple_window(vcpu);
6566
6567         skip_emulated_instruction(vcpu);
6568         kvm_vcpu_on_spin(vcpu);
6569
6570         return 1;
6571 }
6572
6573 static int handle_nop(struct kvm_vcpu *vcpu)
6574 {
6575         skip_emulated_instruction(vcpu);
6576         return 1;
6577 }
6578
6579 static int handle_mwait(struct kvm_vcpu *vcpu)
6580 {
6581         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6582         return handle_nop(vcpu);
6583 }
6584
6585 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6586 {
6587         return 1;
6588 }
6589
6590 static int handle_monitor(struct kvm_vcpu *vcpu)
6591 {
6592         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6593         return handle_nop(vcpu);
6594 }
6595
6596 /*
6597  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6598  * We could reuse a single VMCS for all the L2 guests, but we also want the
6599  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6600  * allows keeping them loaded on the processor, and in the future will allow
6601  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6602  * every entry if they never change.
6603  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6604  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6605  *
6606  * The following functions allocate and free a vmcs02 in this pool.
6607  */
6608
6609 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6610 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6611 {
6612         struct vmcs02_list *item;
6613         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6614                 if (item->vmptr == vmx->nested.current_vmptr) {
6615                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6616                         return &item->vmcs02;
6617                 }
6618
6619         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6620                 /* Recycle the least recently used VMCS. */
6621                 item = list_last_entry(&vmx->nested.vmcs02_pool,
6622                                        struct vmcs02_list, list);
6623                 item->vmptr = vmx->nested.current_vmptr;
6624                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6625                 return &item->vmcs02;
6626         }
6627
6628         /* Create a new VMCS */
6629         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6630         if (!item)
6631                 return NULL;
6632         item->vmcs02.vmcs = alloc_vmcs();
6633         if (!item->vmcs02.vmcs) {
6634                 kfree(item);
6635                 return NULL;
6636         }
6637         loaded_vmcs_init(&item->vmcs02);
6638         item->vmptr = vmx->nested.current_vmptr;
6639         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6640         vmx->nested.vmcs02_num++;
6641         return &item->vmcs02;
6642 }
6643
6644 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6645 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6646 {
6647         struct vmcs02_list *item;
6648         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6649                 if (item->vmptr == vmptr) {
6650                         free_loaded_vmcs(&item->vmcs02);
6651                         list_del(&item->list);
6652                         kfree(item);
6653                         vmx->nested.vmcs02_num--;
6654                         return;
6655                 }
6656 }
6657
6658 /*
6659  * Free all VMCSs saved for this vcpu, except the one pointed by
6660  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6661  * must be &vmx->vmcs01.
6662  */
6663 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6664 {
6665         struct vmcs02_list *item, *n;
6666
6667         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6668         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6669                 /*
6670                  * Something will leak if the above WARN triggers.  Better than
6671                  * a use-after-free.
6672                  */
6673                 if (vmx->loaded_vmcs == &item->vmcs02)
6674                         continue;
6675
6676                 free_loaded_vmcs(&item->vmcs02);
6677                 list_del(&item->list);
6678                 kfree(item);
6679                 vmx->nested.vmcs02_num--;
6680         }
6681 }
6682
6683 /*
6684  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6685  * set the success or error code of an emulated VMX instruction, as specified
6686  * by Vol 2B, VMX Instruction Reference, "Conventions".
6687  */
6688 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6689 {
6690         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6691                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6692                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6693 }
6694
6695 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6696 {
6697         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6698                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6699                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6700                         | X86_EFLAGS_CF);
6701 }
6702
6703 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6704                                         u32 vm_instruction_error)
6705 {
6706         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6707                 /*
6708                  * failValid writes the error number to the current VMCS, which
6709                  * can't be done there isn't a current VMCS.
6710                  */
6711                 nested_vmx_failInvalid(vcpu);
6712                 return;
6713         }
6714         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6715                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6716                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6717                         | X86_EFLAGS_ZF);
6718         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6719         /*
6720          * We don't need to force a shadow sync because
6721          * VM_INSTRUCTION_ERROR is not shadowed
6722          */
6723 }
6724
6725 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6726 {
6727         /* TODO: not to reset guest simply here. */
6728         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6729         pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6730 }
6731
6732 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6733 {
6734         struct vcpu_vmx *vmx =
6735                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6736
6737         vmx->nested.preemption_timer_expired = true;
6738         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6739         kvm_vcpu_kick(&vmx->vcpu);
6740
6741         return HRTIMER_NORESTART;
6742 }
6743
6744 /*
6745  * Decode the memory-address operand of a vmx instruction, as recorded on an
6746  * exit caused by such an instruction (run by a guest hypervisor).
6747  * On success, returns 0. When the operand is invalid, returns 1 and throws
6748  * #UD or #GP.
6749  */
6750 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6751                                  unsigned long exit_qualification,
6752                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
6753 {
6754         gva_t off;
6755         bool exn;
6756         struct kvm_segment s;
6757
6758         /*
6759          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6760          * Execution", on an exit, vmx_instruction_info holds most of the
6761          * addressing components of the operand. Only the displacement part
6762          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6763          * For how an actual address is calculated from all these components,
6764          * refer to Vol. 1, "Operand Addressing".
6765          */
6766         int  scaling = vmx_instruction_info & 3;
6767         int  addr_size = (vmx_instruction_info >> 7) & 7;
6768         bool is_reg = vmx_instruction_info & (1u << 10);
6769         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6770         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6771         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6772         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6773         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6774
6775         if (is_reg) {
6776                 kvm_queue_exception(vcpu, UD_VECTOR);
6777                 return 1;
6778         }
6779
6780         /* Addr = segment_base + offset */
6781         /* offset = base + [index * scale] + displacement */
6782         off = exit_qualification; /* holds the displacement */
6783         if (base_is_valid)
6784                 off += kvm_register_read(vcpu, base_reg);
6785         if (index_is_valid)
6786                 off += kvm_register_read(vcpu, index_reg)<<scaling;
6787         vmx_get_segment(vcpu, &s, seg_reg);
6788         *ret = s.base + off;
6789
6790         if (addr_size == 1) /* 32 bit */
6791                 *ret &= 0xffffffff;
6792
6793         /* Checks for #GP/#SS exceptions. */
6794         exn = false;
6795         if (is_long_mode(vcpu)) {
6796                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6797                  * non-canonical form. This is the only check on the memory
6798                  * destination for long mode!
6799                  */
6800                 exn = is_noncanonical_address(*ret);
6801         } else if (is_protmode(vcpu)) {
6802                 /* Protected mode: apply checks for segment validity in the
6803                  * following order:
6804                  * - segment type check (#GP(0) may be thrown)
6805                  * - usability check (#GP(0)/#SS(0))
6806                  * - limit check (#GP(0)/#SS(0))
6807                  */
6808                 if (wr)
6809                         /* #GP(0) if the destination operand is located in a
6810                          * read-only data segment or any code segment.
6811                          */
6812                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
6813                 else
6814                         /* #GP(0) if the source operand is located in an
6815                          * execute-only code segment
6816                          */
6817                         exn = ((s.type & 0xa) == 8);
6818                 if (exn) {
6819                         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6820                         return 1;
6821                 }
6822                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6823                  */
6824                 exn = (s.unusable != 0);
6825                 /* Protected mode: #GP(0)/#SS(0) if the memory
6826                  * operand is outside the segment limit.
6827                  */
6828                 exn = exn || (off + sizeof(u64) > s.limit);
6829         }
6830         if (exn) {
6831                 kvm_queue_exception_e(vcpu,
6832                                       seg_reg == VCPU_SREG_SS ?
6833                                                 SS_VECTOR : GP_VECTOR,
6834                                       0);
6835                 return 1;
6836         }
6837
6838         return 0;
6839 }
6840
6841 /*
6842  * This function performs the various checks including
6843  * - if it's 4KB aligned
6844  * - No bits beyond the physical address width are set
6845  * - Returns 0 on success or else 1
6846  * (Intel SDM Section 30.3)
6847  */
6848 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6849                                   gpa_t *vmpointer)
6850 {
6851         gva_t gva;
6852         gpa_t vmptr;
6853         struct x86_exception e;
6854         struct page *page;
6855         struct vcpu_vmx *vmx = to_vmx(vcpu);
6856         int maxphyaddr = cpuid_maxphyaddr(vcpu);
6857
6858         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6859                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6860                 return 1;
6861
6862         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6863                                 sizeof(vmptr), &e)) {
6864                 kvm_inject_page_fault(vcpu, &e);
6865                 return 1;
6866         }
6867
6868         switch (exit_reason) {
6869         case EXIT_REASON_VMON:
6870                 /*
6871                  * SDM 3: 24.11.5
6872                  * The first 4 bytes of VMXON region contain the supported
6873                  * VMCS revision identifier
6874                  *
6875                  * Note - IA32_VMX_BASIC[48] will never be 1
6876                  * for the nested case;
6877                  * which replaces physical address width with 32
6878                  *
6879                  */
6880                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6881                         nested_vmx_failInvalid(vcpu);
6882                         skip_emulated_instruction(vcpu);
6883                         return 1;
6884                 }
6885
6886                 page = nested_get_page(vcpu, vmptr);
6887                 if (page == NULL ||
6888                     *(u32 *)kmap(page) != VMCS12_REVISION) {
6889                         nested_vmx_failInvalid(vcpu);
6890                         kunmap(page);
6891                         skip_emulated_instruction(vcpu);
6892                         return 1;
6893                 }
6894                 kunmap(page);
6895                 vmx->nested.vmxon_ptr = vmptr;
6896                 break;
6897         case EXIT_REASON_VMCLEAR:
6898                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6899                         nested_vmx_failValid(vcpu,
6900                                              VMXERR_VMCLEAR_INVALID_ADDRESS);
6901                         skip_emulated_instruction(vcpu);
6902                         return 1;
6903                 }
6904
6905                 if (vmptr == vmx->nested.vmxon_ptr) {
6906                         nested_vmx_failValid(vcpu,
6907                                              VMXERR_VMCLEAR_VMXON_POINTER);
6908                         skip_emulated_instruction(vcpu);
6909                         return 1;
6910                 }
6911                 break;
6912         case EXIT_REASON_VMPTRLD:
6913                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6914                         nested_vmx_failValid(vcpu,
6915                                              VMXERR_VMPTRLD_INVALID_ADDRESS);
6916                         skip_emulated_instruction(vcpu);
6917                         return 1;
6918                 }
6919
6920                 if (vmptr == vmx->nested.vmxon_ptr) {
6921                         nested_vmx_failValid(vcpu,
6922                                              VMXERR_VMCLEAR_VMXON_POINTER);
6923                         skip_emulated_instruction(vcpu);
6924                         return 1;
6925                 }
6926                 break;
6927         default:
6928                 return 1; /* shouldn't happen */
6929         }
6930
6931         if (vmpointer)
6932                 *vmpointer = vmptr;
6933         return 0;
6934 }
6935
6936 /*
6937  * Emulate the VMXON instruction.
6938  * Currently, we just remember that VMX is active, and do not save or even
6939  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6940  * do not currently need to store anything in that guest-allocated memory
6941  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6942  * argument is different from the VMXON pointer (which the spec says they do).
6943  */
6944 static int handle_vmon(struct kvm_vcpu *vcpu)
6945 {
6946         struct kvm_segment cs;
6947         struct vcpu_vmx *vmx = to_vmx(vcpu);
6948         struct vmcs *shadow_vmcs;
6949         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6950                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6951
6952         /* The Intel VMX Instruction Reference lists a bunch of bits that
6953          * are prerequisite to running VMXON, most notably cr4.VMXE must be
6954          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6955          * Otherwise, we should fail with #UD. We test these now:
6956          */
6957         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6958             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6959             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6960                 kvm_queue_exception(vcpu, UD_VECTOR);
6961                 return 1;
6962         }
6963
6964         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6965         if (is_long_mode(vcpu) && !cs.l) {
6966                 kvm_queue_exception(vcpu, UD_VECTOR);
6967                 return 1;
6968         }
6969
6970         if (vmx_get_cpl(vcpu)) {
6971                 kvm_inject_gp(vcpu, 0);
6972                 return 1;
6973         }
6974
6975         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
6976                 return 1;
6977
6978         if (vmx->nested.vmxon) {
6979                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6980                 skip_emulated_instruction(vcpu);
6981                 return 1;
6982         }
6983
6984         if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6985                         != VMXON_NEEDED_FEATURES) {
6986                 kvm_inject_gp(vcpu, 0);
6987                 return 1;
6988         }
6989
6990         if (cpu_has_vmx_msr_bitmap()) {
6991                 vmx->nested.msr_bitmap =
6992                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6993                 if (!vmx->nested.msr_bitmap)
6994                         goto out_msr_bitmap;
6995         }
6996
6997         vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
6998         if (!vmx->nested.cached_vmcs12)
6999                 goto out_cached_vmcs12;
7000
7001         if (enable_shadow_vmcs) {
7002                 shadow_vmcs = alloc_vmcs();
7003                 if (!shadow_vmcs)
7004                         goto out_shadow_vmcs;
7005                 /* mark vmcs as shadow */
7006                 shadow_vmcs->revision_id |= (1u << 31);
7007                 /* init shadow vmcs */
7008                 vmcs_clear(shadow_vmcs);
7009                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
7010         }
7011
7012         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
7013         vmx->nested.vmcs02_num = 0;
7014
7015         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
7016                      HRTIMER_MODE_REL);
7017         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
7018
7019         vmx->nested.vmxon = true;
7020
7021         skip_emulated_instruction(vcpu);
7022         nested_vmx_succeed(vcpu);
7023         return 1;
7024
7025 out_shadow_vmcs:
7026         kfree(vmx->nested.cached_vmcs12);
7027
7028 out_cached_vmcs12:
7029         free_page((unsigned long)vmx->nested.msr_bitmap);
7030
7031 out_msr_bitmap:
7032         return -ENOMEM;
7033 }
7034
7035 /*
7036  * Intel's VMX Instruction Reference specifies a common set of prerequisites
7037  * for running VMX instructions (except VMXON, whose prerequisites are
7038  * slightly different). It also specifies what exception to inject otherwise.
7039  */
7040 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7041 {
7042         struct kvm_segment cs;
7043         struct vcpu_vmx *vmx = to_vmx(vcpu);
7044
7045         if (!vmx->nested.vmxon) {
7046                 kvm_queue_exception(vcpu, UD_VECTOR);
7047                 return 0;
7048         }
7049
7050         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
7051         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
7052             (is_long_mode(vcpu) && !cs.l)) {
7053                 kvm_queue_exception(vcpu, UD_VECTOR);
7054                 return 0;
7055         }
7056
7057         if (vmx_get_cpl(vcpu)) {
7058                 kvm_inject_gp(vcpu, 0);
7059                 return 0;
7060         }
7061
7062         return 1;
7063 }
7064
7065 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7066 {
7067         if (vmx->nested.current_vmptr == -1ull)
7068                 return;
7069
7070         /* current_vmptr and current_vmcs12 are always set/reset together */
7071         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
7072                 return;
7073
7074         if (enable_shadow_vmcs) {
7075                 /* copy to memory all shadowed fields in case
7076                    they were modified */
7077                 copy_shadow_to_vmcs12(vmx);
7078                 vmx->nested.sync_shadow_vmcs = false;
7079                 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
7080                                 SECONDARY_EXEC_SHADOW_VMCS);
7081                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7082         }
7083         vmx->nested.posted_intr_nv = -1;
7084
7085         /* Flush VMCS12 to guest memory */
7086         memcpy(vmx->nested.current_vmcs12, vmx->nested.cached_vmcs12,
7087                VMCS12_SIZE);
7088
7089         kunmap(vmx->nested.current_vmcs12_page);
7090         nested_release_page(vmx->nested.current_vmcs12_page);
7091         vmx->nested.current_vmptr = -1ull;
7092         vmx->nested.current_vmcs12 = NULL;
7093 }
7094
7095 /*
7096  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7097  * just stops using VMX.
7098  */
7099 static void free_nested(struct vcpu_vmx *vmx)
7100 {
7101         if (!vmx->nested.vmxon)
7102                 return;
7103
7104         vmx->nested.vmxon = false;
7105         free_vpid(vmx->nested.vpid02);
7106         nested_release_vmcs12(vmx);
7107         if (vmx->nested.msr_bitmap) {
7108                 free_page((unsigned long)vmx->nested.msr_bitmap);
7109                 vmx->nested.msr_bitmap = NULL;
7110         }
7111         if (enable_shadow_vmcs)
7112                 free_vmcs(vmx->nested.current_shadow_vmcs);
7113         kfree(vmx->nested.cached_vmcs12);
7114         /* Unpin physical memory we referred to in current vmcs02 */
7115         if (vmx->nested.apic_access_page) {
7116                 nested_release_page(vmx->nested.apic_access_page);
7117                 vmx->nested.apic_access_page = NULL;
7118         }
7119         if (vmx->nested.virtual_apic_page) {
7120                 nested_release_page(vmx->nested.virtual_apic_page);
7121                 vmx->nested.virtual_apic_page = NULL;
7122         }
7123         if (vmx->nested.pi_desc_page) {
7124                 kunmap(vmx->nested.pi_desc_page);
7125                 nested_release_page(vmx->nested.pi_desc_page);
7126                 vmx->nested.pi_desc_page = NULL;
7127                 vmx->nested.pi_desc = NULL;
7128         }
7129
7130         nested_free_all_saved_vmcss(vmx);
7131 }
7132
7133 /* Emulate the VMXOFF instruction */
7134 static int handle_vmoff(struct kvm_vcpu *vcpu)
7135 {
7136         if (!nested_vmx_check_permission(vcpu))
7137                 return 1;
7138         free_nested(to_vmx(vcpu));
7139         skip_emulated_instruction(vcpu);
7140         nested_vmx_succeed(vcpu);
7141         return 1;
7142 }
7143
7144 /* Emulate the VMCLEAR instruction */
7145 static int handle_vmclear(struct kvm_vcpu *vcpu)
7146 {
7147         struct vcpu_vmx *vmx = to_vmx(vcpu);
7148         gpa_t vmptr;
7149         struct vmcs12 *vmcs12;
7150         struct page *page;
7151
7152         if (!nested_vmx_check_permission(vcpu))
7153                 return 1;
7154
7155         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
7156                 return 1;
7157
7158         if (vmptr == vmx->nested.current_vmptr)
7159                 nested_release_vmcs12(vmx);
7160
7161         page = nested_get_page(vcpu, vmptr);
7162         if (page == NULL) {
7163                 /*
7164                  * For accurate processor emulation, VMCLEAR beyond available
7165                  * physical memory should do nothing at all. However, it is
7166                  * possible that a nested vmx bug, not a guest hypervisor bug,
7167                  * resulted in this case, so let's shut down before doing any
7168                  * more damage:
7169                  */
7170                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7171                 return 1;
7172         }
7173         vmcs12 = kmap(page);
7174         vmcs12->launch_state = 0;
7175         kunmap(page);
7176         nested_release_page(page);
7177
7178         nested_free_vmcs02(vmx, vmptr);
7179
7180         skip_emulated_instruction(vcpu);
7181         nested_vmx_succeed(vcpu);
7182         return 1;
7183 }
7184
7185 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7186
7187 /* Emulate the VMLAUNCH instruction */
7188 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7189 {
7190         return nested_vmx_run(vcpu, true);
7191 }
7192
7193 /* Emulate the VMRESUME instruction */
7194 static int handle_vmresume(struct kvm_vcpu *vcpu)
7195 {
7196
7197         return nested_vmx_run(vcpu, false);
7198 }
7199
7200 enum vmcs_field_type {
7201         VMCS_FIELD_TYPE_U16 = 0,
7202         VMCS_FIELD_TYPE_U64 = 1,
7203         VMCS_FIELD_TYPE_U32 = 2,
7204         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
7205 };
7206
7207 static inline int vmcs_field_type(unsigned long field)
7208 {
7209         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
7210                 return VMCS_FIELD_TYPE_U32;
7211         return (field >> 13) & 0x3 ;
7212 }
7213
7214 static inline int vmcs_field_readonly(unsigned long field)
7215 {
7216         return (((field >> 10) & 0x3) == 1);
7217 }
7218
7219 /*
7220  * Read a vmcs12 field. Since these can have varying lengths and we return
7221  * one type, we chose the biggest type (u64) and zero-extend the return value
7222  * to that size. Note that the caller, handle_vmread, might need to use only
7223  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7224  * 64-bit fields are to be returned).
7225  */
7226 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7227                                   unsigned long field, u64 *ret)
7228 {
7229         short offset = vmcs_field_to_offset(field);
7230         char *p;
7231
7232         if (offset < 0)
7233                 return offset;
7234
7235         p = ((char *)(get_vmcs12(vcpu))) + offset;
7236
7237         switch (vmcs_field_type(field)) {
7238         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7239                 *ret = *((natural_width *)p);
7240                 return 0;
7241         case VMCS_FIELD_TYPE_U16:
7242                 *ret = *((u16 *)p);
7243                 return 0;
7244         case VMCS_FIELD_TYPE_U32:
7245                 *ret = *((u32 *)p);
7246                 return 0;
7247         case VMCS_FIELD_TYPE_U64:
7248                 *ret = *((u64 *)p);
7249                 return 0;
7250         default:
7251                 WARN_ON(1);
7252                 return -ENOENT;
7253         }
7254 }
7255
7256
7257 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7258                                    unsigned long field, u64 field_value){
7259         short offset = vmcs_field_to_offset(field);
7260         char *p = ((char *) get_vmcs12(vcpu)) + offset;
7261         if (offset < 0)
7262                 return offset;
7263
7264         switch (vmcs_field_type(field)) {
7265         case VMCS_FIELD_TYPE_U16:
7266                 *(u16 *)p = field_value;
7267                 return 0;
7268         case VMCS_FIELD_TYPE_U32:
7269                 *(u32 *)p = field_value;
7270                 return 0;
7271         case VMCS_FIELD_TYPE_U64:
7272                 *(u64 *)p = field_value;
7273                 return 0;
7274         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7275                 *(natural_width *)p = field_value;
7276                 return 0;
7277         default:
7278                 WARN_ON(1);
7279                 return -ENOENT;
7280         }
7281
7282 }
7283
7284 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7285 {
7286         int i;
7287         unsigned long field;
7288         u64 field_value;
7289         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7290         const unsigned long *fields = shadow_read_write_fields;
7291         const int num_fields = max_shadow_read_write_fields;
7292
7293         preempt_disable();
7294
7295         vmcs_load(shadow_vmcs);
7296
7297         for (i = 0; i < num_fields; i++) {
7298                 field = fields[i];
7299                 switch (vmcs_field_type(field)) {
7300                 case VMCS_FIELD_TYPE_U16:
7301                         field_value = vmcs_read16(field);
7302                         break;
7303                 case VMCS_FIELD_TYPE_U32:
7304                         field_value = vmcs_read32(field);
7305                         break;
7306                 case VMCS_FIELD_TYPE_U64:
7307                         field_value = vmcs_read64(field);
7308                         break;
7309                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7310                         field_value = vmcs_readl(field);
7311                         break;
7312                 default:
7313                         WARN_ON(1);
7314                         continue;
7315                 }
7316                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7317         }
7318
7319         vmcs_clear(shadow_vmcs);
7320         vmcs_load(vmx->loaded_vmcs->vmcs);
7321
7322         preempt_enable();
7323 }
7324
7325 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7326 {
7327         const unsigned long *fields[] = {
7328                 shadow_read_write_fields,
7329                 shadow_read_only_fields
7330         };
7331         const int max_fields[] = {
7332                 max_shadow_read_write_fields,
7333                 max_shadow_read_only_fields
7334         };
7335         int i, q;
7336         unsigned long field;
7337         u64 field_value = 0;
7338         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7339
7340         vmcs_load(shadow_vmcs);
7341
7342         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7343                 for (i = 0; i < max_fields[q]; i++) {
7344                         field = fields[q][i];
7345                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7346
7347                         switch (vmcs_field_type(field)) {
7348                         case VMCS_FIELD_TYPE_U16:
7349                                 vmcs_write16(field, (u16)field_value);
7350                                 break;
7351                         case VMCS_FIELD_TYPE_U32:
7352                                 vmcs_write32(field, (u32)field_value);
7353                                 break;
7354                         case VMCS_FIELD_TYPE_U64:
7355                                 vmcs_write64(field, (u64)field_value);
7356                                 break;
7357                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7358                                 vmcs_writel(field, (long)field_value);
7359                                 break;
7360                         default:
7361                                 WARN_ON(1);
7362                                 break;
7363                         }
7364                 }
7365         }
7366
7367         vmcs_clear(shadow_vmcs);
7368         vmcs_load(vmx->loaded_vmcs->vmcs);
7369 }
7370
7371 /*
7372  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7373  * used before) all generate the same failure when it is missing.
7374  */
7375 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7376 {
7377         struct vcpu_vmx *vmx = to_vmx(vcpu);
7378         if (vmx->nested.current_vmptr == -1ull) {
7379                 nested_vmx_failInvalid(vcpu);
7380                 skip_emulated_instruction(vcpu);
7381                 return 0;
7382         }
7383         return 1;
7384 }
7385
7386 static int handle_vmread(struct kvm_vcpu *vcpu)
7387 {
7388         unsigned long field;
7389         u64 field_value;
7390         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7391         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7392         gva_t gva = 0;
7393
7394         if (!nested_vmx_check_permission(vcpu) ||
7395             !nested_vmx_check_vmcs12(vcpu))
7396                 return 1;
7397
7398         /* Decode instruction info and find the field to read */
7399         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7400         /* Read the field, zero-extended to a u64 field_value */
7401         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7402                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7403                 skip_emulated_instruction(vcpu);
7404                 return 1;
7405         }
7406         /*
7407          * Now copy part of this value to register or memory, as requested.
7408          * Note that the number of bits actually copied is 32 or 64 depending
7409          * on the guest's mode (32 or 64 bit), not on the given field's length.
7410          */
7411         if (vmx_instruction_info & (1u << 10)) {
7412                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7413                         field_value);
7414         } else {
7415                 if (get_vmx_mem_address(vcpu, exit_qualification,
7416                                 vmx_instruction_info, true, &gva))
7417                         return 1;
7418                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7419                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7420                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7421         }
7422
7423         nested_vmx_succeed(vcpu);
7424         skip_emulated_instruction(vcpu);
7425         return 1;
7426 }
7427
7428
7429 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7430 {
7431         unsigned long field;
7432         gva_t gva;
7433         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7434         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7435         /* The value to write might be 32 or 64 bits, depending on L1's long
7436          * mode, and eventually we need to write that into a field of several
7437          * possible lengths. The code below first zero-extends the value to 64
7438          * bit (field_value), and then copies only the appropriate number of
7439          * bits into the vmcs12 field.
7440          */
7441         u64 field_value = 0;
7442         struct x86_exception e;
7443
7444         if (!nested_vmx_check_permission(vcpu) ||
7445             !nested_vmx_check_vmcs12(vcpu))
7446                 return 1;
7447
7448         if (vmx_instruction_info & (1u << 10))
7449                 field_value = kvm_register_readl(vcpu,
7450                         (((vmx_instruction_info) >> 3) & 0xf));
7451         else {
7452                 if (get_vmx_mem_address(vcpu, exit_qualification,
7453                                 vmx_instruction_info, false, &gva))
7454                         return 1;
7455                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7456                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7457                         kvm_inject_page_fault(vcpu, &e);
7458                         return 1;
7459                 }
7460         }
7461
7462
7463         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7464         if (vmcs_field_readonly(field)) {
7465                 nested_vmx_failValid(vcpu,
7466                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7467                 skip_emulated_instruction(vcpu);
7468                 return 1;
7469         }
7470
7471         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7472                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7473                 skip_emulated_instruction(vcpu);
7474                 return 1;
7475         }
7476
7477         nested_vmx_succeed(vcpu);
7478         skip_emulated_instruction(vcpu);
7479         return 1;
7480 }
7481
7482 /* Emulate the VMPTRLD instruction */
7483 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7484 {
7485         struct vcpu_vmx *vmx = to_vmx(vcpu);
7486         gpa_t vmptr;
7487
7488         if (!nested_vmx_check_permission(vcpu))
7489                 return 1;
7490
7491         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7492                 return 1;
7493
7494         if (vmx->nested.current_vmptr != vmptr) {
7495                 struct vmcs12 *new_vmcs12;
7496                 struct page *page;
7497                 page = nested_get_page(vcpu, vmptr);
7498                 if (page == NULL) {
7499                         nested_vmx_failInvalid(vcpu);
7500                         skip_emulated_instruction(vcpu);
7501                         return 1;
7502                 }
7503                 new_vmcs12 = kmap(page);
7504                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7505                         kunmap(page);
7506                         nested_release_page_clean(page);
7507                         nested_vmx_failValid(vcpu,
7508                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7509                         skip_emulated_instruction(vcpu);
7510                         return 1;
7511                 }
7512
7513                 nested_release_vmcs12(vmx);
7514                 vmx->nested.current_vmptr = vmptr;
7515                 vmx->nested.current_vmcs12 = new_vmcs12;
7516                 vmx->nested.current_vmcs12_page = page;
7517                 /*
7518                  * Load VMCS12 from guest memory since it is not already
7519                  * cached.
7520                  */
7521                 memcpy(vmx->nested.cached_vmcs12,
7522                        vmx->nested.current_vmcs12, VMCS12_SIZE);
7523
7524                 if (enable_shadow_vmcs) {
7525                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7526                                       SECONDARY_EXEC_SHADOW_VMCS);
7527                         vmcs_write64(VMCS_LINK_POINTER,
7528                                      __pa(vmx->nested.current_shadow_vmcs));
7529                         vmx->nested.sync_shadow_vmcs = true;
7530                 }
7531         }
7532
7533         nested_vmx_succeed(vcpu);
7534         skip_emulated_instruction(vcpu);
7535         return 1;
7536 }
7537
7538 /* Emulate the VMPTRST instruction */
7539 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7540 {
7541         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7542         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7543         gva_t vmcs_gva;
7544         struct x86_exception e;
7545
7546         if (!nested_vmx_check_permission(vcpu))
7547                 return 1;
7548
7549         if (get_vmx_mem_address(vcpu, exit_qualification,
7550                         vmx_instruction_info, true, &vmcs_gva))
7551                 return 1;
7552         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7553         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7554                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7555                                  sizeof(u64), &e)) {
7556                 kvm_inject_page_fault(vcpu, &e);
7557                 return 1;
7558         }
7559         nested_vmx_succeed(vcpu);
7560         skip_emulated_instruction(vcpu);
7561         return 1;
7562 }
7563
7564 /* Emulate the INVEPT instruction */
7565 static int handle_invept(struct kvm_vcpu *vcpu)
7566 {
7567         struct vcpu_vmx *vmx = to_vmx(vcpu);
7568         u32 vmx_instruction_info, types;
7569         unsigned long type;
7570         gva_t gva;
7571         struct x86_exception e;
7572         struct {
7573                 u64 eptp, gpa;
7574         } operand;
7575
7576         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7577               SECONDARY_EXEC_ENABLE_EPT) ||
7578             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7579                 kvm_queue_exception(vcpu, UD_VECTOR);
7580                 return 1;
7581         }
7582
7583         if (!nested_vmx_check_permission(vcpu))
7584                 return 1;
7585
7586         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7587                 kvm_queue_exception(vcpu, UD_VECTOR);
7588                 return 1;
7589         }
7590
7591         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7592         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7593
7594         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7595
7596         if (!(types & (1UL << type))) {
7597                 nested_vmx_failValid(vcpu,
7598                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7599                 skip_emulated_instruction(vcpu);
7600                 return 1;
7601         }
7602
7603         /* According to the Intel VMX instruction reference, the memory
7604          * operand is read even if it isn't needed (e.g., for type==global)
7605          */
7606         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7607                         vmx_instruction_info, false, &gva))
7608                 return 1;
7609         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7610                                 sizeof(operand), &e)) {
7611                 kvm_inject_page_fault(vcpu, &e);
7612                 return 1;
7613         }
7614
7615         switch (type) {
7616         case VMX_EPT_EXTENT_GLOBAL:
7617         /*
7618          * TODO: track mappings and invalidate
7619          * single context requests appropriately
7620          */
7621         case VMX_EPT_EXTENT_CONTEXT:
7622                 kvm_mmu_sync_roots(vcpu);
7623                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7624                 nested_vmx_succeed(vcpu);
7625                 break;
7626         default:
7627                 BUG_ON(1);
7628                 break;
7629         }
7630
7631         skip_emulated_instruction(vcpu);
7632         return 1;
7633 }
7634
7635 static int handle_invvpid(struct kvm_vcpu *vcpu)
7636 {
7637         struct vcpu_vmx *vmx = to_vmx(vcpu);
7638         u32 vmx_instruction_info;
7639         unsigned long type, types;
7640         gva_t gva;
7641         struct x86_exception e;
7642         int vpid;
7643
7644         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7645               SECONDARY_EXEC_ENABLE_VPID) ||
7646                         !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7647                 kvm_queue_exception(vcpu, UD_VECTOR);
7648                 return 1;
7649         }
7650
7651         if (!nested_vmx_check_permission(vcpu))
7652                 return 1;
7653
7654         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7655         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7656
7657         types = (vmx->nested.nested_vmx_vpid_caps >> 8) & 0x7;
7658
7659         if (!(types & (1UL << type))) {
7660                 nested_vmx_failValid(vcpu,
7661                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7662                 skip_emulated_instruction(vcpu);
7663                 return 1;
7664         }
7665
7666         /* according to the intel vmx instruction reference, the memory
7667          * operand is read even if it isn't needed (e.g., for type==global)
7668          */
7669         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7670                         vmx_instruction_info, false, &gva))
7671                 return 1;
7672         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7673                                 sizeof(u32), &e)) {
7674                 kvm_inject_page_fault(vcpu, &e);
7675                 return 1;
7676         }
7677
7678         switch (type) {
7679         case VMX_VPID_EXTENT_SINGLE_CONTEXT:
7680                 /*
7681                  * Old versions of KVM use the single-context version so we
7682                  * have to support it; just treat it the same as all-context.
7683                  */
7684         case VMX_VPID_EXTENT_ALL_CONTEXT:
7685                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
7686                 nested_vmx_succeed(vcpu);
7687                 break;
7688         default:
7689                 /* Trap individual address invalidation invvpid calls */
7690                 BUG_ON(1);
7691                 break;
7692         }
7693
7694         skip_emulated_instruction(vcpu);
7695         return 1;
7696 }
7697
7698 static int handle_pml_full(struct kvm_vcpu *vcpu)
7699 {
7700         unsigned long exit_qualification;
7701
7702         trace_kvm_pml_full(vcpu->vcpu_id);
7703
7704         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7705
7706         /*
7707          * PML buffer FULL happened while executing iret from NMI,
7708          * "blocked by NMI" bit has to be set before next VM entry.
7709          */
7710         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7711                         cpu_has_virtual_nmis() &&
7712                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7713                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7714                                 GUEST_INTR_STATE_NMI);
7715
7716         /*
7717          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7718          * here.., and there's no userspace involvement needed for PML.
7719          */
7720         return 1;
7721 }
7722
7723 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
7724 {
7725         kvm_lapic_expired_hv_timer(vcpu);
7726         return 1;
7727 }
7728
7729 /*
7730  * The exit handlers return 1 if the exit was handled fully and guest execution
7731  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
7732  * to be done to userspace and return 0.
7733  */
7734 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7735         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
7736         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
7737         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
7738         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
7739         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
7740         [EXIT_REASON_CR_ACCESS]               = handle_cr,
7741         [EXIT_REASON_DR_ACCESS]               = handle_dr,
7742         [EXIT_REASON_CPUID]                   = handle_cpuid,
7743         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
7744         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
7745         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
7746         [EXIT_REASON_HLT]                     = handle_halt,
7747         [EXIT_REASON_INVD]                    = handle_invd,
7748         [EXIT_REASON_INVLPG]                  = handle_invlpg,
7749         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
7750         [EXIT_REASON_VMCALL]                  = handle_vmcall,
7751         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
7752         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
7753         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
7754         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
7755         [EXIT_REASON_VMREAD]                  = handle_vmread,
7756         [EXIT_REASON_VMRESUME]                = handle_vmresume,
7757         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
7758         [EXIT_REASON_VMOFF]                   = handle_vmoff,
7759         [EXIT_REASON_VMON]                    = handle_vmon,
7760         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
7761         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
7762         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
7763         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
7764         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
7765         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
7766         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
7767         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
7768         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
7769         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
7770         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
7771         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
7772         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
7773         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
7774         [EXIT_REASON_INVEPT]                  = handle_invept,
7775         [EXIT_REASON_INVVPID]                 = handle_invvpid,
7776         [EXIT_REASON_XSAVES]                  = handle_xsaves,
7777         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
7778         [EXIT_REASON_PML_FULL]                = handle_pml_full,
7779         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
7780 };
7781
7782 static const int kvm_vmx_max_exit_handlers =
7783         ARRAY_SIZE(kvm_vmx_exit_handlers);
7784
7785 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7786                                        struct vmcs12 *vmcs12)
7787 {
7788         unsigned long exit_qualification;
7789         gpa_t bitmap, last_bitmap;
7790         unsigned int port;
7791         int size;
7792         u8 b;
7793
7794         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7795                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7796
7797         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7798
7799         port = exit_qualification >> 16;
7800         size = (exit_qualification & 7) + 1;
7801
7802         last_bitmap = (gpa_t)-1;
7803         b = -1;
7804
7805         while (size > 0) {
7806                 if (port < 0x8000)
7807                         bitmap = vmcs12->io_bitmap_a;
7808                 else if (port < 0x10000)
7809                         bitmap = vmcs12->io_bitmap_b;
7810                 else
7811                         return true;
7812                 bitmap += (port & 0x7fff) / 8;
7813
7814                 if (last_bitmap != bitmap)
7815                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7816                                 return true;
7817                 if (b & (1 << (port & 7)))
7818                         return true;
7819
7820                 port++;
7821                 size--;
7822                 last_bitmap = bitmap;
7823         }
7824
7825         return false;
7826 }
7827
7828 /*
7829  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7830  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7831  * disinterest in the current event (read or write a specific MSR) by using an
7832  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7833  */
7834 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7835         struct vmcs12 *vmcs12, u32 exit_reason)
7836 {
7837         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7838         gpa_t bitmap;
7839
7840         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7841                 return true;
7842
7843         /*
7844          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7845          * for the four combinations of read/write and low/high MSR numbers.
7846          * First we need to figure out which of the four to use:
7847          */
7848         bitmap = vmcs12->msr_bitmap;
7849         if (exit_reason == EXIT_REASON_MSR_WRITE)
7850                 bitmap += 2048;
7851         if (msr_index >= 0xc0000000) {
7852                 msr_index -= 0xc0000000;
7853                 bitmap += 1024;
7854         }
7855
7856         /* Then read the msr_index'th bit from this bitmap: */
7857         if (msr_index < 1024*8) {
7858                 unsigned char b;
7859                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7860                         return true;
7861                 return 1 & (b >> (msr_index & 7));
7862         } else
7863                 return true; /* let L1 handle the wrong parameter */
7864 }
7865
7866 /*
7867  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7868  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7869  * intercept (via guest_host_mask etc.) the current event.
7870  */
7871 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7872         struct vmcs12 *vmcs12)
7873 {
7874         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7875         int cr = exit_qualification & 15;
7876         int reg = (exit_qualification >> 8) & 15;
7877         unsigned long val = kvm_register_readl(vcpu, reg);
7878
7879         switch ((exit_qualification >> 4) & 3) {
7880         case 0: /* mov to cr */
7881                 switch (cr) {
7882                 case 0:
7883                         if (vmcs12->cr0_guest_host_mask &
7884                             (val ^ vmcs12->cr0_read_shadow))
7885                                 return true;
7886                         break;
7887                 case 3:
7888                         if ((vmcs12->cr3_target_count >= 1 &&
7889                                         vmcs12->cr3_target_value0 == val) ||
7890                                 (vmcs12->cr3_target_count >= 2 &&
7891                                         vmcs12->cr3_target_value1 == val) ||
7892                                 (vmcs12->cr3_target_count >= 3 &&
7893                                         vmcs12->cr3_target_value2 == val) ||
7894                                 (vmcs12->cr3_target_count >= 4 &&
7895                                         vmcs12->cr3_target_value3 == val))
7896                                 return false;
7897                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7898                                 return true;
7899                         break;
7900                 case 4:
7901                         if (vmcs12->cr4_guest_host_mask &
7902                             (vmcs12->cr4_read_shadow ^ val))
7903                                 return true;
7904                         break;
7905                 case 8:
7906                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7907                                 return true;
7908                         break;
7909                 }
7910                 break;
7911         case 2: /* clts */
7912                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7913                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
7914                         return true;
7915                 break;
7916         case 1: /* mov from cr */
7917                 switch (cr) {
7918                 case 3:
7919                         if (vmcs12->cpu_based_vm_exec_control &
7920                             CPU_BASED_CR3_STORE_EXITING)
7921                                 return true;
7922                         break;
7923                 case 8:
7924                         if (vmcs12->cpu_based_vm_exec_control &
7925                             CPU_BASED_CR8_STORE_EXITING)
7926                                 return true;
7927                         break;
7928                 }
7929                 break;
7930         case 3: /* lmsw */
7931                 /*
7932                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7933                  * cr0. Other attempted changes are ignored, with no exit.
7934                  */
7935                 if (vmcs12->cr0_guest_host_mask & 0xe &
7936                     (val ^ vmcs12->cr0_read_shadow))
7937                         return true;
7938                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7939                     !(vmcs12->cr0_read_shadow & 0x1) &&
7940                     (val & 0x1))
7941                         return true;
7942                 break;
7943         }
7944         return false;
7945 }
7946
7947 /*
7948  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7949  * should handle it ourselves in L0 (and then continue L2). Only call this
7950  * when in is_guest_mode (L2).
7951  */
7952 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7953 {
7954         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7955         struct vcpu_vmx *vmx = to_vmx(vcpu);
7956         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7957         u32 exit_reason = vmx->exit_reason;
7958
7959         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7960                                 vmcs_readl(EXIT_QUALIFICATION),
7961                                 vmx->idt_vectoring_info,
7962                                 intr_info,
7963                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7964                                 KVM_ISA_VMX);
7965
7966         if (vmx->nested.nested_run_pending)
7967                 return false;
7968
7969         if (unlikely(vmx->fail)) {
7970                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7971                                     vmcs_read32(VM_INSTRUCTION_ERROR));
7972                 return true;
7973         }
7974
7975         switch (exit_reason) {
7976         case EXIT_REASON_EXCEPTION_NMI:
7977                 if (!is_exception(intr_info))
7978                         return false;
7979                 else if (is_page_fault(intr_info))
7980                         return enable_ept;
7981                 else if (is_no_device(intr_info) &&
7982                          !(vmcs12->guest_cr0 & X86_CR0_TS))
7983                         return false;
7984                 else if (is_debug(intr_info) &&
7985                          vcpu->guest_debug &
7986                          (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
7987                         return false;
7988                 else if (is_breakpoint(intr_info) &&
7989                          vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
7990                         return false;
7991                 return vmcs12->exception_bitmap &
7992                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7993         case EXIT_REASON_EXTERNAL_INTERRUPT:
7994                 return false;
7995         case EXIT_REASON_TRIPLE_FAULT:
7996                 return true;
7997         case EXIT_REASON_PENDING_INTERRUPT:
7998                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
7999         case EXIT_REASON_NMI_WINDOW:
8000                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
8001         case EXIT_REASON_TASK_SWITCH:
8002                 return true;
8003         case EXIT_REASON_CPUID:
8004                 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
8005                         return false;
8006                 return true;
8007         case EXIT_REASON_HLT:
8008                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
8009         case EXIT_REASON_INVD:
8010                 return true;
8011         case EXIT_REASON_INVLPG:
8012                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8013         case EXIT_REASON_RDPMC:
8014                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
8015         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
8016                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
8017         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
8018         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
8019         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
8020         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
8021         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
8022         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
8023                 /*
8024                  * VMX instructions trap unconditionally. This allows L1 to
8025                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
8026                  */
8027                 return true;
8028         case EXIT_REASON_CR_ACCESS:
8029                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
8030         case EXIT_REASON_DR_ACCESS:
8031                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
8032         case EXIT_REASON_IO_INSTRUCTION:
8033                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
8034         case EXIT_REASON_MSR_READ:
8035         case EXIT_REASON_MSR_WRITE:
8036                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
8037         case EXIT_REASON_INVALID_STATE:
8038                 return true;
8039         case EXIT_REASON_MWAIT_INSTRUCTION:
8040                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
8041         case EXIT_REASON_MONITOR_TRAP_FLAG:
8042                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
8043         case EXIT_REASON_MONITOR_INSTRUCTION:
8044                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
8045         case EXIT_REASON_PAUSE_INSTRUCTION:
8046                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
8047                         nested_cpu_has2(vmcs12,
8048                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
8049         case EXIT_REASON_MCE_DURING_VMENTRY:
8050                 return false;
8051         case EXIT_REASON_TPR_BELOW_THRESHOLD:
8052                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
8053         case EXIT_REASON_APIC_ACCESS:
8054                 return nested_cpu_has2(vmcs12,
8055                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
8056         case EXIT_REASON_APIC_WRITE:
8057         case EXIT_REASON_EOI_INDUCED:
8058                 /* apic_write and eoi_induced should exit unconditionally. */
8059                 return true;
8060         case EXIT_REASON_EPT_VIOLATION:
8061                 /*
8062                  * L0 always deals with the EPT violation. If nested EPT is
8063                  * used, and the nested mmu code discovers that the address is
8064                  * missing in the guest EPT table (EPT12), the EPT violation
8065                  * will be injected with nested_ept_inject_page_fault()
8066                  */
8067                 return false;
8068         case EXIT_REASON_EPT_MISCONFIG:
8069                 /*
8070                  * L2 never uses directly L1's EPT, but rather L0's own EPT
8071                  * table (shadow on EPT) or a merged EPT table that L0 built
8072                  * (EPT on EPT). So any problems with the structure of the
8073                  * table is L0's fault.
8074                  */
8075                 return false;
8076         case EXIT_REASON_WBINVD:
8077                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
8078         case EXIT_REASON_XSETBV:
8079                 return true;
8080         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
8081                 /*
8082                  * This should never happen, since it is not possible to
8083                  * set XSS to a non-zero value---neither in L1 nor in L2.
8084                  * If if it were, XSS would have to be checked against
8085                  * the XSS exit bitmap in vmcs12.
8086                  */
8087                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
8088         case EXIT_REASON_PREEMPTION_TIMER:
8089                 return false;
8090         default:
8091                 return true;
8092         }
8093 }
8094
8095 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
8096 {
8097         *info1 = vmcs_readl(EXIT_QUALIFICATION);
8098         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
8099 }
8100
8101 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
8102 {
8103         if (vmx->pml_pg) {
8104                 __free_page(vmx->pml_pg);
8105                 vmx->pml_pg = NULL;
8106         }
8107 }
8108
8109 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
8110 {
8111         struct vcpu_vmx *vmx = to_vmx(vcpu);
8112         u64 *pml_buf;
8113         u16 pml_idx;
8114
8115         pml_idx = vmcs_read16(GUEST_PML_INDEX);
8116
8117         /* Do nothing if PML buffer is empty */
8118         if (pml_idx == (PML_ENTITY_NUM - 1))
8119                 return;
8120
8121         /* PML index always points to next available PML buffer entity */
8122         if (pml_idx >= PML_ENTITY_NUM)
8123                 pml_idx = 0;
8124         else
8125                 pml_idx++;
8126
8127         pml_buf = page_address(vmx->pml_pg);
8128         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
8129                 u64 gpa;
8130
8131                 gpa = pml_buf[pml_idx];
8132                 WARN_ON(gpa & (PAGE_SIZE - 1));
8133                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
8134         }
8135
8136         /* reset PML index */
8137         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8138 }
8139
8140 /*
8141  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8142  * Called before reporting dirty_bitmap to userspace.
8143  */
8144 static void kvm_flush_pml_buffers(struct kvm *kvm)
8145 {
8146         int i;
8147         struct kvm_vcpu *vcpu;
8148         /*
8149          * We only need to kick vcpu out of guest mode here, as PML buffer
8150          * is flushed at beginning of all VMEXITs, and it's obvious that only
8151          * vcpus running in guest are possible to have unflushed GPAs in PML
8152          * buffer.
8153          */
8154         kvm_for_each_vcpu(i, vcpu, kvm)
8155                 kvm_vcpu_kick(vcpu);
8156 }
8157
8158 static void vmx_dump_sel(char *name, uint32_t sel)
8159 {
8160         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8161                name, vmcs_read32(sel),
8162                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8163                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8164                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8165 }
8166
8167 static void vmx_dump_dtsel(char *name, uint32_t limit)
8168 {
8169         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
8170                name, vmcs_read32(limit),
8171                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8172 }
8173
8174 static void dump_vmcs(void)
8175 {
8176         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8177         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8178         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8179         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8180         u32 secondary_exec_control = 0;
8181         unsigned long cr4 = vmcs_readl(GUEST_CR4);
8182         u64 efer = vmcs_read64(GUEST_IA32_EFER);
8183         int i, n;
8184
8185         if (cpu_has_secondary_exec_ctrls())
8186                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8187
8188         pr_err("*** Guest State ***\n");
8189         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8190                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8191                vmcs_readl(CR0_GUEST_HOST_MASK));
8192         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8193                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8194         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8195         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8196             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8197         {
8198                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
8199                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8200                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
8201                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
8202         }
8203         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
8204                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8205         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
8206                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8207         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8208                vmcs_readl(GUEST_SYSENTER_ESP),
8209                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8210         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
8211         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
8212         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
8213         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
8214         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
8215         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
8216         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8217         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8218         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8219         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
8220         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8221             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
8222                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
8223                        efer, vmcs_read64(GUEST_IA32_PAT));
8224         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
8225                vmcs_read64(GUEST_IA32_DEBUGCTL),
8226                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8227         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
8228                 pr_err("PerfGlobCtl = 0x%016llx\n",
8229                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
8230         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
8231                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
8232         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
8233                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8234                vmcs_read32(GUEST_ACTIVITY_STATE));
8235         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8236                 pr_err("InterruptStatus = %04x\n",
8237                        vmcs_read16(GUEST_INTR_STATUS));
8238
8239         pr_err("*** Host State ***\n");
8240         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
8241                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8242         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8243                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8244                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8245                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8246                vmcs_read16(HOST_TR_SELECTOR));
8247         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8248                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8249                vmcs_readl(HOST_TR_BASE));
8250         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8251                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8252         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8253                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8254                vmcs_readl(HOST_CR4));
8255         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8256                vmcs_readl(HOST_IA32_SYSENTER_ESP),
8257                vmcs_read32(HOST_IA32_SYSENTER_CS),
8258                vmcs_readl(HOST_IA32_SYSENTER_EIP));
8259         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8260                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
8261                        vmcs_read64(HOST_IA32_EFER),
8262                        vmcs_read64(HOST_IA32_PAT));
8263         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8264                 pr_err("PerfGlobCtl = 0x%016llx\n",
8265                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
8266
8267         pr_err("*** Control State ***\n");
8268         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8269                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8270         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8271         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8272                vmcs_read32(EXCEPTION_BITMAP),
8273                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8274                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8275         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8276                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8277                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8278                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8279         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8280                vmcs_read32(VM_EXIT_INTR_INFO),
8281                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8282                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8283         pr_err("        reason=%08x qualification=%016lx\n",
8284                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8285         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8286                vmcs_read32(IDT_VECTORING_INFO_FIELD),
8287                vmcs_read32(IDT_VECTORING_ERROR_CODE));
8288         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8289         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8290                 pr_err("TSC Multiplier = 0x%016llx\n",
8291                        vmcs_read64(TSC_MULTIPLIER));
8292         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8293                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8294         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8295                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8296         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8297                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8298         n = vmcs_read32(CR3_TARGET_COUNT);
8299         for (i = 0; i + 1 < n; i += 4)
8300                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8301                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8302                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8303         if (i < n)
8304                 pr_err("CR3 target%u=%016lx\n",
8305                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8306         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8307                 pr_err("PLE Gap=%08x Window=%08x\n",
8308                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8309         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8310                 pr_err("Virtual processor ID = 0x%04x\n",
8311                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
8312 }
8313
8314 /*
8315  * The guest has exited.  See if we can fix it or if we need userspace
8316  * assistance.
8317  */
8318 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8319 {
8320         struct vcpu_vmx *vmx = to_vmx(vcpu);
8321         u32 exit_reason = vmx->exit_reason;
8322         u32 vectoring_info = vmx->idt_vectoring_info;
8323
8324         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8325
8326         /*
8327          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8328          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8329          * querying dirty_bitmap, we only need to kick all vcpus out of guest
8330          * mode as if vcpus is in root mode, the PML buffer must has been
8331          * flushed already.
8332          */
8333         if (enable_pml)
8334                 vmx_flush_pml_buffer(vcpu);
8335
8336         /* If guest state is invalid, start emulating */
8337         if (vmx->emulation_required)
8338                 return handle_invalid_guest_state(vcpu);
8339
8340         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8341                 nested_vmx_vmexit(vcpu, exit_reason,
8342                                   vmcs_read32(VM_EXIT_INTR_INFO),
8343                                   vmcs_readl(EXIT_QUALIFICATION));
8344                 return 1;
8345         }
8346
8347         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8348                 dump_vmcs();
8349                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8350                 vcpu->run->fail_entry.hardware_entry_failure_reason
8351                         = exit_reason;
8352                 return 0;
8353         }
8354
8355         if (unlikely(vmx->fail)) {
8356                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8357                 vcpu->run->fail_entry.hardware_entry_failure_reason
8358                         = vmcs_read32(VM_INSTRUCTION_ERROR);
8359                 return 0;
8360         }
8361
8362         /*
8363          * Note:
8364          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8365          * delivery event since it indicates guest is accessing MMIO.
8366          * The vm-exit can be triggered again after return to guest that
8367          * will cause infinite loop.
8368          */
8369         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8370                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8371                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
8372                         exit_reason != EXIT_REASON_PML_FULL &&
8373                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
8374                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8375                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8376                 vcpu->run->internal.ndata = 2;
8377                 vcpu->run->internal.data[0] = vectoring_info;
8378                 vcpu->run->internal.data[1] = exit_reason;
8379                 return 0;
8380         }
8381
8382         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
8383             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
8384                                         get_vmcs12(vcpu))))) {
8385                 if (vmx_interrupt_allowed(vcpu)) {
8386                         vmx->soft_vnmi_blocked = 0;
8387                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
8388                            vcpu->arch.nmi_pending) {
8389                         /*
8390                          * This CPU don't support us in finding the end of an
8391                          * NMI-blocked window if the guest runs with IRQs
8392                          * disabled. So we pull the trigger after 1 s of
8393                          * futile waiting, but inform the user about this.
8394                          */
8395                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8396                                "state on VCPU %d after 1 s timeout\n",
8397                                __func__, vcpu->vcpu_id);
8398                         vmx->soft_vnmi_blocked = 0;
8399                 }
8400         }
8401
8402         if (exit_reason < kvm_vmx_max_exit_handlers
8403             && kvm_vmx_exit_handlers[exit_reason])
8404                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8405         else {
8406                 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
8407                 kvm_queue_exception(vcpu, UD_VECTOR);
8408                 return 1;
8409         }
8410 }
8411
8412 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8413 {
8414         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8415
8416         if (is_guest_mode(vcpu) &&
8417                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8418                 return;
8419
8420         if (irr == -1 || tpr < irr) {
8421                 vmcs_write32(TPR_THRESHOLD, 0);
8422                 return;
8423         }
8424
8425         vmcs_write32(TPR_THRESHOLD, irr);
8426 }
8427
8428 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8429 {
8430         u32 sec_exec_control;
8431
8432         /* Postpone execution until vmcs01 is the current VMCS. */
8433         if (is_guest_mode(vcpu)) {
8434                 to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true;
8435                 return;
8436         }
8437
8438         /*
8439          * There is not point to enable virtualize x2apic without enable
8440          * apicv
8441          */
8442         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
8443                                 !kvm_vcpu_apicv_active(vcpu))
8444                 return;
8445
8446         if (!cpu_need_tpr_shadow(vcpu))
8447                 return;
8448
8449         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8450
8451         if (set) {
8452                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8453                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8454         } else {
8455                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8456                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8457         }
8458         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8459
8460         vmx_set_msr_bitmap(vcpu);
8461 }
8462
8463 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8464 {
8465         struct vcpu_vmx *vmx = to_vmx(vcpu);
8466
8467         /*
8468          * Currently we do not handle the nested case where L2 has an
8469          * APIC access page of its own; that page is still pinned.
8470          * Hence, we skip the case where the VCPU is in guest mode _and_
8471          * L1 prepared an APIC access page for L2.
8472          *
8473          * For the case where L1 and L2 share the same APIC access page
8474          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8475          * in the vmcs12), this function will only update either the vmcs01
8476          * or the vmcs02.  If the former, the vmcs02 will be updated by
8477          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
8478          * the next L2->L1 exit.
8479          */
8480         if (!is_guest_mode(vcpu) ||
8481             !nested_cpu_has2(get_vmcs12(&vmx->vcpu),
8482                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8483                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8484 }
8485
8486 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
8487 {
8488         u16 status;
8489         u8 old;
8490
8491         if (max_isr == -1)
8492                 max_isr = 0;
8493
8494         status = vmcs_read16(GUEST_INTR_STATUS);
8495         old = status >> 8;
8496         if (max_isr != old) {
8497                 status &= 0xff;
8498                 status |= max_isr << 8;
8499                 vmcs_write16(GUEST_INTR_STATUS, status);
8500         }
8501 }
8502
8503 static void vmx_set_rvi(int vector)
8504 {
8505         u16 status;
8506         u8 old;
8507
8508         if (vector == -1)
8509                 vector = 0;
8510
8511         status = vmcs_read16(GUEST_INTR_STATUS);
8512         old = (u8)status & 0xff;
8513         if ((u8)vector != old) {
8514                 status &= ~0xff;
8515                 status |= (u8)vector;
8516                 vmcs_write16(GUEST_INTR_STATUS, status);
8517         }
8518 }
8519
8520 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8521 {
8522         if (!is_guest_mode(vcpu)) {
8523                 vmx_set_rvi(max_irr);
8524                 return;
8525         }
8526
8527         if (max_irr == -1)
8528                 return;
8529
8530         /*
8531          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
8532          * handles it.
8533          */
8534         if (nested_exit_on_intr(vcpu))
8535                 return;
8536
8537         /*
8538          * Else, fall back to pre-APICv interrupt injection since L2
8539          * is run without virtual interrupt delivery.
8540          */
8541         if (!kvm_event_needs_reinjection(vcpu) &&
8542             vmx_interrupt_allowed(vcpu)) {
8543                 kvm_queue_interrupt(vcpu, max_irr, false);
8544                 vmx_inject_irq(vcpu);
8545         }
8546 }
8547
8548 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
8549 {
8550         if (!kvm_vcpu_apicv_active(vcpu))
8551                 return;
8552
8553         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8554         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8555         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8556         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8557 }
8558
8559 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8560 {
8561         u32 exit_intr_info;
8562
8563         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8564               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8565                 return;
8566
8567         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8568         exit_intr_info = vmx->exit_intr_info;
8569
8570         /* Handle machine checks before interrupts are enabled */
8571         if (is_machine_check(exit_intr_info))
8572                 kvm_machine_check();
8573
8574         /* We need to handle NMIs before interrupts are enabled */
8575         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
8576             (exit_intr_info & INTR_INFO_VALID_MASK)) {
8577                 kvm_before_handle_nmi(&vmx->vcpu);
8578                 asm("int $2");
8579                 kvm_after_handle_nmi(&vmx->vcpu);
8580         }
8581 }
8582
8583 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8584 {
8585         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8586         register void *__sp asm(_ASM_SP);
8587
8588         /*
8589          * If external interrupt exists, IF bit is set in rflags/eflags on the
8590          * interrupt stack frame, and interrupt will be enabled on a return
8591          * from interrupt handler.
8592          */
8593         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8594                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8595                 unsigned int vector;
8596                 unsigned long entry;
8597                 gate_desc *desc;
8598                 struct vcpu_vmx *vmx = to_vmx(vcpu);
8599 #ifdef CONFIG_X86_64
8600                 unsigned long tmp;
8601 #endif
8602
8603                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
8604                 desc = (gate_desc *)vmx->host_idt_base + vector;
8605                 entry = gate_offset(*desc);
8606                 asm volatile(
8607 #ifdef CONFIG_X86_64
8608                         "mov %%" _ASM_SP ", %[sp]\n\t"
8609                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8610                         "push $%c[ss]\n\t"
8611                         "push %[sp]\n\t"
8612 #endif
8613                         "pushf\n\t"
8614                         __ASM_SIZE(push) " $%c[cs]\n\t"
8615                         "call *%[entry]\n\t"
8616                         :
8617 #ifdef CONFIG_X86_64
8618                         [sp]"=&r"(tmp),
8619 #endif
8620                         "+r"(__sp)
8621                         :
8622                         [entry]"r"(entry),
8623                         [ss]"i"(__KERNEL_DS),
8624                         [cs]"i"(__KERNEL_CS)
8625                         );
8626         }
8627 }
8628
8629 static bool vmx_has_high_real_mode_segbase(void)
8630 {
8631         return enable_unrestricted_guest || emulate_invalid_guest_state;
8632 }
8633
8634 static bool vmx_mpx_supported(void)
8635 {
8636         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8637                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8638 }
8639
8640 static bool vmx_xsaves_supported(void)
8641 {
8642         return vmcs_config.cpu_based_2nd_exec_ctrl &
8643                 SECONDARY_EXEC_XSAVES;
8644 }
8645
8646 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8647 {
8648         u32 exit_intr_info;
8649         bool unblock_nmi;
8650         u8 vector;
8651         bool idtv_info_valid;
8652
8653         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8654
8655         if (cpu_has_virtual_nmis()) {
8656                 if (vmx->nmi_known_unmasked)
8657                         return;
8658                 /*
8659                  * Can't use vmx->exit_intr_info since we're not sure what
8660                  * the exit reason is.
8661                  */
8662                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8663                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8664                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8665                 /*
8666                  * SDM 3: 27.7.1.2 (September 2008)
8667                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
8668                  * a guest IRET fault.
8669                  * SDM 3: 23.2.2 (September 2008)
8670                  * Bit 12 is undefined in any of the following cases:
8671                  *  If the VM exit sets the valid bit in the IDT-vectoring
8672                  *   information field.
8673                  *  If the VM exit is due to a double fault.
8674                  */
8675                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8676                     vector != DF_VECTOR && !idtv_info_valid)
8677                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8678                                       GUEST_INTR_STATE_NMI);
8679                 else
8680                         vmx->nmi_known_unmasked =
8681                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8682                                   & GUEST_INTR_STATE_NMI);
8683         } else if (unlikely(vmx->soft_vnmi_blocked))
8684                 vmx->vnmi_blocked_time +=
8685                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8686 }
8687
8688 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8689                                       u32 idt_vectoring_info,
8690                                       int instr_len_field,
8691                                       int error_code_field)
8692 {
8693         u8 vector;
8694         int type;
8695         bool idtv_info_valid;
8696
8697         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8698
8699         vcpu->arch.nmi_injected = false;
8700         kvm_clear_exception_queue(vcpu);
8701         kvm_clear_interrupt_queue(vcpu);
8702
8703         if (!idtv_info_valid)
8704                 return;
8705
8706         kvm_make_request(KVM_REQ_EVENT, vcpu);
8707
8708         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8709         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8710
8711         switch (type) {
8712         case INTR_TYPE_NMI_INTR:
8713                 vcpu->arch.nmi_injected = true;
8714                 /*
8715                  * SDM 3: 27.7.1.2 (September 2008)
8716                  * Clear bit "block by NMI" before VM entry if a NMI
8717                  * delivery faulted.
8718                  */
8719                 vmx_set_nmi_mask(vcpu, false);
8720                 break;
8721         case INTR_TYPE_SOFT_EXCEPTION:
8722                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8723                 /* fall through */
8724         case INTR_TYPE_HARD_EXCEPTION:
8725                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8726                         u32 err = vmcs_read32(error_code_field);
8727                         kvm_requeue_exception_e(vcpu, vector, err);
8728                 } else
8729                         kvm_requeue_exception(vcpu, vector);
8730                 break;
8731         case INTR_TYPE_SOFT_INTR:
8732                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8733                 /* fall through */
8734         case INTR_TYPE_EXT_INTR:
8735                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8736                 break;
8737         default:
8738                 break;
8739         }
8740 }
8741
8742 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8743 {
8744         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8745                                   VM_EXIT_INSTRUCTION_LEN,
8746                                   IDT_VECTORING_ERROR_CODE);
8747 }
8748
8749 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8750 {
8751         __vmx_complete_interrupts(vcpu,
8752                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8753                                   VM_ENTRY_INSTRUCTION_LEN,
8754                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
8755
8756         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8757 }
8758
8759 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8760 {
8761         int i, nr_msrs;
8762         struct perf_guest_switch_msr *msrs;
8763
8764         msrs = perf_guest_get_msrs(&nr_msrs);
8765
8766         if (!msrs)
8767                 return;
8768
8769         for (i = 0; i < nr_msrs; i++)
8770                 if (msrs[i].host == msrs[i].guest)
8771                         clear_atomic_switch_msr(vmx, msrs[i].msr);
8772                 else
8773                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8774                                         msrs[i].host);
8775 }
8776
8777 void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
8778 {
8779         struct vcpu_vmx *vmx = to_vmx(vcpu);
8780         u64 tscl;
8781         u32 delta_tsc;
8782
8783         if (vmx->hv_deadline_tsc == -1)
8784                 return;
8785
8786         tscl = rdtsc();
8787         if (vmx->hv_deadline_tsc > tscl)
8788                 /* sure to be 32 bit only because checked on set_hv_timer */
8789                 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
8790                         cpu_preemption_timer_multi);
8791         else
8792                 delta_tsc = 0;
8793
8794         vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
8795 }
8796
8797 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8798 {
8799         struct vcpu_vmx *vmx = to_vmx(vcpu);
8800         unsigned long debugctlmsr, cr4;
8801
8802         /* Record the guest's net vcpu time for enforced NMI injections. */
8803         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8804                 vmx->entry_time = ktime_get();
8805
8806         /* Don't enter VMX if guest state is invalid, let the exit handler
8807            start emulation until we arrive back to a valid state */
8808         if (vmx->emulation_required)
8809                 return;
8810
8811         if (vmx->ple_window_dirty) {
8812                 vmx->ple_window_dirty = false;
8813                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8814         }
8815
8816         if (vmx->nested.sync_shadow_vmcs) {
8817                 copy_vmcs12_to_shadow(vmx);
8818                 vmx->nested.sync_shadow_vmcs = false;
8819         }
8820
8821         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8822                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8823         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8824                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8825
8826         cr4 = cr4_read_shadow();
8827         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8828                 vmcs_writel(HOST_CR4, cr4);
8829                 vmx->host_state.vmcs_host_cr4 = cr4;
8830         }
8831
8832         /* When single-stepping over STI and MOV SS, we must clear the
8833          * corresponding interruptibility bits in the guest state. Otherwise
8834          * vmentry fails as it then expects bit 14 (BS) in pending debug
8835          * exceptions being set, but that's not correct for the guest debugging
8836          * case. */
8837         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8838                 vmx_set_interrupt_shadow(vcpu, 0);
8839
8840         if (vmx->guest_pkru_valid)
8841                 __write_pkru(vmx->guest_pkru);
8842
8843         atomic_switch_perf_msrs(vmx);
8844         debugctlmsr = get_debugctlmsr();
8845
8846         vmx_arm_hv_timer(vcpu);
8847
8848         vmx->__launched = vmx->loaded_vmcs->launched;
8849         asm(
8850                 /* Store host registers */
8851                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8852                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8853                 "push %%" _ASM_CX " \n\t"
8854                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8855                 "je 1f \n\t"
8856                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8857                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8858                 "1: \n\t"
8859                 /* Reload cr2 if changed */
8860                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8861                 "mov %%cr2, %%" _ASM_DX " \n\t"
8862                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8863                 "je 2f \n\t"
8864                 "mov %%" _ASM_AX", %%cr2 \n\t"
8865                 "2: \n\t"
8866                 /* Check if vmlaunch of vmresume is needed */
8867                 "cmpl $0, %c[launched](%0) \n\t"
8868                 /* Load guest registers.  Don't clobber flags. */
8869                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8870                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8871                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8872                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8873                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8874                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8875 #ifdef CONFIG_X86_64
8876                 "mov %c[r8](%0),  %%r8  \n\t"
8877                 "mov %c[r9](%0),  %%r9  \n\t"
8878                 "mov %c[r10](%0), %%r10 \n\t"
8879                 "mov %c[r11](%0), %%r11 \n\t"
8880                 "mov %c[r12](%0), %%r12 \n\t"
8881                 "mov %c[r13](%0), %%r13 \n\t"
8882                 "mov %c[r14](%0), %%r14 \n\t"
8883                 "mov %c[r15](%0), %%r15 \n\t"
8884 #endif
8885                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8886
8887                 /* Enter guest mode */
8888                 "jne 1f \n\t"
8889                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8890                 "jmp 2f \n\t"
8891                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8892                 "2: "
8893                 /* Save guest registers, load host registers, keep flags */
8894                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8895                 "pop %0 \n\t"
8896                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8897                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8898                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8899                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8900                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8901                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8902                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8903 #ifdef CONFIG_X86_64
8904                 "mov %%r8,  %c[r8](%0) \n\t"
8905                 "mov %%r9,  %c[r9](%0) \n\t"
8906                 "mov %%r10, %c[r10](%0) \n\t"
8907                 "mov %%r11, %c[r11](%0) \n\t"
8908                 "mov %%r12, %c[r12](%0) \n\t"
8909                 "mov %%r13, %c[r13](%0) \n\t"
8910                 "mov %%r14, %c[r14](%0) \n\t"
8911                 "mov %%r15, %c[r15](%0) \n\t"
8912 #endif
8913                 "mov %%cr2, %%" _ASM_AX "   \n\t"
8914                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
8915
8916                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
8917                 "setbe %c[fail](%0) \n\t"
8918                 ".pushsection .rodata \n\t"
8919                 ".global vmx_return \n\t"
8920                 "vmx_return: " _ASM_PTR " 2b \n\t"
8921                 ".popsection"
8922               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
8923                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
8924                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
8925                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
8926                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8927                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8928                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8929                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8930                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8931                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8932                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
8933 #ifdef CONFIG_X86_64
8934                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8935                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8936                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8937                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8938                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8939                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8940                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8941                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
8942 #endif
8943                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8944                 [wordsize]"i"(sizeof(ulong))
8945               : "cc", "memory"
8946 #ifdef CONFIG_X86_64
8947                 , "rax", "rbx", "rdi", "rsi"
8948                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8949 #else
8950                 , "eax", "ebx", "edi", "esi"
8951 #endif
8952               );
8953
8954         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8955         if (debugctlmsr)
8956                 update_debugctlmsr(debugctlmsr);
8957
8958 #ifndef CONFIG_X86_64
8959         /*
8960          * The sysexit path does not restore ds/es, so we must set them to
8961          * a reasonable value ourselves.
8962          *
8963          * We can't defer this to vmx_load_host_state() since that function
8964          * may be executed in interrupt context, which saves and restore segments
8965          * around it, nullifying its effect.
8966          */
8967         loadsegment(ds, __USER_DS);
8968         loadsegment(es, __USER_DS);
8969 #endif
8970
8971         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
8972                                   | (1 << VCPU_EXREG_RFLAGS)
8973                                   | (1 << VCPU_EXREG_PDPTR)
8974                                   | (1 << VCPU_EXREG_SEGMENTS)
8975                                   | (1 << VCPU_EXREG_CR3));
8976         vcpu->arch.regs_dirty = 0;
8977
8978         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8979
8980         vmx->loaded_vmcs->launched = 1;
8981
8982         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
8983
8984         /*
8985          * eager fpu is enabled if PKEY is supported and CR4 is switched
8986          * back on host, so it is safe to read guest PKRU from current
8987          * XSAVE.
8988          */
8989         if (boot_cpu_has(X86_FEATURE_OSPKE)) {
8990                 vmx->guest_pkru = __read_pkru();
8991                 if (vmx->guest_pkru != vmx->host_pkru) {
8992                         vmx->guest_pkru_valid = true;
8993                         __write_pkru(vmx->host_pkru);
8994                 } else
8995                         vmx->guest_pkru_valid = false;
8996         }
8997
8998         /*
8999          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9000          * we did not inject a still-pending event to L1 now because of
9001          * nested_run_pending, we need to re-enable this bit.
9002          */
9003         if (vmx->nested.nested_run_pending)
9004                 kvm_make_request(KVM_REQ_EVENT, vcpu);
9005
9006         vmx->nested.nested_run_pending = 0;
9007
9008         vmx_complete_atomic_exit(vmx);
9009         vmx_recover_nmi_blocking(vmx);
9010         vmx_complete_interrupts(vmx);
9011 }
9012
9013 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
9014 {
9015         struct vcpu_vmx *vmx = to_vmx(vcpu);
9016         int cpu;
9017
9018         if (vmx->loaded_vmcs == &vmx->vmcs01)
9019                 return;
9020
9021         cpu = get_cpu();
9022         vmx->loaded_vmcs = &vmx->vmcs01;
9023         vmx_vcpu_put(vcpu);
9024         vmx_vcpu_load(vcpu, cpu);
9025         vcpu->cpu = cpu;
9026         put_cpu();
9027 }
9028
9029 /*
9030  * Ensure that the current vmcs of the logical processor is the
9031  * vmcs01 of the vcpu before calling free_nested().
9032  */
9033 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
9034 {
9035        struct vcpu_vmx *vmx = to_vmx(vcpu);
9036        int r;
9037
9038        r = vcpu_load(vcpu);
9039        BUG_ON(r);
9040        vmx_load_vmcs01(vcpu);
9041        free_nested(vmx);
9042        vcpu_put(vcpu);
9043 }
9044
9045 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
9046 {
9047         struct vcpu_vmx *vmx = to_vmx(vcpu);
9048
9049         if (enable_pml)
9050                 vmx_destroy_pml_buffer(vmx);
9051         free_vpid(vmx->vpid);
9052         leave_guest_mode(vcpu);
9053         vmx_free_vcpu_nested(vcpu);
9054         free_loaded_vmcs(vmx->loaded_vmcs);
9055         kfree(vmx->guest_msrs);
9056         kvm_vcpu_uninit(vcpu);
9057         kmem_cache_free(kvm_vcpu_cache, vmx);
9058 }
9059
9060 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
9061 {
9062         int err;
9063         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
9064         int cpu;
9065
9066         if (!vmx)
9067                 return ERR_PTR(-ENOMEM);
9068
9069         vmx->vpid = allocate_vpid();
9070
9071         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
9072         if (err)
9073                 goto free_vcpu;
9074
9075         err = -ENOMEM;
9076
9077         /*
9078          * If PML is turned on, failure on enabling PML just results in failure
9079          * of creating the vcpu, therefore we can simplify PML logic (by
9080          * avoiding dealing with cases, such as enabling PML partially on vcpus
9081          * for the guest, etc.
9082          */
9083         if (enable_pml) {
9084                 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
9085                 if (!vmx->pml_pg)
9086                         goto uninit_vcpu;
9087         }
9088
9089         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
9090         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
9091                      > PAGE_SIZE);
9092
9093         if (!vmx->guest_msrs)
9094                 goto free_pml;
9095
9096         vmx->loaded_vmcs = &vmx->vmcs01;
9097         vmx->loaded_vmcs->vmcs = alloc_vmcs();
9098         if (!vmx->loaded_vmcs->vmcs)
9099                 goto free_msrs;
9100         if (!vmm_exclusive)
9101                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
9102         loaded_vmcs_init(vmx->loaded_vmcs);
9103         if (!vmm_exclusive)
9104                 kvm_cpu_vmxoff();
9105
9106         cpu = get_cpu();
9107         vmx_vcpu_load(&vmx->vcpu, cpu);
9108         vmx->vcpu.cpu = cpu;
9109         err = vmx_vcpu_setup(vmx);
9110         vmx_vcpu_put(&vmx->vcpu);
9111         put_cpu();
9112         if (err)
9113                 goto free_vmcs;
9114         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9115                 err = alloc_apic_access_page(kvm);
9116                 if (err)
9117                         goto free_vmcs;
9118         }
9119
9120         if (enable_ept) {
9121                 if (!kvm->arch.ept_identity_map_addr)
9122                         kvm->arch.ept_identity_map_addr =
9123                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
9124                 err = init_rmode_identity_map(kvm);
9125                 if (err)
9126                         goto free_vmcs;
9127         }
9128
9129         if (nested) {
9130                 nested_vmx_setup_ctls_msrs(vmx);
9131                 vmx->nested.vpid02 = allocate_vpid();
9132         }
9133
9134         vmx->nested.posted_intr_nv = -1;
9135         vmx->nested.current_vmptr = -1ull;
9136         vmx->nested.current_vmcs12 = NULL;
9137
9138         vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
9139
9140         return &vmx->vcpu;
9141
9142 free_vmcs:
9143         free_vpid(vmx->nested.vpid02);
9144         free_loaded_vmcs(vmx->loaded_vmcs);
9145 free_msrs:
9146         kfree(vmx->guest_msrs);
9147 free_pml:
9148         vmx_destroy_pml_buffer(vmx);
9149 uninit_vcpu:
9150         kvm_vcpu_uninit(&vmx->vcpu);
9151 free_vcpu:
9152         free_vpid(vmx->vpid);
9153         kmem_cache_free(kvm_vcpu_cache, vmx);
9154         return ERR_PTR(err);
9155 }
9156
9157 static void __init vmx_check_processor_compat(void *rtn)
9158 {
9159         struct vmcs_config vmcs_conf;
9160
9161         *(int *)rtn = 0;
9162         if (setup_vmcs_config(&vmcs_conf) < 0)
9163                 *(int *)rtn = -EIO;
9164         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
9165                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
9166                                 smp_processor_id());
9167                 *(int *)rtn = -EIO;
9168         }
9169 }
9170
9171 static int get_ept_level(void)
9172 {
9173         return VMX_EPT_DEFAULT_GAW + 1;
9174 }
9175
9176 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
9177 {
9178         u8 cache;
9179         u64 ipat = 0;
9180
9181         /* For VT-d and EPT combination
9182          * 1. MMIO: always map as UC
9183          * 2. EPT with VT-d:
9184          *   a. VT-d without snooping control feature: can't guarantee the
9185          *      result, try to trust guest.
9186          *   b. VT-d with snooping control feature: snooping control feature of
9187          *      VT-d engine can guarantee the cache correctness. Just set it
9188          *      to WB to keep consistent with host. So the same as item 3.
9189          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9190          *    consistent with host MTRR
9191          */
9192         if (is_mmio) {
9193                 cache = MTRR_TYPE_UNCACHABLE;
9194                 goto exit;
9195         }
9196
9197         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
9198                 ipat = VMX_EPT_IPAT_BIT;
9199                 cache = MTRR_TYPE_WRBACK;
9200                 goto exit;
9201         }
9202
9203         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
9204                 ipat = VMX_EPT_IPAT_BIT;
9205                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
9206                         cache = MTRR_TYPE_WRBACK;
9207                 else
9208                         cache = MTRR_TYPE_UNCACHABLE;
9209                 goto exit;
9210         }
9211
9212         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
9213
9214 exit:
9215         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
9216 }
9217
9218 static int vmx_get_lpage_level(void)
9219 {
9220         if (enable_ept && !cpu_has_vmx_ept_1g_page())
9221                 return PT_DIRECTORY_LEVEL;
9222         else
9223                 /* For shadow and EPT supported 1GB page */
9224                 return PT_PDPE_LEVEL;
9225 }
9226
9227 static void vmcs_set_secondary_exec_control(u32 new_ctl)
9228 {
9229         /*
9230          * These bits in the secondary execution controls field
9231          * are dynamic, the others are mostly based on the hypervisor
9232          * architecture and the guest's CPUID.  Do not touch the
9233          * dynamic bits.
9234          */
9235         u32 mask =
9236                 SECONDARY_EXEC_SHADOW_VMCS |
9237                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9238                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9239
9240         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9241
9242         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9243                      (new_ctl & ~mask) | (cur_ctl & mask));
9244 }
9245
9246 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9247 {
9248         struct kvm_cpuid_entry2 *best;
9249         struct vcpu_vmx *vmx = to_vmx(vcpu);
9250         u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
9251
9252         if (vmx_rdtscp_supported()) {
9253                 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
9254                 if (!rdtscp_enabled)
9255                         secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
9256
9257                 if (nested) {
9258                         if (rdtscp_enabled)
9259                                 vmx->nested.nested_vmx_secondary_ctls_high |=
9260                                         SECONDARY_EXEC_RDTSCP;
9261                         else
9262                                 vmx->nested.nested_vmx_secondary_ctls_high &=
9263                                         ~SECONDARY_EXEC_RDTSCP;
9264                 }
9265         }
9266
9267         /* Exposing INVPCID only when PCID is exposed */
9268         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9269         if (vmx_invpcid_supported() &&
9270             (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
9271             !guest_cpuid_has_pcid(vcpu))) {
9272                 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
9273
9274                 if (best)
9275                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
9276         }
9277
9278         if (cpu_has_secondary_exec_ctrls())
9279                 vmcs_set_secondary_exec_control(secondary_exec_ctl);
9280
9281         if (nested_vmx_allowed(vcpu))
9282                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
9283                         FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9284         else
9285                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
9286                         ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9287 }
9288
9289 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9290 {
9291         if (func == 1 && nested)
9292                 entry->ecx |= bit(X86_FEATURE_VMX);
9293 }
9294
9295 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9296                 struct x86_exception *fault)
9297 {
9298         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9299         u32 exit_reason;
9300
9301         if (fault->error_code & PFERR_RSVD_MASK)
9302                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9303         else
9304                 exit_reason = EXIT_REASON_EPT_VIOLATION;
9305         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
9306         vmcs12->guest_physical_address = fault->address;
9307 }
9308
9309 /* Callbacks for nested_ept_init_mmu_context: */
9310
9311 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9312 {
9313         /* return the page table to be shadowed - in our case, EPT12 */
9314         return get_vmcs12(vcpu)->ept_pointer;
9315 }
9316
9317 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9318 {
9319         WARN_ON(mmu_is_nested(vcpu));
9320         kvm_init_shadow_ept_mmu(vcpu,
9321                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9322                         VMX_EPT_EXECUTE_ONLY_BIT);
9323         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
9324         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
9325         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9326
9327         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
9328 }
9329
9330 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9331 {
9332         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9333 }
9334
9335 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9336                                             u16 error_code)
9337 {
9338         bool inequality, bit;
9339
9340         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9341         inequality =
9342                 (error_code & vmcs12->page_fault_error_code_mask) !=
9343                  vmcs12->page_fault_error_code_match;
9344         return inequality ^ bit;
9345 }
9346
9347 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9348                 struct x86_exception *fault)
9349 {
9350         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9351
9352         WARN_ON(!is_guest_mode(vcpu));
9353
9354         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9355                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9356                                   vmcs_read32(VM_EXIT_INTR_INFO),
9357                                   vmcs_readl(EXIT_QUALIFICATION));
9358         else
9359                 kvm_inject_page_fault(vcpu, fault);
9360 }
9361
9362 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9363                                         struct vmcs12 *vmcs12)
9364 {
9365         struct vcpu_vmx *vmx = to_vmx(vcpu);
9366         int maxphyaddr = cpuid_maxphyaddr(vcpu);
9367
9368         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9369                 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
9370                     vmcs12->apic_access_addr >> maxphyaddr)
9371                         return false;
9372
9373                 /*
9374                  * Translate L1 physical address to host physical
9375                  * address for vmcs02. Keep the page pinned, so this
9376                  * physical address remains valid. We keep a reference
9377                  * to it so we can release it later.
9378                  */
9379                 if (vmx->nested.apic_access_page) /* shouldn't happen */
9380                         nested_release_page(vmx->nested.apic_access_page);
9381                 vmx->nested.apic_access_page =
9382                         nested_get_page(vcpu, vmcs12->apic_access_addr);
9383         }
9384
9385         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9386                 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
9387                     vmcs12->virtual_apic_page_addr >> maxphyaddr)
9388                         return false;
9389
9390                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9391                         nested_release_page(vmx->nested.virtual_apic_page);
9392                 vmx->nested.virtual_apic_page =
9393                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9394
9395                 /*
9396                  * Failing the vm entry is _not_ what the processor does
9397                  * but it's basically the only possibility we have.
9398                  * We could still enter the guest if CR8 load exits are
9399                  * enabled, CR8 store exits are enabled, and virtualize APIC
9400                  * access is disabled; in this case the processor would never
9401                  * use the TPR shadow and we could simply clear the bit from
9402                  * the execution control.  But such a configuration is useless,
9403                  * so let's keep the code simple.
9404                  */
9405                 if (!vmx->nested.virtual_apic_page)
9406                         return false;
9407         }
9408
9409         if (nested_cpu_has_posted_intr(vmcs12)) {
9410                 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
9411                     vmcs12->posted_intr_desc_addr >> maxphyaddr)
9412                         return false;
9413
9414                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9415                         kunmap(vmx->nested.pi_desc_page);
9416                         nested_release_page(vmx->nested.pi_desc_page);
9417                 }
9418                 vmx->nested.pi_desc_page =
9419                         nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9420                 if (!vmx->nested.pi_desc_page)
9421                         return false;
9422
9423                 vmx->nested.pi_desc =
9424                         (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9425                 if (!vmx->nested.pi_desc) {
9426                         nested_release_page_clean(vmx->nested.pi_desc_page);
9427                         return false;
9428                 }
9429                 vmx->nested.pi_desc =
9430                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
9431                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9432                         (PAGE_SIZE - 1)));
9433         }
9434
9435         return true;
9436 }
9437
9438 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9439 {
9440         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9441         struct vcpu_vmx *vmx = to_vmx(vcpu);
9442
9443         if (vcpu->arch.virtual_tsc_khz == 0)
9444                 return;
9445
9446         /* Make sure short timeouts reliably trigger an immediate vmexit.
9447          * hrtimer_start does not guarantee this. */
9448         if (preemption_timeout <= 1) {
9449                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9450                 return;
9451         }
9452
9453         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9454         preemption_timeout *= 1000000;
9455         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9456         hrtimer_start(&vmx->nested.preemption_timer,
9457                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9458 }
9459
9460 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9461                                                 struct vmcs12 *vmcs12)
9462 {
9463         int maxphyaddr;
9464         u64 addr;
9465
9466         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9467                 return 0;
9468
9469         if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9470                 WARN_ON(1);
9471                 return -EINVAL;
9472         }
9473         maxphyaddr = cpuid_maxphyaddr(vcpu);
9474
9475         if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9476            ((addr + PAGE_SIZE) >> maxphyaddr))
9477                 return -EINVAL;
9478
9479         return 0;
9480 }
9481
9482 /*
9483  * Merge L0's and L1's MSR bitmap, return false to indicate that
9484  * we do not use the hardware.
9485  */
9486 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9487                                                struct vmcs12 *vmcs12)
9488 {
9489         int msr;
9490         struct page *page;
9491         unsigned long *msr_bitmap_l1;
9492         unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.msr_bitmap;
9493
9494         /* This shortcut is ok because we support only x2APIC MSRs so far. */
9495         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9496                 return false;
9497
9498         page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9499         if (!page) {
9500                 WARN_ON(1);
9501                 return false;
9502         }
9503         msr_bitmap_l1 = (unsigned long *)kmap(page);
9504         if (!msr_bitmap_l1) {
9505                 nested_release_page_clean(page);
9506                 WARN_ON(1);
9507                 return false;
9508         }
9509
9510         memset(msr_bitmap_l0, 0xff, PAGE_SIZE);
9511
9512         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9513                 if (nested_cpu_has_apic_reg_virt(vmcs12))
9514                         for (msr = 0x800; msr <= 0x8ff; msr++)
9515                                 nested_vmx_disable_intercept_for_msr(
9516                                         msr_bitmap_l1, msr_bitmap_l0,
9517                                         msr, MSR_TYPE_R);
9518
9519                 nested_vmx_disable_intercept_for_msr(
9520                                 msr_bitmap_l1, msr_bitmap_l0,
9521                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9522                                 MSR_TYPE_R | MSR_TYPE_W);
9523
9524                 if (nested_cpu_has_vid(vmcs12)) {
9525                         nested_vmx_disable_intercept_for_msr(
9526                                 msr_bitmap_l1, msr_bitmap_l0,
9527                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9528                                 MSR_TYPE_W);
9529                         nested_vmx_disable_intercept_for_msr(
9530                                 msr_bitmap_l1, msr_bitmap_l0,
9531                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9532                                 MSR_TYPE_W);
9533                 }
9534         }
9535         kunmap(page);
9536         nested_release_page_clean(page);
9537
9538         return true;
9539 }
9540
9541 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9542                                            struct vmcs12 *vmcs12)
9543 {
9544         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9545             !nested_cpu_has_apic_reg_virt(vmcs12) &&
9546             !nested_cpu_has_vid(vmcs12) &&
9547             !nested_cpu_has_posted_intr(vmcs12))
9548                 return 0;
9549
9550         /*
9551          * If virtualize x2apic mode is enabled,
9552          * virtualize apic access must be disabled.
9553          */
9554         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9555             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9556                 return -EINVAL;
9557
9558         /*
9559          * If virtual interrupt delivery is enabled,
9560          * we must exit on external interrupts.
9561          */
9562         if (nested_cpu_has_vid(vmcs12) &&
9563            !nested_exit_on_intr(vcpu))
9564                 return -EINVAL;
9565
9566         /*
9567          * bits 15:8 should be zero in posted_intr_nv,
9568          * the descriptor address has been already checked
9569          * in nested_get_vmcs12_pages.
9570          */
9571         if (nested_cpu_has_posted_intr(vmcs12) &&
9572            (!nested_cpu_has_vid(vmcs12) ||
9573             !nested_exit_intr_ack_set(vcpu) ||
9574             vmcs12->posted_intr_nv & 0xff00))
9575                 return -EINVAL;
9576
9577         /* tpr shadow is needed by all apicv features. */
9578         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9579                 return -EINVAL;
9580
9581         return 0;
9582 }
9583
9584 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9585                                        unsigned long count_field,
9586                                        unsigned long addr_field)
9587 {
9588         int maxphyaddr;
9589         u64 count, addr;
9590
9591         if (vmcs12_read_any(vcpu, count_field, &count) ||
9592             vmcs12_read_any(vcpu, addr_field, &addr)) {
9593                 WARN_ON(1);
9594                 return -EINVAL;
9595         }
9596         if (count == 0)
9597                 return 0;
9598         maxphyaddr = cpuid_maxphyaddr(vcpu);
9599         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9600             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9601                 pr_warn_ratelimited(
9602                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9603                         addr_field, maxphyaddr, count, addr);
9604                 return -EINVAL;
9605         }
9606         return 0;
9607 }
9608
9609 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9610                                                 struct vmcs12 *vmcs12)
9611 {
9612         if (vmcs12->vm_exit_msr_load_count == 0 &&
9613             vmcs12->vm_exit_msr_store_count == 0 &&
9614             vmcs12->vm_entry_msr_load_count == 0)
9615                 return 0; /* Fast path */
9616         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9617                                         VM_EXIT_MSR_LOAD_ADDR) ||
9618             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9619                                         VM_EXIT_MSR_STORE_ADDR) ||
9620             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9621                                         VM_ENTRY_MSR_LOAD_ADDR))
9622                 return -EINVAL;
9623         return 0;
9624 }
9625
9626 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9627                                        struct vmx_msr_entry *e)
9628 {
9629         /* x2APIC MSR accesses are not allowed */
9630         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9631                 return -EINVAL;
9632         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9633             e->index == MSR_IA32_UCODE_REV)
9634                 return -EINVAL;
9635         if (e->reserved != 0)
9636                 return -EINVAL;
9637         return 0;
9638 }
9639
9640 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9641                                      struct vmx_msr_entry *e)
9642 {
9643         if (e->index == MSR_FS_BASE ||
9644             e->index == MSR_GS_BASE ||
9645             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9646             nested_vmx_msr_check_common(vcpu, e))
9647                 return -EINVAL;
9648         return 0;
9649 }
9650
9651 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9652                                       struct vmx_msr_entry *e)
9653 {
9654         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9655             nested_vmx_msr_check_common(vcpu, e))
9656                 return -EINVAL;
9657         return 0;
9658 }
9659
9660 /*
9661  * Load guest's/host's msr at nested entry/exit.
9662  * return 0 for success, entry index for failure.
9663  */
9664 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9665 {
9666         u32 i;
9667         struct vmx_msr_entry e;
9668         struct msr_data msr;
9669
9670         msr.host_initiated = false;
9671         for (i = 0; i < count; i++) {
9672                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9673                                         &e, sizeof(e))) {
9674                         pr_warn_ratelimited(
9675                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9676                                 __func__, i, gpa + i * sizeof(e));
9677                         goto fail;
9678                 }
9679                 if (nested_vmx_load_msr_check(vcpu, &e)) {
9680                         pr_warn_ratelimited(
9681                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9682                                 __func__, i, e.index, e.reserved);
9683                         goto fail;
9684                 }
9685                 msr.index = e.index;
9686                 msr.data = e.value;
9687                 if (kvm_set_msr(vcpu, &msr)) {
9688                         pr_warn_ratelimited(
9689                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9690                                 __func__, i, e.index, e.value);
9691                         goto fail;
9692                 }
9693         }
9694         return 0;
9695 fail:
9696         return i + 1;
9697 }
9698
9699 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9700 {
9701         u32 i;
9702         struct vmx_msr_entry e;
9703
9704         for (i = 0; i < count; i++) {
9705                 struct msr_data msr_info;
9706                 if (kvm_vcpu_read_guest(vcpu,
9707                                         gpa + i * sizeof(e),
9708                                         &e, 2 * sizeof(u32))) {
9709                         pr_warn_ratelimited(
9710                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9711                                 __func__, i, gpa + i * sizeof(e));
9712                         return -EINVAL;
9713                 }
9714                 if (nested_vmx_store_msr_check(vcpu, &e)) {
9715                         pr_warn_ratelimited(
9716                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9717                                 __func__, i, e.index, e.reserved);
9718                         return -EINVAL;
9719                 }
9720                 msr_info.host_initiated = false;
9721                 msr_info.index = e.index;
9722                 if (kvm_get_msr(vcpu, &msr_info)) {
9723                         pr_warn_ratelimited(
9724                                 "%s cannot read MSR (%u, 0x%x)\n",
9725                                 __func__, i, e.index);
9726                         return -EINVAL;
9727                 }
9728                 if (kvm_vcpu_write_guest(vcpu,
9729                                          gpa + i * sizeof(e) +
9730                                              offsetof(struct vmx_msr_entry, value),
9731                                          &msr_info.data, sizeof(msr_info.data))) {
9732                         pr_warn_ratelimited(
9733                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9734                                 __func__, i, e.index, msr_info.data);
9735                         return -EINVAL;
9736                 }
9737         }
9738         return 0;
9739 }
9740
9741 /*
9742  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9743  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9744  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9745  * guest in a way that will both be appropriate to L1's requests, and our
9746  * needs. In addition to modifying the active vmcs (which is vmcs02), this
9747  * function also has additional necessary side-effects, like setting various
9748  * vcpu->arch fields.
9749  */
9750 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9751 {
9752         struct vcpu_vmx *vmx = to_vmx(vcpu);
9753         u32 exec_control;
9754
9755         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9756         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9757         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9758         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9759         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9760         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9761         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9762         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9763         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9764         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9765         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9766         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9767         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9768         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9769         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9770         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9771         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9772         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9773         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9774         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9775         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9776         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9777         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9778         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9779         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9780         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9781         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9782         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9783         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9784         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9785         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9786         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9787         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9788         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9789         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9790         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9791
9792         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9793                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9794                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9795         } else {
9796                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9797                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9798         }
9799         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9800                 vmcs12->vm_entry_intr_info_field);
9801         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9802                 vmcs12->vm_entry_exception_error_code);
9803         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9804                 vmcs12->vm_entry_instruction_len);
9805         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9806                 vmcs12->guest_interruptibility_info);
9807         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
9808         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
9809         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9810                 vmcs12->guest_pending_dbg_exceptions);
9811         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9812         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9813
9814         if (nested_cpu_has_xsaves(vmcs12))
9815                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
9816         vmcs_write64(VMCS_LINK_POINTER, -1ull);
9817
9818         exec_control = vmcs12->pin_based_vm_exec_control;
9819
9820         /* Preemption timer setting is only taken from vmcs01.  */
9821         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9822         exec_control |= vmcs_config.pin_based_exec_ctrl;
9823         if (vmx->hv_deadline_tsc == -1)
9824                 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9825
9826         /* Posted interrupts setting is only taken from vmcs12.  */
9827         if (nested_cpu_has_posted_intr(vmcs12)) {
9828                 /*
9829                  * Note that we use L0's vector here and in
9830                  * vmx_deliver_nested_posted_interrupt.
9831                  */
9832                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9833                 vmx->nested.pi_pending = false;
9834                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9835                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9836                         page_to_phys(vmx->nested.pi_desc_page) +
9837                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9838                         (PAGE_SIZE - 1)));
9839         } else
9840                 exec_control &= ~PIN_BASED_POSTED_INTR;
9841
9842         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
9843
9844         vmx->nested.preemption_timer_expired = false;
9845         if (nested_cpu_has_preemption_timer(vmcs12))
9846                 vmx_start_preemption_timer(vcpu);
9847
9848         /*
9849          * Whether page-faults are trapped is determined by a combination of
9850          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9851          * If enable_ept, L0 doesn't care about page faults and we should
9852          * set all of these to L1's desires. However, if !enable_ept, L0 does
9853          * care about (at least some) page faults, and because it is not easy
9854          * (if at all possible?) to merge L0 and L1's desires, we simply ask
9855          * to exit on each and every L2 page fault. This is done by setting
9856          * MASK=MATCH=0 and (see below) EB.PF=1.
9857          * Note that below we don't need special code to set EB.PF beyond the
9858          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9859          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9860          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9861          *
9862          * A problem with this approach (when !enable_ept) is that L1 may be
9863          * injected with more page faults than it asked for. This could have
9864          * caused problems, but in practice existing hypervisors don't care.
9865          * To fix this, we will need to emulate the PFEC checking (on the L1
9866          * page tables), using walk_addr(), when injecting PFs to L1.
9867          */
9868         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9869                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9870         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9871                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9872
9873         if (cpu_has_secondary_exec_ctrls()) {
9874                 exec_control = vmx_secondary_exec_control(vmx);
9875
9876                 /* Take the following fields only from vmcs12 */
9877                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9878                                   SECONDARY_EXEC_RDTSCP |
9879                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
9880                                   SECONDARY_EXEC_APIC_REGISTER_VIRT);
9881                 if (nested_cpu_has(vmcs12,
9882                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9883                         exec_control |= vmcs12->secondary_vm_exec_control;
9884
9885                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
9886                         /*
9887                          * If translation failed, no matter: This feature asks
9888                          * to exit when accessing the given address, and if it
9889                          * can never be accessed, this feature won't do
9890                          * anything anyway.
9891                          */
9892                         if (!vmx->nested.apic_access_page)
9893                                 exec_control &=
9894                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9895                         else
9896                                 vmcs_write64(APIC_ACCESS_ADDR,
9897                                   page_to_phys(vmx->nested.apic_access_page));
9898                 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9899                             cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9900                         exec_control |=
9901                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9902                         kvm_vcpu_reload_apic_access_page(vcpu);
9903                 }
9904
9905                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9906                         vmcs_write64(EOI_EXIT_BITMAP0,
9907                                 vmcs12->eoi_exit_bitmap0);
9908                         vmcs_write64(EOI_EXIT_BITMAP1,
9909                                 vmcs12->eoi_exit_bitmap1);
9910                         vmcs_write64(EOI_EXIT_BITMAP2,
9911                                 vmcs12->eoi_exit_bitmap2);
9912                         vmcs_write64(EOI_EXIT_BITMAP3,
9913                                 vmcs12->eoi_exit_bitmap3);
9914                         vmcs_write16(GUEST_INTR_STATUS,
9915                                 vmcs12->guest_intr_status);
9916                 }
9917
9918                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9919         }
9920
9921
9922         /*
9923          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9924          * Some constant fields are set here by vmx_set_constant_host_state().
9925          * Other fields are different per CPU, and will be set later when
9926          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9927          */
9928         vmx_set_constant_host_state(vmx);
9929
9930         /*
9931          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9932          * entry, but only if the current (host) sp changed from the value
9933          * we wrote last (vmx->host_rsp). This cache is no longer relevant
9934          * if we switch vmcs, and rather than hold a separate cache per vmcs,
9935          * here we just force the write to happen on entry.
9936          */
9937         vmx->host_rsp = 0;
9938
9939         exec_control = vmx_exec_control(vmx); /* L0's desires */
9940         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9941         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9942         exec_control &= ~CPU_BASED_TPR_SHADOW;
9943         exec_control |= vmcs12->cpu_based_vm_exec_control;
9944
9945         if (exec_control & CPU_BASED_TPR_SHADOW) {
9946                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9947                                 page_to_phys(vmx->nested.virtual_apic_page));
9948                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9949         }
9950
9951         if (cpu_has_vmx_msr_bitmap() &&
9952             exec_control & CPU_BASED_USE_MSR_BITMAPS &&
9953             nested_vmx_merge_msr_bitmap(vcpu, vmcs12))
9954                 ; /* MSR_BITMAP will be set by following vmx_set_efer. */
9955         else
9956                 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9957
9958         /*
9959          * Merging of IO bitmap not currently supported.
9960          * Rather, exit every time.
9961          */
9962         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9963         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9964
9965         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9966
9967         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9968          * bitwise-or of what L1 wants to trap for L2, and what we want to
9969          * trap. Note that CR0.TS also needs updating - we do this later.
9970          */
9971         update_exception_bitmap(vcpu);
9972         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9973         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9974
9975         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9976          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9977          * bits are further modified by vmx_set_efer() below.
9978          */
9979         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
9980
9981         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9982          * emulated by vmx_set_efer(), below.
9983          */
9984         vm_entry_controls_init(vmx,
9985                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9986                         ~VM_ENTRY_IA32E_MODE) |
9987                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9988
9989         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
9990                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
9991                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9992         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
9993                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9994
9995
9996         set_cr4_guest_host_mask(vmx);
9997
9998         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9999                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
10000
10001         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
10002                 vmcs_write64(TSC_OFFSET,
10003                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
10004         else
10005                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10006         if (kvm_has_tsc_control)
10007                 decache_tsc_multiplier(vmx);
10008
10009         if (enable_vpid) {
10010                 /*
10011                  * There is no direct mapping between vpid02 and vpid12, the
10012                  * vpid02 is per-vCPU for L0 and reused while the value of
10013                  * vpid12 is changed w/ one invvpid during nested vmentry.
10014                  * The vpid12 is allocated by L1 for L2, so it will not
10015                  * influence global bitmap(for vpid01 and vpid02 allocation)
10016                  * even if spawn a lot of nested vCPUs.
10017                  */
10018                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
10019                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
10020                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
10021                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
10022                                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
10023                         }
10024                 } else {
10025                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
10026                         vmx_flush_tlb(vcpu);
10027                 }
10028
10029         }
10030
10031         if (nested_cpu_has_ept(vmcs12)) {
10032                 kvm_mmu_unload(vcpu);
10033                 nested_ept_init_mmu_context(vcpu);
10034         }
10035
10036         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
10037                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
10038         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
10039                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10040         else
10041                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10042         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10043         vmx_set_efer(vcpu, vcpu->arch.efer);
10044
10045         /*
10046          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
10047          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
10048          * The CR0_READ_SHADOW is what L2 should have expected to read given
10049          * the specifications by L1; It's not enough to take
10050          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10051          * have more bits than L1 expected.
10052          */
10053         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
10054         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
10055
10056         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
10057         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
10058
10059         /* shadow page tables on either EPT or shadow page tables */
10060         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
10061         kvm_mmu_reset_context(vcpu);
10062
10063         if (!enable_ept)
10064                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
10065
10066         /*
10067          * L1 may access the L2's PDPTR, so save them to construct vmcs12
10068          */
10069         if (enable_ept) {
10070                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
10071                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
10072                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
10073                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
10074         }
10075
10076         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
10077         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
10078 }
10079
10080 /*
10081  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10082  * for running an L2 nested guest.
10083  */
10084 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
10085 {
10086         struct vmcs12 *vmcs12;
10087         struct vcpu_vmx *vmx = to_vmx(vcpu);
10088         int cpu;
10089         struct loaded_vmcs *vmcs02;
10090         bool ia32e;
10091         u32 msr_entry_idx;
10092
10093         if (!nested_vmx_check_permission(vcpu) ||
10094             !nested_vmx_check_vmcs12(vcpu))
10095                 return 1;
10096
10097         skip_emulated_instruction(vcpu);
10098         vmcs12 = get_vmcs12(vcpu);
10099
10100         if (enable_shadow_vmcs)
10101                 copy_shadow_to_vmcs12(vmx);
10102
10103         /*
10104          * The nested entry process starts with enforcing various prerequisites
10105          * on vmcs12 as required by the Intel SDM, and act appropriately when
10106          * they fail: As the SDM explains, some conditions should cause the
10107          * instruction to fail, while others will cause the instruction to seem
10108          * to succeed, but return an EXIT_REASON_INVALID_STATE.
10109          * To speed up the normal (success) code path, we should avoid checking
10110          * for misconfigurations which will anyway be caught by the processor
10111          * when using the merged vmcs02.
10112          */
10113         if (vmcs12->launch_state == launch) {
10114                 nested_vmx_failValid(vcpu,
10115                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10116                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
10117                 return 1;
10118         }
10119
10120         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
10121             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
10122                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10123                 return 1;
10124         }
10125
10126         if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
10127                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10128                 return 1;
10129         }
10130
10131         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
10132                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10133                 return 1;
10134         }
10135
10136         if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
10137                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10138                 return 1;
10139         }
10140
10141         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
10142                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10143                 return 1;
10144         }
10145
10146         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
10147                                 vmx->nested.nested_vmx_true_procbased_ctls_low,
10148                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
10149             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
10150                                 vmx->nested.nested_vmx_secondary_ctls_low,
10151                                 vmx->nested.nested_vmx_secondary_ctls_high) ||
10152             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
10153                                 vmx->nested.nested_vmx_pinbased_ctls_low,
10154                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
10155             !vmx_control_verify(vmcs12->vm_exit_controls,
10156                                 vmx->nested.nested_vmx_true_exit_ctls_low,
10157                                 vmx->nested.nested_vmx_exit_ctls_high) ||
10158             !vmx_control_verify(vmcs12->vm_entry_controls,
10159                                 vmx->nested.nested_vmx_true_entry_ctls_low,
10160                                 vmx->nested.nested_vmx_entry_ctls_high))
10161         {
10162                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
10163                 return 1;
10164         }
10165
10166         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
10167             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
10168                 nested_vmx_failValid(vcpu,
10169                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
10170                 return 1;
10171         }
10172
10173         if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
10174             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
10175                 nested_vmx_entry_failure(vcpu, vmcs12,
10176                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
10177                 return 1;
10178         }
10179         if (vmcs12->vmcs_link_pointer != -1ull) {
10180                 nested_vmx_entry_failure(vcpu, vmcs12,
10181                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
10182                 return 1;
10183         }
10184
10185         /*
10186          * If the load IA32_EFER VM-entry control is 1, the following checks
10187          * are performed on the field for the IA32_EFER MSR:
10188          * - Bits reserved in the IA32_EFER MSR must be 0.
10189          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10190          *   the IA-32e mode guest VM-exit control. It must also be identical
10191          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10192          *   CR0.PG) is 1.
10193          */
10194         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
10195                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
10196                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
10197                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
10198                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
10199                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
10200                         nested_vmx_entry_failure(vcpu, vmcs12,
10201                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
10202                         return 1;
10203                 }
10204         }
10205
10206         /*
10207          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10208          * IA32_EFER MSR must be 0 in the field for that register. In addition,
10209          * the values of the LMA and LME bits in the field must each be that of
10210          * the host address-space size VM-exit control.
10211          */
10212         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
10213                 ia32e = (vmcs12->vm_exit_controls &
10214                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
10215                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
10216                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
10217                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
10218                         nested_vmx_entry_failure(vcpu, vmcs12,
10219                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
10220                         return 1;
10221                 }
10222         }
10223
10224         /*
10225          * We're finally done with prerequisite checking, and can start with
10226          * the nested entry.
10227          */
10228
10229         vmcs02 = nested_get_current_vmcs02(vmx);
10230         if (!vmcs02)
10231                 return -ENOMEM;
10232
10233         enter_guest_mode(vcpu);
10234
10235         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
10236
10237         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
10238                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10239
10240         cpu = get_cpu();
10241         vmx->loaded_vmcs = vmcs02;
10242         vmx_vcpu_put(vcpu);
10243         vmx_vcpu_load(vcpu, cpu);
10244         vcpu->cpu = cpu;
10245         put_cpu();
10246
10247         vmx_segment_cache_clear(vmx);
10248
10249         prepare_vmcs02(vcpu, vmcs12);
10250
10251         msr_entry_idx = nested_vmx_load_msr(vcpu,
10252                                             vmcs12->vm_entry_msr_load_addr,
10253                                             vmcs12->vm_entry_msr_load_count);
10254         if (msr_entry_idx) {
10255                 leave_guest_mode(vcpu);
10256                 vmx_load_vmcs01(vcpu);
10257                 nested_vmx_entry_failure(vcpu, vmcs12,
10258                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10259                 return 1;
10260         }
10261
10262         vmcs12->launch_state = 1;
10263
10264         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
10265                 return kvm_vcpu_halt(vcpu);
10266
10267         vmx->nested.nested_run_pending = 1;
10268
10269         /*
10270          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10271          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10272          * returned as far as L1 is concerned. It will only return (and set
10273          * the success flag) when L2 exits (see nested_vmx_vmexit()).
10274          */
10275         return 1;
10276 }
10277
10278 /*
10279  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10280  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10281  * This function returns the new value we should put in vmcs12.guest_cr0.
10282  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10283  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10284  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10285  *     didn't trap the bit, because if L1 did, so would L0).
10286  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10287  *     been modified by L2, and L1 knows it. So just leave the old value of
10288  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10289  *     isn't relevant, because if L0 traps this bit it can set it to anything.
10290  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10291  *     changed these bits, and therefore they need to be updated, but L0
10292  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10293  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10294  */
10295 static inline unsigned long
10296 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10297 {
10298         return
10299         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10300         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10301         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10302                         vcpu->arch.cr0_guest_owned_bits));
10303 }
10304
10305 static inline unsigned long
10306 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10307 {
10308         return
10309         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10310         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10311         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10312                         vcpu->arch.cr4_guest_owned_bits));
10313 }
10314
10315 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10316                                        struct vmcs12 *vmcs12)
10317 {
10318         u32 idt_vectoring;
10319         unsigned int nr;
10320
10321         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10322                 nr = vcpu->arch.exception.nr;
10323                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10324
10325                 if (kvm_exception_is_soft(nr)) {
10326                         vmcs12->vm_exit_instruction_len =
10327                                 vcpu->arch.event_exit_inst_len;
10328                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10329                 } else
10330                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10331
10332                 if (vcpu->arch.exception.has_error_code) {
10333                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10334                         vmcs12->idt_vectoring_error_code =
10335                                 vcpu->arch.exception.error_code;
10336                 }
10337
10338                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10339         } else if (vcpu->arch.nmi_injected) {
10340                 vmcs12->idt_vectoring_info_field =
10341                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10342         } else if (vcpu->arch.interrupt.pending) {
10343                 nr = vcpu->arch.interrupt.nr;
10344                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10345
10346                 if (vcpu->arch.interrupt.soft) {
10347                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
10348                         vmcs12->vm_entry_instruction_len =
10349                                 vcpu->arch.event_exit_inst_len;
10350                 } else
10351                         idt_vectoring |= INTR_TYPE_EXT_INTR;
10352
10353                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10354         }
10355 }
10356
10357 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10358 {
10359         struct vcpu_vmx *vmx = to_vmx(vcpu);
10360
10361         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10362             vmx->nested.preemption_timer_expired) {
10363                 if (vmx->nested.nested_run_pending)
10364                         return -EBUSY;
10365                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10366                 return 0;
10367         }
10368
10369         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10370                 if (vmx->nested.nested_run_pending ||
10371                     vcpu->arch.interrupt.pending)
10372                         return -EBUSY;
10373                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10374                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
10375                                   INTR_INFO_VALID_MASK, 0);
10376                 /*
10377                  * The NMI-triggered VM exit counts as injection:
10378                  * clear this one and block further NMIs.
10379                  */
10380                 vcpu->arch.nmi_pending = 0;
10381                 vmx_set_nmi_mask(vcpu, true);
10382                 return 0;
10383         }
10384
10385         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10386             nested_exit_on_intr(vcpu)) {
10387                 if (vmx->nested.nested_run_pending)
10388                         return -EBUSY;
10389                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10390                 return 0;
10391         }
10392
10393         return vmx_complete_nested_posted_interrupt(vcpu);
10394 }
10395
10396 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10397 {
10398         ktime_t remaining =
10399                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10400         u64 value;
10401
10402         if (ktime_to_ns(remaining) <= 0)
10403                 return 0;
10404
10405         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10406         do_div(value, 1000000);
10407         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10408 }
10409
10410 /*
10411  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10412  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10413  * and this function updates it to reflect the changes to the guest state while
10414  * L2 was running (and perhaps made some exits which were handled directly by L0
10415  * without going back to L1), and to reflect the exit reason.
10416  * Note that we do not have to copy here all VMCS fields, just those that
10417  * could have changed by the L2 guest or the exit - i.e., the guest-state and
10418  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10419  * which already writes to vmcs12 directly.
10420  */
10421 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10422                            u32 exit_reason, u32 exit_intr_info,
10423                            unsigned long exit_qualification)
10424 {
10425         /* update guest state fields: */
10426         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10427         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10428
10429         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10430         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10431         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10432
10433         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10434         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10435         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10436         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10437         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10438         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10439         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10440         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10441         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10442         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10443         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10444         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10445         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10446         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10447         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10448         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10449         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10450         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10451         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10452         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10453         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10454         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10455         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10456         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10457         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10458         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10459         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10460         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10461         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10462         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10463         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10464         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10465         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10466         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10467         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10468         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10469
10470         vmcs12->guest_interruptibility_info =
10471                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10472         vmcs12->guest_pending_dbg_exceptions =
10473                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10474         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10475                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10476         else
10477                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10478
10479         if (nested_cpu_has_preemption_timer(vmcs12)) {
10480                 if (vmcs12->vm_exit_controls &
10481                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10482                         vmcs12->vmx_preemption_timer_value =
10483                                 vmx_get_preemption_timer_value(vcpu);
10484                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10485         }
10486
10487         /*
10488          * In some cases (usually, nested EPT), L2 is allowed to change its
10489          * own CR3 without exiting. If it has changed it, we must keep it.
10490          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10491          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10492          *
10493          * Additionally, restore L2's PDPTR to vmcs12.
10494          */
10495         if (enable_ept) {
10496                 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
10497                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10498                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10499                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10500                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10501         }
10502
10503         if (nested_cpu_has_vid(vmcs12))
10504                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10505
10506         vmcs12->vm_entry_controls =
10507                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10508                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10509
10510         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10511                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10512                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10513         }
10514
10515         /* TODO: These cannot have changed unless we have MSR bitmaps and
10516          * the relevant bit asks not to trap the change */
10517         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10518                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10519         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10520                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10521         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10522         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10523         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10524         if (kvm_mpx_supported())
10525                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10526         if (nested_cpu_has_xsaves(vmcs12))
10527                 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
10528
10529         /* update exit information fields: */
10530
10531         vmcs12->vm_exit_reason = exit_reason;
10532         vmcs12->exit_qualification = exit_qualification;
10533
10534         vmcs12->vm_exit_intr_info = exit_intr_info;
10535         if ((vmcs12->vm_exit_intr_info &
10536              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10537             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10538                 vmcs12->vm_exit_intr_error_code =
10539                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10540         vmcs12->idt_vectoring_info_field = 0;
10541         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10542         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10543
10544         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10545                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10546                  * instead of reading the real value. */
10547                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10548
10549                 /*
10550                  * Transfer the event that L0 or L1 may wanted to inject into
10551                  * L2 to IDT_VECTORING_INFO_FIELD.
10552                  */
10553                 vmcs12_save_pending_event(vcpu, vmcs12);
10554         }
10555
10556         /*
10557          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10558          * preserved above and would only end up incorrectly in L1.
10559          */
10560         vcpu->arch.nmi_injected = false;
10561         kvm_clear_exception_queue(vcpu);
10562         kvm_clear_interrupt_queue(vcpu);
10563 }
10564
10565 /*
10566  * A part of what we need to when the nested L2 guest exits and we want to
10567  * run its L1 parent, is to reset L1's guest state to the host state specified
10568  * in vmcs12.
10569  * This function is to be called not only on normal nested exit, but also on
10570  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10571  * Failures During or After Loading Guest State").
10572  * This function should be called when the active VMCS is L1's (vmcs01).
10573  */
10574 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10575                                    struct vmcs12 *vmcs12)
10576 {
10577         struct kvm_segment seg;
10578
10579         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10580                 vcpu->arch.efer = vmcs12->host_ia32_efer;
10581         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10582                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10583         else
10584                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10585         vmx_set_efer(vcpu, vcpu->arch.efer);
10586
10587         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10588         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10589         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10590         /*
10591          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10592          * actually changed, because it depends on the current state of
10593          * fpu_active (which may have changed).
10594          * Note that vmx_set_cr0 refers to efer set above.
10595          */
10596         vmx_set_cr0(vcpu, vmcs12->host_cr0);
10597         /*
10598          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10599          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10600          * but we also need to update cr0_guest_host_mask and exception_bitmap.
10601          */
10602         update_exception_bitmap(vcpu);
10603         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
10604         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10605
10606         /*
10607          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10608          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10609          */
10610         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10611         kvm_set_cr4(vcpu, vmcs12->host_cr4);
10612
10613         nested_ept_uninit_mmu_context(vcpu);
10614
10615         kvm_set_cr3(vcpu, vmcs12->host_cr3);
10616         kvm_mmu_reset_context(vcpu);
10617
10618         if (!enable_ept)
10619                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10620
10621         if (enable_vpid) {
10622                 /*
10623                  * Trivially support vpid by letting L2s share their parent
10624                  * L1's vpid. TODO: move to a more elaborate solution, giving
10625                  * each L2 its own vpid and exposing the vpid feature to L1.
10626                  */
10627                 vmx_flush_tlb(vcpu);
10628         }
10629
10630
10631         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10632         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10633         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10634         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10635         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10636
10637         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
10638         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10639                 vmcs_write64(GUEST_BNDCFGS, 0);
10640
10641         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10642                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10643                 vcpu->arch.pat = vmcs12->host_ia32_pat;
10644         }
10645         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10646                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10647                         vmcs12->host_ia32_perf_global_ctrl);
10648
10649         /* Set L1 segment info according to Intel SDM
10650             27.5.2 Loading Host Segment and Descriptor-Table Registers */
10651         seg = (struct kvm_segment) {
10652                 .base = 0,
10653                 .limit = 0xFFFFFFFF,
10654                 .selector = vmcs12->host_cs_selector,
10655                 .type = 11,
10656                 .present = 1,
10657                 .s = 1,
10658                 .g = 1
10659         };
10660         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10661                 seg.l = 1;
10662         else
10663                 seg.db = 1;
10664         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10665         seg = (struct kvm_segment) {
10666                 .base = 0,
10667                 .limit = 0xFFFFFFFF,
10668                 .type = 3,
10669                 .present = 1,
10670                 .s = 1,
10671                 .db = 1,
10672                 .g = 1
10673         };
10674         seg.selector = vmcs12->host_ds_selector;
10675         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10676         seg.selector = vmcs12->host_es_selector;
10677         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10678         seg.selector = vmcs12->host_ss_selector;
10679         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10680         seg.selector = vmcs12->host_fs_selector;
10681         seg.base = vmcs12->host_fs_base;
10682         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10683         seg.selector = vmcs12->host_gs_selector;
10684         seg.base = vmcs12->host_gs_base;
10685         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10686         seg = (struct kvm_segment) {
10687                 .base = vmcs12->host_tr_base,
10688                 .limit = 0x67,
10689                 .selector = vmcs12->host_tr_selector,
10690                 .type = 11,
10691                 .present = 1
10692         };
10693         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10694
10695         kvm_set_dr(vcpu, 7, 0x400);
10696         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
10697
10698         if (cpu_has_vmx_msr_bitmap())
10699                 vmx_set_msr_bitmap(vcpu);
10700
10701         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10702                                 vmcs12->vm_exit_msr_load_count))
10703                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
10704 }
10705
10706 /*
10707  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10708  * and modify vmcs12 to make it see what it would expect to see there if
10709  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10710  */
10711 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10712                               u32 exit_intr_info,
10713                               unsigned long exit_qualification)
10714 {
10715         struct vcpu_vmx *vmx = to_vmx(vcpu);
10716         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10717
10718         /* trying to cancel vmlaunch/vmresume is a bug */
10719         WARN_ON_ONCE(vmx->nested.nested_run_pending);
10720
10721         leave_guest_mode(vcpu);
10722         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10723                        exit_qualification);
10724
10725         if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10726                                  vmcs12->vm_exit_msr_store_count))
10727                 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10728
10729         vmx_load_vmcs01(vcpu);
10730
10731         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10732             && nested_exit_intr_ack_set(vcpu)) {
10733                 int irq = kvm_cpu_get_interrupt(vcpu);
10734                 WARN_ON(irq < 0);
10735                 vmcs12->vm_exit_intr_info = irq |
10736                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10737         }
10738
10739         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10740                                        vmcs12->exit_qualification,
10741                                        vmcs12->idt_vectoring_info_field,
10742                                        vmcs12->vm_exit_intr_info,
10743                                        vmcs12->vm_exit_intr_error_code,
10744                                        KVM_ISA_VMX);
10745
10746         vm_entry_controls_reset_shadow(vmx);
10747         vm_exit_controls_reset_shadow(vmx);
10748         vmx_segment_cache_clear(vmx);
10749
10750         /* if no vmcs02 cache requested, remove the one we used */
10751         if (VMCS02_POOL_SIZE == 0)
10752                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10753
10754         load_vmcs12_host_state(vcpu, vmcs12);
10755
10756         /* Update any VMCS fields that might have changed while L2 ran */
10757         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10758         if (vmx->hv_deadline_tsc == -1)
10759                 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
10760                                 PIN_BASED_VMX_PREEMPTION_TIMER);
10761         else
10762                 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
10763                               PIN_BASED_VMX_PREEMPTION_TIMER);
10764         if (kvm_has_tsc_control)
10765                 decache_tsc_multiplier(vmx);
10766
10767         if (vmx->nested.change_vmcs01_virtual_x2apic_mode) {
10768                 vmx->nested.change_vmcs01_virtual_x2apic_mode = false;
10769                 vmx_set_virtual_x2apic_mode(vcpu,
10770                                 vcpu->arch.apic_base & X2APIC_ENABLE);
10771         }
10772
10773         /* This is needed for same reason as it was needed in prepare_vmcs02 */
10774         vmx->host_rsp = 0;
10775
10776         /* Unpin physical memory we referred to in vmcs02 */
10777         if (vmx->nested.apic_access_page) {
10778                 nested_release_page(vmx->nested.apic_access_page);
10779                 vmx->nested.apic_access_page = NULL;
10780         }
10781         if (vmx->nested.virtual_apic_page) {
10782                 nested_release_page(vmx->nested.virtual_apic_page);
10783                 vmx->nested.virtual_apic_page = NULL;
10784         }
10785         if (vmx->nested.pi_desc_page) {
10786                 kunmap(vmx->nested.pi_desc_page);
10787                 nested_release_page(vmx->nested.pi_desc_page);
10788                 vmx->nested.pi_desc_page = NULL;
10789                 vmx->nested.pi_desc = NULL;
10790         }
10791
10792         /*
10793          * We are now running in L2, mmu_notifier will force to reload the
10794          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10795          */
10796         kvm_vcpu_reload_apic_access_page(vcpu);
10797
10798         /*
10799          * Exiting from L2 to L1, we're now back to L1 which thinks it just
10800          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10801          * success or failure flag accordingly.
10802          */
10803         if (unlikely(vmx->fail)) {
10804                 vmx->fail = 0;
10805                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10806         } else
10807                 nested_vmx_succeed(vcpu);
10808         if (enable_shadow_vmcs)
10809                 vmx->nested.sync_shadow_vmcs = true;
10810
10811         /* in case we halted in L2 */
10812         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10813 }
10814
10815 /*
10816  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10817  */
10818 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10819 {
10820         if (is_guest_mode(vcpu))
10821                 nested_vmx_vmexit(vcpu, -1, 0, 0);
10822         free_nested(to_vmx(vcpu));
10823 }
10824
10825 /*
10826  * L1's failure to enter L2 is a subset of a normal exit, as explained in
10827  * 23.7 "VM-entry failures during or after loading guest state" (this also
10828  * lists the acceptable exit-reason and exit-qualification parameters).
10829  * It should only be called before L2 actually succeeded to run, and when
10830  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10831  */
10832 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10833                         struct vmcs12 *vmcs12,
10834                         u32 reason, unsigned long qualification)
10835 {
10836         load_vmcs12_host_state(vcpu, vmcs12);
10837         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10838         vmcs12->exit_qualification = qualification;
10839         nested_vmx_succeed(vcpu);
10840         if (enable_shadow_vmcs)
10841                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
10842 }
10843
10844 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10845                                struct x86_instruction_info *info,
10846                                enum x86_intercept_stage stage)
10847 {
10848         return X86EMUL_CONTINUE;
10849 }
10850
10851 #ifdef CONFIG_X86_64
10852 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
10853 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
10854                                   u64 divisor, u64 *result)
10855 {
10856         u64 low = a << shift, high = a >> (64 - shift);
10857
10858         /* To avoid the overflow on divq */
10859         if (high >= divisor)
10860                 return 1;
10861
10862         /* Low hold the result, high hold rem which is discarded */
10863         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
10864             "rm" (divisor), "0" (low), "1" (high));
10865         *result = low;
10866
10867         return 0;
10868 }
10869
10870 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
10871 {
10872         struct vcpu_vmx *vmx = to_vmx(vcpu);
10873         u64 tscl = rdtsc();
10874         u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
10875         u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
10876
10877         /* Convert to host delta tsc if tsc scaling is enabled */
10878         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
10879                         u64_shl_div_u64(delta_tsc,
10880                                 kvm_tsc_scaling_ratio_frac_bits,
10881                                 vcpu->arch.tsc_scaling_ratio,
10882                                 &delta_tsc))
10883                 return -ERANGE;
10884
10885         /*
10886          * If the delta tsc can't fit in the 32 bit after the multi shift,
10887          * we can't use the preemption timer.
10888          * It's possible that it fits on later vmentries, but checking
10889          * on every vmentry is costly so we just use an hrtimer.
10890          */
10891         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
10892                 return -ERANGE;
10893
10894         vmx->hv_deadline_tsc = tscl + delta_tsc;
10895         vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
10896                         PIN_BASED_VMX_PREEMPTION_TIMER);
10897         return 0;
10898 }
10899
10900 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
10901 {
10902         struct vcpu_vmx *vmx = to_vmx(vcpu);
10903         vmx->hv_deadline_tsc = -1;
10904         vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
10905                         PIN_BASED_VMX_PREEMPTION_TIMER);
10906 }
10907 #endif
10908
10909 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
10910 {
10911         if (ple_gap)
10912                 shrink_ple_window(vcpu);
10913 }
10914
10915 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10916                                      struct kvm_memory_slot *slot)
10917 {
10918         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10919         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10920 }
10921
10922 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10923                                        struct kvm_memory_slot *slot)
10924 {
10925         kvm_mmu_slot_set_dirty(kvm, slot);
10926 }
10927
10928 static void vmx_flush_log_dirty(struct kvm *kvm)
10929 {
10930         kvm_flush_pml_buffers(kvm);
10931 }
10932
10933 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10934                                            struct kvm_memory_slot *memslot,
10935                                            gfn_t offset, unsigned long mask)
10936 {
10937         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10938 }
10939
10940 /*
10941  * This routine does the following things for vCPU which is going
10942  * to be blocked if VT-d PI is enabled.
10943  * - Store the vCPU to the wakeup list, so when interrupts happen
10944  *   we can find the right vCPU to wake up.
10945  * - Change the Posted-interrupt descriptor as below:
10946  *      'NDST' <-- vcpu->pre_pcpu
10947  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
10948  * - If 'ON' is set during this process, which means at least one
10949  *   interrupt is posted for this vCPU, we cannot block it, in
10950  *   this case, return 1, otherwise, return 0.
10951  *
10952  */
10953 static int pi_pre_block(struct kvm_vcpu *vcpu)
10954 {
10955         unsigned long flags;
10956         unsigned int dest;
10957         struct pi_desc old, new;
10958         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10959
10960         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10961                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
10962                 !kvm_vcpu_apicv_active(vcpu))
10963                 return 0;
10964
10965         vcpu->pre_pcpu = vcpu->cpu;
10966         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10967                           vcpu->pre_pcpu), flags);
10968         list_add_tail(&vcpu->blocked_vcpu_list,
10969                       &per_cpu(blocked_vcpu_on_cpu,
10970                       vcpu->pre_pcpu));
10971         spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
10972                                vcpu->pre_pcpu), flags);
10973
10974         do {
10975                 old.control = new.control = pi_desc->control;
10976
10977                 /*
10978                  * We should not block the vCPU if
10979                  * an interrupt is posted for it.
10980                  */
10981                 if (pi_test_on(pi_desc) == 1) {
10982                         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10983                                           vcpu->pre_pcpu), flags);
10984                         list_del(&vcpu->blocked_vcpu_list);
10985                         spin_unlock_irqrestore(
10986                                         &per_cpu(blocked_vcpu_on_cpu_lock,
10987                                         vcpu->pre_pcpu), flags);
10988                         vcpu->pre_pcpu = -1;
10989
10990                         return 1;
10991                 }
10992
10993                 WARN((pi_desc->sn == 1),
10994                      "Warning: SN field of posted-interrupts "
10995                      "is set before blocking\n");
10996
10997                 /*
10998                  * Since vCPU can be preempted during this process,
10999                  * vcpu->cpu could be different with pre_pcpu, we
11000                  * need to set pre_pcpu as the destination of wakeup
11001                  * notification event, then we can find the right vCPU
11002                  * to wakeup in wakeup handler if interrupts happen
11003                  * when the vCPU is in blocked state.
11004                  */
11005                 dest = cpu_physical_id(vcpu->pre_pcpu);
11006
11007                 if (x2apic_enabled())
11008                         new.ndst = dest;
11009                 else
11010                         new.ndst = (dest << 8) & 0xFF00;
11011
11012                 /* set 'NV' to 'wakeup vector' */
11013                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
11014         } while (cmpxchg(&pi_desc->control, old.control,
11015                         new.control) != old.control);
11016
11017         return 0;
11018 }
11019
11020 static int vmx_pre_block(struct kvm_vcpu *vcpu)
11021 {
11022         if (pi_pre_block(vcpu))
11023                 return 1;
11024
11025         if (kvm_lapic_hv_timer_in_use(vcpu))
11026                 kvm_lapic_switch_to_sw_timer(vcpu);
11027
11028         return 0;
11029 }
11030
11031 static void pi_post_block(struct kvm_vcpu *vcpu)
11032 {
11033         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11034         struct pi_desc old, new;
11035         unsigned int dest;
11036         unsigned long flags;
11037
11038         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11039                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
11040                 !kvm_vcpu_apicv_active(vcpu))
11041                 return;
11042
11043         do {
11044                 old.control = new.control = pi_desc->control;
11045
11046                 dest = cpu_physical_id(vcpu->cpu);
11047
11048                 if (x2apic_enabled())
11049                         new.ndst = dest;
11050                 else
11051                         new.ndst = (dest << 8) & 0xFF00;
11052
11053                 /* Allow posting non-urgent interrupts */
11054                 new.sn = 0;
11055
11056                 /* set 'NV' to 'notification vector' */
11057                 new.nv = POSTED_INTR_VECTOR;
11058         } while (cmpxchg(&pi_desc->control, old.control,
11059                         new.control) != old.control);
11060
11061         if(vcpu->pre_pcpu != -1) {
11062                 spin_lock_irqsave(
11063                         &per_cpu(blocked_vcpu_on_cpu_lock,
11064                         vcpu->pre_pcpu), flags);
11065                 list_del(&vcpu->blocked_vcpu_list);
11066                 spin_unlock_irqrestore(
11067                         &per_cpu(blocked_vcpu_on_cpu_lock,
11068                         vcpu->pre_pcpu), flags);
11069                 vcpu->pre_pcpu = -1;
11070         }
11071 }
11072
11073 static void vmx_post_block(struct kvm_vcpu *vcpu)
11074 {
11075         if (kvm_x86_ops->set_hv_timer)
11076                 kvm_lapic_switch_to_hv_timer(vcpu);
11077
11078         pi_post_block(vcpu);
11079 }
11080
11081 /*
11082  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11083  *
11084  * @kvm: kvm
11085  * @host_irq: host irq of the interrupt
11086  * @guest_irq: gsi of the interrupt
11087  * @set: set or unset PI
11088  * returns 0 on success, < 0 on failure
11089  */
11090 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
11091                               uint32_t guest_irq, bool set)
11092 {
11093         struct kvm_kernel_irq_routing_entry *e;
11094         struct kvm_irq_routing_table *irq_rt;
11095         struct kvm_lapic_irq irq;
11096         struct kvm_vcpu *vcpu;
11097         struct vcpu_data vcpu_info;
11098         int idx, ret = -EINVAL;
11099
11100         if (!kvm_arch_has_assigned_device(kvm) ||
11101                 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11102                 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
11103                 return 0;
11104
11105         idx = srcu_read_lock(&kvm->irq_srcu);
11106         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
11107         BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
11108
11109         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
11110                 if (e->type != KVM_IRQ_ROUTING_MSI)
11111                         continue;
11112                 /*
11113                  * VT-d PI cannot support posting multicast/broadcast
11114                  * interrupts to a vCPU, we still use interrupt remapping
11115                  * for these kind of interrupts.
11116                  *
11117                  * For lowest-priority interrupts, we only support
11118                  * those with single CPU as the destination, e.g. user
11119                  * configures the interrupts via /proc/irq or uses
11120                  * irqbalance to make the interrupts single-CPU.
11121                  *
11122                  * We will support full lowest-priority interrupt later.
11123                  */
11124
11125                 kvm_set_msi_irq(kvm, e, &irq);
11126                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
11127                         /*
11128                          * Make sure the IRTE is in remapped mode if
11129                          * we don't handle it in posted mode.
11130                          */
11131                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11132                         if (ret < 0) {
11133                                 printk(KERN_INFO
11134                                    "failed to back to remapped mode, irq: %u\n",
11135                                    host_irq);
11136                                 goto out;
11137                         }
11138
11139                         continue;
11140                 }
11141
11142                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
11143                 vcpu_info.vector = irq.vector;
11144
11145                 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
11146                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
11147
11148                 if (set)
11149                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
11150                 else {
11151                         /* suppress notification event before unposting */
11152                         pi_set_sn(vcpu_to_pi_desc(vcpu));
11153                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11154                         pi_clear_sn(vcpu_to_pi_desc(vcpu));
11155                 }
11156
11157                 if (ret < 0) {
11158                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
11159                                         __func__);
11160                         goto out;
11161                 }
11162         }
11163
11164         ret = 0;
11165 out:
11166         srcu_read_unlock(&kvm->irq_srcu, idx);
11167         return ret;
11168 }
11169
11170 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
11171 {
11172         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
11173                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
11174                         FEATURE_CONTROL_LMCE;
11175         else
11176                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
11177                         ~FEATURE_CONTROL_LMCE;
11178 }
11179
11180 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
11181         .cpu_has_kvm_support = cpu_has_kvm_support,
11182         .disabled_by_bios = vmx_disabled_by_bios,
11183         .hardware_setup = hardware_setup,
11184         .hardware_unsetup = hardware_unsetup,
11185         .check_processor_compatibility = vmx_check_processor_compat,
11186         .hardware_enable = hardware_enable,
11187         .hardware_disable = hardware_disable,
11188         .cpu_has_accelerated_tpr = report_flexpriority,
11189         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
11190
11191         .vcpu_create = vmx_create_vcpu,
11192         .vcpu_free = vmx_free_vcpu,
11193         .vcpu_reset = vmx_vcpu_reset,
11194
11195         .prepare_guest_switch = vmx_save_host_state,
11196         .vcpu_load = vmx_vcpu_load,
11197         .vcpu_put = vmx_vcpu_put,
11198
11199         .update_bp_intercept = update_exception_bitmap,
11200         .get_msr = vmx_get_msr,
11201         .set_msr = vmx_set_msr,
11202         .get_segment_base = vmx_get_segment_base,
11203         .get_segment = vmx_get_segment,
11204         .set_segment = vmx_set_segment,
11205         .get_cpl = vmx_get_cpl,
11206         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
11207         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
11208         .decache_cr3 = vmx_decache_cr3,
11209         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
11210         .set_cr0 = vmx_set_cr0,
11211         .set_cr3 = vmx_set_cr3,
11212         .set_cr4 = vmx_set_cr4,
11213         .set_efer = vmx_set_efer,
11214         .get_idt = vmx_get_idt,
11215         .set_idt = vmx_set_idt,
11216         .get_gdt = vmx_get_gdt,
11217         .set_gdt = vmx_set_gdt,
11218         .get_dr6 = vmx_get_dr6,
11219         .set_dr6 = vmx_set_dr6,
11220         .set_dr7 = vmx_set_dr7,
11221         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
11222         .cache_reg = vmx_cache_reg,
11223         .get_rflags = vmx_get_rflags,
11224         .set_rflags = vmx_set_rflags,
11225
11226         .get_pkru = vmx_get_pkru,
11227
11228         .fpu_activate = vmx_fpu_activate,
11229         .fpu_deactivate = vmx_fpu_deactivate,
11230
11231         .tlb_flush = vmx_flush_tlb,
11232
11233         .run = vmx_vcpu_run,
11234         .handle_exit = vmx_handle_exit,
11235         .skip_emulated_instruction = skip_emulated_instruction,
11236         .set_interrupt_shadow = vmx_set_interrupt_shadow,
11237         .get_interrupt_shadow = vmx_get_interrupt_shadow,
11238         .patch_hypercall = vmx_patch_hypercall,
11239         .set_irq = vmx_inject_irq,
11240         .set_nmi = vmx_inject_nmi,
11241         .queue_exception = vmx_queue_exception,
11242         .cancel_injection = vmx_cancel_injection,
11243         .interrupt_allowed = vmx_interrupt_allowed,
11244         .nmi_allowed = vmx_nmi_allowed,
11245         .get_nmi_mask = vmx_get_nmi_mask,
11246         .set_nmi_mask = vmx_set_nmi_mask,
11247         .enable_nmi_window = enable_nmi_window,
11248         .enable_irq_window = enable_irq_window,
11249         .update_cr8_intercept = update_cr8_intercept,
11250         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
11251         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
11252         .get_enable_apicv = vmx_get_enable_apicv,
11253         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
11254         .load_eoi_exitmap = vmx_load_eoi_exitmap,
11255         .hwapic_irr_update = vmx_hwapic_irr_update,
11256         .hwapic_isr_update = vmx_hwapic_isr_update,
11257         .sync_pir_to_irr = vmx_sync_pir_to_irr,
11258         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
11259
11260         .set_tss_addr = vmx_set_tss_addr,
11261         .get_tdp_level = get_ept_level,
11262         .get_mt_mask = vmx_get_mt_mask,
11263
11264         .get_exit_info = vmx_get_exit_info,
11265
11266         .get_lpage_level = vmx_get_lpage_level,
11267
11268         .cpuid_update = vmx_cpuid_update,
11269
11270         .rdtscp_supported = vmx_rdtscp_supported,
11271         .invpcid_supported = vmx_invpcid_supported,
11272
11273         .set_supported_cpuid = vmx_set_supported_cpuid,
11274
11275         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
11276
11277         .read_tsc_offset = vmx_read_tsc_offset,
11278         .write_tsc_offset = vmx_write_tsc_offset,
11279         .adjust_tsc_offset_guest = vmx_adjust_tsc_offset_guest,
11280         .read_l1_tsc = vmx_read_l1_tsc,
11281
11282         .set_tdp_cr3 = vmx_set_cr3,
11283
11284         .check_intercept = vmx_check_intercept,
11285         .handle_external_intr = vmx_handle_external_intr,
11286         .mpx_supported = vmx_mpx_supported,
11287         .xsaves_supported = vmx_xsaves_supported,
11288
11289         .check_nested_events = vmx_check_nested_events,
11290
11291         .sched_in = vmx_sched_in,
11292
11293         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
11294         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
11295         .flush_log_dirty = vmx_flush_log_dirty,
11296         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
11297
11298         .pre_block = vmx_pre_block,
11299         .post_block = vmx_post_block,
11300
11301         .pmu_ops = &intel_pmu_ops,
11302
11303         .update_pi_irte = vmx_update_pi_irte,
11304
11305 #ifdef CONFIG_X86_64
11306         .set_hv_timer = vmx_set_hv_timer,
11307         .cancel_hv_timer = vmx_cancel_hv_timer,
11308 #endif
11309
11310         .setup_mce = vmx_setup_mce,
11311 };
11312
11313 static int __init vmx_init(void)
11314 {
11315         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
11316                      __alignof__(struct vcpu_vmx), THIS_MODULE);
11317         if (r)
11318                 return r;
11319
11320 #ifdef CONFIG_KEXEC_CORE
11321         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
11322                            crash_vmclear_local_loaded_vmcss);
11323 #endif
11324
11325         return 0;
11326 }
11327
11328 static void __exit vmx_exit(void)
11329 {
11330 #ifdef CONFIG_KEXEC_CORE
11331         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
11332         synchronize_rcu();
11333 #endif
11334
11335         kvm_exit();
11336 }
11337
11338 module_init(vmx_init)
11339 module_exit(vmx_exit)