2 * Copyright 2002 Andi Kleen, SuSE Labs.
3 * Thanks to Ben LaHaise for precious feedback.
5 #include <linux/highmem.h>
6 #include <linux/bootmem.h>
7 #include <linux/sched.h>
9 #include <linux/interrupt.h>
10 #include <linux/seq_file.h>
11 #include <linux/debugfs.h>
12 #include <linux/pfn.h>
13 #include <linux/percpu.h>
14 #include <linux/gfp.h>
15 #include <linux/pci.h>
16 #include <linux/vmalloc.h>
19 #include <asm/processor.h>
20 #include <asm/tlbflush.h>
21 #include <asm/sections.h>
22 #include <asm/setup.h>
23 #include <asm/uaccess.h>
24 #include <asm/pgalloc.h>
25 #include <asm/proto.h>
29 * The current flushing context - we pass it instead of 5 arguments:
36 unsigned long numpages;
39 unsigned force_split : 1;
45 * Serialize cpa() (for !DEBUG_PAGEALLOC which uses large identity mappings)
46 * using cpa_lock. So that we don't allow any other cpu, with stale large tlb
47 * entries change the page attribute in parallel to some other cpu
48 * splitting a large page entry along with changing the attribute.
50 static DEFINE_SPINLOCK(cpa_lock);
52 #define CPA_FLUSHTLB 1
54 #define CPA_PAGES_ARRAY 4
57 static unsigned long direct_pages_count[PG_LEVEL_NUM];
59 void update_page_count(int level, unsigned long pages)
61 /* Protect against CPA */
63 direct_pages_count[level] += pages;
64 spin_unlock(&pgd_lock);
67 static void split_page_count(int level)
69 if (direct_pages_count[level] == 0)
72 direct_pages_count[level]--;
73 direct_pages_count[level - 1] += PTRS_PER_PTE;
76 void arch_report_meminfo(struct seq_file *m)
78 seq_printf(m, "DirectMap4k: %8lu kB\n",
79 direct_pages_count[PG_LEVEL_4K] << 2);
80 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
81 seq_printf(m, "DirectMap2M: %8lu kB\n",
82 direct_pages_count[PG_LEVEL_2M] << 11);
84 seq_printf(m, "DirectMap4M: %8lu kB\n",
85 direct_pages_count[PG_LEVEL_2M] << 12);
88 seq_printf(m, "DirectMap1G: %8lu kB\n",
89 direct_pages_count[PG_LEVEL_1G] << 20);
92 static inline void split_page_count(int level) { }
97 static inline unsigned long highmap_start_pfn(void)
99 return __pa_symbol(_text) >> PAGE_SHIFT;
102 static inline unsigned long highmap_end_pfn(void)
104 return __pa_symbol(roundup(_brk_end, PMD_SIZE)) >> PAGE_SHIFT;
110 within(unsigned long addr, unsigned long start, unsigned long end)
112 return addr >= start && addr < end;
120 * clflush_cache_range - flush a cache range with clflush
121 * @vaddr: virtual start address
122 * @size: number of bytes to flush
124 * clflushopt is an unordered instruction which needs fencing with mfence or
125 * sfence to avoid ordering issues.
127 void clflush_cache_range(void *vaddr, unsigned int size)
129 const unsigned long clflush_size = boot_cpu_data.x86_clflush_size;
130 void *p = (void *)((unsigned long)vaddr & ~(clflush_size - 1));
131 void *vend = vaddr + size;
138 for (; p < vend; p += clflush_size)
143 EXPORT_SYMBOL_GPL(clflush_cache_range);
145 static void __cpa_flush_all(void *arg)
147 unsigned long cache = (unsigned long)arg;
150 * Flush all to work around Errata in early athlons regarding
151 * large page flushing.
155 if (cache && boot_cpu_data.x86 >= 4)
159 static void cpa_flush_all(unsigned long cache)
161 BUG_ON(irqs_disabled());
163 on_each_cpu(__cpa_flush_all, (void *) cache, 1);
166 static void __cpa_flush_range(void *arg)
169 * We could optimize that further and do individual per page
170 * tlb invalidates for a low number of pages. Caveat: we must
171 * flush the high aliases on 64bit as well.
176 static void cpa_flush_range(unsigned long start, int numpages, int cache)
178 unsigned int i, level;
181 BUG_ON(irqs_disabled());
182 WARN_ON(PAGE_ALIGN(start) != start);
184 on_each_cpu(__cpa_flush_range, NULL, 1);
190 * We only need to flush on one CPU,
191 * clflush is a MESI-coherent instruction that
192 * will cause all other CPUs to flush the same
195 for (i = 0, addr = start; i < numpages; i++, addr += PAGE_SIZE) {
196 pte_t *pte = lookup_address(addr, &level);
199 * Only flush present addresses:
201 if (pte && (pte_val(*pte) & _PAGE_PRESENT))
202 clflush_cache_range((void *) addr, PAGE_SIZE);
206 static void cpa_flush_array(unsigned long *start, int numpages, int cache,
207 int in_flags, struct page **pages)
209 unsigned int i, level;
210 unsigned long do_wbinvd = cache && numpages >= 1024; /* 4M threshold */
212 BUG_ON(irqs_disabled());
214 on_each_cpu(__cpa_flush_all, (void *) do_wbinvd, 1);
216 if (!cache || do_wbinvd)
220 * We only need to flush on one CPU,
221 * clflush is a MESI-coherent instruction that
222 * will cause all other CPUs to flush the same
225 for (i = 0; i < numpages; i++) {
229 if (in_flags & CPA_PAGES_ARRAY)
230 addr = (unsigned long)page_address(pages[i]);
234 pte = lookup_address(addr, &level);
237 * Only flush present addresses:
239 if (pte && (pte_val(*pte) & _PAGE_PRESENT))
240 clflush_cache_range((void *)addr, PAGE_SIZE);
245 * Certain areas of memory on x86 require very specific protection flags,
246 * for example the BIOS area or kernel text. Callers don't always get this
247 * right (again, ioremap() on BIOS memory is not uncommon) so this function
248 * checks and fixes these known static required protection bits.
250 static inline pgprot_t static_protections(pgprot_t prot, unsigned long address,
253 pgprot_t forbidden = __pgprot(0);
256 * The BIOS area between 640k and 1Mb needs to be executable for
257 * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support.
259 #ifdef CONFIG_PCI_BIOS
260 if (pcibios_enabled && within(pfn, BIOS_BEGIN >> PAGE_SHIFT, BIOS_END >> PAGE_SHIFT))
261 pgprot_val(forbidden) |= _PAGE_NX;
265 * The kernel text needs to be executable for obvious reasons
266 * Does not cover __inittext since that is gone later on. On
267 * 64bit we do not enforce !NX on the low mapping
269 if (within(address, (unsigned long)_text, (unsigned long)_etext))
270 pgprot_val(forbidden) |= _PAGE_NX;
273 * The .rodata section needs to be read-only. Using the pfn
274 * catches all aliases.
276 if (within(pfn, __pa_symbol(__start_rodata) >> PAGE_SHIFT,
277 __pa_symbol(__end_rodata) >> PAGE_SHIFT))
278 pgprot_val(forbidden) |= _PAGE_RW;
280 #if defined(CONFIG_X86_64)
282 * Once the kernel maps the text as RO (kernel_set_to_readonly is set),
283 * kernel text mappings for the large page aligned text, rodata sections
284 * will be always read-only. For the kernel identity mappings covering
285 * the holes caused by this alignment can be anything that user asks.
287 * This will preserve the large page mappings for kernel text/data
290 if (kernel_set_to_readonly &&
291 within(address, (unsigned long)_text,
292 (unsigned long)__end_rodata_hpage_align)) {
296 * Don't enforce the !RW mapping for the kernel text mapping,
297 * if the current mapping is already using small page mapping.
298 * No need to work hard to preserve large page mappings in this
301 * This also fixes the Linux Xen paravirt guest boot failure
302 * (because of unexpected read-only mappings for kernel identity
303 * mappings). In this paravirt guest case, the kernel text
304 * mapping and the kernel identity mapping share the same
305 * page-table pages. Thus we can't really use different
306 * protections for the kernel text and identity mappings. Also,
307 * these shared mappings are made of small page mappings.
308 * Thus this don't enforce !RW mapping for small page kernel
309 * text mapping logic will help Linux Xen parvirt guest boot
312 if (lookup_address(address, &level) && (level != PG_LEVEL_4K))
313 pgprot_val(forbidden) |= _PAGE_RW;
317 prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden));
323 * Lookup the page table entry for a virtual address in a specific pgd.
324 * Return a pointer to the entry and the level of the mapping.
326 pte_t *lookup_address_in_pgd(pgd_t *pgd, unsigned long address,
332 *level = PG_LEVEL_NONE;
337 pud = pud_offset(pgd, address);
341 *level = PG_LEVEL_1G;
342 if (pud_large(*pud) || !pud_present(*pud))
345 pmd = pmd_offset(pud, address);
349 *level = PG_LEVEL_2M;
350 if (pmd_large(*pmd) || !pmd_present(*pmd))
353 *level = PG_LEVEL_4K;
355 return pte_offset_kernel(pmd, address);
359 * Lookup the page table entry for a virtual address. Return a pointer
360 * to the entry and the level of the mapping.
362 * Note: We return pud and pmd either when the entry is marked large
363 * or when the present bit is not set. Otherwise we would return a
364 * pointer to a nonexisting mapping.
366 pte_t *lookup_address(unsigned long address, unsigned int *level)
368 return lookup_address_in_pgd(pgd_offset_k(address), address, level);
370 EXPORT_SYMBOL_GPL(lookup_address);
372 static pte_t *_lookup_address_cpa(struct cpa_data *cpa, unsigned long address,
376 return lookup_address_in_pgd(cpa->pgd + pgd_index(address),
379 return lookup_address(address, level);
383 * Lookup the PMD entry for a virtual address. Return a pointer to the entry
384 * or NULL if not present.
386 pmd_t *lookup_pmd_address(unsigned long address)
391 pgd = pgd_offset_k(address);
395 pud = pud_offset(pgd, address);
396 if (pud_none(*pud) || pud_large(*pud) || !pud_present(*pud))
399 return pmd_offset(pud, address);
403 * This is necessary because __pa() does not work on some
404 * kinds of memory, like vmalloc() or the alloc_remap()
405 * areas on 32-bit NUMA systems. The percpu areas can
406 * end up in this kind of memory, for instance.
408 * This could be optimized, but it is only intended to be
409 * used at inititalization time, and keeping it
410 * unoptimized should increase the testing coverage for
411 * the more obscure platforms.
413 phys_addr_t slow_virt_to_phys(void *__virt_addr)
415 unsigned long virt_addr = (unsigned long)__virt_addr;
416 phys_addr_t phys_addr;
417 unsigned long offset;
421 pte = lookup_address(virt_addr, &level);
425 * pXX_pfn() returns unsigned long, which must be cast to phys_addr_t
426 * before being left-shifted PAGE_SHIFT bits -- this trick is to
427 * make 32-PAE kernel work correctly.
431 phys_addr = (phys_addr_t)pud_pfn(*(pud_t *)pte) << PAGE_SHIFT;
432 offset = virt_addr & ~PUD_PAGE_MASK;
435 phys_addr = (phys_addr_t)pmd_pfn(*(pmd_t *)pte) << PAGE_SHIFT;
436 offset = virt_addr & ~PMD_PAGE_MASK;
439 phys_addr = (phys_addr_t)pte_pfn(*pte) << PAGE_SHIFT;
440 offset = virt_addr & ~PAGE_MASK;
443 return (phys_addr_t)(phys_addr | offset);
445 EXPORT_SYMBOL_GPL(slow_virt_to_phys);
448 * Set the new pmd in all the pgds we know about:
450 static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte)
453 set_pte_atomic(kpte, pte);
455 if (!SHARED_KERNEL_PMD) {
458 list_for_each_entry(page, &pgd_list, lru) {
463 pgd = (pgd_t *)page_address(page) + pgd_index(address);
464 pud = pud_offset(pgd, address);
465 pmd = pmd_offset(pud, address);
466 set_pte_atomic((pte_t *)pmd, pte);
473 try_preserve_large_page(pte_t *kpte, unsigned long address,
474 struct cpa_data *cpa)
476 unsigned long nextpage_addr, numpages, pmask, psize, addr, pfn, old_pfn;
477 pte_t new_pte, old_pte, *tmp;
478 pgprot_t old_prot, new_prot, req_prot;
482 if (cpa->force_split)
485 spin_lock(&pgd_lock);
487 * Check for races, another CPU might have split this page
490 tmp = _lookup_address_cpa(cpa, address, &level);
496 old_prot = pmd_pgprot(*(pmd_t *)kpte);
497 old_pfn = pmd_pfn(*(pmd_t *)kpte);
500 old_prot = pud_pgprot(*(pud_t *)kpte);
501 old_pfn = pud_pfn(*(pud_t *)kpte);
508 psize = page_level_size(level);
509 pmask = page_level_mask(level);
512 * Calculate the number of pages, which fit into this large
513 * page starting at address:
515 nextpage_addr = (address + psize) & pmask;
516 numpages = (nextpage_addr - address) >> PAGE_SHIFT;
517 if (numpages < cpa->numpages)
518 cpa->numpages = numpages;
521 * We are safe now. Check whether the new pgprot is the same:
522 * Convert protection attributes to 4k-format, as cpa->mask* are set
526 req_prot = pgprot_large_2_4k(old_prot);
528 pgprot_val(req_prot) &= ~pgprot_val(cpa->mask_clr);
529 pgprot_val(req_prot) |= pgprot_val(cpa->mask_set);
532 * req_prot is in format of 4k pages. It must be converted to large
533 * page format: the caching mode includes the PAT bit located at
534 * different bit positions in the two formats.
536 req_prot = pgprot_4k_2_large(req_prot);
539 * Set the PSE and GLOBAL flags only if the PRESENT flag is
540 * set otherwise pmd_present/pmd_huge will return true even on
541 * a non present pmd. The canon_pgprot will clear _PAGE_GLOBAL
542 * for the ancient hardware that doesn't support it.
544 if (pgprot_val(req_prot) & _PAGE_PRESENT)
545 pgprot_val(req_prot) |= _PAGE_PSE | _PAGE_GLOBAL;
547 pgprot_val(req_prot) &= ~(_PAGE_PSE | _PAGE_GLOBAL);
549 req_prot = canon_pgprot(req_prot);
552 * old_pfn points to the large page base pfn. So we need
553 * to add the offset of the virtual address:
555 pfn = old_pfn + ((address & (psize - 1)) >> PAGE_SHIFT);
558 new_prot = static_protections(req_prot, address, pfn);
561 * We need to check the full range, whether
562 * static_protection() requires a different pgprot for one of
563 * the pages in the range we try to preserve:
565 addr = address & pmask;
567 for (i = 0; i < (psize >> PAGE_SHIFT); i++, addr += PAGE_SIZE, pfn++) {
568 pgprot_t chk_prot = static_protections(req_prot, addr, pfn);
570 if (pgprot_val(chk_prot) != pgprot_val(new_prot))
575 * If there are no changes, return. maxpages has been updated
578 if (pgprot_val(new_prot) == pgprot_val(old_prot)) {
584 * We need to change the attributes. Check, whether we can
585 * change the large page in one go. We request a split, when
586 * the address is not aligned and the number of pages is
587 * smaller than the number of pages in the large page. Note
588 * that we limited the number of possible pages already to
589 * the number of pages in the large page.
591 if (address == (address & pmask) && cpa->numpages == (psize >> PAGE_SHIFT)) {
593 * The address is aligned and the number of pages
594 * covers the full page.
596 new_pte = pfn_pte(old_pfn, new_prot);
597 __set_pmd_pte(kpte, address, new_pte);
598 cpa->flags |= CPA_FLUSHTLB;
603 spin_unlock(&pgd_lock);
609 __split_large_page(struct cpa_data *cpa, pte_t *kpte, unsigned long address,
612 pte_t *pbase = (pte_t *)page_address(base);
613 unsigned long ref_pfn, pfn, pfninc = 1;
614 unsigned int i, level;
618 spin_lock(&pgd_lock);
620 * Check for races, another CPU might have split this page
623 tmp = _lookup_address_cpa(cpa, address, &level);
625 spin_unlock(&pgd_lock);
629 paravirt_alloc_pte(&init_mm, page_to_pfn(base));
633 ref_prot = pmd_pgprot(*(pmd_t *)kpte);
634 /* clear PSE and promote PAT bit to correct position */
635 ref_prot = pgprot_large_2_4k(ref_prot);
636 ref_pfn = pmd_pfn(*(pmd_t *)kpte);
640 ref_prot = pud_pgprot(*(pud_t *)kpte);
641 ref_pfn = pud_pfn(*(pud_t *)kpte);
642 pfninc = PMD_PAGE_SIZE >> PAGE_SHIFT;
645 * Clear the PSE flags if the PRESENT flag is not set
646 * otherwise pmd_present/pmd_huge will return true
647 * even on a non present pmd.
649 if (!(pgprot_val(ref_prot) & _PAGE_PRESENT))
650 pgprot_val(ref_prot) &= ~_PAGE_PSE;
654 spin_unlock(&pgd_lock);
659 * Set the GLOBAL flags only if the PRESENT flag is set
660 * otherwise pmd/pte_present will return true even on a non
661 * present pmd/pte. The canon_pgprot will clear _PAGE_GLOBAL
662 * for the ancient hardware that doesn't support it.
664 if (pgprot_val(ref_prot) & _PAGE_PRESENT)
665 pgprot_val(ref_prot) |= _PAGE_GLOBAL;
667 pgprot_val(ref_prot) &= ~_PAGE_GLOBAL;
670 * Get the target pfn from the original entry:
673 for (i = 0; i < PTRS_PER_PTE; i++, pfn += pfninc)
674 set_pte(&pbase[i], pfn_pte(pfn, canon_pgprot(ref_prot)));
676 if (virt_addr_valid(address)) {
677 unsigned long pfn = PFN_DOWN(__pa(address));
679 if (pfn_range_is_mapped(pfn, pfn + 1))
680 split_page_count(level);
684 * Install the new, split up pagetable.
686 * We use the standard kernel pagetable protections for the new
687 * pagetable protections, the actual ptes set above control the
688 * primary protection behavior:
690 __set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE)));
693 * Intel Atom errata AAH41 workaround.
695 * The real fix should be in hw or in a microcode update, but
696 * we also probabilistically try to reduce the window of having
697 * a large TLB mixed with 4K TLBs while instruction fetches are
701 spin_unlock(&pgd_lock);
706 static int split_large_page(struct cpa_data *cpa, pte_t *kpte,
707 unsigned long address)
711 if (!debug_pagealloc_enabled())
712 spin_unlock(&cpa_lock);
713 base = alloc_pages(GFP_KERNEL | __GFP_NOTRACK, 0);
714 if (!debug_pagealloc_enabled())
715 spin_lock(&cpa_lock);
719 if (__split_large_page(cpa, kpte, address, base))
725 static bool try_to_free_pte_page(pte_t *pte)
729 for (i = 0; i < PTRS_PER_PTE; i++)
730 if (!pte_none(pte[i]))
733 free_page((unsigned long)pte);
737 static bool try_to_free_pmd_page(pmd_t *pmd)
741 for (i = 0; i < PTRS_PER_PMD; i++)
742 if (!pmd_none(pmd[i]))
745 free_page((unsigned long)pmd);
749 static bool unmap_pte_range(pmd_t *pmd, unsigned long start, unsigned long end)
751 pte_t *pte = pte_offset_kernel(pmd, start);
753 while (start < end) {
754 set_pte(pte, __pte(0));
760 if (try_to_free_pte_page((pte_t *)pmd_page_vaddr(*pmd))) {
767 static void __unmap_pmd_range(pud_t *pud, pmd_t *pmd,
768 unsigned long start, unsigned long end)
770 if (unmap_pte_range(pmd, start, end))
771 if (try_to_free_pmd_page((pmd_t *)pud_page_vaddr(*pud)))
775 static void unmap_pmd_range(pud_t *pud, unsigned long start, unsigned long end)
777 pmd_t *pmd = pmd_offset(pud, start);
780 * Not on a 2MB page boundary?
782 if (start & (PMD_SIZE - 1)) {
783 unsigned long next_page = (start + PMD_SIZE) & PMD_MASK;
784 unsigned long pre_end = min_t(unsigned long, end, next_page);
786 __unmap_pmd_range(pud, pmd, start, pre_end);
793 * Try to unmap in 2M chunks.
795 while (end - start >= PMD_SIZE) {
799 __unmap_pmd_range(pud, pmd, start, start + PMD_SIZE);
809 return __unmap_pmd_range(pud, pmd, start, end);
812 * Try again to free the PMD page if haven't succeeded above.
815 if (try_to_free_pmd_page((pmd_t *)pud_page_vaddr(*pud)))
819 static void unmap_pud_range(pgd_t *pgd, unsigned long start, unsigned long end)
821 pud_t *pud = pud_offset(pgd, start);
824 * Not on a GB page boundary?
826 if (start & (PUD_SIZE - 1)) {
827 unsigned long next_page = (start + PUD_SIZE) & PUD_MASK;
828 unsigned long pre_end = min_t(unsigned long, end, next_page);
830 unmap_pmd_range(pud, start, pre_end);
837 * Try to unmap in 1G chunks?
839 while (end - start >= PUD_SIZE) {
844 unmap_pmd_range(pud, start, start + PUD_SIZE);
854 unmap_pmd_range(pud, start, end);
857 * No need to try to free the PUD page because we'll free it in
858 * populate_pgd's error path
862 static int alloc_pte_page(pmd_t *pmd)
864 pte_t *pte = (pte_t *)get_zeroed_page(GFP_KERNEL | __GFP_NOTRACK);
868 set_pmd(pmd, __pmd(__pa(pte) | _KERNPG_TABLE));
872 static int alloc_pmd_page(pud_t *pud)
874 pmd_t *pmd = (pmd_t *)get_zeroed_page(GFP_KERNEL | __GFP_NOTRACK);
878 set_pud(pud, __pud(__pa(pmd) | _KERNPG_TABLE));
882 static void populate_pte(struct cpa_data *cpa,
883 unsigned long start, unsigned long end,
884 unsigned num_pages, pmd_t *pmd, pgprot_t pgprot)
888 pte = pte_offset_kernel(pmd, start);
891 * Set the GLOBAL flags only if the PRESENT flag is
892 * set otherwise pte_present will return true even on
893 * a non present pte. The canon_pgprot will clear
894 * _PAGE_GLOBAL for the ancient hardware that doesn't
897 if (pgprot_val(pgprot) & _PAGE_PRESENT)
898 pgprot_val(pgprot) |= _PAGE_GLOBAL;
900 pgprot_val(pgprot) &= ~_PAGE_GLOBAL;
902 pgprot = canon_pgprot(pgprot);
904 while (num_pages-- && start < end) {
905 set_pte(pte, pfn_pte(cpa->pfn, pgprot));
913 static int populate_pmd(struct cpa_data *cpa,
914 unsigned long start, unsigned long end,
915 unsigned num_pages, pud_t *pud, pgprot_t pgprot)
917 unsigned int cur_pages = 0;
922 * Not on a 2M boundary?
924 if (start & (PMD_SIZE - 1)) {
925 unsigned long pre_end = start + (num_pages << PAGE_SHIFT);
926 unsigned long next_page = (start + PMD_SIZE) & PMD_MASK;
928 pre_end = min_t(unsigned long, pre_end, next_page);
929 cur_pages = (pre_end - start) >> PAGE_SHIFT;
930 cur_pages = min_t(unsigned int, num_pages, cur_pages);
935 pmd = pmd_offset(pud, start);
937 if (alloc_pte_page(pmd))
940 populate_pte(cpa, start, pre_end, cur_pages, pmd, pgprot);
946 * We mapped them all?
948 if (num_pages == cur_pages)
951 pmd_pgprot = pgprot_4k_2_large(pgprot);
953 while (end - start >= PMD_SIZE) {
956 * We cannot use a 1G page so allocate a PMD page if needed.
959 if (alloc_pmd_page(pud))
962 pmd = pmd_offset(pud, start);
964 set_pmd(pmd, __pmd(cpa->pfn << PAGE_SHIFT | _PAGE_PSE |
965 massage_pgprot(pmd_pgprot)));
968 cpa->pfn += PMD_SIZE >> PAGE_SHIFT;
969 cur_pages += PMD_SIZE >> PAGE_SHIFT;
973 * Map trailing 4K pages.
976 pmd = pmd_offset(pud, start);
978 if (alloc_pte_page(pmd))
981 populate_pte(cpa, start, end, num_pages - cur_pages,
987 static int populate_pud(struct cpa_data *cpa, unsigned long start, pgd_t *pgd,
995 end = start + (cpa->numpages << PAGE_SHIFT);
998 * Not on a Gb page boundary? => map everything up to it with
1001 if (start & (PUD_SIZE - 1)) {
1002 unsigned long pre_end;
1003 unsigned long next_page = (start + PUD_SIZE) & PUD_MASK;
1005 pre_end = min_t(unsigned long, end, next_page);
1006 cur_pages = (pre_end - start) >> PAGE_SHIFT;
1007 cur_pages = min_t(int, (int)cpa->numpages, cur_pages);
1009 pud = pud_offset(pgd, start);
1015 if (alloc_pmd_page(pud))
1018 cur_pages = populate_pmd(cpa, start, pre_end, cur_pages,
1026 /* We mapped them all? */
1027 if (cpa->numpages == cur_pages)
1030 pud = pud_offset(pgd, start);
1031 pud_pgprot = pgprot_4k_2_large(pgprot);
1034 * Map everything starting from the Gb boundary, possibly with 1G pages
1036 while (boot_cpu_has(X86_FEATURE_GBPAGES) && end - start >= PUD_SIZE) {
1037 set_pud(pud, __pud(cpa->pfn << PAGE_SHIFT | _PAGE_PSE |
1038 massage_pgprot(pud_pgprot)));
1041 cpa->pfn += PUD_SIZE >> PAGE_SHIFT;
1042 cur_pages += PUD_SIZE >> PAGE_SHIFT;
1046 /* Map trailing leftover */
1050 pud = pud_offset(pgd, start);
1052 if (alloc_pmd_page(pud))
1055 tmp = populate_pmd(cpa, start, end, cpa->numpages - cur_pages,
1066 * Restrictions for kernel page table do not necessarily apply when mapping in
1069 static int populate_pgd(struct cpa_data *cpa, unsigned long addr)
1071 pgprot_t pgprot = __pgprot(_KERNPG_TABLE);
1072 pud_t *pud = NULL; /* shut up gcc */
1076 pgd_entry = cpa->pgd + pgd_index(addr);
1079 * Allocate a PUD page and hand it down for mapping.
1081 if (pgd_none(*pgd_entry)) {
1082 pud = (pud_t *)get_zeroed_page(GFP_KERNEL | __GFP_NOTRACK);
1087 pgprot_val(pgprot) &= ~pgprot_val(cpa->mask_clr);
1088 pgprot_val(pgprot) |= pgprot_val(cpa->mask_set);
1090 ret = populate_pud(cpa, addr, pgd_entry, pgprot);
1093 free_page((unsigned long)pud);
1094 unmap_pud_range(pgd_entry, addr,
1095 addr + (cpa->numpages << PAGE_SHIFT));
1100 set_pgd(pgd_entry, __pgd(__pa(pud) | _KERNPG_TABLE));
1102 cpa->numpages = ret;
1106 static int __cpa_process_fault(struct cpa_data *cpa, unsigned long vaddr,
1111 * Right now, we only execute this code path when mapping
1112 * the EFI virtual memory map regions, no other users
1113 * provide a ->pgd value. This may change in the future.
1115 return populate_pgd(cpa, vaddr);
1119 * Ignore all non primary paths.
1127 * Ignore the NULL PTE for kernel identity mapping, as it is expected
1129 * Also set numpages to '1' indicating that we processed cpa req for
1130 * one virtual address page and its pfn. TBD: numpages can be set based
1131 * on the initial value and the level returned by lookup_address().
1133 if (within(vaddr, PAGE_OFFSET,
1134 PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT))) {
1136 cpa->pfn = __pa(vaddr) >> PAGE_SHIFT;
1139 WARN(1, KERN_WARNING "CPA: called for zero pte. "
1140 "vaddr = %lx cpa->vaddr = %lx\n", vaddr,
1147 static int __change_page_attr(struct cpa_data *cpa, int primary)
1149 unsigned long address;
1152 pte_t *kpte, old_pte;
1154 if (cpa->flags & CPA_PAGES_ARRAY) {
1155 struct page *page = cpa->pages[cpa->curpage];
1156 if (unlikely(PageHighMem(page)))
1158 address = (unsigned long)page_address(page);
1159 } else if (cpa->flags & CPA_ARRAY)
1160 address = cpa->vaddr[cpa->curpage];
1162 address = *cpa->vaddr;
1164 kpte = _lookup_address_cpa(cpa, address, &level);
1166 return __cpa_process_fault(cpa, address, primary);
1169 if (pte_none(old_pte))
1170 return __cpa_process_fault(cpa, address, primary);
1172 if (level == PG_LEVEL_4K) {
1174 pgprot_t new_prot = pte_pgprot(old_pte);
1175 unsigned long pfn = pte_pfn(old_pte);
1177 pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr);
1178 pgprot_val(new_prot) |= pgprot_val(cpa->mask_set);
1180 new_prot = static_protections(new_prot, address, pfn);
1183 * Set the GLOBAL flags only if the PRESENT flag is
1184 * set otherwise pte_present will return true even on
1185 * a non present pte. The canon_pgprot will clear
1186 * _PAGE_GLOBAL for the ancient hardware that doesn't
1189 if (pgprot_val(new_prot) & _PAGE_PRESENT)
1190 pgprot_val(new_prot) |= _PAGE_GLOBAL;
1192 pgprot_val(new_prot) &= ~_PAGE_GLOBAL;
1195 * We need to keep the pfn from the existing PTE,
1196 * after all we're only going to change it's attributes
1197 * not the memory it points to
1199 new_pte = pfn_pte(pfn, canon_pgprot(new_prot));
1202 * Do we really change anything ?
1204 if (pte_val(old_pte) != pte_val(new_pte)) {
1205 set_pte_atomic(kpte, new_pte);
1206 cpa->flags |= CPA_FLUSHTLB;
1213 * Check, whether we can keep the large page intact
1214 * and just change the pte:
1216 do_split = try_preserve_large_page(kpte, address, cpa);
1218 * When the range fits into the existing large page,
1219 * return. cp->numpages and cpa->tlbflush have been updated in
1226 * We have to split the large page:
1228 err = split_large_page(cpa, kpte, address);
1231 * Do a global flush tlb after splitting the large page
1232 * and before we do the actual change page attribute in the PTE.
1234 * With out this, we violate the TLB application note, that says
1235 * "The TLBs may contain both ordinary and large-page
1236 * translations for a 4-KByte range of linear addresses. This
1237 * may occur if software modifies the paging structures so that
1238 * the page size used for the address range changes. If the two
1239 * translations differ with respect to page frame or attributes
1240 * (e.g., permissions), processor behavior is undefined and may
1241 * be implementation-specific."
1243 * We do this global tlb flush inside the cpa_lock, so that we
1244 * don't allow any other cpu, with stale tlb entries change the
1245 * page attribute in parallel, that also falls into the
1246 * just split large page entry.
1255 static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias);
1257 static int cpa_process_alias(struct cpa_data *cpa)
1259 struct cpa_data alias_cpa;
1260 unsigned long laddr = (unsigned long)__va(cpa->pfn << PAGE_SHIFT);
1261 unsigned long vaddr;
1264 if (!pfn_range_is_mapped(cpa->pfn, cpa->pfn + 1))
1268 * No need to redo, when the primary call touched the direct
1271 if (cpa->flags & CPA_PAGES_ARRAY) {
1272 struct page *page = cpa->pages[cpa->curpage];
1273 if (unlikely(PageHighMem(page)))
1275 vaddr = (unsigned long)page_address(page);
1276 } else if (cpa->flags & CPA_ARRAY)
1277 vaddr = cpa->vaddr[cpa->curpage];
1279 vaddr = *cpa->vaddr;
1281 if (!(within(vaddr, PAGE_OFFSET,
1282 PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT)))) {
1285 alias_cpa.vaddr = &laddr;
1286 alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY);
1288 ret = __change_page_attr_set_clr(&alias_cpa, 0);
1293 #ifdef CONFIG_X86_64
1295 * If the primary call didn't touch the high mapping already
1296 * and the physical address is inside the kernel map, we need
1297 * to touch the high mapped kernel as well:
1299 if (!within(vaddr, (unsigned long)_text, _brk_end) &&
1300 within(cpa->pfn, highmap_start_pfn(), highmap_end_pfn())) {
1301 unsigned long temp_cpa_vaddr = (cpa->pfn << PAGE_SHIFT) +
1302 __START_KERNEL_map - phys_base;
1304 alias_cpa.vaddr = &temp_cpa_vaddr;
1305 alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY);
1308 * The high mapping range is imprecise, so ignore the
1311 __change_page_attr_set_clr(&alias_cpa, 0);
1318 static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias)
1320 int ret, numpages = cpa->numpages;
1324 * Store the remaining nr of pages for the large page
1325 * preservation check.
1327 cpa->numpages = numpages;
1328 /* for array changes, we can't use large page */
1329 if (cpa->flags & (CPA_ARRAY | CPA_PAGES_ARRAY))
1332 if (!debug_pagealloc_enabled())
1333 spin_lock(&cpa_lock);
1334 ret = __change_page_attr(cpa, checkalias);
1335 if (!debug_pagealloc_enabled())
1336 spin_unlock(&cpa_lock);
1341 ret = cpa_process_alias(cpa);
1347 * Adjust the number of pages with the result of the
1348 * CPA operation. Either a large page has been
1349 * preserved or a single page update happened.
1351 BUG_ON(cpa->numpages > numpages || !cpa->numpages);
1352 numpages -= cpa->numpages;
1353 if (cpa->flags & (CPA_PAGES_ARRAY | CPA_ARRAY))
1356 *cpa->vaddr += cpa->numpages * PAGE_SIZE;
1362 static int change_page_attr_set_clr(unsigned long *addr, int numpages,
1363 pgprot_t mask_set, pgprot_t mask_clr,
1364 int force_split, int in_flag,
1365 struct page **pages)
1367 struct cpa_data cpa;
1368 int ret, cache, checkalias;
1369 unsigned long baddr = 0;
1371 memset(&cpa, 0, sizeof(cpa));
1374 * Check, if we are requested to change a not supported
1377 mask_set = canon_pgprot(mask_set);
1378 mask_clr = canon_pgprot(mask_clr);
1379 if (!pgprot_val(mask_set) && !pgprot_val(mask_clr) && !force_split)
1382 /* Ensure we are PAGE_SIZE aligned */
1383 if (in_flag & CPA_ARRAY) {
1385 for (i = 0; i < numpages; i++) {
1386 if (addr[i] & ~PAGE_MASK) {
1387 addr[i] &= PAGE_MASK;
1391 } else if (!(in_flag & CPA_PAGES_ARRAY)) {
1393 * in_flag of CPA_PAGES_ARRAY implies it is aligned.
1394 * No need to cehck in that case
1396 if (*addr & ~PAGE_MASK) {
1399 * People should not be passing in unaligned addresses:
1404 * Save address for cache flush. *addr is modified in the call
1405 * to __change_page_attr_set_clr() below.
1410 /* Must avoid aliasing mappings in the highmem code */
1411 kmap_flush_unused();
1417 cpa.numpages = numpages;
1418 cpa.mask_set = mask_set;
1419 cpa.mask_clr = mask_clr;
1422 cpa.force_split = force_split;
1424 if (in_flag & (CPA_ARRAY | CPA_PAGES_ARRAY))
1425 cpa.flags |= in_flag;
1427 /* No alias checking for _NX bit modifications */
1428 checkalias = (pgprot_val(mask_set) | pgprot_val(mask_clr)) != _PAGE_NX;
1430 ret = __change_page_attr_set_clr(&cpa, checkalias);
1433 * Check whether we really changed something:
1435 if (!(cpa.flags & CPA_FLUSHTLB))
1439 * No need to flush, when we did not set any of the caching
1442 cache = !!pgprot2cachemode(mask_set);
1445 * On success we use CLFLUSH, when the CPU supports it to
1446 * avoid the WBINVD. If the CPU does not support it and in the
1447 * error case we fall back to cpa_flush_all (which uses
1450 if (!ret && boot_cpu_has(X86_FEATURE_CLFLUSH)) {
1451 if (cpa.flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) {
1452 cpa_flush_array(addr, numpages, cache,
1455 cpa_flush_range(baddr, numpages, cache);
1457 cpa_flush_all(cache);
1463 static inline int change_page_attr_set(unsigned long *addr, int numpages,
1464 pgprot_t mask, int array)
1466 return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0), 0,
1467 (array ? CPA_ARRAY : 0), NULL);
1470 static inline int change_page_attr_clear(unsigned long *addr, int numpages,
1471 pgprot_t mask, int array)
1473 return change_page_attr_set_clr(addr, numpages, __pgprot(0), mask, 0,
1474 (array ? CPA_ARRAY : 0), NULL);
1477 static inline int cpa_set_pages_array(struct page **pages, int numpages,
1480 return change_page_attr_set_clr(NULL, numpages, mask, __pgprot(0), 0,
1481 CPA_PAGES_ARRAY, pages);
1484 static inline int cpa_clear_pages_array(struct page **pages, int numpages,
1487 return change_page_attr_set_clr(NULL, numpages, __pgprot(0), mask, 0,
1488 CPA_PAGES_ARRAY, pages);
1491 int _set_memory_uc(unsigned long addr, int numpages)
1494 * for now UC MINUS. see comments in ioremap_nocache()
1495 * If you really need strong UC use ioremap_uc(), but note
1496 * that you cannot override IO areas with set_memory_*() as
1497 * these helpers cannot work with IO memory.
1499 return change_page_attr_set(&addr, numpages,
1500 cachemode2pgprot(_PAGE_CACHE_MODE_UC_MINUS),
1504 int set_memory_uc(unsigned long addr, int numpages)
1509 * for now UC MINUS. see comments in ioremap_nocache()
1511 ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE,
1512 _PAGE_CACHE_MODE_UC_MINUS, NULL);
1516 ret = _set_memory_uc(addr, numpages);
1523 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
1527 EXPORT_SYMBOL(set_memory_uc);
1529 static int _set_memory_array(unsigned long *addr, int addrinarray,
1530 enum page_cache_mode new_type)
1532 enum page_cache_mode set_type;
1536 for (i = 0; i < addrinarray; i++) {
1537 ret = reserve_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE,
1543 /* If WC, set to UC- first and then WC */
1544 set_type = (new_type == _PAGE_CACHE_MODE_WC) ?
1545 _PAGE_CACHE_MODE_UC_MINUS : new_type;
1547 ret = change_page_attr_set(addr, addrinarray,
1548 cachemode2pgprot(set_type), 1);
1550 if (!ret && new_type == _PAGE_CACHE_MODE_WC)
1551 ret = change_page_attr_set_clr(addr, addrinarray,
1553 _PAGE_CACHE_MODE_WC),
1554 __pgprot(_PAGE_CACHE_MASK),
1555 0, CPA_ARRAY, NULL);
1562 for (j = 0; j < i; j++)
1563 free_memtype(__pa(addr[j]), __pa(addr[j]) + PAGE_SIZE);
1568 int set_memory_array_uc(unsigned long *addr, int addrinarray)
1570 return _set_memory_array(addr, addrinarray, _PAGE_CACHE_MODE_UC_MINUS);
1572 EXPORT_SYMBOL(set_memory_array_uc);
1574 int set_memory_array_wc(unsigned long *addr, int addrinarray)
1576 return _set_memory_array(addr, addrinarray, _PAGE_CACHE_MODE_WC);
1578 EXPORT_SYMBOL(set_memory_array_wc);
1580 int set_memory_array_wt(unsigned long *addr, int addrinarray)
1582 return _set_memory_array(addr, addrinarray, _PAGE_CACHE_MODE_WT);
1584 EXPORT_SYMBOL_GPL(set_memory_array_wt);
1586 int _set_memory_wc(unsigned long addr, int numpages)
1589 unsigned long addr_copy = addr;
1591 ret = change_page_attr_set(&addr, numpages,
1592 cachemode2pgprot(_PAGE_CACHE_MODE_UC_MINUS),
1595 ret = change_page_attr_set_clr(&addr_copy, numpages,
1597 _PAGE_CACHE_MODE_WC),
1598 __pgprot(_PAGE_CACHE_MASK),
1604 int set_memory_wc(unsigned long addr, int numpages)
1608 ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE,
1609 _PAGE_CACHE_MODE_WC, NULL);
1613 ret = _set_memory_wc(addr, numpages);
1615 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
1619 EXPORT_SYMBOL(set_memory_wc);
1621 int _set_memory_wt(unsigned long addr, int numpages)
1623 return change_page_attr_set(&addr, numpages,
1624 cachemode2pgprot(_PAGE_CACHE_MODE_WT), 0);
1627 int set_memory_wt(unsigned long addr, int numpages)
1631 ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE,
1632 _PAGE_CACHE_MODE_WT, NULL);
1636 ret = _set_memory_wt(addr, numpages);
1638 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
1642 EXPORT_SYMBOL_GPL(set_memory_wt);
1644 int _set_memory_wb(unsigned long addr, int numpages)
1646 /* WB cache mode is hard wired to all cache attribute bits being 0 */
1647 return change_page_attr_clear(&addr, numpages,
1648 __pgprot(_PAGE_CACHE_MASK), 0);
1651 int set_memory_wb(unsigned long addr, int numpages)
1655 ret = _set_memory_wb(addr, numpages);
1659 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
1662 EXPORT_SYMBOL(set_memory_wb);
1664 int set_memory_array_wb(unsigned long *addr, int addrinarray)
1669 /* WB cache mode is hard wired to all cache attribute bits being 0 */
1670 ret = change_page_attr_clear(addr, addrinarray,
1671 __pgprot(_PAGE_CACHE_MASK), 1);
1675 for (i = 0; i < addrinarray; i++)
1676 free_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE);
1680 EXPORT_SYMBOL(set_memory_array_wb);
1682 int set_memory_x(unsigned long addr, int numpages)
1684 if (!(__supported_pte_mask & _PAGE_NX))
1687 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_NX), 0);
1689 EXPORT_SYMBOL(set_memory_x);
1691 int set_memory_nx(unsigned long addr, int numpages)
1693 if (!(__supported_pte_mask & _PAGE_NX))
1696 return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_NX), 0);
1698 EXPORT_SYMBOL(set_memory_nx);
1700 int set_memory_ro(unsigned long addr, int numpages)
1702 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_RW), 0);
1705 int set_memory_rw(unsigned long addr, int numpages)
1707 return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_RW), 0);
1710 int set_memory_np(unsigned long addr, int numpages)
1712 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_PRESENT), 0);
1715 int set_memory_4k(unsigned long addr, int numpages)
1717 return change_page_attr_set_clr(&addr, numpages, __pgprot(0),
1718 __pgprot(0), 1, 0, NULL);
1721 int set_pages_uc(struct page *page, int numpages)
1723 unsigned long addr = (unsigned long)page_address(page);
1725 return set_memory_uc(addr, numpages);
1727 EXPORT_SYMBOL(set_pages_uc);
1729 static int _set_pages_array(struct page **pages, int addrinarray,
1730 enum page_cache_mode new_type)
1732 unsigned long start;
1734 enum page_cache_mode set_type;
1739 for (i = 0; i < addrinarray; i++) {
1740 if (PageHighMem(pages[i]))
1742 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
1743 end = start + PAGE_SIZE;
1744 if (reserve_memtype(start, end, new_type, NULL))
1748 /* If WC, set to UC- first and then WC */
1749 set_type = (new_type == _PAGE_CACHE_MODE_WC) ?
1750 _PAGE_CACHE_MODE_UC_MINUS : new_type;
1752 ret = cpa_set_pages_array(pages, addrinarray,
1753 cachemode2pgprot(set_type));
1754 if (!ret && new_type == _PAGE_CACHE_MODE_WC)
1755 ret = change_page_attr_set_clr(NULL, addrinarray,
1757 _PAGE_CACHE_MODE_WC),
1758 __pgprot(_PAGE_CACHE_MASK),
1759 0, CPA_PAGES_ARRAY, pages);
1762 return 0; /* Success */
1765 for (i = 0; i < free_idx; i++) {
1766 if (PageHighMem(pages[i]))
1768 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
1769 end = start + PAGE_SIZE;
1770 free_memtype(start, end);
1775 int set_pages_array_uc(struct page **pages, int addrinarray)
1777 return _set_pages_array(pages, addrinarray, _PAGE_CACHE_MODE_UC_MINUS);
1779 EXPORT_SYMBOL(set_pages_array_uc);
1781 int set_pages_array_wc(struct page **pages, int addrinarray)
1783 return _set_pages_array(pages, addrinarray, _PAGE_CACHE_MODE_WC);
1785 EXPORT_SYMBOL(set_pages_array_wc);
1787 int set_pages_array_wt(struct page **pages, int addrinarray)
1789 return _set_pages_array(pages, addrinarray, _PAGE_CACHE_MODE_WT);
1791 EXPORT_SYMBOL_GPL(set_pages_array_wt);
1793 int set_pages_wb(struct page *page, int numpages)
1795 unsigned long addr = (unsigned long)page_address(page);
1797 return set_memory_wb(addr, numpages);
1799 EXPORT_SYMBOL(set_pages_wb);
1801 int set_pages_array_wb(struct page **pages, int addrinarray)
1804 unsigned long start;
1808 /* WB cache mode is hard wired to all cache attribute bits being 0 */
1809 retval = cpa_clear_pages_array(pages, addrinarray,
1810 __pgprot(_PAGE_CACHE_MASK));
1814 for (i = 0; i < addrinarray; i++) {
1815 if (PageHighMem(pages[i]))
1817 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
1818 end = start + PAGE_SIZE;
1819 free_memtype(start, end);
1824 EXPORT_SYMBOL(set_pages_array_wb);
1826 int set_pages_x(struct page *page, int numpages)
1828 unsigned long addr = (unsigned long)page_address(page);
1830 return set_memory_x(addr, numpages);
1832 EXPORT_SYMBOL(set_pages_x);
1834 int set_pages_nx(struct page *page, int numpages)
1836 unsigned long addr = (unsigned long)page_address(page);
1838 return set_memory_nx(addr, numpages);
1840 EXPORT_SYMBOL(set_pages_nx);
1842 int set_pages_ro(struct page *page, int numpages)
1844 unsigned long addr = (unsigned long)page_address(page);
1846 return set_memory_ro(addr, numpages);
1849 int set_pages_rw(struct page *page, int numpages)
1851 unsigned long addr = (unsigned long)page_address(page);
1853 return set_memory_rw(addr, numpages);
1856 #ifdef CONFIG_DEBUG_PAGEALLOC
1858 static int __set_pages_p(struct page *page, int numpages)
1860 unsigned long tempaddr = (unsigned long) page_address(page);
1861 struct cpa_data cpa = { .vaddr = &tempaddr,
1863 .numpages = numpages,
1864 .mask_set = __pgprot(_PAGE_PRESENT | _PAGE_RW),
1865 .mask_clr = __pgprot(0),
1869 * No alias checking needed for setting present flag. otherwise,
1870 * we may need to break large pages for 64-bit kernel text
1871 * mappings (this adds to complexity if we want to do this from
1872 * atomic context especially). Let's keep it simple!
1874 return __change_page_attr_set_clr(&cpa, 0);
1877 static int __set_pages_np(struct page *page, int numpages)
1879 unsigned long tempaddr = (unsigned long) page_address(page);
1880 struct cpa_data cpa = { .vaddr = &tempaddr,
1882 .numpages = numpages,
1883 .mask_set = __pgprot(0),
1884 .mask_clr = __pgprot(_PAGE_PRESENT | _PAGE_RW),
1888 * No alias checking needed for setting not present flag. otherwise,
1889 * we may need to break large pages for 64-bit kernel text
1890 * mappings (this adds to complexity if we want to do this from
1891 * atomic context especially). Let's keep it simple!
1893 return __change_page_attr_set_clr(&cpa, 0);
1896 void __kernel_map_pages(struct page *page, int numpages, int enable)
1898 if (PageHighMem(page))
1901 debug_check_no_locks_freed(page_address(page),
1902 numpages * PAGE_SIZE);
1906 * The return value is ignored as the calls cannot fail.
1907 * Large pages for identity mappings are not used at boot time
1908 * and hence no memory allocations during large page split.
1911 __set_pages_p(page, numpages);
1913 __set_pages_np(page, numpages);
1916 * We should perform an IPI and flush all tlbs,
1917 * but that can deadlock->flush only current cpu:
1921 arch_flush_lazy_mmu_mode();
1924 #ifdef CONFIG_HIBERNATION
1926 bool kernel_page_present(struct page *page)
1931 if (PageHighMem(page))
1934 pte = lookup_address((unsigned long)page_address(page), &level);
1935 return (pte_val(*pte) & _PAGE_PRESENT);
1938 #endif /* CONFIG_HIBERNATION */
1940 #endif /* CONFIG_DEBUG_PAGEALLOC */
1942 int kernel_map_pages_in_pgd(pgd_t *pgd, u64 pfn, unsigned long address,
1943 unsigned numpages, unsigned long page_flags)
1945 int retval = -EINVAL;
1947 struct cpa_data cpa = {
1951 .numpages = numpages,
1952 .mask_set = __pgprot(0),
1953 .mask_clr = __pgprot(0),
1957 if (!(__supported_pte_mask & _PAGE_NX))
1960 if (!(page_flags & _PAGE_NX))
1961 cpa.mask_clr = __pgprot(_PAGE_NX);
1963 if (!(page_flags & _PAGE_RW))
1964 cpa.mask_clr = __pgprot(_PAGE_RW);
1966 cpa.mask_set = __pgprot(_PAGE_PRESENT | page_flags);
1968 retval = __change_page_attr_set_clr(&cpa, 0);
1976 * The testcases use internal knowledge of the implementation that shouldn't
1977 * be exposed to the rest of the kernel. Include these directly here.
1979 #ifdef CONFIG_CPA_DEBUG
1980 #include "pageattr-test.c"