arch/xtensa/kernel/setup.c

   1 /*
   2  * arch/xtensa/kernel/setup.c
   3  *
   4  * This file is subject to the terms and conditions of the GNU General Public
   5  * License.  See the file "COPYING" in the main directory of this archive
   6  * for more details.
   7  *
   8  * Copyright (C) 1995  Linus Torvalds
   9  * Copyright (C) 2001 - 2005  Tensilica Inc.
  10  *
  11  * Chris Zankel <chris@zankel.net>
  12  * Joe Taylor   <joe@tensilica.com, joetylr@yahoo.com>
  13  * Kevin Chea
  14  * Marc Gauthier<marc@tensilica.com> <marc@alumni.uwaterloo.ca>
  15  */
  16
  17 #include <linux/errno.h>
  18 #include <linux/init.h>
  19 #include <linux/mm.h>
  20 #include <linux/proc_fs.h>
  21 #include <linux/screen_info.h>
  22 #include <linux/bootmem.h>
  23 #include <linux/kernel.h>
  24 #include <linux/percpu.h>
  25 #include <linux/cpu.h>
  26 #include <linux/of_fdt.h>
  27
  28 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
  29 # include <linux/console.h>
  30 #endif
  31
  32 #ifdef CONFIG_RTC
  33 # include <linux/timex.h>
  34 #endif
  35
  36 #ifdef CONFIG_PROC_FS
  37 # include <linux/seq_file.h>
  38 #endif
  39
  40 #include <asm/bootparam.h>
  41 #include <asm/mmu_context.h>
  42 #include <asm/pgtable.h>
  43 #include <asm/processor.h>
  44 #include <asm/timex.h>
  45 #include <asm/platform.h>
  46 #include <asm/page.h>
  47 #include <asm/setup.h>
  48 #include <asm/param.h>
  49 #include <asm/traps.h>
  50 #include <asm/smp.h>
  51 #include <asm/sysmem.h>
  52
  53 #include <platform/hardware.h>
  54
  55 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
  56 struct screen_info screen_info = { 0, 24, 0, 0, 0, 80, 0, 0, 0, 24, 1, 16};
  57 #endif
  58
  59 #ifdef CONFIG_BLK_DEV_FD
  60 extern struct fd_ops no_fd_ops;
  61 struct fd_ops *fd_ops;
  62 #endif
  63
  64 extern struct rtc_ops no_rtc_ops;
  65 struct rtc_ops *rtc_ops;
  66
  67 #ifdef CONFIG_BLK_DEV_INITRD
  68 extern unsigned long initrd_start;
  69 extern unsigned long initrd_end;
  70 int initrd_is_mapped = 0;
  71 extern int initrd_below_start_ok;
  72 #endif
  73
  74 #ifdef CONFIG_OF
  75 void *dtb_start = __dtb_start;
  76 #endif
  77
  78 unsigned char aux_device_present;
  79 extern unsigned long loops_per_jiffy;
  80
  81 /* Command line specified as configuration option. */
  82
  83 static char __initdata command_line[COMMAND_LINE_SIZE];
  84
  85 #ifdef CONFIG_CMDLINE_BOOL
  86 static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
  87 #endif
  88
  89 /*
  90  * Boot parameter parsing.
  91  *
  92  * The Xtensa port uses a list of variable-sized tags to pass data to
  93  * the kernel. The first tag must be a BP_TAG_FIRST tag for the list
  94  * to be recognised. The list is terminated with a zero-sized
  95  * BP_TAG_LAST tag.
  96  */
  97
  98 typedef struct tagtable {
  99         u32 tag;
 100         int (*parse)(const bp_tag_t*);
 101 } tagtable_t;
 102
 103 #define __tagtable(tag, fn) static tagtable_t __tagtable_##fn           \
 104         __attribute__((used, section(".taglist"))) = { tag, fn }
 105
 106 /* parse current tag */
 107
 108 static int __init parse_tag_mem(const bp_tag_t *tag)
 109 {
 110         struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);
 111
 112         if (mi->type != MEMORY_TYPE_CONVENTIONAL)
 113                 return -1;
 114
 115         return add_sysmem_bank(mi->start, mi->end);
 116 }
 117
 118 __tagtable(BP_TAG_MEMORY, parse_tag_mem);
 119
 120 #ifdef CONFIG_BLK_DEV_INITRD
 121
 122 static int __init parse_tag_initrd(const bp_tag_t* tag)
 123 {
 124         struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);
 125
 126         initrd_start = (unsigned long)__va(mi->start);
 127         initrd_end = (unsigned long)__va(mi->end);
 128
 129         return 0;
 130 }
 131
 132 __tagtable(BP_TAG_INITRD, parse_tag_initrd);
 133
 134 #ifdef CONFIG_OF
 135
 136 static int __init parse_tag_fdt(const bp_tag_t *tag)
 137 {
 138         dtb_start = __va(tag->data[0]);
 139         return 0;
 140 }
 141
 142 __tagtable(BP_TAG_FDT, parse_tag_fdt);
 143
 144 #endif /* CONFIG_OF */
 145
 146 #endif /* CONFIG_BLK_DEV_INITRD */
 147
 148 static int __init parse_tag_cmdline(const bp_tag_t* tag)
 149 {
 150         strlcpy(command_line, (char *)(tag->data), COMMAND_LINE_SIZE);
 151         return 0;
 152 }
 153
 154 __tagtable(BP_TAG_COMMAND_LINE, parse_tag_cmdline);
 155
 156 static int __init parse_bootparam(const bp_tag_t* tag)
 157 {
 158         extern tagtable_t __tagtable_begin, __tagtable_end;
 159         tagtable_t *t;
 160
 161         /* Boot parameters must start with a BP_TAG_FIRST tag. */
 162
 163         if (tag->id != BP_TAG_FIRST) {
 164                 printk(KERN_WARNING "Invalid boot parameters!\n");
 165                 return 0;
 166         }
 167
 168         tag = (bp_tag_t*)((unsigned long)tag + sizeof(bp_tag_t) + tag->size);
 169
 170         /* Parse all tags. */
 171
 172         while (tag != NULL && tag->id != BP_TAG_LAST) {
 173                 for (t = &__tagtable_begin; t < &__tagtable_end; t++) {
 174                         if (tag->id == t->tag) {
 175                                 t->parse(tag);
 176                                 break;
 177                         }
 178                 }
 179                 if (t == &__tagtable_end)
 180                         printk(KERN_WARNING "Ignoring tag "
 181                                "0x%08x\n", tag->id);
 182                 tag = (bp_tag_t*)((unsigned long)(tag + 1) + tag->size);
 183         }
 184
 185         return 0;
 186 }
 187
 188 #ifdef CONFIG_OF
 189 bool __initdata dt_memory_scan = false;
 190
 191 #if !XCHAL_HAVE_PTP_MMU || XCHAL_HAVE_SPANNING_WAY
 192 unsigned long xtensa_kio_paddr = XCHAL_KIO_DEFAULT_PADDR;
 193 EXPORT_SYMBOL(xtensa_kio_paddr);
 194
 195 static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
 196                 int depth, void *data)
 197 {
 198         const __be32 *ranges;
 199         int len;
 200
 201         if (depth > 1)
 202                 return 0;
 203
 204         if (!of_flat_dt_is_compatible(node, "simple-bus"))
 205                 return 0;
 206
 207         ranges = of_get_flat_dt_prop(node, "ranges", &len);
 208         if (!ranges)
 209                 return 1;
 210         if (len == 0)
 211                 return 1;
 212
 213         xtensa_kio_paddr = of_read_ulong(ranges+1, 1);
 214         /* round down to nearest 256MB boundary */
 215         xtensa_kio_paddr &= 0xf0000000;
 216
 217         return 1;
 218 }
 219 #else
 220 static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
 221                 int depth, void *data)
 222 {
 223         return 1;
 224 }
 225 #endif
 226
 227 void __init early_init_dt_add_memory_arch(u64 base, u64 size)
 228 {
 229         if (!dt_memory_scan)
 230                 return;
 231
 232         size &= PAGE_MASK;
 233         add_sysmem_bank(base, base + size);
 234 }
 235
 236 void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
 237 {
 238         return __alloc_bootmem(size, align, 0);
 239 }
 240
 241 void __init early_init_devtree(void *params)
 242 {
 243         if (sysmem.nr_banks == 0)
 244                 dt_memory_scan = true;
 245
 246         early_init_dt_scan(params);
 247         of_scan_flat_dt(xtensa_dt_io_area, NULL);
 248
 249         if (!command_line[0])
 250                 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
 251 }
 252
 253 #endif /* CONFIG_OF */
 254
 255 /*
 256  * Initialize architecture. (Early stage)
 257  */
 258
 259 void __init init_arch(bp_tag_t *bp_start)
 260 {
 261         /* Parse boot parameters */
 262
 263         if (bp_start)
 264                 parse_bootparam(bp_start);
 265
 266 #ifdef CONFIG_OF
 267         early_init_devtree(dtb_start);
 268 #endif
 269
 270         if (sysmem.nr_banks == 0) {
 271                 add_sysmem_bank(PLATFORM_DEFAULT_MEM_START,
 272                                 PLATFORM_DEFAULT_MEM_START +
 273                                 PLATFORM_DEFAULT_MEM_SIZE);
 274         }
 275
 276 #ifdef CONFIG_CMDLINE_BOOL
 277         if (!command_line[0])
 278                 strlcpy(command_line, default_command_line, COMMAND_LINE_SIZE);
 279 #endif
 280
 281         /* Early hook for platforms */
 282
 283         platform_init(bp_start);
 284
 285         /* Initialize MMU. */
 286
 287         init_mmu();
 288 }
 289
 290 /*
 291  * Initialize system. Setup memory and reserve regions.
 292  */
 293
 294 extern char _end;
 295 extern char _stext;
 296 extern char _WindowVectors_text_start;
 297 extern char _WindowVectors_text_end;
 298 extern char _DebugInterruptVector_literal_start;
 299 extern char _DebugInterruptVector_text_end;
 300 extern char _KernelExceptionVector_literal_start;
 301 extern char _KernelExceptionVector_text_end;
 302 extern char _UserExceptionVector_literal_start;
 303 extern char _UserExceptionVector_text_end;
 304 extern char _DoubleExceptionVector_literal_start;
 305 extern char _DoubleExceptionVector_text_end;
 306 #if XCHAL_EXCM_LEVEL >= 2
 307 extern char _Level2InterruptVector_text_start;
 308 extern char _Level2InterruptVector_text_end;
 309 #endif
 310 #if XCHAL_EXCM_LEVEL >= 3
 311 extern char _Level3InterruptVector_text_start;
 312 extern char _Level3InterruptVector_text_end;
 313 #endif
 314 #if XCHAL_EXCM_LEVEL >= 4
 315 extern char _Level4InterruptVector_text_start;
 316 extern char _Level4InterruptVector_text_end;
 317 #endif
 318 #if XCHAL_EXCM_LEVEL >= 5
 319 extern char _Level5InterruptVector_text_start;
 320 extern char _Level5InterruptVector_text_end;
 321 #endif
 322 #if XCHAL_EXCM_LEVEL >= 6
 323 extern char _Level6InterruptVector_text_start;
 324 extern char _Level6InterruptVector_text_end;
 325 #endif
 326 #ifdef CONFIG_SMP
 327 extern char _SecondaryResetVector_text_start;
 328 extern char _SecondaryResetVector_text_end;
 329 #endif
 330
 331
 332 #ifdef CONFIG_S32C1I_SELFTEST
 333 #if XCHAL_HAVE_S32C1I
 334
 335 static int __initdata rcw_word, rcw_probe_pc, rcw_exc;
 336
 337 /*
 338  * Basic atomic compare-and-swap, that records PC of S32C1I for probing.
 339  *
 340  * If *v == cmp, set *v = set.  Return previous *v.
 341  */
 342 static inline int probed_compare_swap(int *v, int cmp, int set)
 343 {
 344         int tmp;
 345
 346         __asm__ __volatile__(
 347                         "       movi    %1, 1f\n"
 348                         "       s32i    %1, %4, 0\n"
 349                         "       wsr     %2, scompare1\n"
 350                         "1:     s32c1i  %0, %3, 0\n"
 351                         : "=a" (set), "=&a" (tmp)
 352                         : "a" (cmp), "a" (v), "a" (&rcw_probe_pc), "0" (set)
 353                         : "memory"
 354                         );
 355         return set;
 356 }
 357
 358 /* Handle probed exception */
 359
 360 static void __init do_probed_exception(struct pt_regs *regs,
 361                 unsigned long exccause)
 362 {
 363         if (regs->pc == rcw_probe_pc) { /* exception on s32c1i ? */
 364                 regs->pc += 3;          /* skip the s32c1i instruction */
 365                 rcw_exc = exccause;
 366         } else {
 367                 do_unhandled(regs, exccause);
 368         }
 369 }
 370
 371 /* Simple test of S32C1I (soc bringup assist) */
 372
 373 static int __init check_s32c1i(void)
 374 {
 375         int n, cause1, cause2;
 376         void *handbus, *handdata, *handaddr; /* temporarily saved handlers */
 377
 378         rcw_probe_pc = 0;
 379         handbus  = trap_set_handler(EXCCAUSE_LOAD_STORE_ERROR,
 380                         do_probed_exception);
 381         handdata = trap_set_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR,
 382                         do_probed_exception);
 383         handaddr = trap_set_handler(EXCCAUSE_LOAD_STORE_ADDR_ERROR,
 384                         do_probed_exception);
 385
 386         /* First try an S32C1I that does not store: */
 387         rcw_exc = 0;
 388         rcw_word = 1;
 389         n = probed_compare_swap(&rcw_word, 0, 2);
 390         cause1 = rcw_exc;
 391
 392         /* took exception? */
 393         if (cause1 != 0) {
 394                 /* unclean exception? */
 395                 if (n != 2 || rcw_word != 1)
 396                         panic("S32C1I exception error");
 397         } else if (rcw_word != 1 || n != 1) {
 398                 panic("S32C1I compare error");
 399         }
 400
 401         /* Then an S32C1I that stores: */
 402         rcw_exc = 0;
 403         rcw_word = 0x1234567;
 404         n = probed_compare_swap(&rcw_word, 0x1234567, 0xabcde);
 405         cause2 = rcw_exc;
 406
 407         if (cause2 != 0) {
 408                 /* unclean exception? */
 409                 if (n != 0xabcde || rcw_word != 0x1234567)
 410                         panic("S32C1I exception error (b)");
 411         } else if (rcw_word != 0xabcde || n != 0x1234567) {
 412                 panic("S32C1I store error");
 413         }
 414
 415         /* Verify consistency of exceptions: */
 416         if (cause1 || cause2) {
 417                 pr_warn("S32C1I took exception %d, %d\n", cause1, cause2);
 418                 /* If emulation of S32C1I upon bus error gets implemented,
 419                    we can get rid of this panic for single core (not SMP) */
 420                 panic("S32C1I exceptions not currently supported");
 421         }
 422         if (cause1 != cause2)
 423                 panic("inconsistent S32C1I exceptions");
 424
 425         trap_set_handler(EXCCAUSE_LOAD_STORE_ERROR, handbus);
 426         trap_set_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR, handdata);
 427         trap_set_handler(EXCCAUSE_LOAD_STORE_ADDR_ERROR, handaddr);
 428         return 0;
 429 }
 430
 431 #else /* XCHAL_HAVE_S32C1I */
 432
 433 /* This condition should not occur with a commercially deployed processor.
 434    Display reminder for early engr test or demo chips / FPGA bitstreams */
 435 static int __init check_s32c1i(void)
 436 {
 437         pr_warn("Processor configuration lacks atomic compare-and-swap support!\n");
 438         return 0;
 439 }
 440
 441 #endif /* XCHAL_HAVE_S32C1I */
 442 early_initcall(check_s32c1i);
 443 #endif /* CONFIG_S32C1I_SELFTEST */
 444
 445
 446 void __init setup_arch(char **cmdline_p)
 447 {
 448         strlcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
 449         *cmdline_p = command_line;
 450
 451         /* Reserve some memory regions */
 452
 453 #ifdef CONFIG_BLK_DEV_INITRD
 454         if (initrd_start < initrd_end) {
 455                 initrd_is_mapped = mem_reserve(__pa(initrd_start),
 456                                                __pa(initrd_end), 0) == 0;
 457                 initrd_below_start_ok = 1;
 458         } else {
 459                 initrd_start = 0;
 460         }
 461 #endif
 462
 463         mem_reserve(__pa(&_stext),__pa(&_end), 1);
 464
 465         mem_reserve(__pa(&_WindowVectors_text_start),
 466                     __pa(&_WindowVectors_text_end), 0);
 467
 468         mem_reserve(__pa(&_DebugInterruptVector_literal_start),
 469                     __pa(&_DebugInterruptVector_text_end), 0);
 470
 471         mem_reserve(__pa(&_KernelExceptionVector_literal_start),
 472                     __pa(&_KernelExceptionVector_text_end), 0);
 473
 474         mem_reserve(__pa(&_UserExceptionVector_literal_start),
 475                     __pa(&_UserExceptionVector_text_end), 0);
 476
 477         mem_reserve(__pa(&_DoubleExceptionVector_literal_start),
 478                     __pa(&_DoubleExceptionVector_text_end), 0);
 479
 480 #if XCHAL_EXCM_LEVEL >= 2
 481         mem_reserve(__pa(&_Level2InterruptVector_text_start),
 482                     __pa(&_Level2InterruptVector_text_end), 0);
 483 #endif
 484 #if XCHAL_EXCM_LEVEL >= 3
 485         mem_reserve(__pa(&_Level3InterruptVector_text_start),
 486                     __pa(&_Level3InterruptVector_text_end), 0);
 487 #endif
 488 #if XCHAL_EXCM_LEVEL >= 4
 489         mem_reserve(__pa(&_Level4InterruptVector_text_start),
 490                     __pa(&_Level4InterruptVector_text_end), 0);
 491 #endif
 492 #if XCHAL_EXCM_LEVEL >= 5
 493         mem_reserve(__pa(&_Level5InterruptVector_text_start),
 494                     __pa(&_Level5InterruptVector_text_end), 0);
 495 #endif
 496 #if XCHAL_EXCM_LEVEL >= 6
 497         mem_reserve(__pa(&_Level6InterruptVector_text_start),
 498                     __pa(&_Level6InterruptVector_text_end), 0);
 499 #endif
 500
 501 #ifdef CONFIG_SMP
 502         mem_reserve(__pa(&_SecondaryResetVector_text_start),
 503                     __pa(&_SecondaryResetVector_text_end), 0);
 504 #endif
 505         parse_early_param();
 506         bootmem_init();
 507
 508         unflatten_and_copy_device_tree();
 509
 510         platform_setup(cmdline_p);
 511
 512 #ifdef CONFIG_SMP
 513         smp_init_cpus();
 514 #endif
 515
 516         paging_init();
 517         zones_init();
 518
 519 #ifdef CONFIG_VT
 520 # if defined(CONFIG_VGA_CONSOLE)
 521         conswitchp = &vga_con;
 522 # elif defined(CONFIG_DUMMY_CONSOLE)
 523         conswitchp = &dummy_con;
 524 # endif
 525 #endif
 526
 527 #ifdef CONFIG_PCI
 528         platform_pcibios_init();
 529 #endif
 530 }
 531
 532 static DEFINE_PER_CPU(struct cpu, cpu_data);
 533
 534 static int __init topology_init(void)
 535 {
 536         int i;
 537
 538         for_each_possible_cpu(i) {
 539                 struct cpu *cpu = &per_cpu(cpu_data, i);
 540                 cpu->hotpluggable = !!i;
 541                 register_cpu(cpu, i);
 542         }
 543
 544         return 0;
 545 }
 546 subsys_initcall(topology_init);
 547
 548 void machine_restart(char * cmd)
 549 {
 550         platform_restart();
 551 }
 552
 553 void machine_halt(void)
 554 {
 555         platform_halt();
 556         while (1);
 557 }
 558
 559 void machine_power_off(void)
 560 {
 561         platform_power_off();
 562         while (1);
 563 }
 564 #ifdef CONFIG_PROC_FS
 565
 566 /*
 567  * Display some core information through /proc/cpuinfo.
 568  */
 569
 570 static int
 571 c_show(struct seq_file *f, void *slot)
 572 {
 573         /* high-level stuff */
 574         seq_printf(f, "CPU count\t: %u\n"
 575                       "CPU list\t: %*pbl\n"
 576                       "vendor_id\t: Tensilica\n"
 577                       "model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n"
 578                       "core ID\t\t: " XCHAL_CORE_ID "\n"
 579                       "build ID\t: 0x%x\n"
 580                       "byte order\t: %s\n"
 581                       "cpu MHz\t\t: %lu.%02lu\n"
 582                       "bogomips\t: %lu.%02lu\n",
 583                       num_online_cpus(),
 584                       cpumask_pr_args(cpu_online_mask),
 585                       XCHAL_BUILD_UNIQUE_ID,
 586                       XCHAL_HAVE_BE ?  "big" : "little",
 587                       ccount_freq/1000000,
 588                       (ccount_freq/10000) % 100,
 589                       loops_per_jiffy/(500000/HZ),
 590                       (loops_per_jiffy/(5000/HZ)) % 100);
 591
 592         seq_printf(f,"flags\t\t: "
 593 #if XCHAL_HAVE_NMI
 594                      "nmi "
 595 #endif
 596 #if XCHAL_HAVE_DEBUG
 597                      "debug "
 598 # if XCHAL_HAVE_OCD
 599                      "ocd "
 600 # endif
 601 #endif
 602 #if XCHAL_HAVE_DENSITY
 603                      "density "
 604 #endif
 605 #if XCHAL_HAVE_BOOLEANS
 606                      "boolean "
 607 #endif
 608 #if XCHAL_HAVE_LOOPS
 609                      "loop "
 610 #endif
 611 #if XCHAL_HAVE_NSA
 612                      "nsa "
 613 #endif
 614 #if XCHAL_HAVE_MINMAX
 615                      "minmax "
 616 #endif
 617 #if XCHAL_HAVE_SEXT
 618                      "sext "
 619 #endif
 620 #if XCHAL_HAVE_CLAMPS
 621                      "clamps "
 622 #endif
 623 #if XCHAL_HAVE_MAC16
 624                      "mac16 "
 625 #endif
 626 #if XCHAL_HAVE_MUL16
 627                      "mul16 "
 628 #endif
 629 #if XCHAL_HAVE_MUL32
 630                      "mul32 "
 631 #endif
 632 #if XCHAL_HAVE_MUL32_HIGH
 633                      "mul32h "
 634 #endif
 635 #if XCHAL_HAVE_FP
 636                      "fpu "
 637 #endif
 638 #if XCHAL_HAVE_S32C1I
 639                      "s32c1i "
 640 #endif
 641                      "\n");
 642
 643         /* Registers. */
 644         seq_printf(f,"physical aregs\t: %d\n"
 645                      "misc regs\t: %d\n"
 646                      "ibreak\t\t: %d\n"
 647                      "dbreak\t\t: %d\n",
 648                      XCHAL_NUM_AREGS,
 649                      XCHAL_NUM_MISC_REGS,
 650                      XCHAL_NUM_IBREAK,
 651                      XCHAL_NUM_DBREAK);
 652
 653
 654         /* Interrupt. */
 655         seq_printf(f,"num ints\t: %d\n"
 656                      "ext ints\t: %d\n"
 657                      "int levels\t: %d\n"
 658                      "timers\t\t: %d\n"
 659                      "debug level\t: %d\n",
 660                      XCHAL_NUM_INTERRUPTS,
 661                      XCHAL_NUM_EXTINTERRUPTS,
 662                      XCHAL_NUM_INTLEVELS,
 663                      XCHAL_NUM_TIMERS,
 664                      XCHAL_DEBUGLEVEL);
 665
 666         /* Cache */
 667         seq_printf(f,"icache line size: %d\n"
 668                      "icache ways\t: %d\n"
 669                      "icache size\t: %d\n"
 670                      "icache flags\t: "
 671 #if XCHAL_ICACHE_LINE_LOCKABLE
 672                      "lock "
 673 #endif
 674                      "\n"
 675                      "dcache line size: %d\n"
 676                      "dcache ways\t: %d\n"
 677                      "dcache size\t: %d\n"
 678                      "dcache flags\t: "
 679 #if XCHAL_DCACHE_IS_WRITEBACK
 680                      "writeback "
 681 #endif
 682 #if XCHAL_DCACHE_LINE_LOCKABLE
 683                      "lock "
 684 #endif
 685                      "\n",
 686                      XCHAL_ICACHE_LINESIZE,
 687                      XCHAL_ICACHE_WAYS,
 688                      XCHAL_ICACHE_SIZE,
 689                      XCHAL_DCACHE_LINESIZE,
 690                      XCHAL_DCACHE_WAYS,
 691                      XCHAL_DCACHE_SIZE);
 692
 693         return 0;
 694 }
 695
 696 /*
 697  * We show only CPU #0 info.
 698  */
 699 static void *
 700 c_start(struct seq_file *f, loff_t *pos)
 701 {
 702         return (*pos == 0) ? (void *)1 : NULL;
 703 }
 704
 705 static void *
 706 c_next(struct seq_file *f, void *v, loff_t *pos)
 707 {
 708         return NULL;
 709 }
 710
 711 static void
 712 c_stop(struct seq_file *f, void *v)
 713 {
 714 }
 715
 716 const struct seq_operations cpuinfo_op =
 717 {
 718         .start  = c_start,
 719         .next   = c_next,
 720         .stop   = c_stop,
 721         .show   = c_show,
 722 };
 723
 724 #endif /* CONFIG_PROC_FS */