drivers/ata/ahci_imx.c

   1 /*
   2  * copyright (c) 2013 Freescale Semiconductor, Inc.
   3  * Freescale IMX AHCI SATA platform driver
   4  *
   5  * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program. If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include <linux/kernel.h>
  21 #include <linux/module.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/regmap.h>
  24 #include <linux/ahci_platform.h>
  25 #include <linux/of_device.h>
  26 #include <linux/mfd/syscon.h>
  27 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
  28 #include <linux/libata.h>
  29 #include "ahci.h"
  30
  31 enum {
  32         /* Timer 1-ms Register */
  33         IMX_TIMER1MS                            = 0x00e0,
  34         /* Port0 PHY Control Register */
  35         IMX_P0PHYCR                             = 0x0178,
  36         IMX_P0PHYCR_TEST_PDDQ                   = 1 << 20,
  37         IMX_P0PHYCR_CR_READ                     = 1 << 19,
  38         IMX_P0PHYCR_CR_WRITE                    = 1 << 18,
  39         IMX_P0PHYCR_CR_CAP_DATA                 = 1 << 17,
  40         IMX_P0PHYCR_CR_CAP_ADDR                 = 1 << 16,
  41         /* Port0 PHY Status Register */
  42         IMX_P0PHYSR                             = 0x017c,
  43         IMX_P0PHYSR_CR_ACK                      = 1 << 18,
  44         IMX_P0PHYSR_CR_DATA_OUT                 = 0xffff << 0,
  45         /* Lane0 Output Status Register */
  46         IMX_LANE0_OUT_STAT                      = 0x2003,
  47         IMX_LANE0_OUT_STAT_RX_PLL_STATE         = 1 << 1,
  48         /* Clock Reset Register */
  49         IMX_CLOCK_RESET                         = 0x7f3f,
  50         IMX_CLOCK_RESET_RESET                   = 1 << 0,
  51 };
  52
  53 enum ahci_imx_type {
  54         AHCI_IMX53,
  55         AHCI_IMX6Q,
  56 };
  57
  58 struct imx_ahci_priv {
  59         struct platform_device *ahci_pdev;
  60         enum ahci_imx_type type;
  61         struct clk *sata_clk;
  62         struct clk *sata_ref_clk;
  63         struct clk *ahb_clk;
  64         struct regmap *gpr;
  65         bool no_device;
  66         bool first_time;
  67         u32 phy_params;
  68 };
  69
  70 static int ahci_imx_hotplug;
  71 module_param_named(hotplug, ahci_imx_hotplug, int, 0644);
  72 MODULE_PARM_DESC(hotplug, "AHCI IMX hot-plug support (0=Don't support, 1=support)");
  73
  74 static void ahci_imx_host_stop(struct ata_host *host);
  75
  76 static int imx_phy_crbit_assert(void __iomem *mmio, u32 bit, bool assert)
  77 {
  78         int timeout = 10;
  79         u32 crval;
  80         u32 srval;
  81
  82         /* Assert or deassert the bit */
  83         crval = readl(mmio + IMX_P0PHYCR);
  84         if (assert)
  85                 crval |= bit;
  86         else
  87                 crval &= ~bit;
  88         writel(crval, mmio + IMX_P0PHYCR);
  89
  90         /* Wait for the cr_ack signal */
  91         do {
  92                 srval = readl(mmio + IMX_P0PHYSR);
  93                 if ((assert ? srval : ~srval) & IMX_P0PHYSR_CR_ACK)
  94                         break;
  95                 usleep_range(100, 200);
  96         } while (--timeout);
  97
  98         return timeout ? 0 : -ETIMEDOUT;
  99 }
 100
 101 static int imx_phy_reg_addressing(u16 addr, void __iomem *mmio)
 102 {
 103         u32 crval = addr;
 104         int ret;
 105
 106         /* Supply the address on cr_data_in */
 107         writel(crval, mmio + IMX_P0PHYCR);
 108
 109         /* Assert the cr_cap_addr signal */
 110         ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, true);
 111         if (ret)
 112                 return ret;
 113
 114         /* Deassert cr_cap_addr */
 115         ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, false);
 116         if (ret)
 117                 return ret;
 118
 119         return 0;
 120 }
 121
 122 static int imx_phy_reg_write(u16 val, void __iomem *mmio)
 123 {
 124         u32 crval = val;
 125         int ret;
 126
 127         /* Supply the data on cr_data_in */
 128         writel(crval, mmio + IMX_P0PHYCR);
 129
 130         /* Assert the cr_cap_data signal */
 131         ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, true);
 132         if (ret)
 133                 return ret;
 134
 135         /* Deassert cr_cap_data */
 136         ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, false);
 137         if (ret)
 138                 return ret;
 139
 140         if (val & IMX_CLOCK_RESET_RESET) {
 141                 /*
 142                  * In case we're resetting the phy, it's unable to acknowledge,
 143                  * so we return immediately here.
 144                  */
 145                 crval |= IMX_P0PHYCR_CR_WRITE;
 146                 writel(crval, mmio + IMX_P0PHYCR);
 147                 goto out;
 148         }
 149
 150         /* Assert the cr_write signal */
 151         ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, true);
 152         if (ret)
 153                 return ret;
 154
 155         /* Deassert cr_write */
 156         ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, false);
 157         if (ret)
 158                 return ret;
 159
 160 out:
 161         return 0;
 162 }
 163
 164 static int imx_phy_reg_read(u16 *val, void __iomem *mmio)
 165 {
 166         int ret;
 167
 168         /* Assert the cr_read signal */
 169         ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, true);
 170         if (ret)
 171                 return ret;
 172
 173         /* Capture the data from cr_data_out[] */
 174         *val = readl(mmio + IMX_P0PHYSR) & IMX_P0PHYSR_CR_DATA_OUT;
 175
 176         /* Deassert cr_read */
 177         ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, false);
 178         if (ret)
 179                 return ret;
 180
 181         return 0;
 182 }
 183
 184 static int imx_sata_phy_reset(struct ahci_host_priv *hpriv)
 185 {
 186         void __iomem *mmio = hpriv->mmio;
 187         int timeout = 10;
 188         u16 val;
 189         int ret;
 190
 191         /* Reset SATA PHY by setting RESET bit of PHY register CLOCK_RESET */
 192         ret = imx_phy_reg_addressing(IMX_CLOCK_RESET, mmio);
 193         if (ret)
 194                 return ret;
 195         ret = imx_phy_reg_write(IMX_CLOCK_RESET_RESET, mmio);
 196         if (ret)
 197                 return ret;
 198
 199         /* Wait for PHY RX_PLL to be stable */
 200         do {
 201                 usleep_range(100, 200);
 202                 ret = imx_phy_reg_addressing(IMX_LANE0_OUT_STAT, mmio);
 203                 if (ret)
 204                         return ret;
 205                 ret = imx_phy_reg_read(&val, mmio);
 206                 if (ret)
 207                         return ret;
 208                 if (val & IMX_LANE0_OUT_STAT_RX_PLL_STATE)
 209                         break;
 210         } while (--timeout);
 211
 212         return timeout ? 0 : -ETIMEDOUT;
 213 }
 214
 215 static int imx_sata_enable(struct ahci_host_priv *hpriv)
 216 {
 217         struct imx_ahci_priv *imxpriv = hpriv->plat_data;
 218         struct device *dev = &imxpriv->ahci_pdev->dev;
 219         int ret;
 220
 221         if (imxpriv->no_device)
 222                 return 0;
 223
 224         if (hpriv->target_pwr) {
 225                 ret = regulator_enable(hpriv->target_pwr);
 226                 if (ret)
 227                         return ret;
 228         }
 229
 230         ret = clk_prepare_enable(imxpriv->sata_ref_clk);
 231         if (ret < 0)
 232                 goto disable_regulator;
 233
 234         if (imxpriv->type == AHCI_IMX6Q) {
 235                 /*
 236                  * set PHY Paremeters, two steps to configure the GPR13,
 237                  * one write for rest of parameters, mask of first write
 238                  * is 0x07ffffff, and the other one write for setting
 239                  * the mpll_clk_en.
 240                  */
 241                 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
 242                                    IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK |
 243                                    IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK |
 244                                    IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK |
 245                                    IMX6Q_GPR13_SATA_SPD_MODE_MASK |
 246                                    IMX6Q_GPR13_SATA_MPLL_SS_EN |
 247                                    IMX6Q_GPR13_SATA_TX_ATTEN_MASK |
 248                                    IMX6Q_GPR13_SATA_TX_BOOST_MASK |
 249                                    IMX6Q_GPR13_SATA_TX_LVL_MASK |
 250                                    IMX6Q_GPR13_SATA_MPLL_CLK_EN |
 251                                    IMX6Q_GPR13_SATA_TX_EDGE_RATE,
 252                                    imxpriv->phy_params);
 253                 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
 254                                    IMX6Q_GPR13_SATA_MPLL_CLK_EN,
 255                                    IMX6Q_GPR13_SATA_MPLL_CLK_EN);
 256
 257                 usleep_range(100, 200);
 258
 259                 ret = imx_sata_phy_reset(hpriv);
 260                 if (ret) {
 261                         dev_err(dev, "failed to reset phy: %d\n", ret);
 262                         goto disable_clk;
 263                 }
 264         }
 265
 266         usleep_range(1000, 2000);
 267
 268         return 0;
 269
 270 disable_clk:
 271         clk_disable_unprepare(imxpriv->sata_ref_clk);
 272 disable_regulator:
 273         if (hpriv->target_pwr)
 274                 regulator_disable(hpriv->target_pwr);
 275
 276         return ret;
 277 }
 278
 279 static void imx_sata_disable(struct ahci_host_priv *hpriv)
 280 {
 281         struct imx_ahci_priv *imxpriv = hpriv->plat_data;
 282
 283         if (imxpriv->no_device)
 284                 return;
 285
 286         if (imxpriv->type == AHCI_IMX6Q) {
 287                 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
 288                                    IMX6Q_GPR13_SATA_MPLL_CLK_EN,
 289                                    !IMX6Q_GPR13_SATA_MPLL_CLK_EN);
 290         }
 291
 292         clk_disable_unprepare(imxpriv->sata_ref_clk);
 293
 294         if (hpriv->target_pwr)
 295                 regulator_disable(hpriv->target_pwr);
 296 }
 297
 298 static void ahci_imx_error_handler(struct ata_port *ap)
 299 {
 300         u32 reg_val;
 301         struct ata_device *dev;
 302         struct ata_host *host = dev_get_drvdata(ap->dev);
 303         struct ahci_host_priv *hpriv = host->private_data;
 304         void __iomem *mmio = hpriv->mmio;
 305         struct imx_ahci_priv *imxpriv = hpriv->plat_data;
 306
 307         ahci_error_handler(ap);
 308
 309         if (!(imxpriv->first_time) || ahci_imx_hotplug)
 310                 return;
 311
 312         imxpriv->first_time = false;
 313
 314         ata_for_each_dev(dev, &ap->link, ENABLED)
 315                 return;
 316         /*
 317          * Disable link to save power.  An imx ahci port can't be recovered
 318          * without full reset once the pddq mode is enabled making it
 319          * impossible to use as part of libata LPM.
 320          */
 321         reg_val = readl(mmio + IMX_P0PHYCR);
 322         writel(reg_val | IMX_P0PHYCR_TEST_PDDQ, mmio + IMX_P0PHYCR);
 323         imx_sata_disable(hpriv);
 324         imxpriv->no_device = true;
 325
 326         dev_info(ap->dev, "no device found, disabling link.\n");
 327         dev_info(ap->dev, "pass " MODULE_PARAM_PREFIX ".hotplug=1 to enable hotplug\n");
 328 }
 329
 330 static int ahci_imx_softreset(struct ata_link *link, unsigned int *class,
 331                        unsigned long deadline)
 332 {
 333         struct ata_port *ap = link->ap;
 334         struct ata_host *host = dev_get_drvdata(ap->dev);
 335         struct ahci_host_priv *hpriv = host->private_data;
 336         struct imx_ahci_priv *imxpriv = hpriv->plat_data;
 337         int ret = -EIO;
 338
 339         if (imxpriv->type == AHCI_IMX53)
 340                 ret = ahci_pmp_retry_srst_ops.softreset(link, class, deadline);
 341         else if (imxpriv->type == AHCI_IMX6Q)
 342                 ret = ahci_ops.softreset(link, class, deadline);
 343
 344         return ret;
 345 }
 346
 347 static struct ata_port_operations ahci_imx_ops = {
 348         .inherits       = &ahci_ops,
 349         .host_stop      = ahci_imx_host_stop,
 350         .error_handler  = ahci_imx_error_handler,
 351         .softreset      = ahci_imx_softreset,
 352 };
 353
 354 static const struct ata_port_info ahci_imx_port_info = {
 355         .flags          = AHCI_FLAG_COMMON,
 356         .pio_mask       = ATA_PIO4,
 357         .udma_mask      = ATA_UDMA6,
 358         .port_ops       = &ahci_imx_ops,
 359 };
 360
 361 static const struct of_device_id imx_ahci_of_match[] = {
 362         { .compatible = "fsl,imx53-ahci", .data = (void *)AHCI_IMX53 },
 363         { .compatible = "fsl,imx6q-ahci", .data = (void *)AHCI_IMX6Q },
 364         {},
 365 };
 366 MODULE_DEVICE_TABLE(of, imx_ahci_of_match);
 367
 368 struct reg_value {
 369         u32 of_value;
 370         u32 reg_value;
 371 };
 372
 373 struct reg_property {
 374         const char *name;
 375         const struct reg_value *values;
 376         size_t num_values;
 377         u32 def_value;
 378         u32 set_value;
 379 };
 380
 381 static const struct reg_value gpr13_tx_level[] = {
 382         {  937, IMX6Q_GPR13_SATA_TX_LVL_0_937_V },
 383         {  947, IMX6Q_GPR13_SATA_TX_LVL_0_947_V },
 384         {  957, IMX6Q_GPR13_SATA_TX_LVL_0_957_V },
 385         {  966, IMX6Q_GPR13_SATA_TX_LVL_0_966_V },
 386         {  976, IMX6Q_GPR13_SATA_TX_LVL_0_976_V },
 387         {  986, IMX6Q_GPR13_SATA_TX_LVL_0_986_V },
 388         {  996, IMX6Q_GPR13_SATA_TX_LVL_0_996_V },
 389         { 1005, IMX6Q_GPR13_SATA_TX_LVL_1_005_V },
 390         { 1015, IMX6Q_GPR13_SATA_TX_LVL_1_015_V },
 391         { 1025, IMX6Q_GPR13_SATA_TX_LVL_1_025_V },
 392         { 1035, IMX6Q_GPR13_SATA_TX_LVL_1_035_V },
 393         { 1045, IMX6Q_GPR13_SATA_TX_LVL_1_045_V },
 394         { 1054, IMX6Q_GPR13_SATA_TX_LVL_1_054_V },
 395         { 1064, IMX6Q_GPR13_SATA_TX_LVL_1_064_V },
 396         { 1074, IMX6Q_GPR13_SATA_TX_LVL_1_074_V },
 397         { 1084, IMX6Q_GPR13_SATA_TX_LVL_1_084_V },
 398         { 1094, IMX6Q_GPR13_SATA_TX_LVL_1_094_V },
 399         { 1104, IMX6Q_GPR13_SATA_TX_LVL_1_104_V },
 400         { 1113, IMX6Q_GPR13_SATA_TX_LVL_1_113_V },
 401         { 1123, IMX6Q_GPR13_SATA_TX_LVL_1_123_V },
 402         { 1133, IMX6Q_GPR13_SATA_TX_LVL_1_133_V },
 403         { 1143, IMX6Q_GPR13_SATA_TX_LVL_1_143_V },
 404         { 1152, IMX6Q_GPR13_SATA_TX_LVL_1_152_V },
 405         { 1162, IMX6Q_GPR13_SATA_TX_LVL_1_162_V },
 406         { 1172, IMX6Q_GPR13_SATA_TX_LVL_1_172_V },
 407         { 1182, IMX6Q_GPR13_SATA_TX_LVL_1_182_V },
 408         { 1191, IMX6Q_GPR13_SATA_TX_LVL_1_191_V },
 409         { 1201, IMX6Q_GPR13_SATA_TX_LVL_1_201_V },
 410         { 1211, IMX6Q_GPR13_SATA_TX_LVL_1_211_V },
 411         { 1221, IMX6Q_GPR13_SATA_TX_LVL_1_221_V },
 412         { 1230, IMX6Q_GPR13_SATA_TX_LVL_1_230_V },
 413         { 1240, IMX6Q_GPR13_SATA_TX_LVL_1_240_V }
 414 };
 415
 416 static const struct reg_value gpr13_tx_boost[] = {
 417         {    0, IMX6Q_GPR13_SATA_TX_BOOST_0_00_DB },
 418         {  370, IMX6Q_GPR13_SATA_TX_BOOST_0_37_DB },
 419         {  740, IMX6Q_GPR13_SATA_TX_BOOST_0_74_DB },
 420         { 1110, IMX6Q_GPR13_SATA_TX_BOOST_1_11_DB },
 421         { 1480, IMX6Q_GPR13_SATA_TX_BOOST_1_48_DB },
 422         { 1850, IMX6Q_GPR13_SATA_TX_BOOST_1_85_DB },
 423         { 2220, IMX6Q_GPR13_SATA_TX_BOOST_2_22_DB },
 424         { 2590, IMX6Q_GPR13_SATA_TX_BOOST_2_59_DB },
 425         { 2960, IMX6Q_GPR13_SATA_TX_BOOST_2_96_DB },
 426         { 3330, IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB },
 427         { 3700, IMX6Q_GPR13_SATA_TX_BOOST_3_70_DB },
 428         { 4070, IMX6Q_GPR13_SATA_TX_BOOST_4_07_DB },
 429         { 4440, IMX6Q_GPR13_SATA_TX_BOOST_4_44_DB },
 430         { 4810, IMX6Q_GPR13_SATA_TX_BOOST_4_81_DB },
 431         { 5280, IMX6Q_GPR13_SATA_TX_BOOST_5_28_DB },
 432         { 5750, IMX6Q_GPR13_SATA_TX_BOOST_5_75_DB }
 433 };
 434
 435 static const struct reg_value gpr13_tx_atten[] = {
 436         {  8, IMX6Q_GPR13_SATA_TX_ATTEN_8_16 },
 437         {  9, IMX6Q_GPR13_SATA_TX_ATTEN_9_16 },
 438         { 10, IMX6Q_GPR13_SATA_TX_ATTEN_10_16 },
 439         { 12, IMX6Q_GPR13_SATA_TX_ATTEN_12_16 },
 440         { 14, IMX6Q_GPR13_SATA_TX_ATTEN_14_16 },
 441         { 16, IMX6Q_GPR13_SATA_TX_ATTEN_16_16 },
 442 };
 443
 444 static const struct reg_value gpr13_rx_eq[] = {
 445         {  500, IMX6Q_GPR13_SATA_RX_EQ_VAL_0_5_DB },
 446         { 1000, IMX6Q_GPR13_SATA_RX_EQ_VAL_1_0_DB },
 447         { 1500, IMX6Q_GPR13_SATA_RX_EQ_VAL_1_5_DB },
 448         { 2000, IMX6Q_GPR13_SATA_RX_EQ_VAL_2_0_DB },
 449         { 2500, IMX6Q_GPR13_SATA_RX_EQ_VAL_2_5_DB },
 450         { 3000, IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB },
 451         { 3500, IMX6Q_GPR13_SATA_RX_EQ_VAL_3_5_DB },
 452         { 4000, IMX6Q_GPR13_SATA_RX_EQ_VAL_4_0_DB },
 453 };
 454
 455 static const struct reg_property gpr13_props[] = {
 456         {
 457                 .name = "fsl,transmit-level-mV",
 458                 .values = gpr13_tx_level,
 459                 .num_values = ARRAY_SIZE(gpr13_tx_level),
 460                 .def_value = IMX6Q_GPR13_SATA_TX_LVL_1_025_V,
 461         }, {
 462                 .name = "fsl,transmit-boost-mdB",
 463                 .values = gpr13_tx_boost,
 464                 .num_values = ARRAY_SIZE(gpr13_tx_boost),
 465                 .def_value = IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB,
 466         }, {
 467                 .name = "fsl,transmit-atten-16ths",
 468                 .values = gpr13_tx_atten,
 469                 .num_values = ARRAY_SIZE(gpr13_tx_atten),
 470                 .def_value = IMX6Q_GPR13_SATA_TX_ATTEN_9_16,
 471         }, {
 472                 .name = "fsl,receive-eq-mdB",
 473                 .values = gpr13_rx_eq,
 474                 .num_values = ARRAY_SIZE(gpr13_rx_eq),
 475                 .def_value = IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB,
 476         }, {
 477                 .name = "fsl,no-spread-spectrum",
 478                 .def_value = IMX6Q_GPR13_SATA_MPLL_SS_EN,
 479                 .set_value = 0,
 480         },
 481 };
 482
 483 static u32 imx_ahci_parse_props(struct device *dev,
 484                                 const struct reg_property *prop, size_t num)
 485 {
 486         struct device_node *np = dev->of_node;
 487         u32 reg_value = 0;
 488         int i, j;
 489
 490         for (i = 0; i < num; i++, prop++) {
 491                 u32 of_val;
 492
 493                 if (prop->num_values == 0) {
 494                         if (of_property_read_bool(np, prop->name))
 495                                 reg_value |= prop->set_value;
 496                         else
 497                                 reg_value |= prop->def_value;
 498                         continue;
 499                 }
 500
 501                 if (of_property_read_u32(np, prop->name, &of_val)) {
 502                         dev_info(dev, "%s not specified, using %08x\n",
 503                                 prop->name, prop->def_value);
 504                         reg_value |= prop->def_value;
 505                         continue;
 506                 }
 507
 508                 for (j = 0; j < prop->num_values; j++) {
 509                         if (prop->values[j].of_value == of_val) {
 510                                 dev_info(dev, "%s value %u, using %08x\n",
 511                                         prop->name, of_val, prop->values[j].reg_value);
 512                                 reg_value |= prop->values[j].reg_value;
 513                                 break;
 514                         }
 515                 }
 516
 517                 if (j == prop->num_values) {
 518                         dev_err(dev, "DT property %s is not a valid value\n",
 519                                 prop->name);
 520                         reg_value |= prop->def_value;
 521                 }
 522         }
 523
 524         return reg_value;
 525 }
 526
 527 static int imx_ahci_probe(struct platform_device *pdev)
 528 {
 529         struct device *dev = &pdev->dev;
 530         const struct of_device_id *of_id;
 531         struct ahci_host_priv *hpriv;
 532         struct imx_ahci_priv *imxpriv;
 533         unsigned int reg_val;
 534         int ret;
 535
 536         of_id = of_match_device(imx_ahci_of_match, dev);
 537         if (!of_id)
 538                 return -EINVAL;
 539
 540         imxpriv = devm_kzalloc(dev, sizeof(*imxpriv), GFP_KERNEL);
 541         if (!imxpriv)
 542                 return -ENOMEM;
 543
 544         imxpriv->ahci_pdev = pdev;
 545         imxpriv->no_device = false;
 546         imxpriv->first_time = true;
 547         imxpriv->type = (enum ahci_imx_type)of_id->data;
 548
 549         imxpriv->sata_clk = devm_clk_get(dev, "sata");
 550         if (IS_ERR(imxpriv->sata_clk)) {
 551                 dev_err(dev, "can't get sata clock.\n");
 552                 return PTR_ERR(imxpriv->sata_clk);
 553         }
 554
 555         imxpriv->sata_ref_clk = devm_clk_get(dev, "sata_ref");
 556         if (IS_ERR(imxpriv->sata_ref_clk)) {
 557                 dev_err(dev, "can't get sata_ref clock.\n");
 558                 return PTR_ERR(imxpriv->sata_ref_clk);
 559         }
 560
 561         imxpriv->ahb_clk = devm_clk_get(dev, "ahb");
 562         if (IS_ERR(imxpriv->ahb_clk)) {
 563                 dev_err(dev, "can't get ahb clock.\n");
 564                 return PTR_ERR(imxpriv->ahb_clk);
 565         }
 566
 567         if (imxpriv->type == AHCI_IMX6Q) {
 568                 u32 reg_value;
 569
 570                 imxpriv->gpr = syscon_regmap_lookup_by_compatible(
 571                                                         "fsl,imx6q-iomuxc-gpr");
 572                 if (IS_ERR(imxpriv->gpr)) {
 573                         dev_err(dev,
 574                                 "failed to find fsl,imx6q-iomux-gpr regmap\n");
 575                         return PTR_ERR(imxpriv->gpr);
 576                 }
 577
 578                 reg_value = imx_ahci_parse_props(dev, gpr13_props,
 579                                                  ARRAY_SIZE(gpr13_props));
 580
 581                 imxpriv->phy_params =
 582                                    IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M |
 583                                    IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F |
 584                                    IMX6Q_GPR13_SATA_SPD_MODE_3P0G |
 585                                    reg_value;
 586         }
 587
 588         hpriv = ahci_platform_get_resources(pdev);
 589         if (IS_ERR(hpriv))
 590                 return PTR_ERR(hpriv);
 591
 592         hpriv->plat_data = imxpriv;
 593
 594         ret = clk_prepare_enable(imxpriv->sata_clk);
 595         if (ret)
 596                 return ret;
 597
 598         ret = imx_sata_enable(hpriv);
 599         if (ret)
 600                 goto disable_clk;
 601
 602         /*
 603          * Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL,
 604          * and IP vendor specific register IMX_TIMER1MS.
 605          * Configure CAP_SSS (support stagered spin up).
 606          * Implement the port0.
 607          * Get the ahb clock rate, and configure the TIMER1MS register.
 608          */
 609         reg_val = readl(hpriv->mmio + HOST_CAP);
 610         if (!(reg_val & HOST_CAP_SSS)) {
 611                 reg_val |= HOST_CAP_SSS;
 612                 writel(reg_val, hpriv->mmio + HOST_CAP);
 613         }
 614         reg_val = readl(hpriv->mmio + HOST_PORTS_IMPL);
 615         if (!(reg_val & 0x1)) {
 616                 reg_val |= 0x1;
 617                 writel(reg_val, hpriv->mmio + HOST_PORTS_IMPL);
 618         }
 619
 620         reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000;
 621         writel(reg_val, hpriv->mmio + IMX_TIMER1MS);
 622
 623         ret = ahci_platform_init_host(pdev, hpriv, &ahci_imx_port_info);
 624         if (ret)
 625                 goto disable_sata;
 626
 627         return 0;
 628
 629 disable_sata:
 630         imx_sata_disable(hpriv);
 631 disable_clk:
 632         clk_disable_unprepare(imxpriv->sata_clk);
 633         return ret;
 634 }
 635
 636 static void ahci_imx_host_stop(struct ata_host *host)
 637 {
 638         struct ahci_host_priv *hpriv = host->private_data;
 639         struct imx_ahci_priv *imxpriv = hpriv->plat_data;
 640
 641         imx_sata_disable(hpriv);
 642         clk_disable_unprepare(imxpriv->sata_clk);
 643 }
 644
 645 #ifdef CONFIG_PM_SLEEP
 646 static int imx_ahci_suspend(struct device *dev)
 647 {
 648         struct ata_host *host = dev_get_drvdata(dev);
 649         struct ahci_host_priv *hpriv = host->private_data;
 650         int ret;
 651
 652         ret = ahci_platform_suspend_host(dev);
 653         if (ret)
 654                 return ret;
 655
 656         imx_sata_disable(hpriv);
 657
 658         return 0;
 659 }
 660
 661 static int imx_ahci_resume(struct device *dev)
 662 {
 663         struct ata_host *host = dev_get_drvdata(dev);
 664         struct ahci_host_priv *hpriv = host->private_data;
 665         int ret;
 666
 667         ret = imx_sata_enable(hpriv);
 668         if (ret)
 669                 return ret;
 670
 671         return ahci_platform_resume_host(dev);
 672 }
 673 #endif
 674
 675 static SIMPLE_DEV_PM_OPS(ahci_imx_pm_ops, imx_ahci_suspend, imx_ahci_resume);
 676
 677 static struct platform_driver imx_ahci_driver = {
 678         .probe = imx_ahci_probe,
 679         .remove = ata_platform_remove_one,
 680         .driver = {
 681                 .name = "ahci-imx",
 682                 .of_match_table = imx_ahci_of_match,
 683                 .pm = &ahci_imx_pm_ops,
 684         },
 685 };
 686 module_platform_driver(imx_ahci_driver);
 687
 688 MODULE_DESCRIPTION("Freescale i.MX AHCI SATA platform driver");
 689 MODULE_AUTHOR("Richard Zhu <Hong-Xing.Zhu@freescale.com>");
 690 MODULE_LICENSE("GPL");
 691 MODULE_ALIAS("ahci:imx");