drivers/block/nvme.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  */
  18
  19 #include <linux/nvme.h>
  20 #include <linux/bio.h>
  21 #include <linux/bitops.h>
  22 #include <linux/blkdev.h>
  23 #include <linux/delay.h>
  24 #include <linux/errno.h>
  25 #include <linux/fs.h>
  26 #include <linux/genhd.h>
  27 #include <linux/idr.h>
  28 #include <linux/init.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/io.h>
  31 #include <linux/kdev_t.h>
  32 #include <linux/kthread.h>
  33 #include <linux/kernel.h>
  34 #include <linux/mm.h>
  35 #include <linux/module.h>
  36 #include <linux/moduleparam.h>
  37 #include <linux/pci.h>
  38 #include <linux/poison.h>
  39 #include <linux/sched.h>
  40 #include <linux/slab.h>
  41 #include <linux/types.h>
  42 #include <linux/version.h>
  43
  44 #define NVME_Q_DEPTH 1024
  45 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  46 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  47 #define NVME_MINORS 64
  48 #define IO_TIMEOUT      (5 * HZ)
  49 #define ADMIN_TIMEOUT   (60 * HZ)
  50
  51 static int nvme_major;
  52 module_param(nvme_major, int, 0);
  53
  54 static int use_threaded_interrupts;
  55 module_param(use_threaded_interrupts, int, 0);
  56
  57 static DEFINE_SPINLOCK(dev_list_lock);
  58 static LIST_HEAD(dev_list);
  59 static struct task_struct *nvme_thread;
  60
  61 /*
  62  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
  63  */
  64 struct nvme_dev {
  65         struct list_head node;
  66         struct nvme_queue **queues;
  67         u32 __iomem *dbs;
  68         struct pci_dev *pci_dev;
  69         struct dma_pool *prp_page_pool;
  70         struct dma_pool *prp_small_pool;
  71         int instance;
  72         int queue_count;
  73         u32 ctrl_config;
  74         struct msix_entry *entry;
  75         struct nvme_bar __iomem *bar;
  76         struct list_head namespaces;
  77         char serial[20];
  78         char model[40];
  79         char firmware_rev[8];
  80 };
  81
  82 /*
  83  * An NVM Express namespace is equivalent to a SCSI LUN
  84  */
  85 struct nvme_ns {
  86         struct list_head list;
  87
  88         struct nvme_dev *dev;
  89         struct request_queue *queue;
  90         struct gendisk *disk;
  91
  92         int ns_id;
  93         int lba_shift;
  94 };
  95
  96 /*
  97  * An NVM Express queue.  Each device has at least two (one for admin
  98  * commands and one for I/O commands).
  99  */
 100 struct nvme_queue {
 101         struct device *q_dmadev;
 102         struct nvme_dev *dev;
 103         spinlock_t q_lock;
 104         struct nvme_command *sq_cmds;
 105         volatile struct nvme_completion *cqes;
 106         dma_addr_t sq_dma_addr;
 107         dma_addr_t cq_dma_addr;
 108         wait_queue_head_t sq_full;
 109         wait_queue_t sq_cong_wait;
 110         struct bio_list sq_cong;
 111         u32 __iomem *q_db;
 112         u16 q_depth;
 113         u16 cq_vector;
 114         u16 sq_head;
 115         u16 sq_tail;
 116         u16 cq_head;
 117         u16 cq_phase;
 118         unsigned long cmdid_data[];
 119 };
 120
 121 /*
 122  * Check we didin't inadvertently grow the command struct
 123  */
 124 static inline void _nvme_check_size(void)
 125 {
 126         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 127         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 128         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 129         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 130         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 131         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 132         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
 133         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
 134         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 135 }
 136
 137 struct nvme_cmd_info {
 138         unsigned long ctx;
 139         unsigned long timeout;
 140 };
 141
 142 static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
 143 {
 144         return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
 145 }
 146
 147 /**
 148  * alloc_cmdid() - Allocate a Command ID
 149  * @nvmeq: The queue that will be used for this command
 150  * @ctx: A pointer that will be passed to the handler
 151  * @handler: The ID of the handler to call
 152  *
 153  * Allocate a Command ID for a queue.  The data passed in will
 154  * be passed to the completion handler.  This is implemented by using
 155  * the bottom two bits of the ctx pointer to store the handler ID.
 156  * Passing in a pointer that's not 4-byte aligned will cause a BUG.
 157  * We can change this if it becomes a problem.
 158  *
 159  * May be called with local interrupts disabled and the q_lock held,
 160  * or with interrupts enabled and no locks held.
 161  */
 162 static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx, int handler,
 163                                                         unsigned timeout)
 164 {
 165         int depth = nvmeq->q_depth - 1;
 166         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 167         int cmdid;
 168
 169         BUG_ON((unsigned long)ctx & 3);
 170
 171         do {
 172                 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
 173                 if (cmdid >= depth)
 174                         return -EBUSY;
 175         } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
 176
 177         info[cmdid].ctx = (unsigned long)ctx | handler;
 178         info[cmdid].timeout = jiffies + timeout;
 179         return cmdid;
 180 }
 181
 182 static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
 183                                                 int handler, unsigned timeout)
 184 {
 185         int cmdid;
 186         wait_event_killable(nvmeq->sq_full,
 187                 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
 188         return (cmdid < 0) ? -EINTR : cmdid;
 189 }
 190
 191 /*
 192  * If you need more than four handlers, you'll need to change how
 193  * alloc_cmdid and nvme_process_cq work.  Consider using a special
 194  * CMD_CTX value instead, if that works for your situation.
 195  */
 196 enum {
 197         sync_completion_id = 0,
 198         bio_completion_id,
 199 };
 200
 201 /* Special values must be a multiple of 4, and less than 0x1000 */
 202 #define CMD_CTX_BASE            (POISON_POINTER_DELTA + sync_completion_id)
 203 #define CMD_CTX_CANCELLED       (0x30C + CMD_CTX_BASE)
 204 #define CMD_CTX_COMPLETED       (0x310 + CMD_CTX_BASE)
 205 #define CMD_CTX_INVALID         (0x314 + CMD_CTX_BASE)
 206 #define CMD_CTX_FLUSH           (0x318 + CMD_CTX_BASE)
 207
 208 /*
 209  * Called with local interrupts disabled and the q_lock held.  May not sleep.
 210  */
 211 static unsigned long free_cmdid(struct nvme_queue *nvmeq, int cmdid)
 212 {
 213         unsigned long data;
 214         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 215
 216         if (cmdid >= nvmeq->q_depth)
 217                 return CMD_CTX_INVALID;
 218         data = info[cmdid].ctx;
 219         info[cmdid].ctx = CMD_CTX_COMPLETED;
 220         clear_bit(cmdid, nvmeq->cmdid_data);
 221         wake_up(&nvmeq->sq_full);
 222         return data;
 223 }
 224
 225 static unsigned long cancel_cmdid(struct nvme_queue *nvmeq, int cmdid)
 226 {
 227         unsigned long data;
 228         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
 229         data = info[cmdid].ctx;
 230         info[cmdid].ctx = CMD_CTX_CANCELLED;
 231         return data;
 232 }
 233
 234 static struct nvme_queue *get_nvmeq(struct nvme_ns *ns)
 235 {
 236         return ns->dev->queues[get_cpu() + 1];
 237 }
 238
 239 static void put_nvmeq(struct nvme_queue *nvmeq)
 240 {
 241         put_cpu();
 242 }
 243
 244 /**
 245  * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
 246  * @nvmeq: The queue to use
 247  * @cmd: The command to send
 248  *
 249  * Safe to use from interrupt context
 250  */
 251 static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
 252 {
 253         unsigned long flags;
 254         u16 tail;
 255         spin_lock_irqsave(&nvmeq->q_lock, flags);
 256         tail = nvmeq->sq_tail;
 257         memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 258         if (++tail == nvmeq->q_depth)
 259                 tail = 0;
 260         writel(tail, nvmeq->q_db);
 261         nvmeq->sq_tail = tail;
 262         spin_unlock_irqrestore(&nvmeq->q_lock, flags);
 263
 264         return 0;
 265 }
 266
 267 struct nvme_prps {
 268         int npages;
 269         dma_addr_t first_dma;
 270         __le64 *list[0];
 271 };
 272
 273 static void nvme_free_prps(struct nvme_dev *dev, struct nvme_prps *prps)
 274 {
 275         const int last_prp = PAGE_SIZE / 8 - 1;
 276         int i;
 277         dma_addr_t prp_dma;
 278
 279         if (!prps)
 280                 return;
 281
 282         prp_dma = prps->first_dma;
 283
 284         if (prps->npages == 0)
 285                 dma_pool_free(dev->prp_small_pool, prps->list[0], prp_dma);
 286         for (i = 0; i < prps->npages; i++) {
 287                 __le64 *prp_list = prps->list[i];
 288                 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
 289                 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
 290                 prp_dma = next_prp_dma;
 291         }
 292         kfree(prps);
 293 }
 294
 295 struct nvme_bio {
 296         struct bio *bio;
 297         int nents;
 298         struct nvme_prps *prps;
 299         struct scatterlist sg[0];
 300 };
 301
 302 /* XXX: use a mempool */
 303 static struct nvme_bio *alloc_nbio(unsigned nseg, gfp_t gfp)
 304 {
 305         return kzalloc(sizeof(struct nvme_bio) +
 306                         sizeof(struct scatterlist) * nseg, gfp);
 307 }
 308
 309 static void free_nbio(struct nvme_queue *nvmeq, struct nvme_bio *nbio)
 310 {
 311         nvme_free_prps(nvmeq->dev, nbio->prps);
 312         kfree(nbio);
 313 }
 314
 315 static void bio_completion(struct nvme_queue *nvmeq, void *ctx,
 316                                                 struct nvme_completion *cqe)
 317 {
 318         struct nvme_bio *nbio = ctx;
 319         struct bio *bio = nbio->bio;
 320         u16 status = le16_to_cpup(&cqe->status) >> 1;
 321
 322         dma_unmap_sg(nvmeq->q_dmadev, nbio->sg, nbio->nents,
 323                         bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 324         free_nbio(nvmeq, nbio);
 325         if (status) {
 326                 bio_endio(bio, -EIO);
 327         } else if (bio->bi_vcnt > bio->bi_idx) {
 328                 bio_list_add(&nvmeq->sq_cong, bio);
 329                 wake_up_process(nvme_thread);
 330         } else {
 331                 bio_endio(bio, 0);
 332         }
 333 }
 334
 335 /* length is in bytes.  gfp flags indicates whether we may sleep. */
 336 static struct nvme_prps *nvme_setup_prps(struct nvme_dev *dev,
 337                                         struct nvme_common_command *cmd,
 338                                         struct scatterlist *sg, int *len,
 339                                         gfp_t gfp)
 340 {
 341         struct dma_pool *pool;
 342         int length = *len;
 343         int dma_len = sg_dma_len(sg);
 344         u64 dma_addr = sg_dma_address(sg);
 345         int offset = offset_in_page(dma_addr);
 346         __le64 *prp_list;
 347         dma_addr_t prp_dma;
 348         int nprps, npages, i, prp_page;
 349         struct nvme_prps *prps = NULL;
 350
 351         cmd->prp1 = cpu_to_le64(dma_addr);
 352         length -= (PAGE_SIZE - offset);
 353         if (length <= 0)
 354                 return prps;
 355
 356         dma_len -= (PAGE_SIZE - offset);
 357         if (dma_len) {
 358                 dma_addr += (PAGE_SIZE - offset);
 359         } else {
 360                 sg = sg_next(sg);
 361                 dma_addr = sg_dma_address(sg);
 362                 dma_len = sg_dma_len(sg);
 363         }
 364
 365         if (length <= PAGE_SIZE) {
 366                 cmd->prp2 = cpu_to_le64(dma_addr);
 367                 return prps;
 368         }
 369
 370         nprps = DIV_ROUND_UP(length, PAGE_SIZE);
 371         npages = DIV_ROUND_UP(8 * nprps, PAGE_SIZE);
 372         prps = kmalloc(sizeof(*prps) + sizeof(__le64 *) * npages, gfp);
 373         if (!prps) {
 374                 cmd->prp2 = cpu_to_le64(dma_addr);
 375                 *len = (*len - length) + PAGE_SIZE;
 376                 return prps;
 377         }
 378         prp_page = 0;
 379         if (nprps <= (256 / 8)) {
 380                 pool = dev->prp_small_pool;
 381                 prps->npages = 0;
 382         } else {
 383                 pool = dev->prp_page_pool;
 384                 prps->npages = npages;
 385         }
 386
 387         prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
 388         if (!prp_list) {
 389                 cmd->prp2 = cpu_to_le64(dma_addr);
 390                 *len = (*len - length) + PAGE_SIZE;
 391                 kfree(prps);
 392                 return NULL;
 393         }
 394         prps->list[prp_page++] = prp_list;
 395         prps->first_dma = prp_dma;
 396         cmd->prp2 = cpu_to_le64(prp_dma);
 397         i = 0;
 398         for (;;) {
 399                 if (i == PAGE_SIZE / 8) {
 400                         __le64 *old_prp_list = prp_list;
 401                         prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
 402                         if (!prp_list) {
 403                                 *len = (*len - length);
 404                                 return prps;
 405                         }
 406                         prps->list[prp_page++] = prp_list;
 407                         prp_list[0] = old_prp_list[i - 1];
 408                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 409                         i = 1;
 410                 }
 411                 prp_list[i++] = cpu_to_le64(dma_addr);
 412                 dma_len -= PAGE_SIZE;
 413                 dma_addr += PAGE_SIZE;
 414                 length -= PAGE_SIZE;
 415                 if (length <= 0)
 416                         break;
 417                 if (dma_len > 0)
 418                         continue;
 419                 BUG_ON(dma_len < 0);
 420                 sg = sg_next(sg);
 421                 dma_addr = sg_dma_address(sg);
 422                 dma_len = sg_dma_len(sg);
 423         }
 424
 425         return prps;
 426 }
 427
 428 /* NVMe scatterlists require no holes in the virtual address */
 429 #define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2)   ((vec2)->bv_offset || \
 430                         (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE))
 431
 432 static int nvme_map_bio(struct device *dev, struct nvme_bio *nbio,
 433                 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
 434 {
 435         struct bio_vec *bvec, *bvprv = NULL;
 436         struct scatterlist *sg = NULL;
 437         int i, old_idx, length = 0, nsegs = 0;
 438
 439         sg_init_table(nbio->sg, psegs);
 440         old_idx = bio->bi_idx;
 441         bio_for_each_segment(bvec, bio, i) {
 442                 if (bvprv && BIOVEC_PHYS_MERGEABLE(bvprv, bvec)) {
 443                         sg->length += bvec->bv_len;
 444                 } else {
 445                         if (bvprv && BIOVEC_NOT_VIRT_MERGEABLE(bvprv, bvec))
 446                                 break;
 447                         sg = sg ? sg + 1 : nbio->sg;
 448                         sg_set_page(sg, bvec->bv_page, bvec->bv_len,
 449                                                         bvec->bv_offset);
 450                         nsegs++;
 451                 }
 452                 length += bvec->bv_len;
 453                 bvprv = bvec;
 454         }
 455         bio->bi_idx = i;
 456         nbio->nents = nsegs;
 457         sg_mark_end(sg);
 458         if (dma_map_sg(dev, nbio->sg, nbio->nents, dma_dir) == 0) {
 459                 bio->bi_idx = old_idx;
 460                 return -ENOMEM;
 461         }
 462         return length;
 463 }
 464
 465 static int nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
 466                                                                 int cmdid)
 467 {
 468         struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
 469
 470         memset(cmnd, 0, sizeof(*cmnd));
 471         cmnd->common.opcode = nvme_cmd_flush;
 472         cmnd->common.command_id = cmdid;
 473         cmnd->common.nsid = cpu_to_le32(ns->ns_id);
 474
 475         if (++nvmeq->sq_tail == nvmeq->q_depth)
 476                 nvmeq->sq_tail = 0;
 477         writel(nvmeq->sq_tail, nvmeq->q_db);
 478
 479         return 0;
 480 }
 481
 482 static int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns)
 483 {
 484         int cmdid = alloc_cmdid(nvmeq, (void *)CMD_CTX_FLUSH,
 485                                                 sync_completion_id, IO_TIMEOUT);
 486         if (unlikely(cmdid < 0))
 487                 return cmdid;
 488
 489         return nvme_submit_flush(nvmeq, ns, cmdid);
 490 }
 491
 492 /*
 493  * Called with local interrupts disabled and the q_lock held.  May not sleep.
 494  */
 495 static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
 496                                                                 struct bio *bio)
 497 {
 498         struct nvme_command *cmnd;
 499         struct nvme_bio *nbio;
 500         enum dma_data_direction dma_dir;
 501         int cmdid, length, result = -ENOMEM;
 502         u16 control;
 503         u32 dsmgmt;
 504         int psegs = bio_phys_segments(ns->queue, bio);
 505
 506         if ((bio->bi_rw & REQ_FLUSH) && psegs) {
 507                 result = nvme_submit_flush_data(nvmeq, ns);
 508                 if (result)
 509                         return result;
 510         }
 511
 512         nbio = alloc_nbio(psegs, GFP_ATOMIC);
 513         if (!nbio)
 514                 goto nomem;
 515         nbio->bio = bio;
 516
 517         result = -EBUSY;
 518         cmdid = alloc_cmdid(nvmeq, nbio, bio_completion_id, IO_TIMEOUT);
 519         if (unlikely(cmdid < 0))
 520                 goto free_nbio;
 521
 522         if ((bio->bi_rw & REQ_FLUSH) && !psegs)
 523                 return nvme_submit_flush(nvmeq, ns, cmdid);
 524
 525         control = 0;
 526         if (bio->bi_rw & REQ_FUA)
 527                 control |= NVME_RW_FUA;
 528         if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
 529                 control |= NVME_RW_LR;
 530
 531         dsmgmt = 0;
 532         if (bio->bi_rw & REQ_RAHEAD)
 533                 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
 534
 535         cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
 536
 537         memset(cmnd, 0, sizeof(*cmnd));
 538         if (bio_data_dir(bio)) {
 539                 cmnd->rw.opcode = nvme_cmd_write;
 540                 dma_dir = DMA_TO_DEVICE;
 541         } else {
 542                 cmnd->rw.opcode = nvme_cmd_read;
 543                 dma_dir = DMA_FROM_DEVICE;
 544         }
 545
 546         result = nvme_map_bio(nvmeq->q_dmadev, nbio, bio, dma_dir, psegs);
 547         if (result < 0)
 548                 goto free_nbio;
 549         length = result;
 550
 551         cmnd->rw.command_id = cmdid;
 552         cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
 553         nbio->prps = nvme_setup_prps(nvmeq->dev, &cmnd->common, nbio->sg,
 554                                                         &length, GFP_ATOMIC);
 555         cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9));
 556         cmnd->rw.length = cpu_to_le16((length >> ns->lba_shift) - 1);
 557         cmnd->rw.control = cpu_to_le16(control);
 558         cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
 559
 560         bio->bi_sector += length >> 9;
 561
 562         if (++nvmeq->sq_tail == nvmeq->q_depth)
 563                 nvmeq->sq_tail = 0;
 564         writel(nvmeq->sq_tail, nvmeq->q_db);
 565
 566         return 0;
 567
 568  free_nbio:
 569         free_nbio(nvmeq, nbio);
 570  nomem:
 571         return result;
 572 }
 573
 574 /*
 575  * NB: return value of non-zero would mean that we were a stacking driver.
 576  * make_request must always succeed.
 577  */
 578 static int nvme_make_request(struct request_queue *q, struct bio *bio)
 579 {
 580         struct nvme_ns *ns = q->queuedata;
 581         struct nvme_queue *nvmeq = get_nvmeq(ns);
 582         int result = -EBUSY;
 583
 584         spin_lock_irq(&nvmeq->q_lock);
 585         if (bio_list_empty(&nvmeq->sq_cong))
 586                 result = nvme_submit_bio_queue(nvmeq, ns, bio);
 587         if (unlikely(result)) {
 588                 if (bio_list_empty(&nvmeq->sq_cong))
 589                         add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
 590                 bio_list_add(&nvmeq->sq_cong, bio);
 591         }
 592
 593         spin_unlock_irq(&nvmeq->q_lock);
 594         put_nvmeq(nvmeq);
 595
 596         return 0;
 597 }
 598
 599 struct sync_cmd_info {
 600         struct task_struct *task;
 601         u32 result;
 602         int status;
 603 };
 604
 605 static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
 606                                                 struct nvme_completion *cqe)
 607 {
 608         struct sync_cmd_info *cmdinfo = ctx;
 609         if (unlikely((unsigned long)cmdinfo == CMD_CTX_CANCELLED))
 610                 return;
 611         if ((unsigned long)cmdinfo == CMD_CTX_FLUSH)
 612                 return;
 613         if (unlikely((unsigned long)cmdinfo == CMD_CTX_COMPLETED)) {
 614                 dev_warn(nvmeq->q_dmadev,
 615                                 "completed id %d twice on queue %d\n",
 616                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
 617                 return;
 618         }
 619         if (unlikely((unsigned long)cmdinfo == CMD_CTX_INVALID)) {
 620                 dev_warn(nvmeq->q_dmadev,
 621                                 "invalid id %d completed on queue %d\n",
 622                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
 623                 return;
 624         }
 625         cmdinfo->result = le32_to_cpup(&cqe->result);
 626         cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
 627         wake_up_process(cmdinfo->task);
 628 }
 629
 630 typedef void (*completion_fn)(struct nvme_queue *, void *,
 631                                                 struct nvme_completion *);
 632
 633 static const completion_fn nvme_completions[4] = {
 634         [sync_completion_id] = sync_completion,
 635         [bio_completion_id]  = bio_completion,
 636 };
 637
 638 static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq)
 639 {
 640         u16 head, phase;
 641
 642         head = nvmeq->cq_head;
 643         phase = nvmeq->cq_phase;
 644
 645         for (;;) {
 646                 unsigned long data;
 647                 void *ptr;
 648                 unsigned char handler;
 649                 struct nvme_completion cqe = nvmeq->cqes[head];
 650                 if ((le16_to_cpu(cqe.status) & 1) != phase)
 651                         break;
 652                 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
 653                 if (++head == nvmeq->q_depth) {
 654                         head = 0;
 655                         phase = !phase;
 656                 }
 657
 658                 data = free_cmdid(nvmeq, cqe.command_id);
 659                 handler = data & 3;
 660                 ptr = (void *)(data & ~3UL);
 661                 nvme_completions[handler](nvmeq, ptr, &cqe);
 662         }
 663
 664         /* If the controller ignores the cq head doorbell and continuously
 665          * writes to the queue, it is theoretically possible to wrap around
 666          * the queue twice and mistakenly return IRQ_NONE.  Linux only
 667          * requires that 0.1% of your interrupts are handled, so this isn't
 668          * a big problem.
 669          */
 670         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
 671                 return IRQ_NONE;
 672
 673         writel(head, nvmeq->q_db + 1);
 674         nvmeq->cq_head = head;
 675         nvmeq->cq_phase = phase;
 676
 677         return IRQ_HANDLED;
 678 }
 679
 680 static irqreturn_t nvme_irq(int irq, void *data)
 681 {
 682         irqreturn_t result;
 683         struct nvme_queue *nvmeq = data;
 684         spin_lock(&nvmeq->q_lock);
 685         result = nvme_process_cq(nvmeq);
 686         spin_unlock(&nvmeq->q_lock);
 687         return result;
 688 }
 689
 690 static irqreturn_t nvme_irq_check(int irq, void *data)
 691 {
 692         struct nvme_queue *nvmeq = data;
 693         struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
 694         if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
 695                 return IRQ_NONE;
 696         return IRQ_WAKE_THREAD;
 697 }
 698
 699 static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
 700 {
 701         spin_lock_irq(&nvmeq->q_lock);
 702         cancel_cmdid(nvmeq, cmdid);
 703         spin_unlock_irq(&nvmeq->q_lock);
 704 }
 705
 706 /*
 707  * Returns 0 on success.  If the result is negative, it's a Linux error code;
 708  * if the result is positive, it's an NVM Express status code
 709  */
 710 static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq,
 711                         struct nvme_command *cmd, u32 *result, unsigned timeout)
 712 {
 713         int cmdid;
 714         struct sync_cmd_info cmdinfo;
 715
 716         cmdinfo.task = current;
 717         cmdinfo.status = -EINTR;
 718
 719         cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion_id,
 720                                                                 timeout);
 721         if (cmdid < 0)
 722                 return cmdid;
 723         cmd->common.command_id = cmdid;
 724
 725         set_current_state(TASK_KILLABLE);
 726         nvme_submit_cmd(nvmeq, cmd);
 727         schedule();
 728
 729         if (cmdinfo.status == -EINTR) {
 730                 nvme_abort_command(nvmeq, cmdid);
 731                 return -EINTR;
 732         }
 733
 734         if (result)
 735                 *result = cmdinfo.result;
 736
 737         return cmdinfo.status;
 738 }
 739
 740 static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
 741                                                                 u32 *result)
 742 {
 743         return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT);
 744 }
 745
 746 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
 747 {
 748         int status;
 749         struct nvme_command c;
 750
 751         memset(&c, 0, sizeof(c));
 752         c.delete_queue.opcode = opcode;
 753         c.delete_queue.qid = cpu_to_le16(id);
 754
 755         status = nvme_submit_admin_cmd(dev, &c, NULL);
 756         if (status)
 757                 return -EIO;
 758         return 0;
 759 }
 760
 761 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
 762                                                 struct nvme_queue *nvmeq)
 763 {
 764         int status;
 765         struct nvme_command c;
 766         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
 767
 768         memset(&c, 0, sizeof(c));
 769         c.create_cq.opcode = nvme_admin_create_cq;
 770         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
 771         c.create_cq.cqid = cpu_to_le16(qid);
 772         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 773         c.create_cq.cq_flags = cpu_to_le16(flags);
 774         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
 775
 776         status = nvme_submit_admin_cmd(dev, &c, NULL);
 777         if (status)
 778                 return -EIO;
 779         return 0;
 780 }
 781
 782 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
 783                                                 struct nvme_queue *nvmeq)
 784 {
 785         int status;
 786         struct nvme_command c;
 787         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
 788
 789         memset(&c, 0, sizeof(c));
 790         c.create_sq.opcode = nvme_admin_create_sq;
 791         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
 792         c.create_sq.sqid = cpu_to_le16(qid);
 793         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 794         c.create_sq.sq_flags = cpu_to_le16(flags);
 795         c.create_sq.cqid = cpu_to_le16(qid);
 796
 797         status = nvme_submit_admin_cmd(dev, &c, NULL);
 798         if (status)
 799                 return -EIO;
 800         return 0;
 801 }
 802
 803 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
 804 {
 805         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
 806 }
 807
 808 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
 809 {
 810         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
 811 }
 812
 813 static void nvme_free_queue(struct nvme_dev *dev, int qid)
 814 {
 815         struct nvme_queue *nvmeq = dev->queues[qid];
 816         int vector = dev->entry[nvmeq->cq_vector].vector;
 817
 818         irq_set_affinity_hint(vector, NULL);
 819         free_irq(vector, nvmeq);
 820
 821         /* Don't tell the adapter to delete the admin queue */
 822         if (qid) {
 823                 adapter_delete_sq(dev, qid);
 824                 adapter_delete_cq(dev, qid);
 825         }
 826
 827         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 828                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 829         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 830                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 831         kfree(nvmeq);
 832 }
 833
 834 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
 835                                                         int depth, int vector)
 836 {
 837         struct device *dmadev = &dev->pci_dev->dev;
 838         unsigned extra = (depth / 8) + (depth * sizeof(struct nvme_cmd_info));
 839         struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
 840         if (!nvmeq)
 841                 return NULL;
 842
 843         nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
 844                                         &nvmeq->cq_dma_addr, GFP_KERNEL);
 845         if (!nvmeq->cqes)
 846                 goto free_nvmeq;
 847         memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
 848
 849         nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
 850                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
 851         if (!nvmeq->sq_cmds)
 852                 goto free_cqdma;
 853
 854         nvmeq->q_dmadev = dmadev;
 855         nvmeq->dev = dev;
 856         spin_lock_init(&nvmeq->q_lock);
 857         nvmeq->cq_head = 0;
 858         nvmeq->cq_phase = 1;
 859         init_waitqueue_head(&nvmeq->sq_full);
 860         init_waitqueue_entry(&nvmeq->sq_cong_wait, nvme_thread);
 861         bio_list_init(&nvmeq->sq_cong);
 862         nvmeq->q_db = &dev->dbs[qid * 2];
 863         nvmeq->q_depth = depth;
 864         nvmeq->cq_vector = vector;
 865
 866         return nvmeq;
 867
 868  free_cqdma:
 869         dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes,
 870                                                         nvmeq->cq_dma_addr);
 871  free_nvmeq:
 872         kfree(nvmeq);
 873         return NULL;
 874 }
 875
 876 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
 877                                                         const char *name)
 878 {
 879         if (use_threaded_interrupts)
 880                 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
 881                                         nvme_irq_check, nvme_irq,
 882                                         IRQF_DISABLED | IRQF_SHARED,
 883                                         name, nvmeq);
 884         return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
 885                                 IRQF_DISABLED | IRQF_SHARED, name, nvmeq);
 886 }
 887
 888 static __devinit struct nvme_queue *nvme_create_queue(struct nvme_dev *dev,
 889                                         int qid, int cq_size, int vector)
 890 {
 891         int result;
 892         struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector);
 893
 894         if (!nvmeq)
 895                 return NULL;
 896
 897         result = adapter_alloc_cq(dev, qid, nvmeq);
 898         if (result < 0)
 899                 goto free_nvmeq;
 900
 901         result = adapter_alloc_sq(dev, qid, nvmeq);
 902         if (result < 0)
 903                 goto release_cq;
 904
 905         result = queue_request_irq(dev, nvmeq, "nvme");
 906         if (result < 0)
 907                 goto release_sq;
 908
 909         return nvmeq;
 910
 911  release_sq:
 912         adapter_delete_sq(dev, qid);
 913  release_cq:
 914         adapter_delete_cq(dev, qid);
 915  free_nvmeq:
 916         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 917                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 918         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 919                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 920         kfree(nvmeq);
 921         return NULL;
 922 }
 923
 924 static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev)
 925 {
 926         int result;
 927         u32 aqa;
 928         u64 cap;
 929         unsigned long timeout;
 930         struct nvme_queue *nvmeq;
 931
 932         dev->dbs = ((void __iomem *)dev->bar) + 4096;
 933
 934         nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
 935         if (!nvmeq)
 936                 return -ENOMEM;
 937
 938         aqa = nvmeq->q_depth - 1;
 939         aqa |= aqa << 16;
 940
 941         dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
 942         dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
 943         dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
 944         dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
 945
 946         writel(0, &dev->bar->cc);
 947         writel(aqa, &dev->bar->aqa);
 948         writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
 949         writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
 950         writel(dev->ctrl_config, &dev->bar->cc);
 951
 952         cap = readq(&dev->bar->cap);
 953         timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
 954
 955         while (!(readl(&dev->bar->csts) & NVME_CSTS_RDY)) {
 956                 msleep(100);
 957                 if (fatal_signal_pending(current))
 958                         return -EINTR;
 959                 if (time_after(jiffies, timeout)) {
 960                         dev_err(&dev->pci_dev->dev,
 961                                 "Device not ready; aborting initialisation\n");
 962                         return -ENODEV;
 963                 }
 964         }
 965
 966         result = queue_request_irq(dev, nvmeq, "nvme admin");
 967         dev->queues[0] = nvmeq;
 968         return result;
 969 }
 970
 971 static int nvme_map_user_pages(struct nvme_dev *dev, int write,
 972                                 unsigned long addr, unsigned length,
 973                                 struct scatterlist **sgp)
 974 {
 975         int i, err, count, nents, offset;
 976         struct scatterlist *sg;
 977         struct page **pages;
 978
 979         if (addr & 3)
 980                 return -EINVAL;
 981         if (!length)
 982                 return -EINVAL;
 983
 984         offset = offset_in_page(addr);
 985         count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
 986         pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
 987
 988         err = get_user_pages_fast(addr, count, 1, pages);
 989         if (err < count) {
 990                 count = err;
 991                 err = -EFAULT;
 992                 goto put_pages;
 993         }
 994
 995         sg = kcalloc(count, sizeof(*sg), GFP_KERNEL);
 996         sg_init_table(sg, count);
 997         sg_set_page(&sg[0], pages[0], PAGE_SIZE - offset, offset);
 998         length -= (PAGE_SIZE - offset);
 999         for (i = 1; i < count; i++) {
1000                 sg_set_page(&sg[i], pages[i], min_t(int, length, PAGE_SIZE), 0);
1001                 length -= PAGE_SIZE;
1002         }
1003
1004         err = -ENOMEM;
1005         nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
1006                                 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1007         if (!nents)
1008                 goto put_pages;
1009
1010         kfree(pages);
1011         *sgp = sg;
1012         return nents;
1013
1014  put_pages:
1015         for (i = 0; i < count; i++)
1016                 put_page(pages[i]);
1017         kfree(pages);
1018         return err;
1019 }
1020
1021 static void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
1022                                 unsigned long addr, int length,
1023                                 struct scatterlist *sg, int nents)
1024 {
1025         int i, count;
1026
1027         count = DIV_ROUND_UP(offset_in_page(addr) + length, PAGE_SIZE);
1028         dma_unmap_sg(&dev->pci_dev->dev, sg, nents, DMA_FROM_DEVICE);
1029
1030         for (i = 0; i < count; i++)
1031                 put_page(sg_page(&sg[i]));
1032 }
1033
1034 static int nvme_submit_user_admin_command(struct nvme_dev *dev,
1035                                         unsigned long addr, unsigned length,
1036                                         struct nvme_command *cmd)
1037 {
1038         int err, nents, tmplen = length;
1039         struct scatterlist *sg;
1040         struct nvme_prps *prps;
1041
1042         nents = nvme_map_user_pages(dev, 0, addr, length, &sg);
1043         if (nents < 0)
1044                 return nents;
1045         prps = nvme_setup_prps(dev, &cmd->common, sg, &tmplen, GFP_KERNEL);
1046         if (tmplen != length)
1047                 err = -ENOMEM;
1048         else
1049                 err = nvme_submit_admin_cmd(dev, cmd, NULL);
1050         nvme_unmap_user_pages(dev, 0, addr, length, sg, nents);
1051         nvme_free_prps(dev, prps);
1052         return err ? -EIO : 0;
1053 }
1054
1055 static int nvme_identify(struct nvme_ns *ns, unsigned long addr, int cns)
1056 {
1057         struct nvme_command c;
1058
1059         memset(&c, 0, sizeof(c));
1060         c.identify.opcode = nvme_admin_identify;
1061         c.identify.nsid = cns ? 0 : cpu_to_le32(ns->ns_id);
1062         c.identify.cns = cpu_to_le32(cns);
1063
1064         return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
1065 }
1066
1067 static int nvme_get_range_type(struct nvme_ns *ns, unsigned long addr)
1068 {
1069         struct nvme_command c;
1070
1071         memset(&c, 0, sizeof(c));
1072         c.features.opcode = nvme_admin_get_features;
1073         c.features.nsid = cpu_to_le32(ns->ns_id);
1074         c.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
1075
1076         return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c);
1077 }
1078
1079 static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1080 {
1081         struct nvme_dev *dev = ns->dev;
1082         struct nvme_queue *nvmeq;
1083         struct nvme_user_io io;
1084         struct nvme_command c;
1085         unsigned length;
1086         int nents, status;
1087         struct scatterlist *sg;
1088         struct nvme_prps *prps;
1089
1090         if (copy_from_user(&io, uio, sizeof(io)))
1091                 return -EFAULT;
1092         length = (io.nblocks + 1) << ns->lba_shift;
1093
1094         switch (io.opcode) {
1095         case nvme_cmd_write:
1096         case nvme_cmd_read:
1097                 nents = nvme_map_user_pages(dev, io.opcode & 1, io.addr,
1098                                                                 length, &sg);
1099         default:
1100                 return -EFAULT;
1101         }
1102
1103         if (nents < 0)
1104                 return nents;
1105
1106         memset(&c, 0, sizeof(c));
1107         c.rw.opcode = io.opcode;
1108         c.rw.flags = io.flags;
1109         c.rw.nsid = cpu_to_le32(ns->ns_id);
1110         c.rw.slba = cpu_to_le64(io.slba);
1111         c.rw.length = cpu_to_le16(io.nblocks);
1112         c.rw.control = cpu_to_le16(io.control);
1113         c.rw.dsmgmt = cpu_to_le16(io.dsmgmt);
1114         c.rw.reftag = io.reftag;
1115         c.rw.apptag = io.apptag;
1116         c.rw.appmask = io.appmask;
1117         /* XXX: metadata */
1118         prps = nvme_setup_prps(dev, &c.common, sg, &length, GFP_KERNEL);
1119
1120         nvmeq = get_nvmeq(ns);
1121         /*
1122          * Since nvme_submit_sync_cmd sleeps, we can't keep preemption
1123          * disabled.  We may be preempted at any point, and be rescheduled
1124          * to a different CPU.  That will cause cacheline bouncing, but no
1125          * additional races since q_lock already protects against other CPUs.
1126          */
1127         put_nvmeq(nvmeq);
1128         if (length != (io.nblocks + 1) << ns->lba_shift)
1129                 status = -ENOMEM;
1130         else
1131                 status = nvme_submit_sync_cmd(nvmeq, &c, NULL, IO_TIMEOUT);
1132
1133         nvme_unmap_user_pages(dev, io.opcode & 1, io.addr, length, sg, nents);
1134         nvme_free_prps(dev, prps);
1135         return status;
1136 }
1137
1138 static int nvme_download_firmware(struct nvme_ns *ns,
1139                                                 struct nvme_dlfw __user *udlfw)
1140 {
1141         struct nvme_dev *dev = ns->dev;
1142         struct nvme_dlfw dlfw;
1143         struct nvme_command c;
1144         int nents, status, length;
1145         struct scatterlist *sg;
1146         struct nvme_prps *prps;
1147
1148         if (copy_from_user(&dlfw, udlfw, sizeof(dlfw)))
1149                 return -EFAULT;
1150         if (dlfw.length >= (1 << 30))
1151                 return -EINVAL;
1152         length = dlfw.length * 4;
1153
1154         nents = nvme_map_user_pages(dev, 1, dlfw.addr, length, &sg);
1155         if (nents < 0)
1156                 return nents;
1157
1158         memset(&c, 0, sizeof(c));
1159         c.dlfw.opcode = nvme_admin_download_fw;
1160         c.dlfw.numd = cpu_to_le32(dlfw.length);
1161         c.dlfw.offset = cpu_to_le32(dlfw.offset);
1162         prps = nvme_setup_prps(dev, &c.common, sg, &length, GFP_KERNEL);
1163         if (length != dlfw.length * 4)
1164                 status = -ENOMEM;
1165         else
1166                 status = nvme_submit_admin_cmd(dev, &c, NULL);
1167         nvme_unmap_user_pages(dev, 0, dlfw.addr, dlfw.length * 4, sg, nents);
1168         nvme_free_prps(dev, prps);
1169         return status;
1170 }
1171
1172 static int nvme_activate_firmware(struct nvme_ns *ns, unsigned long arg)
1173 {
1174         struct nvme_dev *dev = ns->dev;
1175         struct nvme_command c;
1176
1177         memset(&c, 0, sizeof(c));
1178         c.common.opcode = nvme_admin_activate_fw;
1179         c.common.rsvd10[0] = cpu_to_le32(arg);
1180
1181         return nvme_submit_admin_cmd(dev, &c, NULL);
1182 }
1183
1184 static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1185                                                         unsigned long arg)
1186 {
1187         struct nvme_ns *ns = bdev->bd_disk->private_data;
1188
1189         switch (cmd) {
1190         case NVME_IOCTL_IDENTIFY_NS:
1191                 return nvme_identify(ns, arg, 0);
1192         case NVME_IOCTL_IDENTIFY_CTRL:
1193                 return nvme_identify(ns, arg, 1);
1194         case NVME_IOCTL_GET_RANGE_TYPE:
1195                 return nvme_get_range_type(ns, arg);
1196         case NVME_IOCTL_SUBMIT_IO:
1197                 return nvme_submit_io(ns, (void __user *)arg);
1198         case NVME_IOCTL_DOWNLOAD_FW:
1199                 return nvme_download_firmware(ns, (void __user *)arg);
1200         case NVME_IOCTL_ACTIVATE_FW:
1201                 return nvme_activate_firmware(ns, arg);
1202         default:
1203                 return -ENOTTY;
1204         }
1205 }
1206
1207 static const struct block_device_operations nvme_fops = {
1208         .owner          = THIS_MODULE,
1209         .ioctl          = nvme_ioctl,
1210         .compat_ioctl   = nvme_ioctl,
1211 };
1212
1213 static void nvme_timeout_ios(struct nvme_queue *nvmeq)
1214 {
1215         int depth = nvmeq->q_depth - 1;
1216         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
1217         unsigned long now = jiffies;
1218         int cmdid;
1219
1220         for_each_set_bit(cmdid, nvmeq->cmdid_data, depth) {
1221                 unsigned long data;
1222                 void *ptr;
1223                 unsigned char handler;
1224                 static struct nvme_completion cqe = { .status = cpu_to_le16(NVME_SC_ABORT_REQ) << 1, };
1225
1226                 if (!time_after(now, info[cmdid].timeout))
1227                         continue;
1228                 dev_warn(nvmeq->q_dmadev, "Timing out I/O %d\n", cmdid);
1229                 data = cancel_cmdid(nvmeq, cmdid);
1230                 handler = data & 3;
1231                 ptr = (void *)(data & ~3UL);
1232                 nvme_completions[handler](nvmeq, ptr, &cqe);
1233         }
1234 }
1235
1236 static void nvme_resubmit_bios(struct nvme_queue *nvmeq)
1237 {
1238         while (bio_list_peek(&nvmeq->sq_cong)) {
1239                 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1240                 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
1241                 if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
1242                         bio_list_add_head(&nvmeq->sq_cong, bio);
1243                         break;
1244                 }
1245                 if (bio_list_empty(&nvmeq->sq_cong))
1246                         remove_wait_queue(&nvmeq->sq_full,
1247                                                         &nvmeq->sq_cong_wait);
1248         }
1249 }
1250
1251 static int nvme_kthread(void *data)
1252 {
1253         struct nvme_dev *dev;
1254
1255         while (!kthread_should_stop()) {
1256                 __set_current_state(TASK_RUNNING);
1257                 spin_lock(&dev_list_lock);
1258                 list_for_each_entry(dev, &dev_list, node) {
1259                         int i;
1260                         for (i = 0; i < dev->queue_count; i++) {
1261                                 struct nvme_queue *nvmeq = dev->queues[i];
1262                                 if (!nvmeq)
1263                                         continue;
1264                                 spin_lock_irq(&nvmeq->q_lock);
1265                                 if (nvme_process_cq(nvmeq))
1266                                         printk("process_cq did something\n");
1267                                 nvme_timeout_ios(nvmeq);
1268                                 nvme_resubmit_bios(nvmeq);
1269                                 spin_unlock_irq(&nvmeq->q_lock);
1270                         }
1271                 }
1272                 spin_unlock(&dev_list_lock);
1273                 set_current_state(TASK_INTERRUPTIBLE);
1274                 schedule_timeout(HZ);
1275         }
1276         return 0;
1277 }
1278
1279 static DEFINE_IDA(nvme_index_ida);
1280
1281 static int nvme_get_ns_idx(void)
1282 {
1283         int index, error;
1284
1285         do {
1286                 if (!ida_pre_get(&nvme_index_ida, GFP_KERNEL))
1287                         return -1;
1288
1289                 spin_lock(&dev_list_lock);
1290                 error = ida_get_new(&nvme_index_ida, &index);
1291                 spin_unlock(&dev_list_lock);
1292         } while (error == -EAGAIN);
1293
1294         if (error)
1295                 index = -1;
1296         return index;
1297 }
1298
1299 static void nvme_put_ns_idx(int index)
1300 {
1301         spin_lock(&dev_list_lock);
1302         ida_remove(&nvme_index_ida, index);
1303         spin_unlock(&dev_list_lock);
1304 }
1305
1306 static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int nsid,
1307                         struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1308 {
1309         struct nvme_ns *ns;
1310         struct gendisk *disk;
1311         int lbaf;
1312
1313         if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1314                 return NULL;
1315
1316         ns = kzalloc(sizeof(*ns), GFP_KERNEL);
1317         if (!ns)
1318                 return NULL;
1319         ns->queue = blk_alloc_queue(GFP_KERNEL);
1320         if (!ns->queue)
1321                 goto out_free_ns;
1322         ns->queue->queue_flags = QUEUE_FLAG_DEFAULT | QUEUE_FLAG_NOMERGES |
1323                                 QUEUE_FLAG_NONROT | QUEUE_FLAG_DISCARD;
1324         blk_queue_make_request(ns->queue, nvme_make_request);
1325         ns->dev = dev;
1326         ns->queue->queuedata = ns;
1327
1328         disk = alloc_disk(NVME_MINORS);
1329         if (!disk)
1330                 goto out_free_queue;
1331         ns->ns_id = nsid;
1332         ns->disk = disk;
1333         lbaf = id->flbas & 0xf;
1334         ns->lba_shift = id->lbaf[lbaf].ds;
1335
1336         disk->major = nvme_major;
1337         disk->minors = NVME_MINORS;
1338         disk->first_minor = NVME_MINORS * nvme_get_ns_idx();
1339         disk->fops = &nvme_fops;
1340         disk->private_data = ns;
1341         disk->queue = ns->queue;
1342         disk->driverfs_dev = &dev->pci_dev->dev;
1343         sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
1344         set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1345
1346         return ns;
1347
1348  out_free_queue:
1349         blk_cleanup_queue(ns->queue);
1350  out_free_ns:
1351         kfree(ns);
1352         return NULL;
1353 }
1354
1355 static void nvme_ns_free(struct nvme_ns *ns)
1356 {
1357         int index = ns->disk->first_minor / NVME_MINORS;
1358         put_disk(ns->disk);
1359         nvme_put_ns_idx(index);
1360         blk_cleanup_queue(ns->queue);
1361         kfree(ns);
1362 }
1363
1364 static int set_queue_count(struct nvme_dev *dev, int count)
1365 {
1366         int status;
1367         u32 result;
1368         struct nvme_command c;
1369         u32 q_count = (count - 1) | ((count - 1) << 16);
1370
1371         memset(&c, 0, sizeof(c));
1372         c.features.opcode = nvme_admin_get_features;
1373         c.features.fid = cpu_to_le32(NVME_FEAT_NUM_QUEUES);
1374         c.features.dword11 = cpu_to_le32(q_count);
1375
1376         status = nvme_submit_admin_cmd(dev, &c, &result);
1377         if (status)
1378                 return -EIO;
1379         return min(result & 0xffff, result >> 16) + 1;
1380 }
1381
1382 static int __devinit nvme_setup_io_queues(struct nvme_dev *dev)
1383 {
1384         int result, cpu, i, nr_io_queues;
1385
1386         nr_io_queues = num_online_cpus();
1387         result = set_queue_count(dev, nr_io_queues);
1388         if (result < 0)
1389                 return result;
1390         if (result < nr_io_queues)
1391                 nr_io_queues = result;
1392
1393         /* Deregister the admin queue's interrupt */
1394         free_irq(dev->entry[0].vector, dev->queues[0]);
1395
1396         for (i = 0; i < nr_io_queues; i++)
1397                 dev->entry[i].entry = i;
1398         for (;;) {
1399                 result = pci_enable_msix(dev->pci_dev, dev->entry,
1400                                                                 nr_io_queues);
1401                 if (result == 0) {
1402                         break;
1403                 } else if (result > 0) {
1404                         nr_io_queues = result;
1405                         continue;
1406                 } else {
1407                         nr_io_queues = 1;
1408                         break;
1409                 }
1410         }
1411
1412         result = queue_request_irq(dev, dev->queues[0], "nvme admin");
1413         /* XXX: handle failure here */
1414
1415         cpu = cpumask_first(cpu_online_mask);
1416         for (i = 0; i < nr_io_queues; i++) {
1417                 irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu));
1418                 cpu = cpumask_next(cpu, cpu_online_mask);
1419         }
1420
1421         for (i = 0; i < nr_io_queues; i++) {
1422                 dev->queues[i + 1] = nvme_create_queue(dev, i + 1,
1423                                                         NVME_Q_DEPTH, i);
1424                 if (!dev->queues[i + 1])
1425                         return -ENOMEM;
1426                 dev->queue_count++;
1427         }
1428
1429         for (; i < num_possible_cpus(); i++) {
1430                 int target = i % rounddown_pow_of_two(dev->queue_count - 1);
1431                 dev->queues[i + 1] = dev->queues[target + 1];
1432         }
1433
1434         return 0;
1435 }
1436
1437 static void nvme_free_queues(struct nvme_dev *dev)
1438 {
1439         int i;
1440
1441         for (i = dev->queue_count - 1; i >= 0; i--)
1442                 nvme_free_queue(dev, i);
1443 }
1444
1445 static int __devinit nvme_dev_add(struct nvme_dev *dev)
1446 {
1447         int res, nn, i;
1448         struct nvme_ns *ns, *next;
1449         struct nvme_id_ctrl *ctrl;
1450         void *id;
1451         dma_addr_t dma_addr;
1452         struct nvme_command cid, crt;
1453
1454         res = nvme_setup_io_queues(dev);
1455         if (res)
1456                 return res;
1457
1458         /* XXX: Switch to a SG list once prp2 works */
1459         id = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr,
1460                                                                 GFP_KERNEL);
1461
1462         memset(&cid, 0, sizeof(cid));
1463         cid.identify.opcode = nvme_admin_identify;
1464         cid.identify.nsid = 0;
1465         cid.identify.prp1 = cpu_to_le64(dma_addr);
1466         cid.identify.cns = cpu_to_le32(1);
1467
1468         res = nvme_submit_admin_cmd(dev, &cid, NULL);
1469         if (res) {
1470                 res = -EIO;
1471                 goto out_free;
1472         }
1473
1474         ctrl = id;
1475         nn = le32_to_cpup(&ctrl->nn);
1476         memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
1477         memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
1478         memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
1479
1480         cid.identify.cns = 0;
1481         memset(&crt, 0, sizeof(crt));
1482         crt.features.opcode = nvme_admin_get_features;
1483         crt.features.prp1 = cpu_to_le64(dma_addr + 4096);
1484         crt.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE);
1485
1486         for (i = 0; i <= nn; i++) {
1487                 cid.identify.nsid = cpu_to_le32(i);
1488                 res = nvme_submit_admin_cmd(dev, &cid, NULL);
1489                 if (res)
1490                         continue;
1491
1492                 if (((struct nvme_id_ns *)id)->ncap == 0)
1493                         continue;
1494
1495                 crt.features.nsid = cpu_to_le32(i);
1496                 res = nvme_submit_admin_cmd(dev, &crt, NULL);
1497                 if (res)
1498                         continue;
1499
1500                 ns = nvme_alloc_ns(dev, i, id, id + 4096);
1501                 if (ns)
1502                         list_add_tail(&ns->list, &dev->namespaces);
1503         }
1504         list_for_each_entry(ns, &dev->namespaces, list)
1505                 add_disk(ns->disk);
1506
1507         dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1508         return 0;
1509
1510  out_free:
1511         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1512                 list_del(&ns->list);
1513                 nvme_ns_free(ns);
1514         }
1515
1516         dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1517         return res;
1518 }
1519
1520 static int nvme_dev_remove(struct nvme_dev *dev)
1521 {
1522         struct nvme_ns *ns, *next;
1523
1524         spin_lock(&dev_list_lock);
1525         list_del(&dev->node);
1526         spin_unlock(&dev_list_lock);
1527
1528         /* TODO: wait all I/O finished or cancel them */
1529
1530         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1531                 list_del(&ns->list);
1532                 del_gendisk(ns->disk);
1533                 nvme_ns_free(ns);
1534         }
1535
1536         nvme_free_queues(dev);
1537
1538         return 0;
1539 }
1540
1541 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1542 {
1543         struct device *dmadev = &dev->pci_dev->dev;
1544         dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
1545                                                 PAGE_SIZE, PAGE_SIZE, 0);
1546         if (!dev->prp_page_pool)
1547                 return -ENOMEM;
1548
1549         /* Optimisation for I/Os between 4k and 128k */
1550         dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
1551                                                 256, 256, 0);
1552         if (!dev->prp_small_pool) {
1553                 dma_pool_destroy(dev->prp_page_pool);
1554                 return -ENOMEM;
1555         }
1556         return 0;
1557 }
1558
1559 static void nvme_release_prp_pools(struct nvme_dev *dev)
1560 {
1561         dma_pool_destroy(dev->prp_page_pool);
1562         dma_pool_destroy(dev->prp_small_pool);
1563 }
1564
1565 /* XXX: Use an ida or something to let remove / add work correctly */
1566 static void nvme_set_instance(struct nvme_dev *dev)
1567 {
1568         static int instance;
1569         dev->instance = instance++;
1570 }
1571
1572 static void nvme_release_instance(struct nvme_dev *dev)
1573 {
1574 }
1575
1576 static int __devinit nvme_probe(struct pci_dev *pdev,
1577                                                 const struct pci_device_id *id)
1578 {
1579         int bars, result = -ENOMEM;
1580         struct nvme_dev *dev;
1581
1582         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1583         if (!dev)
1584                 return -ENOMEM;
1585         dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
1586                                                                 GFP_KERNEL);
1587         if (!dev->entry)
1588                 goto free;
1589         dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
1590                                                                 GFP_KERNEL);
1591         if (!dev->queues)
1592                 goto free;
1593
1594         if (pci_enable_device_mem(pdev))
1595                 goto free;
1596         pci_set_master(pdev);
1597         bars = pci_select_bars(pdev, IORESOURCE_MEM);
1598         if (pci_request_selected_regions(pdev, bars, "nvme"))
1599                 goto disable;
1600
1601         INIT_LIST_HEAD(&dev->namespaces);
1602         dev->pci_dev = pdev;
1603         pci_set_drvdata(pdev, dev);
1604         dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1605         dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1606         nvme_set_instance(dev);
1607         dev->entry[0].vector = pdev->irq;
1608
1609         result = nvme_setup_prp_pools(dev);
1610         if (result)
1611                 goto disable_msix;
1612
1613         dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1614         if (!dev->bar) {
1615                 result = -ENOMEM;
1616                 goto disable_msix;
1617         }
1618
1619         result = nvme_configure_admin_queue(dev);
1620         if (result)
1621                 goto unmap;
1622         dev->queue_count++;
1623
1624         spin_lock(&dev_list_lock);
1625         list_add(&dev->node, &dev_list);
1626         spin_unlock(&dev_list_lock);
1627
1628         result = nvme_dev_add(dev);
1629         if (result)
1630                 goto delete;
1631
1632         return 0;
1633
1634  delete:
1635         spin_lock(&dev_list_lock);
1636         list_del(&dev->node);
1637         spin_unlock(&dev_list_lock);
1638
1639         nvme_free_queues(dev);
1640  unmap:
1641         iounmap(dev->bar);
1642  disable_msix:
1643         pci_disable_msix(pdev);
1644         nvme_release_instance(dev);
1645         nvme_release_prp_pools(dev);
1646  disable:
1647         pci_disable_device(pdev);
1648         pci_release_regions(pdev);
1649  free:
1650         kfree(dev->queues);
1651         kfree(dev->entry);
1652         kfree(dev);
1653         return result;
1654 }
1655
1656 static void __devexit nvme_remove(struct pci_dev *pdev)
1657 {
1658         struct nvme_dev *dev = pci_get_drvdata(pdev);
1659         nvme_dev_remove(dev);
1660         pci_disable_msix(pdev);
1661         iounmap(dev->bar);
1662         nvme_release_instance(dev);
1663         nvme_release_prp_pools(dev);
1664         pci_disable_device(pdev);
1665         pci_release_regions(pdev);
1666         kfree(dev->queues);
1667         kfree(dev->entry);
1668         kfree(dev);
1669 }
1670
1671 /* These functions are yet to be implemented */
1672 #define nvme_error_detected NULL
1673 #define nvme_dump_registers NULL
1674 #define nvme_link_reset NULL
1675 #define nvme_slot_reset NULL
1676 #define nvme_error_resume NULL
1677 #define nvme_suspend NULL
1678 #define nvme_resume NULL
1679
1680 static struct pci_error_handlers nvme_err_handler = {
1681         .error_detected = nvme_error_detected,
1682         .mmio_enabled   = nvme_dump_registers,
1683         .link_reset     = nvme_link_reset,
1684         .slot_reset     = nvme_slot_reset,
1685         .resume         = nvme_error_resume,
1686 };
1687
1688 /* Move to pci_ids.h later */
1689 #define PCI_CLASS_STORAGE_EXPRESS       0x010802
1690
1691 static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = {
1692         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
1693         { 0, }
1694 };
1695 MODULE_DEVICE_TABLE(pci, nvme_id_table);
1696
1697 static struct pci_driver nvme_driver = {
1698         .name           = "nvme",
1699         .id_table       = nvme_id_table,
1700         .probe          = nvme_probe,
1701         .remove         = __devexit_p(nvme_remove),
1702         .suspend        = nvme_suspend,
1703         .resume         = nvme_resume,
1704         .err_handler    = &nvme_err_handler,
1705 };
1706
1707 static int __init nvme_init(void)
1708 {
1709         int result = -EBUSY;
1710
1711         nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
1712         if (IS_ERR(nvme_thread))
1713                 return PTR_ERR(nvme_thread);
1714
1715         nvme_major = register_blkdev(nvme_major, "nvme");
1716         if (nvme_major <= 0)
1717                 goto kill_kthread;
1718
1719         result = pci_register_driver(&nvme_driver);
1720         if (result)
1721                 goto unregister_blkdev;
1722         return 0;
1723
1724  unregister_blkdev:
1725         unregister_blkdev(nvme_major, "nvme");
1726  kill_kthread:
1727         kthread_stop(nvme_thread);
1728         return result;
1729 }
1730
1731 static void __exit nvme_exit(void)
1732 {
1733         pci_unregister_driver(&nvme_driver);
1734         unregister_blkdev(nvme_major, "nvme");
1735         kthread_stop(nvme_thread);
1736 }
1737
1738 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
1739 MODULE_LICENSE("GPL");
1740 MODULE_VERSION("0.5");
1741 module_init(nvme_init);
1742 module_exit(nvme_exit);