drivers/bus/arm-ccn.c

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License version 2 as
   4  * published by the Free Software Foundation.
   5  *
   6  * This program is distributed in the hope that it will be useful,
   7  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   8  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   9  * GNU General Public License for more details.
  10  *
  11  * Copyright (C) 2014 ARM Limited
  12  */
  13
  14 #include <linux/ctype.h>
  15 #include <linux/hrtimer.h>
  16 #include <linux/idr.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/perf_event.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/slab.h>
  23
  24 #define CCN_NUM_XP_PORTS 2
  25 #define CCN_NUM_VCS 4
  26 #define CCN_NUM_REGIONS 256
  27 #define CCN_REGION_SIZE 0x10000
  28
  29 #define CCN_ALL_OLY_ID                  0xff00
  30 #define CCN_ALL_OLY_ID__OLY_ID__SHIFT                   0
  31 #define CCN_ALL_OLY_ID__OLY_ID__MASK                    0x1f
  32 #define CCN_ALL_OLY_ID__NODE_ID__SHIFT                  8
  33 #define CCN_ALL_OLY_ID__NODE_ID__MASK                   0x3f
  34
  35 #define CCN_MN_ERRINT_STATUS            0x0008
  36 #define CCN_MN_ERRINT_STATUS__INTREQ__DESSERT           0x11
  37 #define CCN_MN_ERRINT_STATUS__ALL_ERRORS__ENABLE        0x02
  38 #define CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLED      0x20
  39 #define CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLE       0x22
  40 #define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_ENABLE   0x04
  41 #define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_DISABLED 0x40
  42 #define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_DISABLE  0x44
  43 #define CCN_MN_ERRINT_STATUS__PMU_EVENTS__ENABLE        0x08
  44 #define CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLED      0x80
  45 #define CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLE       0x88
  46 #define CCN_MN_OLY_COMP_LIST_63_0       0x01e0
  47 #define CCN_MN_ERR_SIG_VAL_63_0         0x0300
  48 #define CCN_MN_ERR_SIG_VAL_63_0__DT                     (1 << 1)
  49
  50 #define CCN_DT_ACTIVE_DSM               0x0000
  51 #define CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(n)             ((n) * 8)
  52 #define CCN_DT_ACTIVE_DSM__DSM_ID__MASK                 0xff
  53 #define CCN_DT_CTL                      0x0028
  54 #define CCN_DT_CTL__DT_EN                               (1 << 0)
  55 #define CCN_DT_PMEVCNT(n)               (0x0100 + (n) * 0x8)
  56 #define CCN_DT_PMCCNTR                  0x0140
  57 #define CCN_DT_PMCCNTRSR                0x0190
  58 #define CCN_DT_PMOVSR                   0x0198
  59 #define CCN_DT_PMOVSR_CLR               0x01a0
  60 #define CCN_DT_PMOVSR_CLR__MASK                         0x1f
  61 #define CCN_DT_PMCR                     0x01a8
  62 #define CCN_DT_PMCR__OVFL_INTR_EN                       (1 << 6)
  63 #define CCN_DT_PMCR__PMU_EN                             (1 << 0)
  64 #define CCN_DT_PMSR                     0x01b0
  65 #define CCN_DT_PMSR_REQ                 0x01b8
  66 #define CCN_DT_PMSR_CLR                 0x01c0
  67
  68 #define CCN_HNF_PMU_EVENT_SEL           0x0600
  69 #define CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(n)             ((n) * 4)
  70 #define CCN_HNF_PMU_EVENT_SEL__ID__MASK                 0xf
  71
  72 #define CCN_XP_DT_CONFIG                0x0300
  73 #define CCN_XP_DT_CONFIG__DT_CFG__SHIFT(n)              ((n) * 4)
  74 #define CCN_XP_DT_CONFIG__DT_CFG__MASK                  0xf
  75 #define CCN_XP_DT_CONFIG__DT_CFG__PASS_THROUGH          0x0
  76 #define CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT_0_OR_1     0x1
  77 #define CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT(n)         (0x2 + (n))
  78 #define CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(n)       (0x4 + (n))
  79 #define CCN_XP_DT_CONFIG__DT_CFG__DEVICE_PMU_EVENT(d, n) (0x8 + (d) * 4 + (n))
  80 #define CCN_XP_DT_INTERFACE_SEL         0x0308
  81 #define CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(n)    (0 + (n) * 8)
  82 #define CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__MASK        0x1
  83 #define CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(n)   (1 + (n) * 8)
  84 #define CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__MASK       0x1
  85 #define CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(n)    (2 + (n) * 8)
  86 #define CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__MASK        0x3
  87 #define CCN_XP_DT_CMP_VAL_L(n)          (0x0310 + (n) * 0x40)
  88 #define CCN_XP_DT_CMP_VAL_H(n)          (0x0318 + (n) * 0x40)
  89 #define CCN_XP_DT_CMP_MASK_L(n)         (0x0320 + (n) * 0x40)
  90 #define CCN_XP_DT_CMP_MASK_H(n)         (0x0328 + (n) * 0x40)
  91 #define CCN_XP_DT_CONTROL               0x0370
  92 #define CCN_XP_DT_CONTROL__DT_ENABLE                    (1 << 0)
  93 #define CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(n)         (12 + (n) * 4)
  94 #define CCN_XP_DT_CONTROL__WP_ARM_SEL__MASK             0xf
  95 #define CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS           0xf
  96 #define CCN_XP_PMU_EVENT_SEL            0x0600
  97 #define CCN_XP_PMU_EVENT_SEL__ID__SHIFT(n)              ((n) * 7)
  98 #define CCN_XP_PMU_EVENT_SEL__ID__MASK                  0x3f
  99
 100 #define CCN_SBAS_PMU_EVENT_SEL          0x0600
 101 #define CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(n)            ((n) * 4)
 102 #define CCN_SBAS_PMU_EVENT_SEL__ID__MASK                0xf
 103
 104 #define CCN_RNI_PMU_EVENT_SEL           0x0600
 105 #define CCN_RNI_PMU_EVENT_SEL__ID__SHIFT(n)             ((n) * 4)
 106 #define CCN_RNI_PMU_EVENT_SEL__ID__MASK                 0xf
 107
 108 #define CCN_TYPE_MN     0x01
 109 #define CCN_TYPE_DT     0x02
 110 #define CCN_TYPE_HNF    0x04
 111 #define CCN_TYPE_HNI    0x05
 112 #define CCN_TYPE_XP     0x08
 113 #define CCN_TYPE_SBSX   0x0c
 114 #define CCN_TYPE_SBAS   0x10
 115 #define CCN_TYPE_RNI_1P 0x14
 116 #define CCN_TYPE_RNI_2P 0x15
 117 #define CCN_TYPE_RNI_3P 0x16
 118 #define CCN_TYPE_RND_1P 0x18 /* RN-D = RN-I + DVM */
 119 #define CCN_TYPE_RND_2P 0x19
 120 #define CCN_TYPE_RND_3P 0x1a
 121 #define CCN_TYPE_CYCLES 0xff /* Pseudotype */
 122
 123 #define CCN_EVENT_WATCHPOINT 0xfe /* Pseudoevent */
 124
 125 #define CCN_NUM_PMU_EVENTS              4
 126 #define CCN_NUM_XP_WATCHPOINTS          2 /* See DT.dbg_id.num_watchpoints */
 127 #define CCN_NUM_PMU_EVENT_COUNTERS      8 /* See DT.dbg_id.num_pmucntr */
 128 #define CCN_IDX_PMU_CYCLE_COUNTER       CCN_NUM_PMU_EVENT_COUNTERS
 129
 130 #define CCN_NUM_PREDEFINED_MASKS        4
 131 #define CCN_IDX_MASK_ANY                (CCN_NUM_PMU_EVENT_COUNTERS + 0)
 132 #define CCN_IDX_MASK_EXACT              (CCN_NUM_PMU_EVENT_COUNTERS + 1)
 133 #define CCN_IDX_MASK_ORDER              (CCN_NUM_PMU_EVENT_COUNTERS + 2)
 134 #define CCN_IDX_MASK_OPCODE             (CCN_NUM_PMU_EVENT_COUNTERS + 3)
 135
 136 struct arm_ccn_component {
 137         void __iomem *base;
 138         u32 type;
 139
 140         DECLARE_BITMAP(pmu_events_mask, CCN_NUM_PMU_EVENTS);
 141         union {
 142                 struct {
 143                         DECLARE_BITMAP(dt_cmp_mask, CCN_NUM_XP_WATCHPOINTS);
 144                 } xp;
 145         };
 146 };
 147
 148 #define pmu_to_arm_ccn(_pmu) container_of(container_of(_pmu, \
 149         struct arm_ccn_dt, pmu), struct arm_ccn, dt)
 150
 151 struct arm_ccn_dt {
 152         int id;
 153         void __iomem *base;
 154
 155         spinlock_t config_lock;
 156
 157         DECLARE_BITMAP(pmu_counters_mask, CCN_NUM_PMU_EVENT_COUNTERS + 1);
 158         struct {
 159                 struct arm_ccn_component *source;
 160                 struct perf_event *event;
 161         } pmu_counters[CCN_NUM_PMU_EVENT_COUNTERS + 1];
 162
 163         struct {
 164                u64 l, h;
 165         } cmp_mask[CCN_NUM_PMU_EVENT_COUNTERS + CCN_NUM_PREDEFINED_MASKS];
 166
 167         struct hrtimer hrtimer;
 168
 169         cpumask_t cpu;
 170         struct hlist_node node;
 171
 172         struct pmu pmu;
 173 };
 174
 175 struct arm_ccn {
 176         struct device *dev;
 177         void __iomem *base;
 178         unsigned int irq;
 179
 180         unsigned sbas_present:1;
 181         unsigned sbsx_present:1;
 182
 183         int num_nodes;
 184         struct arm_ccn_component *node;
 185
 186         int num_xps;
 187         struct arm_ccn_component *xp;
 188
 189         struct arm_ccn_dt dt;
 190 };
 191
 192 static int arm_ccn_node_to_xp(int node)
 193 {
 194         return node / CCN_NUM_XP_PORTS;
 195 }
 196
 197 static int arm_ccn_node_to_xp_port(int node)
 198 {
 199         return node % CCN_NUM_XP_PORTS;
 200 }
 201
 202
 203 /*
 204  * Bit shifts and masks in these defines must be kept in sync with
 205  * arm_ccn_pmu_config_set() and CCN_FORMAT_ATTRs below!
 206  */
 207 #define CCN_CONFIG_NODE(_config)        (((_config) >> 0) & 0xff)
 208 #define CCN_CONFIG_XP(_config)          (((_config) >> 0) & 0xff)
 209 #define CCN_CONFIG_TYPE(_config)        (((_config) >> 8) & 0xff)
 210 #define CCN_CONFIG_EVENT(_config)       (((_config) >> 16) & 0xff)
 211 #define CCN_CONFIG_PORT(_config)        (((_config) >> 24) & 0x3)
 212 #define CCN_CONFIG_VC(_config)          (((_config) >> 26) & 0x7)
 213 #define CCN_CONFIG_DIR(_config)         (((_config) >> 29) & 0x1)
 214 #define CCN_CONFIG_MASK(_config)        (((_config) >> 30) & 0xf)
 215
 216 static void arm_ccn_pmu_config_set(u64 *config, u32 node_xp, u32 type, u32 port)
 217 {
 218         *config &= ~((0xff << 0) | (0xff << 8) | (0x3 << 24));
 219         *config |= (node_xp << 0) | (type << 8) | (port << 24);
 220 }
 221
 222 static ssize_t arm_ccn_pmu_format_show(struct device *dev,
 223                 struct device_attribute *attr, char *buf)
 224 {
 225         struct dev_ext_attribute *ea = container_of(attr,
 226                         struct dev_ext_attribute, attr);
 227
 228         return snprintf(buf, PAGE_SIZE, "%s\n", (char *)ea->var);
 229 }
 230
 231 #define CCN_FORMAT_ATTR(_name, _config) \
 232         struct dev_ext_attribute arm_ccn_pmu_format_attr_##_name = \
 233                         { __ATTR(_name, S_IRUGO, arm_ccn_pmu_format_show, \
 234                         NULL), _config }
 235
 236 static CCN_FORMAT_ATTR(node, "config:0-7");
 237 static CCN_FORMAT_ATTR(xp, "config:0-7");
 238 static CCN_FORMAT_ATTR(type, "config:8-15");
 239 static CCN_FORMAT_ATTR(event, "config:16-23");
 240 static CCN_FORMAT_ATTR(port, "config:24-25");
 241 static CCN_FORMAT_ATTR(vc, "config:26-28");
 242 static CCN_FORMAT_ATTR(dir, "config:29-29");
 243 static CCN_FORMAT_ATTR(mask, "config:30-33");
 244 static CCN_FORMAT_ATTR(cmp_l, "config1:0-62");
 245 static CCN_FORMAT_ATTR(cmp_h, "config2:0-59");
 246
 247 static struct attribute *arm_ccn_pmu_format_attrs[] = {
 248         &arm_ccn_pmu_format_attr_node.attr.attr,
 249         &arm_ccn_pmu_format_attr_xp.attr.attr,
 250         &arm_ccn_pmu_format_attr_type.attr.attr,
 251         &arm_ccn_pmu_format_attr_event.attr.attr,
 252         &arm_ccn_pmu_format_attr_port.attr.attr,
 253         &arm_ccn_pmu_format_attr_vc.attr.attr,
 254         &arm_ccn_pmu_format_attr_dir.attr.attr,
 255         &arm_ccn_pmu_format_attr_mask.attr.attr,
 256         &arm_ccn_pmu_format_attr_cmp_l.attr.attr,
 257         &arm_ccn_pmu_format_attr_cmp_h.attr.attr,
 258         NULL
 259 };
 260
 261 static struct attribute_group arm_ccn_pmu_format_attr_group = {
 262         .name = "format",
 263         .attrs = arm_ccn_pmu_format_attrs,
 264 };
 265
 266
 267 struct arm_ccn_pmu_event {
 268         struct device_attribute attr;
 269         u32 type;
 270         u32 event;
 271         int num_ports;
 272         int num_vcs;
 273         const char *def;
 274         int mask;
 275 };
 276
 277 #define CCN_EVENT_ATTR(_name) \
 278         __ATTR(_name, S_IRUGO, arm_ccn_pmu_event_show, NULL)
 279
 280 /*
 281  * Events defined in TRM for MN, HN-I and SBSX are actually watchpoints set on
 282  * their ports in XP they are connected to. For the sake of usability they are
 283  * explicitly defined here (and translated into a relevant watchpoint in
 284  * arm_ccn_pmu_event_init()) so the user can easily request them without deep
 285  * knowledge of the flit format.
 286  */
 287
 288 #define CCN_EVENT_MN(_name, _def, _mask) { .attr = CCN_EVENT_ATTR(mn_##_name), \
 289                 .type = CCN_TYPE_MN, .event = CCN_EVENT_WATCHPOINT, \
 290                 .num_ports = CCN_NUM_XP_PORTS, .num_vcs = CCN_NUM_VCS, \
 291                 .def = _def, .mask = _mask, }
 292
 293 #define CCN_EVENT_HNI(_name, _def, _mask) { \
 294                 .attr = CCN_EVENT_ATTR(hni_##_name), .type = CCN_TYPE_HNI, \
 295                 .event = CCN_EVENT_WATCHPOINT, .num_ports = CCN_NUM_XP_PORTS, \
 296                 .num_vcs = CCN_NUM_VCS, .def = _def, .mask = _mask, }
 297
 298 #define CCN_EVENT_SBSX(_name, _def, _mask) { \
 299                 .attr = CCN_EVENT_ATTR(sbsx_##_name), .type = CCN_TYPE_SBSX, \
 300                 .event = CCN_EVENT_WATCHPOINT, .num_ports = CCN_NUM_XP_PORTS, \
 301                 .num_vcs = CCN_NUM_VCS, .def = _def, .mask = _mask, }
 302
 303 #define CCN_EVENT_HNF(_name, _event) { .attr = CCN_EVENT_ATTR(hnf_##_name), \
 304                 .type = CCN_TYPE_HNF, .event = _event, }
 305
 306 #define CCN_EVENT_XP(_name, _event) { .attr = CCN_EVENT_ATTR(xp_##_name), \
 307                 .type = CCN_TYPE_XP, .event = _event, \
 308                 .num_ports = CCN_NUM_XP_PORTS, .num_vcs = CCN_NUM_VCS, }
 309
 310 /*
 311  * RN-I & RN-D (RN-D = RN-I + DVM) nodes have different type ID depending
 312  * on configuration. One of them is picked to represent the whole group,
 313  * as they all share the same event types.
 314  */
 315 #define CCN_EVENT_RNI(_name, _event) { .attr = CCN_EVENT_ATTR(rni_##_name), \
 316                 .type = CCN_TYPE_RNI_3P, .event = _event, }
 317
 318 #define CCN_EVENT_SBAS(_name, _event) { .attr = CCN_EVENT_ATTR(sbas_##_name), \
 319                 .type = CCN_TYPE_SBAS, .event = _event, }
 320
 321 #define CCN_EVENT_CYCLES(_name) { .attr = CCN_EVENT_ATTR(_name), \
 322                 .type = CCN_TYPE_CYCLES }
 323
 324
 325 static ssize_t arm_ccn_pmu_event_show(struct device *dev,
 326                 struct device_attribute *attr, char *buf)
 327 {
 328         struct arm_ccn_pmu_event *event = container_of(attr,
 329                         struct arm_ccn_pmu_event, attr);
 330         ssize_t res;
 331
 332         res = snprintf(buf, PAGE_SIZE, "type=0x%x", event->type);
 333         if (event->event)
 334                 res += snprintf(buf + res, PAGE_SIZE - res, ",event=0x%x",
 335                                 event->event);
 336         if (event->def)
 337                 res += snprintf(buf + res, PAGE_SIZE - res, ",%s",
 338                                 event->def);
 339         if (event->mask)
 340                 res += snprintf(buf + res, PAGE_SIZE - res, ",mask=0x%x",
 341                                 event->mask);
 342
 343         /* Arguments required by an event */
 344         switch (event->type) {
 345         case CCN_TYPE_CYCLES:
 346                 break;
 347         case CCN_TYPE_XP:
 348                 res += snprintf(buf + res, PAGE_SIZE - res,
 349                                 ",xp=?,port=?,vc=?,dir=?");
 350                 if (event->event == CCN_EVENT_WATCHPOINT)
 351                         res += snprintf(buf + res, PAGE_SIZE - res,
 352                                         ",cmp_l=?,cmp_h=?,mask=?");
 353                 break;
 354         default:
 355                 res += snprintf(buf + res, PAGE_SIZE - res, ",node=?");
 356                 break;
 357         }
 358
 359         res += snprintf(buf + res, PAGE_SIZE - res, "\n");
 360
 361         return res;
 362 }
 363
 364 static umode_t arm_ccn_pmu_events_is_visible(struct kobject *kobj,
 365                                      struct attribute *attr, int index)
 366 {
 367         struct device *dev = kobj_to_dev(kobj);
 368         struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
 369         struct device_attribute *dev_attr = container_of(attr,
 370                         struct device_attribute, attr);
 371         struct arm_ccn_pmu_event *event = container_of(dev_attr,
 372                         struct arm_ccn_pmu_event, attr);
 373
 374         if (event->type == CCN_TYPE_SBAS && !ccn->sbas_present)
 375                 return 0;
 376         if (event->type == CCN_TYPE_SBSX && !ccn->sbsx_present)
 377                 return 0;
 378
 379         return attr->mode;
 380 }
 381
 382 static struct arm_ccn_pmu_event arm_ccn_pmu_events[] = {
 383         CCN_EVENT_MN(eobarrier, "dir=0,vc=0,cmp_h=0x1c00", CCN_IDX_MASK_OPCODE),
 384         CCN_EVENT_MN(ecbarrier, "dir=0,vc=0,cmp_h=0x1e00", CCN_IDX_MASK_OPCODE),
 385         CCN_EVENT_MN(dvmop, "dir=0,vc=0,cmp_h=0x2800", CCN_IDX_MASK_OPCODE),
 386         CCN_EVENT_HNI(txdatflits, "dir=1,vc=3", CCN_IDX_MASK_ANY),
 387         CCN_EVENT_HNI(rxdatflits, "dir=0,vc=3", CCN_IDX_MASK_ANY),
 388         CCN_EVENT_HNI(txreqflits, "dir=1,vc=0", CCN_IDX_MASK_ANY),
 389         CCN_EVENT_HNI(rxreqflits, "dir=0,vc=0", CCN_IDX_MASK_ANY),
 390         CCN_EVENT_HNI(rxreqflits_order, "dir=0,vc=0,cmp_h=0x8000",
 391                         CCN_IDX_MASK_ORDER),
 392         CCN_EVENT_SBSX(txdatflits, "dir=1,vc=3", CCN_IDX_MASK_ANY),
 393         CCN_EVENT_SBSX(rxdatflits, "dir=0,vc=3", CCN_IDX_MASK_ANY),
 394         CCN_EVENT_SBSX(txreqflits, "dir=1,vc=0", CCN_IDX_MASK_ANY),
 395         CCN_EVENT_SBSX(rxreqflits, "dir=0,vc=0", CCN_IDX_MASK_ANY),
 396         CCN_EVENT_SBSX(rxreqflits_order, "dir=0,vc=0,cmp_h=0x8000",
 397                         CCN_IDX_MASK_ORDER),
 398         CCN_EVENT_HNF(cache_miss, 0x1),
 399         CCN_EVENT_HNF(l3_sf_cache_access, 0x02),
 400         CCN_EVENT_HNF(cache_fill, 0x3),
 401         CCN_EVENT_HNF(pocq_retry, 0x4),
 402         CCN_EVENT_HNF(pocq_reqs_recvd, 0x5),
 403         CCN_EVENT_HNF(sf_hit, 0x6),
 404         CCN_EVENT_HNF(sf_evictions, 0x7),
 405         CCN_EVENT_HNF(snoops_sent, 0x8),
 406         CCN_EVENT_HNF(snoops_broadcast, 0x9),
 407         CCN_EVENT_HNF(l3_eviction, 0xa),
 408         CCN_EVENT_HNF(l3_fill_invalid_way, 0xb),
 409         CCN_EVENT_HNF(mc_retries, 0xc),
 410         CCN_EVENT_HNF(mc_reqs, 0xd),
 411         CCN_EVENT_HNF(qos_hh_retry, 0xe),
 412         CCN_EVENT_RNI(rdata_beats_p0, 0x1),
 413         CCN_EVENT_RNI(rdata_beats_p1, 0x2),
 414         CCN_EVENT_RNI(rdata_beats_p2, 0x3),
 415         CCN_EVENT_RNI(rxdat_flits, 0x4),
 416         CCN_EVENT_RNI(txdat_flits, 0x5),
 417         CCN_EVENT_RNI(txreq_flits, 0x6),
 418         CCN_EVENT_RNI(txreq_flits_retried, 0x7),
 419         CCN_EVENT_RNI(rrt_full, 0x8),
 420         CCN_EVENT_RNI(wrt_full, 0x9),
 421         CCN_EVENT_RNI(txreq_flits_replayed, 0xa),
 422         CCN_EVENT_XP(upload_starvation, 0x1),
 423         CCN_EVENT_XP(download_starvation, 0x2),
 424         CCN_EVENT_XP(respin, 0x3),
 425         CCN_EVENT_XP(valid_flit, 0x4),
 426         CCN_EVENT_XP(watchpoint, CCN_EVENT_WATCHPOINT),
 427         CCN_EVENT_SBAS(rdata_beats_p0, 0x1),
 428         CCN_EVENT_SBAS(rxdat_flits, 0x4),
 429         CCN_EVENT_SBAS(txdat_flits, 0x5),
 430         CCN_EVENT_SBAS(txreq_flits, 0x6),
 431         CCN_EVENT_SBAS(txreq_flits_retried, 0x7),
 432         CCN_EVENT_SBAS(rrt_full, 0x8),
 433         CCN_EVENT_SBAS(wrt_full, 0x9),
 434         CCN_EVENT_SBAS(txreq_flits_replayed, 0xa),
 435         CCN_EVENT_CYCLES(cycles),
 436 };
 437
 438 /* Populated in arm_ccn_init() */
 439 static struct attribute
 440                 *arm_ccn_pmu_events_attrs[ARRAY_SIZE(arm_ccn_pmu_events) + 1];
 441
 442 static struct attribute_group arm_ccn_pmu_events_attr_group = {
 443         .name = "events",
 444         .is_visible = arm_ccn_pmu_events_is_visible,
 445         .attrs = arm_ccn_pmu_events_attrs,
 446 };
 447
 448
 449 static u64 *arm_ccn_pmu_get_cmp_mask(struct arm_ccn *ccn, const char *name)
 450 {
 451         unsigned long i;
 452
 453         if (WARN_ON(!name || !name[0] || !isxdigit(name[0]) || !name[1]))
 454                 return NULL;
 455         i = isdigit(name[0]) ? name[0] - '0' : 0xa + tolower(name[0]) - 'a';
 456
 457         switch (name[1]) {
 458         case 'l':
 459                 return &ccn->dt.cmp_mask[i].l;
 460         case 'h':
 461                 return &ccn->dt.cmp_mask[i].h;
 462         default:
 463                 return NULL;
 464         }
 465 }
 466
 467 static ssize_t arm_ccn_pmu_cmp_mask_show(struct device *dev,
 468                 struct device_attribute *attr, char *buf)
 469 {
 470         struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
 471         u64 *mask = arm_ccn_pmu_get_cmp_mask(ccn, attr->attr.name);
 472
 473         return mask ? snprintf(buf, PAGE_SIZE, "0x%016llx\n", *mask) : -EINVAL;
 474 }
 475
 476 static ssize_t arm_ccn_pmu_cmp_mask_store(struct device *dev,
 477                 struct device_attribute *attr, const char *buf, size_t count)
 478 {
 479         struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
 480         u64 *mask = arm_ccn_pmu_get_cmp_mask(ccn, attr->attr.name);
 481         int err = -EINVAL;
 482
 483         if (mask)
 484                 err = kstrtoull(buf, 0, mask);
 485
 486         return err ? err : count;
 487 }
 488
 489 #define CCN_CMP_MASK_ATTR(_name) \
 490         struct device_attribute arm_ccn_pmu_cmp_mask_attr_##_name = \
 491                         __ATTR(_name, S_IRUGO | S_IWUSR, \
 492                         arm_ccn_pmu_cmp_mask_show, arm_ccn_pmu_cmp_mask_store)
 493
 494 #define CCN_CMP_MASK_ATTR_RO(_name) \
 495         struct device_attribute arm_ccn_pmu_cmp_mask_attr_##_name = \
 496                         __ATTR(_name, S_IRUGO, arm_ccn_pmu_cmp_mask_show, NULL)
 497
 498 static CCN_CMP_MASK_ATTR(0l);
 499 static CCN_CMP_MASK_ATTR(0h);
 500 static CCN_CMP_MASK_ATTR(1l);
 501 static CCN_CMP_MASK_ATTR(1h);
 502 static CCN_CMP_MASK_ATTR(2l);
 503 static CCN_CMP_MASK_ATTR(2h);
 504 static CCN_CMP_MASK_ATTR(3l);
 505 static CCN_CMP_MASK_ATTR(3h);
 506 static CCN_CMP_MASK_ATTR(4l);
 507 static CCN_CMP_MASK_ATTR(4h);
 508 static CCN_CMP_MASK_ATTR(5l);
 509 static CCN_CMP_MASK_ATTR(5h);
 510 static CCN_CMP_MASK_ATTR(6l);
 511 static CCN_CMP_MASK_ATTR(6h);
 512 static CCN_CMP_MASK_ATTR(7l);
 513 static CCN_CMP_MASK_ATTR(7h);
 514 static CCN_CMP_MASK_ATTR_RO(8l);
 515 static CCN_CMP_MASK_ATTR_RO(8h);
 516 static CCN_CMP_MASK_ATTR_RO(9l);
 517 static CCN_CMP_MASK_ATTR_RO(9h);
 518 static CCN_CMP_MASK_ATTR_RO(al);
 519 static CCN_CMP_MASK_ATTR_RO(ah);
 520 static CCN_CMP_MASK_ATTR_RO(bl);
 521 static CCN_CMP_MASK_ATTR_RO(bh);
 522
 523 static struct attribute *arm_ccn_pmu_cmp_mask_attrs[] = {
 524         &arm_ccn_pmu_cmp_mask_attr_0l.attr, &arm_ccn_pmu_cmp_mask_attr_0h.attr,
 525         &arm_ccn_pmu_cmp_mask_attr_1l.attr, &arm_ccn_pmu_cmp_mask_attr_1h.attr,
 526         &arm_ccn_pmu_cmp_mask_attr_2l.attr, &arm_ccn_pmu_cmp_mask_attr_2h.attr,
 527         &arm_ccn_pmu_cmp_mask_attr_3l.attr, &arm_ccn_pmu_cmp_mask_attr_3h.attr,
 528         &arm_ccn_pmu_cmp_mask_attr_4l.attr, &arm_ccn_pmu_cmp_mask_attr_4h.attr,
 529         &arm_ccn_pmu_cmp_mask_attr_5l.attr, &arm_ccn_pmu_cmp_mask_attr_5h.attr,
 530         &arm_ccn_pmu_cmp_mask_attr_6l.attr, &arm_ccn_pmu_cmp_mask_attr_6h.attr,
 531         &arm_ccn_pmu_cmp_mask_attr_7l.attr, &arm_ccn_pmu_cmp_mask_attr_7h.attr,
 532         &arm_ccn_pmu_cmp_mask_attr_8l.attr, &arm_ccn_pmu_cmp_mask_attr_8h.attr,
 533         &arm_ccn_pmu_cmp_mask_attr_9l.attr, &arm_ccn_pmu_cmp_mask_attr_9h.attr,
 534         &arm_ccn_pmu_cmp_mask_attr_al.attr, &arm_ccn_pmu_cmp_mask_attr_ah.attr,
 535         &arm_ccn_pmu_cmp_mask_attr_bl.attr, &arm_ccn_pmu_cmp_mask_attr_bh.attr,
 536         NULL
 537 };
 538
 539 static struct attribute_group arm_ccn_pmu_cmp_mask_attr_group = {
 540         .name = "cmp_mask",
 541         .attrs = arm_ccn_pmu_cmp_mask_attrs,
 542 };
 543
 544 static ssize_t arm_ccn_pmu_cpumask_show(struct device *dev,
 545                                      struct device_attribute *attr, char *buf)
 546 {
 547         struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
 548
 549         return cpumap_print_to_pagebuf(true, buf, &ccn->dt.cpu);
 550 }
 551
 552 static struct device_attribute arm_ccn_pmu_cpumask_attr =
 553                 __ATTR(cpumask, S_IRUGO, arm_ccn_pmu_cpumask_show, NULL);
 554
 555 static struct attribute *arm_ccn_pmu_cpumask_attrs[] = {
 556         &arm_ccn_pmu_cpumask_attr.attr,
 557         NULL,
 558 };
 559
 560 static struct attribute_group arm_ccn_pmu_cpumask_attr_group = {
 561         .attrs = arm_ccn_pmu_cpumask_attrs,
 562 };
 563
 564 /*
 565  * Default poll period is 10ms, which is way over the top anyway,
 566  * as in the worst case scenario (an event every cycle), with 1GHz
 567  * clocked bus, the smallest, 32 bit counter will overflow in
 568  * more than 4s.
 569  */
 570 static unsigned int arm_ccn_pmu_poll_period_us = 10000;
 571 module_param_named(pmu_poll_period_us, arm_ccn_pmu_poll_period_us, uint,
 572                 S_IRUGO | S_IWUSR);
 573
 574 static ktime_t arm_ccn_pmu_timer_period(void)
 575 {
 576         return ns_to_ktime((u64)arm_ccn_pmu_poll_period_us * 1000);
 577 }
 578
 579
 580 static const struct attribute_group *arm_ccn_pmu_attr_groups[] = {
 581         &arm_ccn_pmu_events_attr_group,
 582         &arm_ccn_pmu_format_attr_group,
 583         &arm_ccn_pmu_cmp_mask_attr_group,
 584         &arm_ccn_pmu_cpumask_attr_group,
 585         NULL
 586 };
 587
 588
 589 static int arm_ccn_pmu_alloc_bit(unsigned long *bitmap, unsigned long size)
 590 {
 591         int bit;
 592
 593         do {
 594                 bit = find_first_zero_bit(bitmap, size);
 595                 if (bit >= size)
 596                         return -EAGAIN;
 597         } while (test_and_set_bit(bit, bitmap));
 598
 599         return bit;
 600 }
 601
 602 /* All RN-I and RN-D nodes have identical PMUs */
 603 static int arm_ccn_pmu_type_eq(u32 a, u32 b)
 604 {
 605         if (a == b)
 606                 return 1;
 607
 608         switch (a) {
 609         case CCN_TYPE_RNI_1P:
 610         case CCN_TYPE_RNI_2P:
 611         case CCN_TYPE_RNI_3P:
 612         case CCN_TYPE_RND_1P:
 613         case CCN_TYPE_RND_2P:
 614         case CCN_TYPE_RND_3P:
 615                 switch (b) {
 616                 case CCN_TYPE_RNI_1P:
 617                 case CCN_TYPE_RNI_2P:
 618                 case CCN_TYPE_RNI_3P:
 619                 case CCN_TYPE_RND_1P:
 620                 case CCN_TYPE_RND_2P:
 621                 case CCN_TYPE_RND_3P:
 622                         return 1;
 623                 }
 624                 break;
 625         }
 626
 627         return 0;
 628 }
 629
 630 static int arm_ccn_pmu_event_alloc(struct perf_event *event)
 631 {
 632         struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
 633         struct hw_perf_event *hw = &event->hw;
 634         u32 node_xp, type, event_id;
 635         struct arm_ccn_component *source;
 636         int bit;
 637
 638         node_xp = CCN_CONFIG_NODE(event->attr.config);
 639         type = CCN_CONFIG_TYPE(event->attr.config);
 640         event_id = CCN_CONFIG_EVENT(event->attr.config);
 641
 642         /* Allocate the cycle counter */
 643         if (type == CCN_TYPE_CYCLES) {
 644                 if (test_and_set_bit(CCN_IDX_PMU_CYCLE_COUNTER,
 645                                 ccn->dt.pmu_counters_mask))
 646                         return -EAGAIN;
 647
 648                 hw->idx = CCN_IDX_PMU_CYCLE_COUNTER;
 649                 ccn->dt.pmu_counters[CCN_IDX_PMU_CYCLE_COUNTER].event = event;
 650
 651                 return 0;
 652         }
 653
 654         /* Allocate an event counter */
 655         hw->idx = arm_ccn_pmu_alloc_bit(ccn->dt.pmu_counters_mask,
 656                         CCN_NUM_PMU_EVENT_COUNTERS);
 657         if (hw->idx < 0) {
 658                 dev_dbg(ccn->dev, "No more counters available!\n");
 659                 return -EAGAIN;
 660         }
 661
 662         if (type == CCN_TYPE_XP)
 663                 source = &ccn->xp[node_xp];
 664         else
 665                 source = &ccn->node[node_xp];
 666         ccn->dt.pmu_counters[hw->idx].source = source;
 667
 668         /* Allocate an event source or a watchpoint */
 669         if (type == CCN_TYPE_XP && event_id == CCN_EVENT_WATCHPOINT)
 670                 bit = arm_ccn_pmu_alloc_bit(source->xp.dt_cmp_mask,
 671                                 CCN_NUM_XP_WATCHPOINTS);
 672         else
 673                 bit = arm_ccn_pmu_alloc_bit(source->pmu_events_mask,
 674                                 CCN_NUM_PMU_EVENTS);
 675         if (bit < 0) {
 676                 dev_dbg(ccn->dev, "No more event sources/watchpoints on node/XP %d!\n",
 677                                 node_xp);
 678                 clear_bit(hw->idx, ccn->dt.pmu_counters_mask);
 679                 return -EAGAIN;
 680         }
 681         hw->config_base = bit;
 682
 683         ccn->dt.pmu_counters[hw->idx].event = event;
 684
 685         return 0;
 686 }
 687
 688 static void arm_ccn_pmu_event_release(struct perf_event *event)
 689 {
 690         struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
 691         struct hw_perf_event *hw = &event->hw;
 692
 693         if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER) {
 694                 clear_bit(CCN_IDX_PMU_CYCLE_COUNTER, ccn->dt.pmu_counters_mask);
 695         } else {
 696                 struct arm_ccn_component *source =
 697                                 ccn->dt.pmu_counters[hw->idx].source;
 698
 699                 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP &&
 700                                 CCN_CONFIG_EVENT(event->attr.config) ==
 701                                 CCN_EVENT_WATCHPOINT)
 702                         clear_bit(hw->config_base, source->xp.dt_cmp_mask);
 703                 else
 704                         clear_bit(hw->config_base, source->pmu_events_mask);
 705                 clear_bit(hw->idx, ccn->dt.pmu_counters_mask);
 706         }
 707
 708         ccn->dt.pmu_counters[hw->idx].source = NULL;
 709         ccn->dt.pmu_counters[hw->idx].event = NULL;
 710 }
 711
 712 static int arm_ccn_pmu_event_init(struct perf_event *event)
 713 {
 714         struct arm_ccn *ccn;
 715         struct hw_perf_event *hw = &event->hw;
 716         u32 node_xp, type, event_id;
 717         int valid;
 718         int i;
 719         struct perf_event *sibling;
 720
 721         if (event->attr.type != event->pmu->type)
 722                 return -ENOENT;
 723
 724         ccn = pmu_to_arm_ccn(event->pmu);
 725
 726         if (hw->sample_period) {
 727                 dev_warn(ccn->dev, "Sampling not supported!\n");
 728                 return -EOPNOTSUPP;
 729         }
 730
 731         if (has_branch_stack(event) || event->attr.exclude_user ||
 732                         event->attr.exclude_kernel || event->attr.exclude_hv ||
 733                         event->attr.exclude_idle) {
 734                 dev_warn(ccn->dev, "Can't exclude execution levels!\n");
 735                 return -EOPNOTSUPP;
 736         }
 737
 738         if (event->cpu < 0) {
 739                 dev_warn(ccn->dev, "Can't provide per-task data!\n");
 740                 return -EOPNOTSUPP;
 741         }
 742         /*
 743          * Many perf core operations (eg. events rotation) operate on a
 744          * single CPU context. This is obvious for CPU PMUs, where one
 745          * expects the same sets of events being observed on all CPUs,
 746          * but can lead to issues for off-core PMUs, like CCN, where each
 747          * event could be theoretically assigned to a different CPU. To
 748          * mitigate this, we enforce CPU assignment to one, selected
 749          * processor (the one described in the "cpumask" attribute).
 750          */
 751         event->cpu = cpumask_first(&ccn->dt.cpu);
 752
 753         node_xp = CCN_CONFIG_NODE(event->attr.config);
 754         type = CCN_CONFIG_TYPE(event->attr.config);
 755         event_id = CCN_CONFIG_EVENT(event->attr.config);
 756
 757         /* Validate node/xp vs topology */
 758         switch (type) {
 759         case CCN_TYPE_XP:
 760                 if (node_xp >= ccn->num_xps) {
 761                         dev_warn(ccn->dev, "Invalid XP ID %d!\n", node_xp);
 762                         return -EINVAL;
 763                 }
 764                 break;
 765         case CCN_TYPE_CYCLES:
 766                 break;
 767         default:
 768                 if (node_xp >= ccn->num_nodes) {
 769                         dev_warn(ccn->dev, "Invalid node ID %d!\n", node_xp);
 770                         return -EINVAL;
 771                 }
 772                 if (!arm_ccn_pmu_type_eq(type, ccn->node[node_xp].type)) {
 773                         dev_warn(ccn->dev, "Invalid type 0x%x for node %d!\n",
 774                                         type, node_xp);
 775                         return -EINVAL;
 776                 }
 777                 break;
 778         }
 779
 780         /* Validate event ID vs available for the type */
 781         for (i = 0, valid = 0; i < ARRAY_SIZE(arm_ccn_pmu_events) && !valid;
 782                         i++) {
 783                 struct arm_ccn_pmu_event *e = &arm_ccn_pmu_events[i];
 784                 u32 port = CCN_CONFIG_PORT(event->attr.config);
 785                 u32 vc = CCN_CONFIG_VC(event->attr.config);
 786
 787                 if (!arm_ccn_pmu_type_eq(type, e->type))
 788                         continue;
 789                 if (event_id != e->event)
 790                         continue;
 791                 if (e->num_ports && port >= e->num_ports) {
 792                         dev_warn(ccn->dev, "Invalid port %d for node/XP %d!\n",
 793                                         port, node_xp);
 794                         return -EINVAL;
 795                 }
 796                 if (e->num_vcs && vc >= e->num_vcs) {
 797                         dev_warn(ccn->dev, "Invalid vc %d for node/XP %d!\n",
 798                                         vc, node_xp);
 799                         return -EINVAL;
 800                 }
 801                 valid = 1;
 802         }
 803         if (!valid) {
 804                 dev_warn(ccn->dev, "Invalid event 0x%x for node/XP %d!\n",
 805                                 event_id, node_xp);
 806                 return -EINVAL;
 807         }
 808
 809         /* Watchpoint-based event for a node is actually set on XP */
 810         if (event_id == CCN_EVENT_WATCHPOINT && type != CCN_TYPE_XP) {
 811                 u32 port;
 812
 813                 type = CCN_TYPE_XP;
 814                 port = arm_ccn_node_to_xp_port(node_xp);
 815                 node_xp = arm_ccn_node_to_xp(node_xp);
 816
 817                 arm_ccn_pmu_config_set(&event->attr.config,
 818                                 node_xp, type, port);
 819         }
 820
 821         /*
 822          * We must NOT create groups containing mixed PMUs, although software
 823          * events are acceptable (for example to create a CCN group
 824          * periodically read when a hrtimer aka cpu-clock leader triggers).
 825          */
 826         if (event->group_leader->pmu != event->pmu &&
 827                         !is_software_event(event->group_leader))
 828                 return -EINVAL;
 829
 830         list_for_each_entry(sibling, &event->group_leader->sibling_list,
 831                         group_entry)
 832                 if (sibling->pmu != event->pmu &&
 833                                 !is_software_event(sibling))
 834                         return -EINVAL;
 835
 836         return 0;
 837 }
 838
 839 static u64 arm_ccn_pmu_read_counter(struct arm_ccn *ccn, int idx)
 840 {
 841         u64 res;
 842
 843         if (idx == CCN_IDX_PMU_CYCLE_COUNTER) {
 844 #ifdef readq
 845                 res = readq(ccn->dt.base + CCN_DT_PMCCNTR);
 846 #else
 847                 /* 40 bit counter, can do snapshot and read in two parts */
 848                 writel(0x1, ccn->dt.base + CCN_DT_PMSR_REQ);
 849                 while (!(readl(ccn->dt.base + CCN_DT_PMSR) & 0x1))
 850                         ;
 851                 writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR);
 852                 res = readl(ccn->dt.base + CCN_DT_PMCCNTRSR + 4) & 0xff;
 853                 res <<= 32;
 854                 res |= readl(ccn->dt.base + CCN_DT_PMCCNTRSR);
 855 #endif
 856         } else {
 857                 res = readl(ccn->dt.base + CCN_DT_PMEVCNT(idx));
 858         }
 859
 860         return res;
 861 }
 862
 863 static void arm_ccn_pmu_event_update(struct perf_event *event)
 864 {
 865         struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
 866         struct hw_perf_event *hw = &event->hw;
 867         u64 prev_count, new_count, mask;
 868
 869         do {
 870                 prev_count = local64_read(&hw->prev_count);
 871                 new_count = arm_ccn_pmu_read_counter(ccn, hw->idx);
 872         } while (local64_xchg(&hw->prev_count, new_count) != prev_count);
 873
 874         mask = (1LLU << (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER ? 40 : 32)) - 1;
 875
 876         local64_add((new_count - prev_count) & mask, &event->count);
 877 }
 878
 879 static void arm_ccn_pmu_xp_dt_config(struct perf_event *event, int enable)
 880 {
 881         struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
 882         struct hw_perf_event *hw = &event->hw;
 883         struct arm_ccn_component *xp;
 884         u32 val, dt_cfg;
 885
 886         if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP)
 887                 xp = &ccn->xp[CCN_CONFIG_XP(event->attr.config)];
 888         else
 889                 xp = &ccn->xp[arm_ccn_node_to_xp(
 890                                 CCN_CONFIG_NODE(event->attr.config))];
 891
 892         if (enable)
 893                 dt_cfg = hw->event_base;
 894         else
 895                 dt_cfg = CCN_XP_DT_CONFIG__DT_CFG__PASS_THROUGH;
 896
 897         spin_lock(&ccn->dt.config_lock);
 898
 899         val = readl(xp->base + CCN_XP_DT_CONFIG);
 900         val &= ~(CCN_XP_DT_CONFIG__DT_CFG__MASK <<
 901                         CCN_XP_DT_CONFIG__DT_CFG__SHIFT(hw->idx));
 902         val |= dt_cfg << CCN_XP_DT_CONFIG__DT_CFG__SHIFT(hw->idx);
 903         writel(val, xp->base + CCN_XP_DT_CONFIG);
 904
 905         spin_unlock(&ccn->dt.config_lock);
 906 }
 907
 908 static void arm_ccn_pmu_event_start(struct perf_event *event, int flags)
 909 {
 910         struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
 911         struct hw_perf_event *hw = &event->hw;
 912
 913         local64_set(&event->hw.prev_count,
 914                         arm_ccn_pmu_read_counter(ccn, hw->idx));
 915         hw->state = 0;
 916
 917         /*
 918          * Pin the timer, so that the overflows are handled by the chosen
 919          * event->cpu (this is the same one as presented in "cpumask"
 920          * attribute).
 921          */
 922         if (!ccn->irq)
 923                 hrtimer_start(&ccn->dt.hrtimer, arm_ccn_pmu_timer_period(),
 924                                 HRTIMER_MODE_REL_PINNED);
 925
 926         /* Set the DT bus input, engaging the counter */
 927         arm_ccn_pmu_xp_dt_config(event, 1);
 928 }
 929
 930 static void arm_ccn_pmu_event_stop(struct perf_event *event, int flags)
 931 {
 932         struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
 933         struct hw_perf_event *hw = &event->hw;
 934         u64 timeout;
 935
 936         /* Disable counting, setting the DT bus to pass-through mode */
 937         arm_ccn_pmu_xp_dt_config(event, 0);
 938
 939         if (!ccn->irq)
 940                 hrtimer_cancel(&ccn->dt.hrtimer);
 941
 942         /* Let the DT bus drain */
 943         timeout = arm_ccn_pmu_read_counter(ccn, CCN_IDX_PMU_CYCLE_COUNTER) +
 944                         ccn->num_xps;
 945         while (arm_ccn_pmu_read_counter(ccn, CCN_IDX_PMU_CYCLE_COUNTER) <
 946                         timeout)
 947                 cpu_relax();
 948
 949         if (flags & PERF_EF_UPDATE)
 950                 arm_ccn_pmu_event_update(event);
 951
 952         hw->state |= PERF_HES_STOPPED;
 953 }
 954
 955 static void arm_ccn_pmu_xp_watchpoint_config(struct perf_event *event)
 956 {
 957         struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
 958         struct hw_perf_event *hw = &event->hw;
 959         struct arm_ccn_component *source =
 960                         ccn->dt.pmu_counters[hw->idx].source;
 961         unsigned long wp = hw->config_base;
 962         u32 val;
 963         u64 cmp_l = event->attr.config1;
 964         u64 cmp_h = event->attr.config2;
 965         u64 mask_l = ccn->dt.cmp_mask[CCN_CONFIG_MASK(event->attr.config)].l;
 966         u64 mask_h = ccn->dt.cmp_mask[CCN_CONFIG_MASK(event->attr.config)].h;
 967
 968         hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT(wp);
 969
 970         /* Direction (RX/TX), device (port) & virtual channel */
 971         val = readl(source->base + CCN_XP_DT_INTERFACE_SEL);
 972         val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__MASK <<
 973                         CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(wp));
 974         val |= CCN_CONFIG_DIR(event->attr.config) <<
 975                         CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(wp);
 976         val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__MASK <<
 977                         CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(wp));
 978         val |= CCN_CONFIG_PORT(event->attr.config) <<
 979                         CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(wp);
 980         val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__MASK <<
 981                         CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(wp));
 982         val |= CCN_CONFIG_VC(event->attr.config) <<
 983                         CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(wp);
 984         writel(val, source->base + CCN_XP_DT_INTERFACE_SEL);
 985
 986         /* Comparison values */
 987         writel(cmp_l & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_L(wp));
 988         writel((cmp_l >> 32) & 0xefffffff,
 989                         source->base + CCN_XP_DT_CMP_VAL_L(wp) + 4);
 990         writel(cmp_h & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_H(wp));
 991         writel((cmp_h >> 32) & 0x0fffffff,
 992                         source->base + CCN_XP_DT_CMP_VAL_H(wp) + 4);
 993
 994         /* Mask */
 995         writel(mask_l & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_L(wp));
 996         writel((mask_l >> 32) & 0xefffffff,
 997                         source->base + CCN_XP_DT_CMP_MASK_L(wp) + 4);
 998         writel(mask_h & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_H(wp));
 999         writel((mask_h >> 32) & 0x0fffffff,
1000                         source->base + CCN_XP_DT_CMP_MASK_H(wp) + 4);
1001 }
1002
1003 static void arm_ccn_pmu_xp_event_config(struct perf_event *event)
1004 {
1005         struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
1006         struct hw_perf_event *hw = &event->hw;
1007         struct arm_ccn_component *source =
1008                         ccn->dt.pmu_counters[hw->idx].source;
1009         u32 val, id;
1010
1011         hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(hw->config_base);
1012
1013         id = (CCN_CONFIG_VC(event->attr.config) << 4) |
1014                         (CCN_CONFIG_PORT(event->attr.config) << 3) |
1015                         (CCN_CONFIG_EVENT(event->attr.config) << 0);
1016
1017         val = readl(source->base + CCN_XP_PMU_EVENT_SEL);
1018         val &= ~(CCN_XP_PMU_EVENT_SEL__ID__MASK <<
1019                         CCN_XP_PMU_EVENT_SEL__ID__SHIFT(hw->config_base));
1020         val |= id << CCN_XP_PMU_EVENT_SEL__ID__SHIFT(hw->config_base);
1021         writel(val, source->base + CCN_XP_PMU_EVENT_SEL);
1022 }
1023
1024 static void arm_ccn_pmu_node_event_config(struct perf_event *event)
1025 {
1026         struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
1027         struct hw_perf_event *hw = &event->hw;
1028         struct arm_ccn_component *source =
1029                         ccn->dt.pmu_counters[hw->idx].source;
1030         u32 type = CCN_CONFIG_TYPE(event->attr.config);
1031         u32 val, port;
1032
1033         port = arm_ccn_node_to_xp_port(CCN_CONFIG_NODE(event->attr.config));
1034         hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__DEVICE_PMU_EVENT(port,
1035                         hw->config_base);
1036
1037         /* These *_event_sel regs should be identical, but let's make sure... */
1038         BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL != CCN_SBAS_PMU_EVENT_SEL);
1039         BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL != CCN_RNI_PMU_EVENT_SEL);
1040         BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(1) !=
1041                         CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(1));
1042         BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(1) !=
1043                         CCN_RNI_PMU_EVENT_SEL__ID__SHIFT(1));
1044         BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL__ID__MASK !=
1045                         CCN_SBAS_PMU_EVENT_SEL__ID__MASK);
1046         BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL__ID__MASK !=
1047                         CCN_RNI_PMU_EVENT_SEL__ID__MASK);
1048         if (WARN_ON(type != CCN_TYPE_HNF && type != CCN_TYPE_SBAS &&
1049                         !arm_ccn_pmu_type_eq(type, CCN_TYPE_RNI_3P)))
1050                 return;
1051
1052         /* Set the event id for the pre-allocated counter */
1053         val = readl(source->base + CCN_HNF_PMU_EVENT_SEL);
1054         val &= ~(CCN_HNF_PMU_EVENT_SEL__ID__MASK <<
1055                 CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(hw->config_base));
1056         val |= CCN_CONFIG_EVENT(event->attr.config) <<
1057                 CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(hw->config_base);
1058         writel(val, source->base + CCN_HNF_PMU_EVENT_SEL);
1059 }
1060
1061 static void arm_ccn_pmu_event_config(struct perf_event *event)
1062 {
1063         struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
1064         struct hw_perf_event *hw = &event->hw;
1065         u32 xp, offset, val;
1066
1067         /* Cycle counter requires no setup */
1068         if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER)
1069                 return;
1070
1071         if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP)
1072                 xp = CCN_CONFIG_XP(event->attr.config);
1073         else
1074                 xp = arm_ccn_node_to_xp(CCN_CONFIG_NODE(event->attr.config));
1075
1076         spin_lock(&ccn->dt.config_lock);
1077
1078         /* Set the DT bus "distance" register */
1079         offset = (hw->idx / 4) * 4;
1080         val = readl(ccn->dt.base + CCN_DT_ACTIVE_DSM + offset);
1081         val &= ~(CCN_DT_ACTIVE_DSM__DSM_ID__MASK <<
1082                         CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(hw->idx % 4));
1083         val |= xp << CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(hw->idx % 4);
1084         writel(val, ccn->dt.base + CCN_DT_ACTIVE_DSM + offset);
1085
1086         if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP) {
1087                 if (CCN_CONFIG_EVENT(event->attr.config) ==
1088                                 CCN_EVENT_WATCHPOINT)
1089                         arm_ccn_pmu_xp_watchpoint_config(event);
1090                 else
1091                         arm_ccn_pmu_xp_event_config(event);
1092         } else {
1093                 arm_ccn_pmu_node_event_config(event);
1094         }
1095
1096         spin_unlock(&ccn->dt.config_lock);
1097 }
1098
1099 static int arm_ccn_pmu_event_add(struct perf_event *event, int flags)
1100 {
1101         int err;
1102         struct hw_perf_event *hw = &event->hw;
1103
1104         err = arm_ccn_pmu_event_alloc(event);
1105         if (err)
1106                 return err;
1107
1108         arm_ccn_pmu_event_config(event);
1109
1110         hw->state = PERF_HES_STOPPED;
1111
1112         if (flags & PERF_EF_START)
1113                 arm_ccn_pmu_event_start(event, PERF_EF_UPDATE);
1114
1115         return 0;
1116 }
1117
1118 static void arm_ccn_pmu_event_del(struct perf_event *event, int flags)
1119 {
1120         arm_ccn_pmu_event_stop(event, PERF_EF_UPDATE);
1121
1122         arm_ccn_pmu_event_release(event);
1123 }
1124
1125 static void arm_ccn_pmu_event_read(struct perf_event *event)
1126 {
1127         arm_ccn_pmu_event_update(event);
1128 }
1129
1130 static irqreturn_t arm_ccn_pmu_overflow_handler(struct arm_ccn_dt *dt)
1131 {
1132         u32 pmovsr = readl(dt->base + CCN_DT_PMOVSR);
1133         int idx;
1134
1135         if (!pmovsr)
1136                 return IRQ_NONE;
1137
1138         writel(pmovsr, dt->base + CCN_DT_PMOVSR_CLR);
1139
1140         BUILD_BUG_ON(CCN_IDX_PMU_CYCLE_COUNTER != CCN_NUM_PMU_EVENT_COUNTERS);
1141
1142         for (idx = 0; idx < CCN_NUM_PMU_EVENT_COUNTERS + 1; idx++) {
1143                 struct perf_event *event = dt->pmu_counters[idx].event;
1144                 int overflowed = pmovsr & BIT(idx);
1145
1146                 WARN_ON_ONCE(overflowed && !event &&
1147                                 idx != CCN_IDX_PMU_CYCLE_COUNTER);
1148
1149                 if (!event || !overflowed)
1150                         continue;
1151
1152                 arm_ccn_pmu_event_update(event);
1153         }
1154
1155         return IRQ_HANDLED;
1156 }
1157
1158 static enum hrtimer_restart arm_ccn_pmu_timer_handler(struct hrtimer *hrtimer)
1159 {
1160         struct arm_ccn_dt *dt = container_of(hrtimer, struct arm_ccn_dt,
1161                         hrtimer);
1162         unsigned long flags;
1163
1164         local_irq_save(flags);
1165         arm_ccn_pmu_overflow_handler(dt);
1166         local_irq_restore(flags);
1167
1168         hrtimer_forward_now(hrtimer, arm_ccn_pmu_timer_period());
1169         return HRTIMER_RESTART;
1170 }
1171
1172
1173 static int arm_ccn_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node)
1174 {
1175         struct arm_ccn_dt *dt = hlist_entry_safe(node, struct arm_ccn_dt, node);
1176         struct arm_ccn *ccn = container_of(dt, struct arm_ccn, dt);
1177         unsigned int target;
1178
1179         if (!cpumask_test_and_clear_cpu(cpu, &dt->cpu))
1180                 return 0;
1181         target = cpumask_any_but(cpu_online_mask, cpu);
1182         if (target >= nr_cpu_ids)
1183                 return 0;
1184         perf_pmu_migrate_context(&dt->pmu, cpu, target);
1185         cpumask_set_cpu(target, &dt->cpu);
1186         if (ccn->irq)
1187                 WARN_ON(irq_set_affinity_hint(ccn->irq, &dt->cpu) != 0);
1188         return 0;
1189 }
1190
1191 static DEFINE_IDA(arm_ccn_pmu_ida);
1192
1193 static int arm_ccn_pmu_init(struct arm_ccn *ccn)
1194 {
1195         int i;
1196         char *name;
1197         int err;
1198
1199         /* Initialize DT subsystem */
1200         ccn->dt.base = ccn->base + CCN_REGION_SIZE;
1201         spin_lock_init(&ccn->dt.config_lock);
1202         writel(CCN_DT_PMOVSR_CLR__MASK, ccn->dt.base + CCN_DT_PMOVSR_CLR);
1203         writel(CCN_DT_CTL__DT_EN, ccn->dt.base + CCN_DT_CTL);
1204         writel(CCN_DT_PMCR__OVFL_INTR_EN | CCN_DT_PMCR__PMU_EN,
1205                         ccn->dt.base + CCN_DT_PMCR);
1206         writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR);
1207         for (i = 0; i < ccn->num_xps; i++) {
1208                 writel(0, ccn->xp[i].base + CCN_XP_DT_CONFIG);
1209                 writel((CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS <<
1210                                 CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(0)) |
1211                                 (CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS <<
1212                                 CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(1)) |
1213                                 CCN_XP_DT_CONTROL__DT_ENABLE,
1214                                 ccn->xp[i].base + CCN_XP_DT_CONTROL);
1215         }
1216         ccn->dt.cmp_mask[CCN_IDX_MASK_ANY].l = ~0;
1217         ccn->dt.cmp_mask[CCN_IDX_MASK_ANY].h = ~0;
1218         ccn->dt.cmp_mask[CCN_IDX_MASK_EXACT].l = 0;
1219         ccn->dt.cmp_mask[CCN_IDX_MASK_EXACT].h = 0;
1220         ccn->dt.cmp_mask[CCN_IDX_MASK_ORDER].l = ~0;
1221         ccn->dt.cmp_mask[CCN_IDX_MASK_ORDER].h = ~(0x1 << 15);
1222         ccn->dt.cmp_mask[CCN_IDX_MASK_OPCODE].l = ~0;
1223         ccn->dt.cmp_mask[CCN_IDX_MASK_OPCODE].h = ~(0x1f << 9);
1224
1225         /* Get a convenient /sys/event_source/devices/ name */
1226         ccn->dt.id = ida_simple_get(&arm_ccn_pmu_ida, 0, 0, GFP_KERNEL);
1227         if (ccn->dt.id == 0) {
1228                 name = "ccn";
1229         } else {
1230                 int len = snprintf(NULL, 0, "ccn_%d", ccn->dt.id);
1231
1232                 name = devm_kzalloc(ccn->dev, len + 1, GFP_KERNEL);
1233                 snprintf(name, len + 1, "ccn_%d", ccn->dt.id);
1234         }
1235
1236         /* Perf driver registration */
1237         ccn->dt.pmu = (struct pmu) {
1238                 .attr_groups = arm_ccn_pmu_attr_groups,
1239                 .task_ctx_nr = perf_invalid_context,
1240                 .event_init = arm_ccn_pmu_event_init,
1241                 .add = arm_ccn_pmu_event_add,
1242                 .del = arm_ccn_pmu_event_del,
1243                 .start = arm_ccn_pmu_event_start,
1244                 .stop = arm_ccn_pmu_event_stop,
1245                 .read = arm_ccn_pmu_event_read,
1246         };
1247
1248         /* No overflow interrupt? Have to use a timer instead. */
1249         if (!ccn->irq) {
1250                 dev_info(ccn->dev, "No access to interrupts, using timer.\n");
1251                 hrtimer_init(&ccn->dt.hrtimer, CLOCK_MONOTONIC,
1252                                 HRTIMER_MODE_REL);
1253                 ccn->dt.hrtimer.function = arm_ccn_pmu_timer_handler;
1254         }
1255
1256         /* Pick one CPU which we will use to collect data from CCN... */
1257         cpumask_set_cpu(smp_processor_id(), &ccn->dt.cpu);
1258
1259         /* Also make sure that the overflow interrupt is handled by this CPU */
1260         if (ccn->irq) {
1261                 err = irq_set_affinity_hint(ccn->irq, &ccn->dt.cpu);
1262                 if (err) {
1263                         dev_err(ccn->dev, "Failed to set interrupt affinity!\n");
1264                         goto error_set_affinity;
1265                 }
1266         }
1267
1268         err = perf_pmu_register(&ccn->dt.pmu, name, -1);
1269         if (err)
1270                 goto error_pmu_register;
1271
1272         cpuhp_state_add_instance_nocalls(CPUHP_AP_PERF_ARM_CCN_ONLINE,
1273                                          &ccn->dt.node);
1274         return 0;
1275
1276 error_pmu_register:
1277 error_set_affinity:
1278         ida_simple_remove(&arm_ccn_pmu_ida, ccn->dt.id);
1279         for (i = 0; i < ccn->num_xps; i++)
1280                 writel(0, ccn->xp[i].base + CCN_XP_DT_CONTROL);
1281         writel(0, ccn->dt.base + CCN_DT_PMCR);
1282         return err;
1283 }
1284
1285 static void arm_ccn_pmu_cleanup(struct arm_ccn *ccn)
1286 {
1287         int i;
1288
1289         cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_CCN_ONLINE,
1290                                             &ccn->dt.node);
1291         if (ccn->irq)
1292                 irq_set_affinity_hint(ccn->irq, NULL);
1293         for (i = 0; i < ccn->num_xps; i++)
1294                 writel(0, ccn->xp[i].base + CCN_XP_DT_CONTROL);
1295         writel(0, ccn->dt.base + CCN_DT_PMCR);
1296         perf_pmu_unregister(&ccn->dt.pmu);
1297         ida_simple_remove(&arm_ccn_pmu_ida, ccn->dt.id);
1298 }
1299
1300 static int arm_ccn_for_each_valid_region(struct arm_ccn *ccn,
1301                 int (*callback)(struct arm_ccn *ccn, int region,
1302                 void __iomem *base, u32 type, u32 id))
1303 {
1304         int region;
1305
1306         for (region = 0; region < CCN_NUM_REGIONS; region++) {
1307                 u32 val, type, id;
1308                 void __iomem *base;
1309                 int err;
1310
1311                 val = readl(ccn->base + CCN_MN_OLY_COMP_LIST_63_0 +
1312                                 4 * (region / 32));
1313                 if (!(val & (1 << (region % 32))))
1314                         continue;
1315
1316                 base = ccn->base + region * CCN_REGION_SIZE;
1317                 val = readl(base + CCN_ALL_OLY_ID);
1318                 type = (val >> CCN_ALL_OLY_ID__OLY_ID__SHIFT) &
1319                                 CCN_ALL_OLY_ID__OLY_ID__MASK;
1320                 id = (val >> CCN_ALL_OLY_ID__NODE_ID__SHIFT) &
1321                                 CCN_ALL_OLY_ID__NODE_ID__MASK;
1322
1323                 err = callback(ccn, region, base, type, id);
1324                 if (err)
1325                         return err;
1326         }
1327
1328         return 0;
1329 }
1330
1331 static int arm_ccn_get_nodes_num(struct arm_ccn *ccn, int region,
1332                 void __iomem *base, u32 type, u32 id)
1333 {
1334
1335         if (type == CCN_TYPE_XP && id >= ccn->num_xps)
1336                 ccn->num_xps = id + 1;
1337         else if (id >= ccn->num_nodes)
1338                 ccn->num_nodes = id + 1;
1339
1340         return 0;
1341 }
1342
1343 static int arm_ccn_init_nodes(struct arm_ccn *ccn, int region,
1344                 void __iomem *base, u32 type, u32 id)
1345 {
1346         struct arm_ccn_component *component;
1347
1348         dev_dbg(ccn->dev, "Region %d: id=%u, type=0x%02x\n", region, id, type);
1349
1350         switch (type) {
1351         case CCN_TYPE_MN:
1352         case CCN_TYPE_DT:
1353                 return 0;
1354         case CCN_TYPE_XP:
1355                 component = &ccn->xp[id];
1356                 break;
1357         case CCN_TYPE_SBSX:
1358                 ccn->sbsx_present = 1;
1359                 component = &ccn->node[id];
1360                 break;
1361         case CCN_TYPE_SBAS:
1362                 ccn->sbas_present = 1;
1363                 /* Fall-through */
1364         default:
1365                 component = &ccn->node[id];
1366                 break;
1367         }
1368
1369         component->base = base;
1370         component->type = type;
1371
1372         return 0;
1373 }
1374
1375
1376 static irqreturn_t arm_ccn_error_handler(struct arm_ccn *ccn,
1377                 const u32 *err_sig_val)
1378 {
1379         /* This should be really handled by firmware... */
1380         dev_err(ccn->dev, "Error reported in %08x%08x%08x%08x%08x%08x.\n",
1381                         err_sig_val[5], err_sig_val[4], err_sig_val[3],
1382                         err_sig_val[2], err_sig_val[1], err_sig_val[0]);
1383         dev_err(ccn->dev, "Disabling interrupt generation for all errors.\n");
1384         writel(CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLE,
1385                         ccn->base + CCN_MN_ERRINT_STATUS);
1386
1387         return IRQ_HANDLED;
1388 }
1389
1390
1391 static irqreturn_t arm_ccn_irq_handler(int irq, void *dev_id)
1392 {
1393         irqreturn_t res = IRQ_NONE;
1394         struct arm_ccn *ccn = dev_id;
1395         u32 err_sig_val[6];
1396         u32 err_or;
1397         int i;
1398
1399         /* PMU overflow is a special case */
1400         err_or = err_sig_val[0] = readl(ccn->base + CCN_MN_ERR_SIG_VAL_63_0);
1401         if (err_or & CCN_MN_ERR_SIG_VAL_63_0__DT) {
1402                 err_or &= ~CCN_MN_ERR_SIG_VAL_63_0__DT;
1403                 res = arm_ccn_pmu_overflow_handler(&ccn->dt);
1404         }
1405
1406         /* Have to read all err_sig_vals to clear them */
1407         for (i = 1; i < ARRAY_SIZE(err_sig_val); i++) {
1408                 err_sig_val[i] = readl(ccn->base +
1409                                 CCN_MN_ERR_SIG_VAL_63_0 + i * 4);
1410                 err_or |= err_sig_val[i];
1411         }
1412         if (err_or)
1413                 res |= arm_ccn_error_handler(ccn, err_sig_val);
1414
1415         if (res != IRQ_NONE)
1416                 writel(CCN_MN_ERRINT_STATUS__INTREQ__DESSERT,
1417                                 ccn->base + CCN_MN_ERRINT_STATUS);
1418
1419         return res;
1420 }
1421
1422
1423 static int arm_ccn_probe(struct platform_device *pdev)
1424 {
1425         struct arm_ccn *ccn;
1426         struct resource *res;
1427         unsigned int irq;
1428         int err;
1429
1430         ccn = devm_kzalloc(&pdev->dev, sizeof(*ccn), GFP_KERNEL);
1431         if (!ccn)
1432                 return -ENOMEM;
1433         ccn->dev = &pdev->dev;
1434         platform_set_drvdata(pdev, ccn);
1435
1436         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1437         if (!res)
1438                 return -EINVAL;
1439
1440         if (!devm_request_mem_region(ccn->dev, res->start,
1441                         resource_size(res), pdev->name))
1442                 return -EBUSY;
1443
1444         ccn->base = devm_ioremap(ccn->dev, res->start,
1445                                 resource_size(res));
1446         if (!ccn->base)
1447                 return -EFAULT;
1448
1449         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1450         if (!res)
1451                 return -EINVAL;
1452         irq = res->start;
1453
1454         /* Check if we can use the interrupt */
1455         writel(CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLE,
1456                         ccn->base + CCN_MN_ERRINT_STATUS);
1457         if (readl(ccn->base + CCN_MN_ERRINT_STATUS) &
1458                         CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLED) {
1459                 /* Can set 'disable' bits, so can acknowledge interrupts */
1460                 writel(CCN_MN_ERRINT_STATUS__PMU_EVENTS__ENABLE,
1461                                 ccn->base + CCN_MN_ERRINT_STATUS);
1462                 err = devm_request_irq(ccn->dev, irq, arm_ccn_irq_handler, 0,
1463                                 dev_name(ccn->dev), ccn);
1464                 if (err)
1465                         return err;
1466
1467                 ccn->irq = irq;
1468         }
1469
1470
1471         /* Build topology */
1472
1473         err = arm_ccn_for_each_valid_region(ccn, arm_ccn_get_nodes_num);
1474         if (err)
1475                 return err;
1476
1477         ccn->node = devm_kzalloc(ccn->dev, sizeof(*ccn->node) * ccn->num_nodes,
1478                 GFP_KERNEL);
1479         ccn->xp = devm_kzalloc(ccn->dev, sizeof(*ccn->node) * ccn->num_xps,
1480                 GFP_KERNEL);
1481         if (!ccn->node || !ccn->xp)
1482                 return -ENOMEM;
1483
1484         err = arm_ccn_for_each_valid_region(ccn, arm_ccn_init_nodes);
1485         if (err)
1486                 return err;
1487
1488         return arm_ccn_pmu_init(ccn);
1489 }
1490
1491 static int arm_ccn_remove(struct platform_device *pdev)
1492 {
1493         struct arm_ccn *ccn = platform_get_drvdata(pdev);
1494
1495         arm_ccn_pmu_cleanup(ccn);
1496
1497         return 0;
1498 }
1499
1500 static const struct of_device_id arm_ccn_match[] = {
1501         { .compatible = "arm,ccn-504", },
1502         {},
1503 };
1504
1505 static struct platform_driver arm_ccn_driver = {
1506         .driver = {
1507                 .name = "arm-ccn",
1508                 .of_match_table = arm_ccn_match,
1509         },
1510         .probe = arm_ccn_probe,
1511         .remove = arm_ccn_remove,
1512 };
1513
1514 static int __init arm_ccn_init(void)
1515 {
1516         int i, ret;
1517
1518         ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_CCN_ONLINE,
1519                                       "AP_PERF_ARM_CCN_ONLINE", NULL,
1520                                       arm_ccn_pmu_offline_cpu);
1521         if (ret)
1522                 return ret;
1523
1524         for (i = 0; i < ARRAY_SIZE(arm_ccn_pmu_events); i++)
1525                 arm_ccn_pmu_events_attrs[i] = &arm_ccn_pmu_events[i].attr.attr;
1526
1527         return platform_driver_register(&arm_ccn_driver);
1528 }
1529
1530 static void __exit arm_ccn_exit(void)
1531 {
1532         cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_CCN_ONLINE);
1533         platform_driver_unregister(&arm_ccn_driver);
1534 }
1535
1536 module_init(arm_ccn_init);
1537 module_exit(arm_ccn_exit);
1538
1539 MODULE_AUTHOR("Pawel Moll <pawel.moll@arm.com>");
1540 MODULE_LICENSE("GPL");