drivers/bus/omap_l3_noc.h

   1 /*
   2  * OMAP L3 Interconnect  error handling driver header
   3  *
   4  * Copyright (C) 2011-2014 Texas Instruments Incorporated - http://www.ti.com/
   5  *      Santosh Shilimkar <santosh.shilimkar@ti.com>
   6  *      sricharan <r.sricharan@ti.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  13  * kind, whether express or implied; without even the implied warranty
  14  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17 #ifndef __OMAP_L3_NOC_H
  18 #define __OMAP_L3_NOC_H
  19
  20 #define MAX_L3_MODULES                  3
  21 #define MAX_CLKDM_TARGETS               31
  22
  23 #define CLEAR_STDERR_LOG                (1 << 31)
  24 #define CUSTOM_ERROR                    0x2
  25 #define STANDARD_ERROR                  0x0
  26 #define INBAND_ERROR                    0x0
  27 #define L3_APPLICATION_ERROR            0x0
  28 #define L3_DEBUG_ERROR                  0x1
  29
  30 /* L3 TARG register offsets */
  31 #define L3_TARG_STDERRLOG_MAIN          0x48
  32 #define L3_TARG_STDERRLOG_HDR           0x4c
  33 #define L3_TARG_STDERRLOG_MSTADDR       0x50
  34 #define L3_TARG_STDERRLOG_INFO          0x58
  35 #define L3_TARG_STDERRLOG_SLVOFSLSB     0x5c
  36 #define L3_TARG_STDERRLOG_CINFO_INFO    0x64
  37 #define L3_TARG_STDERRLOG_CINFO_MSTADDR 0x68
  38 #define L3_TARG_STDERRLOG_CINFO_OPCODE  0x6c
  39 #define L3_FLAGMUX_REGERR0              0xc
  40 #define L3_FLAGMUX_MASK0                0x8
  41
  42 #define L3_TARGET_NOT_SUPPORTED         NULL
  43
  44 #define L3_BASE_IS_SUBMODULE            ((void __iomem *)(1 << 0))
  45
  46 static const char * const l3_transaction_type[] = {
  47         /* 0 0 0 */ "Idle",
  48         /* 0 0 1 */ "Write",
  49         /* 0 1 0 */ "Read",
  50         /* 0 1 1 */ "ReadEx",
  51         /* 1 0 0 */ "Read Link",
  52         /* 1 0 1 */ "Write Non-Posted",
  53         /* 1 1 0 */ "Write Conditional",
  54         /* 1 1 1 */ "Write Broadcast",
  55 };
  56
  57 /**
  58  * struct l3_masters_data - L3 Master information
  59  * @id:         ID of the L3 Master
  60  * @name:       master name
  61  */
  62 struct l3_masters_data {
  63         u32 id;
  64         char *name;
  65 };
  66
  67 /**
  68  * struct l3_target_data - L3 Target information
  69  * @offset:     Offset from base for L3 Target
  70  * @name:       Target name
  71  *
  72  * Target information is organized indexed by bit field definitions.
  73  */
  74 struct l3_target_data {
  75         u32 offset;
  76         char *name;
  77 };
  78
  79 /**
  80  * struct l3_flagmux_data - Flag Mux information
  81  * @offset:     offset from base for flagmux register
  82  * @l3_targ:    array indexed by flagmux index (bit offset) pointing to the
  83  *              target data. unsupported ones are marked with
  84  *              L3_TARGET_NOT_SUPPORTED
  85  * @num_targ_data: number of entries in target data
  86  * @mask_app_bits: ignore these from raw application irq status
  87  * @mask_dbg_bits: ignore these from raw debug irq status
  88  */
  89 struct l3_flagmux_data {
  90         u32 offset;
  91         struct l3_target_data *l3_targ;
  92         u8 num_targ_data;
  93         u32 mask_app_bits;
  94         u32 mask_dbg_bits;
  95 };
  96
  97
  98 /**
  99  * struct omap_l3 - Description of data relevant for L3 bus.
 100  * @dev:        device representing the bus (populated runtime)
 101  * @l3_base:    base addresses of modules (populated runtime if 0)
 102  *              if set to L3_BASE_IS_SUBMODULE, then uses previous
 103  *              module index as the base address
 104  * @l3_flag_mux: array containing flag mux data per module
 105  *               offset from corresponding module base indexed per
 106  *               module.
 107  * @num_modules: number of clock domains / modules.
 108  * @l3_masters: array pointing to master data containing name and register
 109  *              offset for the master.
 110  * @num_master: number of masters
 111  * @mst_addr_mask: Mask representing MSTADDR information of NTTP packet
 112  * @debug_irq:  irq number of the debug interrupt (populated runtime)
 113  * @app_irq:    irq number of the application interrupt (populated runtime)
 114  */
 115 struct omap_l3 {
 116         struct device *dev;
 117
 118         void __iomem *l3_base[MAX_L3_MODULES];
 119         struct l3_flagmux_data **l3_flagmux;
 120         int num_modules;
 121
 122         struct l3_masters_data *l3_masters;
 123         int num_masters;
 124         u32 mst_addr_mask;
 125
 126         int debug_irq;
 127         int app_irq;
 128 };
 129
 130 static struct l3_target_data omap_l3_target_data_clk1[] = {
 131         {0x100, "DMM1",},
 132         {0x200, "DMM2",},
 133         {0x300, "ABE",},
 134         {0x400, "L4CFG",},
 135         {0x600, "CLK2PWRDISC",},
 136         {0x0,   "HOSTCLK1",},
 137         {0x900, "L4WAKEUP",},
 138 };
 139
 140 static struct l3_flagmux_data omap_l3_flagmux_clk1 = {
 141         .offset = 0x500,
 142         .l3_targ = omap_l3_target_data_clk1,
 143         .num_targ_data = ARRAY_SIZE(omap_l3_target_data_clk1),
 144 };
 145
 146
 147 static struct l3_target_data omap_l3_target_data_clk2[] = {
 148         {0x500, "CORTEXM3",},
 149         {0x300, "DSS",},
 150         {0x100, "GPMC",},
 151         {0x400, "ISS",},
 152         {0x700, "IVAHD",},
 153         {0xD00, "AES1",},
 154         {0x900, "L4PER0",},
 155         {0x200, "OCMRAM",},
 156         {0x100, "GPMCsERROR",},
 157         {0x600, "SGX",},
 158         {0x800, "SL2",},
 159         {0x1600, "C2C",},
 160         {0x1100, "PWRDISCCLK1",},
 161         {0xF00, "SHA1",},
 162         {0xE00, "AES2",},
 163         {0xC00, "L4PER3",},
 164         {0xA00, "L4PER1",},
 165         {0xB00, "L4PER2",},
 166         {0x0,   "HOSTCLK2",},
 167         {0x1800, "CAL",},
 168         {0x1700, "LLI",},
 169 };
 170
 171 static struct l3_flagmux_data omap_l3_flagmux_clk2 = {
 172         .offset = 0x1000,
 173         .l3_targ = omap_l3_target_data_clk2,
 174         .num_targ_data = ARRAY_SIZE(omap_l3_target_data_clk2),
 175 };
 176
 177
 178 static struct l3_target_data omap_l3_target_data_clk3[] = {
 179         {0x0100, "EMUSS",},
 180         {0x0300, "DEBUG SOURCE",},
 181         {0x0,   "HOST CLK3",},
 182 };
 183
 184 static struct l3_flagmux_data omap_l3_flagmux_clk3 = {
 185         .offset = 0x0200,
 186         .l3_targ = omap_l3_target_data_clk3,
 187         .num_targ_data = ARRAY_SIZE(omap_l3_target_data_clk3),
 188 };
 189
 190 static struct l3_masters_data omap_l3_masters[] = {
 191         { 0x00, "MPU"},
 192         { 0x04, "CS_ADP"},
 193         { 0x05, "xxx"},
 194         { 0x08, "DSP"},
 195         { 0x0C, "IVAHD"},
 196         { 0x10, "ISS"},
 197         { 0x11, "DucatiM3"},
 198         { 0x12, "FaceDetect"},
 199         { 0x14, "SDMA_Rd"},
 200         { 0x15, "SDMA_Wr"},
 201         { 0x16, "xxx"},
 202         { 0x17, "xxx"},
 203         { 0x18, "SGX"},
 204         { 0x1C, "DSS"},
 205         { 0x20, "C2C"},
 206         { 0x22, "xxx"},
 207         { 0x23, "xxx"},
 208         { 0x24, "HSI"},
 209         { 0x28, "MMC1"},
 210         { 0x29, "MMC2"},
 211         { 0x2A, "MMC6"},
 212         { 0x2C, "UNIPRO1"},
 213         { 0x30, "USBHOSTHS"},
 214         { 0x31, "USBOTGHS"},
 215         { 0x32, "USBHOSTFS"}
 216 };
 217
 218 static struct l3_flagmux_data *omap_l3_flagmux[] = {
 219         &omap_l3_flagmux_clk1,
 220         &omap_l3_flagmux_clk2,
 221         &omap_l3_flagmux_clk3,
 222 };
 223
 224 static const struct omap_l3 omap_l3_data = {
 225         .l3_flagmux = omap_l3_flagmux,
 226         .num_modules = ARRAY_SIZE(omap_l3_flagmux),
 227         .l3_masters = omap_l3_masters,
 228         .num_masters = ARRAY_SIZE(omap_l3_masters),
 229         /* The 6 MSBs of register field used to distinguish initiator */
 230         .mst_addr_mask = 0xFC,
 231 };
 232
 233 /* DRA7 data */
 234 static struct l3_target_data dra_l3_target_data_clk1[] = {
 235         {0x2a00, "AES1",},
 236         {0x0200, "DMM_P1",},
 237         {0x0600, "DSP2_SDMA",},
 238         {0x0b00, "EVE2",},
 239         {0x1300, "DMM_P2",},
 240         {0x2c00, "AES2",},
 241         {0x0300, "DSP1_SDMA",},
 242         {0x0a00, "EVE1",},
 243         {0x0c00, "EVE3",},
 244         {0x0d00, "EVE4",},
 245         {0x2900, "DSS",},
 246         {0x0100, "GPMC",},
 247         {0x3700, "PCIE1",},
 248         {0x1600, "IVA_CONFIG",},
 249         {0x1800, "IVA_SL2IF",},
 250         {0x0500, "L4_CFG",},
 251         {0x1d00, "L4_WKUP",},
 252         {0x3800, "PCIE2",},
 253         {0x3300, "SHA2_1",},
 254         {0x1200, "GPU",},
 255         {0x1000, "IPU1",},
 256         {0x1100, "IPU2",},
 257         {0x2000, "TPCC_EDMA",},
 258         {0x2e00, "TPTC1_EDMA",},
 259         {0x2b00, "TPTC2_EDMA",},
 260         {0x0700, "VCP1",},
 261         {0x2500, "L4_PER2_P3",},
 262         {0x0e00, "L4_PER3_P3",},
 263         {0x2200, "MMU1",},
 264         {0x1400, "PRUSS1",},
 265         {0x1500, "PRUSS2"},
 266         {0x0800, "VCP1",},
 267 };
 268
 269 static struct l3_flagmux_data dra_l3_flagmux_clk1 = {
 270         .offset = 0x803500,
 271         .l3_targ = dra_l3_target_data_clk1,
 272         .num_targ_data = ARRAY_SIZE(dra_l3_target_data_clk1),
 273 };
 274
 275 static struct l3_target_data dra_l3_target_data_clk2[] = {
 276         {0x0,   "HOST CLK1",},
 277         {0x0,   "HOST CLK2",},
 278         {0xdead, L3_TARGET_NOT_SUPPORTED,},
 279         {0x3400, "SHA2_2",},
 280         {0x0900, "BB2D",},
 281         {0xdead, L3_TARGET_NOT_SUPPORTED,},
 282         {0x2100, "L4_PER1_P3",},
 283         {0x1c00, "L4_PER1_P1",},
 284         {0x1f00, "L4_PER1_P2",},
 285         {0x2300, "L4_PER2_P1",},
 286         {0x2400, "L4_PER2_P2",},
 287         {0x2600, "L4_PER3_P1",},
 288         {0x2700, "L4_PER3_P2",},
 289         {0x2f00, "MCASP1",},
 290         {0x3000, "MCASP2",},
 291         {0x3100, "MCASP3",},
 292         {0x2800, "MMU2",},
 293         {0x0f00, "OCMC_RAM1",},
 294         {0x1700, "OCMC_RAM2",},
 295         {0x1900, "OCMC_RAM3",},
 296         {0x1e00, "OCMC_ROM",},
 297         {0x3900, "QSPI",},
 298 };
 299
 300 static struct l3_flagmux_data dra_l3_flagmux_clk2 = {
 301         .offset = 0x803600,
 302         .l3_targ = dra_l3_target_data_clk2,
 303         .num_targ_data = ARRAY_SIZE(dra_l3_target_data_clk2),
 304 };
 305
 306 static struct l3_target_data dra_l3_target_data_clk3[] = {
 307         {0x0100, "L3_INSTR"},
 308         {0x0300, "DEBUGSS_CT_TBR"},
 309         {0x0,    "HOST CLK3"},
 310 };
 311
 312 static struct l3_flagmux_data dra_l3_flagmux_clk3 = {
 313         .offset = 0x200,
 314         .l3_targ = dra_l3_target_data_clk3,
 315         .num_targ_data = ARRAY_SIZE(dra_l3_target_data_clk3),
 316 };
 317
 318 static struct l3_masters_data dra_l3_masters[] = {
 319         { 0x0, "MPU" },
 320         { 0x4, "CS_DAP" },
 321         { 0x5, "IEEE1500_2_OCP" },
 322         { 0x8, "DSP1_MDMA" },
 323         { 0x9, "DSP1_CFG" },
 324         { 0xA, "DSP1_DMA" },
 325         { 0xB, "DSP2_MDMA" },
 326         { 0xC, "DSP2_CFG" },
 327         { 0xD, "DSP2_DMA" },
 328         { 0xE, "IVA" },
 329         { 0x10, "EVE1_P1" },
 330         { 0x11, "EVE2_P1" },
 331         { 0x12, "EVE3_P1" },
 332         { 0x13, "EVE4_P1" },
 333         { 0x14, "PRUSS1 PRU1" },
 334         { 0x15, "PRUSS1 PRU2" },
 335         { 0x16, "PRUSS2 PRU1" },
 336         { 0x17, "PRUSS2 PRU2" },
 337         { 0x18, "IPU1" },
 338         { 0x19, "IPU2" },
 339         { 0x1A, "SDMA" },
 340         { 0x1B, "CDMA" },
 341         { 0x1C, "TC1_EDMA" },
 342         { 0x1D, "TC2_EDMA" },
 343         { 0x20, "DSS" },
 344         { 0x21, "MMU1" },
 345         { 0x22, "PCIE1" },
 346         { 0x23, "MMU2" },
 347         { 0x24, "VIP1" },
 348         { 0x25, "VIP2" },
 349         { 0x26, "VIP3" },
 350         { 0x27, "VPE" },
 351         { 0x28, "GPU_P1" },
 352         { 0x29, "BB2D" },
 353         { 0x29, "GPU_P2" },
 354         { 0x2B, "GMAC_SW" },
 355         { 0x2C, "USB3" },
 356         { 0x2D, "USB2_SS" },
 357         { 0x2E, "USB2_ULPI_SS1" },
 358         { 0x2F, "USB2_ULPI_SS2" },
 359         { 0x30, "CSI2_1" },
 360         { 0x31, "CSI2_2" },
 361         { 0x33, "SATA" },
 362         { 0x34, "EVE1_P2" },
 363         { 0x35, "EVE2_P2" },
 364         { 0x36, "EVE3_P2" },
 365         { 0x37, "EVE4_P2" }
 366 };
 367
 368 static struct l3_flagmux_data *dra_l3_flagmux[] = {
 369         &dra_l3_flagmux_clk1,
 370         &dra_l3_flagmux_clk2,
 371         &dra_l3_flagmux_clk3,
 372 };
 373
 374 static const struct omap_l3 dra_l3_data = {
 375         .l3_base = { [1] = L3_BASE_IS_SUBMODULE },
 376         .l3_flagmux = dra_l3_flagmux,
 377         .num_modules = ARRAY_SIZE(dra_l3_flagmux),
 378         .l3_masters = dra_l3_masters,
 379         .num_masters = ARRAY_SIZE(dra_l3_masters),
 380         /* The 6 MSBs of register field used to distinguish initiator */
 381         .mst_addr_mask = 0xFC,
 382 };
 383
 384 /* AM4372 data */
 385 static struct l3_target_data am4372_l3_target_data_200f[] = {
 386         {0xf00,  "EMIF",},
 387         {0x1200, "DES",},
 388         {0x400,  "OCMCRAM",},
 389         {0x700,  "TPTC0",},
 390         {0x800,  "TPTC1",},
 391         {0x900,  "TPTC2"},
 392         {0xb00,  "TPCC",},
 393         {0xd00,  "DEBUGSS",},
 394         {0xdead, L3_TARGET_NOT_SUPPORTED,},
 395         {0x200,  "SHA",},
 396         {0xc00,  "SGX530",},
 397         {0x500,  "AES0",},
 398         {0xa00,  "L4_FAST",},
 399         {0x300,  "MPUSS_L2_RAM",},
 400         {0x100,  "ICSS",},
 401 };
 402
 403 static struct l3_flagmux_data am4372_l3_flagmux_200f = {
 404         .offset = 0x1000,
 405         .l3_targ = am4372_l3_target_data_200f,
 406         .num_targ_data = ARRAY_SIZE(am4372_l3_target_data_200f),
 407 };
 408
 409 static struct l3_target_data am4372_l3_target_data_100s[] = {
 410         {0x100, "L4_PER_0",},
 411         {0x200, "L4_PER_1",},
 412         {0x300, "L4_PER_2",},
 413         {0x400, "L4_PER_3",},
 414         {0x800, "McASP0",},
 415         {0x900, "McASP1",},
 416         {0xC00, "MMCHS2",},
 417         {0x700, "GPMC",},
 418         {0xD00, "L4_FW",},
 419         {0xdead, L3_TARGET_NOT_SUPPORTED,},
 420         {0x500, "ADCTSC",},
 421         {0xE00, "L4_WKUP",},
 422         {0xA00, "MAG_CARD",},
 423 };
 424
 425 static struct l3_flagmux_data am4372_l3_flagmux_100s = {
 426         .offset = 0x600,
 427         .l3_targ = am4372_l3_target_data_100s,
 428         .num_targ_data = ARRAY_SIZE(am4372_l3_target_data_100s),
 429 };
 430
 431 static struct l3_masters_data am4372_l3_masters[] = {
 432         { 0x0, "M1 (128-bit)"},
 433         { 0x1, "M2 (64-bit)"},
 434         { 0x4, "DAP"},
 435         { 0x5, "P1500"},
 436         { 0xC, "ICSS0"},
 437         { 0xD, "ICSS1"},
 438         { 0x14, "Wakeup Processor"},
 439         { 0x18, "TPTC0 Read"},
 440         { 0x19, "TPTC0 Write"},
 441         { 0x1A, "TPTC1 Read"},
 442         { 0x1B, "TPTC1 Write"},
 443         { 0x1C, "TPTC2 Read"},
 444         { 0x1D, "TPTC2 Write"},
 445         { 0x20, "SGX530"},
 446         { 0x21, "OCP WP Traffic Probe"},
 447         { 0x22, "OCP WP DMA Profiling"},
 448         { 0x23, "OCP WP Event Trace"},
 449         { 0x25, "DSS"},
 450         { 0x28, "Crypto DMA RD"},
 451         { 0x29, "Crypto DMA WR"},
 452         { 0x2C, "VPFE0"},
 453         { 0x2D, "VPFE1"},
 454         { 0x30, "GEMAC"},
 455         { 0x34, "USB0 RD"},
 456         { 0x35, "USB0 WR"},
 457         { 0x36, "USB1 RD"},
 458         { 0x37, "USB1 WR"},
 459 };
 460
 461 static struct l3_flagmux_data *am4372_l3_flagmux[] = {
 462         &am4372_l3_flagmux_200f,
 463         &am4372_l3_flagmux_100s,
 464 };
 465
 466 static const struct omap_l3 am4372_l3_data = {
 467         .l3_flagmux = am4372_l3_flagmux,
 468         .num_modules = ARRAY_SIZE(am4372_l3_flagmux),
 469         .l3_masters = am4372_l3_masters,
 470         .num_masters = ARRAY_SIZE(am4372_l3_masters),
 471         /* All 6 bits of register field used to distinguish initiator */
 472         .mst_addr_mask = 0x3F,
 473 };
 474
 475 #endif  /* __OMAP_L3_NOC_H */