drivers/char/agp/intel-agp.c

   1 /*
   2  * Intel AGPGART routines.
   3  */
   4
   5 #include <linux/module.h>
   6 #include <linux/pci.h>
   7 #include <linux/init.h>
   8 #include <linux/kernel.h>
   9 #include <linux/pagemap.h>
  10 #include <linux/agp_backend.h>
  11 #include "agp.h"
  12
  13 /*
  14  * If we have Intel graphics, we're not going to have anything other than
  15  * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
  16  * on the Intel IOMMU support (CONFIG_DMAR).
  17  * Only newer chipsets need to bother with this, of course.
  18  */
  19 #ifdef CONFIG_DMAR
  20 #define USE_PCI_DMA_API 1
  21 #endif
  22
  23 #define PCI_DEVICE_ID_INTEL_E7221_HB    0x2588
  24 #define PCI_DEVICE_ID_INTEL_E7221_IG    0x258a
  25 #define PCI_DEVICE_ID_INTEL_82946GZ_HB      0x2970
  26 #define PCI_DEVICE_ID_INTEL_82946GZ_IG      0x2972
  27 #define PCI_DEVICE_ID_INTEL_82G35_HB     0x2980
  28 #define PCI_DEVICE_ID_INTEL_82G35_IG     0x2982
  29 #define PCI_DEVICE_ID_INTEL_82965Q_HB       0x2990
  30 #define PCI_DEVICE_ID_INTEL_82965Q_IG       0x2992
  31 #define PCI_DEVICE_ID_INTEL_82965G_HB       0x29A0
  32 #define PCI_DEVICE_ID_INTEL_82965G_IG       0x29A2
  33 #define PCI_DEVICE_ID_INTEL_82965GM_HB      0x2A00
  34 #define PCI_DEVICE_ID_INTEL_82965GM_IG      0x2A02
  35 #define PCI_DEVICE_ID_INTEL_82965GME_HB     0x2A10
  36 #define PCI_DEVICE_ID_INTEL_82965GME_IG     0x2A12
  37 #define PCI_DEVICE_ID_INTEL_82945GME_HB     0x27AC
  38 #define PCI_DEVICE_ID_INTEL_82945GME_IG     0x27AE
  39 #define PCI_DEVICE_ID_INTEL_IGDGM_HB        0xA010
  40 #define PCI_DEVICE_ID_INTEL_IGDGM_IG        0xA011
  41 #define PCI_DEVICE_ID_INTEL_IGDG_HB         0xA000
  42 #define PCI_DEVICE_ID_INTEL_IGDG_IG         0xA001
  43 #define PCI_DEVICE_ID_INTEL_G33_HB          0x29C0
  44 #define PCI_DEVICE_ID_INTEL_G33_IG          0x29C2
  45 #define PCI_DEVICE_ID_INTEL_Q35_HB          0x29B0
  46 #define PCI_DEVICE_ID_INTEL_Q35_IG          0x29B2
  47 #define PCI_DEVICE_ID_INTEL_Q33_HB          0x29D0
  48 #define PCI_DEVICE_ID_INTEL_Q33_IG          0x29D2
  49 #define PCI_DEVICE_ID_INTEL_GM45_HB         0x2A40
  50 #define PCI_DEVICE_ID_INTEL_GM45_IG         0x2A42
  51 #define PCI_DEVICE_ID_INTEL_IGD_E_HB        0x2E00
  52 #define PCI_DEVICE_ID_INTEL_IGD_E_IG        0x2E02
  53 #define PCI_DEVICE_ID_INTEL_Q45_HB          0x2E10
  54 #define PCI_DEVICE_ID_INTEL_Q45_IG          0x2E12
  55 #define PCI_DEVICE_ID_INTEL_G45_HB          0x2E20
  56 #define PCI_DEVICE_ID_INTEL_G45_IG          0x2E22
  57 #define PCI_DEVICE_ID_INTEL_G41_HB          0x2E30
  58 #define PCI_DEVICE_ID_INTEL_G41_IG          0x2E32
  59 #define PCI_DEVICE_ID_INTEL_IGDNG_D_HB      0x0040
  60 #define PCI_DEVICE_ID_INTEL_IGDNG_D_IG      0x0042
  61 #define PCI_DEVICE_ID_INTEL_IGDNG_M_HB      0x0044
  62 #define PCI_DEVICE_ID_INTEL_IGDNG_MA_HB     0x0062
  63 #define PCI_DEVICE_ID_INTEL_IGDNG_M_IG      0x0046
  64
  65 /* cover 915 and 945 variants */
  66 #define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \
  67                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || \
  68                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || \
  69                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || \
  70                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || \
  71                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB)
  72
  73 #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
  74                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82G35_HB || \
  75                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
  76                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \
  77                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \
  78                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB)
  79
  80 #define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \
  81                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
  82                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB || \
  83                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDGM_HB || \
  84                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDG_HB)
  85
  86 #define IS_IGD (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDGM_HB || \
  87                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDG_HB)
  88
  89 #define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_E_HB || \
  90                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \
  91                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \
  92                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_GM45_HB || \
  93                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G41_HB || \
  94                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_D_HB || \
  95                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_M_HB || \
  96                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_MA_HB)
  97
  98 extern int agp_memory_reserved;
  99
 100
 101 /* Intel 815 register */
 102 #define INTEL_815_APCONT        0x51
 103 #define INTEL_815_ATTBASE_MASK  ~0x1FFFFFFF
 104
 105 /* Intel i820 registers */
 106 #define INTEL_I820_RDCR         0x51
 107 #define INTEL_I820_ERRSTS       0xc8
 108
 109 /* Intel i840 registers */
 110 #define INTEL_I840_MCHCFG       0x50
 111 #define INTEL_I840_ERRSTS       0xc8
 112
 113 /* Intel i850 registers */
 114 #define INTEL_I850_MCHCFG       0x50
 115 #define INTEL_I850_ERRSTS       0xc8
 116
 117 /* intel 915G registers */
 118 #define I915_GMADDR     0x18
 119 #define I915_MMADDR     0x10
 120 #define I915_PTEADDR    0x1C
 121 #define I915_GMCH_GMS_STOLEN_48M        (0x6 << 4)
 122 #define I915_GMCH_GMS_STOLEN_64M        (0x7 << 4)
 123 #define G33_GMCH_GMS_STOLEN_128M        (0x8 << 4)
 124 #define G33_GMCH_GMS_STOLEN_256M        (0x9 << 4)
 125 #define INTEL_GMCH_GMS_STOLEN_96M       (0xa << 4)
 126 #define INTEL_GMCH_GMS_STOLEN_160M      (0xb << 4)
 127 #define INTEL_GMCH_GMS_STOLEN_224M      (0xc << 4)
 128 #define INTEL_GMCH_GMS_STOLEN_352M      (0xd << 4)
 129
 130 #define I915_IFPADDR    0x60
 131
 132 /* Intel 965G registers */
 133 #define I965_MSAC 0x62
 134 #define I965_IFPADDR    0x70
 135
 136 /* Intel 7505 registers */
 137 #define INTEL_I7505_APSIZE      0x74
 138 #define INTEL_I7505_NCAPID      0x60
 139 #define INTEL_I7505_NISTAT      0x6c
 140 #define INTEL_I7505_ATTBASE     0x78
 141 #define INTEL_I7505_ERRSTS      0x42
 142 #define INTEL_I7505_AGPCTRL     0x70
 143 #define INTEL_I7505_MCHCFG      0x50
 144
 145 static const struct aper_size_info_fixed intel_i810_sizes[] =
 146 {
 147         {64, 16384, 4},
 148         /* The 32M mode still requires a 64k gatt */
 149         {32, 8192, 4}
 150 };
 151
 152 #define AGP_DCACHE_MEMORY       1
 153 #define AGP_PHYS_MEMORY         2
 154 #define INTEL_AGP_CACHED_MEMORY 3
 155
 156 static struct gatt_mask intel_i810_masks[] =
 157 {
 158         {.mask = I810_PTE_VALID, .type = 0},
 159         {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
 160         {.mask = I810_PTE_VALID, .type = 0},
 161         {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
 162          .type = INTEL_AGP_CACHED_MEMORY}
 163 };
 164
 165 static struct _intel_private {
 166         struct pci_dev *pcidev; /* device one */
 167         u8 __iomem *registers;
 168         u32 __iomem *gtt;               /* I915G */
 169         int num_dcache_entries;
 170         /* gtt_entries is the number of gtt entries that are already mapped
 171          * to stolen memory.  Stolen memory is larger than the memory mapped
 172          * through gtt_entries, as it includes some reserved space for the BIOS
 173          * popup and for the GTT.
 174          */
 175         int gtt_entries;                        /* i830+ */
 176         union {
 177                 void __iomem *i9xx_flush_page;
 178                 void *i8xx_flush_page;
 179         };
 180         struct page *i8xx_page;
 181         struct resource ifp_resource;
 182         int resource_valid;
 183 } intel_private;
 184
 185 #ifdef USE_PCI_DMA_API
 186 static int intel_agp_map_page(struct page *page, dma_addr_t *ret)
 187 {
 188         *ret = pci_map_page(intel_private.pcidev, page, 0,
 189                             PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 190         if (pci_dma_mapping_error(intel_private.pcidev, *ret))
 191                 return -EINVAL;
 192         return 0;
 193 }
 194
 195 static void intel_agp_unmap_page(struct page *page, dma_addr_t dma)
 196 {
 197         pci_unmap_page(intel_private.pcidev, dma,
 198                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 199 }
 200
 201 static void intel_agp_free_sglist(struct agp_memory *mem)
 202 {
 203         struct sg_table st;
 204
 205         st.sgl = mem->sg_list;
 206         st.orig_nents = st.nents = mem->page_count;
 207
 208         sg_free_table(&st);
 209
 210         mem->sg_list = NULL;
 211         mem->num_sg = 0;
 212 }
 213
 214 static int intel_agp_map_memory(struct agp_memory *mem)
 215 {
 216         struct sg_table st;
 217         struct scatterlist *sg;
 218         int i;
 219
 220         DBG("try mapping %lu pages\n", (unsigned long)mem->page_count);
 221
 222         if (sg_alloc_table(&st, mem->page_count, GFP_KERNEL))
 223                 return -ENOMEM;
 224
 225         mem->sg_list = sg = st.sgl;
 226
 227         for (i = 0 ; i < mem->page_count; i++, sg = sg_next(sg))
 228                 sg_set_page(sg, mem->pages[i], PAGE_SIZE, 0);
 229
 230         mem->num_sg = pci_map_sg(intel_private.pcidev, mem->sg_list,
 231                                  mem->page_count, PCI_DMA_BIDIRECTIONAL);
 232         if (unlikely(!mem->num_sg)) {
 233                 intel_agp_free_sglist(mem);
 234                 return -ENOMEM;
 235         }
 236         return 0;
 237 }
 238
 239 static void intel_agp_unmap_memory(struct agp_memory *mem)
 240 {
 241         DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count);
 242
 243         pci_unmap_sg(intel_private.pcidev, mem->sg_list,
 244                      mem->page_count, PCI_DMA_BIDIRECTIONAL);
 245         intel_agp_free_sglist(mem);
 246 }
 247
 248 static void intel_agp_insert_sg_entries(struct agp_memory *mem,
 249                                         off_t pg_start, int mask_type)
 250 {
 251         struct scatterlist *sg;
 252         int i, j;
 253
 254         j = pg_start;
 255
 256         WARN_ON(!mem->num_sg);
 257
 258         if (mem->num_sg == mem->page_count) {
 259                 for_each_sg(mem->sg_list, sg, mem->page_count, i) {
 260                         writel(agp_bridge->driver->mask_memory(agp_bridge,
 261                                         sg_dma_address(sg), mask_type),
 262                                         intel_private.gtt+j);
 263                         j++;
 264                 }
 265         } else {
 266                 /* sg may merge pages, but we have to seperate
 267                  * per-page addr for GTT */
 268                 unsigned int len, m;
 269
 270                 for_each_sg(mem->sg_list, sg, mem->num_sg, i) {
 271                         len = sg_dma_len(sg) / PAGE_SIZE;
 272                         for (m = 0; m < len; m++) {
 273                                 writel(agp_bridge->driver->mask_memory(agp_bridge,
 274                                                                        sg_dma_address(sg) + m * PAGE_SIZE,
 275                                                                        mask_type),
 276                                        intel_private.gtt+j);
 277                                 j++;
 278                         }
 279                 }
 280         }
 281         readl(intel_private.gtt+j-1);
 282 }
 283
 284 #else
 285
 286 static void intel_agp_insert_sg_entries(struct agp_memory *mem,
 287                                         off_t pg_start, int mask_type)
 288 {
 289         int i, j;
 290
 291         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 292                 writel(agp_bridge->driver->mask_memory(agp_bridge,
 293                                 page_to_phys(mem->pages[i]), mask_type),
 294                        intel_private.gtt+j);
 295         }
 296
 297         readl(intel_private.gtt+j-1);
 298 }
 299
 300 #endif
 301
 302 static int intel_i810_fetch_size(void)
 303 {
 304         u32 smram_miscc;
 305         struct aper_size_info_fixed *values;
 306
 307         pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc);
 308         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
 309
 310         if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
 311                 dev_warn(&agp_bridge->dev->dev, "i810 is disabled\n");
 312                 return 0;
 313         }
 314         if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
 315                 agp_bridge->previous_size =
 316                         agp_bridge->current_size = (void *) (values + 1);
 317                 agp_bridge->aperture_size_idx = 1;
 318                 return values[1].size;
 319         } else {
 320                 agp_bridge->previous_size =
 321                         agp_bridge->current_size = (void *) (values);
 322                 agp_bridge->aperture_size_idx = 0;
 323                 return values[0].size;
 324         }
 325
 326         return 0;
 327 }
 328
 329 static int intel_i810_configure(void)
 330 {
 331         struct aper_size_info_fixed *current_size;
 332         u32 temp;
 333         int i;
 334
 335         current_size = A_SIZE_FIX(agp_bridge->current_size);
 336
 337         if (!intel_private.registers) {
 338                 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
 339                 temp &= 0xfff80000;
 340
 341                 intel_private.registers = ioremap(temp, 128 * 4096);
 342                 if (!intel_private.registers) {
 343                         dev_err(&intel_private.pcidev->dev,
 344                                 "can't remap memory\n");
 345                         return -ENOMEM;
 346                 }
 347         }
 348
 349         if ((readl(intel_private.registers+I810_DRAM_CTL)
 350                 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
 351                 /* This will need to be dynamically assigned */
 352                 dev_info(&intel_private.pcidev->dev,
 353                          "detected 4MB dedicated video ram\n");
 354                 intel_private.num_dcache_entries = 1024;
 355         }
 356         pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
 357         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 358         writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
 359         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
 360
 361         if (agp_bridge->driver->needs_scratch_page) {
 362                 for (i = 0; i < current_size->num_entries; i++) {
 363                         writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 364                 }
 365                 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */
 366         }
 367         global_cache_flush();
 368         return 0;
 369 }
 370
 371 static void intel_i810_cleanup(void)
 372 {
 373         writel(0, intel_private.registers+I810_PGETBL_CTL);
 374         readl(intel_private.registers); /* PCI Posting. */
 375         iounmap(intel_private.registers);
 376 }
 377
 378 static void intel_i810_tlbflush(struct agp_memory *mem)
 379 {
 380         return;
 381 }
 382
 383 static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode)
 384 {
 385         return;
 386 }
 387
 388 /* Exists to support ARGB cursors */
 389 static struct page *i8xx_alloc_pages(void)
 390 {
 391         struct page *page;
 392
 393         page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
 394         if (page == NULL)
 395                 return NULL;
 396
 397         if (set_pages_uc(page, 4) < 0) {
 398                 set_pages_wb(page, 4);
 399                 __free_pages(page, 2);
 400                 return NULL;
 401         }
 402         get_page(page);
 403         atomic_inc(&agp_bridge->current_memory_agp);
 404         return page;
 405 }
 406
 407 static void i8xx_destroy_pages(struct page *page)
 408 {
 409         if (page == NULL)
 410                 return;
 411
 412         set_pages_wb(page, 4);
 413         put_page(page);
 414         __free_pages(page, 2);
 415         atomic_dec(&agp_bridge->current_memory_agp);
 416 }
 417
 418 static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge,
 419                                         int type)
 420 {
 421         if (type < AGP_USER_TYPES)
 422                 return type;
 423         else if (type == AGP_USER_CACHED_MEMORY)
 424                 return INTEL_AGP_CACHED_MEMORY;
 425         else
 426                 return 0;
 427 }
 428
 429 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
 430                                 int type)
 431 {
 432         int i, j, num_entries;
 433         void *temp;
 434         int ret = -EINVAL;
 435         int mask_type;
 436
 437         if (mem->page_count == 0)
 438                 goto out;
 439
 440         temp = agp_bridge->current_size;
 441         num_entries = A_SIZE_FIX(temp)->num_entries;
 442
 443         if ((pg_start + mem->page_count) > num_entries)
 444                 goto out_err;
 445
 446
 447         for (j = pg_start; j < (pg_start + mem->page_count); j++) {
 448                 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
 449                         ret = -EBUSY;
 450                         goto out_err;
 451                 }
 452         }
 453
 454         if (type != mem->type)
 455                 goto out_err;
 456
 457         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
 458
 459         switch (mask_type) {
 460         case AGP_DCACHE_MEMORY:
 461                 if (!mem->is_flushed)
 462                         global_cache_flush();
 463                 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
 464                         writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
 465                                intel_private.registers+I810_PTE_BASE+(i*4));
 466                 }
 467                 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
 468                 break;
 469         case AGP_PHYS_MEMORY:
 470         case AGP_NORMAL_MEMORY:
 471                 if (!mem->is_flushed)
 472                         global_cache_flush();
 473                 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 474                         writel(agp_bridge->driver->mask_memory(agp_bridge,
 475                                         page_to_phys(mem->pages[i]), mask_type),
 476                                intel_private.registers+I810_PTE_BASE+(j*4));
 477                 }
 478                 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
 479                 break;
 480         default:
 481                 goto out_err;
 482         }
 483
 484         agp_bridge->driver->tlb_flush(mem);
 485 out:
 486         ret = 0;
 487 out_err:
 488         mem->is_flushed = true;
 489         return ret;
 490 }
 491
 492 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
 493                                 int type)
 494 {
 495         int i;
 496
 497         if (mem->page_count == 0)
 498                 return 0;
 499
 500         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
 501                 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 502         }
 503         readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
 504
 505         agp_bridge->driver->tlb_flush(mem);
 506         return 0;
 507 }
 508
 509 /*
 510  * The i810/i830 requires a physical address to program its mouse
 511  * pointer into hardware.
 512  * However the Xserver still writes to it through the agp aperture.
 513  */
 514 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
 515 {
 516         struct agp_memory *new;
 517         struct page *page;
 518
 519         switch (pg_count) {
 520         case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge);
 521                 break;
 522         case 4:
 523                 /* kludge to get 4 physical pages for ARGB cursor */
 524                 page = i8xx_alloc_pages();
 525                 break;
 526         default:
 527                 return NULL;
 528         }
 529
 530         if (page == NULL)
 531                 return NULL;
 532
 533         new = agp_create_memory(pg_count);
 534         if (new == NULL)
 535                 return NULL;
 536
 537         new->pages[0] = page;
 538         if (pg_count == 4) {
 539                 /* kludge to get 4 physical pages for ARGB cursor */
 540                 new->pages[1] = new->pages[0] + 1;
 541                 new->pages[2] = new->pages[1] + 1;
 542                 new->pages[3] = new->pages[2] + 1;
 543         }
 544         new->page_count = pg_count;
 545         new->num_scratch_pages = pg_count;
 546         new->type = AGP_PHYS_MEMORY;
 547         new->physical = page_to_phys(new->pages[0]);
 548         return new;
 549 }
 550
 551 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
 552 {
 553         struct agp_memory *new;
 554
 555         if (type == AGP_DCACHE_MEMORY) {
 556                 if (pg_count != intel_private.num_dcache_entries)
 557                         return NULL;
 558
 559                 new = agp_create_memory(1);
 560                 if (new == NULL)
 561                         return NULL;
 562
 563                 new->type = AGP_DCACHE_MEMORY;
 564                 new->page_count = pg_count;
 565                 new->num_scratch_pages = 0;
 566                 agp_free_page_array(new);
 567                 return new;
 568         }
 569         if (type == AGP_PHYS_MEMORY)
 570                 return alloc_agpphysmem_i8xx(pg_count, type);
 571         return NULL;
 572 }
 573
 574 static void intel_i810_free_by_type(struct agp_memory *curr)
 575 {
 576         agp_free_key(curr->key);
 577         if (curr->type == AGP_PHYS_MEMORY) {
 578                 if (curr->page_count == 4)
 579                         i8xx_destroy_pages(curr->pages[0]);
 580                 else {
 581                         agp_bridge->driver->agp_destroy_page(curr->pages[0],
 582                                                              AGP_PAGE_DESTROY_UNMAP);
 583                         agp_bridge->driver->agp_destroy_page(curr->pages[0],
 584                                                              AGP_PAGE_DESTROY_FREE);
 585                 }
 586                 agp_free_page_array(curr);
 587         }
 588         kfree(curr);
 589 }
 590
 591 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
 592                                             dma_addr_t addr, int type)
 593 {
 594         /* Type checking must be done elsewhere */
 595         return addr | bridge->driver->masks[type].mask;
 596 }
 597
 598 static struct aper_size_info_fixed intel_i830_sizes[] =
 599 {
 600         {128, 32768, 5},
 601         /* The 64M mode still requires a 128k gatt */
 602         {64, 16384, 5},
 603         {256, 65536, 6},
 604         {512, 131072, 7},
 605 };
 606
 607 static void intel_i830_init_gtt_entries(void)
 608 {
 609         u16 gmch_ctrl;
 610         int gtt_entries;
 611         u8 rdct;
 612         int local = 0;
 613         static const int ddt[4] = { 0, 16, 32, 64 };
 614         int size; /* reserved space (in kb) at the top of stolen memory */
 615
 616         pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
 617
 618         if (IS_I965) {
 619                 u32 pgetbl_ctl;
 620                 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
 621
 622                 /* The 965 has a field telling us the size of the GTT,
 623                  * which may be larger than what is necessary to map the
 624                  * aperture.
 625                  */
 626                 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
 627                 case I965_PGETBL_SIZE_128KB:
 628                         size = 128;
 629                         break;
 630                 case I965_PGETBL_SIZE_256KB:
 631                         size = 256;
 632                         break;
 633                 case I965_PGETBL_SIZE_512KB:
 634                         size = 512;
 635                         break;
 636                 case I965_PGETBL_SIZE_1MB:
 637                         size = 1024;
 638                         break;
 639                 case I965_PGETBL_SIZE_2MB:
 640                         size = 2048;
 641                         break;
 642                 case I965_PGETBL_SIZE_1_5MB:
 643                         size = 1024 + 512;
 644                         break;
 645                 default:
 646                         dev_info(&intel_private.pcidev->dev,
 647                                  "unknown page table size, assuming 512KB\n");
 648                         size = 512;
 649                 }
 650                 size += 4; /* add in BIOS popup space */
 651         } else if (IS_G33 && !IS_IGD) {
 652         /* G33's GTT size defined in gmch_ctrl */
 653                 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) {
 654                 case G33_PGETBL_SIZE_1M:
 655                         size = 1024;
 656                         break;
 657                 case G33_PGETBL_SIZE_2M:
 658                         size = 2048;
 659                         break;
 660                 default:
 661                         dev_info(&agp_bridge->dev->dev,
 662                                  "unknown page table size 0x%x, assuming 512KB\n",
 663                                 (gmch_ctrl & G33_PGETBL_SIZE_MASK));
 664                         size = 512;
 665                 }
 666                 size += 4;
 667         } else if (IS_G4X || IS_IGD) {
 668                 /* On 4 series hardware, GTT stolen is separate from graphics
 669                  * stolen, ignore it in stolen gtt entries counting.  However,
 670                  * 4KB of the stolen memory doesn't get mapped to the GTT.
 671                  */
 672                 size = 4;
 673         } else {
 674                 /* On previous hardware, the GTT size was just what was
 675                  * required to map the aperture.
 676                  */
 677                 size = agp_bridge->driver->fetch_size() + 4;
 678         }
 679
 680         if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
 681             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
 682                 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
 683                 case I830_GMCH_GMS_STOLEN_512:
 684                         gtt_entries = KB(512) - KB(size);
 685                         break;
 686                 case I830_GMCH_GMS_STOLEN_1024:
 687                         gtt_entries = MB(1) - KB(size);
 688                         break;
 689                 case I830_GMCH_GMS_STOLEN_8192:
 690                         gtt_entries = MB(8) - KB(size);
 691                         break;
 692                 case I830_GMCH_GMS_LOCAL:
 693                         rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
 694                         gtt_entries = (I830_RDRAM_ND(rdct) + 1) *
 695                                         MB(ddt[I830_RDRAM_DDT(rdct)]);
 696                         local = 1;
 697                         break;
 698                 default:
 699                         gtt_entries = 0;
 700                         break;
 701                 }
 702         } else {
 703                 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
 704                 case I855_GMCH_GMS_STOLEN_1M:
 705                         gtt_entries = MB(1) - KB(size);
 706                         break;
 707                 case I855_GMCH_GMS_STOLEN_4M:
 708                         gtt_entries = MB(4) - KB(size);
 709                         break;
 710                 case I855_GMCH_GMS_STOLEN_8M:
 711                         gtt_entries = MB(8) - KB(size);
 712                         break;
 713                 case I855_GMCH_GMS_STOLEN_16M:
 714                         gtt_entries = MB(16) - KB(size);
 715                         break;
 716                 case I855_GMCH_GMS_STOLEN_32M:
 717                         gtt_entries = MB(32) - KB(size);
 718                         break;
 719                 case I915_GMCH_GMS_STOLEN_48M:
 720                         /* Check it's really I915G */
 721                         if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
 722                                 gtt_entries = MB(48) - KB(size);
 723                         else
 724                                 gtt_entries = 0;
 725                         break;
 726                 case I915_GMCH_GMS_STOLEN_64M:
 727                         /* Check it's really I915G */
 728                         if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
 729                                 gtt_entries = MB(64) - KB(size);
 730                         else
 731                                 gtt_entries = 0;
 732                         break;
 733                 case G33_GMCH_GMS_STOLEN_128M:
 734                         if (IS_G33 || IS_I965 || IS_G4X)
 735                                 gtt_entries = MB(128) - KB(size);
 736                         else
 737                                 gtt_entries = 0;
 738                         break;
 739                 case G33_GMCH_GMS_STOLEN_256M:
 740                         if (IS_G33 || IS_I965 || IS_G4X)
 741                                 gtt_entries = MB(256) - KB(size);
 742                         else
 743                                 gtt_entries = 0;
 744                         break;
 745                 case INTEL_GMCH_GMS_STOLEN_96M:
 746                         if (IS_I965 || IS_G4X)
 747                                 gtt_entries = MB(96) - KB(size);
 748                         else
 749                                 gtt_entries = 0;
 750                         break;
 751                 case INTEL_GMCH_GMS_STOLEN_160M:
 752                         if (IS_I965 || IS_G4X)
 753                                 gtt_entries = MB(160) - KB(size);
 754                         else
 755                                 gtt_entries = 0;
 756                         break;
 757                 case INTEL_GMCH_GMS_STOLEN_224M:
 758                         if (IS_I965 || IS_G4X)
 759                                 gtt_entries = MB(224) - KB(size);
 760                         else
 761                                 gtt_entries = 0;
 762                         break;
 763                 case INTEL_GMCH_GMS_STOLEN_352M:
 764                         if (IS_I965 || IS_G4X)
 765                                 gtt_entries = MB(352) - KB(size);
 766                         else
 767                                 gtt_entries = 0;
 768                         break;
 769                 default:
 770                         gtt_entries = 0;
 771                         break;
 772                 }
 773         }
 774         if (gtt_entries > 0) {
 775                 dev_info(&agp_bridge->dev->dev, "detected %dK %s memory\n",
 776                        gtt_entries / KB(1), local ? "local" : "stolen");
 777                 gtt_entries /= KB(4);
 778         } else {
 779                 dev_info(&agp_bridge->dev->dev,
 780                        "no pre-allocated video memory detected\n");
 781                 gtt_entries = 0;
 782         }
 783
 784         intel_private.gtt_entries = gtt_entries;
 785 }
 786
 787 static void intel_i830_fini_flush(void)
 788 {
 789         kunmap(intel_private.i8xx_page);
 790         intel_private.i8xx_flush_page = NULL;
 791         unmap_page_from_agp(intel_private.i8xx_page);
 792
 793         __free_page(intel_private.i8xx_page);
 794         intel_private.i8xx_page = NULL;
 795 }
 796
 797 static void intel_i830_setup_flush(void)
 798 {
 799         /* return if we've already set the flush mechanism up */
 800         if (intel_private.i8xx_page)
 801                 return;
 802
 803         intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32);
 804         if (!intel_private.i8xx_page)
 805                 return;
 806
 807         /* make page uncached */
 808         map_page_into_agp(intel_private.i8xx_page);
 809
 810         intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
 811         if (!intel_private.i8xx_flush_page)
 812                 intel_i830_fini_flush();
 813 }
 814
 815 static void intel_i830_chipset_flush(struct agp_bridge_data *bridge)
 816 {
 817         unsigned int *pg = intel_private.i8xx_flush_page;
 818         int i;
 819
 820         for (i = 0; i < 256; i += 2)
 821                 *(pg + i) = i;
 822
 823         wmb();
 824 }
 825
 826 /* The intel i830 automatically initializes the agp aperture during POST.
 827  * Use the memory already set aside for in the GTT.
 828  */
 829 static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
 830 {
 831         int page_order;
 832         struct aper_size_info_fixed *size;
 833         int num_entries;
 834         u32 temp;
 835
 836         size = agp_bridge->current_size;
 837         page_order = size->page_order;
 838         num_entries = size->num_entries;
 839         agp_bridge->gatt_table_real = NULL;
 840
 841         pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
 842         temp &= 0xfff80000;
 843
 844         intel_private.registers = ioremap(temp, 128 * 4096);
 845         if (!intel_private.registers)
 846                 return -ENOMEM;
 847
 848         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
 849         global_cache_flush();   /* FIXME: ?? */
 850
 851         /* we have to call this as early as possible after the MMIO base address is known */
 852         intel_i830_init_gtt_entries();
 853
 854         agp_bridge->gatt_table = NULL;
 855
 856         agp_bridge->gatt_bus_addr = temp;
 857
 858         return 0;
 859 }
 860
 861 /* Return the gatt table to a sane state. Use the top of stolen
 862  * memory for the GTT.
 863  */
 864 static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge)
 865 {
 866         return 0;
 867 }
 868
 869 static int intel_i830_fetch_size(void)
 870 {
 871         u16 gmch_ctrl;
 872         struct aper_size_info_fixed *values;
 873
 874         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
 875
 876         if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB &&
 877             agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) {
 878                 /* 855GM/852GM/865G has 128MB aperture size */
 879                 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
 880                 agp_bridge->aperture_size_idx = 0;
 881                 return values[0].size;
 882         }
 883
 884         pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
 885
 886         if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
 887                 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
 888                 agp_bridge->aperture_size_idx = 0;
 889                 return values[0].size;
 890         } else {
 891                 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1);
 892                 agp_bridge->aperture_size_idx = 1;
 893                 return values[1].size;
 894         }
 895
 896         return 0;
 897 }
 898
 899 static int intel_i830_configure(void)
 900 {
 901         struct aper_size_info_fixed *current_size;
 902         u32 temp;
 903         u16 gmch_ctrl;
 904         int i;
 905
 906         current_size = A_SIZE_FIX(agp_bridge->current_size);
 907
 908         pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
 909         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 910
 911         pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
 912         gmch_ctrl |= I830_GMCH_ENABLED;
 913         pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
 914
 915         writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
 916         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
 917
 918         if (agp_bridge->driver->needs_scratch_page) {
 919                 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
 920                         writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 921                 }
 922                 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI Posting. */
 923         }
 924
 925         global_cache_flush();
 926
 927         intel_i830_setup_flush();
 928         return 0;
 929 }
 930
 931 static void intel_i830_cleanup(void)
 932 {
 933         iounmap(intel_private.registers);
 934 }
 935
 936 static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start,
 937                                      int type)
 938 {
 939         int i, j, num_entries;
 940         void *temp;
 941         int ret = -EINVAL;
 942         int mask_type;
 943
 944         if (mem->page_count == 0)
 945                 goto out;
 946
 947         temp = agp_bridge->current_size;
 948         num_entries = A_SIZE_FIX(temp)->num_entries;
 949
 950         if (pg_start < intel_private.gtt_entries) {
 951                 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
 952                            "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n",
 953                            pg_start, intel_private.gtt_entries);
 954
 955                 dev_info(&intel_private.pcidev->dev,
 956                          "trying to insert into local/stolen memory\n");
 957                 goto out_err;
 958         }
 959
 960         if ((pg_start + mem->page_count) > num_entries)
 961                 goto out_err;
 962
 963         /* The i830 can't check the GTT for entries since its read only,
 964          * depend on the caller to make the correct offset decisions.
 965          */
 966
 967         if (type != mem->type)
 968                 goto out_err;
 969
 970         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
 971
 972         if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
 973             mask_type != INTEL_AGP_CACHED_MEMORY)
 974                 goto out_err;
 975
 976         if (!mem->is_flushed)
 977                 global_cache_flush();
 978
 979         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 980                 writel(agp_bridge->driver->mask_memory(agp_bridge,
 981                                 page_to_phys(mem->pages[i]), mask_type),
 982                        intel_private.registers+I810_PTE_BASE+(j*4));
 983         }
 984         readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
 985         agp_bridge->driver->tlb_flush(mem);
 986
 987 out:
 988         ret = 0;
 989 out_err:
 990         mem->is_flushed = true;
 991         return ret;
 992 }
 993
 994 static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start,
 995                                      int type)
 996 {
 997         int i;
 998
 999         if (mem->page_count == 0)
1000                 return 0;
1001
1002         if (pg_start < intel_private.gtt_entries) {
1003                 dev_info(&intel_private.pcidev->dev,
1004                          "trying to disable local/stolen memory\n");
1005                 return -EINVAL;
1006         }
1007
1008         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
1009                 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
1010         }
1011         readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
1012
1013         agp_bridge->driver->tlb_flush(mem);
1014         return 0;
1015 }
1016
1017 static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count, int type)
1018 {
1019         if (type == AGP_PHYS_MEMORY)
1020                 return alloc_agpphysmem_i8xx(pg_count, type);
1021         /* always return NULL for other allocation types for now */
1022         return NULL;
1023 }
1024
1025 static int intel_alloc_chipset_flush_resource(void)
1026 {
1027         int ret;
1028         ret = pci_bus_alloc_resource(agp_bridge->dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
1029                                      PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
1030                                      pcibios_align_resource, agp_bridge->dev);
1031
1032         return ret;
1033 }
1034
1035 static void intel_i915_setup_chipset_flush(void)
1036 {
1037         int ret;
1038         u32 temp;
1039
1040         pci_read_config_dword(agp_bridge->dev, I915_IFPADDR, &temp);
1041         if (!(temp & 0x1)) {
1042                 intel_alloc_chipset_flush_resource();
1043                 intel_private.resource_valid = 1;
1044                 pci_write_config_dword(agp_bridge->dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1045         } else {
1046                 temp &= ~1;
1047
1048                 intel_private.resource_valid = 1;
1049                 intel_private.ifp_resource.start = temp;
1050                 intel_private.ifp_resource.end = temp + PAGE_SIZE;
1051                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1052                 /* some BIOSes reserve this area in a pnp some don't */
1053                 if (ret)
1054                         intel_private.resource_valid = 0;
1055         }
1056 }
1057
1058 static void intel_i965_g33_setup_chipset_flush(void)
1059 {
1060         u32 temp_hi, temp_lo;
1061         int ret;
1062
1063         pci_read_config_dword(agp_bridge->dev, I965_IFPADDR + 4, &temp_hi);
1064         pci_read_config_dword(agp_bridge->dev, I965_IFPADDR, &temp_lo);
1065
1066         if (!(temp_lo & 0x1)) {
1067
1068                 intel_alloc_chipset_flush_resource();
1069
1070                 intel_private.resource_valid = 1;
1071                 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR + 4,
1072                         upper_32_bits(intel_private.ifp_resource.start));
1073                 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1074         } else {
1075                 u64 l64;
1076
1077                 temp_lo &= ~0x1;
1078                 l64 = ((u64)temp_hi << 32) | temp_lo;
1079
1080                 intel_private.resource_valid = 1;
1081                 intel_private.ifp_resource.start = l64;
1082                 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
1083                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1084                 /* some BIOSes reserve this area in a pnp some don't */
1085                 if (ret)
1086                         intel_private.resource_valid = 0;
1087         }
1088 }
1089
1090 static void intel_i9xx_setup_flush(void)
1091 {
1092         /* return if already configured */
1093         if (intel_private.ifp_resource.start)
1094                 return;
1095
1096         /* setup a resource for this object */
1097         intel_private.ifp_resource.name = "Intel Flush Page";
1098         intel_private.ifp_resource.flags = IORESOURCE_MEM;
1099
1100         /* Setup chipset flush for 915 */
1101         if (IS_I965 || IS_G33 || IS_G4X) {
1102                 intel_i965_g33_setup_chipset_flush();
1103         } else {
1104                 intel_i915_setup_chipset_flush();
1105         }
1106
1107         if (intel_private.ifp_resource.start) {
1108                 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
1109                 if (!intel_private.i9xx_flush_page)
1110                         dev_info(&intel_private.pcidev->dev, "can't ioremap flush page - no chipset flushing");
1111         }
1112 }
1113
1114 static int intel_i915_configure(void)
1115 {
1116         struct aper_size_info_fixed *current_size;
1117         u32 temp;
1118         u16 gmch_ctrl;
1119         int i;
1120
1121         current_size = A_SIZE_FIX(agp_bridge->current_size);
1122
1123         pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp);
1124
1125         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1126
1127         pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
1128         gmch_ctrl |= I830_GMCH_ENABLED;
1129         pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
1130
1131         writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
1132         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
1133
1134         if (agp_bridge->driver->needs_scratch_page) {
1135                 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
1136                         writel(agp_bridge->scratch_page, intel_private.gtt+i);
1137                 }
1138                 readl(intel_private.gtt+i-1);   /* PCI Posting. */
1139         }
1140
1141         global_cache_flush();
1142
1143         intel_i9xx_setup_flush();
1144
1145 #ifdef USE_PCI_DMA_API
1146         if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(36)))
1147                 dev_err(&intel_private.pcidev->dev,
1148                         "set gfx device dma mask 36bit failed!\n");
1149 #endif
1150
1151         return 0;
1152 }
1153
1154 static void intel_i915_cleanup(void)
1155 {
1156         if (intel_private.i9xx_flush_page)
1157                 iounmap(intel_private.i9xx_flush_page);
1158         if (intel_private.resource_valid)
1159                 release_resource(&intel_private.ifp_resource);
1160         intel_private.ifp_resource.start = 0;
1161         intel_private.resource_valid = 0;
1162         iounmap(intel_private.gtt);
1163         iounmap(intel_private.registers);
1164 }
1165
1166 static void intel_i915_chipset_flush(struct agp_bridge_data *bridge)
1167 {
1168         if (intel_private.i9xx_flush_page)
1169                 writel(1, intel_private.i9xx_flush_page);
1170 }
1171
1172 static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start,
1173                                      int type)
1174 {
1175         int num_entries;
1176         void *temp;
1177         int ret = -EINVAL;
1178         int mask_type;
1179
1180         if (mem->page_count == 0)
1181                 goto out;
1182
1183         temp = agp_bridge->current_size;
1184         num_entries = A_SIZE_FIX(temp)->num_entries;
1185
1186         if (pg_start < intel_private.gtt_entries) {
1187                 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
1188                            "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n",
1189                            pg_start, intel_private.gtt_entries);
1190
1191                 dev_info(&intel_private.pcidev->dev,
1192                          "trying to insert into local/stolen memory\n");
1193                 goto out_err;
1194         }
1195
1196         if ((pg_start + mem->page_count) > num_entries)
1197                 goto out_err;
1198
1199         /* The i915 can't check the GTT for entries since it's read only;
1200          * depend on the caller to make the correct offset decisions.
1201          */
1202
1203         if (type != mem->type)
1204                 goto out_err;
1205
1206         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
1207
1208         if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
1209             mask_type != INTEL_AGP_CACHED_MEMORY)
1210                 goto out_err;
1211
1212         if (!mem->is_flushed)
1213                 global_cache_flush();
1214
1215         intel_agp_insert_sg_entries(mem, pg_start, mask_type);
1216         agp_bridge->driver->tlb_flush(mem);
1217
1218  out:
1219         ret = 0;
1220  out_err:
1221         mem->is_flushed = true;
1222         return ret;
1223 }
1224
1225 static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start,
1226                                      int type)
1227 {
1228         int i;
1229
1230         if (mem->page_count == 0)
1231                 return 0;
1232
1233         if (pg_start < intel_private.gtt_entries) {
1234                 dev_info(&intel_private.pcidev->dev,
1235                          "trying to disable local/stolen memory\n");
1236                 return -EINVAL;
1237         }
1238
1239         for (i = pg_start; i < (mem->page_count + pg_start); i++)
1240                 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1241
1242         readl(intel_private.gtt+i-1);
1243
1244         agp_bridge->driver->tlb_flush(mem);
1245         return 0;
1246 }
1247
1248 /* Return the aperture size by just checking the resource length.  The effect
1249  * described in the spec of the MSAC registers is just changing of the
1250  * resource size.
1251  */
1252 static int intel_i9xx_fetch_size(void)
1253 {
1254         int num_sizes = ARRAY_SIZE(intel_i830_sizes);
1255         int aper_size; /* size in megabytes */
1256         int i;
1257
1258         aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1);
1259
1260         for (i = 0; i < num_sizes; i++) {
1261                 if (aper_size == intel_i830_sizes[i].size) {
1262                         agp_bridge->current_size = intel_i830_sizes + i;
1263                         agp_bridge->previous_size = agp_bridge->current_size;
1264                         return aper_size;
1265                 }
1266         }
1267
1268         return 0;
1269 }
1270
1271 /* The intel i915 automatically initializes the agp aperture during POST.
1272  * Use the memory already set aside for in the GTT.
1273  */
1274 static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
1275 {
1276         int page_order;
1277         struct aper_size_info_fixed *size;
1278         int num_entries;
1279         u32 temp, temp2;
1280         int gtt_map_size = 256 * 1024;
1281
1282         size = agp_bridge->current_size;
1283         page_order = size->page_order;
1284         num_entries = size->num_entries;
1285         agp_bridge->gatt_table_real = NULL;
1286
1287         pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1288         pci_read_config_dword(intel_private.pcidev, I915_PTEADDR, &temp2);
1289
1290         if (IS_G33)
1291             gtt_map_size = 1024 * 1024; /* 1M on G33 */
1292         intel_private.gtt = ioremap(temp2, gtt_map_size);
1293         if (!intel_private.gtt)
1294                 return -ENOMEM;
1295
1296         temp &= 0xfff80000;
1297
1298         intel_private.registers = ioremap(temp, 128 * 4096);
1299         if (!intel_private.registers) {
1300                 iounmap(intel_private.gtt);
1301                 return -ENOMEM;
1302         }
1303
1304         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1305         global_cache_flush();   /* FIXME: ? */
1306
1307         /* we have to call this as early as possible after the MMIO base address is known */
1308         intel_i830_init_gtt_entries();
1309
1310         agp_bridge->gatt_table = NULL;
1311
1312         agp_bridge->gatt_bus_addr = temp;
1313
1314         return 0;
1315 }
1316
1317 /*
1318  * The i965 supports 36-bit physical addresses, but to keep
1319  * the format of the GTT the same, the bits that don't fit
1320  * in a 32-bit word are shifted down to bits 4..7.
1321  *
1322  * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
1323  * is always zero on 32-bit architectures, so no need to make
1324  * this conditional.
1325  */
1326 static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
1327                                             dma_addr_t addr, int type)
1328 {
1329         /* Shift high bits down */
1330         addr |= (addr >> 28) & 0xf0;
1331
1332         /* Type checking must be done elsewhere */
1333         return addr | bridge->driver->masks[type].mask;
1334 }
1335
1336 static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
1337 {
1338         switch (agp_bridge->dev->device) {
1339         case PCI_DEVICE_ID_INTEL_GM45_HB:
1340         case PCI_DEVICE_ID_INTEL_IGD_E_HB:
1341         case PCI_DEVICE_ID_INTEL_Q45_HB:
1342         case PCI_DEVICE_ID_INTEL_G45_HB:
1343         case PCI_DEVICE_ID_INTEL_G41_HB:
1344         case PCI_DEVICE_ID_INTEL_IGDNG_D_HB:
1345         case PCI_DEVICE_ID_INTEL_IGDNG_M_HB:
1346         case PCI_DEVICE_ID_INTEL_IGDNG_MA_HB:
1347                 *gtt_offset = *gtt_size = MB(2);
1348                 break;
1349         default:
1350                 *gtt_offset = *gtt_size = KB(512);
1351         }
1352 }
1353
1354 /* The intel i965 automatically initializes the agp aperture during POST.
1355  * Use the memory already set aside for in the GTT.
1356  */
1357 static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
1358 {
1359         int page_order;
1360         struct aper_size_info_fixed *size;
1361         int num_entries;
1362         u32 temp;
1363         int gtt_offset, gtt_size;
1364
1365         size = agp_bridge->current_size;
1366         page_order = size->page_order;
1367         num_entries = size->num_entries;
1368         agp_bridge->gatt_table_real = NULL;
1369
1370         pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1371
1372         temp &= 0xfff00000;
1373
1374         intel_i965_get_gtt_range(&gtt_offset, &gtt_size);
1375
1376         intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size);
1377
1378         if (!intel_private.gtt)
1379                 return -ENOMEM;
1380
1381         intel_private.registers = ioremap(temp, 128 * 4096);
1382         if (!intel_private.registers) {
1383                 iounmap(intel_private.gtt);
1384                 return -ENOMEM;
1385         }
1386
1387         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1388         global_cache_flush();   /* FIXME: ? */
1389
1390         /* we have to call this as early as possible after the MMIO base address is known */
1391         intel_i830_init_gtt_entries();
1392
1393         agp_bridge->gatt_table = NULL;
1394
1395         agp_bridge->gatt_bus_addr = temp;
1396
1397         return 0;
1398 }
1399
1400
1401 static int intel_fetch_size(void)
1402 {
1403         int i;
1404         u16 temp;
1405         struct aper_size_info_16 *values;
1406
1407         pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
1408         values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
1409
1410         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1411                 if (temp == values[i].size_value) {
1412                         agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
1413                         agp_bridge->aperture_size_idx = i;
1414                         return values[i].size;
1415                 }
1416         }
1417
1418         return 0;
1419 }
1420
1421 static int __intel_8xx_fetch_size(u8 temp)
1422 {
1423         int i;
1424         struct aper_size_info_8 *values;
1425
1426         values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
1427
1428         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1429                 if (temp == values[i].size_value) {
1430                         agp_bridge->previous_size =
1431                                 agp_bridge->current_size = (void *) (values + i);
1432                         agp_bridge->aperture_size_idx = i;
1433                         return values[i].size;
1434                 }
1435         }
1436         return 0;
1437 }
1438
1439 static int intel_8xx_fetch_size(void)
1440 {
1441         u8 temp;
1442
1443         pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1444         return __intel_8xx_fetch_size(temp);
1445 }
1446
1447 static int intel_815_fetch_size(void)
1448 {
1449         u8 temp;
1450
1451         /* Intel 815 chipsets have a _weird_ APSIZE register with only
1452          * one non-reserved bit, so mask the others out ... */
1453         pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1454         temp &= (1 << 3);
1455
1456         return __intel_8xx_fetch_size(temp);
1457 }
1458
1459 static void intel_tlbflush(struct agp_memory *mem)
1460 {
1461         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
1462         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1463 }
1464
1465
1466 static void intel_8xx_tlbflush(struct agp_memory *mem)
1467 {
1468         u32 temp;
1469         pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1470         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
1471         pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1472         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
1473 }
1474
1475
1476 static void intel_cleanup(void)
1477 {
1478         u16 temp;
1479         struct aper_size_info_16 *previous_size;
1480
1481         previous_size = A_SIZE_16(agp_bridge->previous_size);
1482         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1483         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1484         pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1485 }
1486
1487
1488 static void intel_8xx_cleanup(void)
1489 {
1490         u16 temp;
1491         struct aper_size_info_8 *previous_size;
1492
1493         previous_size = A_SIZE_8(agp_bridge->previous_size);
1494         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1495         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1496         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1497 }
1498
1499
1500 static int intel_configure(void)
1501 {
1502         u32 temp;
1503         u16 temp2;
1504         struct aper_size_info_16 *current_size;
1505
1506         current_size = A_SIZE_16(agp_bridge->current_size);
1507
1508         /* aperture size */
1509         pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1510
1511         /* address to map to */
1512         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1513         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1514
1515         /* attbase - aperture base */
1516         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1517
1518         /* agpctrl */
1519         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1520
1521         /* paccfg/nbxcfg */
1522         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1523         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
1524                         (temp2 & ~(1 << 10)) | (1 << 9));
1525         /* clear any possible error conditions */
1526         pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
1527         return 0;
1528 }
1529
1530 static int intel_815_configure(void)
1531 {
1532         u32 temp, addr;
1533         u8 temp2;
1534         struct aper_size_info_8 *current_size;
1535
1536         /* attbase - aperture base */
1537         /* the Intel 815 chipset spec. says that bits 29-31 in the
1538         * ATTBASE register are reserved -> try not to write them */
1539         if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {
1540                 dev_emerg(&agp_bridge->dev->dev, "gatt bus addr too high");
1541                 return -EINVAL;
1542         }
1543
1544         current_size = A_SIZE_8(agp_bridge->current_size);
1545
1546         /* aperture size */
1547         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1548                         current_size->size_value);
1549
1550         /* address to map to */
1551         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1552         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1553
1554         pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
1555         addr &= INTEL_815_ATTBASE_MASK;
1556         addr |= agp_bridge->gatt_bus_addr;
1557         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
1558
1559         /* agpctrl */
1560         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1561
1562         /* apcont */
1563         pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
1564         pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
1565
1566         /* clear any possible error conditions */
1567         /* Oddness : this chipset seems to have no ERRSTS register ! */
1568         return 0;
1569 }
1570
1571 static void intel_820_tlbflush(struct agp_memory *mem)
1572 {
1573         return;
1574 }
1575
1576 static void intel_820_cleanup(void)
1577 {
1578         u8 temp;
1579         struct aper_size_info_8 *previous_size;
1580
1581         previous_size = A_SIZE_8(agp_bridge->previous_size);
1582         pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
1583         pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
1584                         temp & ~(1 << 1));
1585         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1586                         previous_size->size_value);
1587 }
1588
1589
1590 static int intel_820_configure(void)
1591 {
1592         u32 temp;
1593         u8 temp2;
1594         struct aper_size_info_8 *current_size;
1595
1596         current_size = A_SIZE_8(agp_bridge->current_size);
1597
1598         /* aperture size */
1599         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1600
1601         /* address to map to */
1602         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1603         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1604
1605         /* attbase - aperture base */
1606         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1607
1608         /* agpctrl */
1609         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1610
1611         /* global enable aperture access */
1612         /* This flag is not accessed through MCHCFG register as in */
1613         /* i850 chipset. */
1614         pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
1615         pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
1616         /* clear any possible AGP-related error conditions */
1617         pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
1618         return 0;
1619 }
1620
1621 static int intel_840_configure(void)
1622 {
1623         u32 temp;
1624         u16 temp2;
1625         struct aper_size_info_8 *current_size;
1626
1627         current_size = A_SIZE_8(agp_bridge->current_size);
1628
1629         /* aperture size */
1630         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1631
1632         /* address to map to */
1633         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1634         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1635
1636         /* attbase - aperture base */
1637         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1638
1639         /* agpctrl */
1640         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1641
1642         /* mcgcfg */
1643         pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
1644         pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
1645         /* clear any possible error conditions */
1646         pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
1647         return 0;
1648 }
1649
1650 static int intel_845_configure(void)
1651 {
1652         u32 temp;
1653         u8 temp2;
1654         struct aper_size_info_8 *current_size;
1655
1656         current_size = A_SIZE_8(agp_bridge->current_size);
1657
1658         /* aperture size */
1659         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1660
1661         if (agp_bridge->apbase_config != 0) {
1662                 pci_write_config_dword(agp_bridge->dev, AGP_APBASE,
1663                                        agp_bridge->apbase_config);
1664         } else {
1665                 /* address to map to */
1666                 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1667                 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1668                 agp_bridge->apbase_config = temp;
1669         }
1670
1671         /* attbase - aperture base */
1672         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1673
1674         /* agpctrl */
1675         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1676
1677         /* agpm */
1678         pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
1679         pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
1680         /* clear any possible error conditions */
1681         pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
1682
1683         intel_i830_setup_flush();
1684         return 0;
1685 }
1686
1687 static int intel_850_configure(void)
1688 {
1689         u32 temp;
1690         u16 temp2;
1691         struct aper_size_info_8 *current_size;
1692
1693         current_size = A_SIZE_8(agp_bridge->current_size);
1694
1695         /* aperture size */
1696         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1697
1698         /* address to map to */
1699         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1700         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1701
1702         /* attbase - aperture base */
1703         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1704
1705         /* agpctrl */
1706         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1707
1708         /* mcgcfg */
1709         pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
1710         pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
1711         /* clear any possible AGP-related error conditions */
1712         pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
1713         return 0;
1714 }
1715
1716 static int intel_860_configure(void)
1717 {
1718         u32 temp;
1719         u16 temp2;
1720         struct aper_size_info_8 *current_size;
1721
1722         current_size = A_SIZE_8(agp_bridge->current_size);
1723
1724         /* aperture size */
1725         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1726
1727         /* address to map to */
1728         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1729         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1730
1731         /* attbase - aperture base */
1732         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1733
1734         /* agpctrl */
1735         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1736
1737         /* mcgcfg */
1738         pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
1739         pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
1740         /* clear any possible AGP-related error conditions */
1741         pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
1742         return 0;
1743 }
1744
1745 static int intel_830mp_configure(void)
1746 {
1747         u32 temp;
1748         u16 temp2;
1749         struct aper_size_info_8 *current_size;
1750
1751         current_size = A_SIZE_8(agp_bridge->current_size);
1752
1753         /* aperture size */
1754         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1755
1756         /* address to map to */
1757         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1758         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1759
1760         /* attbase - aperture base */
1761         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1762
1763         /* agpctrl */
1764         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1765
1766         /* gmch */
1767         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1768         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
1769         /* clear any possible AGP-related error conditions */
1770         pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
1771         return 0;
1772 }
1773
1774 static int intel_7505_configure(void)
1775 {
1776         u32 temp;
1777         u16 temp2;
1778         struct aper_size_info_8 *current_size;
1779
1780         current_size = A_SIZE_8(agp_bridge->current_size);
1781
1782         /* aperture size */
1783         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1784
1785         /* address to map to */
1786         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1787         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1788
1789         /* attbase - aperture base */
1790         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1791
1792         /* agpctrl */
1793         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1794
1795         /* mchcfg */
1796         pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2);
1797         pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9));
1798
1799         return 0;
1800 }
1801
1802 /* Setup function */
1803 static const struct gatt_mask intel_generic_masks[] =
1804 {
1805         {.mask = 0x00000017, .type = 0}
1806 };
1807
1808 static const struct aper_size_info_8 intel_815_sizes[2] =
1809 {
1810         {64, 16384, 4, 0},
1811         {32, 8192, 3, 8},
1812 };
1813
1814 static const struct aper_size_info_8 intel_8xx_sizes[7] =
1815 {
1816         {256, 65536, 6, 0},
1817         {128, 32768, 5, 32},
1818         {64, 16384, 4, 48},
1819         {32, 8192, 3, 56},
1820         {16, 4096, 2, 60},
1821         {8, 2048, 1, 62},
1822         {4, 1024, 0, 63}
1823 };
1824
1825 static const struct aper_size_info_16 intel_generic_sizes[7] =
1826 {
1827         {256, 65536, 6, 0},
1828         {128, 32768, 5, 32},
1829         {64, 16384, 4, 48},
1830         {32, 8192, 3, 56},
1831         {16, 4096, 2, 60},
1832         {8, 2048, 1, 62},
1833         {4, 1024, 0, 63}
1834 };
1835
1836 static const struct aper_size_info_8 intel_830mp_sizes[4] =
1837 {
1838         {256, 65536, 6, 0},
1839         {128, 32768, 5, 32},
1840         {64, 16384, 4, 48},
1841         {32, 8192, 3, 56}
1842 };
1843
1844 static const struct agp_bridge_driver intel_generic_driver = {
1845         .owner                  = THIS_MODULE,
1846         .aperture_sizes         = intel_generic_sizes,
1847         .size_type              = U16_APER_SIZE,
1848         .num_aperture_sizes     = 7,
1849         .configure              = intel_configure,
1850         .fetch_size             = intel_fetch_size,
1851         .cleanup                = intel_cleanup,
1852         .tlb_flush              = intel_tlbflush,
1853         .mask_memory            = agp_generic_mask_memory,
1854         .masks                  = intel_generic_masks,
1855         .agp_enable             = agp_generic_enable,
1856         .cache_flush            = global_cache_flush,
1857         .create_gatt_table      = agp_generic_create_gatt_table,
1858         .free_gatt_table        = agp_generic_free_gatt_table,
1859         .insert_memory          = agp_generic_insert_memory,
1860         .remove_memory          = agp_generic_remove_memory,
1861         .alloc_by_type          = agp_generic_alloc_by_type,
1862         .free_by_type           = agp_generic_free_by_type,
1863         .agp_alloc_page         = agp_generic_alloc_page,
1864         .agp_alloc_pages        = agp_generic_alloc_pages,
1865         .agp_destroy_page       = agp_generic_destroy_page,
1866         .agp_destroy_pages      = agp_generic_destroy_pages,
1867         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1868 };
1869
1870 static const struct agp_bridge_driver intel_810_driver = {
1871         .owner                  = THIS_MODULE,
1872         .aperture_sizes         = intel_i810_sizes,
1873         .size_type              = FIXED_APER_SIZE,
1874         .num_aperture_sizes     = 2,
1875         .needs_scratch_page     = true,
1876         .configure              = intel_i810_configure,
1877         .fetch_size             = intel_i810_fetch_size,
1878         .cleanup                = intel_i810_cleanup,
1879         .tlb_flush              = intel_i810_tlbflush,
1880         .mask_memory            = intel_i810_mask_memory,
1881         .masks                  = intel_i810_masks,
1882         .agp_enable             = intel_i810_agp_enable,
1883         .cache_flush            = global_cache_flush,
1884         .create_gatt_table      = agp_generic_create_gatt_table,
1885         .free_gatt_table        = agp_generic_free_gatt_table,
1886         .insert_memory          = intel_i810_insert_entries,
1887         .remove_memory          = intel_i810_remove_entries,
1888         .alloc_by_type          = intel_i810_alloc_by_type,
1889         .free_by_type           = intel_i810_free_by_type,
1890         .agp_alloc_page         = agp_generic_alloc_page,
1891         .agp_alloc_pages        = agp_generic_alloc_pages,
1892         .agp_destroy_page       = agp_generic_destroy_page,
1893         .agp_destroy_pages      = agp_generic_destroy_pages,
1894         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1895 };
1896
1897 static const struct agp_bridge_driver intel_815_driver = {
1898         .owner                  = THIS_MODULE,
1899         .aperture_sizes         = intel_815_sizes,
1900         .size_type              = U8_APER_SIZE,
1901         .num_aperture_sizes     = 2,
1902         .configure              = intel_815_configure,
1903         .fetch_size             = intel_815_fetch_size,
1904         .cleanup                = intel_8xx_cleanup,
1905         .tlb_flush              = intel_8xx_tlbflush,
1906         .mask_memory            = agp_generic_mask_memory,
1907         .masks                  = intel_generic_masks,
1908         .agp_enable             = agp_generic_enable,
1909         .cache_flush            = global_cache_flush,
1910         .create_gatt_table      = agp_generic_create_gatt_table,
1911         .free_gatt_table        = agp_generic_free_gatt_table,
1912         .insert_memory          = agp_generic_insert_memory,
1913         .remove_memory          = agp_generic_remove_memory,
1914         .alloc_by_type          = agp_generic_alloc_by_type,
1915         .free_by_type           = agp_generic_free_by_type,
1916         .agp_alloc_page         = agp_generic_alloc_page,
1917         .agp_alloc_pages        = agp_generic_alloc_pages,
1918         .agp_destroy_page       = agp_generic_destroy_page,
1919         .agp_destroy_pages      = agp_generic_destroy_pages,
1920         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1921 };
1922
1923 static const struct agp_bridge_driver intel_830_driver = {
1924         .owner                  = THIS_MODULE,
1925         .aperture_sizes         = intel_i830_sizes,
1926         .size_type              = FIXED_APER_SIZE,
1927         .num_aperture_sizes     = 4,
1928         .needs_scratch_page     = true,
1929         .configure              = intel_i830_configure,
1930         .fetch_size             = intel_i830_fetch_size,
1931         .cleanup                = intel_i830_cleanup,
1932         .tlb_flush              = intel_i810_tlbflush,
1933         .mask_memory            = intel_i810_mask_memory,
1934         .masks                  = intel_i810_masks,
1935         .agp_enable             = intel_i810_agp_enable,
1936         .cache_flush            = global_cache_flush,
1937         .create_gatt_table      = intel_i830_create_gatt_table,
1938         .free_gatt_table        = intel_i830_free_gatt_table,
1939         .insert_memory          = intel_i830_insert_entries,
1940         .remove_memory          = intel_i830_remove_entries,
1941         .alloc_by_type          = intel_i830_alloc_by_type,
1942         .free_by_type           = intel_i810_free_by_type,
1943         .agp_alloc_page         = agp_generic_alloc_page,
1944         .agp_alloc_pages        = agp_generic_alloc_pages,
1945         .agp_destroy_page       = agp_generic_destroy_page,
1946         .agp_destroy_pages      = agp_generic_destroy_pages,
1947         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1948         .chipset_flush          = intel_i830_chipset_flush,
1949 };
1950
1951 static const struct agp_bridge_driver intel_820_driver = {
1952         .owner                  = THIS_MODULE,
1953         .aperture_sizes         = intel_8xx_sizes,
1954         .size_type              = U8_APER_SIZE,
1955         .num_aperture_sizes     = 7,
1956         .configure              = intel_820_configure,
1957         .fetch_size             = intel_8xx_fetch_size,
1958         .cleanup                = intel_820_cleanup,
1959         .tlb_flush              = intel_820_tlbflush,
1960         .mask_memory            = agp_generic_mask_memory,
1961         .masks                  = intel_generic_masks,
1962         .agp_enable             = agp_generic_enable,
1963         .cache_flush            = global_cache_flush,
1964         .create_gatt_table      = agp_generic_create_gatt_table,
1965         .free_gatt_table        = agp_generic_free_gatt_table,
1966         .insert_memory          = agp_generic_insert_memory,
1967         .remove_memory          = agp_generic_remove_memory,
1968         .alloc_by_type          = agp_generic_alloc_by_type,
1969         .free_by_type           = agp_generic_free_by_type,
1970         .agp_alloc_page         = agp_generic_alloc_page,
1971         .agp_alloc_pages        = agp_generic_alloc_pages,
1972         .agp_destroy_page       = agp_generic_destroy_page,
1973         .agp_destroy_pages      = agp_generic_destroy_pages,
1974         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1975 };
1976
1977 static const struct agp_bridge_driver intel_830mp_driver = {
1978         .owner                  = THIS_MODULE,
1979         .aperture_sizes         = intel_830mp_sizes,
1980         .size_type              = U8_APER_SIZE,
1981         .num_aperture_sizes     = 4,
1982         .configure              = intel_830mp_configure,
1983         .fetch_size             = intel_8xx_fetch_size,
1984         .cleanup                = intel_8xx_cleanup,
1985         .tlb_flush              = intel_8xx_tlbflush,
1986         .mask_memory            = agp_generic_mask_memory,
1987         .masks                  = intel_generic_masks,
1988         .agp_enable             = agp_generic_enable,
1989         .cache_flush            = global_cache_flush,
1990         .create_gatt_table      = agp_generic_create_gatt_table,
1991         .free_gatt_table        = agp_generic_free_gatt_table,
1992         .insert_memory          = agp_generic_insert_memory,
1993         .remove_memory          = agp_generic_remove_memory,
1994         .alloc_by_type          = agp_generic_alloc_by_type,
1995         .free_by_type           = agp_generic_free_by_type,
1996         .agp_alloc_page         = agp_generic_alloc_page,
1997         .agp_alloc_pages        = agp_generic_alloc_pages,
1998         .agp_destroy_page       = agp_generic_destroy_page,
1999         .agp_destroy_pages      = agp_generic_destroy_pages,
2000         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
2001 };
2002
2003 static const struct agp_bridge_driver intel_840_driver = {
2004         .owner                  = THIS_MODULE,
2005         .aperture_sizes         = intel_8xx_sizes,
2006         .size_type              = U8_APER_SIZE,
2007         .num_aperture_sizes     = 7,
2008         .configure              = intel_840_configure,
2009         .fetch_size             = intel_8xx_fetch_size,
2010         .cleanup                = intel_8xx_cleanup,
2011         .tlb_flush              = intel_8xx_tlbflush,
2012         .mask_memory            = agp_generic_mask_memory,
2013         .masks                  = intel_generic_masks,
2014         .agp_enable             = agp_generic_enable,
2015         .cache_flush            = global_cache_flush,
2016         .create_gatt_table      = agp_generic_create_gatt_table,
2017         .free_gatt_table        = agp_generic_free_gatt_table,
2018         .insert_memory          = agp_generic_insert_memory,
2019         .remove_memory          = agp_generic_remove_memory,
2020         .alloc_by_type          = agp_generic_alloc_by_type,
2021         .free_by_type           = agp_generic_free_by_type,
2022         .agp_alloc_page         = agp_generic_alloc_page,
2023         .agp_alloc_pages        = agp_generic_alloc_pages,
2024         .agp_destroy_page       = agp_generic_destroy_page,
2025         .agp_destroy_pages      = agp_generic_destroy_pages,
2026         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
2027 };
2028
2029 static const struct agp_bridge_driver intel_845_driver = {
2030         .owner                  = THIS_MODULE,
2031         .aperture_sizes         = intel_8xx_sizes,
2032         .size_type              = U8_APER_SIZE,
2033         .num_aperture_sizes     = 7,
2034         .configure              = intel_845_configure,
2035         .fetch_size             = intel_8xx_fetch_size,
2036         .cleanup                = intel_8xx_cleanup,
2037         .tlb_flush              = intel_8xx_tlbflush,
2038         .mask_memory            = agp_generic_mask_memory,
2039         .masks                  = intel_generic_masks,
2040         .agp_enable             = agp_generic_enable,
2041         .cache_flush            = global_cache_flush,
2042         .create_gatt_table      = agp_generic_create_gatt_table,
2043         .free_gatt_table        = agp_generic_free_gatt_table,
2044         .insert_memory          = agp_generic_insert_memory,
2045         .remove_memory          = agp_generic_remove_memory,
2046         .alloc_by_type          = agp_generic_alloc_by_type,
2047         .free_by_type           = agp_generic_free_by_type,
2048         .agp_alloc_page         = agp_generic_alloc_page,
2049         .agp_alloc_pages        = agp_generic_alloc_pages,
2050         .agp_destroy_page       = agp_generic_destroy_page,
2051         .agp_destroy_pages      = agp_generic_destroy_pages,
2052         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
2053         .chipset_flush          = intel_i830_chipset_flush,
2054 };
2055
2056 static const struct agp_bridge_driver intel_850_driver = {
2057         .owner                  = THIS_MODULE,
2058         .aperture_sizes         = intel_8xx_sizes,
2059         .size_type              = U8_APER_SIZE,
2060         .num_aperture_sizes     = 7,
2061         .configure              = intel_850_configure,
2062         .fetch_size             = intel_8xx_fetch_size,
2063         .cleanup                = intel_8xx_cleanup,
2064         .tlb_flush              = intel_8xx_tlbflush,
2065         .mask_memory            = agp_generic_mask_memory,
2066         .masks                  = intel_generic_masks,
2067         .agp_enable             = agp_generic_enable,
2068         .cache_flush            = global_cache_flush,
2069         .create_gatt_table      = agp_generic_create_gatt_table,
2070         .free_gatt_table        = agp_generic_free_gatt_table,
2071         .insert_memory          = agp_generic_insert_memory,
2072         .remove_memory          = agp_generic_remove_memory,
2073         .alloc_by_type          = agp_generic_alloc_by_type,
2074         .free_by_type           = agp_generic_free_by_type,
2075         .agp_alloc_page         = agp_generic_alloc_page,
2076         .agp_alloc_pages        = agp_generic_alloc_pages,
2077         .agp_destroy_page       = agp_generic_destroy_page,
2078         .agp_destroy_pages      = agp_generic_destroy_pages,
2079         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
2080 };
2081
2082 static const struct agp_bridge_driver intel_860_driver = {
2083         .owner                  = THIS_MODULE,
2084         .aperture_sizes         = intel_8xx_sizes,
2085         .size_type              = U8_APER_SIZE,
2086         .num_aperture_sizes     = 7,
2087         .configure              = intel_860_configure,
2088         .fetch_size             = intel_8xx_fetch_size,
2089         .cleanup                = intel_8xx_cleanup,
2090         .tlb_flush              = intel_8xx_tlbflush,
2091         .mask_memory            = agp_generic_mask_memory,
2092         .masks                  = intel_generic_masks,
2093         .agp_enable             = agp_generic_enable,
2094         .cache_flush            = global_cache_flush,
2095         .create_gatt_table      = agp_generic_create_gatt_table,
2096         .free_gatt_table        = agp_generic_free_gatt_table,
2097         .insert_memory          = agp_generic_insert_memory,
2098         .remove_memory          = agp_generic_remove_memory,
2099         .alloc_by_type          = agp_generic_alloc_by_type,
2100         .free_by_type           = agp_generic_free_by_type,
2101         .agp_alloc_page         = agp_generic_alloc_page,
2102         .agp_alloc_pages        = agp_generic_alloc_pages,
2103         .agp_destroy_page       = agp_generic_destroy_page,
2104         .agp_destroy_pages      = agp_generic_destroy_pages,
2105         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
2106 };
2107
2108 static const struct agp_bridge_driver intel_915_driver = {
2109         .owner                  = THIS_MODULE,
2110         .aperture_sizes         = intel_i830_sizes,
2111         .size_type              = FIXED_APER_SIZE,
2112         .num_aperture_sizes     = 4,
2113         .needs_scratch_page     = true,
2114         .configure              = intel_i915_configure,
2115         .fetch_size             = intel_i9xx_fetch_size,
2116         .cleanup                = intel_i915_cleanup,
2117         .tlb_flush              = intel_i810_tlbflush,
2118         .mask_memory            = intel_i810_mask_memory,
2119         .masks                  = intel_i810_masks,
2120         .agp_enable             = intel_i810_agp_enable,
2121         .cache_flush            = global_cache_flush,
2122         .create_gatt_table      = intel_i915_create_gatt_table,
2123         .free_gatt_table        = intel_i830_free_gatt_table,
2124         .insert_memory          = intel_i915_insert_entries,
2125         .remove_memory          = intel_i915_remove_entries,
2126         .alloc_by_type          = intel_i830_alloc_by_type,
2127         .free_by_type           = intel_i810_free_by_type,
2128         .agp_alloc_page         = agp_generic_alloc_page,
2129         .agp_alloc_pages        = agp_generic_alloc_pages,
2130         .agp_destroy_page       = agp_generic_destroy_page,
2131         .agp_destroy_pages      = agp_generic_destroy_pages,
2132         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
2133         .chipset_flush          = intel_i915_chipset_flush,
2134 #ifdef USE_PCI_DMA_API
2135         .agp_map_page           = intel_agp_map_page,
2136         .agp_unmap_page         = intel_agp_unmap_page,
2137         .agp_map_memory         = intel_agp_map_memory,
2138         .agp_unmap_memory       = intel_agp_unmap_memory,
2139 #endif
2140 };
2141
2142 static const struct agp_bridge_driver intel_i965_driver = {
2143         .owner                  = THIS_MODULE,
2144         .aperture_sizes         = intel_i830_sizes,
2145         .size_type              = FIXED_APER_SIZE,
2146         .num_aperture_sizes     = 4,
2147         .needs_scratch_page     = true,
2148         .configure              = intel_i915_configure,
2149         .fetch_size             = intel_i9xx_fetch_size,
2150         .cleanup                = intel_i915_cleanup,
2151         .tlb_flush              = intel_i810_tlbflush,
2152         .mask_memory            = intel_i965_mask_memory,
2153         .masks                  = intel_i810_masks,
2154         .agp_enable             = intel_i810_agp_enable,
2155         .cache_flush            = global_cache_flush,
2156         .create_gatt_table      = intel_i965_create_gatt_table,
2157         .free_gatt_table        = intel_i830_free_gatt_table,
2158         .insert_memory          = intel_i915_insert_entries,
2159         .remove_memory          = intel_i915_remove_entries,
2160         .alloc_by_type          = intel_i830_alloc_by_type,
2161         .free_by_type           = intel_i810_free_by_type,
2162         .agp_alloc_page         = agp_generic_alloc_page,
2163         .agp_alloc_pages        = agp_generic_alloc_pages,
2164         .agp_destroy_page       = agp_generic_destroy_page,
2165         .agp_destroy_pages      = agp_generic_destroy_pages,
2166         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
2167         .chipset_flush          = intel_i915_chipset_flush,
2168 #ifdef USE_PCI_DMA_API
2169         .agp_map_page           = intel_agp_map_page,
2170         .agp_unmap_page         = intel_agp_unmap_page,
2171         .agp_map_memory         = intel_agp_map_memory,
2172         .agp_unmap_memory       = intel_agp_unmap_memory,
2173 #endif
2174 };
2175
2176 static const struct agp_bridge_driver intel_7505_driver = {
2177         .owner                  = THIS_MODULE,
2178         .aperture_sizes         = intel_8xx_sizes,
2179         .size_type              = U8_APER_SIZE,
2180         .num_aperture_sizes     = 7,
2181         .configure              = intel_7505_configure,
2182         .fetch_size             = intel_8xx_fetch_size,
2183         .cleanup                = intel_8xx_cleanup,
2184         .tlb_flush              = intel_8xx_tlbflush,
2185         .mask_memory            = agp_generic_mask_memory,
2186         .masks                  = intel_generic_masks,
2187         .agp_enable             = agp_generic_enable,
2188         .cache_flush            = global_cache_flush,
2189         .create_gatt_table      = agp_generic_create_gatt_table,
2190         .free_gatt_table        = agp_generic_free_gatt_table,
2191         .insert_memory          = agp_generic_insert_memory,
2192         .remove_memory          = agp_generic_remove_memory,
2193         .alloc_by_type          = agp_generic_alloc_by_type,
2194         .free_by_type           = agp_generic_free_by_type,
2195         .agp_alloc_page         = agp_generic_alloc_page,
2196         .agp_alloc_pages        = agp_generic_alloc_pages,
2197         .agp_destroy_page       = agp_generic_destroy_page,
2198         .agp_destroy_pages      = agp_generic_destroy_pages,
2199         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
2200 };
2201
2202 static const struct agp_bridge_driver intel_g33_driver = {
2203         .owner                  = THIS_MODULE,
2204         .aperture_sizes         = intel_i830_sizes,
2205         .size_type              = FIXED_APER_SIZE,
2206         .num_aperture_sizes     = 4,
2207         .needs_scratch_page     = true,
2208         .configure              = intel_i915_configure,
2209         .fetch_size             = intel_i9xx_fetch_size,
2210         .cleanup                = intel_i915_cleanup,
2211         .tlb_flush              = intel_i810_tlbflush,
2212         .mask_memory            = intel_i965_mask_memory,
2213         .masks                  = intel_i810_masks,
2214         .agp_enable             = intel_i810_agp_enable,
2215         .cache_flush            = global_cache_flush,
2216         .create_gatt_table      = intel_i915_create_gatt_table,
2217         .free_gatt_table        = intel_i830_free_gatt_table,
2218         .insert_memory          = intel_i915_insert_entries,
2219         .remove_memory          = intel_i915_remove_entries,
2220         .alloc_by_type          = intel_i830_alloc_by_type,
2221         .free_by_type           = intel_i810_free_by_type,
2222         .agp_alloc_page         = agp_generic_alloc_page,
2223         .agp_alloc_pages        = agp_generic_alloc_pages,
2224         .agp_destroy_page       = agp_generic_destroy_page,
2225         .agp_destroy_pages      = agp_generic_destroy_pages,
2226         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
2227         .chipset_flush          = intel_i915_chipset_flush,
2228 #ifdef USE_PCI_DMA_API
2229         .agp_map_page           = intel_agp_map_page,
2230         .agp_unmap_page         = intel_agp_unmap_page,
2231         .agp_map_memory         = intel_agp_map_memory,
2232         .agp_unmap_memory       = intel_agp_unmap_memory,
2233 #endif
2234 };
2235
2236 static int find_gmch(u16 device)
2237 {
2238         struct pci_dev *gmch_device;
2239
2240         gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
2241         if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
2242                 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
2243                                              device, gmch_device);
2244         }
2245
2246         if (!gmch_device)
2247                 return 0;
2248
2249         intel_private.pcidev = gmch_device;
2250         return 1;
2251 }
2252
2253 /* Table to describe Intel GMCH and AGP/PCIE GART drivers.  At least one of
2254  * driver and gmch_driver must be non-null, and find_gmch will determine
2255  * which one should be used if a gmch_chip_id is present.
2256  */
2257 static const struct intel_driver_description {
2258         unsigned int chip_id;
2259         unsigned int gmch_chip_id;
2260         unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */
2261         char *name;
2262         const struct agp_bridge_driver *driver;
2263         const struct agp_bridge_driver *gmch_driver;
2264 } intel_agp_chipsets[] = {
2265         { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL },
2266         { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL },
2267         { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL },
2268         { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810",
2269                 NULL, &intel_810_driver },
2270         { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810",
2271                 NULL, &intel_810_driver },
2272         { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810",
2273                 NULL, &intel_810_driver },
2274         { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815",
2275                 &intel_815_driver, &intel_810_driver },
2276         { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL },
2277         { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL },
2278         { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M",
2279                 &intel_830mp_driver, &intel_830_driver },
2280         { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL },
2281         { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL },
2282         { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M",
2283                 &intel_845_driver, &intel_830_driver },
2284         { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL },
2285         { PCI_DEVICE_ID_INTEL_82854_HB, PCI_DEVICE_ID_INTEL_82854_IG, 0, "854",
2286                 &intel_845_driver, &intel_830_driver },
2287         { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL },
2288         { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM",
2289                 &intel_845_driver, &intel_830_driver },
2290         { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL },
2291         { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865",
2292                 &intel_845_driver, &intel_830_driver },
2293         { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL },
2294         { PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, 0, "E7221 (i915)",
2295                 NULL, &intel_915_driver },
2296         { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G",
2297                 NULL, &intel_915_driver },
2298         { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM",
2299                 NULL, &intel_915_driver },
2300         { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G",
2301                 NULL, &intel_915_driver },
2302         { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM",
2303                 NULL, &intel_915_driver },
2304         { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME",
2305                 NULL, &intel_915_driver },
2306         { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ",
2307                 NULL, &intel_i965_driver },
2308         { PCI_DEVICE_ID_INTEL_82G35_HB, PCI_DEVICE_ID_INTEL_82G35_IG, 0, "G35",
2309                 NULL, &intel_i965_driver },
2310         { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q",
2311                 NULL, &intel_i965_driver },
2312         { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G",
2313                 NULL, &intel_i965_driver },
2314         { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM",
2315                 NULL, &intel_i965_driver },
2316         { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE",
2317                 NULL, &intel_i965_driver },
2318         { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL },
2319         { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL },
2320         { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33",
2321                 NULL, &intel_g33_driver },
2322         { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35",
2323                 NULL, &intel_g33_driver },
2324         { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33",
2325                 NULL, &intel_g33_driver },
2326         { PCI_DEVICE_ID_INTEL_IGDGM_HB, PCI_DEVICE_ID_INTEL_IGDGM_IG, 0, "IGD",
2327                 NULL, &intel_g33_driver },
2328         { PCI_DEVICE_ID_INTEL_IGDG_HB, PCI_DEVICE_ID_INTEL_IGDG_IG, 0, "IGD",
2329                 NULL, &intel_g33_driver },
2330         { PCI_DEVICE_ID_INTEL_GM45_HB, PCI_DEVICE_ID_INTEL_GM45_IG, 0,
2331             "Mobile Intel® GM45 Express", NULL, &intel_i965_driver },
2332         { PCI_DEVICE_ID_INTEL_IGD_E_HB, PCI_DEVICE_ID_INTEL_IGD_E_IG, 0,
2333             "Intel Integrated Graphics Device", NULL, &intel_i965_driver },
2334         { PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG, 0,
2335             "Q45/Q43", NULL, &intel_i965_driver },
2336         { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, 0,
2337             "G45/G43", NULL, &intel_i965_driver },
2338         { PCI_DEVICE_ID_INTEL_G41_HB, PCI_DEVICE_ID_INTEL_G41_IG, 0,
2339             "G41", NULL, &intel_i965_driver },
2340         { PCI_DEVICE_ID_INTEL_IGDNG_D_HB, PCI_DEVICE_ID_INTEL_IGDNG_D_IG, 0,
2341             "IGDNG/D", NULL, &intel_i965_driver },
2342         { PCI_DEVICE_ID_INTEL_IGDNG_M_HB, PCI_DEVICE_ID_INTEL_IGDNG_M_IG, 0,
2343             "IGDNG/M", NULL, &intel_i965_driver },
2344         { PCI_DEVICE_ID_INTEL_IGDNG_MA_HB, PCI_DEVICE_ID_INTEL_IGDNG_M_IG, 0,
2345             "IGDNG/MA", NULL, &intel_i965_driver },
2346         { 0, 0, 0, NULL, NULL, NULL }
2347 };
2348
2349 static int __devinit agp_intel_probe(struct pci_dev *pdev,
2350                                      const struct pci_device_id *ent)
2351 {
2352         struct agp_bridge_data *bridge;
2353         u8 cap_ptr = 0;
2354         struct resource *r;
2355         int i;
2356
2357         cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
2358
2359         bridge = agp_alloc_bridge();
2360         if (!bridge)
2361                 return -ENOMEM;
2362
2363         for (i = 0; intel_agp_chipsets[i].name != NULL; i++) {
2364                 /* In case that multiple models of gfx chip may
2365                    stand on same host bridge type, this can be
2366                    sure we detect the right IGD. */
2367                 if (pdev->device == intel_agp_chipsets[i].chip_id) {
2368                         if ((intel_agp_chipsets[i].gmch_chip_id != 0) &&
2369                                 find_gmch(intel_agp_chipsets[i].gmch_chip_id)) {
2370                                 bridge->driver =
2371                                         intel_agp_chipsets[i].gmch_driver;
2372                                 break;
2373                         } else if (intel_agp_chipsets[i].multi_gmch_chip) {
2374                                 continue;
2375                         } else {
2376                                 bridge->driver = intel_agp_chipsets[i].driver;
2377                                 break;
2378                         }
2379                 }
2380         }
2381
2382         if (intel_agp_chipsets[i].name == NULL) {
2383                 if (cap_ptr)
2384                         dev_warn(&pdev->dev, "unsupported Intel chipset [%04x/%04x]\n",
2385                                  pdev->vendor, pdev->device);
2386                 agp_put_bridge(bridge);
2387                 return -ENODEV;
2388         }
2389
2390         if (bridge->driver == NULL) {
2391                 /* bridge has no AGP and no IGD detected */
2392                 if (cap_ptr)
2393                         dev_warn(&pdev->dev, "can't find bridge device (chip_id: %04x)\n",
2394                                  intel_agp_chipsets[i].gmch_chip_id);
2395                 agp_put_bridge(bridge);
2396                 return -ENODEV;
2397         }
2398
2399         bridge->dev = pdev;
2400         bridge->capndx = cap_ptr;
2401         bridge->dev_private_data = &intel_private;
2402
2403         dev_info(&pdev->dev, "Intel %s Chipset\n", intel_agp_chipsets[i].name);
2404
2405         /*
2406         * The following fixes the case where the BIOS has "forgotten" to
2407         * provide an address range for the GART.
2408         * 20030610 - hamish@zot.org
2409         */
2410         r = &pdev->resource[0];
2411         if (!r->start && r->end) {
2412                 if (pci_assign_resource(pdev, 0)) {
2413                         dev_err(&pdev->dev, "can't assign resource 0\n");
2414                         agp_put_bridge(bridge);
2415                         return -ENODEV;
2416                 }
2417         }
2418
2419         /*
2420         * If the device has not been properly setup, the following will catch
2421         * the problem and should stop the system from crashing.
2422         * 20030610 - hamish@zot.org
2423         */
2424         if (pci_enable_device(pdev)) {
2425                 dev_err(&pdev->dev, "can't enable PCI device\n");
2426                 agp_put_bridge(bridge);
2427                 return -ENODEV;
2428         }
2429
2430         /* Fill in the mode register */
2431         if (cap_ptr) {
2432                 pci_read_config_dword(pdev,
2433                                 bridge->capndx+PCI_AGP_STATUS,
2434                                 &bridge->mode);
2435         }
2436
2437         pci_set_drvdata(pdev, bridge);
2438         return agp_add_bridge(bridge);
2439 }
2440
2441 static void __devexit agp_intel_remove(struct pci_dev *pdev)
2442 {
2443         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2444
2445         agp_remove_bridge(bridge);
2446
2447         if (intel_private.pcidev)
2448                 pci_dev_put(intel_private.pcidev);
2449
2450         agp_put_bridge(bridge);
2451 }
2452
2453 #ifdef CONFIG_PM
2454 static int agp_intel_resume(struct pci_dev *pdev)
2455 {
2456         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2457         int ret_val;
2458
2459         if (bridge->driver == &intel_generic_driver)
2460                 intel_configure();
2461         else if (bridge->driver == &intel_850_driver)
2462                 intel_850_configure();
2463         else if (bridge->driver == &intel_845_driver)
2464                 intel_845_configure();
2465         else if (bridge->driver == &intel_830mp_driver)
2466                 intel_830mp_configure();
2467         else if (bridge->driver == &intel_915_driver)
2468                 intel_i915_configure();
2469         else if (bridge->driver == &intel_830_driver)
2470                 intel_i830_configure();
2471         else if (bridge->driver == &intel_810_driver)
2472                 intel_i810_configure();
2473         else if (bridge->driver == &intel_i965_driver)
2474                 intel_i915_configure();
2475
2476         ret_val = agp_rebind_memory();
2477         if (ret_val != 0)
2478                 return ret_val;
2479
2480         return 0;
2481 }
2482 #endif
2483
2484 static struct pci_device_id agp_intel_pci_table[] = {
2485 #define ID(x)                                           \
2486         {                                               \
2487         .class          = (PCI_CLASS_BRIDGE_HOST << 8), \
2488         .class_mask     = ~0,                           \
2489         .vendor         = PCI_VENDOR_ID_INTEL,          \
2490         .device         = x,                            \
2491         .subvendor      = PCI_ANY_ID,                   \
2492         .subdevice      = PCI_ANY_ID,                   \
2493         }
2494         ID(PCI_DEVICE_ID_INTEL_82443LX_0),
2495         ID(PCI_DEVICE_ID_INTEL_82443BX_0),
2496         ID(PCI_DEVICE_ID_INTEL_82443GX_0),
2497         ID(PCI_DEVICE_ID_INTEL_82810_MC1),
2498         ID(PCI_DEVICE_ID_INTEL_82810_MC3),
2499         ID(PCI_DEVICE_ID_INTEL_82810E_MC),
2500         ID(PCI_DEVICE_ID_INTEL_82815_MC),
2501         ID(PCI_DEVICE_ID_INTEL_82820_HB),
2502         ID(PCI_DEVICE_ID_INTEL_82820_UP_HB),
2503         ID(PCI_DEVICE_ID_INTEL_82830_HB),
2504         ID(PCI_DEVICE_ID_INTEL_82840_HB),
2505         ID(PCI_DEVICE_ID_INTEL_82845_HB),
2506         ID(PCI_DEVICE_ID_INTEL_82845G_HB),
2507         ID(PCI_DEVICE_ID_INTEL_82850_HB),
2508         ID(PCI_DEVICE_ID_INTEL_82854_HB),
2509         ID(PCI_DEVICE_ID_INTEL_82855PM_HB),
2510         ID(PCI_DEVICE_ID_INTEL_82855GM_HB),
2511         ID(PCI_DEVICE_ID_INTEL_82860_HB),
2512         ID(PCI_DEVICE_ID_INTEL_82865_HB),
2513         ID(PCI_DEVICE_ID_INTEL_82875_HB),
2514         ID(PCI_DEVICE_ID_INTEL_7505_0),
2515         ID(PCI_DEVICE_ID_INTEL_7205_0),
2516         ID(PCI_DEVICE_ID_INTEL_E7221_HB),
2517         ID(PCI_DEVICE_ID_INTEL_82915G_HB),
2518         ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
2519         ID(PCI_DEVICE_ID_INTEL_82945G_HB),
2520         ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
2521         ID(PCI_DEVICE_ID_INTEL_82945GME_HB),
2522         ID(PCI_DEVICE_ID_INTEL_IGDGM_HB),
2523         ID(PCI_DEVICE_ID_INTEL_IGDG_HB),
2524         ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
2525         ID(PCI_DEVICE_ID_INTEL_82G35_HB),
2526         ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
2527         ID(PCI_DEVICE_ID_INTEL_82965G_HB),
2528         ID(PCI_DEVICE_ID_INTEL_82965GM_HB),
2529         ID(PCI_DEVICE_ID_INTEL_82965GME_HB),
2530         ID(PCI_DEVICE_ID_INTEL_G33_HB),
2531         ID(PCI_DEVICE_ID_INTEL_Q35_HB),
2532         ID(PCI_DEVICE_ID_INTEL_Q33_HB),
2533         ID(PCI_DEVICE_ID_INTEL_GM45_HB),
2534         ID(PCI_DEVICE_ID_INTEL_IGD_E_HB),
2535         ID(PCI_DEVICE_ID_INTEL_Q45_HB),
2536         ID(PCI_DEVICE_ID_INTEL_G45_HB),
2537         ID(PCI_DEVICE_ID_INTEL_G41_HB),
2538         ID(PCI_DEVICE_ID_INTEL_IGDNG_D_HB),
2539         ID(PCI_DEVICE_ID_INTEL_IGDNG_M_HB),
2540         ID(PCI_DEVICE_ID_INTEL_IGDNG_MA_HB),
2541         { }
2542 };
2543
2544 MODULE_DEVICE_TABLE(pci, agp_intel_pci_table);
2545
2546 static struct pci_driver agp_intel_pci_driver = {
2547         .name           = "agpgart-intel",
2548         .id_table       = agp_intel_pci_table,
2549         .probe          = agp_intel_probe,
2550         .remove         = __devexit_p(agp_intel_remove),
2551 #ifdef CONFIG_PM
2552         .resume         = agp_intel_resume,
2553 #endif
2554 };
2555
2556 static int __init agp_intel_init(void)
2557 {
2558         if (agp_off)
2559                 return -EINVAL;
2560         return pci_register_driver(&agp_intel_pci_driver);
2561 }
2562
2563 static void __exit agp_intel_cleanup(void)
2564 {
2565         pci_unregister_driver(&agp_intel_pci_driver);
2566 }
2567
2568 module_init(agp_intel_init);
2569 module_exit(agp_intel_cleanup);
2570
2571 MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
2572 MODULE_LICENSE("GPL and additional rights");