drivers/char/tpm/tpm_nsc.c

   1 /*
   2  * Copyright (C) 2004 IBM Corporation
   3  *
   4  * Authors:
   5  * Leendert van Doorn <leendert@watson.ibm.com>
   6  * Dave Safford <safford@watson.ibm.com>
   7  * Reiner Sailer <sailer@watson.ibm.com>
   8  * Kylene Hall <kjhall@us.ibm.com>
   9  *
  10  * Maintained by: <tpmdd-devel@lists.sourceforge.net>
  11  *
  12  * Device driver for TCG/TCPA TPM (trusted platform module).
  13  * Specifications at www.trustedcomputinggroup.org
  14  *
  15  * This program is free software; you can redistribute it and/or
  16  * modify it under the terms of the GNU General Public License as
  17  * published by the Free Software Foundation, version 2 of the
  18  * License.
  19  *
  20  */
  21
  22 #include <linux/platform_device.h>
  23 #include <linux/slab.h>
  24 #include "tpm.h"
  25
  26 /* National definitions */
  27 enum tpm_nsc_addr{
  28         TPM_NSC_IRQ = 0x07,
  29         TPM_NSC_BASE0_HI = 0x60,
  30         TPM_NSC_BASE0_LO = 0x61,
  31         TPM_NSC_BASE1_HI = 0x62,
  32         TPM_NSC_BASE1_LO = 0x63
  33 };
  34
  35 enum tpm_nsc_index {
  36         NSC_LDN_INDEX = 0x07,
  37         NSC_SID_INDEX = 0x20,
  38         NSC_LDC_INDEX = 0x30,
  39         NSC_DIO_INDEX = 0x60,
  40         NSC_CIO_INDEX = 0x62,
  41         NSC_IRQ_INDEX = 0x70,
  42         NSC_ITS_INDEX = 0x71
  43 };
  44
  45 enum tpm_nsc_status_loc {
  46         NSC_STATUS = 0x01,
  47         NSC_COMMAND = 0x01,
  48         NSC_DATA = 0x00
  49 };
  50
  51 /* status bits */
  52 enum tpm_nsc_status {
  53         NSC_STATUS_OBF = 0x01,  /* output buffer full */
  54         NSC_STATUS_IBF = 0x02,  /* input buffer full */
  55         NSC_STATUS_F0 = 0x04,   /* F0 */
  56         NSC_STATUS_A2 = 0x08,   /* A2 */
  57         NSC_STATUS_RDY = 0x10,  /* ready to receive command */
  58         NSC_STATUS_IBR = 0x20   /* ready to receive data */
  59 };
  60
  61 /* command bits */
  62 enum tpm_nsc_cmd_mode {
  63         NSC_COMMAND_NORMAL = 0x01,      /* normal mode */
  64         NSC_COMMAND_EOC = 0x03,
  65         NSC_COMMAND_CANCEL = 0x22
  66 };
  67
  68 struct tpm_nsc_priv {
  69         unsigned long base;
  70 };
  71
  72 static inline struct tpm_nsc_priv *nsc_get_priv(struct tpm_chip *chip)
  73 {
  74         return chip->vendor.priv;
  75 }
  76
  77 /*
  78  * Wait for a certain status to appear
  79  */
  80 static int wait_for_stat(struct tpm_chip *chip, u8 mask, u8 val, u8 * data)
  81 {
  82         unsigned long stop;
  83
  84         /* status immediately available check */
  85         *data = inb(nsc_get_priv(chip)->base + NSC_STATUS);
  86         if ((*data & mask) == val)
  87                 return 0;
  88
  89         /* wait for status */
  90         stop = jiffies + 10 * HZ;
  91         do {
  92                 msleep(TPM_TIMEOUT);
  93                 *data = inb(nsc_get_priv(chip)->base + 1);
  94                 if ((*data & mask) == val)
  95                         return 0;
  96         }
  97         while (time_before(jiffies, stop));
  98
  99         return -EBUSY;
 100 }
 101
 102 static int nsc_wait_for_ready(struct tpm_chip *chip)
 103 {
 104         int status;
 105         unsigned long stop;
 106
 107         /* status immediately available check */
 108         status = inb(nsc_get_priv(chip)->base + NSC_STATUS);
 109         if (status & NSC_STATUS_OBF)
 110                 status = inb(nsc_get_priv(chip)->base + NSC_DATA);
 111         if (status & NSC_STATUS_RDY)
 112                 return 0;
 113
 114         /* wait for status */
 115         stop = jiffies + 100;
 116         do {
 117                 msleep(TPM_TIMEOUT);
 118                 status = inb(nsc_get_priv(chip)->base + NSC_STATUS);
 119                 if (status & NSC_STATUS_OBF)
 120                         status = inb(nsc_get_priv(chip)->base + NSC_DATA);
 121                 if (status & NSC_STATUS_RDY)
 122                         return 0;
 123         }
 124         while (time_before(jiffies, stop));
 125
 126         dev_info(&chip->dev, "wait for ready failed\n");
 127         return -EBUSY;
 128 }
 129
 130
 131 static int tpm_nsc_recv(struct tpm_chip *chip, u8 * buf, size_t count)
 132 {
 133         u8 *buffer = buf;
 134         u8 data, *p;
 135         u32 size;
 136         __be32 *native_size;
 137
 138         if (count < 6)
 139                 return -EIO;
 140
 141         if (wait_for_stat(chip, NSC_STATUS_F0, NSC_STATUS_F0, &data) < 0) {
 142                 dev_err(&chip->dev, "F0 timeout\n");
 143                 return -EIO;
 144         }
 145
 146         data = inb(nsc_get_priv(chip)->base + NSC_DATA);
 147         if (data != NSC_COMMAND_NORMAL) {
 148                 dev_err(&chip->dev, "not in normal mode (0x%x)\n",
 149                         data);
 150                 return -EIO;
 151         }
 152
 153         /* read the whole packet */
 154         for (p = buffer; p < &buffer[count]; p++) {
 155                 if (wait_for_stat
 156                     (chip, NSC_STATUS_OBF, NSC_STATUS_OBF, &data) < 0) {
 157                         dev_err(&chip->dev,
 158                                 "OBF timeout (while reading data)\n");
 159                         return -EIO;
 160                 }
 161                 if (data & NSC_STATUS_F0)
 162                         break;
 163                 *p = inb(nsc_get_priv(chip)->base + NSC_DATA);
 164         }
 165
 166         if ((data & NSC_STATUS_F0) == 0 &&
 167         (wait_for_stat(chip, NSC_STATUS_F0, NSC_STATUS_F0, &data) < 0)) {
 168                 dev_err(&chip->dev, "F0 not set\n");
 169                 return -EIO;
 170         }
 171
 172         data = inb(nsc_get_priv(chip)->base + NSC_DATA);
 173         if (data != NSC_COMMAND_EOC) {
 174                 dev_err(&chip->dev,
 175                         "expected end of command(0x%x)\n", data);
 176                 return -EIO;
 177         }
 178
 179         native_size = (__force __be32 *) (buf + 2);
 180         size = be32_to_cpu(*native_size);
 181
 182         if (count < size)
 183                 return -EIO;
 184
 185         return size;
 186 }
 187
 188 static int tpm_nsc_send(struct tpm_chip *chip, u8 * buf, size_t count)
 189 {
 190         u8 data;
 191         int i;
 192
 193         /*
 194          * If we hit the chip with back to back commands it locks up
 195          * and never set IBF. Hitting it with this "hammer" seems to
 196          * fix it. Not sure why this is needed, we followed the flow
 197          * chart in the manual to the letter.
 198          */
 199         outb(NSC_COMMAND_CANCEL, nsc_get_priv(chip)->base + NSC_COMMAND);
 200
 201         if (nsc_wait_for_ready(chip) != 0)
 202                 return -EIO;
 203
 204         if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
 205                 dev_err(&chip->dev, "IBF timeout\n");
 206                 return -EIO;
 207         }
 208
 209         outb(NSC_COMMAND_NORMAL, nsc_get_priv(chip)->base + NSC_COMMAND);
 210         if (wait_for_stat(chip, NSC_STATUS_IBR, NSC_STATUS_IBR, &data) < 0) {
 211                 dev_err(&chip->dev, "IBR timeout\n");
 212                 return -EIO;
 213         }
 214
 215         for (i = 0; i < count; i++) {
 216                 if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
 217                         dev_err(&chip->dev,
 218                                 "IBF timeout (while writing data)\n");
 219                         return -EIO;
 220                 }
 221                 outb(buf[i], nsc_get_priv(chip)->base + NSC_DATA);
 222         }
 223
 224         if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
 225                 dev_err(&chip->dev, "IBF timeout\n");
 226                 return -EIO;
 227         }
 228         outb(NSC_COMMAND_EOC, nsc_get_priv(chip)->base + NSC_COMMAND);
 229
 230         return count;
 231 }
 232
 233 static void tpm_nsc_cancel(struct tpm_chip *chip)
 234 {
 235         outb(NSC_COMMAND_CANCEL, nsc_get_priv(chip)->base + NSC_COMMAND);
 236 }
 237
 238 static u8 tpm_nsc_status(struct tpm_chip *chip)
 239 {
 240         return inb(nsc_get_priv(chip)->base + NSC_STATUS);
 241 }
 242
 243 static bool tpm_nsc_req_canceled(struct tpm_chip *chip, u8 status)
 244 {
 245         return (status == NSC_STATUS_RDY);
 246 }
 247
 248 static const struct tpm_class_ops tpm_nsc = {
 249         .recv = tpm_nsc_recv,
 250         .send = tpm_nsc_send,
 251         .cancel = tpm_nsc_cancel,
 252         .status = tpm_nsc_status,
 253         .req_complete_mask = NSC_STATUS_OBF,
 254         .req_complete_val = NSC_STATUS_OBF,
 255         .req_canceled = tpm_nsc_req_canceled,
 256 };
 257
 258 static struct platform_device *pdev = NULL;
 259
 260 static void tpm_nsc_remove(struct device *dev)
 261 {
 262         struct tpm_chip *chip = dev_get_drvdata(dev);
 263
 264         tpm_chip_unregister(chip);
 265         release_region(nsc_get_priv(chip)->base, 2);
 266 }
 267
 268 static SIMPLE_DEV_PM_OPS(tpm_nsc_pm, tpm_pm_suspend, tpm_pm_resume);
 269
 270 static struct platform_driver nsc_drv = {
 271         .driver          = {
 272                 .name    = "tpm_nsc",
 273                 .pm      = &tpm_nsc_pm,
 274         },
 275 };
 276
 277 static int __init init_nsc(void)
 278 {
 279         int rc = 0;
 280         int lo, hi, err;
 281         int nscAddrBase = TPM_ADDR;
 282         struct tpm_chip *chip;
 283         unsigned long base;
 284         struct tpm_nsc_priv *priv;
 285
 286         /* verify that it is a National part (SID) */
 287         if (tpm_read_index(TPM_ADDR, NSC_SID_INDEX) != 0xEF) {
 288                 nscAddrBase = (tpm_read_index(TPM_SUPERIO_ADDR, 0x2C)<<8)|
 289                         (tpm_read_index(TPM_SUPERIO_ADDR, 0x2B)&0xFE);
 290                 if (tpm_read_index(nscAddrBase, NSC_SID_INDEX) != 0xF6)
 291                         return -ENODEV;
 292         }
 293
 294         err = platform_driver_register(&nsc_drv);
 295         if (err)
 296                 return err;
 297
 298         hi = tpm_read_index(nscAddrBase, TPM_NSC_BASE0_HI);
 299         lo = tpm_read_index(nscAddrBase, TPM_NSC_BASE0_LO);
 300         base = (hi<<8) | lo;
 301
 302         /* enable the DPM module */
 303         tpm_write_index(nscAddrBase, NSC_LDC_INDEX, 0x01);
 304
 305         pdev = platform_device_alloc("tpm_nscl0", -1);
 306         if (!pdev) {
 307                 rc = -ENOMEM;
 308                 goto err_unreg_drv;
 309         }
 310
 311         pdev->num_resources = 0;
 312         pdev->dev.driver = &nsc_drv.driver;
 313         pdev->dev.release = tpm_nsc_remove;
 314
 315         if ((rc = platform_device_add(pdev)) < 0)
 316                 goto err_put_dev;
 317
 318         priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
 319         if (!priv) {
 320                 rc = -ENOMEM;
 321                 goto err_del_dev;
 322         }
 323
 324         priv->base = base;
 325
 326         if (request_region(base, 2, "tpm_nsc0") == NULL ) {
 327                 rc = -EBUSY;
 328                 goto err_del_dev;
 329         }
 330
 331         chip = tpmm_chip_alloc(&pdev->dev, &tpm_nsc);
 332         if (IS_ERR(chip)) {
 333                 rc = -ENODEV;
 334                 goto err_rel_reg;
 335         }
 336
 337         chip->vendor.priv = priv;
 338
 339         rc = tpm_chip_register(chip);
 340         if (rc)
 341                 goto err_rel_reg;
 342
 343         dev_dbg(&pdev->dev, "NSC TPM detected\n");
 344         dev_dbg(&pdev->dev,
 345                 "NSC LDN 0x%x, SID 0x%x, SRID 0x%x\n",
 346                 tpm_read_index(nscAddrBase,0x07), tpm_read_index(nscAddrBase,0x20),
 347                 tpm_read_index(nscAddrBase,0x27));
 348         dev_dbg(&pdev->dev,
 349                 "NSC SIOCF1 0x%x SIOCF5 0x%x SIOCF6 0x%x SIOCF8 0x%x\n",
 350                 tpm_read_index(nscAddrBase,0x21), tpm_read_index(nscAddrBase,0x25),
 351                 tpm_read_index(nscAddrBase,0x26), tpm_read_index(nscAddrBase,0x28));
 352         dev_dbg(&pdev->dev, "NSC IO Base0 0x%x\n",
 353                 (tpm_read_index(nscAddrBase,0x60) << 8) | tpm_read_index(nscAddrBase,0x61));
 354         dev_dbg(&pdev->dev, "NSC IO Base1 0x%x\n",
 355                 (tpm_read_index(nscAddrBase,0x62) << 8) | tpm_read_index(nscAddrBase,0x63));
 356         dev_dbg(&pdev->dev, "NSC Interrupt number and wakeup 0x%x\n",
 357                 tpm_read_index(nscAddrBase,0x70));
 358         dev_dbg(&pdev->dev, "NSC IRQ type select 0x%x\n",
 359                 tpm_read_index(nscAddrBase,0x71));
 360         dev_dbg(&pdev->dev,
 361                 "NSC DMA channel select0 0x%x, select1 0x%x\n",
 362                 tpm_read_index(nscAddrBase,0x74), tpm_read_index(nscAddrBase,0x75));
 363         dev_dbg(&pdev->dev,
 364                 "NSC Config "
 365                 "0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
 366                 tpm_read_index(nscAddrBase,0xF0), tpm_read_index(nscAddrBase,0xF1),
 367                 tpm_read_index(nscAddrBase,0xF2), tpm_read_index(nscAddrBase,0xF3),
 368                 tpm_read_index(nscAddrBase,0xF4), tpm_read_index(nscAddrBase,0xF5),
 369                 tpm_read_index(nscAddrBase,0xF6), tpm_read_index(nscAddrBase,0xF7),
 370                 tpm_read_index(nscAddrBase,0xF8), tpm_read_index(nscAddrBase,0xF9));
 371
 372         dev_info(&pdev->dev,
 373                  "NSC TPM revision %d\n",
 374                  tpm_read_index(nscAddrBase, 0x27) & 0x1F);
 375
 376         return 0;
 377
 378 err_rel_reg:
 379         release_region(base, 2);
 380 err_del_dev:
 381         platform_device_del(pdev);
 382 err_put_dev:
 383         platform_device_put(pdev);
 384 err_unreg_drv:
 385         platform_driver_unregister(&nsc_drv);
 386         return rc;
 387 }
 388
 389 static void __exit cleanup_nsc(void)
 390 {
 391         if (pdev) {
 392                 tpm_nsc_remove(&pdev->dev);
 393                 platform_device_unregister(pdev);
 394         }
 395
 396         platform_driver_unregister(&nsc_drv);
 397 }
 398
 399 module_init(init_nsc);
 400 module_exit(cleanup_nsc);
 401
 402 MODULE_AUTHOR("Leendert van Doorn (leendert@watson.ibm.com)");
 403 MODULE_DESCRIPTION("TPM Driver");
 404 MODULE_VERSION("2.0");
 405 MODULE_LICENSE("GPL");