drivers/clk/clk-efm32gg.c

   1 /*
   2  * Copyright (C) 2013 Pengutronix
   3  * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it under
   6  * the terms of the GNU General Public License version 2 as published by the
   7  * Free Software Foundation.
   8  */
   9 #include <linux/io.h>
  10 #include <linux/clk-provider.h>
  11 #include <linux/of.h>
  12 #include <linux/of_address.h>
  13 #include <linux/slab.h>
  14
  15 #include <dt-bindings/clock/efm32-cmu.h>
  16
  17 #define CMU_HFPERCLKEN0         0x44
  18 #define CMU_MAX_CLKS            37
  19
  20 static struct clk_hw_onecell_data *clk_data;
  21
  22 static void __init efm32gg_cmu_init(struct device_node *np)
  23 {
  24         int i;
  25         void __iomem *base;
  26         struct clk_hw **hws;
  27
  28         clk_data = kzalloc(sizeof(*clk_data) +
  29                            sizeof(*clk_data->hws) * CMU_MAX_CLKS, GFP_KERNEL);
  30
  31         if (!clk_data)
  32                 return;
  33
  34         hws = clk_data->hws;
  35
  36         for (i = 0; i < CMU_MAX_CLKS; ++i)
  37                 hws[i] = ERR_PTR(-ENOENT);
  38
  39         base = of_iomap(np, 0);
  40         if (!base) {
  41                 pr_warn("Failed to map address range for efm32gg,cmu node\n");
  42                 return;
  43         }
  44
  45         hws[clk_HFXO] = clk_hw_register_fixed_rate(NULL, "HFXO", NULL, 0,
  46                                                    48000000);
  47
  48         hws[clk_HFPERCLKUSART0] = clk_hw_register_gate(NULL, "HFPERCLK.USART0",
  49                         "HFXO", 0, base + CMU_HFPERCLKEN0, 0, 0, NULL);
  50         hws[clk_HFPERCLKUSART1] = clk_hw_register_gate(NULL, "HFPERCLK.USART1",
  51                         "HFXO", 0, base + CMU_HFPERCLKEN0, 1, 0, NULL);
  52         hws[clk_HFPERCLKUSART2] = clk_hw_register_gate(NULL, "HFPERCLK.USART2",
  53                         "HFXO", 0, base + CMU_HFPERCLKEN0, 2, 0, NULL);
  54         hws[clk_HFPERCLKUART0] = clk_hw_register_gate(NULL, "HFPERCLK.UART0",
  55                         "HFXO", 0, base + CMU_HFPERCLKEN0, 3, 0, NULL);
  56         hws[clk_HFPERCLKUART1] = clk_hw_register_gate(NULL, "HFPERCLK.UART1",
  57                         "HFXO", 0, base + CMU_HFPERCLKEN0, 4, 0, NULL);
  58         hws[clk_HFPERCLKTIMER0] = clk_hw_register_gate(NULL, "HFPERCLK.TIMER0",
  59                         "HFXO", 0, base + CMU_HFPERCLKEN0, 5, 0, NULL);
  60         hws[clk_HFPERCLKTIMER1] = clk_hw_register_gate(NULL, "HFPERCLK.TIMER1",
  61                         "HFXO", 0, base + CMU_HFPERCLKEN0, 6, 0, NULL);
  62         hws[clk_HFPERCLKTIMER2] = clk_hw_register_gate(NULL, "HFPERCLK.TIMER2",
  63                         "HFXO", 0, base + CMU_HFPERCLKEN0, 7, 0, NULL);
  64         hws[clk_HFPERCLKTIMER3] = clk_hw_register_gate(NULL, "HFPERCLK.TIMER3",
  65                         "HFXO", 0, base + CMU_HFPERCLKEN0, 8, 0, NULL);
  66         hws[clk_HFPERCLKACMP0] = clk_hw_register_gate(NULL, "HFPERCLK.ACMP0",
  67                         "HFXO", 0, base + CMU_HFPERCLKEN0, 9, 0, NULL);
  68         hws[clk_HFPERCLKACMP1] = clk_hw_register_gate(NULL, "HFPERCLK.ACMP1",
  69                         "HFXO", 0, base + CMU_HFPERCLKEN0, 10, 0, NULL);
  70         hws[clk_HFPERCLKI2C0] = clk_hw_register_gate(NULL, "HFPERCLK.I2C0",
  71                         "HFXO", 0, base + CMU_HFPERCLKEN0, 11, 0, NULL);
  72         hws[clk_HFPERCLKI2C1] = clk_hw_register_gate(NULL, "HFPERCLK.I2C1",
  73                         "HFXO", 0, base + CMU_HFPERCLKEN0, 12, 0, NULL);
  74         hws[clk_HFPERCLKGPIO] = clk_hw_register_gate(NULL, "HFPERCLK.GPIO",
  75                         "HFXO", 0, base + CMU_HFPERCLKEN0, 13, 0, NULL);
  76         hws[clk_HFPERCLKVCMP] = clk_hw_register_gate(NULL, "HFPERCLK.VCMP",
  77                         "HFXO", 0, base + CMU_HFPERCLKEN0, 14, 0, NULL);
  78         hws[clk_HFPERCLKPRS] = clk_hw_register_gate(NULL, "HFPERCLK.PRS",
  79                         "HFXO", 0, base + CMU_HFPERCLKEN0, 15, 0, NULL);
  80         hws[clk_HFPERCLKADC0] = clk_hw_register_gate(NULL, "HFPERCLK.ADC0",
  81                         "HFXO", 0, base + CMU_HFPERCLKEN0, 16, 0, NULL);
  82         hws[clk_HFPERCLKDAC0] = clk_hw_register_gate(NULL, "HFPERCLK.DAC0",
  83                         "HFXO", 0, base + CMU_HFPERCLKEN0, 17, 0, NULL);
  84
  85         of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data);
  86 }
  87 CLK_OF_DECLARE(efm32ggcmu, "efm32gg,cmu", efm32gg_cmu_init);