drivers/clk/clk-fixed-rate.c

   1 /*
   2  * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
   3  * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * Fixed rate clock implementation
  10  */
  11
  12 #include <linux/clk-provider.h>
  13 #include <linux/module.h>
  14 #include <linux/slab.h>
  15 #include <linux/io.h>
  16 #include <linux/err.h>
  17 #include <linux/of.h>
  18
  19 /*
  20  * DOC: basic fixed-rate clock that cannot gate
  21  *
  22  * Traits of this clock:
  23  * prepare - clk_(un)prepare only ensures parents are prepared
  24  * enable - clk_enable only ensures parents are enabled
  25  * rate - rate is always a fixed value.  No clk_set_rate support
  26  * parent - fixed parent.  No clk_set_parent support
  27  */
  28
  29 static unsigned long clk_fixed_rate_recalc_rate(struct clk_hw *hw,
  30                 unsigned long parent_rate)
  31 {
  32         return to_clk_fixed_rate(hw)->fixed_rate;
  33 }
  34
  35 static unsigned long clk_fixed_rate_recalc_accuracy(struct clk_hw *hw,
  36                 unsigned long parent_accuracy)
  37 {
  38         return to_clk_fixed_rate(hw)->fixed_accuracy;
  39 }
  40
  41 const struct clk_ops clk_fixed_rate_ops = {
  42         .recalc_rate = clk_fixed_rate_recalc_rate,
  43         .recalc_accuracy = clk_fixed_rate_recalc_accuracy,
  44 };
  45 EXPORT_SYMBOL_GPL(clk_fixed_rate_ops);
  46
  47 /**
  48  * clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with
  49  * the clock framework
  50  * @dev: device that is registering this clock
  51  * @name: name of this clock
  52  * @parent_name: name of clock's parent
  53  * @flags: framework-specific flags
  54  * @fixed_rate: non-adjustable clock rate
  55  * @fixed_accuracy: non-adjustable clock rate
  56  */
  57 struct clk_hw *clk_hw_register_fixed_rate_with_accuracy(struct device *dev,
  58                 const char *name, const char *parent_name, unsigned long flags,
  59                 unsigned long fixed_rate, unsigned long fixed_accuracy)
  60 {
  61         struct clk_fixed_rate *fixed;
  62         struct clk_hw *hw;
  63         struct clk_init_data init;
  64         int ret;
  65
  66         /* allocate fixed-rate clock */
  67         fixed = kzalloc(sizeof(*fixed), GFP_KERNEL);
  68         if (!fixed)
  69                 return ERR_PTR(-ENOMEM);
  70
  71         init.name = name;
  72         init.ops = &clk_fixed_rate_ops;
  73         init.flags = flags | CLK_IS_BASIC;
  74         init.parent_names = (parent_name ? &parent_name: NULL);
  75         init.num_parents = (parent_name ? 1 : 0);
  76
  77         /* struct clk_fixed_rate assignments */
  78         fixed->fixed_rate = fixed_rate;
  79         fixed->fixed_accuracy = fixed_accuracy;
  80         fixed->hw.init = &init;
  81
  82         /* register the clock */
  83         hw = &fixed->hw;
  84         ret = clk_hw_register(dev, hw);
  85         if (ret) {
  86                 kfree(fixed);
  87                 hw = ERR_PTR(ret);
  88         }
  89
  90         return hw;
  91 }
  92 EXPORT_SYMBOL_GPL(clk_hw_register_fixed_rate_with_accuracy);
  93
  94 struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev,
  95                 const char *name, const char *parent_name, unsigned long flags,
  96                 unsigned long fixed_rate, unsigned long fixed_accuracy)
  97 {
  98         struct clk_hw *hw;
  99
 100         hw = clk_hw_register_fixed_rate_with_accuracy(dev, name, parent_name,
 101                         flags, fixed_rate, fixed_accuracy);
 102         if (IS_ERR(hw))
 103                 return ERR_CAST(hw);
 104         return hw->clk;
 105 }
 106 EXPORT_SYMBOL_GPL(clk_register_fixed_rate_with_accuracy);
 107
 108 /**
 109  * clk_hw_register_fixed_rate - register fixed-rate clock with the clock
 110  * framework
 111  * @dev: device that is registering this clock
 112  * @name: name of this clock
 113  * @parent_name: name of clock's parent
 114  * @flags: framework-specific flags
 115  * @fixed_rate: non-adjustable clock rate
 116  */
 117 struct clk_hw *clk_hw_register_fixed_rate(struct device *dev, const char *name,
 118                 const char *parent_name, unsigned long flags,
 119                 unsigned long fixed_rate)
 120 {
 121         return clk_hw_register_fixed_rate_with_accuracy(dev, name, parent_name,
 122                                                      flags, fixed_rate, 0);
 123 }
 124 EXPORT_SYMBOL_GPL(clk_hw_register_fixed_rate);
 125
 126 struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
 127                 const char *parent_name, unsigned long flags,
 128                 unsigned long fixed_rate)
 129 {
 130         return clk_register_fixed_rate_with_accuracy(dev, name, parent_name,
 131                                                      flags, fixed_rate, 0);
 132 }
 133 EXPORT_SYMBOL_GPL(clk_register_fixed_rate);
 134
 135 void clk_unregister_fixed_rate(struct clk *clk)
 136 {
 137         struct clk_hw *hw;
 138
 139         hw = __clk_get_hw(clk);
 140         if (!hw)
 141                 return;
 142
 143         clk_unregister(clk);
 144         kfree(to_clk_fixed_rate(hw));
 145 }
 146 EXPORT_SYMBOL_GPL(clk_unregister_fixed_rate);
 147
 148 void clk_hw_unregister_fixed_rate(struct clk_hw *hw)
 149 {
 150         struct clk_fixed_rate *fixed;
 151
 152         fixed = to_clk_fixed_rate(hw);
 153
 154         clk_hw_unregister(hw);
 155         kfree(fixed);
 156 }
 157 EXPORT_SYMBOL_GPL(clk_hw_unregister_fixed_rate);
 158
 159 #ifdef CONFIG_OF
 160 /**
 161  * of_fixed_clk_setup() - Setup function for simple fixed rate clock
 162  */
 163 void of_fixed_clk_setup(struct device_node *node)
 164 {
 165         struct clk *clk;
 166         const char *clk_name = node->name;
 167         u32 rate;
 168         u32 accuracy = 0;
 169
 170         if (of_property_read_u32(node, "clock-frequency", &rate))
 171                 return;
 172
 173         of_property_read_u32(node, "clock-accuracy", &accuracy);
 174
 175         of_property_read_string(node, "clock-output-names", &clk_name);
 176
 177         clk = clk_register_fixed_rate_with_accuracy(NULL, clk_name, NULL,
 178                                                     0, rate, accuracy);
 179         if (!IS_ERR(clk))
 180                 of_clk_add_provider(node, of_clk_src_simple_get, clk);
 181 }
 182 EXPORT_SYMBOL_GPL(of_fixed_clk_setup);
 183 CLK_OF_DECLARE(fixed_clk, "fixed-clock", of_fixed_clk_setup);
 184 #endif