drivers/clocksource/arm_arch_timer.c

   1 /*
   2  *  linux/drivers/clocksource/arm_arch_timer.c
   3  *
   4  *  Copyright (C) 2011 ARM Ltd.
   5  *  All Rights Reserved
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11 #include <linux/init.h>
  12 #include <linux/kernel.h>
  13 #include <linux/device.h>
  14 #include <linux/smp.h>
  15 #include <linux/cpu.h>
  16 #include <linux/cpu_pm.h>
  17 #include <linux/clockchips.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/of_irq.h>
  20 #include <linux/of_address.h>
  21 #include <linux/io.h>
  22 #include <linux/slab.h>
  23 #include <linux/sched_clock.h>
  24
  25 #include <asm/arch_timer.h>
  26 #include <asm/virt.h>
  27
  28 #include <clocksource/arm_arch_timer.h>
  29
  30 #define CNTTIDR         0x08
  31 #define CNTTIDR_VIRT(n) (BIT(1) << ((n) * 4))
  32
  33 #define CNTVCT_LO       0x08
  34 #define CNTVCT_HI       0x0c
  35 #define CNTFRQ          0x10
  36 #define CNTP_TVAL       0x28
  37 #define CNTP_CTL        0x2c
  38 #define CNTV_TVAL       0x38
  39 #define CNTV_CTL        0x3c
  40
  41 #define ARCH_CP15_TIMER BIT(0)
  42 #define ARCH_MEM_TIMER  BIT(1)
  43 static unsigned arch_timers_present __initdata;
  44
  45 static void __iomem *arch_counter_base;
  46
  47 struct arch_timer {
  48         void __iomem *base;
  49         struct clock_event_device evt;
  50 };
  51
  52 #define to_arch_timer(e) container_of(e, struct arch_timer, evt)
  53
  54 static u32 arch_timer_rate;
  55
  56 enum ppi_nr {
  57         PHYS_SECURE_PPI,
  58         PHYS_NONSECURE_PPI,
  59         VIRT_PPI,
  60         HYP_PPI,
  61         MAX_TIMER_PPI
  62 };
  63
  64 static int arch_timer_ppi[MAX_TIMER_PPI];
  65
  66 static struct clock_event_device __percpu *arch_timer_evt;
  67
  68 static bool arch_timer_use_virtual = true;
  69 static bool arch_timer_c3stop;
  70 static bool arch_timer_mem_use_virtual;
  71
  72 /*
  73  * Architected system timer support.
  74  */
  75
  76 static __always_inline
  77 void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,
  78                           struct clock_event_device *clk)
  79 {
  80         if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
  81                 struct arch_timer *timer = to_arch_timer(clk);
  82                 switch (reg) {
  83                 case ARCH_TIMER_REG_CTRL:
  84                         writel_relaxed(val, timer->base + CNTP_CTL);
  85                         break;
  86                 case ARCH_TIMER_REG_TVAL:
  87                         writel_relaxed(val, timer->base + CNTP_TVAL);
  88                         break;
  89                 }
  90         } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
  91                 struct arch_timer *timer = to_arch_timer(clk);
  92                 switch (reg) {
  93                 case ARCH_TIMER_REG_CTRL:
  94                         writel_relaxed(val, timer->base + CNTV_CTL);
  95                         break;
  96                 case ARCH_TIMER_REG_TVAL:
  97                         writel_relaxed(val, timer->base + CNTV_TVAL);
  98                         break;
  99                 }
 100         } else {
 101                 arch_timer_reg_write_cp15(access, reg, val);
 102         }
 103 }
 104
 105 static __always_inline
 106 u32 arch_timer_reg_read(int access, enum arch_timer_reg reg,
 107                         struct clock_event_device *clk)
 108 {
 109         u32 val;
 110
 111         if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
 112                 struct arch_timer *timer = to_arch_timer(clk);
 113                 switch (reg) {
 114                 case ARCH_TIMER_REG_CTRL:
 115                         val = readl_relaxed(timer->base + CNTP_CTL);
 116                         break;
 117                 case ARCH_TIMER_REG_TVAL:
 118                         val = readl_relaxed(timer->base + CNTP_TVAL);
 119                         break;
 120                 }
 121         } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
 122                 struct arch_timer *timer = to_arch_timer(clk);
 123                 switch (reg) {
 124                 case ARCH_TIMER_REG_CTRL:
 125                         val = readl_relaxed(timer->base + CNTV_CTL);
 126                         break;
 127                 case ARCH_TIMER_REG_TVAL:
 128                         val = readl_relaxed(timer->base + CNTV_TVAL);
 129                         break;
 130                 }
 131         } else {
 132                 val = arch_timer_reg_read_cp15(access, reg);
 133         }
 134
 135         return val;
 136 }
 137
 138 static __always_inline irqreturn_t timer_handler(const int access,
 139                                         struct clock_event_device *evt)
 140 {
 141         unsigned long ctrl;
 142
 143         ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, evt);
 144         if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
 145                 ctrl |= ARCH_TIMER_CTRL_IT_MASK;
 146                 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, evt);
 147                 evt->event_handler(evt);
 148                 return IRQ_HANDLED;
 149         }
 150
 151         return IRQ_NONE;
 152 }
 153
 154 static irqreturn_t arch_timer_handler_virt(int irq, void *dev_id)
 155 {
 156         struct clock_event_device *evt = dev_id;
 157
 158         return timer_handler(ARCH_TIMER_VIRT_ACCESS, evt);
 159 }
 160
 161 static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id)
 162 {
 163         struct clock_event_device *evt = dev_id;
 164
 165         return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt);
 166 }
 167
 168 static irqreturn_t arch_timer_handler_phys_mem(int irq, void *dev_id)
 169 {
 170         struct clock_event_device *evt = dev_id;
 171
 172         return timer_handler(ARCH_TIMER_MEM_PHYS_ACCESS, evt);
 173 }
 174
 175 static irqreturn_t arch_timer_handler_virt_mem(int irq, void *dev_id)
 176 {
 177         struct clock_event_device *evt = dev_id;
 178
 179         return timer_handler(ARCH_TIMER_MEM_VIRT_ACCESS, evt);
 180 }
 181
 182 static __always_inline void timer_set_mode(const int access, int mode,
 183                                   struct clock_event_device *clk)
 184 {
 185         unsigned long ctrl;
 186         switch (mode) {
 187         case CLOCK_EVT_MODE_UNUSED:
 188         case CLOCK_EVT_MODE_SHUTDOWN:
 189                 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
 190                 ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
 191                 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
 192                 break;
 193         default:
 194                 break;
 195         }
 196 }
 197
 198 static void arch_timer_set_mode_virt(enum clock_event_mode mode,
 199                                      struct clock_event_device *clk)
 200 {
 201         timer_set_mode(ARCH_TIMER_VIRT_ACCESS, mode, clk);
 202 }
 203
 204 static void arch_timer_set_mode_phys(enum clock_event_mode mode,
 205                                      struct clock_event_device *clk)
 206 {
 207         timer_set_mode(ARCH_TIMER_PHYS_ACCESS, mode, clk);
 208 }
 209
 210 static void arch_timer_set_mode_virt_mem(enum clock_event_mode mode,
 211                                          struct clock_event_device *clk)
 212 {
 213         timer_set_mode(ARCH_TIMER_MEM_VIRT_ACCESS, mode, clk);
 214 }
 215
 216 static void arch_timer_set_mode_phys_mem(enum clock_event_mode mode,
 217                                          struct clock_event_device *clk)
 218 {
 219         timer_set_mode(ARCH_TIMER_MEM_PHYS_ACCESS, mode, clk);
 220 }
 221
 222 static __always_inline void set_next_event(const int access, unsigned long evt,
 223                                            struct clock_event_device *clk)
 224 {
 225         unsigned long ctrl;
 226         ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
 227         ctrl |= ARCH_TIMER_CTRL_ENABLE;
 228         ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
 229         arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt, clk);
 230         arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
 231 }
 232
 233 static int arch_timer_set_next_event_virt(unsigned long evt,
 234                                           struct clock_event_device *clk)
 235 {
 236         set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk);
 237         return 0;
 238 }
 239
 240 static int arch_timer_set_next_event_phys(unsigned long evt,
 241                                           struct clock_event_device *clk)
 242 {
 243         set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk);
 244         return 0;
 245 }
 246
 247 static int arch_timer_set_next_event_virt_mem(unsigned long evt,
 248                                               struct clock_event_device *clk)
 249 {
 250         set_next_event(ARCH_TIMER_MEM_VIRT_ACCESS, evt, clk);
 251         return 0;
 252 }
 253
 254 static int arch_timer_set_next_event_phys_mem(unsigned long evt,
 255                                               struct clock_event_device *clk)
 256 {
 257         set_next_event(ARCH_TIMER_MEM_PHYS_ACCESS, evt, clk);
 258         return 0;
 259 }
 260
 261 static void __arch_timer_setup(unsigned type,
 262                                struct clock_event_device *clk)
 263 {
 264         clk->features = CLOCK_EVT_FEAT_ONESHOT;
 265
 266         if (type == ARCH_CP15_TIMER) {
 267                 if (arch_timer_c3stop)
 268                         clk->features |= CLOCK_EVT_FEAT_C3STOP;
 269                 clk->name = "arch_sys_timer";
 270                 clk->rating = 450;
 271                 clk->cpumask = cpumask_of(smp_processor_id());
 272                 if (arch_timer_use_virtual) {
 273                         clk->irq = arch_timer_ppi[VIRT_PPI];
 274                         clk->set_mode = arch_timer_set_mode_virt;
 275                         clk->set_next_event = arch_timer_set_next_event_virt;
 276                 } else {
 277                         clk->irq = arch_timer_ppi[PHYS_SECURE_PPI];
 278                         clk->set_mode = arch_timer_set_mode_phys;
 279                         clk->set_next_event = arch_timer_set_next_event_phys;
 280                 }
 281         } else {
 282                 clk->features |= CLOCK_EVT_FEAT_DYNIRQ;
 283                 clk->name = "arch_mem_timer";
 284                 clk->rating = 400;
 285                 clk->cpumask = cpu_all_mask;
 286                 if (arch_timer_mem_use_virtual) {
 287                         clk->set_mode = arch_timer_set_mode_virt_mem;
 288                         clk->set_next_event =
 289                                 arch_timer_set_next_event_virt_mem;
 290                 } else {
 291                         clk->set_mode = arch_timer_set_mode_phys_mem;
 292                         clk->set_next_event =
 293                                 arch_timer_set_next_event_phys_mem;
 294                 }
 295         }
 296
 297         clk->set_mode(CLOCK_EVT_MODE_SHUTDOWN, clk);
 298
 299         clockevents_config_and_register(clk, arch_timer_rate, 0xf, 0x7fffffff);
 300 }
 301
 302 static void arch_timer_evtstrm_enable(int divider)
 303 {
 304         u32 cntkctl = arch_timer_get_cntkctl();
 305
 306         cntkctl &= ~ARCH_TIMER_EVT_TRIGGER_MASK;
 307         /* Set the divider and enable virtual event stream */
 308         cntkctl |= (divider << ARCH_TIMER_EVT_TRIGGER_SHIFT)
 309                         | ARCH_TIMER_VIRT_EVT_EN;
 310         arch_timer_set_cntkctl(cntkctl);
 311         elf_hwcap |= HWCAP_EVTSTRM;
 312 #ifdef CONFIG_COMPAT
 313         compat_elf_hwcap |= COMPAT_HWCAP_EVTSTRM;
 314 #endif
 315 }
 316
 317 static void arch_timer_configure_evtstream(void)
 318 {
 319         int evt_stream_div, pos;
 320
 321         /* Find the closest power of two to the divisor */
 322         evt_stream_div = arch_timer_rate / ARCH_TIMER_EVT_STREAM_FREQ;
 323         pos = fls(evt_stream_div);
 324         if (pos > 1 && !(evt_stream_div & (1 << (pos - 2))))
 325                 pos--;
 326         /* enable event stream */
 327         arch_timer_evtstrm_enable(min(pos, 15));
 328 }
 329
 330 static void arch_counter_set_user_access(void)
 331 {
 332         u32 cntkctl = arch_timer_get_cntkctl();
 333
 334         /* Disable user access to the timers and the physical counter */
 335         /* Also disable virtual event stream */
 336         cntkctl &= ~(ARCH_TIMER_USR_PT_ACCESS_EN
 337                         | ARCH_TIMER_USR_VT_ACCESS_EN
 338                         | ARCH_TIMER_VIRT_EVT_EN
 339                         | ARCH_TIMER_USR_PCT_ACCESS_EN);
 340
 341         /* Enable user access to the virtual counter */
 342         cntkctl |= ARCH_TIMER_USR_VCT_ACCESS_EN;
 343
 344         arch_timer_set_cntkctl(cntkctl);
 345 }
 346
 347 static int arch_timer_setup(struct clock_event_device *clk)
 348 {
 349         __arch_timer_setup(ARCH_CP15_TIMER, clk);
 350
 351         if (arch_timer_use_virtual)
 352                 enable_percpu_irq(arch_timer_ppi[VIRT_PPI], 0);
 353         else {
 354                 enable_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI], 0);
 355                 if (arch_timer_ppi[PHYS_NONSECURE_PPI])
 356                         enable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI], 0);
 357         }
 358
 359         arch_counter_set_user_access();
 360         if (IS_ENABLED(CONFIG_ARM_ARCH_TIMER_EVTSTREAM))
 361                 arch_timer_configure_evtstream();
 362
 363         return 0;
 364 }
 365
 366 static void
 367 arch_timer_detect_rate(void __iomem *cntbase, struct device_node *np)
 368 {
 369         /* Who has more than one independent system counter? */
 370         if (arch_timer_rate)
 371                 return;
 372
 373         /* Try to determine the frequency from the device tree or CNTFRQ */
 374         if (of_property_read_u32(np, "clock-frequency", &arch_timer_rate)) {
 375                 if (cntbase)
 376                         arch_timer_rate = readl_relaxed(cntbase + CNTFRQ);
 377                 else
 378                         arch_timer_rate = arch_timer_get_cntfrq();
 379         }
 380
 381         /* Check the timer frequency. */
 382         if (arch_timer_rate == 0)
 383                 pr_warn("Architected timer frequency not available\n");
 384 }
 385
 386 static void arch_timer_banner(unsigned type)
 387 {
 388         pr_info("Architected %s%s%s timer(s) running at %lu.%02luMHz (%s%s%s).\n",
 389                      type & ARCH_CP15_TIMER ? "cp15" : "",
 390                      type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ?  " and " : "",
 391                      type & ARCH_MEM_TIMER ? "mmio" : "",
 392                      (unsigned long)arch_timer_rate / 1000000,
 393                      (unsigned long)(arch_timer_rate / 10000) % 100,
 394                      type & ARCH_CP15_TIMER ?
 395                         arch_timer_use_virtual ? "virt" : "phys" :
 396                         "",
 397                      type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ?  "/" : "",
 398                      type & ARCH_MEM_TIMER ?
 399                         arch_timer_mem_use_virtual ? "virt" : "phys" :
 400                         "");
 401 }
 402
 403 u32 arch_timer_get_rate(void)
 404 {
 405         return arch_timer_rate;
 406 }
 407
 408 static u64 arch_counter_get_cntvct_mem(void)
 409 {
 410         u32 vct_lo, vct_hi, tmp_hi;
 411
 412         do {
 413                 vct_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);
 414                 vct_lo = readl_relaxed(arch_counter_base + CNTVCT_LO);
 415                 tmp_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);
 416         } while (vct_hi != tmp_hi);
 417
 418         return ((u64) vct_hi << 32) | vct_lo;
 419 }
 420
 421 /*
 422  * Default to cp15 based access because arm64 uses this function for
 423  * sched_clock() before DT is probed and the cp15 method is guaranteed
 424  * to exist on arm64. arm doesn't use this before DT is probed so even
 425  * if we don't have the cp15 accessors we won't have a problem.
 426  */
 427 u64 (*arch_timer_read_counter)(void) = arch_counter_get_cntvct;
 428
 429 static cycle_t arch_counter_read(struct clocksource *cs)
 430 {
 431         return arch_timer_read_counter();
 432 }
 433
 434 static cycle_t arch_counter_read_cc(const struct cyclecounter *cc)
 435 {
 436         return arch_timer_read_counter();
 437 }
 438
 439 static struct clocksource clocksource_counter = {
 440         .name   = "arch_sys_counter",
 441         .rating = 400,
 442         .read   = arch_counter_read,
 443         .mask   = CLOCKSOURCE_MASK(56),
 444         .flags  = CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTOP,
 445 };
 446
 447 static struct cyclecounter cyclecounter = {
 448         .read   = arch_counter_read_cc,
 449         .mask   = CLOCKSOURCE_MASK(56),
 450 };
 451
 452 static struct timecounter timecounter;
 453
 454 struct timecounter *arch_timer_get_timecounter(void)
 455 {
 456         return &timecounter;
 457 }
 458
 459 static void __init arch_counter_register(unsigned type)
 460 {
 461         u64 start_count;
 462
 463         /* Register the CP15 based counter if we have one */
 464         if (type & ARCH_CP15_TIMER) {
 465                 arch_timer_read_counter = arch_counter_get_cntvct;
 466         } else {
 467                 arch_timer_read_counter = arch_counter_get_cntvct_mem;
 468
 469                 /* If the clocksource name is "arch_sys_counter" the
 470                  * VDSO will attempt to read the CP15-based counter.
 471                  * Ensure this does not happen when CP15-based
 472                  * counter is not available.
 473                  */
 474                 clocksource_counter.name = "arch_mem_counter";
 475         }
 476
 477         start_count = arch_timer_read_counter();
 478         clocksource_register_hz(&clocksource_counter, arch_timer_rate);
 479         cyclecounter.mult = clocksource_counter.mult;
 480         cyclecounter.shift = clocksource_counter.shift;
 481         timecounter_init(&timecounter, &cyclecounter, start_count);
 482
 483         /* 56 bits minimum, so we assume worst case rollover */
 484         sched_clock_register(arch_timer_read_counter, 56, arch_timer_rate);
 485 }
 486
 487 static void arch_timer_stop(struct clock_event_device *clk)
 488 {
 489         pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n",
 490                  clk->irq, smp_processor_id());
 491
 492         if (arch_timer_use_virtual)
 493                 disable_percpu_irq(arch_timer_ppi[VIRT_PPI]);
 494         else {
 495                 disable_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI]);
 496                 if (arch_timer_ppi[PHYS_NONSECURE_PPI])
 497                         disable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI]);
 498         }
 499
 500         clk->set_mode(CLOCK_EVT_MODE_UNUSED, clk);
 501 }
 502
 503 static int arch_timer_cpu_notify(struct notifier_block *self,
 504                                            unsigned long action, void *hcpu)
 505 {
 506         /*
 507          * Grab cpu pointer in each case to avoid spurious
 508          * preemptible warnings
 509          */
 510         switch (action & ~CPU_TASKS_FROZEN) {
 511         case CPU_STARTING:
 512                 arch_timer_setup(this_cpu_ptr(arch_timer_evt));
 513                 break;
 514         case CPU_DYING:
 515                 arch_timer_stop(this_cpu_ptr(arch_timer_evt));
 516                 break;
 517         }
 518
 519         return NOTIFY_OK;
 520 }
 521
 522 static struct notifier_block arch_timer_cpu_nb = {
 523         .notifier_call = arch_timer_cpu_notify,
 524 };
 525
 526 #ifdef CONFIG_CPU_PM
 527 static unsigned int saved_cntkctl;
 528 static int arch_timer_cpu_pm_notify(struct notifier_block *self,
 529                                     unsigned long action, void *hcpu)
 530 {
 531         if (action == CPU_PM_ENTER)
 532                 saved_cntkctl = arch_timer_get_cntkctl();
 533         else if (action == CPU_PM_ENTER_FAILED || action == CPU_PM_EXIT)
 534                 arch_timer_set_cntkctl(saved_cntkctl);
 535         return NOTIFY_OK;
 536 }
 537
 538 static struct notifier_block arch_timer_cpu_pm_notifier = {
 539         .notifier_call = arch_timer_cpu_pm_notify,
 540 };
 541
 542 static int __init arch_timer_cpu_pm_init(void)
 543 {
 544         return cpu_pm_register_notifier(&arch_timer_cpu_pm_notifier);
 545 }
 546 #else
 547 static int __init arch_timer_cpu_pm_init(void)
 548 {
 549         return 0;
 550 }
 551 #endif
 552
 553 static int __init arch_timer_register(void)
 554 {
 555         int err;
 556         int ppi;
 557
 558         arch_timer_evt = alloc_percpu(struct clock_event_device);
 559         if (!arch_timer_evt) {
 560                 err = -ENOMEM;
 561                 goto out;
 562         }
 563
 564         if (arch_timer_use_virtual) {
 565                 ppi = arch_timer_ppi[VIRT_PPI];
 566                 err = request_percpu_irq(ppi, arch_timer_handler_virt,
 567                                          "arch_timer", arch_timer_evt);
 568         } else {
 569                 ppi = arch_timer_ppi[PHYS_SECURE_PPI];
 570                 err = request_percpu_irq(ppi, arch_timer_handler_phys,
 571                                          "arch_timer", arch_timer_evt);
 572                 if (!err && arch_timer_ppi[PHYS_NONSECURE_PPI]) {
 573                         ppi = arch_timer_ppi[PHYS_NONSECURE_PPI];
 574                         err = request_percpu_irq(ppi, arch_timer_handler_phys,
 575                                                  "arch_timer", arch_timer_evt);
 576                         if (err)
 577                                 free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI],
 578                                                 arch_timer_evt);
 579                 }
 580         }
 581
 582         if (err) {
 583                 pr_err("arch_timer: can't register interrupt %d (%d)\n",
 584                        ppi, err);
 585                 goto out_free;
 586         }
 587
 588         err = register_cpu_notifier(&arch_timer_cpu_nb);
 589         if (err)
 590                 goto out_free_irq;
 591
 592         err = arch_timer_cpu_pm_init();
 593         if (err)
 594                 goto out_unreg_notify;
 595
 596         /* Immediately configure the timer on the boot CPU */
 597         arch_timer_setup(this_cpu_ptr(arch_timer_evt));
 598
 599         return 0;
 600
 601 out_unreg_notify:
 602         unregister_cpu_notifier(&arch_timer_cpu_nb);
 603 out_free_irq:
 604         if (arch_timer_use_virtual)
 605                 free_percpu_irq(arch_timer_ppi[VIRT_PPI], arch_timer_evt);
 606         else {
 607                 free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI],
 608                                 arch_timer_evt);
 609                 if (arch_timer_ppi[PHYS_NONSECURE_PPI])
 610                         free_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI],
 611                                         arch_timer_evt);
 612         }
 613
 614 out_free:
 615         free_percpu(arch_timer_evt);
 616 out:
 617         return err;
 618 }
 619
 620 static int __init arch_timer_mem_register(void __iomem *base, unsigned int irq)
 621 {
 622         int ret;
 623         irq_handler_t func;
 624         struct arch_timer *t;
 625
 626         t = kzalloc(sizeof(*t), GFP_KERNEL);
 627         if (!t)
 628                 return -ENOMEM;
 629
 630         t->base = base;
 631         t->evt.irq = irq;
 632         __arch_timer_setup(ARCH_MEM_TIMER, &t->evt);
 633
 634         if (arch_timer_mem_use_virtual)
 635                 func = arch_timer_handler_virt_mem;
 636         else
 637                 func = arch_timer_handler_phys_mem;
 638
 639         ret = request_irq(irq, func, IRQF_TIMER, "arch_mem_timer", &t->evt);
 640         if (ret) {
 641                 pr_err("arch_timer: Failed to request mem timer irq\n");
 642                 kfree(t);
 643         }
 644
 645         return ret;
 646 }
 647
 648 static const struct of_device_id arch_timer_of_match[] __initconst = {
 649         { .compatible   = "arm,armv7-timer",    },
 650         { .compatible   = "arm,armv8-timer",    },
 651         {},
 652 };
 653
 654 static const struct of_device_id arch_timer_mem_of_match[] __initconst = {
 655         { .compatible   = "arm,armv7-timer-mem", },
 656         {},
 657 };
 658
 659 static bool __init
 660 arch_timer_probed(int type, const struct of_device_id *matches)
 661 {
 662         struct device_node *dn;
 663         bool probed = false;
 664
 665         dn = of_find_matching_node(NULL, matches);
 666         if (dn && of_device_is_available(dn) && (arch_timers_present & type))
 667                 probed = true;
 668         of_node_put(dn);
 669
 670         return probed;
 671 }
 672
 673 static void __init arch_timer_common_init(void)
 674 {
 675         unsigned mask = ARCH_CP15_TIMER | ARCH_MEM_TIMER;
 676
 677         /* Wait until both nodes are probed if we have two timers */
 678         if ((arch_timers_present & mask) != mask) {
 679                 if (!arch_timer_probed(ARCH_MEM_TIMER, arch_timer_mem_of_match))
 680                         return;
 681                 if (!arch_timer_probed(ARCH_CP15_TIMER, arch_timer_of_match))
 682                         return;
 683         }
 684
 685         arch_timer_banner(arch_timers_present);
 686         arch_counter_register(arch_timers_present);
 687         arch_timer_arch_init();
 688 }
 689
 690 static void __init arch_timer_init(struct device_node *np)
 691 {
 692         int i;
 693
 694         if (arch_timers_present & ARCH_CP15_TIMER) {
 695                 pr_warn("arch_timer: multiple nodes in dt, skipping\n");
 696                 return;
 697         }
 698
 699         arch_timers_present |= ARCH_CP15_TIMER;
 700         for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++)
 701                 arch_timer_ppi[i] = irq_of_parse_and_map(np, i);
 702         arch_timer_detect_rate(NULL, np);
 703
 704         /*
 705          * If HYP mode is available, we know that the physical timer
 706          * has been configured to be accessible from PL1. Use it, so
 707          * that a guest can use the virtual timer instead.
 708          *
 709          * If no interrupt provided for virtual timer, we'll have to
 710          * stick to the physical timer. It'd better be accessible...
 711          */
 712         if (is_hyp_mode_available() || !arch_timer_ppi[VIRT_PPI]) {
 713                 arch_timer_use_virtual = false;
 714
 715                 if (!arch_timer_ppi[PHYS_SECURE_PPI] ||
 716                     !arch_timer_ppi[PHYS_NONSECURE_PPI]) {
 717                         pr_warn("arch_timer: No interrupt available, giving up\n");
 718                         return;
 719                 }
 720         }
 721
 722         arch_timer_c3stop = !of_property_read_bool(np, "always-on");
 723
 724         arch_timer_register();
 725         arch_timer_common_init();
 726 }
 727 CLOCKSOURCE_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_init);
 728 CLOCKSOURCE_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_init);
 729
 730 static void __init arch_timer_mem_init(struct device_node *np)
 731 {
 732         struct device_node *frame, *best_frame = NULL;
 733         void __iomem *cntctlbase, *base;
 734         unsigned int irq;
 735         u32 cnttidr;
 736
 737         arch_timers_present |= ARCH_MEM_TIMER;
 738         cntctlbase = of_iomap(np, 0);
 739         if (!cntctlbase) {
 740                 pr_err("arch_timer: Can't find CNTCTLBase\n");
 741                 return;
 742         }
 743
 744         cnttidr = readl_relaxed(cntctlbase + CNTTIDR);
 745         iounmap(cntctlbase);
 746
 747         /*
 748          * Try to find a virtual capable frame. Otherwise fall back to a
 749          * physical capable frame.
 750          */
 751         for_each_available_child_of_node(np, frame) {
 752                 int n;
 753
 754                 if (of_property_read_u32(frame, "frame-number", &n)) {
 755                         pr_err("arch_timer: Missing frame-number\n");
 756                         of_node_put(best_frame);
 757                         of_node_put(frame);
 758                         return;
 759                 }
 760
 761                 if (cnttidr & CNTTIDR_VIRT(n)) {
 762                         of_node_put(best_frame);
 763                         best_frame = frame;
 764                         arch_timer_mem_use_virtual = true;
 765                         break;
 766                 }
 767                 of_node_put(best_frame);
 768                 best_frame = of_node_get(frame);
 769         }
 770
 771         base = arch_counter_base = of_iomap(best_frame, 0);
 772         if (!base) {
 773                 pr_err("arch_timer: Can't map frame's registers\n");
 774                 of_node_put(best_frame);
 775                 return;
 776         }
 777
 778         if (arch_timer_mem_use_virtual)
 779                 irq = irq_of_parse_and_map(best_frame, 1);
 780         else
 781                 irq = irq_of_parse_and_map(best_frame, 0);
 782         of_node_put(best_frame);
 783         if (!irq) {
 784                 pr_err("arch_timer: Frame missing %s irq",
 785                        arch_timer_mem_use_virtual ? "virt" : "phys");
 786                 return;
 787         }
 788
 789         arch_timer_detect_rate(base, np);
 790         arch_timer_mem_register(base, irq);
 791         arch_timer_common_init();
 792 }
 793 CLOCKSOURCE_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem",
 794                        arch_timer_mem_init);