drivers/cpufreq/intel_pstate.c

   1 /*
   2  * intel_pstate.c: Native P state management for Intel processors
   3  *
   4  * (C) Copyright 2012 Intel Corporation
   5  * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; version 2
  10  * of the License.
  11  */
  12
  13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  14
  15 #include <linux/kernel.h>
  16 #include <linux/kernel_stat.h>
  17 #include <linux/module.h>
  18 #include <linux/ktime.h>
  19 #include <linux/hrtimer.h>
  20 #include <linux/tick.h>
  21 #include <linux/slab.h>
  22 #include <linux/sched.h>
  23 #include <linux/list.h>
  24 #include <linux/cpu.h>
  25 #include <linux/cpufreq.h>
  26 #include <linux/sysfs.h>
  27 #include <linux/types.h>
  28 #include <linux/fs.h>
  29 #include <linux/debugfs.h>
  30 #include <linux/acpi.h>
  31 #include <linux/vmalloc.h>
  32 #include <trace/events/power.h>
  33
  34 #include <asm/div64.h>
  35 #include <asm/msr.h>
  36 #include <asm/cpu_device_id.h>
  37 #include <asm/cpufeature.h>
  38
  39 #define ATOM_RATIOS             0x66a
  40 #define ATOM_VIDS               0x66b
  41 #define ATOM_TURBO_RATIOS       0x66c
  42 #define ATOM_TURBO_VIDS         0x66d
  43
  44 #define FRAC_BITS 8
  45 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
  46 #define fp_toint(X) ((X) >> FRAC_BITS)
  47
  48 static inline int32_t mul_fp(int32_t x, int32_t y)
  49 {
  50         return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
  51 }
  52
  53 static inline int32_t div_fp(s64 x, s64 y)
  54 {
  55         return div64_s64((int64_t)x << FRAC_BITS, y);
  56 }
  57
  58 static inline int ceiling_fp(int32_t x)
  59 {
  60         int mask, ret;
  61
  62         ret = fp_toint(x);
  63         mask = (1 << FRAC_BITS) - 1;
  64         if (x & mask)
  65                 ret += 1;
  66         return ret;
  67 }
  68
  69 /**
  70  * struct sample -      Store performance sample
  71  * @core_pct_busy:      Ratio of APERF/MPERF in percent, which is actual
  72  *                      performance during last sample period
  73  * @busy_scaled:        Scaled busy value which is used to calculate next
  74  *                      P state. This can be different than core_pct_busy
  75  *                      to account for cpu idle period
  76  * @aperf:              Difference of actual performance frequency clock count
  77  *                      read from APERF MSR between last and current sample
  78  * @mperf:              Difference of maximum performance frequency clock count
  79  *                      read from MPERF MSR between last and current sample
  80  * @tsc:                Difference of time stamp counter between last and
  81  *                      current sample
  82  * @freq:               Effective frequency calculated from APERF/MPERF
  83  * @time:               Current time from scheduler
  84  *
  85  * This structure is used in the cpudata structure to store performance sample
  86  * data for choosing next P State.
  87  */
  88 struct sample {
  89         int32_t core_pct_busy;
  90         int32_t busy_scaled;
  91         u64 aperf;
  92         u64 mperf;
  93         u64 tsc;
  94         int freq;
  95         u64 time;
  96 };
  97
  98 /**
  99  * struct pstate_data - Store P state data
 100  * @current_pstate:     Current requested P state
 101  * @min_pstate:         Min P state possible for this platform
 102  * @max_pstate:         Max P state possible for this platform
 103  * @max_pstate_physical:This is physical Max P state for a processor
 104  *                      This can be higher than the max_pstate which can
 105  *                      be limited by platform thermal design power limits
 106  * @scaling:            Scaling factor to  convert frequency to cpufreq
 107  *                      frequency units
 108  * @turbo_pstate:       Max Turbo P state possible for this platform
 109  *
 110  * Stores the per cpu model P state limits and current P state.
 111  */
 112 struct pstate_data {
 113         int     current_pstate;
 114         int     min_pstate;
 115         int     max_pstate;
 116         int     max_pstate_physical;
 117         int     scaling;
 118         int     turbo_pstate;
 119 };
 120
 121 /**
 122  * struct vid_data -    Stores voltage information data
 123  * @min:                VID data for this platform corresponding to
 124  *                      the lowest P state
 125  * @max:                VID data corresponding to the highest P State.
 126  * @turbo:              VID data for turbo P state
 127  * @ratio:              Ratio of (vid max - vid min) /
 128  *                      (max P state - Min P State)
 129  *
 130  * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
 131  * This data is used in Atom platforms, where in addition to target P state,
 132  * the voltage data needs to be specified to select next P State.
 133  */
 134 struct vid_data {
 135         int min;
 136         int max;
 137         int turbo;
 138         int32_t ratio;
 139 };
 140
 141 /**
 142  * struct _pid -        Stores PID data
 143  * @setpoint:           Target set point for busyness or performance
 144  * @integral:           Storage for accumulated error values
 145  * @p_gain:             PID proportional gain
 146  * @i_gain:             PID integral gain
 147  * @d_gain:             PID derivative gain
 148  * @deadband:           PID deadband
 149  * @last_err:           Last error storage for integral part of PID calculation
 150  *
 151  * Stores PID coefficients and last error for PID controller.
 152  */
 153 struct _pid {
 154         int setpoint;
 155         int32_t integral;
 156         int32_t p_gain;
 157         int32_t i_gain;
 158         int32_t d_gain;
 159         int deadband;
 160         int32_t last_err;
 161 };
 162
 163 /**
 164  * struct cpudata -     Per CPU instance data storage
 165  * @cpu:                CPU number for this instance data
 166  * @update_util:        CPUFreq utility callback information
 167  * @pstate:             Stores P state limits for this CPU
 168  * @vid:                Stores VID limits for this CPU
 169  * @pid:                Stores PID parameters for this CPU
 170  * @last_sample_time:   Last Sample time
 171  * @prev_aperf:         Last APERF value read from APERF MSR
 172  * @prev_mperf:         Last MPERF value read from MPERF MSR
 173  * @prev_tsc:           Last timestamp counter (TSC) value
 174  * @prev_cummulative_iowait: IO Wait time difference from last and
 175  *                      current sample
 176  * @sample:             Storage for storing last Sample data
 177  *
 178  * This structure stores per CPU instance data for all CPUs.
 179  */
 180 struct cpudata {
 181         int cpu;
 182
 183         struct update_util_data update_util;
 184
 185         struct pstate_data pstate;
 186         struct vid_data vid;
 187         struct _pid pid;
 188
 189         u64     last_sample_time;
 190         u64     prev_aperf;
 191         u64     prev_mperf;
 192         u64     prev_tsc;
 193         u64     prev_cummulative_iowait;
 194         struct sample sample;
 195 };
 196
 197 static struct cpudata **all_cpu_data;
 198
 199 /**
 200  * struct pid_adjust_policy - Stores static PID configuration data
 201  * @sample_rate_ms:     PID calculation sample rate in ms
 202  * @sample_rate_ns:     Sample rate calculation in ns
 203  * @deadband:           PID deadband
 204  * @setpoint:           PID Setpoint
 205  * @p_gain_pct:         PID proportional gain
 206  * @i_gain_pct:         PID integral gain
 207  * @d_gain_pct:         PID derivative gain
 208  *
 209  * Stores per CPU model static PID configuration data.
 210  */
 211 struct pstate_adjust_policy {
 212         int sample_rate_ms;
 213         s64 sample_rate_ns;
 214         int deadband;
 215         int setpoint;
 216         int p_gain_pct;
 217         int d_gain_pct;
 218         int i_gain_pct;
 219 };
 220
 221 /**
 222  * struct pstate_funcs - Per CPU model specific callbacks
 223  * @get_max:            Callback to get maximum non turbo effective P state
 224  * @get_max_physical:   Callback to get maximum non turbo physical P state
 225  * @get_min:            Callback to get minimum P state
 226  * @get_turbo:          Callback to get turbo P state
 227  * @get_scaling:        Callback to get frequency scaling factor
 228  * @get_val:            Callback to convert P state to actual MSR write value
 229  * @get_vid:            Callback to get VID data for Atom platforms
 230  * @get_target_pstate:  Callback to a function to calculate next P state to use
 231  *
 232  * Core and Atom CPU models have different way to get P State limits. This
 233  * structure is used to store those callbacks.
 234  */
 235 struct pstate_funcs {
 236         int (*get_max)(void);
 237         int (*get_max_physical)(void);
 238         int (*get_min)(void);
 239         int (*get_turbo)(void);
 240         int (*get_scaling)(void);
 241         u64 (*get_val)(struct cpudata*, int pstate);
 242         void (*get_vid)(struct cpudata *);
 243         int32_t (*get_target_pstate)(struct cpudata *);
 244 };
 245
 246 /**
 247  * struct cpu_defaults- Per CPU model default config data
 248  * @pid_policy: PID config data
 249  * @funcs:              Callback function data
 250  */
 251 struct cpu_defaults {
 252         struct pstate_adjust_policy pid_policy;
 253         struct pstate_funcs funcs;
 254 };
 255
 256 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu);
 257 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu);
 258
 259 static struct pstate_adjust_policy pid_params;
 260 static struct pstate_funcs pstate_funcs;
 261 static int hwp_active;
 262
 263
 264 /**
 265  * struct perf_limits - Store user and policy limits
 266  * @no_turbo:           User requested turbo state from intel_pstate sysfs
 267  * @turbo_disabled:     Platform turbo status either from msr
 268  *                      MSR_IA32_MISC_ENABLE or when maximum available pstate
 269  *                      matches the maximum turbo pstate
 270  * @max_perf_pct:       Effective maximum performance limit in percentage, this
 271  *                      is minimum of either limits enforced by cpufreq policy
 272  *                      or limits from user set limits via intel_pstate sysfs
 273  * @min_perf_pct:       Effective minimum performance limit in percentage, this
 274  *                      is maximum of either limits enforced by cpufreq policy
 275  *                      or limits from user set limits via intel_pstate sysfs
 276  * @max_perf:           This is a scaled value between 0 to 255 for max_perf_pct
 277  *                      This value is used to limit max pstate
 278  * @min_perf:           This is a scaled value between 0 to 255 for min_perf_pct
 279  *                      This value is used to limit min pstate
 280  * @max_policy_pct:     The maximum performance in percentage enforced by
 281  *                      cpufreq setpolicy interface
 282  * @max_sysfs_pct:      The maximum performance in percentage enforced by
 283  *                      intel pstate sysfs interface
 284  * @min_policy_pct:     The minimum performance in percentage enforced by
 285  *                      cpufreq setpolicy interface
 286  * @min_sysfs_pct:      The minimum performance in percentage enforced by
 287  *                      intel pstate sysfs interface
 288  *
 289  * Storage for user and policy defined limits.
 290  */
 291 struct perf_limits {
 292         int no_turbo;
 293         int turbo_disabled;
 294         int max_perf_pct;
 295         int min_perf_pct;
 296         int32_t max_perf;
 297         int32_t min_perf;
 298         int max_policy_pct;
 299         int max_sysfs_pct;
 300         int min_policy_pct;
 301         int min_sysfs_pct;
 302 };
 303
 304 static struct perf_limits performance_limits = {
 305         .no_turbo = 0,
 306         .turbo_disabled = 0,
 307         .max_perf_pct = 100,
 308         .max_perf = int_tofp(1),
 309         .min_perf_pct = 100,
 310         .min_perf = int_tofp(1),
 311         .max_policy_pct = 100,
 312         .max_sysfs_pct = 100,
 313         .min_policy_pct = 0,
 314         .min_sysfs_pct = 0,
 315 };
 316
 317 static struct perf_limits powersave_limits = {
 318         .no_turbo = 0,
 319         .turbo_disabled = 0,
 320         .max_perf_pct = 100,
 321         .max_perf = int_tofp(1),
 322         .min_perf_pct = 0,
 323         .min_perf = 0,
 324         .max_policy_pct = 100,
 325         .max_sysfs_pct = 100,
 326         .min_policy_pct = 0,
 327         .min_sysfs_pct = 0,
 328 };
 329
 330 #ifdef CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE
 331 static struct perf_limits *limits = &performance_limits;
 332 #else
 333 static struct perf_limits *limits = &powersave_limits;
 334 #endif
 335
 336 static inline void pid_reset(struct _pid *pid, int setpoint, int busy,
 337                              int deadband, int integral) {
 338         pid->setpoint = int_tofp(setpoint);
 339         pid->deadband  = int_tofp(deadband);
 340         pid->integral  = int_tofp(integral);
 341         pid->last_err  = int_tofp(setpoint) - int_tofp(busy);
 342 }
 343
 344 static inline void pid_p_gain_set(struct _pid *pid, int percent)
 345 {
 346         pid->p_gain = div_fp(percent, 100);
 347 }
 348
 349 static inline void pid_i_gain_set(struct _pid *pid, int percent)
 350 {
 351         pid->i_gain = div_fp(percent, 100);
 352 }
 353
 354 static inline void pid_d_gain_set(struct _pid *pid, int percent)
 355 {
 356         pid->d_gain = div_fp(percent, 100);
 357 }
 358
 359 static signed int pid_calc(struct _pid *pid, int32_t busy)
 360 {
 361         signed int result;
 362         int32_t pterm, dterm, fp_error;
 363         int32_t integral_limit;
 364
 365         fp_error = pid->setpoint - busy;
 366
 367         if (abs(fp_error) <= pid->deadband)
 368                 return 0;
 369
 370         pterm = mul_fp(pid->p_gain, fp_error);
 371
 372         pid->integral += fp_error;
 373
 374         /*
 375          * We limit the integral here so that it will never
 376          * get higher than 30.  This prevents it from becoming
 377          * too large an input over long periods of time and allows
 378          * it to get factored out sooner.
 379          *
 380          * The value of 30 was chosen through experimentation.
 381          */
 382         integral_limit = int_tofp(30);
 383         if (pid->integral > integral_limit)
 384                 pid->integral = integral_limit;
 385         if (pid->integral < -integral_limit)
 386                 pid->integral = -integral_limit;
 387
 388         dterm = mul_fp(pid->d_gain, fp_error - pid->last_err);
 389         pid->last_err = fp_error;
 390
 391         result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm;
 392         result = result + (1 << (FRAC_BITS-1));
 393         return (signed int)fp_toint(result);
 394 }
 395
 396 static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu)
 397 {
 398         pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct);
 399         pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct);
 400         pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct);
 401
 402         pid_reset(&cpu->pid, pid_params.setpoint, 100, pid_params.deadband, 0);
 403 }
 404
 405 static inline void intel_pstate_reset_all_pid(void)
 406 {
 407         unsigned int cpu;
 408
 409         for_each_online_cpu(cpu) {
 410                 if (all_cpu_data[cpu])
 411                         intel_pstate_busy_pid_reset(all_cpu_data[cpu]);
 412         }
 413 }
 414
 415 static inline void update_turbo_state(void)
 416 {
 417         u64 misc_en;
 418         struct cpudata *cpu;
 419
 420         cpu = all_cpu_data[0];
 421         rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
 422         limits->turbo_disabled =
 423                 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
 424                  cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
 425 }
 426
 427 static void intel_pstate_hwp_set(const struct cpumask *cpumask)
 428 {
 429         int min, hw_min, max, hw_max, cpu, range, adj_range;
 430         u64 value, cap;
 431
 432         rdmsrl(MSR_HWP_CAPABILITIES, cap);
 433         hw_min = HWP_LOWEST_PERF(cap);
 434         hw_max = HWP_HIGHEST_PERF(cap);
 435         range = hw_max - hw_min;
 436
 437         for_each_cpu(cpu, cpumask) {
 438                 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
 439                 adj_range = limits->min_perf_pct * range / 100;
 440                 min = hw_min + adj_range;
 441                 value &= ~HWP_MIN_PERF(~0L);
 442                 value |= HWP_MIN_PERF(min);
 443
 444                 adj_range = limits->max_perf_pct * range / 100;
 445                 max = hw_min + adj_range;
 446                 if (limits->no_turbo) {
 447                         hw_max = HWP_GUARANTEED_PERF(cap);
 448                         if (hw_max < max)
 449                                 max = hw_max;
 450                 }
 451
 452                 value &= ~HWP_MAX_PERF(~0L);
 453                 value |= HWP_MAX_PERF(max);
 454                 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
 455         }
 456 }
 457
 458 static void intel_pstate_hwp_set_online_cpus(void)
 459 {
 460         get_online_cpus();
 461         intel_pstate_hwp_set(cpu_online_mask);
 462         put_online_cpus();
 463 }
 464
 465 /************************** debugfs begin ************************/
 466 static int pid_param_set(void *data, u64 val)
 467 {
 468         *(u32 *)data = val;
 469         intel_pstate_reset_all_pid();
 470         return 0;
 471 }
 472
 473 static int pid_param_get(void *data, u64 *val)
 474 {
 475         *val = *(u32 *)data;
 476         return 0;
 477 }
 478 DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n");
 479
 480 struct pid_param {
 481         char *name;
 482         void *value;
 483 };
 484
 485 static struct pid_param pid_files[] = {
 486         {"sample_rate_ms", &pid_params.sample_rate_ms},
 487         {"d_gain_pct", &pid_params.d_gain_pct},
 488         {"i_gain_pct", &pid_params.i_gain_pct},
 489         {"deadband", &pid_params.deadband},
 490         {"setpoint", &pid_params.setpoint},
 491         {"p_gain_pct", &pid_params.p_gain_pct},
 492         {NULL, NULL}
 493 };
 494
 495 static void __init intel_pstate_debug_expose_params(void)
 496 {
 497         struct dentry *debugfs_parent;
 498         int i = 0;
 499
 500         if (hwp_active)
 501                 return;
 502         debugfs_parent = debugfs_create_dir("pstate_snb", NULL);
 503         if (IS_ERR_OR_NULL(debugfs_parent))
 504                 return;
 505         while (pid_files[i].name) {
 506                 debugfs_create_file(pid_files[i].name, 0660,
 507                                     debugfs_parent, pid_files[i].value,
 508                                     &fops_pid_param);
 509                 i++;
 510         }
 511 }
 512
 513 /************************** debugfs end ************************/
 514
 515 /************************** sysfs begin ************************/
 516 #define show_one(file_name, object)                                     \
 517         static ssize_t show_##file_name                                 \
 518         (struct kobject *kobj, struct attribute *attr, char *buf)       \
 519         {                                                               \
 520                 return sprintf(buf, "%u\n", limits->object);            \
 521         }
 522
 523 static ssize_t show_turbo_pct(struct kobject *kobj,
 524                                 struct attribute *attr, char *buf)
 525 {
 526         struct cpudata *cpu;
 527         int total, no_turbo, turbo_pct;
 528         uint32_t turbo_fp;
 529
 530         cpu = all_cpu_data[0];
 531
 532         total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
 533         no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
 534         turbo_fp = div_fp(no_turbo, total);
 535         turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
 536         return sprintf(buf, "%u\n", turbo_pct);
 537 }
 538
 539 static ssize_t show_num_pstates(struct kobject *kobj,
 540                                 struct attribute *attr, char *buf)
 541 {
 542         struct cpudata *cpu;
 543         int total;
 544
 545         cpu = all_cpu_data[0];
 546         total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
 547         return sprintf(buf, "%u\n", total);
 548 }
 549
 550 static ssize_t show_no_turbo(struct kobject *kobj,
 551                              struct attribute *attr, char *buf)
 552 {
 553         ssize_t ret;
 554
 555         update_turbo_state();
 556         if (limits->turbo_disabled)
 557                 ret = sprintf(buf, "%u\n", limits->turbo_disabled);
 558         else
 559                 ret = sprintf(buf, "%u\n", limits->no_turbo);
 560
 561         return ret;
 562 }
 563
 564 static ssize_t store_no_turbo(struct kobject *a, struct attribute *b,
 565                               const char *buf, size_t count)
 566 {
 567         unsigned int input;
 568         int ret;
 569
 570         ret = sscanf(buf, "%u", &input);
 571         if (ret != 1)
 572                 return -EINVAL;
 573
 574         update_turbo_state();
 575         if (limits->turbo_disabled) {
 576                 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
 577                 return -EPERM;
 578         }
 579
 580         limits->no_turbo = clamp_t(int, input, 0, 1);
 581
 582         if (hwp_active)
 583                 intel_pstate_hwp_set_online_cpus();
 584
 585         return count;
 586 }
 587
 588 static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b,
 589                                   const char *buf, size_t count)
 590 {
 591         unsigned int input;
 592         int ret;
 593
 594         ret = sscanf(buf, "%u", &input);
 595         if (ret != 1)
 596                 return -EINVAL;
 597
 598         limits->max_sysfs_pct = clamp_t(int, input, 0 , 100);
 599         limits->max_perf_pct = min(limits->max_policy_pct,
 600                                    limits->max_sysfs_pct);
 601         limits->max_perf_pct = max(limits->min_policy_pct,
 602                                    limits->max_perf_pct);
 603         limits->max_perf_pct = max(limits->min_perf_pct,
 604                                    limits->max_perf_pct);
 605         limits->max_perf = div_fp(limits->max_perf_pct, 100);
 606
 607         if (hwp_active)
 608                 intel_pstate_hwp_set_online_cpus();
 609         return count;
 610 }
 611
 612 static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b,
 613                                   const char *buf, size_t count)
 614 {
 615         unsigned int input;
 616         int ret;
 617
 618         ret = sscanf(buf, "%u", &input);
 619         if (ret != 1)
 620                 return -EINVAL;
 621
 622         limits->min_sysfs_pct = clamp_t(int, input, 0 , 100);
 623         limits->min_perf_pct = max(limits->min_policy_pct,
 624                                    limits->min_sysfs_pct);
 625         limits->min_perf_pct = min(limits->max_policy_pct,
 626                                    limits->min_perf_pct);
 627         limits->min_perf_pct = min(limits->max_perf_pct,
 628                                    limits->min_perf_pct);
 629         limits->min_perf = div_fp(limits->min_perf_pct, 100);
 630
 631         if (hwp_active)
 632                 intel_pstate_hwp_set_online_cpus();
 633         return count;
 634 }
 635
 636 show_one(max_perf_pct, max_perf_pct);
 637 show_one(min_perf_pct, min_perf_pct);
 638
 639 define_one_global_rw(no_turbo);
 640 define_one_global_rw(max_perf_pct);
 641 define_one_global_rw(min_perf_pct);
 642 define_one_global_ro(turbo_pct);
 643 define_one_global_ro(num_pstates);
 644
 645 static struct attribute *intel_pstate_attributes[] = {
 646         &no_turbo.attr,
 647         &max_perf_pct.attr,
 648         &min_perf_pct.attr,
 649         &turbo_pct.attr,
 650         &num_pstates.attr,
 651         NULL
 652 };
 653
 654 static struct attribute_group intel_pstate_attr_group = {
 655         .attrs = intel_pstate_attributes,
 656 };
 657
 658 static void __init intel_pstate_sysfs_expose_params(void)
 659 {
 660         struct kobject *intel_pstate_kobject;
 661         int rc;
 662
 663         intel_pstate_kobject = kobject_create_and_add("intel_pstate",
 664                                                 &cpu_subsys.dev_root->kobj);
 665         BUG_ON(!intel_pstate_kobject);
 666         rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
 667         BUG_ON(rc);
 668 }
 669 /************************** sysfs end ************************/
 670
 671 static void intel_pstate_hwp_enable(struct cpudata *cpudata)
 672 {
 673         /* First disable HWP notification interrupt as we don't process them */
 674         wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
 675
 676         wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
 677 }
 678
 679 static int atom_get_min_pstate(void)
 680 {
 681         u64 value;
 682
 683         rdmsrl(ATOM_RATIOS, value);
 684         return (value >> 8) & 0x7F;
 685 }
 686
 687 static int atom_get_max_pstate(void)
 688 {
 689         u64 value;
 690
 691         rdmsrl(ATOM_RATIOS, value);
 692         return (value >> 16) & 0x7F;
 693 }
 694
 695 static int atom_get_turbo_pstate(void)
 696 {
 697         u64 value;
 698
 699         rdmsrl(ATOM_TURBO_RATIOS, value);
 700         return value & 0x7F;
 701 }
 702
 703 static u64 atom_get_val(struct cpudata *cpudata, int pstate)
 704 {
 705         u64 val;
 706         int32_t vid_fp;
 707         u32 vid;
 708
 709         val = (u64)pstate << 8;
 710         if (limits->no_turbo && !limits->turbo_disabled)
 711                 val |= (u64)1 << 32;
 712
 713         vid_fp = cpudata->vid.min + mul_fp(
 714                 int_tofp(pstate - cpudata->pstate.min_pstate),
 715                 cpudata->vid.ratio);
 716
 717         vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
 718         vid = ceiling_fp(vid_fp);
 719
 720         if (pstate > cpudata->pstate.max_pstate)
 721                 vid = cpudata->vid.turbo;
 722
 723         return val | vid;
 724 }
 725
 726 static int silvermont_get_scaling(void)
 727 {
 728         u64 value;
 729         int i;
 730         /* Defined in Table 35-6 from SDM (Sept 2015) */
 731         static int silvermont_freq_table[] = {
 732                 83300, 100000, 133300, 116700, 80000};
 733
 734         rdmsrl(MSR_FSB_FREQ, value);
 735         i = value & 0x7;
 736         WARN_ON(i > 4);
 737
 738         return silvermont_freq_table[i];
 739 }
 740
 741 static int airmont_get_scaling(void)
 742 {
 743         u64 value;
 744         int i;
 745         /* Defined in Table 35-10 from SDM (Sept 2015) */
 746         static int airmont_freq_table[] = {
 747                 83300, 100000, 133300, 116700, 80000,
 748                 93300, 90000, 88900, 87500};
 749
 750         rdmsrl(MSR_FSB_FREQ, value);
 751         i = value & 0xF;
 752         WARN_ON(i > 8);
 753
 754         return airmont_freq_table[i];
 755 }
 756
 757 static void atom_get_vid(struct cpudata *cpudata)
 758 {
 759         u64 value;
 760
 761         rdmsrl(ATOM_VIDS, value);
 762         cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
 763         cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
 764         cpudata->vid.ratio = div_fp(
 765                 cpudata->vid.max - cpudata->vid.min,
 766                 int_tofp(cpudata->pstate.max_pstate -
 767                         cpudata->pstate.min_pstate));
 768
 769         rdmsrl(ATOM_TURBO_VIDS, value);
 770         cpudata->vid.turbo = value & 0x7f;
 771 }
 772
 773 static int core_get_min_pstate(void)
 774 {
 775         u64 value;
 776
 777         rdmsrl(MSR_PLATFORM_INFO, value);
 778         return (value >> 40) & 0xFF;
 779 }
 780
 781 static int core_get_max_pstate_physical(void)
 782 {
 783         u64 value;
 784
 785         rdmsrl(MSR_PLATFORM_INFO, value);
 786         return (value >> 8) & 0xFF;
 787 }
 788
 789 static int core_get_max_pstate(void)
 790 {
 791         u64 tar;
 792         u64 plat_info;
 793         int max_pstate;
 794         int err;
 795
 796         rdmsrl(MSR_PLATFORM_INFO, plat_info);
 797         max_pstate = (plat_info >> 8) & 0xFF;
 798
 799         err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar);
 800         if (!err) {
 801                 /* Do some sanity checking for safety */
 802                 if (plat_info & 0x600000000) {
 803                         u64 tdp_ctrl;
 804                         u64 tdp_ratio;
 805                         int tdp_msr;
 806
 807                         err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
 808                         if (err)
 809                                 goto skip_tar;
 810
 811                         tdp_msr = MSR_CONFIG_TDP_NOMINAL + tdp_ctrl;
 812                         err = rdmsrl_safe(tdp_msr, &tdp_ratio);
 813                         if (err)
 814                                 goto skip_tar;
 815
 816                         if (tdp_ratio - 1 == tar) {
 817                                 max_pstate = tar;
 818                                 pr_debug("max_pstate=TAC %x\n", max_pstate);
 819                         } else {
 820                                 goto skip_tar;
 821                         }
 822                 }
 823         }
 824
 825 skip_tar:
 826         return max_pstate;
 827 }
 828
 829 static int core_get_turbo_pstate(void)
 830 {
 831         u64 value;
 832         int nont, ret;
 833
 834         rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT, value);
 835         nont = core_get_max_pstate();
 836         ret = (value) & 255;
 837         if (ret <= nont)
 838                 ret = nont;
 839         return ret;
 840 }
 841
 842 static inline int core_get_scaling(void)
 843 {
 844         return 100000;
 845 }
 846
 847 static u64 core_get_val(struct cpudata *cpudata, int pstate)
 848 {
 849         u64 val;
 850
 851         val = (u64)pstate << 8;
 852         if (limits->no_turbo && !limits->turbo_disabled)
 853                 val |= (u64)1 << 32;
 854
 855         return val;
 856 }
 857
 858 static int knl_get_turbo_pstate(void)
 859 {
 860         u64 value;
 861         int nont, ret;
 862
 863         rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT, value);
 864         nont = core_get_max_pstate();
 865         ret = (((value) >> 8) & 0xFF);
 866         if (ret <= nont)
 867                 ret = nont;
 868         return ret;
 869 }
 870
 871 static struct cpu_defaults core_params = {
 872         .pid_policy = {
 873                 .sample_rate_ms = 10,
 874                 .deadband = 0,
 875                 .setpoint = 97,
 876                 .p_gain_pct = 20,
 877                 .d_gain_pct = 0,
 878                 .i_gain_pct = 0,
 879         },
 880         .funcs = {
 881                 .get_max = core_get_max_pstate,
 882                 .get_max_physical = core_get_max_pstate_physical,
 883                 .get_min = core_get_min_pstate,
 884                 .get_turbo = core_get_turbo_pstate,
 885                 .get_scaling = core_get_scaling,
 886                 .get_val = core_get_val,
 887                 .get_target_pstate = get_target_pstate_use_performance,
 888         },
 889 };
 890
 891 static struct cpu_defaults silvermont_params = {
 892         .pid_policy = {
 893                 .sample_rate_ms = 10,
 894                 .deadband = 0,
 895                 .setpoint = 60,
 896                 .p_gain_pct = 14,
 897                 .d_gain_pct = 0,
 898                 .i_gain_pct = 4,
 899         },
 900         .funcs = {
 901                 .get_max = atom_get_max_pstate,
 902                 .get_max_physical = atom_get_max_pstate,
 903                 .get_min = atom_get_min_pstate,
 904                 .get_turbo = atom_get_turbo_pstate,
 905                 .get_val = atom_get_val,
 906                 .get_scaling = silvermont_get_scaling,
 907                 .get_vid = atom_get_vid,
 908                 .get_target_pstate = get_target_pstate_use_cpu_load,
 909         },
 910 };
 911
 912 static struct cpu_defaults airmont_params = {
 913         .pid_policy = {
 914                 .sample_rate_ms = 10,
 915                 .deadband = 0,
 916                 .setpoint = 60,
 917                 .p_gain_pct = 14,
 918                 .d_gain_pct = 0,
 919                 .i_gain_pct = 4,
 920         },
 921         .funcs = {
 922                 .get_max = atom_get_max_pstate,
 923                 .get_max_physical = atom_get_max_pstate,
 924                 .get_min = atom_get_min_pstate,
 925                 .get_turbo = atom_get_turbo_pstate,
 926                 .get_val = atom_get_val,
 927                 .get_scaling = airmont_get_scaling,
 928                 .get_vid = atom_get_vid,
 929                 .get_target_pstate = get_target_pstate_use_cpu_load,
 930         },
 931 };
 932
 933 static struct cpu_defaults knl_params = {
 934         .pid_policy = {
 935                 .sample_rate_ms = 10,
 936                 .deadband = 0,
 937                 .setpoint = 97,
 938                 .p_gain_pct = 20,
 939                 .d_gain_pct = 0,
 940                 .i_gain_pct = 0,
 941         },
 942         .funcs = {
 943                 .get_max = core_get_max_pstate,
 944                 .get_max_physical = core_get_max_pstate_physical,
 945                 .get_min = core_get_min_pstate,
 946                 .get_turbo = knl_get_turbo_pstate,
 947                 .get_scaling = core_get_scaling,
 948                 .get_val = core_get_val,
 949                 .get_target_pstate = get_target_pstate_use_performance,
 950         },
 951 };
 952
 953 static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max)
 954 {
 955         int max_perf = cpu->pstate.turbo_pstate;
 956         int max_perf_adj;
 957         int min_perf;
 958
 959         if (limits->no_turbo || limits->turbo_disabled)
 960                 max_perf = cpu->pstate.max_pstate;
 961
 962         /*
 963          * performance can be limited by user through sysfs, by cpufreq
 964          * policy, or by cpu specific default values determined through
 965          * experimentation.
 966          */
 967         max_perf_adj = fp_toint(max_perf * limits->max_perf);
 968         *max = clamp_t(int, max_perf_adj,
 969                         cpu->pstate.min_pstate, cpu->pstate.turbo_pstate);
 970
 971         min_perf = fp_toint(max_perf * limits->min_perf);
 972         *min = clamp_t(int, min_perf, cpu->pstate.min_pstate, max_perf);
 973 }
 974
 975 static inline void intel_pstate_record_pstate(struct cpudata *cpu, int pstate)
 976 {
 977         trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
 978         cpu->pstate.current_pstate = pstate;
 979 }
 980
 981 static void intel_pstate_set_min_pstate(struct cpudata *cpu)
 982 {
 983         int pstate = cpu->pstate.min_pstate;
 984
 985         intel_pstate_record_pstate(cpu, pstate);
 986         /*
 987          * Generally, there is no guarantee that this code will always run on
 988          * the CPU being updated, so force the register update to run on the
 989          * right CPU.
 990          */
 991         wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
 992                       pstate_funcs.get_val(cpu, pstate));
 993 }
 994
 995 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
 996 {
 997         cpu->pstate.min_pstate = pstate_funcs.get_min();
 998         cpu->pstate.max_pstate = pstate_funcs.get_max();
 999         cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical();
1000         cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
1001         cpu->pstate.scaling = pstate_funcs.get_scaling();
1002
1003         if (pstate_funcs.get_vid)
1004                 pstate_funcs.get_vid(cpu);
1005
1006         intel_pstate_set_min_pstate(cpu);
1007 }
1008
1009 static inline void intel_pstate_calc_busy(struct cpudata *cpu)
1010 {
1011         struct sample *sample = &cpu->sample;
1012         int64_t core_pct;
1013
1014         core_pct = sample->aperf * int_tofp(100);
1015         core_pct = div64_u64(core_pct, sample->mperf);
1016
1017         sample->core_pct_busy = (int32_t)core_pct;
1018 }
1019
1020 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
1021 {
1022         u64 aperf, mperf;
1023         unsigned long flags;
1024         u64 tsc;
1025
1026         local_irq_save(flags);
1027         rdmsrl(MSR_IA32_APERF, aperf);
1028         rdmsrl(MSR_IA32_MPERF, mperf);
1029         tsc = rdtsc();
1030         if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
1031                 local_irq_restore(flags);
1032                 return false;
1033         }
1034         local_irq_restore(flags);
1035
1036         cpu->last_sample_time = cpu->sample.time;
1037         cpu->sample.time = time;
1038         cpu->sample.aperf = aperf;
1039         cpu->sample.mperf = mperf;
1040         cpu->sample.tsc =  tsc;
1041         cpu->sample.aperf -= cpu->prev_aperf;
1042         cpu->sample.mperf -= cpu->prev_mperf;
1043         cpu->sample.tsc -= cpu->prev_tsc;
1044
1045         cpu->prev_aperf = aperf;
1046         cpu->prev_mperf = mperf;
1047         cpu->prev_tsc = tsc;
1048         /*
1049          * First time this function is invoked in a given cycle, all of the
1050          * previous sample data fields are equal to zero or stale and they must
1051          * be populated with meaningful numbers for things to work, so assume
1052          * that sample.time will always be reset before setting the utilization
1053          * update hook and make the caller skip the sample then.
1054          */
1055         return !!cpu->last_sample_time;
1056 }
1057
1058 static inline int32_t get_avg_frequency(struct cpudata *cpu)
1059 {
1060         return div64_u64(cpu->pstate.max_pstate_physical * cpu->sample.aperf *
1061                 cpu->pstate.scaling, cpu->sample.mperf);
1062 }
1063
1064 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu)
1065 {
1066         struct sample *sample = &cpu->sample;
1067         u64 cummulative_iowait, delta_iowait_us;
1068         u64 delta_iowait_mperf;
1069         u64 mperf, now;
1070         int32_t cpu_load;
1071
1072         cummulative_iowait = get_cpu_iowait_time_us(cpu->cpu, &now);
1073
1074         /*
1075          * Convert iowait time into number of IO cycles spent at max_freq.
1076          * IO is considered as busy only for the cpu_load algorithm. For
1077          * performance this is not needed since we always try to reach the
1078          * maximum P-State, so we are already boosting the IOs.
1079          */
1080         delta_iowait_us = cummulative_iowait - cpu->prev_cummulative_iowait;
1081         delta_iowait_mperf = div64_u64(delta_iowait_us * cpu->pstate.scaling *
1082                 cpu->pstate.max_pstate, MSEC_PER_SEC);
1083
1084         mperf = cpu->sample.mperf + delta_iowait_mperf;
1085         cpu->prev_cummulative_iowait = cummulative_iowait;
1086
1087         /*
1088          * The load can be estimated as the ratio of the mperf counter
1089          * running at a constant frequency during active periods
1090          * (C0) and the time stamp counter running at the same frequency
1091          * also during C-states.
1092          */
1093         cpu_load = div64_u64(int_tofp(100) * mperf, sample->tsc);
1094         cpu->sample.busy_scaled = cpu_load;
1095
1096         return cpu->pstate.current_pstate - pid_calc(&cpu->pid, cpu_load);
1097 }
1098
1099 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu)
1100 {
1101         int32_t core_busy, max_pstate, current_pstate, sample_ratio;
1102         u64 duration_ns;
1103
1104         intel_pstate_calc_busy(cpu);
1105
1106         /*
1107          * core_busy is the ratio of actual performance to max
1108          * max_pstate is the max non turbo pstate available
1109          * current_pstate was the pstate that was requested during
1110          *      the last sample period.
1111          *
1112          * We normalize core_busy, which was our actual percent
1113          * performance to what we requested during the last sample
1114          * period. The result will be a percentage of busy at a
1115          * specified pstate.
1116          */
1117         core_busy = cpu->sample.core_pct_busy;
1118         max_pstate = cpu->pstate.max_pstate_physical;
1119         current_pstate = cpu->pstate.current_pstate;
1120         core_busy = mul_fp(core_busy, div_fp(max_pstate, current_pstate));
1121
1122         /*
1123          * Since our utilization update callback will not run unless we are
1124          * in C0, check if the actual elapsed time is significantly greater (3x)
1125          * than our sample interval.  If it is, then we were idle for a long
1126          * enough period of time to adjust our busyness.
1127          */
1128         duration_ns = cpu->sample.time - cpu->last_sample_time;
1129         if ((s64)duration_ns > pid_params.sample_rate_ns * 3) {
1130                 sample_ratio = div_fp(pid_params.sample_rate_ns, duration_ns);
1131                 core_busy = mul_fp(core_busy, sample_ratio);
1132         }
1133
1134         cpu->sample.busy_scaled = core_busy;
1135         return cpu->pstate.current_pstate - pid_calc(&cpu->pid, core_busy);
1136 }
1137
1138 static inline void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
1139 {
1140         int max_perf, min_perf;
1141
1142         update_turbo_state();
1143
1144         intel_pstate_get_min_max(cpu, &min_perf, &max_perf);
1145         pstate = clamp_t(int, pstate, min_perf, max_perf);
1146         if (pstate == cpu->pstate.current_pstate)
1147                 return;
1148
1149         intel_pstate_record_pstate(cpu, pstate);
1150         wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
1151 }
1152
1153 static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu)
1154 {
1155         int from, target_pstate;
1156         struct sample *sample;
1157
1158         from = cpu->pstate.current_pstate;
1159
1160         target_pstate = pstate_funcs.get_target_pstate(cpu);
1161
1162         intel_pstate_update_pstate(cpu, target_pstate);
1163
1164         sample = &cpu->sample;
1165         trace_pstate_sample(fp_toint(sample->core_pct_busy),
1166                 fp_toint(sample->busy_scaled),
1167                 from,
1168                 cpu->pstate.current_pstate,
1169                 sample->mperf,
1170                 sample->aperf,
1171                 sample->tsc,
1172                 get_avg_frequency(cpu));
1173 }
1174
1175 static void intel_pstate_update_util(struct update_util_data *data, u64 time,
1176                                      unsigned long util, unsigned long max)
1177 {
1178         struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1179         u64 delta_ns = time - cpu->sample.time;
1180
1181         if ((s64)delta_ns >= pid_params.sample_rate_ns) {
1182                 bool sample_taken = intel_pstate_sample(cpu, time);
1183
1184                 if (sample_taken && !hwp_active)
1185                         intel_pstate_adjust_busy_pstate(cpu);
1186         }
1187 }
1188
1189 #define ICPU(model, policy) \
1190         { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
1191                         (unsigned long)&policy }
1192
1193 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
1194         ICPU(0x2a, core_params),
1195         ICPU(0x2d, core_params),
1196         ICPU(0x37, silvermont_params),
1197         ICPU(0x3a, core_params),
1198         ICPU(0x3c, core_params),
1199         ICPU(0x3d, core_params),
1200         ICPU(0x3e, core_params),
1201         ICPU(0x3f, core_params),
1202         ICPU(0x45, core_params),
1203         ICPU(0x46, core_params),
1204         ICPU(0x47, core_params),
1205         ICPU(0x4c, airmont_params),
1206         ICPU(0x4e, core_params),
1207         ICPU(0x4f, core_params),
1208         ICPU(0x5e, core_params),
1209         ICPU(0x56, core_params),
1210         ICPU(0x57, knl_params),
1211         {}
1212 };
1213 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
1214
1215 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] = {
1216         ICPU(0x56, core_params),
1217         {}
1218 };
1219
1220 static int intel_pstate_init_cpu(unsigned int cpunum)
1221 {
1222         struct cpudata *cpu;
1223
1224         if (!all_cpu_data[cpunum])
1225                 all_cpu_data[cpunum] = kzalloc(sizeof(struct cpudata),
1226                                                GFP_KERNEL);
1227         if (!all_cpu_data[cpunum])
1228                 return -ENOMEM;
1229
1230         cpu = all_cpu_data[cpunum];
1231
1232         cpu->cpu = cpunum;
1233
1234         if (hwp_active) {
1235                 intel_pstate_hwp_enable(cpu);
1236                 pid_params.sample_rate_ms = 50;
1237                 pid_params.sample_rate_ns = 50 * NSEC_PER_MSEC;
1238         }
1239
1240         intel_pstate_get_cpu_pstates(cpu);
1241
1242         intel_pstate_busy_pid_reset(cpu);
1243
1244         pr_debug("controlling: cpu %d\n", cpunum);
1245
1246         return 0;
1247 }
1248
1249 static unsigned int intel_pstate_get(unsigned int cpu_num)
1250 {
1251         struct sample *sample;
1252         struct cpudata *cpu;
1253
1254         cpu = all_cpu_data[cpu_num];
1255         if (!cpu)
1256                 return 0;
1257         sample = &cpu->sample;
1258         return get_avg_frequency(cpu);
1259 }
1260
1261 static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
1262 {
1263         struct cpudata *cpu = all_cpu_data[cpu_num];
1264
1265         /* Prevent intel_pstate_update_util() from using stale data. */
1266         cpu->sample.time = 0;
1267         cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
1268                                      intel_pstate_update_util);
1269 }
1270
1271 static void intel_pstate_clear_update_util_hook(unsigned int cpu)
1272 {
1273         cpufreq_remove_update_util_hook(cpu);
1274         synchronize_sched();
1275 }
1276
1277 static void intel_pstate_set_performance_limits(struct perf_limits *limits)
1278 {
1279         limits->no_turbo = 0;
1280         limits->turbo_disabled = 0;
1281         limits->max_perf_pct = 100;
1282         limits->max_perf = int_tofp(1);
1283         limits->min_perf_pct = 100;
1284         limits->min_perf = int_tofp(1);
1285         limits->max_policy_pct = 100;
1286         limits->max_sysfs_pct = 100;
1287         limits->min_policy_pct = 0;
1288         limits->min_sysfs_pct = 0;
1289 }
1290
1291 static int intel_pstate_set_policy(struct cpufreq_policy *policy)
1292 {
1293         if (!policy->cpuinfo.max_freq)
1294                 return -ENODEV;
1295
1296         intel_pstate_clear_update_util_hook(policy->cpu);
1297
1298         if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
1299                 limits = &performance_limits;
1300                 if (policy->max >= policy->cpuinfo.max_freq) {
1301                         pr_debug("set performance\n");
1302                         intel_pstate_set_performance_limits(limits);
1303                         goto out;
1304                 }
1305         } else {
1306                 pr_debug("set powersave\n");
1307                 limits = &powersave_limits;
1308         }
1309
1310         limits->min_policy_pct = (policy->min * 100) / policy->cpuinfo.max_freq;
1311         limits->min_policy_pct = clamp_t(int, limits->min_policy_pct, 0 , 100);
1312         limits->max_policy_pct = DIV_ROUND_UP(policy->max * 100,
1313                                               policy->cpuinfo.max_freq);
1314         limits->max_policy_pct = clamp_t(int, limits->max_policy_pct, 0 , 100);
1315
1316         /* Normalize user input to [min_policy_pct, max_policy_pct] */
1317         limits->min_perf_pct = max(limits->min_policy_pct,
1318                                    limits->min_sysfs_pct);
1319         limits->min_perf_pct = min(limits->max_policy_pct,
1320                                    limits->min_perf_pct);
1321         limits->max_perf_pct = min(limits->max_policy_pct,
1322                                    limits->max_sysfs_pct);
1323         limits->max_perf_pct = max(limits->min_policy_pct,
1324                                    limits->max_perf_pct);
1325         limits->max_perf = round_up(limits->max_perf, FRAC_BITS);
1326
1327         /* Make sure min_perf_pct <= max_perf_pct */
1328         limits->min_perf_pct = min(limits->max_perf_pct, limits->min_perf_pct);
1329
1330         limits->min_perf = div_fp(limits->min_perf_pct, 100);
1331         limits->max_perf = div_fp(limits->max_perf_pct, 100);
1332
1333  out:
1334         intel_pstate_set_update_util_hook(policy->cpu);
1335
1336         if (hwp_active)
1337                 intel_pstate_hwp_set(policy->cpus);
1338
1339         return 0;
1340 }
1341
1342 static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
1343 {
1344         cpufreq_verify_within_cpu_limits(policy);
1345
1346         if (policy->policy != CPUFREQ_POLICY_POWERSAVE &&
1347             policy->policy != CPUFREQ_POLICY_PERFORMANCE)
1348                 return -EINVAL;
1349
1350         return 0;
1351 }
1352
1353 static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
1354 {
1355         int cpu_num = policy->cpu;
1356         struct cpudata *cpu = all_cpu_data[cpu_num];
1357
1358         pr_debug("CPU %d exiting\n", cpu_num);
1359
1360         intel_pstate_clear_update_util_hook(cpu_num);
1361
1362         if (hwp_active)
1363                 return;
1364
1365         intel_pstate_set_min_pstate(cpu);
1366 }
1367
1368 static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
1369 {
1370         struct cpudata *cpu;
1371         int rc;
1372
1373         rc = intel_pstate_init_cpu(policy->cpu);
1374         if (rc)
1375                 return rc;
1376
1377         cpu = all_cpu_data[policy->cpu];
1378
1379         if (limits->min_perf_pct == 100 && limits->max_perf_pct == 100)
1380                 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
1381         else
1382                 policy->policy = CPUFREQ_POLICY_POWERSAVE;
1383
1384         policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling;
1385         policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
1386
1387         /* cpuinfo and default policy values */
1388         policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;
1389         policy->cpuinfo.max_freq =
1390                 cpu->pstate.turbo_pstate * cpu->pstate.scaling;
1391         policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
1392         cpumask_set_cpu(policy->cpu, policy->cpus);
1393
1394         return 0;
1395 }
1396
1397 static struct cpufreq_driver intel_pstate_driver = {
1398         .flags          = CPUFREQ_CONST_LOOPS,
1399         .verify         = intel_pstate_verify_policy,
1400         .setpolicy      = intel_pstate_set_policy,
1401         .get            = intel_pstate_get,
1402         .init           = intel_pstate_cpu_init,
1403         .stop_cpu       = intel_pstate_stop_cpu,
1404         .name           = "intel_pstate",
1405 };
1406
1407 static int __initdata no_load;
1408 static int __initdata no_hwp;
1409 static int __initdata hwp_only;
1410 static unsigned int force_load;
1411
1412 static int intel_pstate_msrs_not_valid(void)
1413 {
1414         if (!pstate_funcs.get_max() ||
1415             !pstate_funcs.get_min() ||
1416             !pstate_funcs.get_turbo())
1417                 return -ENODEV;
1418
1419         return 0;
1420 }
1421
1422 static void copy_pid_params(struct pstate_adjust_policy *policy)
1423 {
1424         pid_params.sample_rate_ms = policy->sample_rate_ms;
1425         pid_params.sample_rate_ns = pid_params.sample_rate_ms * NSEC_PER_MSEC;
1426         pid_params.p_gain_pct = policy->p_gain_pct;
1427         pid_params.i_gain_pct = policy->i_gain_pct;
1428         pid_params.d_gain_pct = policy->d_gain_pct;
1429         pid_params.deadband = policy->deadband;
1430         pid_params.setpoint = policy->setpoint;
1431 }
1432
1433 static void copy_cpu_funcs(struct pstate_funcs *funcs)
1434 {
1435         pstate_funcs.get_max   = funcs->get_max;
1436         pstate_funcs.get_max_physical = funcs->get_max_physical;
1437         pstate_funcs.get_min   = funcs->get_min;
1438         pstate_funcs.get_turbo = funcs->get_turbo;
1439         pstate_funcs.get_scaling = funcs->get_scaling;
1440         pstate_funcs.get_val   = funcs->get_val;
1441         pstate_funcs.get_vid   = funcs->get_vid;
1442         pstate_funcs.get_target_pstate = funcs->get_target_pstate;
1443
1444 }
1445
1446 #if IS_ENABLED(CONFIG_ACPI)
1447 #include <acpi/processor.h>
1448
1449 static bool intel_pstate_no_acpi_pss(void)
1450 {
1451         int i;
1452
1453         for_each_possible_cpu(i) {
1454                 acpi_status status;
1455                 union acpi_object *pss;
1456                 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1457                 struct acpi_processor *pr = per_cpu(processors, i);
1458
1459                 if (!pr)
1460                         continue;
1461
1462                 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
1463                 if (ACPI_FAILURE(status))
1464                         continue;
1465
1466                 pss = buffer.pointer;
1467                 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
1468                         kfree(pss);
1469                         return false;
1470                 }
1471
1472                 kfree(pss);
1473         }
1474
1475         return true;
1476 }
1477
1478 static bool intel_pstate_has_acpi_ppc(void)
1479 {
1480         int i;
1481
1482         for_each_possible_cpu(i) {
1483                 struct acpi_processor *pr = per_cpu(processors, i);
1484
1485                 if (!pr)
1486                         continue;
1487                 if (acpi_has_method(pr->handle, "_PPC"))
1488                         return true;
1489         }
1490         return false;
1491 }
1492
1493 enum {
1494         PSS,
1495         PPC,
1496 };
1497
1498 struct hw_vendor_info {
1499         u16  valid;
1500         char oem_id[ACPI_OEM_ID_SIZE];
1501         char oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
1502         int  oem_pwr_table;
1503 };
1504
1505 /* Hardware vendor-specific info that has its own power management modes */
1506 static struct hw_vendor_info vendor_info[] = {
1507         {1, "HP    ", "ProLiant", PSS},
1508         {1, "ORACLE", "X4-2    ", PPC},
1509         {1, "ORACLE", "X4-2L   ", PPC},
1510         {1, "ORACLE", "X4-2B   ", PPC},
1511         {1, "ORACLE", "X3-2    ", PPC},
1512         {1, "ORACLE", "X3-2L   ", PPC},
1513         {1, "ORACLE", "X3-2B   ", PPC},
1514         {1, "ORACLE", "X4470M2 ", PPC},
1515         {1, "ORACLE", "X4270M3 ", PPC},
1516         {1, "ORACLE", "X4270M2 ", PPC},
1517         {1, "ORACLE", "X4170M2 ", PPC},
1518         {1, "ORACLE", "X4170 M3", PPC},
1519         {1, "ORACLE", "X4275 M3", PPC},
1520         {1, "ORACLE", "X6-2    ", PPC},
1521         {1, "ORACLE", "Sudbury ", PPC},
1522         {0, "", ""},
1523 };
1524
1525 static bool intel_pstate_platform_pwr_mgmt_exists(void)
1526 {
1527         struct acpi_table_header hdr;
1528         struct hw_vendor_info *v_info;
1529         const struct x86_cpu_id *id;
1530         u64 misc_pwr;
1531
1532         id = x86_match_cpu(intel_pstate_cpu_oob_ids);
1533         if (id) {
1534                 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
1535                 if ( misc_pwr & (1 << 8))
1536                         return true;
1537         }
1538
1539         if (acpi_disabled ||
1540             ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr)))
1541                 return false;
1542
1543         for (v_info = vendor_info; v_info->valid; v_info++) {
1544                 if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) &&
1545                         !strncmp(hdr.oem_table_id, v_info->oem_table_id,
1546                                                 ACPI_OEM_TABLE_ID_SIZE))
1547                         switch (v_info->oem_pwr_table) {
1548                         case PSS:
1549                                 return intel_pstate_no_acpi_pss();
1550                         case PPC:
1551                                 return intel_pstate_has_acpi_ppc() &&
1552                                         (!force_load);
1553                         }
1554         }
1555
1556         return false;
1557 }
1558 #else /* CONFIG_ACPI not enabled */
1559 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
1560 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
1561 #endif /* CONFIG_ACPI */
1562
1563 static const struct x86_cpu_id hwp_support_ids[] __initconst = {
1564         { X86_VENDOR_INTEL, 6, X86_MODEL_ANY, X86_FEATURE_HWP },
1565         {}
1566 };
1567
1568 static int __init intel_pstate_init(void)
1569 {
1570         int cpu, rc = 0;
1571         const struct x86_cpu_id *id;
1572         struct cpu_defaults *cpu_def;
1573
1574         if (no_load)
1575                 return -ENODEV;
1576
1577         if (x86_match_cpu(hwp_support_ids) && !no_hwp) {
1578                 copy_cpu_funcs(&core_params.funcs);
1579                 hwp_active++;
1580                 goto hwp_cpu_matched;
1581         }
1582
1583         id = x86_match_cpu(intel_pstate_cpu_ids);
1584         if (!id)
1585                 return -ENODEV;
1586
1587         cpu_def = (struct cpu_defaults *)id->driver_data;
1588
1589         copy_pid_params(&cpu_def->pid_policy);
1590         copy_cpu_funcs(&cpu_def->funcs);
1591
1592         if (intel_pstate_msrs_not_valid())
1593                 return -ENODEV;
1594
1595 hwp_cpu_matched:
1596         /*
1597          * The Intel pstate driver will be ignored if the platform
1598          * firmware has its own power management modes.
1599          */
1600         if (intel_pstate_platform_pwr_mgmt_exists())
1601                 return -ENODEV;
1602
1603         pr_info("Intel P-state driver initializing\n");
1604
1605         all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus());
1606         if (!all_cpu_data)
1607                 return -ENOMEM;
1608
1609         if (!hwp_active && hwp_only)
1610                 goto out;
1611
1612         rc = cpufreq_register_driver(&intel_pstate_driver);
1613         if (rc)
1614                 goto out;
1615
1616         intel_pstate_debug_expose_params();
1617         intel_pstate_sysfs_expose_params();
1618
1619         if (hwp_active)
1620                 pr_info("HWP enabled\n");
1621
1622         return rc;
1623 out:
1624         get_online_cpus();
1625         for_each_online_cpu(cpu) {
1626                 if (all_cpu_data[cpu]) {
1627                         intel_pstate_clear_update_util_hook(cpu);
1628                         kfree(all_cpu_data[cpu]);
1629                 }
1630         }
1631
1632         put_online_cpus();
1633         vfree(all_cpu_data);
1634         return -ENODEV;
1635 }
1636 device_initcall(intel_pstate_init);
1637
1638 static int __init intel_pstate_setup(char *str)
1639 {
1640         if (!str)
1641                 return -EINVAL;
1642
1643         if (!strcmp(str, "disable"))
1644                 no_load = 1;
1645         if (!strcmp(str, "no_hwp")) {
1646                 pr_info("HWP disabled\n");
1647                 no_hwp = 1;
1648         }
1649         if (!strcmp(str, "force"))
1650                 force_load = 1;
1651         if (!strcmp(str, "hwp_only"))
1652                 hwp_only = 1;
1653         return 0;
1654 }
1655 early_param("intel_pstate", intel_pstate_setup);
1656
1657 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
1658 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
1659 MODULE_LICENSE("GPL");