drivers/cpufreq/intel_pstate.c

   1 /*
   2  * intel_pstate.c: Native P state management for Intel processors
   3  *
   4  * (C) Copyright 2012 Intel Corporation
   5  * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; version 2
  10  * of the License.
  11  */
  12
  13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  14
  15 #include <linux/kernel.h>
  16 #include <linux/kernel_stat.h>
  17 #include <linux/module.h>
  18 #include <linux/ktime.h>
  19 #include <linux/hrtimer.h>
  20 #include <linux/tick.h>
  21 #include <linux/slab.h>
  22 #include <linux/sched.h>
  23 #include <linux/list.h>
  24 #include <linux/cpu.h>
  25 #include <linux/cpufreq.h>
  26 #include <linux/sysfs.h>
  27 #include <linux/types.h>
  28 #include <linux/fs.h>
  29 #include <linux/debugfs.h>
  30 #include <linux/acpi.h>
  31 #include <linux/vmalloc.h>
  32 #include <trace/events/power.h>
  33
  34 #include <asm/div64.h>
  35 #include <asm/msr.h>
  36 #include <asm/cpu_device_id.h>
  37 #include <asm/cpufeature.h>
  38 #include <asm/intel-family.h>
  39
  40 #define ATOM_RATIOS             0x66a
  41 #define ATOM_VIDS               0x66b
  42 #define ATOM_TURBO_RATIOS       0x66c
  43 #define ATOM_TURBO_VIDS         0x66d
  44
  45 #ifdef CONFIG_ACPI
  46 #include <acpi/processor.h>
  47 #endif
  48
  49 #define FRAC_BITS 8
  50 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
  51 #define fp_toint(X) ((X) >> FRAC_BITS)
  52
  53 #define EXT_BITS 6
  54 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
  55
  56 static inline int32_t mul_fp(int32_t x, int32_t y)
  57 {
  58         return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
  59 }
  60
  61 static inline int32_t div_fp(s64 x, s64 y)
  62 {
  63         return div64_s64((int64_t)x << FRAC_BITS, y);
  64 }
  65
  66 static inline int ceiling_fp(int32_t x)
  67 {
  68         int mask, ret;
  69
  70         ret = fp_toint(x);
  71         mask = (1 << FRAC_BITS) - 1;
  72         if (x & mask)
  73                 ret += 1;
  74         return ret;
  75 }
  76
  77 static inline u64 mul_ext_fp(u64 x, u64 y)
  78 {
  79         return (x * y) >> EXT_FRAC_BITS;
  80 }
  81
  82 static inline u64 div_ext_fp(u64 x, u64 y)
  83 {
  84         return div64_u64(x << EXT_FRAC_BITS, y);
  85 }
  86
  87 /**
  88  * struct sample -      Store performance sample
  89  * @core_avg_perf:      Ratio of APERF/MPERF which is the actual average
  90  *                      performance during last sample period
  91  * @busy_scaled:        Scaled busy value which is used to calculate next
  92  *                      P state. This can be different than core_avg_perf
  93  *                      to account for cpu idle period
  94  * @aperf:              Difference of actual performance frequency clock count
  95  *                      read from APERF MSR between last and current sample
  96  * @mperf:              Difference of maximum performance frequency clock count
  97  *                      read from MPERF MSR between last and current sample
  98  * @tsc:                Difference of time stamp counter between last and
  99  *                      current sample
 100  * @time:               Current time from scheduler
 101  *
 102  * This structure is used in the cpudata structure to store performance sample
 103  * data for choosing next P State.
 104  */
 105 struct sample {
 106         int32_t core_avg_perf;
 107         int32_t busy_scaled;
 108         u64 aperf;
 109         u64 mperf;
 110         u64 tsc;
 111         u64 time;
 112 };
 113
 114 /**
 115  * struct pstate_data - Store P state data
 116  * @current_pstate:     Current requested P state
 117  * @min_pstate:         Min P state possible for this platform
 118  * @max_pstate:         Max P state possible for this platform
 119  * @max_pstate_physical:This is physical Max P state for a processor
 120  *                      This can be higher than the max_pstate which can
 121  *                      be limited by platform thermal design power limits
 122  * @scaling:            Scaling factor to  convert frequency to cpufreq
 123  *                      frequency units
 124  * @turbo_pstate:       Max Turbo P state possible for this platform
 125  *
 126  * Stores the per cpu model P state limits and current P state.
 127  */
 128 struct pstate_data {
 129         int     current_pstate;
 130         int     min_pstate;
 131         int     max_pstate;
 132         int     max_pstate_physical;
 133         int     scaling;
 134         int     turbo_pstate;
 135 };
 136
 137 /**
 138  * struct vid_data -    Stores voltage information data
 139  * @min:                VID data for this platform corresponding to
 140  *                      the lowest P state
 141  * @max:                VID data corresponding to the highest P State.
 142  * @turbo:              VID data for turbo P state
 143  * @ratio:              Ratio of (vid max - vid min) /
 144  *                      (max P state - Min P State)
 145  *
 146  * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
 147  * This data is used in Atom platforms, where in addition to target P state,
 148  * the voltage data needs to be specified to select next P State.
 149  */
 150 struct vid_data {
 151         int min;
 152         int max;
 153         int turbo;
 154         int32_t ratio;
 155 };
 156
 157 /**
 158  * struct _pid -        Stores PID data
 159  * @setpoint:           Target set point for busyness or performance
 160  * @integral:           Storage for accumulated error values
 161  * @p_gain:             PID proportional gain
 162  * @i_gain:             PID integral gain
 163  * @d_gain:             PID derivative gain
 164  * @deadband:           PID deadband
 165  * @last_err:           Last error storage for integral part of PID calculation
 166  *
 167  * Stores PID coefficients and last error for PID controller.
 168  */
 169 struct _pid {
 170         int setpoint;
 171         int32_t integral;
 172         int32_t p_gain;
 173         int32_t i_gain;
 174         int32_t d_gain;
 175         int deadband;
 176         int32_t last_err;
 177 };
 178
 179 /**
 180  * struct cpudata -     Per CPU instance data storage
 181  * @cpu:                CPU number for this instance data
 182  * @update_util:        CPUFreq utility callback information
 183  * @update_util_set:    CPUFreq utility callback is set
 184  * @iowait_boost:       iowait-related boost fraction
 185  * @last_update:        Time of the last update.
 186  * @pstate:             Stores P state limits for this CPU
 187  * @vid:                Stores VID limits for this CPU
 188  * @pid:                Stores PID parameters for this CPU
 189  * @last_sample_time:   Last Sample time
 190  * @prev_aperf:         Last APERF value read from APERF MSR
 191  * @prev_mperf:         Last MPERF value read from MPERF MSR
 192  * @prev_tsc:           Last timestamp counter (TSC) value
 193  * @prev_cummulative_iowait: IO Wait time difference from last and
 194  *                      current sample
 195  * @sample:             Storage for storing last Sample data
 196  * @acpi_perf_data:     Stores ACPI perf information read from _PSS
 197  * @valid_pss_table:    Set to true for valid ACPI _PSS entries found
 198  *
 199  * This structure stores per CPU instance data for all CPUs.
 200  */
 201 struct cpudata {
 202         int cpu;
 203
 204         struct update_util_data update_util;
 205         bool   update_util_set;
 206
 207         struct pstate_data pstate;
 208         struct vid_data vid;
 209         struct _pid pid;
 210
 211         u64     last_update;
 212         u64     last_sample_time;
 213         u64     prev_aperf;
 214         u64     prev_mperf;
 215         u64     prev_tsc;
 216         u64     prev_cummulative_iowait;
 217         struct sample sample;
 218 #ifdef CONFIG_ACPI
 219         struct acpi_processor_performance acpi_perf_data;
 220         bool valid_pss_table;
 221 #endif
 222         unsigned int iowait_boost;
 223 };
 224
 225 static struct cpudata **all_cpu_data;
 226
 227 /**
 228  * struct pid_adjust_policy - Stores static PID configuration data
 229  * @sample_rate_ms:     PID calculation sample rate in ms
 230  * @sample_rate_ns:     Sample rate calculation in ns
 231  * @deadband:           PID deadband
 232  * @setpoint:           PID Setpoint
 233  * @p_gain_pct:         PID proportional gain
 234  * @i_gain_pct:         PID integral gain
 235  * @d_gain_pct:         PID derivative gain
 236  * @boost_iowait:       Whether or not to use iowait boosting.
 237  *
 238  * Stores per CPU model static PID configuration data.
 239  */
 240 struct pstate_adjust_policy {
 241         int sample_rate_ms;
 242         s64 sample_rate_ns;
 243         int deadband;
 244         int setpoint;
 245         int p_gain_pct;
 246         int d_gain_pct;
 247         int i_gain_pct;
 248         bool boost_iowait;
 249 };
 250
 251 /**
 252  * struct pstate_funcs - Per CPU model specific callbacks
 253  * @get_max:            Callback to get maximum non turbo effective P state
 254  * @get_max_physical:   Callback to get maximum non turbo physical P state
 255  * @get_min:            Callback to get minimum P state
 256  * @get_turbo:          Callback to get turbo P state
 257  * @get_scaling:        Callback to get frequency scaling factor
 258  * @get_val:            Callback to convert P state to actual MSR write value
 259  * @get_vid:            Callback to get VID data for Atom platforms
 260  * @get_target_pstate:  Callback to a function to calculate next P state to use
 261  *
 262  * Core and Atom CPU models have different way to get P State limits. This
 263  * structure is used to store those callbacks.
 264  */
 265 struct pstate_funcs {
 266         int (*get_max)(void);
 267         int (*get_max_physical)(void);
 268         int (*get_min)(void);
 269         int (*get_turbo)(void);
 270         int (*get_scaling)(void);
 271         u64 (*get_val)(struct cpudata*, int pstate);
 272         void (*get_vid)(struct cpudata *);
 273         int32_t (*get_target_pstate)(struct cpudata *);
 274 };
 275
 276 /**
 277  * struct cpu_defaults- Per CPU model default config data
 278  * @pid_policy: PID config data
 279  * @funcs:              Callback function data
 280  */
 281 struct cpu_defaults {
 282         struct pstate_adjust_policy pid_policy;
 283         struct pstate_funcs funcs;
 284 };
 285
 286 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu);
 287 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu);
 288
 289 static struct pstate_adjust_policy pid_params __read_mostly;
 290 static struct pstate_funcs pstate_funcs __read_mostly;
 291 static int hwp_active __read_mostly;
 292
 293 #ifdef CONFIG_ACPI
 294 static bool acpi_ppc;
 295 #endif
 296
 297 /**
 298  * struct perf_limits - Store user and policy limits
 299  * @no_turbo:           User requested turbo state from intel_pstate sysfs
 300  * @turbo_disabled:     Platform turbo status either from msr
 301  *                      MSR_IA32_MISC_ENABLE or when maximum available pstate
 302  *                      matches the maximum turbo pstate
 303  * @max_perf_pct:       Effective maximum performance limit in percentage, this
 304  *                      is minimum of either limits enforced by cpufreq policy
 305  *                      or limits from user set limits via intel_pstate sysfs
 306  * @min_perf_pct:       Effective minimum performance limit in percentage, this
 307  *                      is maximum of either limits enforced by cpufreq policy
 308  *                      or limits from user set limits via intel_pstate sysfs
 309  * @max_perf:           This is a scaled value between 0 to 255 for max_perf_pct
 310  *                      This value is used to limit max pstate
 311  * @min_perf:           This is a scaled value between 0 to 255 for min_perf_pct
 312  *                      This value is used to limit min pstate
 313  * @max_policy_pct:     The maximum performance in percentage enforced by
 314  *                      cpufreq setpolicy interface
 315  * @max_sysfs_pct:      The maximum performance in percentage enforced by
 316  *                      intel pstate sysfs interface
 317  * @min_policy_pct:     The minimum performance in percentage enforced by
 318  *                      cpufreq setpolicy interface
 319  * @min_sysfs_pct:      The minimum performance in percentage enforced by
 320  *                      intel pstate sysfs interface
 321  *
 322  * Storage for user and policy defined limits.
 323  */
 324 struct perf_limits {
 325         int no_turbo;
 326         int turbo_disabled;
 327         int max_perf_pct;
 328         int min_perf_pct;
 329         int32_t max_perf;
 330         int32_t min_perf;
 331         int max_policy_pct;
 332         int max_sysfs_pct;
 333         int min_policy_pct;
 334         int min_sysfs_pct;
 335 };
 336
 337 static struct perf_limits performance_limits = {
 338         .no_turbo = 0,
 339         .turbo_disabled = 0,
 340         .max_perf_pct = 100,
 341         .max_perf = int_tofp(1),
 342         .min_perf_pct = 100,
 343         .min_perf = int_tofp(1),
 344         .max_policy_pct = 100,
 345         .max_sysfs_pct = 100,
 346         .min_policy_pct = 0,
 347         .min_sysfs_pct = 0,
 348 };
 349
 350 static struct perf_limits powersave_limits = {
 351         .no_turbo = 0,
 352         .turbo_disabled = 0,
 353         .max_perf_pct = 100,
 354         .max_perf = int_tofp(1),
 355         .min_perf_pct = 0,
 356         .min_perf = 0,
 357         .max_policy_pct = 100,
 358         .max_sysfs_pct = 100,
 359         .min_policy_pct = 0,
 360         .min_sysfs_pct = 0,
 361 };
 362
 363 #ifdef CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE
 364 static struct perf_limits *limits = &performance_limits;
 365 #else
 366 static struct perf_limits *limits = &powersave_limits;
 367 #endif
 368
 369 #ifdef CONFIG_ACPI
 370
 371 static bool intel_pstate_get_ppc_enable_status(void)
 372 {
 373         if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
 374             acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
 375                 return true;
 376
 377         return acpi_ppc;
 378 }
 379
 380 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
 381 {
 382         struct cpudata *cpu;
 383         int ret;
 384         int i;
 385
 386         if (hwp_active)
 387                 return;
 388
 389         if (!intel_pstate_get_ppc_enable_status())
 390                 return;
 391
 392         cpu = all_cpu_data[policy->cpu];
 393
 394         ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
 395                                                   policy->cpu);
 396         if (ret)
 397                 return;
 398
 399         /*
 400          * Check if the control value in _PSS is for PERF_CTL MSR, which should
 401          * guarantee that the states returned by it map to the states in our
 402          * list directly.
 403          */
 404         if (cpu->acpi_perf_data.control_register.space_id !=
 405                                                 ACPI_ADR_SPACE_FIXED_HARDWARE)
 406                 goto err;
 407
 408         /*
 409          * If there is only one entry _PSS, simply ignore _PSS and continue as
 410          * usual without taking _PSS into account
 411          */
 412         if (cpu->acpi_perf_data.state_count < 2)
 413                 goto err;
 414
 415         pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
 416         for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
 417                 pr_debug("     %cP%d: %u MHz, %u mW, 0x%x\n",
 418                          (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
 419                          (u32) cpu->acpi_perf_data.states[i].core_frequency,
 420                          (u32) cpu->acpi_perf_data.states[i].power,
 421                          (u32) cpu->acpi_perf_data.states[i].control);
 422         }
 423
 424         /*
 425          * The _PSS table doesn't contain whole turbo frequency range.
 426          * This just contains +1 MHZ above the max non turbo frequency,
 427          * with control value corresponding to max turbo ratio. But
 428          * when cpufreq set policy is called, it will call with this
 429          * max frequency, which will cause a reduced performance as
 430          * this driver uses real max turbo frequency as the max
 431          * frequency. So correct this frequency in _PSS table to
 432          * correct max turbo frequency based on the turbo state.
 433          * Also need to convert to MHz as _PSS freq is in MHz.
 434          */
 435         if (!limits->turbo_disabled)
 436                 cpu->acpi_perf_data.states[0].core_frequency =
 437                                         policy->cpuinfo.max_freq / 1000;
 438         cpu->valid_pss_table = true;
 439         pr_debug("_PPC limits will be enforced\n");
 440
 441         return;
 442
 443  err:
 444         cpu->valid_pss_table = false;
 445         acpi_processor_unregister_performance(policy->cpu);
 446 }
 447
 448 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
 449 {
 450         struct cpudata *cpu;
 451
 452         cpu = all_cpu_data[policy->cpu];
 453         if (!cpu->valid_pss_table)
 454                 return;
 455
 456         acpi_processor_unregister_performance(policy->cpu);
 457 }
 458
 459 #else
 460 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
 461 {
 462 }
 463
 464 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
 465 {
 466 }
 467 #endif
 468
 469 static inline void pid_reset(struct _pid *pid, int setpoint, int busy,
 470                              int deadband, int integral) {
 471         pid->setpoint = int_tofp(setpoint);
 472         pid->deadband  = int_tofp(deadband);
 473         pid->integral  = int_tofp(integral);
 474         pid->last_err  = int_tofp(setpoint) - int_tofp(busy);
 475 }
 476
 477 static inline void pid_p_gain_set(struct _pid *pid, int percent)
 478 {
 479         pid->p_gain = div_fp(percent, 100);
 480 }
 481
 482 static inline void pid_i_gain_set(struct _pid *pid, int percent)
 483 {
 484         pid->i_gain = div_fp(percent, 100);
 485 }
 486
 487 static inline void pid_d_gain_set(struct _pid *pid, int percent)
 488 {
 489         pid->d_gain = div_fp(percent, 100);
 490 }
 491
 492 static signed int pid_calc(struct _pid *pid, int32_t busy)
 493 {
 494         signed int result;
 495         int32_t pterm, dterm, fp_error;
 496         int32_t integral_limit;
 497
 498         fp_error = pid->setpoint - busy;
 499
 500         if (abs(fp_error) <= pid->deadband)
 501                 return 0;
 502
 503         pterm = mul_fp(pid->p_gain, fp_error);
 504
 505         pid->integral += fp_error;
 506
 507         /*
 508          * We limit the integral here so that it will never
 509          * get higher than 30.  This prevents it from becoming
 510          * too large an input over long periods of time and allows
 511          * it to get factored out sooner.
 512          *
 513          * The value of 30 was chosen through experimentation.
 514          */
 515         integral_limit = int_tofp(30);
 516         if (pid->integral > integral_limit)
 517                 pid->integral = integral_limit;
 518         if (pid->integral < -integral_limit)
 519                 pid->integral = -integral_limit;
 520
 521         dterm = mul_fp(pid->d_gain, fp_error - pid->last_err);
 522         pid->last_err = fp_error;
 523
 524         result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm;
 525         result = result + (1 << (FRAC_BITS-1));
 526         return (signed int)fp_toint(result);
 527 }
 528
 529 static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu)
 530 {
 531         pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct);
 532         pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct);
 533         pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct);
 534
 535         pid_reset(&cpu->pid, pid_params.setpoint, 100, pid_params.deadband, 0);
 536 }
 537
 538 static inline void intel_pstate_reset_all_pid(void)
 539 {
 540         unsigned int cpu;
 541
 542         for_each_online_cpu(cpu) {
 543                 if (all_cpu_data[cpu])
 544                         intel_pstate_busy_pid_reset(all_cpu_data[cpu]);
 545         }
 546 }
 547
 548 static inline void update_turbo_state(void)
 549 {
 550         u64 misc_en;
 551         struct cpudata *cpu;
 552
 553         cpu = all_cpu_data[0];
 554         rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
 555         limits->turbo_disabled =
 556                 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
 557                  cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
 558 }
 559
 560 static void intel_pstate_hwp_set(const struct cpumask *cpumask)
 561 {
 562         int min, hw_min, max, hw_max, cpu, range, adj_range;
 563         u64 value, cap;
 564
 565         for_each_cpu(cpu, cpumask) {
 566                 rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap);
 567                 hw_min = HWP_LOWEST_PERF(cap);
 568                 hw_max = HWP_HIGHEST_PERF(cap);
 569                 range = hw_max - hw_min;
 570
 571                 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
 572                 adj_range = limits->min_perf_pct * range / 100;
 573                 min = hw_min + adj_range;
 574                 value &= ~HWP_MIN_PERF(~0L);
 575                 value |= HWP_MIN_PERF(min);
 576
 577                 adj_range = limits->max_perf_pct * range / 100;
 578                 max = hw_min + adj_range;
 579                 if (limits->no_turbo) {
 580                         hw_max = HWP_GUARANTEED_PERF(cap);
 581                         if (hw_max < max)
 582                                 max = hw_max;
 583                 }
 584
 585                 value &= ~HWP_MAX_PERF(~0L);
 586                 value |= HWP_MAX_PERF(max);
 587                 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
 588         }
 589 }
 590
 591 static int intel_pstate_hwp_set_policy(struct cpufreq_policy *policy)
 592 {
 593         if (hwp_active)
 594                 intel_pstate_hwp_set(policy->cpus);
 595
 596         return 0;
 597 }
 598
 599 static void intel_pstate_hwp_set_online_cpus(void)
 600 {
 601         get_online_cpus();
 602         intel_pstate_hwp_set(cpu_online_mask);
 603         put_online_cpus();
 604 }
 605
 606 /************************** debugfs begin ************************/
 607 static int pid_param_set(void *data, u64 val)
 608 {
 609         *(u32 *)data = val;
 610         intel_pstate_reset_all_pid();
 611         return 0;
 612 }
 613
 614 static int pid_param_get(void *data, u64 *val)
 615 {
 616         *val = *(u32 *)data;
 617         return 0;
 618 }
 619 DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n");
 620
 621 struct pid_param {
 622         char *name;
 623         void *value;
 624 };
 625
 626 static struct pid_param pid_files[] = {
 627         {"sample_rate_ms", &pid_params.sample_rate_ms},
 628         {"d_gain_pct", &pid_params.d_gain_pct},
 629         {"i_gain_pct", &pid_params.i_gain_pct},
 630         {"deadband", &pid_params.deadband},
 631         {"setpoint", &pid_params.setpoint},
 632         {"p_gain_pct", &pid_params.p_gain_pct},
 633         {NULL, NULL}
 634 };
 635
 636 static void __init intel_pstate_debug_expose_params(void)
 637 {
 638         struct dentry *debugfs_parent;
 639         int i = 0;
 640
 641         if (hwp_active)
 642                 return;
 643         debugfs_parent = debugfs_create_dir("pstate_snb", NULL);
 644         if (IS_ERR_OR_NULL(debugfs_parent))
 645                 return;
 646         while (pid_files[i].name) {
 647                 debugfs_create_file(pid_files[i].name, 0660,
 648                                     debugfs_parent, pid_files[i].value,
 649                                     &fops_pid_param);
 650                 i++;
 651         }
 652 }
 653
 654 /************************** debugfs end ************************/
 655
 656 /************************** sysfs begin ************************/
 657 #define show_one(file_name, object)                                     \
 658         static ssize_t show_##file_name                                 \
 659         (struct kobject *kobj, struct attribute *attr, char *buf)       \
 660         {                                                               \
 661                 return sprintf(buf, "%u\n", limits->object);            \
 662         }
 663
 664 static ssize_t show_turbo_pct(struct kobject *kobj,
 665                                 struct attribute *attr, char *buf)
 666 {
 667         struct cpudata *cpu;
 668         int total, no_turbo, turbo_pct;
 669         uint32_t turbo_fp;
 670
 671         cpu = all_cpu_data[0];
 672
 673         total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
 674         no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
 675         turbo_fp = div_fp(no_turbo, total);
 676         turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
 677         return sprintf(buf, "%u\n", turbo_pct);
 678 }
 679
 680 static ssize_t show_num_pstates(struct kobject *kobj,
 681                                 struct attribute *attr, char *buf)
 682 {
 683         struct cpudata *cpu;
 684         int total;
 685
 686         cpu = all_cpu_data[0];
 687         total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
 688         return sprintf(buf, "%u\n", total);
 689 }
 690
 691 static ssize_t show_no_turbo(struct kobject *kobj,
 692                              struct attribute *attr, char *buf)
 693 {
 694         ssize_t ret;
 695
 696         update_turbo_state();
 697         if (limits->turbo_disabled)
 698                 ret = sprintf(buf, "%u\n", limits->turbo_disabled);
 699         else
 700                 ret = sprintf(buf, "%u\n", limits->no_turbo);
 701
 702         return ret;
 703 }
 704
 705 static ssize_t store_no_turbo(struct kobject *a, struct attribute *b,
 706                               const char *buf, size_t count)
 707 {
 708         unsigned int input;
 709         int ret;
 710
 711         ret = sscanf(buf, "%u", &input);
 712         if (ret != 1)
 713                 return -EINVAL;
 714
 715         update_turbo_state();
 716         if (limits->turbo_disabled) {
 717                 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
 718                 return -EPERM;
 719         }
 720
 721         limits->no_turbo = clamp_t(int, input, 0, 1);
 722
 723         if (hwp_active)
 724                 intel_pstate_hwp_set_online_cpus();
 725
 726         return count;
 727 }
 728
 729 static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b,
 730                                   const char *buf, size_t count)
 731 {
 732         unsigned int input;
 733         int ret;
 734
 735         ret = sscanf(buf, "%u", &input);
 736         if (ret != 1)
 737                 return -EINVAL;
 738
 739         limits->max_sysfs_pct = clamp_t(int, input, 0 , 100);
 740         limits->max_perf_pct = min(limits->max_policy_pct,
 741                                    limits->max_sysfs_pct);
 742         limits->max_perf_pct = max(limits->min_policy_pct,
 743                                    limits->max_perf_pct);
 744         limits->max_perf_pct = max(limits->min_perf_pct,
 745                                    limits->max_perf_pct);
 746         limits->max_perf = div_fp(limits->max_perf_pct, 100);
 747
 748         if (hwp_active)
 749                 intel_pstate_hwp_set_online_cpus();
 750         return count;
 751 }
 752
 753 static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b,
 754                                   const char *buf, size_t count)
 755 {
 756         unsigned int input;
 757         int ret;
 758
 759         ret = sscanf(buf, "%u", &input);
 760         if (ret != 1)
 761                 return -EINVAL;
 762
 763         limits->min_sysfs_pct = clamp_t(int, input, 0 , 100);
 764         limits->min_perf_pct = max(limits->min_policy_pct,
 765                                    limits->min_sysfs_pct);
 766         limits->min_perf_pct = min(limits->max_policy_pct,
 767                                    limits->min_perf_pct);
 768         limits->min_perf_pct = min(limits->max_perf_pct,
 769                                    limits->min_perf_pct);
 770         limits->min_perf = div_fp(limits->min_perf_pct, 100);
 771
 772         if (hwp_active)
 773                 intel_pstate_hwp_set_online_cpus();
 774         return count;
 775 }
 776
 777 show_one(max_perf_pct, max_perf_pct);
 778 show_one(min_perf_pct, min_perf_pct);
 779
 780 define_one_global_rw(no_turbo);
 781 define_one_global_rw(max_perf_pct);
 782 define_one_global_rw(min_perf_pct);
 783 define_one_global_ro(turbo_pct);
 784 define_one_global_ro(num_pstates);
 785
 786 static struct attribute *intel_pstate_attributes[] = {
 787         &no_turbo.attr,
 788         &max_perf_pct.attr,
 789         &min_perf_pct.attr,
 790         &turbo_pct.attr,
 791         &num_pstates.attr,
 792         NULL
 793 };
 794
 795 static struct attribute_group intel_pstate_attr_group = {
 796         .attrs = intel_pstate_attributes,
 797 };
 798
 799 static void __init intel_pstate_sysfs_expose_params(void)
 800 {
 801         struct kobject *intel_pstate_kobject;
 802         int rc;
 803
 804         intel_pstate_kobject = kobject_create_and_add("intel_pstate",
 805                                                 &cpu_subsys.dev_root->kobj);
 806         BUG_ON(!intel_pstate_kobject);
 807         rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
 808         BUG_ON(rc);
 809 }
 810 /************************** sysfs end ************************/
 811
 812 static void intel_pstate_hwp_enable(struct cpudata *cpudata)
 813 {
 814         /* First disable HWP notification interrupt as we don't process them */
 815         if (static_cpu_has(X86_FEATURE_HWP_NOTIFY))
 816                 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
 817
 818         wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
 819 }
 820
 821 static int atom_get_min_pstate(void)
 822 {
 823         u64 value;
 824
 825         rdmsrl(ATOM_RATIOS, value);
 826         return (value >> 8) & 0x7F;
 827 }
 828
 829 static int atom_get_max_pstate(void)
 830 {
 831         u64 value;
 832
 833         rdmsrl(ATOM_RATIOS, value);
 834         return (value >> 16) & 0x7F;
 835 }
 836
 837 static int atom_get_turbo_pstate(void)
 838 {
 839         u64 value;
 840
 841         rdmsrl(ATOM_TURBO_RATIOS, value);
 842         return value & 0x7F;
 843 }
 844
 845 static u64 atom_get_val(struct cpudata *cpudata, int pstate)
 846 {
 847         u64 val;
 848         int32_t vid_fp;
 849         u32 vid;
 850
 851         val = (u64)pstate << 8;
 852         if (limits->no_turbo && !limits->turbo_disabled)
 853                 val |= (u64)1 << 32;
 854
 855         vid_fp = cpudata->vid.min + mul_fp(
 856                 int_tofp(pstate - cpudata->pstate.min_pstate),
 857                 cpudata->vid.ratio);
 858
 859         vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
 860         vid = ceiling_fp(vid_fp);
 861
 862         if (pstate > cpudata->pstate.max_pstate)
 863                 vid = cpudata->vid.turbo;
 864
 865         return val | vid;
 866 }
 867
 868 static int silvermont_get_scaling(void)
 869 {
 870         u64 value;
 871         int i;
 872         /* Defined in Table 35-6 from SDM (Sept 2015) */
 873         static int silvermont_freq_table[] = {
 874                 83300, 100000, 133300, 116700, 80000};
 875
 876         rdmsrl(MSR_FSB_FREQ, value);
 877         i = value & 0x7;
 878         WARN_ON(i > 4);
 879
 880         return silvermont_freq_table[i];
 881 }
 882
 883 static int airmont_get_scaling(void)
 884 {
 885         u64 value;
 886         int i;
 887         /* Defined in Table 35-10 from SDM (Sept 2015) */
 888         static int airmont_freq_table[] = {
 889                 83300, 100000, 133300, 116700, 80000,
 890                 93300, 90000, 88900, 87500};
 891
 892         rdmsrl(MSR_FSB_FREQ, value);
 893         i = value & 0xF;
 894         WARN_ON(i > 8);
 895
 896         return airmont_freq_table[i];
 897 }
 898
 899 static void atom_get_vid(struct cpudata *cpudata)
 900 {
 901         u64 value;
 902
 903         rdmsrl(ATOM_VIDS, value);
 904         cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
 905         cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
 906         cpudata->vid.ratio = div_fp(
 907                 cpudata->vid.max - cpudata->vid.min,
 908                 int_tofp(cpudata->pstate.max_pstate -
 909                         cpudata->pstate.min_pstate));
 910
 911         rdmsrl(ATOM_TURBO_VIDS, value);
 912         cpudata->vid.turbo = value & 0x7f;
 913 }
 914
 915 static int core_get_min_pstate(void)
 916 {
 917         u64 value;
 918
 919         rdmsrl(MSR_PLATFORM_INFO, value);
 920         return (value >> 40) & 0xFF;
 921 }
 922
 923 static int core_get_max_pstate_physical(void)
 924 {
 925         u64 value;
 926
 927         rdmsrl(MSR_PLATFORM_INFO, value);
 928         return (value >> 8) & 0xFF;
 929 }
 930
 931 static int core_get_max_pstate(void)
 932 {
 933         u64 tar;
 934         u64 plat_info;
 935         int max_pstate;
 936         int err;
 937
 938         rdmsrl(MSR_PLATFORM_INFO, plat_info);
 939         max_pstate = (plat_info >> 8) & 0xFF;
 940
 941         err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar);
 942         if (!err) {
 943                 /* Do some sanity checking for safety */
 944                 if (plat_info & 0x600000000) {
 945                         u64 tdp_ctrl;
 946                         u64 tdp_ratio;
 947                         int tdp_msr;
 948
 949                         err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
 950                         if (err)
 951                                 goto skip_tar;
 952
 953                         tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x3);
 954                         err = rdmsrl_safe(tdp_msr, &tdp_ratio);
 955                         if (err)
 956                                 goto skip_tar;
 957
 958                         /* For level 1 and 2, bits[23:16] contain the ratio */
 959                         if (tdp_ctrl)
 960                                 tdp_ratio >>= 16;
 961
 962                         tdp_ratio &= 0xff; /* ratios are only 8 bits long */
 963                         if (tdp_ratio - 1 == tar) {
 964                                 max_pstate = tar;
 965                                 pr_debug("max_pstate=TAC %x\n", max_pstate);
 966                         } else {
 967                                 goto skip_tar;
 968                         }
 969                 }
 970         }
 971
 972 skip_tar:
 973         return max_pstate;
 974 }
 975
 976 static int core_get_turbo_pstate(void)
 977 {
 978         u64 value;
 979         int nont, ret;
 980
 981         rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
 982         nont = core_get_max_pstate();
 983         ret = (value) & 255;
 984         if (ret <= nont)
 985                 ret = nont;
 986         return ret;
 987 }
 988
 989 static inline int core_get_scaling(void)
 990 {
 991         return 100000;
 992 }
 993
 994 static u64 core_get_val(struct cpudata *cpudata, int pstate)
 995 {
 996         u64 val;
 997
 998         val = (u64)pstate << 8;
 999         if (limits->no_turbo && !limits->turbo_disabled)
1000                 val |= (u64)1 << 32;
1001
1002         return val;
1003 }
1004
1005 static int knl_get_turbo_pstate(void)
1006 {
1007         u64 value;
1008         int nont, ret;
1009
1010         rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1011         nont = core_get_max_pstate();
1012         ret = (((value) >> 8) & 0xFF);
1013         if (ret <= nont)
1014                 ret = nont;
1015         return ret;
1016 }
1017
1018 static struct cpu_defaults core_params = {
1019         .pid_policy = {
1020                 .sample_rate_ms = 10,
1021                 .deadband = 0,
1022                 .setpoint = 97,
1023                 .p_gain_pct = 20,
1024                 .d_gain_pct = 0,
1025                 .i_gain_pct = 0,
1026         },
1027         .funcs = {
1028                 .get_max = core_get_max_pstate,
1029                 .get_max_physical = core_get_max_pstate_physical,
1030                 .get_min = core_get_min_pstate,
1031                 .get_turbo = core_get_turbo_pstate,
1032                 .get_scaling = core_get_scaling,
1033                 .get_val = core_get_val,
1034                 .get_target_pstate = get_target_pstate_use_performance,
1035         },
1036 };
1037
1038 static const struct cpu_defaults silvermont_params = {
1039         .pid_policy = {
1040                 .sample_rate_ms = 10,
1041                 .deadband = 0,
1042                 .setpoint = 60,
1043                 .p_gain_pct = 14,
1044                 .d_gain_pct = 0,
1045                 .i_gain_pct = 4,
1046                 .boost_iowait = true,
1047         },
1048         .funcs = {
1049                 .get_max = atom_get_max_pstate,
1050                 .get_max_physical = atom_get_max_pstate,
1051                 .get_min = atom_get_min_pstate,
1052                 .get_turbo = atom_get_turbo_pstate,
1053                 .get_val = atom_get_val,
1054                 .get_scaling = silvermont_get_scaling,
1055                 .get_vid = atom_get_vid,
1056                 .get_target_pstate = get_target_pstate_use_cpu_load,
1057         },
1058 };
1059
1060 static const struct cpu_defaults airmont_params = {
1061         .pid_policy = {
1062                 .sample_rate_ms = 10,
1063                 .deadband = 0,
1064                 .setpoint = 60,
1065                 .p_gain_pct = 14,
1066                 .d_gain_pct = 0,
1067                 .i_gain_pct = 4,
1068                 .boost_iowait = true,
1069         },
1070         .funcs = {
1071                 .get_max = atom_get_max_pstate,
1072                 .get_max_physical = atom_get_max_pstate,
1073                 .get_min = atom_get_min_pstate,
1074                 .get_turbo = atom_get_turbo_pstate,
1075                 .get_val = atom_get_val,
1076                 .get_scaling = airmont_get_scaling,
1077                 .get_vid = atom_get_vid,
1078                 .get_target_pstate = get_target_pstate_use_cpu_load,
1079         },
1080 };
1081
1082 static const struct cpu_defaults knl_params = {
1083         .pid_policy = {
1084                 .sample_rate_ms = 10,
1085                 .deadband = 0,
1086                 .setpoint = 97,
1087                 .p_gain_pct = 20,
1088                 .d_gain_pct = 0,
1089                 .i_gain_pct = 0,
1090         },
1091         .funcs = {
1092                 .get_max = core_get_max_pstate,
1093                 .get_max_physical = core_get_max_pstate_physical,
1094                 .get_min = core_get_min_pstate,
1095                 .get_turbo = knl_get_turbo_pstate,
1096                 .get_scaling = core_get_scaling,
1097                 .get_val = core_get_val,
1098                 .get_target_pstate = get_target_pstate_use_performance,
1099         },
1100 };
1101
1102 static const struct cpu_defaults bxt_params = {
1103         .pid_policy = {
1104                 .sample_rate_ms = 10,
1105                 .deadband = 0,
1106                 .setpoint = 60,
1107                 .p_gain_pct = 14,
1108                 .d_gain_pct = 0,
1109                 .i_gain_pct = 4,
1110                 .boost_iowait = true,
1111         },
1112         .funcs = {
1113                 .get_max = core_get_max_pstate,
1114                 .get_max_physical = core_get_max_pstate_physical,
1115                 .get_min = core_get_min_pstate,
1116                 .get_turbo = core_get_turbo_pstate,
1117                 .get_scaling = core_get_scaling,
1118                 .get_val = core_get_val,
1119                 .get_target_pstate = get_target_pstate_use_cpu_load,
1120         },
1121 };
1122
1123 static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max)
1124 {
1125         int max_perf = cpu->pstate.turbo_pstate;
1126         int max_perf_adj;
1127         int min_perf;
1128
1129         if (limits->no_turbo || limits->turbo_disabled)
1130                 max_perf = cpu->pstate.max_pstate;
1131
1132         /*
1133          * performance can be limited by user through sysfs, by cpufreq
1134          * policy, or by cpu specific default values determined through
1135          * experimentation.
1136          */
1137         max_perf_adj = fp_toint(max_perf * limits->max_perf);
1138         *max = clamp_t(int, max_perf_adj,
1139                         cpu->pstate.min_pstate, cpu->pstate.turbo_pstate);
1140
1141         min_perf = fp_toint(max_perf * limits->min_perf);
1142         *min = clamp_t(int, min_perf, cpu->pstate.min_pstate, max_perf);
1143 }
1144
1145 static void intel_pstate_set_min_pstate(struct cpudata *cpu)
1146 {
1147         int pstate = cpu->pstate.min_pstate;
1148
1149         trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1150         cpu->pstate.current_pstate = pstate;
1151         /*
1152          * Generally, there is no guarantee that this code will always run on
1153          * the CPU being updated, so force the register update to run on the
1154          * right CPU.
1155          */
1156         wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
1157                       pstate_funcs.get_val(cpu, pstate));
1158 }
1159
1160 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
1161 {
1162         cpu->pstate.min_pstate = pstate_funcs.get_min();
1163         cpu->pstate.max_pstate = pstate_funcs.get_max();
1164         cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical();
1165         cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
1166         cpu->pstate.scaling = pstate_funcs.get_scaling();
1167
1168         if (pstate_funcs.get_vid)
1169                 pstate_funcs.get_vid(cpu);
1170
1171         intel_pstate_set_min_pstate(cpu);
1172 }
1173
1174 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
1175 {
1176         struct sample *sample = &cpu->sample;
1177
1178         sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
1179 }
1180
1181 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
1182 {
1183         u64 aperf, mperf;
1184         unsigned long flags;
1185         u64 tsc;
1186
1187         local_irq_save(flags);
1188         rdmsrl(MSR_IA32_APERF, aperf);
1189         rdmsrl(MSR_IA32_MPERF, mperf);
1190         tsc = rdtsc();
1191         if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
1192                 local_irq_restore(flags);
1193                 return false;
1194         }
1195         local_irq_restore(flags);
1196
1197         cpu->last_sample_time = cpu->sample.time;
1198         cpu->sample.time = time;
1199         cpu->sample.aperf = aperf;
1200         cpu->sample.mperf = mperf;
1201         cpu->sample.tsc =  tsc;
1202         cpu->sample.aperf -= cpu->prev_aperf;
1203         cpu->sample.mperf -= cpu->prev_mperf;
1204         cpu->sample.tsc -= cpu->prev_tsc;
1205
1206         cpu->prev_aperf = aperf;
1207         cpu->prev_mperf = mperf;
1208         cpu->prev_tsc = tsc;
1209         /*
1210          * First time this function is invoked in a given cycle, all of the
1211          * previous sample data fields are equal to zero or stale and they must
1212          * be populated with meaningful numbers for things to work, so assume
1213          * that sample.time will always be reset before setting the utilization
1214          * update hook and make the caller skip the sample then.
1215          */
1216         return !!cpu->last_sample_time;
1217 }
1218
1219 static inline int32_t get_avg_frequency(struct cpudata *cpu)
1220 {
1221         return mul_ext_fp(cpu->sample.core_avg_perf,
1222                           cpu->pstate.max_pstate_physical * cpu->pstate.scaling);
1223 }
1224
1225 static inline int32_t get_avg_pstate(struct cpudata *cpu)
1226 {
1227         return mul_ext_fp(cpu->pstate.max_pstate_physical,
1228                           cpu->sample.core_avg_perf);
1229 }
1230
1231 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu)
1232 {
1233         struct sample *sample = &cpu->sample;
1234         int32_t busy_frac, boost;
1235         int target, avg_pstate;
1236
1237         busy_frac = div_fp(sample->mperf, sample->tsc);
1238
1239         boost = cpu->iowait_boost;
1240         cpu->iowait_boost >>= 1;
1241
1242         if (busy_frac < boost)
1243                 busy_frac = boost;
1244
1245         sample->busy_scaled = busy_frac * 100;
1246
1247         target = limits->no_turbo || limits->turbo_disabled ?
1248                         cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1249         target += target >> 2;
1250         target = mul_fp(target, busy_frac);
1251         if (target < cpu->pstate.min_pstate)
1252                 target = cpu->pstate.min_pstate;
1253
1254         /*
1255          * If the average P-state during the previous cycle was higher than the
1256          * current target, add 50% of the difference to the target to reduce
1257          * possible performance oscillations and offset possible performance
1258          * loss related to moving the workload from one CPU to another within
1259          * a package/module.
1260          */
1261         avg_pstate = get_avg_pstate(cpu);
1262         if (avg_pstate > target)
1263                 target += (avg_pstate - target) >> 1;
1264
1265         return target;
1266 }
1267
1268 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu)
1269 {
1270         int32_t perf_scaled, max_pstate, current_pstate, sample_ratio;
1271         u64 duration_ns;
1272
1273         /*
1274          * perf_scaled is the ratio of the average P-state during the last
1275          * sampling period to the P-state requested last time (in percent).
1276          *
1277          * That measures the system's response to the previous P-state
1278          * selection.
1279          */
1280         max_pstate = cpu->pstate.max_pstate_physical;
1281         current_pstate = cpu->pstate.current_pstate;
1282         perf_scaled = mul_ext_fp(cpu->sample.core_avg_perf,
1283                                div_fp(100 * max_pstate, current_pstate));
1284
1285         /*
1286          * Since our utilization update callback will not run unless we are
1287          * in C0, check if the actual elapsed time is significantly greater (3x)
1288          * than our sample interval.  If it is, then we were idle for a long
1289          * enough period of time to adjust our performance metric.
1290          */
1291         duration_ns = cpu->sample.time - cpu->last_sample_time;
1292         if ((s64)duration_ns > pid_params.sample_rate_ns * 3) {
1293                 sample_ratio = div_fp(pid_params.sample_rate_ns, duration_ns);
1294                 perf_scaled = mul_fp(perf_scaled, sample_ratio);
1295         } else {
1296                 sample_ratio = div_fp(100 * cpu->sample.mperf, cpu->sample.tsc);
1297                 if (sample_ratio < int_tofp(1))
1298                         perf_scaled = 0;
1299         }
1300
1301         cpu->sample.busy_scaled = perf_scaled;
1302         return cpu->pstate.current_pstate - pid_calc(&cpu->pid, perf_scaled);
1303 }
1304
1305 static inline void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
1306 {
1307         int max_perf, min_perf;
1308
1309         update_turbo_state();
1310
1311         intel_pstate_get_min_max(cpu, &min_perf, &max_perf);
1312         pstate = clamp_t(int, pstate, min_perf, max_perf);
1313         trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1314         if (pstate == cpu->pstate.current_pstate)
1315                 return;
1316
1317         cpu->pstate.current_pstate = pstate;
1318         wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
1319 }
1320
1321 static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu)
1322 {
1323         int from, target_pstate;
1324         struct sample *sample;
1325
1326         from = cpu->pstate.current_pstate;
1327
1328         target_pstate = pstate_funcs.get_target_pstate(cpu);
1329
1330         intel_pstate_update_pstate(cpu, target_pstate);
1331
1332         sample = &cpu->sample;
1333         trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
1334                 fp_toint(sample->busy_scaled),
1335                 from,
1336                 cpu->pstate.current_pstate,
1337                 sample->mperf,
1338                 sample->aperf,
1339                 sample->tsc,
1340                 get_avg_frequency(cpu),
1341                 fp_toint(cpu->iowait_boost * 100));
1342 }
1343
1344 static void intel_pstate_update_util(struct update_util_data *data, u64 time,
1345                                      unsigned int flags)
1346 {
1347         struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1348         u64 delta_ns;
1349
1350         if (pid_params.boost_iowait) {
1351                 if (flags & SCHED_CPUFREQ_IOWAIT) {
1352                         cpu->iowait_boost = int_tofp(1);
1353                 } else if (cpu->iowait_boost) {
1354                         /* Clear iowait_boost if the CPU may have been idle. */
1355                         delta_ns = time - cpu->last_update;
1356                         if (delta_ns > TICK_NSEC)
1357                                 cpu->iowait_boost = 0;
1358                 }
1359                 cpu->last_update = time;
1360         }
1361
1362         delta_ns = time - cpu->sample.time;
1363         if ((s64)delta_ns >= pid_params.sample_rate_ns) {
1364                 bool sample_taken = intel_pstate_sample(cpu, time);
1365
1366                 if (sample_taken) {
1367                         intel_pstate_calc_avg_perf(cpu);
1368                         if (!hwp_active)
1369                                 intel_pstate_adjust_busy_pstate(cpu);
1370                 }
1371         }
1372 }
1373
1374 #define ICPU(model, policy) \
1375         { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
1376                         (unsigned long)&policy }
1377
1378 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
1379         ICPU(INTEL_FAM6_SANDYBRIDGE,            core_params),
1380         ICPU(INTEL_FAM6_SANDYBRIDGE_X,          core_params),
1381         ICPU(INTEL_FAM6_ATOM_SILVERMONT1,       silvermont_params),
1382         ICPU(INTEL_FAM6_IVYBRIDGE,              core_params),
1383         ICPU(INTEL_FAM6_HASWELL_CORE,           core_params),
1384         ICPU(INTEL_FAM6_BROADWELL_CORE,         core_params),
1385         ICPU(INTEL_FAM6_IVYBRIDGE_X,            core_params),
1386         ICPU(INTEL_FAM6_HASWELL_X,              core_params),
1387         ICPU(INTEL_FAM6_HASWELL_ULT,            core_params),
1388         ICPU(INTEL_FAM6_HASWELL_GT3E,           core_params),
1389         ICPU(INTEL_FAM6_BROADWELL_GT3E,         core_params),
1390         ICPU(INTEL_FAM6_ATOM_AIRMONT,           airmont_params),
1391         ICPU(INTEL_FAM6_SKYLAKE_MOBILE,         core_params),
1392         ICPU(INTEL_FAM6_BROADWELL_X,            core_params),
1393         ICPU(INTEL_FAM6_SKYLAKE_DESKTOP,        core_params),
1394         ICPU(INTEL_FAM6_BROADWELL_XEON_D,       core_params),
1395         ICPU(INTEL_FAM6_XEON_PHI_KNL,           knl_params),
1396         ICPU(INTEL_FAM6_ATOM_GOLDMONT,          bxt_params),
1397         {}
1398 };
1399 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
1400
1401 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
1402         ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_params),
1403         ICPU(INTEL_FAM6_BROADWELL_X, core_params),
1404         ICPU(INTEL_FAM6_SKYLAKE_X, core_params),
1405         {}
1406 };
1407
1408 static int intel_pstate_init_cpu(unsigned int cpunum)
1409 {
1410         struct cpudata *cpu;
1411
1412         if (!all_cpu_data[cpunum])
1413                 all_cpu_data[cpunum] = kzalloc(sizeof(struct cpudata),
1414                                                GFP_KERNEL);
1415         if (!all_cpu_data[cpunum])
1416                 return -ENOMEM;
1417
1418         cpu = all_cpu_data[cpunum];
1419
1420         cpu->cpu = cpunum;
1421
1422         if (hwp_active) {
1423                 intel_pstate_hwp_enable(cpu);
1424                 pid_params.sample_rate_ms = 50;
1425                 pid_params.sample_rate_ns = 50 * NSEC_PER_MSEC;
1426         }
1427
1428         intel_pstate_get_cpu_pstates(cpu);
1429
1430         intel_pstate_busy_pid_reset(cpu);
1431
1432         pr_debug("controlling: cpu %d\n", cpunum);
1433
1434         return 0;
1435 }
1436
1437 static unsigned int intel_pstate_get(unsigned int cpu_num)
1438 {
1439         struct cpudata *cpu = all_cpu_data[cpu_num];
1440
1441         return cpu ? get_avg_frequency(cpu) : 0;
1442 }
1443
1444 static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
1445 {
1446         struct cpudata *cpu = all_cpu_data[cpu_num];
1447
1448         if (cpu->update_util_set)
1449                 return;
1450
1451         /* Prevent intel_pstate_update_util() from using stale data. */
1452         cpu->sample.time = 0;
1453         cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
1454                                      intel_pstate_update_util);
1455         cpu->update_util_set = true;
1456 }
1457
1458 static void intel_pstate_clear_update_util_hook(unsigned int cpu)
1459 {
1460         struct cpudata *cpu_data = all_cpu_data[cpu];
1461
1462         if (!cpu_data->update_util_set)
1463                 return;
1464
1465         cpufreq_remove_update_util_hook(cpu);
1466         cpu_data->update_util_set = false;
1467         synchronize_sched();
1468 }
1469
1470 static void intel_pstate_set_performance_limits(struct perf_limits *limits)
1471 {
1472         limits->no_turbo = 0;
1473         limits->turbo_disabled = 0;
1474         limits->max_perf_pct = 100;
1475         limits->max_perf = int_tofp(1);
1476         limits->min_perf_pct = 100;
1477         limits->min_perf = int_tofp(1);
1478         limits->max_policy_pct = 100;
1479         limits->max_sysfs_pct = 100;
1480         limits->min_policy_pct = 0;
1481         limits->min_sysfs_pct = 0;
1482 }
1483
1484 static int intel_pstate_set_policy(struct cpufreq_policy *policy)
1485 {
1486         struct cpudata *cpu;
1487
1488         if (!policy->cpuinfo.max_freq)
1489                 return -ENODEV;
1490
1491         pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
1492                  policy->cpuinfo.max_freq, policy->max);
1493
1494         cpu = all_cpu_data[0];
1495         if (cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
1496             policy->max < policy->cpuinfo.max_freq &&
1497             policy->max > cpu->pstate.max_pstate * cpu->pstate.scaling) {
1498                 pr_debug("policy->max > max non turbo frequency\n");
1499                 policy->max = policy->cpuinfo.max_freq;
1500         }
1501
1502         if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
1503                 limits = &performance_limits;
1504                 if (policy->max >= policy->cpuinfo.max_freq) {
1505                         pr_debug("set performance\n");
1506                         intel_pstate_set_performance_limits(limits);
1507                         goto out;
1508                 }
1509         } else {
1510                 pr_debug("set powersave\n");
1511                 limits = &powersave_limits;
1512         }
1513
1514         limits->min_policy_pct = (policy->min * 100) / policy->cpuinfo.max_freq;
1515         limits->min_policy_pct = clamp_t(int, limits->min_policy_pct, 0 , 100);
1516         limits->max_policy_pct = DIV_ROUND_UP(policy->max * 100,
1517                                               policy->cpuinfo.max_freq);
1518         limits->max_policy_pct = clamp_t(int, limits->max_policy_pct, 0 , 100);
1519
1520         /* Normalize user input to [min_policy_pct, max_policy_pct] */
1521         limits->min_perf_pct = max(limits->min_policy_pct,
1522                                    limits->min_sysfs_pct);
1523         limits->min_perf_pct = min(limits->max_policy_pct,
1524                                    limits->min_perf_pct);
1525         limits->max_perf_pct = min(limits->max_policy_pct,
1526                                    limits->max_sysfs_pct);
1527         limits->max_perf_pct = max(limits->min_policy_pct,
1528                                    limits->max_perf_pct);
1529
1530         /* Make sure min_perf_pct <= max_perf_pct */
1531         limits->min_perf_pct = min(limits->max_perf_pct, limits->min_perf_pct);
1532
1533         limits->min_perf = div_fp(limits->min_perf_pct, 100);
1534         limits->max_perf = div_fp(limits->max_perf_pct, 100);
1535         limits->max_perf = round_up(limits->max_perf, FRAC_BITS);
1536
1537  out:
1538         intel_pstate_set_update_util_hook(policy->cpu);
1539
1540         intel_pstate_hwp_set_policy(policy);
1541
1542         return 0;
1543 }
1544
1545 static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
1546 {
1547         cpufreq_verify_within_cpu_limits(policy);
1548
1549         if (policy->policy != CPUFREQ_POLICY_POWERSAVE &&
1550             policy->policy != CPUFREQ_POLICY_PERFORMANCE)
1551                 return -EINVAL;
1552
1553         return 0;
1554 }
1555
1556 static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
1557 {
1558         int cpu_num = policy->cpu;
1559         struct cpudata *cpu = all_cpu_data[cpu_num];
1560
1561         pr_debug("CPU %d exiting\n", cpu_num);
1562
1563         intel_pstate_clear_update_util_hook(cpu_num);
1564
1565         if (hwp_active)
1566                 return;
1567
1568         intel_pstate_set_min_pstate(cpu);
1569 }
1570
1571 static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
1572 {
1573         struct cpudata *cpu;
1574         int rc;
1575
1576         rc = intel_pstate_init_cpu(policy->cpu);
1577         if (rc)
1578                 return rc;
1579
1580         cpu = all_cpu_data[policy->cpu];
1581
1582         if (limits->min_perf_pct == 100 && limits->max_perf_pct == 100)
1583                 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
1584         else
1585                 policy->policy = CPUFREQ_POLICY_POWERSAVE;
1586
1587         policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling;
1588         policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
1589
1590         /* cpuinfo and default policy values */
1591         policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;
1592         update_turbo_state();
1593         policy->cpuinfo.max_freq = limits->turbo_disabled ?
1594                         cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1595         policy->cpuinfo.max_freq *= cpu->pstate.scaling;
1596
1597         intel_pstate_init_acpi_perf_limits(policy);
1598         policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
1599         cpumask_set_cpu(policy->cpu, policy->cpus);
1600
1601         return 0;
1602 }
1603
1604 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
1605 {
1606         intel_pstate_exit_perf_limits(policy);
1607
1608         return 0;
1609 }
1610
1611 static struct cpufreq_driver intel_pstate_driver = {
1612         .flags          = CPUFREQ_CONST_LOOPS,
1613         .verify         = intel_pstate_verify_policy,
1614         .setpolicy      = intel_pstate_set_policy,
1615         .resume         = intel_pstate_hwp_set_policy,
1616         .get            = intel_pstate_get,
1617         .init           = intel_pstate_cpu_init,
1618         .exit           = intel_pstate_cpu_exit,
1619         .stop_cpu       = intel_pstate_stop_cpu,
1620         .name           = "intel_pstate",
1621 };
1622
1623 static int no_load __initdata;
1624 static int no_hwp __initdata;
1625 static int hwp_only __initdata;
1626 static unsigned int force_load __initdata;
1627
1628 static int __init intel_pstate_msrs_not_valid(void)
1629 {
1630         if (!pstate_funcs.get_max() ||
1631             !pstate_funcs.get_min() ||
1632             !pstate_funcs.get_turbo())
1633                 return -ENODEV;
1634
1635         return 0;
1636 }
1637
1638 static void __init copy_pid_params(struct pstate_adjust_policy *policy)
1639 {
1640         pid_params.sample_rate_ms = policy->sample_rate_ms;
1641         pid_params.sample_rate_ns = pid_params.sample_rate_ms * NSEC_PER_MSEC;
1642         pid_params.p_gain_pct = policy->p_gain_pct;
1643         pid_params.i_gain_pct = policy->i_gain_pct;
1644         pid_params.d_gain_pct = policy->d_gain_pct;
1645         pid_params.deadband = policy->deadband;
1646         pid_params.setpoint = policy->setpoint;
1647 }
1648
1649 static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
1650 {
1651         pstate_funcs.get_max   = funcs->get_max;
1652         pstate_funcs.get_max_physical = funcs->get_max_physical;
1653         pstate_funcs.get_min   = funcs->get_min;
1654         pstate_funcs.get_turbo = funcs->get_turbo;
1655         pstate_funcs.get_scaling = funcs->get_scaling;
1656         pstate_funcs.get_val   = funcs->get_val;
1657         pstate_funcs.get_vid   = funcs->get_vid;
1658         pstate_funcs.get_target_pstate = funcs->get_target_pstate;
1659
1660 }
1661
1662 #ifdef CONFIG_ACPI
1663
1664 static bool __init intel_pstate_no_acpi_pss(void)
1665 {
1666         int i;
1667
1668         for_each_possible_cpu(i) {
1669                 acpi_status status;
1670                 union acpi_object *pss;
1671                 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1672                 struct acpi_processor *pr = per_cpu(processors, i);
1673
1674                 if (!pr)
1675                         continue;
1676
1677                 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
1678                 if (ACPI_FAILURE(status))
1679                         continue;
1680
1681                 pss = buffer.pointer;
1682                 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
1683                         kfree(pss);
1684                         return false;
1685                 }
1686
1687                 kfree(pss);
1688         }
1689
1690         return true;
1691 }
1692
1693 static bool __init intel_pstate_has_acpi_ppc(void)
1694 {
1695         int i;
1696
1697         for_each_possible_cpu(i) {
1698                 struct acpi_processor *pr = per_cpu(processors, i);
1699
1700                 if (!pr)
1701                         continue;
1702                 if (acpi_has_method(pr->handle, "_PPC"))
1703                         return true;
1704         }
1705         return false;
1706 }
1707
1708 enum {
1709         PSS,
1710         PPC,
1711 };
1712
1713 struct hw_vendor_info {
1714         u16  valid;
1715         char oem_id[ACPI_OEM_ID_SIZE];
1716         char oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
1717         int  oem_pwr_table;
1718 };
1719
1720 /* Hardware vendor-specific info that has its own power management modes */
1721 static struct hw_vendor_info vendor_info[] __initdata = {
1722         {1, "HP    ", "ProLiant", PSS},
1723         {1, "ORACLE", "X4-2    ", PPC},
1724         {1, "ORACLE", "X4-2L   ", PPC},
1725         {1, "ORACLE", "X4-2B   ", PPC},
1726         {1, "ORACLE", "X3-2    ", PPC},
1727         {1, "ORACLE", "X3-2L   ", PPC},
1728         {1, "ORACLE", "X3-2B   ", PPC},
1729         {1, "ORACLE", "X4470M2 ", PPC},
1730         {1, "ORACLE", "X4270M3 ", PPC},
1731         {1, "ORACLE", "X4270M2 ", PPC},
1732         {1, "ORACLE", "X4170M2 ", PPC},
1733         {1, "ORACLE", "X4170 M3", PPC},
1734         {1, "ORACLE", "X4275 M3", PPC},
1735         {1, "ORACLE", "X6-2    ", PPC},
1736         {1, "ORACLE", "Sudbury ", PPC},
1737         {0, "", ""},
1738 };
1739
1740 static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
1741 {
1742         struct acpi_table_header hdr;
1743         struct hw_vendor_info *v_info;
1744         const struct x86_cpu_id *id;
1745         u64 misc_pwr;
1746
1747         id = x86_match_cpu(intel_pstate_cpu_oob_ids);
1748         if (id) {
1749                 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
1750                 if ( misc_pwr & (1 << 8))
1751                         return true;
1752         }
1753
1754         if (acpi_disabled ||
1755             ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr)))
1756                 return false;
1757
1758         for (v_info = vendor_info; v_info->valid; v_info++) {
1759                 if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) &&
1760                         !strncmp(hdr.oem_table_id, v_info->oem_table_id,
1761                                                 ACPI_OEM_TABLE_ID_SIZE))
1762                         switch (v_info->oem_pwr_table) {
1763                         case PSS:
1764                                 return intel_pstate_no_acpi_pss();
1765                         case PPC:
1766                                 return intel_pstate_has_acpi_ppc() &&
1767                                         (!force_load);
1768                         }
1769         }
1770
1771         return false;
1772 }
1773 #else /* CONFIG_ACPI not enabled */
1774 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
1775 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
1776 #endif /* CONFIG_ACPI */
1777
1778 static const struct x86_cpu_id hwp_support_ids[] __initconst = {
1779         { X86_VENDOR_INTEL, 6, X86_MODEL_ANY, X86_FEATURE_HWP },
1780         {}
1781 };
1782
1783 static int __init intel_pstate_init(void)
1784 {
1785         int cpu, rc = 0;
1786         const struct x86_cpu_id *id;
1787         struct cpu_defaults *cpu_def;
1788
1789         if (no_load)
1790                 return -ENODEV;
1791
1792         if (x86_match_cpu(hwp_support_ids) && !no_hwp) {
1793                 copy_cpu_funcs(&core_params.funcs);
1794                 hwp_active++;
1795                 goto hwp_cpu_matched;
1796         }
1797
1798         id = x86_match_cpu(intel_pstate_cpu_ids);
1799         if (!id)
1800                 return -ENODEV;
1801
1802         cpu_def = (struct cpu_defaults *)id->driver_data;
1803
1804         copy_pid_params(&cpu_def->pid_policy);
1805         copy_cpu_funcs(&cpu_def->funcs);
1806
1807         if (intel_pstate_msrs_not_valid())
1808                 return -ENODEV;
1809
1810 hwp_cpu_matched:
1811         /*
1812          * The Intel pstate driver will be ignored if the platform
1813          * firmware has its own power management modes.
1814          */
1815         if (intel_pstate_platform_pwr_mgmt_exists())
1816                 return -ENODEV;
1817
1818         pr_info("Intel P-state driver initializing\n");
1819
1820         all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus());
1821         if (!all_cpu_data)
1822                 return -ENOMEM;
1823
1824         if (!hwp_active && hwp_only)
1825                 goto out;
1826
1827         rc = cpufreq_register_driver(&intel_pstate_driver);
1828         if (rc)
1829                 goto out;
1830
1831         intel_pstate_debug_expose_params();
1832         intel_pstate_sysfs_expose_params();
1833
1834         if (hwp_active)
1835                 pr_info("HWP enabled\n");
1836
1837         return rc;
1838 out:
1839         get_online_cpus();
1840         for_each_online_cpu(cpu) {
1841                 if (all_cpu_data[cpu]) {
1842                         intel_pstate_clear_update_util_hook(cpu);
1843                         kfree(all_cpu_data[cpu]);
1844                 }
1845         }
1846
1847         put_online_cpus();
1848         vfree(all_cpu_data);
1849         return -ENODEV;
1850 }
1851 device_initcall(intel_pstate_init);
1852
1853 static int __init intel_pstate_setup(char *str)
1854 {
1855         if (!str)
1856                 return -EINVAL;
1857
1858         if (!strcmp(str, "disable"))
1859                 no_load = 1;
1860         if (!strcmp(str, "no_hwp")) {
1861                 pr_info("HWP disabled\n");
1862                 no_hwp = 1;
1863         }
1864         if (!strcmp(str, "force"))
1865                 force_load = 1;
1866         if (!strcmp(str, "hwp_only"))
1867                 hwp_only = 1;
1868
1869 #ifdef CONFIG_ACPI
1870         if (!strcmp(str, "support_acpi_ppc"))
1871                 acpi_ppc = true;
1872 #endif
1873
1874         return 0;
1875 }
1876 early_param("intel_pstate", intel_pstate_setup);
1877
1878 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
1879 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
1880 MODULE_LICENSE("GPL");