drivers/crypto/omap-sham.c

   1 /*
   2  * Cryptographic API.
   3  *
   4  * Support for OMAP SHA1/MD5 HW acceleration.
   5  *
   6  * Copyright (c) 2010 Nokia Corporation
   7  * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
   8  * Copyright (c) 2011 Texas Instruments Incorporated
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as published
  12  * by the Free Software Foundation.
  13  *
  14  * Some ideas are from old omap-sha1-md5.c driver.
  15  */
  16
  17 #define pr_fmt(fmt) "%s: " fmt, __func__
  18
  19 #include <linux/err.h>
  20 #include <linux/device.h>
  21 #include <linux/module.h>
  22 #include <linux/init.h>
  23 #include <linux/errno.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/kernel.h>
  26 #include <linux/irq.h>
  27 #include <linux/io.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/scatterlist.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/dmaengine.h>
  32 #include <linux/pm_runtime.h>
  33 #include <linux/of.h>
  34 #include <linux/of_device.h>
  35 #include <linux/of_address.h>
  36 #include <linux/of_irq.h>
  37 #include <linux/delay.h>
  38 #include <linux/crypto.h>
  39 #include <linux/cryptohash.h>
  40 #include <crypto/scatterwalk.h>
  41 #include <crypto/algapi.h>
  42 #include <crypto/sha.h>
  43 #include <crypto/hash.h>
  44 #include <crypto/internal/hash.h>
  45
  46 #define MD5_DIGEST_SIZE                 16
  47
  48 #define SHA_REG_IDIGEST(dd, x)          ((dd)->pdata->idigest_ofs + ((x)*0x04))
  49 #define SHA_REG_DIN(dd, x)              ((dd)->pdata->din_ofs + ((x) * 0x04))
  50 #define SHA_REG_DIGCNT(dd)              ((dd)->pdata->digcnt_ofs)
  51
  52 #define SHA_REG_ODIGEST(dd, x)          ((dd)->pdata->odigest_ofs + (x * 0x04))
  53
  54 #define SHA_REG_CTRL                    0x18
  55 #define SHA_REG_CTRL_LENGTH             (0xFFFFFFFF << 5)
  56 #define SHA_REG_CTRL_CLOSE_HASH         (1 << 4)
  57 #define SHA_REG_CTRL_ALGO_CONST         (1 << 3)
  58 #define SHA_REG_CTRL_ALGO               (1 << 2)
  59 #define SHA_REG_CTRL_INPUT_READY        (1 << 1)
  60 #define SHA_REG_CTRL_OUTPUT_READY       (1 << 0)
  61
  62 #define SHA_REG_REV(dd)                 ((dd)->pdata->rev_ofs)
  63
  64 #define SHA_REG_MASK(dd)                ((dd)->pdata->mask_ofs)
  65 #define SHA_REG_MASK_DMA_EN             (1 << 3)
  66 #define SHA_REG_MASK_IT_EN              (1 << 2)
  67 #define SHA_REG_MASK_SOFTRESET          (1 << 1)
  68 #define SHA_REG_AUTOIDLE                (1 << 0)
  69
  70 #define SHA_REG_SYSSTATUS(dd)           ((dd)->pdata->sysstatus_ofs)
  71 #define SHA_REG_SYSSTATUS_RESETDONE     (1 << 0)
  72
  73 #define SHA_REG_MODE(dd)                ((dd)->pdata->mode_ofs)
  74 #define SHA_REG_MODE_HMAC_OUTER_HASH    (1 << 7)
  75 #define SHA_REG_MODE_HMAC_KEY_PROC      (1 << 5)
  76 #define SHA_REG_MODE_CLOSE_HASH         (1 << 4)
  77 #define SHA_REG_MODE_ALGO_CONSTANT      (1 << 3)
  78
  79 #define SHA_REG_MODE_ALGO_MASK          (7 << 0)
  80 #define SHA_REG_MODE_ALGO_MD5_128       (0 << 1)
  81 #define SHA_REG_MODE_ALGO_SHA1_160      (1 << 1)
  82 #define SHA_REG_MODE_ALGO_SHA2_224      (2 << 1)
  83 #define SHA_REG_MODE_ALGO_SHA2_256      (3 << 1)
  84 #define SHA_REG_MODE_ALGO_SHA2_384      (1 << 0)
  85 #define SHA_REG_MODE_ALGO_SHA2_512      (3 << 0)
  86
  87 #define SHA_REG_LENGTH(dd)              ((dd)->pdata->length_ofs)
  88
  89 #define SHA_REG_IRQSTATUS               0x118
  90 #define SHA_REG_IRQSTATUS_CTX_RDY       (1 << 3)
  91 #define SHA_REG_IRQSTATUS_PARTHASH_RDY (1 << 2)
  92 #define SHA_REG_IRQSTATUS_INPUT_RDY     (1 << 1)
  93 #define SHA_REG_IRQSTATUS_OUTPUT_RDY    (1 << 0)
  94
  95 #define SHA_REG_IRQENA                  0x11C
  96 #define SHA_REG_IRQENA_CTX_RDY          (1 << 3)
  97 #define SHA_REG_IRQENA_PARTHASH_RDY     (1 << 2)
  98 #define SHA_REG_IRQENA_INPUT_RDY        (1 << 1)
  99 #define SHA_REG_IRQENA_OUTPUT_RDY       (1 << 0)
 100
 101 #define DEFAULT_TIMEOUT_INTERVAL        HZ
 102
 103 #define DEFAULT_AUTOSUSPEND_DELAY       1000
 104
 105 /* mostly device flags */
 106 #define FLAGS_BUSY              0
 107 #define FLAGS_FINAL             1
 108 #define FLAGS_DMA_ACTIVE        2
 109 #define FLAGS_OUTPUT_READY      3
 110 #define FLAGS_INIT              4
 111 #define FLAGS_CPU               5
 112 #define FLAGS_DMA_READY         6
 113 #define FLAGS_AUTO_XOR          7
 114 #define FLAGS_BE32_SHA1         8
 115 /* context flags */
 116 #define FLAGS_FINUP             16
 117 #define FLAGS_SG                17
 118
 119 #define FLAGS_MODE_SHIFT        18
 120 #define FLAGS_MODE_MASK         (SHA_REG_MODE_ALGO_MASK << FLAGS_MODE_SHIFT)
 121 #define FLAGS_MODE_MD5          (SHA_REG_MODE_ALGO_MD5_128 << FLAGS_MODE_SHIFT)
 122 #define FLAGS_MODE_SHA1         (SHA_REG_MODE_ALGO_SHA1_160 << FLAGS_MODE_SHIFT)
 123 #define FLAGS_MODE_SHA224       (SHA_REG_MODE_ALGO_SHA2_224 << FLAGS_MODE_SHIFT)
 124 #define FLAGS_MODE_SHA256       (SHA_REG_MODE_ALGO_SHA2_256 << FLAGS_MODE_SHIFT)
 125 #define FLAGS_MODE_SHA384       (SHA_REG_MODE_ALGO_SHA2_384 << FLAGS_MODE_SHIFT)
 126 #define FLAGS_MODE_SHA512       (SHA_REG_MODE_ALGO_SHA2_512 << FLAGS_MODE_SHIFT)
 127
 128 #define FLAGS_HMAC              21
 129 #define FLAGS_ERROR             22
 130
 131 #define OP_UPDATE               1
 132 #define OP_FINAL                2
 133
 134 #define OMAP_ALIGN_MASK         (sizeof(u32)-1)
 135 #define OMAP_ALIGNED            __attribute__((aligned(sizeof(u32))))
 136
 137 #define BUFLEN                  PAGE_SIZE
 138
 139 struct omap_sham_dev;
 140
 141 struct omap_sham_reqctx {
 142         struct omap_sham_dev    *dd;
 143         unsigned long           flags;
 144         unsigned long           op;
 145
 146         u8                      digest[SHA512_DIGEST_SIZE] OMAP_ALIGNED;
 147         size_t                  digcnt;
 148         size_t                  bufcnt;
 149         size_t                  buflen;
 150         dma_addr_t              dma_addr;
 151
 152         /* walk state */
 153         struct scatterlist      *sg;
 154         struct scatterlist      sgl_tmp;
 155         unsigned int            offset; /* offset in current sg */
 156         unsigned int            total;  /* total request */
 157
 158         u8                      buffer[0] OMAP_ALIGNED;
 159 };
 160
 161 struct omap_sham_hmac_ctx {
 162         struct crypto_shash     *shash;
 163         u8                      ipad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
 164         u8                      opad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
 165 };
 166
 167 struct omap_sham_ctx {
 168         struct omap_sham_dev    *dd;
 169
 170         unsigned long           flags;
 171
 172         /* fallback stuff */
 173         struct crypto_shash     *fallback;
 174
 175         struct omap_sham_hmac_ctx base[0];
 176 };
 177
 178 #define OMAP_SHAM_QUEUE_LENGTH  10
 179
 180 struct omap_sham_algs_info {
 181         struct ahash_alg        *algs_list;
 182         unsigned int            size;
 183         unsigned int            registered;
 184 };
 185
 186 struct omap_sham_pdata {
 187         struct omap_sham_algs_info      *algs_info;
 188         unsigned int    algs_info_size;
 189         unsigned long   flags;
 190         int             digest_size;
 191
 192         void            (*copy_hash)(struct ahash_request *req, int out);
 193         void            (*write_ctrl)(struct omap_sham_dev *dd, size_t length,
 194                                       int final, int dma);
 195         void            (*trigger)(struct omap_sham_dev *dd, size_t length);
 196         int             (*poll_irq)(struct omap_sham_dev *dd);
 197         irqreturn_t     (*intr_hdlr)(int irq, void *dev_id);
 198
 199         u32             odigest_ofs;
 200         u32             idigest_ofs;
 201         u32             din_ofs;
 202         u32             digcnt_ofs;
 203         u32             rev_ofs;
 204         u32             mask_ofs;
 205         u32             sysstatus_ofs;
 206         u32             mode_ofs;
 207         u32             length_ofs;
 208
 209         u32             major_mask;
 210         u32             major_shift;
 211         u32             minor_mask;
 212         u32             minor_shift;
 213 };
 214
 215 struct omap_sham_dev {
 216         struct list_head        list;
 217         unsigned long           phys_base;
 218         struct device           *dev;
 219         void __iomem            *io_base;
 220         int                     irq;
 221         spinlock_t              lock;
 222         int                     err;
 223         struct dma_chan         *dma_lch;
 224         struct tasklet_struct   done_task;
 225         u8                      polling_mode;
 226
 227         unsigned long           flags;
 228         struct crypto_queue     queue;
 229         struct ahash_request    *req;
 230
 231         const struct omap_sham_pdata    *pdata;
 232 };
 233
 234 struct omap_sham_drv {
 235         struct list_head        dev_list;
 236         spinlock_t              lock;
 237         unsigned long           flags;
 238 };
 239
 240 static struct omap_sham_drv sham = {
 241         .dev_list = LIST_HEAD_INIT(sham.dev_list),
 242         .lock = __SPIN_LOCK_UNLOCKED(sham.lock),
 243 };
 244
 245 static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset)
 246 {
 247         return __raw_readl(dd->io_base + offset);
 248 }
 249
 250 static inline void omap_sham_write(struct omap_sham_dev *dd,
 251                                         u32 offset, u32 value)
 252 {
 253         __raw_writel(value, dd->io_base + offset);
 254 }
 255
 256 static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address,
 257                                         u32 value, u32 mask)
 258 {
 259         u32 val;
 260
 261         val = omap_sham_read(dd, address);
 262         val &= ~mask;
 263         val |= value;
 264         omap_sham_write(dd, address, val);
 265 }
 266
 267 static inline int omap_sham_wait(struct omap_sham_dev *dd, u32 offset, u32 bit)
 268 {
 269         unsigned long timeout = jiffies + DEFAULT_TIMEOUT_INTERVAL;
 270
 271         while (!(omap_sham_read(dd, offset) & bit)) {
 272                 if (time_is_before_jiffies(timeout))
 273                         return -ETIMEDOUT;
 274         }
 275
 276         return 0;
 277 }
 278
 279 static void omap_sham_copy_hash_omap2(struct ahash_request *req, int out)
 280 {
 281         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 282         struct omap_sham_dev *dd = ctx->dd;
 283         u32 *hash = (u32 *)ctx->digest;
 284         int i;
 285
 286         for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
 287                 if (out)
 288                         hash[i] = omap_sham_read(dd, SHA_REG_IDIGEST(dd, i));
 289                 else
 290                         omap_sham_write(dd, SHA_REG_IDIGEST(dd, i), hash[i]);
 291         }
 292 }
 293
 294 static void omap_sham_copy_hash_omap4(struct ahash_request *req, int out)
 295 {
 296         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 297         struct omap_sham_dev *dd = ctx->dd;
 298         int i;
 299
 300         if (ctx->flags & BIT(FLAGS_HMAC)) {
 301                 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
 302                 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 303                 struct omap_sham_hmac_ctx *bctx = tctx->base;
 304                 u32 *opad = (u32 *)bctx->opad;
 305
 306                 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
 307                         if (out)
 308                                 opad[i] = omap_sham_read(dd,
 309                                                 SHA_REG_ODIGEST(dd, i));
 310                         else
 311                                 omap_sham_write(dd, SHA_REG_ODIGEST(dd, i),
 312                                                 opad[i]);
 313                 }
 314         }
 315
 316         omap_sham_copy_hash_omap2(req, out);
 317 }
 318
 319 static void omap_sham_copy_ready_hash(struct ahash_request *req)
 320 {
 321         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 322         u32 *in = (u32 *)ctx->digest;
 323         u32 *hash = (u32 *)req->result;
 324         int i, d, big_endian = 0;
 325
 326         if (!hash)
 327                 return;
 328
 329         switch (ctx->flags & FLAGS_MODE_MASK) {
 330         case FLAGS_MODE_MD5:
 331                 d = MD5_DIGEST_SIZE / sizeof(u32);
 332                 break;
 333         case FLAGS_MODE_SHA1:
 334                 /* OMAP2 SHA1 is big endian */
 335                 if (test_bit(FLAGS_BE32_SHA1, &ctx->dd->flags))
 336                         big_endian = 1;
 337                 d = SHA1_DIGEST_SIZE / sizeof(u32);
 338                 break;
 339         case FLAGS_MODE_SHA224:
 340                 d = SHA224_DIGEST_SIZE / sizeof(u32);
 341                 break;
 342         case FLAGS_MODE_SHA256:
 343                 d = SHA256_DIGEST_SIZE / sizeof(u32);
 344                 break;
 345         case FLAGS_MODE_SHA384:
 346                 d = SHA384_DIGEST_SIZE / sizeof(u32);
 347                 break;
 348         case FLAGS_MODE_SHA512:
 349                 d = SHA512_DIGEST_SIZE / sizeof(u32);
 350                 break;
 351         default:
 352                 d = 0;
 353         }
 354
 355         if (big_endian)
 356                 for (i = 0; i < d; i++)
 357                         hash[i] = be32_to_cpu(in[i]);
 358         else
 359                 for (i = 0; i < d; i++)
 360                         hash[i] = le32_to_cpu(in[i]);
 361 }
 362
 363 static int omap_sham_hw_init(struct omap_sham_dev *dd)
 364 {
 365         int err;
 366
 367         err = pm_runtime_get_sync(dd->dev);
 368         if (err < 0) {
 369                 dev_err(dd->dev, "failed to get sync: %d\n", err);
 370                 return err;
 371         }
 372
 373         if (!test_bit(FLAGS_INIT, &dd->flags)) {
 374                 set_bit(FLAGS_INIT, &dd->flags);
 375                 dd->err = 0;
 376         }
 377
 378         return 0;
 379 }
 380
 381 static void omap_sham_write_ctrl_omap2(struct omap_sham_dev *dd, size_t length,
 382                                  int final, int dma)
 383 {
 384         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 385         u32 val = length << 5, mask;
 386
 387         if (likely(ctx->digcnt))
 388                 omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt);
 389
 390         omap_sham_write_mask(dd, SHA_REG_MASK(dd),
 391                 SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0),
 392                 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
 393         /*
 394          * Setting ALGO_CONST only for the first iteration
 395          * and CLOSE_HASH only for the last one.
 396          */
 397         if ((ctx->flags & FLAGS_MODE_MASK) == FLAGS_MODE_SHA1)
 398                 val |= SHA_REG_CTRL_ALGO;
 399         if (!ctx->digcnt)
 400                 val |= SHA_REG_CTRL_ALGO_CONST;
 401         if (final)
 402                 val |= SHA_REG_CTRL_CLOSE_HASH;
 403
 404         mask = SHA_REG_CTRL_ALGO_CONST | SHA_REG_CTRL_CLOSE_HASH |
 405                         SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH;
 406
 407         omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask);
 408 }
 409
 410 static void omap_sham_trigger_omap2(struct omap_sham_dev *dd, size_t length)
 411 {
 412 }
 413
 414 static int omap_sham_poll_irq_omap2(struct omap_sham_dev *dd)
 415 {
 416         return omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY);
 417 }
 418
 419 static int get_block_size(struct omap_sham_reqctx *ctx)
 420 {
 421         int d;
 422
 423         switch (ctx->flags & FLAGS_MODE_MASK) {
 424         case FLAGS_MODE_MD5:
 425         case FLAGS_MODE_SHA1:
 426                 d = SHA1_BLOCK_SIZE;
 427                 break;
 428         case FLAGS_MODE_SHA224:
 429         case FLAGS_MODE_SHA256:
 430                 d = SHA256_BLOCK_SIZE;
 431                 break;
 432         case FLAGS_MODE_SHA384:
 433         case FLAGS_MODE_SHA512:
 434                 d = SHA512_BLOCK_SIZE;
 435                 break;
 436         default:
 437                 d = 0;
 438         }
 439
 440         return d;
 441 }
 442
 443 static void omap_sham_write_n(struct omap_sham_dev *dd, u32 offset,
 444                                     u32 *value, int count)
 445 {
 446         for (; count--; value++, offset += 4)
 447                 omap_sham_write(dd, offset, *value);
 448 }
 449
 450 static void omap_sham_write_ctrl_omap4(struct omap_sham_dev *dd, size_t length,
 451                                  int final, int dma)
 452 {
 453         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 454         u32 val, mask;
 455
 456         /*
 457          * Setting ALGO_CONST only for the first iteration and
 458          * CLOSE_HASH only for the last one. Note that flags mode bits
 459          * correspond to algorithm encoding in mode register.
 460          */
 461         val = (ctx->flags & FLAGS_MODE_MASK) >> (FLAGS_MODE_SHIFT);
 462         if (!ctx->digcnt) {
 463                 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
 464                 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 465                 struct omap_sham_hmac_ctx *bctx = tctx->base;
 466                 int bs, nr_dr;
 467
 468                 val |= SHA_REG_MODE_ALGO_CONSTANT;
 469
 470                 if (ctx->flags & BIT(FLAGS_HMAC)) {
 471                         bs = get_block_size(ctx);
 472                         nr_dr = bs / (2 * sizeof(u32));
 473                         val |= SHA_REG_MODE_HMAC_KEY_PROC;
 474                         omap_sham_write_n(dd, SHA_REG_ODIGEST(dd, 0),
 475                                           (u32 *)bctx->ipad, nr_dr);
 476                         omap_sham_write_n(dd, SHA_REG_IDIGEST(dd, 0),
 477                                           (u32 *)bctx->ipad + nr_dr, nr_dr);
 478                         ctx->digcnt += bs;
 479                 }
 480         }
 481
 482         if (final) {
 483                 val |= SHA_REG_MODE_CLOSE_HASH;
 484
 485                 if (ctx->flags & BIT(FLAGS_HMAC))
 486                         val |= SHA_REG_MODE_HMAC_OUTER_HASH;
 487         }
 488
 489         mask = SHA_REG_MODE_ALGO_CONSTANT | SHA_REG_MODE_CLOSE_HASH |
 490                SHA_REG_MODE_ALGO_MASK | SHA_REG_MODE_HMAC_OUTER_HASH |
 491                SHA_REG_MODE_HMAC_KEY_PROC;
 492
 493         dev_dbg(dd->dev, "ctrl: %08x, flags: %08lx\n", val, ctx->flags);
 494         omap_sham_write_mask(dd, SHA_REG_MODE(dd), val, mask);
 495         omap_sham_write(dd, SHA_REG_IRQENA, SHA_REG_IRQENA_OUTPUT_RDY);
 496         omap_sham_write_mask(dd, SHA_REG_MASK(dd),
 497                              SHA_REG_MASK_IT_EN |
 498                                      (dma ? SHA_REG_MASK_DMA_EN : 0),
 499                              SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
 500 }
 501
 502 static void omap_sham_trigger_omap4(struct omap_sham_dev *dd, size_t length)
 503 {
 504         omap_sham_write(dd, SHA_REG_LENGTH(dd), length);
 505 }
 506
 507 static int omap_sham_poll_irq_omap4(struct omap_sham_dev *dd)
 508 {
 509         return omap_sham_wait(dd, SHA_REG_IRQSTATUS,
 510                               SHA_REG_IRQSTATUS_INPUT_RDY);
 511 }
 512
 513 static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, const u8 *buf,
 514                               size_t length, int final)
 515 {
 516         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 517         int count, len32, bs32, offset = 0;
 518         const u32 *buffer = (const u32 *)buf;
 519
 520         dev_dbg(dd->dev, "xmit_cpu: digcnt: %d, length: %d, final: %d\n",
 521                                                 ctx->digcnt, length, final);
 522
 523         dd->pdata->write_ctrl(dd, length, final, 0);
 524         dd->pdata->trigger(dd, length);
 525
 526         /* should be non-zero before next lines to disable clocks later */
 527         ctx->digcnt += length;
 528
 529         if (final)
 530                 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
 531
 532         set_bit(FLAGS_CPU, &dd->flags);
 533
 534         len32 = DIV_ROUND_UP(length, sizeof(u32));
 535         bs32 = get_block_size(ctx) / sizeof(u32);
 536
 537         while (len32) {
 538                 if (dd->pdata->poll_irq(dd))
 539                         return -ETIMEDOUT;
 540
 541                 for (count = 0; count < min(len32, bs32); count++, offset++)
 542                         omap_sham_write(dd, SHA_REG_DIN(dd, count),
 543                                         buffer[offset]);
 544                 len32 -= min(len32, bs32);
 545         }
 546
 547         return -EINPROGRESS;
 548 }
 549
 550 static void omap_sham_dma_callback(void *param)
 551 {
 552         struct omap_sham_dev *dd = param;
 553
 554         set_bit(FLAGS_DMA_READY, &dd->flags);
 555         tasklet_schedule(&dd->done_task);
 556 }
 557
 558 static int omap_sham_xmit_dma(struct omap_sham_dev *dd, dma_addr_t dma_addr,
 559                               size_t length, int final, int is_sg)
 560 {
 561         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 562         struct dma_async_tx_descriptor *tx;
 563         struct dma_slave_config cfg;
 564         int len32, ret, dma_min = get_block_size(ctx);
 565
 566         dev_dbg(dd->dev, "xmit_dma: digcnt: %d, length: %d, final: %d\n",
 567                                                 ctx->digcnt, length, final);
 568
 569         memset(&cfg, 0, sizeof(cfg));
 570
 571         cfg.dst_addr = dd->phys_base + SHA_REG_DIN(dd, 0);
 572         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 573         cfg.dst_maxburst = dma_min / DMA_SLAVE_BUSWIDTH_4_BYTES;
 574
 575         ret = dmaengine_slave_config(dd->dma_lch, &cfg);
 576         if (ret) {
 577                 pr_err("omap-sham: can't configure dmaengine slave: %d\n", ret);
 578                 return ret;
 579         }
 580
 581         len32 = DIV_ROUND_UP(length, dma_min) * dma_min;
 582
 583         if (is_sg) {
 584                 /*
 585                  * The SG entry passed in may not have the 'length' member
 586                  * set correctly so use a local SG entry (sgl_tmp) with the
 587                  * proper value for 'length' instead.  If this is not done,
 588                  * the dmaengine may try to DMA the incorrect amount of data.
 589                  */
 590                 sg_init_table(&ctx->sgl_tmp, 1);
 591                 sg_assign_page(&ctx->sgl_tmp, sg_page(ctx->sg));
 592                 ctx->sgl_tmp.offset = ctx->sg->offset;
 593                 sg_dma_len(&ctx->sgl_tmp) = len32;
 594                 sg_dma_address(&ctx->sgl_tmp) = sg_dma_address(ctx->sg);
 595
 596                 tx = dmaengine_prep_slave_sg(dd->dma_lch, &ctx->sgl_tmp, 1,
 597                                              DMA_MEM_TO_DEV,
 598                                              DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 599         } else {
 600                 tx = dmaengine_prep_slave_single(dd->dma_lch, dma_addr, len32,
 601                         DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 602         }
 603
 604         if (!tx) {
 605                 dev_err(dd->dev, "prep_slave_sg/single() failed\n");
 606                 return -EINVAL;
 607         }
 608
 609         tx->callback = omap_sham_dma_callback;
 610         tx->callback_param = dd;
 611
 612         dd->pdata->write_ctrl(dd, length, final, 1);
 613
 614         ctx->digcnt += length;
 615
 616         if (final)
 617                 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
 618
 619         set_bit(FLAGS_DMA_ACTIVE, &dd->flags);
 620
 621         dmaengine_submit(tx);
 622         dma_async_issue_pending(dd->dma_lch);
 623
 624         dd->pdata->trigger(dd, length);
 625
 626         return -EINPROGRESS;
 627 }
 628
 629 static size_t omap_sham_append_buffer(struct omap_sham_reqctx *ctx,
 630                                 const u8 *data, size_t length)
 631 {
 632         size_t count = min(length, ctx->buflen - ctx->bufcnt);
 633
 634         count = min(count, ctx->total);
 635         if (count <= 0)
 636                 return 0;
 637         memcpy(ctx->buffer + ctx->bufcnt, data, count);
 638         ctx->bufcnt += count;
 639
 640         return count;
 641 }
 642
 643 static size_t omap_sham_append_sg(struct omap_sham_reqctx *ctx)
 644 {
 645         size_t count;
 646         const u8 *vaddr;
 647
 648         while (ctx->sg) {
 649                 vaddr = kmap_atomic(sg_page(ctx->sg));
 650                 vaddr += ctx->sg->offset;
 651
 652                 count = omap_sham_append_buffer(ctx,
 653                                 vaddr + ctx->offset,
 654                                 ctx->sg->length - ctx->offset);
 655
 656                 kunmap_atomic((void *)vaddr);
 657
 658                 if (!count)
 659                         break;
 660                 ctx->offset += count;
 661                 ctx->total -= count;
 662                 if (ctx->offset == ctx->sg->length) {
 663                         ctx->sg = sg_next(ctx->sg);
 664                         if (ctx->sg)
 665                                 ctx->offset = 0;
 666                         else
 667                                 ctx->total = 0;
 668                 }
 669         }
 670
 671         return 0;
 672 }
 673
 674 static int omap_sham_xmit_dma_map(struct omap_sham_dev *dd,
 675                                         struct omap_sham_reqctx *ctx,
 676                                         size_t length, int final)
 677 {
 678         int ret;
 679
 680         ctx->dma_addr = dma_map_single(dd->dev, ctx->buffer, ctx->buflen,
 681                                        DMA_TO_DEVICE);
 682         if (dma_mapping_error(dd->dev, ctx->dma_addr)) {
 683                 dev_err(dd->dev, "dma %u bytes error\n", ctx->buflen);
 684                 return -EINVAL;
 685         }
 686
 687         ctx->flags &= ~BIT(FLAGS_SG);
 688
 689         ret = omap_sham_xmit_dma(dd, ctx->dma_addr, length, final, 0);
 690         if (ret != -EINPROGRESS)
 691                 dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen,
 692                                  DMA_TO_DEVICE);
 693
 694         return ret;
 695 }
 696
 697 static int omap_sham_update_dma_slow(struct omap_sham_dev *dd)
 698 {
 699         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 700         unsigned int final;
 701         size_t count;
 702
 703         omap_sham_append_sg(ctx);
 704
 705         final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total;
 706
 707         dev_dbg(dd->dev, "slow: bufcnt: %u, digcnt: %d, final: %d\n",
 708                                          ctx->bufcnt, ctx->digcnt, final);
 709
 710         if (final || (ctx->bufcnt == ctx->buflen && ctx->total)) {
 711                 count = ctx->bufcnt;
 712                 ctx->bufcnt = 0;
 713                 return omap_sham_xmit_dma_map(dd, ctx, count, final);
 714         }
 715
 716         return 0;
 717 }
 718
 719 /* Start address alignment */
 720 #define SG_AA(sg)       (IS_ALIGNED(sg->offset, sizeof(u32)))
 721 /* SHA1 block size alignment */
 722 #define SG_SA(sg, bs)   (IS_ALIGNED(sg->length, bs))
 723
 724 static int omap_sham_update_dma_start(struct omap_sham_dev *dd)
 725 {
 726         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 727         unsigned int length, final, tail;
 728         struct scatterlist *sg;
 729         int ret, bs;
 730
 731         if (!ctx->total)
 732                 return 0;
 733
 734         if (ctx->bufcnt || ctx->offset)
 735                 return omap_sham_update_dma_slow(dd);
 736
 737         /*
 738          * Don't use the sg interface when the transfer size is less
 739          * than the number of elements in a DMA frame.  Otherwise,
 740          * the dmaengine infrastructure will calculate that it needs
 741          * to transfer 0 frames which ultimately fails.
 742          */
 743         if (ctx->total < get_block_size(ctx))
 744                 return omap_sham_update_dma_slow(dd);
 745
 746         dev_dbg(dd->dev, "fast: digcnt: %d, bufcnt: %u, total: %u\n",
 747                         ctx->digcnt, ctx->bufcnt, ctx->total);
 748
 749         sg = ctx->sg;
 750         bs = get_block_size(ctx);
 751
 752         if (!SG_AA(sg))
 753                 return omap_sham_update_dma_slow(dd);
 754
 755         if (!sg_is_last(sg) && !SG_SA(sg, bs))
 756                 /* size is not BLOCK_SIZE aligned */
 757                 return omap_sham_update_dma_slow(dd);
 758
 759         length = min(ctx->total, sg->length);
 760
 761         if (sg_is_last(sg)) {
 762                 if (!(ctx->flags & BIT(FLAGS_FINUP))) {
 763                         /* not last sg must be BLOCK_SIZE aligned */
 764                         tail = length & (bs - 1);
 765                         /* without finup() we need one block to close hash */
 766                         if (!tail)
 767                                 tail = bs;
 768                         length -= tail;
 769                 }
 770         }
 771
 772         if (!dma_map_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE)) {
 773                 dev_err(dd->dev, "dma_map_sg  error\n");
 774                 return -EINVAL;
 775         }
 776
 777         ctx->flags |= BIT(FLAGS_SG);
 778
 779         ctx->total -= length;
 780         ctx->offset = length; /* offset where to start slow */
 781
 782         final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total;
 783
 784         ret = omap_sham_xmit_dma(dd, sg_dma_address(ctx->sg), length, final, 1);
 785         if (ret != -EINPROGRESS)
 786                 dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE);
 787
 788         return ret;
 789 }
 790
 791 static int omap_sham_update_cpu(struct omap_sham_dev *dd)
 792 {
 793         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 794         int bufcnt, final;
 795
 796         if (!ctx->total)
 797                 return 0;
 798
 799         omap_sham_append_sg(ctx);
 800
 801         final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total;
 802
 803         dev_dbg(dd->dev, "cpu: bufcnt: %u, digcnt: %d, final: %d\n",
 804                 ctx->bufcnt, ctx->digcnt, final);
 805
 806         if (final || (ctx->bufcnt == ctx->buflen && ctx->total)) {
 807                 bufcnt = ctx->bufcnt;
 808                 ctx->bufcnt = 0;
 809                 return omap_sham_xmit_cpu(dd, ctx->buffer, bufcnt, final);
 810         }
 811
 812         return 0;
 813 }
 814
 815 static int omap_sham_update_dma_stop(struct omap_sham_dev *dd)
 816 {
 817         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 818
 819
 820         if (ctx->flags & BIT(FLAGS_SG)) {
 821                 dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE);
 822                 if (ctx->sg->length == ctx->offset) {
 823                         ctx->sg = sg_next(ctx->sg);
 824                         if (ctx->sg)
 825                                 ctx->offset = 0;
 826                 }
 827         } else {
 828                 dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen,
 829                                  DMA_TO_DEVICE);
 830         }
 831
 832         return 0;
 833 }
 834
 835 static int omap_sham_init(struct ahash_request *req)
 836 {
 837         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 838         struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 839         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 840         struct omap_sham_dev *dd = NULL, *tmp;
 841         int bs = 0;
 842
 843         spin_lock_bh(&sham.lock);
 844         if (!tctx->dd) {
 845                 list_for_each_entry(tmp, &sham.dev_list, list) {
 846                         dd = tmp;
 847                         break;
 848                 }
 849                 tctx->dd = dd;
 850         } else {
 851                 dd = tctx->dd;
 852         }
 853         spin_unlock_bh(&sham.lock);
 854
 855         ctx->dd = dd;
 856
 857         ctx->flags = 0;
 858
 859         dev_dbg(dd->dev, "init: digest size: %d\n",
 860                 crypto_ahash_digestsize(tfm));
 861
 862         switch (crypto_ahash_digestsize(tfm)) {
 863         case MD5_DIGEST_SIZE:
 864                 ctx->flags |= FLAGS_MODE_MD5;
 865                 bs = SHA1_BLOCK_SIZE;
 866                 break;
 867         case SHA1_DIGEST_SIZE:
 868                 ctx->flags |= FLAGS_MODE_SHA1;
 869                 bs = SHA1_BLOCK_SIZE;
 870                 break;
 871         case SHA224_DIGEST_SIZE:
 872                 ctx->flags |= FLAGS_MODE_SHA224;
 873                 bs = SHA224_BLOCK_SIZE;
 874                 break;
 875         case SHA256_DIGEST_SIZE:
 876                 ctx->flags |= FLAGS_MODE_SHA256;
 877                 bs = SHA256_BLOCK_SIZE;
 878                 break;
 879         case SHA384_DIGEST_SIZE:
 880                 ctx->flags |= FLAGS_MODE_SHA384;
 881                 bs = SHA384_BLOCK_SIZE;
 882                 break;
 883         case SHA512_DIGEST_SIZE:
 884                 ctx->flags |= FLAGS_MODE_SHA512;
 885                 bs = SHA512_BLOCK_SIZE;
 886                 break;
 887         }
 888
 889         ctx->bufcnt = 0;
 890         ctx->digcnt = 0;
 891         ctx->buflen = BUFLEN;
 892
 893         if (tctx->flags & BIT(FLAGS_HMAC)) {
 894                 if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) {
 895                         struct omap_sham_hmac_ctx *bctx = tctx->base;
 896
 897                         memcpy(ctx->buffer, bctx->ipad, bs);
 898                         ctx->bufcnt = bs;
 899                 }
 900
 901                 ctx->flags |= BIT(FLAGS_HMAC);
 902         }
 903
 904         return 0;
 905
 906 }
 907
 908 static int omap_sham_update_req(struct omap_sham_dev *dd)
 909 {
 910         struct ahash_request *req = dd->req;
 911         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 912         int err;
 913
 914         dev_dbg(dd->dev, "update_req: total: %u, digcnt: %d, finup: %d\n",
 915                  ctx->total, ctx->digcnt, (ctx->flags & BIT(FLAGS_FINUP)) != 0);
 916
 917         if (ctx->flags & BIT(FLAGS_CPU))
 918                 err = omap_sham_update_cpu(dd);
 919         else
 920                 err = omap_sham_update_dma_start(dd);
 921
 922         /* wait for dma completion before can take more data */
 923         dev_dbg(dd->dev, "update: err: %d, digcnt: %d\n", err, ctx->digcnt);
 924
 925         return err;
 926 }
 927
 928 static int omap_sham_final_req(struct omap_sham_dev *dd)
 929 {
 930         struct ahash_request *req = dd->req;
 931         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 932         int err = 0, use_dma = 1;
 933
 934         if ((ctx->bufcnt <= get_block_size(ctx)) || dd->polling_mode)
 935                 /*
 936                  * faster to handle last block with cpu or
 937                  * use cpu when dma is not present.
 938                  */
 939                 use_dma = 0;
 940
 941         if (use_dma)
 942                 err = omap_sham_xmit_dma_map(dd, ctx, ctx->bufcnt, 1);
 943         else
 944                 err = omap_sham_xmit_cpu(dd, ctx->buffer, ctx->bufcnt, 1);
 945
 946         ctx->bufcnt = 0;
 947
 948         dev_dbg(dd->dev, "final_req: err: %d\n", err);
 949
 950         return err;
 951 }
 952
 953 static int omap_sham_finish_hmac(struct ahash_request *req)
 954 {
 955         struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
 956         struct omap_sham_hmac_ctx *bctx = tctx->base;
 957         int bs = crypto_shash_blocksize(bctx->shash);
 958         int ds = crypto_shash_digestsize(bctx->shash);
 959         SHASH_DESC_ON_STACK(shash, bctx->shash);
 960
 961         shash->tfm = bctx->shash;
 962         shash->flags = 0; /* not CRYPTO_TFM_REQ_MAY_SLEEP */
 963
 964         return crypto_shash_init(shash) ?:
 965                crypto_shash_update(shash, bctx->opad, bs) ?:
 966                crypto_shash_finup(shash, req->result, ds, req->result);
 967 }
 968
 969 static int omap_sham_finish(struct ahash_request *req)
 970 {
 971         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 972         struct omap_sham_dev *dd = ctx->dd;
 973         int err = 0;
 974
 975         if (ctx->digcnt) {
 976                 omap_sham_copy_ready_hash(req);
 977                 if ((ctx->flags & BIT(FLAGS_HMAC)) &&
 978                                 !test_bit(FLAGS_AUTO_XOR, &dd->flags))
 979                         err = omap_sham_finish_hmac(req);
 980         }
 981
 982         dev_dbg(dd->dev, "digcnt: %d, bufcnt: %d\n", ctx->digcnt, ctx->bufcnt);
 983
 984         return err;
 985 }
 986
 987 static void omap_sham_finish_req(struct ahash_request *req, int err)
 988 {
 989         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 990         struct omap_sham_dev *dd = ctx->dd;
 991
 992         if (!err) {
 993                 dd->pdata->copy_hash(req, 1);
 994                 if (test_bit(FLAGS_FINAL, &dd->flags))
 995                         err = omap_sham_finish(req);
 996         } else {
 997                 ctx->flags |= BIT(FLAGS_ERROR);
 998         }
 999
1000         /* atomic operation is not needed here */
1001         dd->flags &= ~(BIT(FLAGS_BUSY) | BIT(FLAGS_FINAL) | BIT(FLAGS_CPU) |
1002                         BIT(FLAGS_DMA_READY) | BIT(FLAGS_OUTPUT_READY));
1003
1004         pm_runtime_mark_last_busy(dd->dev);
1005         pm_runtime_put_autosuspend(dd->dev);
1006
1007         if (req->base.complete)
1008                 req->base.complete(&req->base, err);
1009 }
1010
1011 static int omap_sham_handle_queue(struct omap_sham_dev *dd,
1012                                   struct ahash_request *req)
1013 {
1014         struct crypto_async_request *async_req, *backlog;
1015         struct omap_sham_reqctx *ctx;
1016         unsigned long flags;
1017         int err = 0, ret = 0;
1018
1019 retry:
1020         spin_lock_irqsave(&dd->lock, flags);
1021         if (req)
1022                 ret = ahash_enqueue_request(&dd->queue, req);
1023         if (test_bit(FLAGS_BUSY, &dd->flags)) {
1024                 spin_unlock_irqrestore(&dd->lock, flags);
1025                 return ret;
1026         }
1027         backlog = crypto_get_backlog(&dd->queue);
1028         async_req = crypto_dequeue_request(&dd->queue);
1029         if (async_req)
1030                 set_bit(FLAGS_BUSY, &dd->flags);
1031         spin_unlock_irqrestore(&dd->lock, flags);
1032
1033         if (!async_req)
1034                 return ret;
1035
1036         if (backlog)
1037                 backlog->complete(backlog, -EINPROGRESS);
1038
1039         req = ahash_request_cast(async_req);
1040         dd->req = req;
1041         ctx = ahash_request_ctx(req);
1042
1043         dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n",
1044                                                 ctx->op, req->nbytes);
1045
1046         err = omap_sham_hw_init(dd);
1047         if (err)
1048                 goto err1;
1049
1050         if (ctx->digcnt)
1051                 /* request has changed - restore hash */
1052                 dd->pdata->copy_hash(req, 0);
1053
1054         if (ctx->op == OP_UPDATE) {
1055                 err = omap_sham_update_req(dd);
1056                 if (err != -EINPROGRESS && (ctx->flags & BIT(FLAGS_FINUP)))
1057                         /* no final() after finup() */
1058                         err = omap_sham_final_req(dd);
1059         } else if (ctx->op == OP_FINAL) {
1060                 err = omap_sham_final_req(dd);
1061         }
1062 err1:
1063         dev_dbg(dd->dev, "exit, err: %d\n", err);
1064
1065         if (err != -EINPROGRESS) {
1066                 /* done_task will not finish it, so do it here */
1067                 omap_sham_finish_req(req, err);
1068                 req = NULL;
1069
1070                 /*
1071                  * Execute next request immediately if there is anything
1072                  * in queue.
1073                  */
1074                 goto retry;
1075         }
1076
1077         return ret;
1078 }
1079
1080 static int omap_sham_enqueue(struct ahash_request *req, unsigned int op)
1081 {
1082         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1083         struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1084         struct omap_sham_dev *dd = tctx->dd;
1085
1086         ctx->op = op;
1087
1088         return omap_sham_handle_queue(dd, req);
1089 }
1090
1091 static int omap_sham_update(struct ahash_request *req)
1092 {
1093         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1094         struct omap_sham_dev *dd = ctx->dd;
1095         int bs = get_block_size(ctx);
1096
1097         if (!req->nbytes)
1098                 return 0;
1099
1100         ctx->total = req->nbytes;
1101         ctx->sg = req->src;
1102         ctx->offset = 0;
1103
1104         if (ctx->flags & BIT(FLAGS_FINUP)) {
1105                 if ((ctx->digcnt + ctx->bufcnt + ctx->total) < 240) {
1106                         /*
1107                         * OMAP HW accel works only with buffers >= 9
1108                         * will switch to bypass in final()
1109                         * final has the same request and data
1110                         */
1111                         omap_sham_append_sg(ctx);
1112                         return 0;
1113                 } else if ((ctx->bufcnt + ctx->total <= bs) ||
1114                            dd->polling_mode) {
1115                         /*
1116                          * faster to use CPU for short transfers or
1117                          * use cpu when dma is not present.
1118                          */
1119                         ctx->flags |= BIT(FLAGS_CPU);
1120                 }
1121         } else if (ctx->bufcnt + ctx->total < ctx->buflen) {
1122                 omap_sham_append_sg(ctx);
1123                 return 0;
1124         }
1125
1126         if (dd->polling_mode)
1127                 ctx->flags |= BIT(FLAGS_CPU);
1128
1129         return omap_sham_enqueue(req, OP_UPDATE);
1130 }
1131
1132 static int omap_sham_shash_digest(struct crypto_shash *tfm, u32 flags,
1133                                   const u8 *data, unsigned int len, u8 *out)
1134 {
1135         SHASH_DESC_ON_STACK(shash, tfm);
1136
1137         shash->tfm = tfm;
1138         shash->flags = flags & CRYPTO_TFM_REQ_MAY_SLEEP;
1139
1140         return crypto_shash_digest(shash, data, len, out);
1141 }
1142
1143 static int omap_sham_final_shash(struct ahash_request *req)
1144 {
1145         struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1146         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1147         int offset = 0;
1148
1149         /*
1150          * If we are running HMAC on limited hardware support, skip
1151          * the ipad in the beginning of the buffer if we are going for
1152          * software fallback algorithm.
1153          */
1154         if (test_bit(FLAGS_HMAC, &ctx->flags) &&
1155             !test_bit(FLAGS_AUTO_XOR, &ctx->dd->flags))
1156                 offset = get_block_size(ctx);
1157
1158         return omap_sham_shash_digest(tctx->fallback, req->base.flags,
1159                                       ctx->buffer + offset,
1160                                       ctx->bufcnt - offset, req->result);
1161 }
1162
1163 static int omap_sham_final(struct ahash_request *req)
1164 {
1165         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1166
1167         ctx->flags |= BIT(FLAGS_FINUP);
1168
1169         if (ctx->flags & BIT(FLAGS_ERROR))
1170                 return 0; /* uncompleted hash is not needed */
1171
1172         /*
1173          * OMAP HW accel works only with buffers >= 9.
1174          * HMAC is always >= 9 because ipad == block size.
1175          * If buffersize is less than 240, we use fallback SW encoding,
1176          * as using DMA + HW in this case doesn't provide any benefit.
1177          */
1178         if (!ctx->digcnt && ctx->bufcnt < 240)
1179                 return omap_sham_final_shash(req);
1180         else if (ctx->bufcnt)
1181                 return omap_sham_enqueue(req, OP_FINAL);
1182
1183         /* copy ready hash (+ finalize hmac) */
1184         return omap_sham_finish(req);
1185 }
1186
1187 static int omap_sham_finup(struct ahash_request *req)
1188 {
1189         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1190         int err1, err2;
1191
1192         ctx->flags |= BIT(FLAGS_FINUP);
1193
1194         err1 = omap_sham_update(req);
1195         if (err1 == -EINPROGRESS || err1 == -EBUSY)
1196                 return err1;
1197         /*
1198          * final() has to be always called to cleanup resources
1199          * even if udpate() failed, except EINPROGRESS
1200          */
1201         err2 = omap_sham_final(req);
1202
1203         return err1 ?: err2;
1204 }
1205
1206 static int omap_sham_digest(struct ahash_request *req)
1207 {
1208         return omap_sham_init(req) ?: omap_sham_finup(req);
1209 }
1210
1211 static int omap_sham_setkey(struct crypto_ahash *tfm, const u8 *key,
1212                       unsigned int keylen)
1213 {
1214         struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
1215         struct omap_sham_hmac_ctx *bctx = tctx->base;
1216         int bs = crypto_shash_blocksize(bctx->shash);
1217         int ds = crypto_shash_digestsize(bctx->shash);
1218         struct omap_sham_dev *dd = NULL, *tmp;
1219         int err, i;
1220
1221         spin_lock_bh(&sham.lock);
1222         if (!tctx->dd) {
1223                 list_for_each_entry(tmp, &sham.dev_list, list) {
1224                         dd = tmp;
1225                         break;
1226                 }
1227                 tctx->dd = dd;
1228         } else {
1229                 dd = tctx->dd;
1230         }
1231         spin_unlock_bh(&sham.lock);
1232
1233         err = crypto_shash_setkey(tctx->fallback, key, keylen);
1234         if (err)
1235                 return err;
1236
1237         if (keylen > bs) {
1238                 err = omap_sham_shash_digest(bctx->shash,
1239                                 crypto_shash_get_flags(bctx->shash),
1240                                 key, keylen, bctx->ipad);
1241                 if (err)
1242                         return err;
1243                 keylen = ds;
1244         } else {
1245                 memcpy(bctx->ipad, key, keylen);
1246         }
1247
1248         memset(bctx->ipad + keylen, 0, bs - keylen);
1249
1250         if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) {
1251                 memcpy(bctx->opad, bctx->ipad, bs);
1252
1253                 for (i = 0; i < bs; i++) {
1254                         bctx->ipad[i] ^= 0x36;
1255                         bctx->opad[i] ^= 0x5c;
1256                 }
1257         }
1258
1259         return err;
1260 }
1261
1262 static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base)
1263 {
1264         struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1265         const char *alg_name = crypto_tfm_alg_name(tfm);
1266
1267         /* Allocate a fallback and abort if it failed. */
1268         tctx->fallback = crypto_alloc_shash(alg_name, 0,
1269                                             CRYPTO_ALG_NEED_FALLBACK);
1270         if (IS_ERR(tctx->fallback)) {
1271                 pr_err("omap-sham: fallback driver '%s' "
1272                                 "could not be loaded.\n", alg_name);
1273                 return PTR_ERR(tctx->fallback);
1274         }
1275
1276         crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1277                                  sizeof(struct omap_sham_reqctx) + BUFLEN);
1278
1279         if (alg_base) {
1280                 struct omap_sham_hmac_ctx *bctx = tctx->base;
1281                 tctx->flags |= BIT(FLAGS_HMAC);
1282                 bctx->shash = crypto_alloc_shash(alg_base, 0,
1283                                                 CRYPTO_ALG_NEED_FALLBACK);
1284                 if (IS_ERR(bctx->shash)) {
1285                         pr_err("omap-sham: base driver '%s' "
1286                                         "could not be loaded.\n", alg_base);
1287                         crypto_free_shash(tctx->fallback);
1288                         return PTR_ERR(bctx->shash);
1289                 }
1290
1291         }
1292
1293         return 0;
1294 }
1295
1296 static int omap_sham_cra_init(struct crypto_tfm *tfm)
1297 {
1298         return omap_sham_cra_init_alg(tfm, NULL);
1299 }
1300
1301 static int omap_sham_cra_sha1_init(struct crypto_tfm *tfm)
1302 {
1303         return omap_sham_cra_init_alg(tfm, "sha1");
1304 }
1305
1306 static int omap_sham_cra_sha224_init(struct crypto_tfm *tfm)
1307 {
1308         return omap_sham_cra_init_alg(tfm, "sha224");
1309 }
1310
1311 static int omap_sham_cra_sha256_init(struct crypto_tfm *tfm)
1312 {
1313         return omap_sham_cra_init_alg(tfm, "sha256");
1314 }
1315
1316 static int omap_sham_cra_md5_init(struct crypto_tfm *tfm)
1317 {
1318         return omap_sham_cra_init_alg(tfm, "md5");
1319 }
1320
1321 static int omap_sham_cra_sha384_init(struct crypto_tfm *tfm)
1322 {
1323         return omap_sham_cra_init_alg(tfm, "sha384");
1324 }
1325
1326 static int omap_sham_cra_sha512_init(struct crypto_tfm *tfm)
1327 {
1328         return omap_sham_cra_init_alg(tfm, "sha512");
1329 }
1330
1331 static void omap_sham_cra_exit(struct crypto_tfm *tfm)
1332 {
1333         struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1334
1335         crypto_free_shash(tctx->fallback);
1336         tctx->fallback = NULL;
1337
1338         if (tctx->flags & BIT(FLAGS_HMAC)) {
1339                 struct omap_sham_hmac_ctx *bctx = tctx->base;
1340                 crypto_free_shash(bctx->shash);
1341         }
1342 }
1343
1344 static int omap_sham_export(struct ahash_request *req, void *out)
1345 {
1346         return -ENOTSUPP;
1347 }
1348
1349 static int omap_sham_import(struct ahash_request *req, const void *in)
1350 {
1351         return -ENOTSUPP;
1352 }
1353
1354 static struct ahash_alg algs_sha1_md5[] = {
1355 {
1356         .init           = omap_sham_init,
1357         .update         = omap_sham_update,
1358         .final          = omap_sham_final,
1359         .finup          = omap_sham_finup,
1360         .digest         = omap_sham_digest,
1361         .halg.digestsize        = SHA1_DIGEST_SIZE,
1362         .halg.base      = {
1363                 .cra_name               = "sha1",
1364                 .cra_driver_name        = "omap-sha1",
1365                 .cra_priority           = 400,
1366                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1367                                                 CRYPTO_ALG_KERN_DRIVER_ONLY |
1368                                                 CRYPTO_ALG_ASYNC |
1369                                                 CRYPTO_ALG_NEED_FALLBACK,
1370                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1371                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1372                 .cra_alignmask          = OMAP_ALIGN_MASK,
1373                 .cra_module             = THIS_MODULE,
1374                 .cra_init               = omap_sham_cra_init,
1375                 .cra_exit               = omap_sham_cra_exit,
1376         }
1377 },
1378 {
1379         .init           = omap_sham_init,
1380         .update         = omap_sham_update,
1381         .final          = omap_sham_final,
1382         .finup          = omap_sham_finup,
1383         .digest         = omap_sham_digest,
1384         .halg.digestsize        = MD5_DIGEST_SIZE,
1385         .halg.base      = {
1386                 .cra_name               = "md5",
1387                 .cra_driver_name        = "omap-md5",
1388                 .cra_priority           = 400,
1389                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1390                                                 CRYPTO_ALG_KERN_DRIVER_ONLY |
1391                                                 CRYPTO_ALG_ASYNC |
1392                                                 CRYPTO_ALG_NEED_FALLBACK,
1393                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1394                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1395                 .cra_alignmask          = OMAP_ALIGN_MASK,
1396                 .cra_module             = THIS_MODULE,
1397                 .cra_init               = omap_sham_cra_init,
1398                 .cra_exit               = omap_sham_cra_exit,
1399         }
1400 },
1401 {
1402         .init           = omap_sham_init,
1403         .update         = omap_sham_update,
1404         .final          = omap_sham_final,
1405         .finup          = omap_sham_finup,
1406         .digest         = omap_sham_digest,
1407         .setkey         = omap_sham_setkey,
1408         .halg.digestsize        = SHA1_DIGEST_SIZE,
1409         .halg.base      = {
1410                 .cra_name               = "hmac(sha1)",
1411                 .cra_driver_name        = "omap-hmac-sha1",
1412                 .cra_priority           = 400,
1413                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1414                                                 CRYPTO_ALG_KERN_DRIVER_ONLY |
1415                                                 CRYPTO_ALG_ASYNC |
1416                                                 CRYPTO_ALG_NEED_FALLBACK,
1417                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1418                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1419                                         sizeof(struct omap_sham_hmac_ctx),
1420                 .cra_alignmask          = OMAP_ALIGN_MASK,
1421                 .cra_module             = THIS_MODULE,
1422                 .cra_init               = omap_sham_cra_sha1_init,
1423                 .cra_exit               = omap_sham_cra_exit,
1424         }
1425 },
1426 {
1427         .init           = omap_sham_init,
1428         .update         = omap_sham_update,
1429         .final          = omap_sham_final,
1430         .finup          = omap_sham_finup,
1431         .digest         = omap_sham_digest,
1432         .setkey         = omap_sham_setkey,
1433         .halg.digestsize        = MD5_DIGEST_SIZE,
1434         .halg.base      = {
1435                 .cra_name               = "hmac(md5)",
1436                 .cra_driver_name        = "omap-hmac-md5",
1437                 .cra_priority           = 400,
1438                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1439                                                 CRYPTO_ALG_KERN_DRIVER_ONLY |
1440                                                 CRYPTO_ALG_ASYNC |
1441                                                 CRYPTO_ALG_NEED_FALLBACK,
1442                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1443                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1444                                         sizeof(struct omap_sham_hmac_ctx),
1445                 .cra_alignmask          = OMAP_ALIGN_MASK,
1446                 .cra_module             = THIS_MODULE,
1447                 .cra_init               = omap_sham_cra_md5_init,
1448                 .cra_exit               = omap_sham_cra_exit,
1449         }
1450 }
1451 };
1452
1453 /* OMAP4 has some algs in addition to what OMAP2 has */
1454 static struct ahash_alg algs_sha224_sha256[] = {
1455 {
1456         .init           = omap_sham_init,
1457         .update         = omap_sham_update,
1458         .final          = omap_sham_final,
1459         .finup          = omap_sham_finup,
1460         .digest         = omap_sham_digest,
1461         .halg.digestsize        = SHA224_DIGEST_SIZE,
1462         .halg.base      = {
1463                 .cra_name               = "sha224",
1464                 .cra_driver_name        = "omap-sha224",
1465                 .cra_priority           = 400,
1466                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1467                                                 CRYPTO_ALG_ASYNC |
1468                                                 CRYPTO_ALG_NEED_FALLBACK,
1469                 .cra_blocksize          = SHA224_BLOCK_SIZE,
1470                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1471                 .cra_alignmask          = OMAP_ALIGN_MASK,
1472                 .cra_module             = THIS_MODULE,
1473                 .cra_init               = omap_sham_cra_init,
1474                 .cra_exit               = omap_sham_cra_exit,
1475         }
1476 },
1477 {
1478         .init           = omap_sham_init,
1479         .update         = omap_sham_update,
1480         .final          = omap_sham_final,
1481         .finup          = omap_sham_finup,
1482         .digest         = omap_sham_digest,
1483         .halg.digestsize        = SHA256_DIGEST_SIZE,
1484         .halg.base      = {
1485                 .cra_name               = "sha256",
1486                 .cra_driver_name        = "omap-sha256",
1487                 .cra_priority           = 400,
1488                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1489                                                 CRYPTO_ALG_ASYNC |
1490                                                 CRYPTO_ALG_NEED_FALLBACK,
1491                 .cra_blocksize          = SHA256_BLOCK_SIZE,
1492                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1493                 .cra_alignmask          = OMAP_ALIGN_MASK,
1494                 .cra_module             = THIS_MODULE,
1495                 .cra_init               = omap_sham_cra_init,
1496                 .cra_exit               = omap_sham_cra_exit,
1497         }
1498 },
1499 {
1500         .init           = omap_sham_init,
1501         .update         = omap_sham_update,
1502         .final          = omap_sham_final,
1503         .finup          = omap_sham_finup,
1504         .digest         = omap_sham_digest,
1505         .setkey         = omap_sham_setkey,
1506         .halg.digestsize        = SHA224_DIGEST_SIZE,
1507         .halg.base      = {
1508                 .cra_name               = "hmac(sha224)",
1509                 .cra_driver_name        = "omap-hmac-sha224",
1510                 .cra_priority           = 400,
1511                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1512                                                 CRYPTO_ALG_ASYNC |
1513                                                 CRYPTO_ALG_NEED_FALLBACK,
1514                 .cra_blocksize          = SHA224_BLOCK_SIZE,
1515                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1516                                         sizeof(struct omap_sham_hmac_ctx),
1517                 .cra_alignmask          = OMAP_ALIGN_MASK,
1518                 .cra_module             = THIS_MODULE,
1519                 .cra_init               = omap_sham_cra_sha224_init,
1520                 .cra_exit               = omap_sham_cra_exit,
1521         }
1522 },
1523 {
1524         .init           = omap_sham_init,
1525         .update         = omap_sham_update,
1526         .final          = omap_sham_final,
1527         .finup          = omap_sham_finup,
1528         .digest         = omap_sham_digest,
1529         .setkey         = omap_sham_setkey,
1530         .halg.digestsize        = SHA256_DIGEST_SIZE,
1531         .halg.base      = {
1532                 .cra_name               = "hmac(sha256)",
1533                 .cra_driver_name        = "omap-hmac-sha256",
1534                 .cra_priority           = 400,
1535                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1536                                                 CRYPTO_ALG_ASYNC |
1537                                                 CRYPTO_ALG_NEED_FALLBACK,
1538                 .cra_blocksize          = SHA256_BLOCK_SIZE,
1539                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1540                                         sizeof(struct omap_sham_hmac_ctx),
1541                 .cra_alignmask          = OMAP_ALIGN_MASK,
1542                 .cra_module             = THIS_MODULE,
1543                 .cra_init               = omap_sham_cra_sha256_init,
1544                 .cra_exit               = omap_sham_cra_exit,
1545         }
1546 },
1547 };
1548
1549 static struct ahash_alg algs_sha384_sha512[] = {
1550 {
1551         .init           = omap_sham_init,
1552         .update         = omap_sham_update,
1553         .final          = omap_sham_final,
1554         .finup          = omap_sham_finup,
1555         .digest         = omap_sham_digest,
1556         .halg.digestsize        = SHA384_DIGEST_SIZE,
1557         .halg.base      = {
1558                 .cra_name               = "sha384",
1559                 .cra_driver_name        = "omap-sha384",
1560                 .cra_priority           = 400,
1561                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1562                                                 CRYPTO_ALG_ASYNC |
1563                                                 CRYPTO_ALG_NEED_FALLBACK,
1564                 .cra_blocksize          = SHA384_BLOCK_SIZE,
1565                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1566                 .cra_alignmask          = OMAP_ALIGN_MASK,
1567                 .cra_module             = THIS_MODULE,
1568                 .cra_init               = omap_sham_cra_init,
1569                 .cra_exit               = omap_sham_cra_exit,
1570         }
1571 },
1572 {
1573         .init           = omap_sham_init,
1574         .update         = omap_sham_update,
1575         .final          = omap_sham_final,
1576         .finup          = omap_sham_finup,
1577         .digest         = omap_sham_digest,
1578         .halg.digestsize        = SHA512_DIGEST_SIZE,
1579         .halg.base      = {
1580                 .cra_name               = "sha512",
1581                 .cra_driver_name        = "omap-sha512",
1582                 .cra_priority           = 400,
1583                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1584                                                 CRYPTO_ALG_ASYNC |
1585                                                 CRYPTO_ALG_NEED_FALLBACK,
1586                 .cra_blocksize          = SHA512_BLOCK_SIZE,
1587                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1588                 .cra_alignmask          = OMAP_ALIGN_MASK,
1589                 .cra_module             = THIS_MODULE,
1590                 .cra_init               = omap_sham_cra_init,
1591                 .cra_exit               = omap_sham_cra_exit,
1592         }
1593 },
1594 {
1595         .init           = omap_sham_init,
1596         .update         = omap_sham_update,
1597         .final          = omap_sham_final,
1598         .finup          = omap_sham_finup,
1599         .digest         = omap_sham_digest,
1600         .setkey         = omap_sham_setkey,
1601         .halg.digestsize        = SHA384_DIGEST_SIZE,
1602         .halg.base      = {
1603                 .cra_name               = "hmac(sha384)",
1604                 .cra_driver_name        = "omap-hmac-sha384",
1605                 .cra_priority           = 400,
1606                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1607                                                 CRYPTO_ALG_ASYNC |
1608                                                 CRYPTO_ALG_NEED_FALLBACK,
1609                 .cra_blocksize          = SHA384_BLOCK_SIZE,
1610                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1611                                         sizeof(struct omap_sham_hmac_ctx),
1612                 .cra_alignmask          = OMAP_ALIGN_MASK,
1613                 .cra_module             = THIS_MODULE,
1614                 .cra_init               = omap_sham_cra_sha384_init,
1615                 .cra_exit               = omap_sham_cra_exit,
1616         }
1617 },
1618 {
1619         .init           = omap_sham_init,
1620         .update         = omap_sham_update,
1621         .final          = omap_sham_final,
1622         .finup          = omap_sham_finup,
1623         .digest         = omap_sham_digest,
1624         .setkey         = omap_sham_setkey,
1625         .halg.digestsize        = SHA512_DIGEST_SIZE,
1626         .halg.base      = {
1627                 .cra_name               = "hmac(sha512)",
1628                 .cra_driver_name        = "omap-hmac-sha512",
1629                 .cra_priority           = 400,
1630                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1631                                                 CRYPTO_ALG_ASYNC |
1632                                                 CRYPTO_ALG_NEED_FALLBACK,
1633                 .cra_blocksize          = SHA512_BLOCK_SIZE,
1634                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1635                                         sizeof(struct omap_sham_hmac_ctx),
1636                 .cra_alignmask          = OMAP_ALIGN_MASK,
1637                 .cra_module             = THIS_MODULE,
1638                 .cra_init               = omap_sham_cra_sha512_init,
1639                 .cra_exit               = omap_sham_cra_exit,
1640         }
1641 },
1642 };
1643
1644 static void omap_sham_done_task(unsigned long data)
1645 {
1646         struct omap_sham_dev *dd = (struct omap_sham_dev *)data;
1647         int err = 0;
1648
1649         if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1650                 omap_sham_handle_queue(dd, NULL);
1651                 return;
1652         }
1653
1654         if (test_bit(FLAGS_CPU, &dd->flags)) {
1655                 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) {
1656                         /* hash or semi-hash ready */
1657                         err = omap_sham_update_cpu(dd);
1658                         if (err != -EINPROGRESS)
1659                                 goto finish;
1660                 }
1661         } else if (test_bit(FLAGS_DMA_READY, &dd->flags)) {
1662                 if (test_and_clear_bit(FLAGS_DMA_ACTIVE, &dd->flags)) {
1663                         omap_sham_update_dma_stop(dd);
1664                         if (dd->err) {
1665                                 err = dd->err;
1666                                 goto finish;
1667                         }
1668                 }
1669                 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) {
1670                         /* hash or semi-hash ready */
1671                         clear_bit(FLAGS_DMA_READY, &dd->flags);
1672                         err = omap_sham_update_dma_start(dd);
1673                         if (err != -EINPROGRESS)
1674                                 goto finish;
1675                 }
1676         }
1677
1678         return;
1679
1680 finish:
1681         dev_dbg(dd->dev, "update done: err: %d\n", err);
1682         /* finish curent request */
1683         omap_sham_finish_req(dd->req, err);
1684
1685         /* If we are not busy, process next req */
1686         if (!test_bit(FLAGS_BUSY, &dd->flags))
1687                 omap_sham_handle_queue(dd, NULL);
1688 }
1689
1690 static irqreturn_t omap_sham_irq_common(struct omap_sham_dev *dd)
1691 {
1692         if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1693                 dev_warn(dd->dev, "Interrupt when no active requests.\n");
1694         } else {
1695                 set_bit(FLAGS_OUTPUT_READY, &dd->flags);
1696                 tasklet_schedule(&dd->done_task);
1697         }
1698
1699         return IRQ_HANDLED;
1700 }
1701
1702 static irqreturn_t omap_sham_irq_omap2(int irq, void *dev_id)
1703 {
1704         struct omap_sham_dev *dd = dev_id;
1705
1706         if (unlikely(test_bit(FLAGS_FINAL, &dd->flags)))
1707                 /* final -> allow device to go to power-saving mode */
1708                 omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH);
1709
1710         omap_sham_write_mask(dd, SHA_REG_CTRL, SHA_REG_CTRL_OUTPUT_READY,
1711                                  SHA_REG_CTRL_OUTPUT_READY);
1712         omap_sham_read(dd, SHA_REG_CTRL);
1713
1714         return omap_sham_irq_common(dd);
1715 }
1716
1717 static irqreturn_t omap_sham_irq_omap4(int irq, void *dev_id)
1718 {
1719         struct omap_sham_dev *dd = dev_id;
1720
1721         omap_sham_write_mask(dd, SHA_REG_MASK(dd), 0, SHA_REG_MASK_IT_EN);
1722
1723         return omap_sham_irq_common(dd);
1724 }
1725
1726 static struct omap_sham_algs_info omap_sham_algs_info_omap2[] = {
1727         {
1728                 .algs_list      = algs_sha1_md5,
1729                 .size           = ARRAY_SIZE(algs_sha1_md5),
1730         },
1731 };
1732
1733 static const struct omap_sham_pdata omap_sham_pdata_omap2 = {
1734         .algs_info      = omap_sham_algs_info_omap2,
1735         .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap2),
1736         .flags          = BIT(FLAGS_BE32_SHA1),
1737         .digest_size    = SHA1_DIGEST_SIZE,
1738         .copy_hash      = omap_sham_copy_hash_omap2,
1739         .write_ctrl     = omap_sham_write_ctrl_omap2,
1740         .trigger        = omap_sham_trigger_omap2,
1741         .poll_irq       = omap_sham_poll_irq_omap2,
1742         .intr_hdlr      = omap_sham_irq_omap2,
1743         .idigest_ofs    = 0x00,
1744         .din_ofs        = 0x1c,
1745         .digcnt_ofs     = 0x14,
1746         .rev_ofs        = 0x5c,
1747         .mask_ofs       = 0x60,
1748         .sysstatus_ofs  = 0x64,
1749         .major_mask     = 0xf0,
1750         .major_shift    = 4,
1751         .minor_mask     = 0x0f,
1752         .minor_shift    = 0,
1753 };
1754
1755 #ifdef CONFIG_OF
1756 static struct omap_sham_algs_info omap_sham_algs_info_omap4[] = {
1757         {
1758                 .algs_list      = algs_sha1_md5,
1759                 .size           = ARRAY_SIZE(algs_sha1_md5),
1760         },
1761         {
1762                 .algs_list      = algs_sha224_sha256,
1763                 .size           = ARRAY_SIZE(algs_sha224_sha256),
1764         },
1765 };
1766
1767 static const struct omap_sham_pdata omap_sham_pdata_omap4 = {
1768         .algs_info      = omap_sham_algs_info_omap4,
1769         .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap4),
1770         .flags          = BIT(FLAGS_AUTO_XOR),
1771         .digest_size    = SHA256_DIGEST_SIZE,
1772         .copy_hash      = omap_sham_copy_hash_omap4,
1773         .write_ctrl     = omap_sham_write_ctrl_omap4,
1774         .trigger        = omap_sham_trigger_omap4,
1775         .poll_irq       = omap_sham_poll_irq_omap4,
1776         .intr_hdlr      = omap_sham_irq_omap4,
1777         .idigest_ofs    = 0x020,
1778         .odigest_ofs    = 0x0,
1779         .din_ofs        = 0x080,
1780         .digcnt_ofs     = 0x040,
1781         .rev_ofs        = 0x100,
1782         .mask_ofs       = 0x110,
1783         .sysstatus_ofs  = 0x114,
1784         .mode_ofs       = 0x44,
1785         .length_ofs     = 0x48,
1786         .major_mask     = 0x0700,
1787         .major_shift    = 8,
1788         .minor_mask     = 0x003f,
1789         .minor_shift    = 0,
1790 };
1791
1792 static struct omap_sham_algs_info omap_sham_algs_info_omap5[] = {
1793         {
1794                 .algs_list      = algs_sha1_md5,
1795                 .size           = ARRAY_SIZE(algs_sha1_md5),
1796         },
1797         {
1798                 .algs_list      = algs_sha224_sha256,
1799                 .size           = ARRAY_SIZE(algs_sha224_sha256),
1800         },
1801         {
1802                 .algs_list      = algs_sha384_sha512,
1803                 .size           = ARRAY_SIZE(algs_sha384_sha512),
1804         },
1805 };
1806
1807 static const struct omap_sham_pdata omap_sham_pdata_omap5 = {
1808         .algs_info      = omap_sham_algs_info_omap5,
1809         .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap5),
1810         .flags          = BIT(FLAGS_AUTO_XOR),
1811         .digest_size    = SHA512_DIGEST_SIZE,
1812         .copy_hash      = omap_sham_copy_hash_omap4,
1813         .write_ctrl     = omap_sham_write_ctrl_omap4,
1814         .trigger        = omap_sham_trigger_omap4,
1815         .poll_irq       = omap_sham_poll_irq_omap4,
1816         .intr_hdlr      = omap_sham_irq_omap4,
1817         .idigest_ofs    = 0x240,
1818         .odigest_ofs    = 0x200,
1819         .din_ofs        = 0x080,
1820         .digcnt_ofs     = 0x280,
1821         .rev_ofs        = 0x100,
1822         .mask_ofs       = 0x110,
1823         .sysstatus_ofs  = 0x114,
1824         .mode_ofs       = 0x284,
1825         .length_ofs     = 0x288,
1826         .major_mask     = 0x0700,
1827         .major_shift    = 8,
1828         .minor_mask     = 0x003f,
1829         .minor_shift    = 0,
1830 };
1831
1832 static const struct of_device_id omap_sham_of_match[] = {
1833         {
1834                 .compatible     = "ti,omap2-sham",
1835                 .data           = &omap_sham_pdata_omap2,
1836         },
1837         {
1838                 .compatible     = "ti,omap3-sham",
1839                 .data           = &omap_sham_pdata_omap2,
1840         },
1841         {
1842                 .compatible     = "ti,omap4-sham",
1843                 .data           = &omap_sham_pdata_omap4,
1844         },
1845         {
1846                 .compatible     = "ti,omap5-sham",
1847                 .data           = &omap_sham_pdata_omap5,
1848         },
1849         {},
1850 };
1851 MODULE_DEVICE_TABLE(of, omap_sham_of_match);
1852
1853 static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1854                 struct device *dev, struct resource *res)
1855 {
1856         struct device_node *node = dev->of_node;
1857         const struct of_device_id *match;
1858         int err = 0;
1859
1860         match = of_match_device(of_match_ptr(omap_sham_of_match), dev);
1861         if (!match) {
1862                 dev_err(dev, "no compatible OF match\n");
1863                 err = -EINVAL;
1864                 goto err;
1865         }
1866
1867         err = of_address_to_resource(node, 0, res);
1868         if (err < 0) {
1869                 dev_err(dev, "can't translate OF node address\n");
1870                 err = -EINVAL;
1871                 goto err;
1872         }
1873
1874         dd->irq = irq_of_parse_and_map(node, 0);
1875         if (!dd->irq) {
1876                 dev_err(dev, "can't translate OF irq value\n");
1877                 err = -EINVAL;
1878                 goto err;
1879         }
1880
1881         dd->pdata = match->data;
1882
1883 err:
1884         return err;
1885 }
1886 #else
1887 static const struct of_device_id omap_sham_of_match[] = {
1888         {},
1889 };
1890
1891 static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1892                 struct device *dev, struct resource *res)
1893 {
1894         return -EINVAL;
1895 }
1896 #endif
1897
1898 static int omap_sham_get_res_pdev(struct omap_sham_dev *dd,
1899                 struct platform_device *pdev, struct resource *res)
1900 {
1901         struct device *dev = &pdev->dev;
1902         struct resource *r;
1903         int err = 0;
1904
1905         /* Get the base address */
1906         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1907         if (!r) {
1908                 dev_err(dev, "no MEM resource info\n");
1909                 err = -ENODEV;
1910                 goto err;
1911         }
1912         memcpy(res, r, sizeof(*res));
1913
1914         /* Get the IRQ */
1915         dd->irq = platform_get_irq(pdev, 0);
1916         if (dd->irq < 0) {
1917                 dev_err(dev, "no IRQ resource info\n");
1918                 err = dd->irq;
1919                 goto err;
1920         }
1921
1922         /* Only OMAP2/3 can be non-DT */
1923         dd->pdata = &omap_sham_pdata_omap2;
1924
1925 err:
1926         return err;
1927 }
1928
1929 static int omap_sham_probe(struct platform_device *pdev)
1930 {
1931         struct omap_sham_dev *dd;
1932         struct device *dev = &pdev->dev;
1933         struct resource res;
1934         dma_cap_mask_t mask;
1935         int err, i, j;
1936         u32 rev;
1937
1938         dd = devm_kzalloc(dev, sizeof(struct omap_sham_dev), GFP_KERNEL);
1939         if (dd == NULL) {
1940                 dev_err(dev, "unable to alloc data struct.\n");
1941                 err = -ENOMEM;
1942                 goto data_err;
1943         }
1944         dd->dev = dev;
1945         platform_set_drvdata(pdev, dd);
1946
1947         INIT_LIST_HEAD(&dd->list);
1948         spin_lock_init(&dd->lock);
1949         tasklet_init(&dd->done_task, omap_sham_done_task, (unsigned long)dd);
1950         crypto_init_queue(&dd->queue, OMAP_SHAM_QUEUE_LENGTH);
1951
1952         err = (dev->of_node) ? omap_sham_get_res_of(dd, dev, &res) :
1953                                omap_sham_get_res_pdev(dd, pdev, &res);
1954         if (err)
1955                 goto data_err;
1956
1957         dd->io_base = devm_ioremap_resource(dev, &res);
1958         if (IS_ERR(dd->io_base)) {
1959                 err = PTR_ERR(dd->io_base);
1960                 goto data_err;
1961         }
1962         dd->phys_base = res.start;
1963
1964         err = devm_request_irq(dev, dd->irq, dd->pdata->intr_hdlr,
1965                                IRQF_TRIGGER_NONE, dev_name(dev), dd);
1966         if (err) {
1967                 dev_err(dev, "unable to request irq %d, err = %d\n",
1968                         dd->irq, err);
1969                 goto data_err;
1970         }
1971
1972         dma_cap_zero(mask);
1973         dma_cap_set(DMA_SLAVE, mask);
1974
1975         dd->dma_lch = dma_request_chan(dev, "rx");
1976         if (IS_ERR(dd->dma_lch)) {
1977                 err = PTR_ERR(dd->dma_lch);
1978                 if (err == -EPROBE_DEFER)
1979                         goto data_err;
1980
1981                 dd->polling_mode = 1;
1982                 dev_dbg(dev, "using polling mode instead of dma\n");
1983         }
1984
1985         dd->flags |= dd->pdata->flags;
1986
1987         pm_runtime_use_autosuspend(dev);
1988         pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY);
1989
1990         pm_runtime_enable(dev);
1991         pm_runtime_irq_safe(dev);
1992
1993         err = pm_runtime_get_sync(dev);
1994         if (err < 0) {
1995                 dev_err(dev, "failed to get sync: %d\n", err);
1996                 goto err_pm;
1997         }
1998
1999         rev = omap_sham_read(dd, SHA_REG_REV(dd));
2000         pm_runtime_put_sync(&pdev->dev);
2001
2002         dev_info(dev, "hw accel on OMAP rev %u.%u\n",
2003                 (rev & dd->pdata->major_mask) >> dd->pdata->major_shift,
2004                 (rev & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
2005
2006         spin_lock(&sham.lock);
2007         list_add_tail(&dd->list, &sham.dev_list);
2008         spin_unlock(&sham.lock);
2009
2010         for (i = 0; i < dd->pdata->algs_info_size; i++) {
2011                 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
2012                         struct ahash_alg *alg;
2013
2014                         alg = &dd->pdata->algs_info[i].algs_list[j];
2015                         alg->export = omap_sham_export;
2016                         alg->import = omap_sham_import;
2017                         alg->halg.statesize = sizeof(struct omap_sham_reqctx);
2018                         err = crypto_register_ahash(alg);
2019                         if (err)
2020                                 goto err_algs;
2021
2022                         dd->pdata->algs_info[i].registered++;
2023                 }
2024         }
2025
2026         return 0;
2027
2028 err_algs:
2029         for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
2030                 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
2031                         crypto_unregister_ahash(
2032                                         &dd->pdata->algs_info[i].algs_list[j]);
2033 err_pm:
2034         pm_runtime_disable(dev);
2035         if (!dd->polling_mode)
2036                 dma_release_channel(dd->dma_lch);
2037 data_err:
2038         dev_err(dev, "initialization failed.\n");
2039
2040         return err;
2041 }
2042
2043 static int omap_sham_remove(struct platform_device *pdev)
2044 {
2045         static struct omap_sham_dev *dd;
2046         int i, j;
2047
2048         dd = platform_get_drvdata(pdev);
2049         if (!dd)
2050                 return -ENODEV;
2051         spin_lock(&sham.lock);
2052         list_del(&dd->list);
2053         spin_unlock(&sham.lock);
2054         for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
2055                 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
2056                         crypto_unregister_ahash(
2057                                         &dd->pdata->algs_info[i].algs_list[j]);
2058         tasklet_kill(&dd->done_task);
2059         pm_runtime_disable(&pdev->dev);
2060
2061         if (!dd->polling_mode)
2062                 dma_release_channel(dd->dma_lch);
2063
2064         return 0;
2065 }
2066
2067 #ifdef CONFIG_PM_SLEEP
2068 static int omap_sham_suspend(struct device *dev)
2069 {
2070         pm_runtime_put_sync(dev);
2071         return 0;
2072 }
2073
2074 static int omap_sham_resume(struct device *dev)
2075 {
2076         int err = pm_runtime_get_sync(dev);
2077         if (err < 0) {
2078                 dev_err(dev, "failed to get sync: %d\n", err);
2079                 return err;
2080         }
2081         return 0;
2082 }
2083 #endif
2084
2085 static SIMPLE_DEV_PM_OPS(omap_sham_pm_ops, omap_sham_suspend, omap_sham_resume);
2086
2087 static struct platform_driver omap_sham_driver = {
2088         .probe  = omap_sham_probe,
2089         .remove = omap_sham_remove,
2090         .driver = {
2091                 .name   = "omap-sham",
2092                 .pm     = &omap_sham_pm_ops,
2093                 .of_match_table = omap_sham_of_match,
2094         },
2095 };
2096
2097 module_platform_driver(omap_sham_driver);
2098
2099 MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support.");
2100 MODULE_LICENSE("GPL v2");
2101 MODULE_AUTHOR("Dmitry Kasatkin");
2102 MODULE_ALIAS("platform:omap-sham");