drivers/dma/fsl-edma.c

   1 /*
   2  * drivers/dma/fsl-edma.c
   3  *
   4  * Copyright 2013-2014 Freescale Semiconductor, Inc.
   5  *
   6  * Driver for the Freescale eDMA engine with flexible channel multiplexing
   7  * capability for DMA request sources. The eDMA block can be found on some
   8  * Vybrid and Layerscape SoCs.
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/module.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/clk.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/dmapool.h>
  22 #include <linux/slab.h>
  23 #include <linux/spinlock.h>
  24 #include <linux/of.h>
  25 #include <linux/of_device.h>
  26 #include <linux/of_address.h>
  27 #include <linux/of_irq.h>
  28 #include <linux/of_dma.h>
  29
  30 #include "virt-dma.h"
  31
  32 #define EDMA_CR                 0x00
  33 #define EDMA_ES                 0x04
  34 #define EDMA_ERQ                0x0C
  35 #define EDMA_EEI                0x14
  36 #define EDMA_SERQ               0x1B
  37 #define EDMA_CERQ               0x1A
  38 #define EDMA_SEEI               0x19
  39 #define EDMA_CEEI               0x18
  40 #define EDMA_CINT               0x1F
  41 #define EDMA_CERR               0x1E
  42 #define EDMA_SSRT               0x1D
  43 #define EDMA_CDNE               0x1C
  44 #define EDMA_INTR               0x24
  45 #define EDMA_ERR                0x2C
  46
  47 #define EDMA_TCD_SADDR(x)       (0x1000 + 32 * (x))
  48 #define EDMA_TCD_SOFF(x)        (0x1004 + 32 * (x))
  49 #define EDMA_TCD_ATTR(x)        (0x1006 + 32 * (x))
  50 #define EDMA_TCD_NBYTES(x)      (0x1008 + 32 * (x))
  51 #define EDMA_TCD_SLAST(x)       (0x100C + 32 * (x))
  52 #define EDMA_TCD_DADDR(x)       (0x1010 + 32 * (x))
  53 #define EDMA_TCD_DOFF(x)        (0x1014 + 32 * (x))
  54 #define EDMA_TCD_CITER_ELINK(x) (0x1016 + 32 * (x))
  55 #define EDMA_TCD_CITER(x)       (0x1016 + 32 * (x))
  56 #define EDMA_TCD_DLAST_SGA(x)   (0x1018 + 32 * (x))
  57 #define EDMA_TCD_CSR(x)         (0x101C + 32 * (x))
  58 #define EDMA_TCD_BITER_ELINK(x) (0x101E + 32 * (x))
  59 #define EDMA_TCD_BITER(x)       (0x101E + 32 * (x))
  60
  61 #define EDMA_CR_EDBG            BIT(1)
  62 #define EDMA_CR_ERCA            BIT(2)
  63 #define EDMA_CR_ERGA            BIT(3)
  64 #define EDMA_CR_HOE             BIT(4)
  65 #define EDMA_CR_HALT            BIT(5)
  66 #define EDMA_CR_CLM             BIT(6)
  67 #define EDMA_CR_EMLM            BIT(7)
  68 #define EDMA_CR_ECX             BIT(16)
  69 #define EDMA_CR_CX              BIT(17)
  70
  71 #define EDMA_SEEI_SEEI(x)       ((x) & 0x1F)
  72 #define EDMA_CEEI_CEEI(x)       ((x) & 0x1F)
  73 #define EDMA_CINT_CINT(x)       ((x) & 0x1F)
  74 #define EDMA_CERR_CERR(x)       ((x) & 0x1F)
  75
  76 #define EDMA_TCD_ATTR_DSIZE(x)          (((x) & 0x0007))
  77 #define EDMA_TCD_ATTR_DMOD(x)           (((x) & 0x001F) << 3)
  78 #define EDMA_TCD_ATTR_SSIZE(x)          (((x) & 0x0007) << 8)
  79 #define EDMA_TCD_ATTR_SMOD(x)           (((x) & 0x001F) << 11)
  80 #define EDMA_TCD_ATTR_SSIZE_8BIT        (0x0000)
  81 #define EDMA_TCD_ATTR_SSIZE_16BIT       (0x0100)
  82 #define EDMA_TCD_ATTR_SSIZE_32BIT       (0x0200)
  83 #define EDMA_TCD_ATTR_SSIZE_64BIT       (0x0300)
  84 #define EDMA_TCD_ATTR_SSIZE_32BYTE      (0x0500)
  85 #define EDMA_TCD_ATTR_DSIZE_8BIT        (0x0000)
  86 #define EDMA_TCD_ATTR_DSIZE_16BIT       (0x0001)
  87 #define EDMA_TCD_ATTR_DSIZE_32BIT       (0x0002)
  88 #define EDMA_TCD_ATTR_DSIZE_64BIT       (0x0003)
  89 #define EDMA_TCD_ATTR_DSIZE_32BYTE      (0x0005)
  90
  91 #define EDMA_TCD_SOFF_SOFF(x)           (x)
  92 #define EDMA_TCD_NBYTES_NBYTES(x)       (x)
  93 #define EDMA_TCD_SLAST_SLAST(x)         (x)
  94 #define EDMA_TCD_DADDR_DADDR(x)         (x)
  95 #define EDMA_TCD_CITER_CITER(x)         ((x) & 0x7FFF)
  96 #define EDMA_TCD_DOFF_DOFF(x)           (x)
  97 #define EDMA_TCD_DLAST_SGA_DLAST_SGA(x) (x)
  98 #define EDMA_TCD_BITER_BITER(x)         ((x) & 0x7FFF)
  99
 100 #define EDMA_TCD_CSR_START              BIT(0)
 101 #define EDMA_TCD_CSR_INT_MAJOR          BIT(1)
 102 #define EDMA_TCD_CSR_INT_HALF           BIT(2)
 103 #define EDMA_TCD_CSR_D_REQ              BIT(3)
 104 #define EDMA_TCD_CSR_E_SG               BIT(4)
 105 #define EDMA_TCD_CSR_E_LINK             BIT(5)
 106 #define EDMA_TCD_CSR_ACTIVE             BIT(6)
 107 #define EDMA_TCD_CSR_DONE               BIT(7)
 108
 109 #define EDMAMUX_CHCFG_DIS               0x0
 110 #define EDMAMUX_CHCFG_ENBL              0x80
 111 #define EDMAMUX_CHCFG_SOURCE(n)         ((n) & 0x3F)
 112
 113 #define DMAMUX_NR       2
 114
 115 #define FSL_EDMA_BUSWIDTHS      BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
 116                                 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
 117                                 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
 118                                 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)
 119
 120 struct fsl_edma_hw_tcd {
 121         __le32  saddr;
 122         __le16  soff;
 123         __le16  attr;
 124         __le32  nbytes;
 125         __le32  slast;
 126         __le32  daddr;
 127         __le16  doff;
 128         __le16  citer;
 129         __le32  dlast_sga;
 130         __le16  csr;
 131         __le16  biter;
 132 };
 133
 134 struct fsl_edma_sw_tcd {
 135         dma_addr_t                      ptcd;
 136         struct fsl_edma_hw_tcd          *vtcd;
 137 };
 138
 139 struct fsl_edma_slave_config {
 140         enum dma_transfer_direction     dir;
 141         enum dma_slave_buswidth         addr_width;
 142         u32                             dev_addr;
 143         u32                             burst;
 144         u32                             attr;
 145 };
 146
 147 struct fsl_edma_chan {
 148         struct virt_dma_chan            vchan;
 149         enum dma_status                 status;
 150         struct fsl_edma_engine          *edma;
 151         struct fsl_edma_desc            *edesc;
 152         struct fsl_edma_slave_config    fsc;
 153         struct dma_pool                 *tcd_pool;
 154 };
 155
 156 struct fsl_edma_desc {
 157         struct virt_dma_desc            vdesc;
 158         struct fsl_edma_chan            *echan;
 159         bool                            iscyclic;
 160         unsigned int                    n_tcds;
 161         struct fsl_edma_sw_tcd          tcd[];
 162 };
 163
 164 struct fsl_edma_engine {
 165         struct dma_device       dma_dev;
 166         void __iomem            *membase;
 167         void __iomem            *muxbase[DMAMUX_NR];
 168         struct clk              *muxclk[DMAMUX_NR];
 169         struct mutex            fsl_edma_mutex;
 170         u32                     n_chans;
 171         int                     txirq;
 172         int                     errirq;
 173         bool                    big_endian;
 174         struct fsl_edma_chan    chans[];
 175 };
 176
 177 /*
 178  * R/W functions for big- or little-endian registers:
 179  * The eDMA controller's endian is independent of the CPU core's endian.
 180  * For the big-endian IP module, the offset for 8-bit or 16-bit registers
 181  * should also be swapped opposite to that in little-endian IP.
 182  */
 183
 184 static u32 edma_readl(struct fsl_edma_engine *edma, void __iomem *addr)
 185 {
 186         if (edma->big_endian)
 187                 return ioread32be(addr);
 188         else
 189                 return ioread32(addr);
 190 }
 191
 192 static void edma_writeb(struct fsl_edma_engine *edma, u8 val, void __iomem *addr)
 193 {
 194         /* swap the reg offset for these in big-endian mode */
 195         if (edma->big_endian)
 196                 iowrite8(val, (void __iomem *)((unsigned long)addr ^ 0x3));
 197         else
 198                 iowrite8(val, addr);
 199 }
 200
 201 static void edma_writew(struct fsl_edma_engine *edma, u16 val, void __iomem *addr)
 202 {
 203         /* swap the reg offset for these in big-endian mode */
 204         if (edma->big_endian)
 205                 iowrite16be(val, (void __iomem *)((unsigned long)addr ^ 0x2));
 206         else
 207                 iowrite16(val, addr);
 208 }
 209
 210 static void edma_writel(struct fsl_edma_engine *edma, u32 val, void __iomem *addr)
 211 {
 212         if (edma->big_endian)
 213                 iowrite32be(val, addr);
 214         else
 215                 iowrite32(val, addr);
 216 }
 217
 218 static struct fsl_edma_chan *to_fsl_edma_chan(struct dma_chan *chan)
 219 {
 220         return container_of(chan, struct fsl_edma_chan, vchan.chan);
 221 }
 222
 223 static struct fsl_edma_desc *to_fsl_edma_desc(struct virt_dma_desc *vd)
 224 {
 225         return container_of(vd, struct fsl_edma_desc, vdesc);
 226 }
 227
 228 static void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan)
 229 {
 230         void __iomem *addr = fsl_chan->edma->membase;
 231         u32 ch = fsl_chan->vchan.chan.chan_id;
 232
 233         edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), addr + EDMA_SEEI);
 234         edma_writeb(fsl_chan->edma, ch, addr + EDMA_SERQ);
 235 }
 236
 237 static void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan)
 238 {
 239         void __iomem *addr = fsl_chan->edma->membase;
 240         u32 ch = fsl_chan->vchan.chan.chan_id;
 241
 242         edma_writeb(fsl_chan->edma, ch, addr + EDMA_CERQ);
 243         edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), addr + EDMA_CEEI);
 244 }
 245
 246 static void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan,
 247                         unsigned int slot, bool enable)
 248 {
 249         u32 ch = fsl_chan->vchan.chan.chan_id;
 250         void __iomem *muxaddr;
 251         unsigned chans_per_mux, ch_off;
 252
 253         chans_per_mux = fsl_chan->edma->n_chans / DMAMUX_NR;
 254         ch_off = fsl_chan->vchan.chan.chan_id % chans_per_mux;
 255         muxaddr = fsl_chan->edma->muxbase[ch / chans_per_mux];
 256         slot = EDMAMUX_CHCFG_SOURCE(slot);
 257
 258         if (enable)
 259                 iowrite8(EDMAMUX_CHCFG_ENBL | slot, muxaddr + ch_off);
 260         else
 261                 iowrite8(EDMAMUX_CHCFG_DIS, muxaddr + ch_off);
 262 }
 263
 264 static unsigned int fsl_edma_get_tcd_attr(enum dma_slave_buswidth addr_width)
 265 {
 266         switch (addr_width) {
 267         case 1:
 268                 return EDMA_TCD_ATTR_SSIZE_8BIT | EDMA_TCD_ATTR_DSIZE_8BIT;
 269         case 2:
 270                 return EDMA_TCD_ATTR_SSIZE_16BIT | EDMA_TCD_ATTR_DSIZE_16BIT;
 271         case 4:
 272                 return EDMA_TCD_ATTR_SSIZE_32BIT | EDMA_TCD_ATTR_DSIZE_32BIT;
 273         case 8:
 274                 return EDMA_TCD_ATTR_SSIZE_64BIT | EDMA_TCD_ATTR_DSIZE_64BIT;
 275         default:
 276                 return EDMA_TCD_ATTR_SSIZE_32BIT | EDMA_TCD_ATTR_DSIZE_32BIT;
 277         }
 278 }
 279
 280 static void fsl_edma_free_desc(struct virt_dma_desc *vdesc)
 281 {
 282         struct fsl_edma_desc *fsl_desc;
 283         int i;
 284
 285         fsl_desc = to_fsl_edma_desc(vdesc);
 286         for (i = 0; i < fsl_desc->n_tcds; i++)
 287                 dma_pool_free(fsl_desc->echan->tcd_pool, fsl_desc->tcd[i].vtcd,
 288                               fsl_desc->tcd[i].ptcd);
 289         kfree(fsl_desc);
 290 }
 291
 292 static int fsl_edma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 293                 unsigned long arg)
 294 {
 295         struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
 296         struct dma_slave_config *cfg = (void *)arg;
 297         unsigned long flags;
 298         LIST_HEAD(head);
 299
 300         switch (cmd) {
 301         case DMA_TERMINATE_ALL:
 302                 spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
 303                 fsl_edma_disable_request(fsl_chan);
 304                 fsl_chan->edesc = NULL;
 305                 vchan_get_all_descriptors(&fsl_chan->vchan, &head);
 306                 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
 307                 vchan_dma_desc_free_list(&fsl_chan->vchan, &head);
 308                 return 0;
 309
 310         case DMA_SLAVE_CONFIG:
 311                 fsl_chan->fsc.dir = cfg->direction;
 312                 if (cfg->direction == DMA_DEV_TO_MEM) {
 313                         fsl_chan->fsc.dev_addr = cfg->src_addr;
 314                         fsl_chan->fsc.addr_width = cfg->src_addr_width;
 315                         fsl_chan->fsc.burst = cfg->src_maxburst;
 316                         fsl_chan->fsc.attr = fsl_edma_get_tcd_attr(cfg->src_addr_width);
 317                 } else if (cfg->direction == DMA_MEM_TO_DEV) {
 318                         fsl_chan->fsc.dev_addr = cfg->dst_addr;
 319                         fsl_chan->fsc.addr_width = cfg->dst_addr_width;
 320                         fsl_chan->fsc.burst = cfg->dst_maxburst;
 321                         fsl_chan->fsc.attr = fsl_edma_get_tcd_attr(cfg->dst_addr_width);
 322                 } else {
 323                         return -EINVAL;
 324                 }
 325                 return 0;
 326
 327         case DMA_PAUSE:
 328                 spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
 329                 if (fsl_chan->edesc) {
 330                         fsl_edma_disable_request(fsl_chan);
 331                         fsl_chan->status = DMA_PAUSED;
 332                 }
 333                 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
 334                 return 0;
 335
 336         case DMA_RESUME:
 337                 spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
 338                 if (fsl_chan->edesc) {
 339                         fsl_edma_enable_request(fsl_chan);
 340                         fsl_chan->status = DMA_IN_PROGRESS;
 341                 }
 342                 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
 343                 return 0;
 344
 345         default:
 346                 return -ENXIO;
 347         }
 348 }
 349
 350 static size_t fsl_edma_desc_residue(struct fsl_edma_chan *fsl_chan,
 351                 struct virt_dma_desc *vdesc, bool in_progress)
 352 {
 353         struct fsl_edma_desc *edesc = fsl_chan->edesc;
 354         void __iomem *addr = fsl_chan->edma->membase;
 355         u32 ch = fsl_chan->vchan.chan.chan_id;
 356         enum dma_transfer_direction dir = fsl_chan->fsc.dir;
 357         dma_addr_t cur_addr, dma_addr;
 358         size_t len, size;
 359         int i;
 360
 361         /* calculate the total size in this desc */
 362         for (len = i = 0; i < fsl_chan->edesc->n_tcds; i++)
 363                 len += le32_to_cpu(edesc->tcd[i].vtcd->nbytes)
 364                         * le16_to_cpu(edesc->tcd[i].vtcd->biter);
 365
 366         if (!in_progress)
 367                 return len;
 368
 369         if (dir == DMA_MEM_TO_DEV)
 370                 cur_addr = edma_readl(fsl_chan->edma, addr + EDMA_TCD_SADDR(ch));
 371         else
 372                 cur_addr = edma_readl(fsl_chan->edma, addr + EDMA_TCD_DADDR(ch));
 373
 374         /* figure out the finished and calculate the residue */
 375         for (i = 0; i < fsl_chan->edesc->n_tcds; i++) {
 376                 size = le32_to_cpu(edesc->tcd[i].vtcd->nbytes)
 377                         * le16_to_cpu(edesc->tcd[i].vtcd->biter);
 378                 if (dir == DMA_MEM_TO_DEV)
 379                         dma_addr = le32_to_cpu(edesc->tcd[i].vtcd->saddr);
 380                 else
 381                         dma_addr = le32_to_cpu(edesc->tcd[i].vtcd->daddr);
 382
 383                 len -= size;
 384                 if (cur_addr >= dma_addr && cur_addr < dma_addr + size) {
 385                         len += dma_addr + size - cur_addr;
 386                         break;
 387                 }
 388         }
 389
 390         return len;
 391 }
 392
 393 static enum dma_status fsl_edma_tx_status(struct dma_chan *chan,
 394                 dma_cookie_t cookie, struct dma_tx_state *txstate)
 395 {
 396         struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
 397         struct virt_dma_desc *vdesc;
 398         enum dma_status status;
 399         unsigned long flags;
 400
 401         status = dma_cookie_status(chan, cookie, txstate);
 402         if (status == DMA_COMPLETE)
 403                 return status;
 404
 405         if (!txstate)
 406                 return fsl_chan->status;
 407
 408         spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
 409         vdesc = vchan_find_desc(&fsl_chan->vchan, cookie);
 410         if (fsl_chan->edesc && cookie == fsl_chan->edesc->vdesc.tx.cookie)
 411                 txstate->residue = fsl_edma_desc_residue(fsl_chan, vdesc, true);
 412         else if (vdesc)
 413                 txstate->residue = fsl_edma_desc_residue(fsl_chan, vdesc, false);
 414         else
 415                 txstate->residue = 0;
 416
 417         spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
 418
 419         return fsl_chan->status;
 420 }
 421
 422 static void fsl_edma_set_tcd_regs(struct fsl_edma_chan *fsl_chan,
 423                                   struct fsl_edma_hw_tcd *tcd)
 424 {
 425         struct fsl_edma_engine *edma = fsl_chan->edma;
 426         void __iomem *addr = fsl_chan->edma->membase;
 427         u32 ch = fsl_chan->vchan.chan.chan_id;
 428
 429         /*
 430          * TCD parameters are stored in struct fsl_edma_hw_tcd in little
 431          * endian format. However, we need to load the TCD registers in
 432          * big- or little-endian obeying the eDMA engine model endian.
 433          */
 434         edma_writew(edma, 0, addr + EDMA_TCD_CSR(ch));
 435         edma_writel(edma, le32_to_cpu(tcd->saddr), addr + EDMA_TCD_SADDR(ch));
 436         edma_writel(edma, le32_to_cpu(tcd->daddr), addr + EDMA_TCD_DADDR(ch));
 437
 438         edma_writew(edma, le16_to_cpu(tcd->attr), addr + EDMA_TCD_ATTR(ch));
 439         edma_writew(edma, le16_to_cpu(tcd->soff), addr + EDMA_TCD_SOFF(ch));
 440
 441         edma_writel(edma, le32_to_cpu(tcd->nbytes), addr + EDMA_TCD_NBYTES(ch));
 442         edma_writel(edma, le32_to_cpu(tcd->slast), addr + EDMA_TCD_SLAST(ch));
 443
 444         edma_writew(edma, le16_to_cpu(tcd->citer), addr + EDMA_TCD_CITER(ch));
 445         edma_writew(edma, le16_to_cpu(tcd->biter), addr + EDMA_TCD_BITER(ch));
 446         edma_writew(edma, le16_to_cpu(tcd->doff), addr + EDMA_TCD_DOFF(ch));
 447
 448         edma_writel(edma, le32_to_cpu(tcd->dlast_sga), addr + EDMA_TCD_DLAST_SGA(ch));
 449
 450         edma_writew(edma, le16_to_cpu(tcd->csr), addr + EDMA_TCD_CSR(ch));
 451 }
 452
 453 static inline
 454 void fsl_edma_fill_tcd(struct fsl_edma_hw_tcd *tcd, u32 src, u32 dst,
 455                        u16 attr, u16 soff, u32 nbytes, u32 slast, u16 citer,
 456                        u16 biter, u16 doff, u32 dlast_sga, bool major_int,
 457                        bool disable_req, bool enable_sg)
 458 {
 459         u16 csr = 0;
 460
 461         /*
 462          * eDMA hardware SGs require the TCDs to be stored in little
 463          * endian format irrespective of the register endian model.
 464          * So we put the value in little endian in memory, waiting
 465          * for fsl_edma_set_tcd_regs doing the swap.
 466          */
 467         tcd->saddr = cpu_to_le32(src);
 468         tcd->daddr = cpu_to_le32(dst);
 469
 470         tcd->attr = cpu_to_le16(attr);
 471
 472         tcd->soff = cpu_to_le16(EDMA_TCD_SOFF_SOFF(soff));
 473
 474         tcd->nbytes = cpu_to_le32(EDMA_TCD_NBYTES_NBYTES(nbytes));
 475         tcd->slast = cpu_to_le32(EDMA_TCD_SLAST_SLAST(slast));
 476
 477         tcd->citer = cpu_to_le16(EDMA_TCD_CITER_CITER(citer));
 478         tcd->doff = cpu_to_le16(EDMA_TCD_DOFF_DOFF(doff));
 479
 480         tcd->dlast_sga = cpu_to_le32(EDMA_TCD_DLAST_SGA_DLAST_SGA(dlast_sga));
 481
 482         tcd->biter = cpu_to_le16(EDMA_TCD_BITER_BITER(biter));
 483         if (major_int)
 484                 csr |= EDMA_TCD_CSR_INT_MAJOR;
 485
 486         if (disable_req)
 487                 csr |= EDMA_TCD_CSR_D_REQ;
 488
 489         if (enable_sg)
 490                 csr |= EDMA_TCD_CSR_E_SG;
 491
 492         tcd->csr = cpu_to_le16(csr);
 493 }
 494
 495 static struct fsl_edma_desc *fsl_edma_alloc_desc(struct fsl_edma_chan *fsl_chan,
 496                 int sg_len)
 497 {
 498         struct fsl_edma_desc *fsl_desc;
 499         int i;
 500
 501         fsl_desc = kzalloc(sizeof(*fsl_desc) + sizeof(struct fsl_edma_sw_tcd) * sg_len,
 502                                 GFP_NOWAIT);
 503         if (!fsl_desc)
 504                 return NULL;
 505
 506         fsl_desc->echan = fsl_chan;
 507         fsl_desc->n_tcds = sg_len;
 508         for (i = 0; i < sg_len; i++) {
 509                 fsl_desc->tcd[i].vtcd = dma_pool_alloc(fsl_chan->tcd_pool,
 510                                         GFP_NOWAIT, &fsl_desc->tcd[i].ptcd);
 511                 if (!fsl_desc->tcd[i].vtcd)
 512                         goto err;
 513         }
 514         return fsl_desc;
 515
 516 err:
 517         while (--i >= 0)
 518                 dma_pool_free(fsl_chan->tcd_pool, fsl_desc->tcd[i].vtcd,
 519                                 fsl_desc->tcd[i].ptcd);
 520         kfree(fsl_desc);
 521         return NULL;
 522 }
 523
 524 static struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic(
 525                 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
 526                 size_t period_len, enum dma_transfer_direction direction,
 527                 unsigned long flags)
 528 {
 529         struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
 530         struct fsl_edma_desc *fsl_desc;
 531         dma_addr_t dma_buf_next;
 532         int sg_len, i;
 533         u32 src_addr, dst_addr, last_sg, nbytes;
 534         u16 soff, doff, iter;
 535
 536         if (!is_slave_direction(fsl_chan->fsc.dir))
 537                 return NULL;
 538
 539         sg_len = buf_len / period_len;
 540         fsl_desc = fsl_edma_alloc_desc(fsl_chan, sg_len);
 541         if (!fsl_desc)
 542                 return NULL;
 543         fsl_desc->iscyclic = true;
 544
 545         dma_buf_next = dma_addr;
 546         nbytes = fsl_chan->fsc.addr_width * fsl_chan->fsc.burst;
 547         iter = period_len / nbytes;
 548
 549         for (i = 0; i < sg_len; i++) {
 550                 if (dma_buf_next >= dma_addr + buf_len)
 551                         dma_buf_next = dma_addr;
 552
 553                 /* get next sg's physical address */
 554                 last_sg = fsl_desc->tcd[(i + 1) % sg_len].ptcd;
 555
 556                 if (fsl_chan->fsc.dir == DMA_MEM_TO_DEV) {
 557                         src_addr = dma_buf_next;
 558                         dst_addr = fsl_chan->fsc.dev_addr;
 559                         soff = fsl_chan->fsc.addr_width;
 560                         doff = 0;
 561                 } else {
 562                         src_addr = fsl_chan->fsc.dev_addr;
 563                         dst_addr = dma_buf_next;
 564                         soff = 0;
 565                         doff = fsl_chan->fsc.addr_width;
 566                 }
 567
 568                 fsl_edma_fill_tcd(fsl_desc->tcd[i].vtcd, src_addr, dst_addr,
 569                                   fsl_chan->fsc.attr, soff, nbytes, 0, iter,
 570                                   iter, doff, last_sg, true, false, true);
 571                 dma_buf_next += period_len;
 572         }
 573
 574         return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags);
 575 }
 576
 577 static struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg(
 578                 struct dma_chan *chan, struct scatterlist *sgl,
 579                 unsigned int sg_len, enum dma_transfer_direction direction,
 580                 unsigned long flags, void *context)
 581 {
 582         struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
 583         struct fsl_edma_desc *fsl_desc;
 584         struct scatterlist *sg;
 585         u32 src_addr, dst_addr, last_sg, nbytes;
 586         u16 soff, doff, iter;
 587         int i;
 588
 589         if (!is_slave_direction(fsl_chan->fsc.dir))
 590                 return NULL;
 591
 592         fsl_desc = fsl_edma_alloc_desc(fsl_chan, sg_len);
 593         if (!fsl_desc)
 594                 return NULL;
 595         fsl_desc->iscyclic = false;
 596
 597         nbytes = fsl_chan->fsc.addr_width * fsl_chan->fsc.burst;
 598         for_each_sg(sgl, sg, sg_len, i) {
 599                 /* get next sg's physical address */
 600                 last_sg = fsl_desc->tcd[(i + 1) % sg_len].ptcd;
 601
 602                 if (fsl_chan->fsc.dir == DMA_MEM_TO_DEV) {
 603                         src_addr = sg_dma_address(sg);
 604                         dst_addr = fsl_chan->fsc.dev_addr;
 605                         soff = fsl_chan->fsc.addr_width;
 606                         doff = 0;
 607                 } else {
 608                         src_addr = fsl_chan->fsc.dev_addr;
 609                         dst_addr = sg_dma_address(sg);
 610                         soff = 0;
 611                         doff = fsl_chan->fsc.addr_width;
 612                 }
 613
 614                 iter = sg_dma_len(sg) / nbytes;
 615                 if (i < sg_len - 1) {
 616                         last_sg = fsl_desc->tcd[(i + 1)].ptcd;
 617                         fsl_edma_fill_tcd(fsl_desc->tcd[i].vtcd, src_addr,
 618                                           dst_addr, fsl_chan->fsc.attr, soff,
 619                                           nbytes, 0, iter, iter, doff, last_sg,
 620                                           false, false, true);
 621                 } else {
 622                         last_sg = 0;
 623                         fsl_edma_fill_tcd(fsl_desc->tcd[i].vtcd, src_addr,
 624                                           dst_addr, fsl_chan->fsc.attr, soff,
 625                                           nbytes, 0, iter, iter, doff, last_sg,
 626                                           true, true, false);
 627                 }
 628         }
 629
 630         return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags);
 631 }
 632
 633 static void fsl_edma_xfer_desc(struct fsl_edma_chan *fsl_chan)
 634 {
 635         struct virt_dma_desc *vdesc;
 636
 637         vdesc = vchan_next_desc(&fsl_chan->vchan);
 638         if (!vdesc)
 639                 return;
 640         fsl_chan->edesc = to_fsl_edma_desc(vdesc);
 641         fsl_edma_set_tcd_regs(fsl_chan, fsl_chan->edesc->tcd[0].vtcd);
 642         fsl_edma_enable_request(fsl_chan);
 643         fsl_chan->status = DMA_IN_PROGRESS;
 644 }
 645
 646 static irqreturn_t fsl_edma_tx_handler(int irq, void *dev_id)
 647 {
 648         struct fsl_edma_engine *fsl_edma = dev_id;
 649         unsigned int intr, ch;
 650         void __iomem *base_addr;
 651         struct fsl_edma_chan *fsl_chan;
 652
 653         base_addr = fsl_edma->membase;
 654
 655         intr = edma_readl(fsl_edma, base_addr + EDMA_INTR);
 656         if (!intr)
 657                 return IRQ_NONE;
 658
 659         for (ch = 0; ch < fsl_edma->n_chans; ch++) {
 660                 if (intr & (0x1 << ch)) {
 661                         edma_writeb(fsl_edma, EDMA_CINT_CINT(ch),
 662                                 base_addr + EDMA_CINT);
 663
 664                         fsl_chan = &fsl_edma->chans[ch];
 665
 666                         spin_lock(&fsl_chan->vchan.lock);
 667                         if (!fsl_chan->edesc->iscyclic) {
 668                                 list_del(&fsl_chan->edesc->vdesc.node);
 669                                 vchan_cookie_complete(&fsl_chan->edesc->vdesc);
 670                                 fsl_chan->edesc = NULL;
 671                                 fsl_chan->status = DMA_COMPLETE;
 672                         } else {
 673                                 vchan_cyclic_callback(&fsl_chan->edesc->vdesc);
 674                         }
 675
 676                         if (!fsl_chan->edesc)
 677                                 fsl_edma_xfer_desc(fsl_chan);
 678
 679                         spin_unlock(&fsl_chan->vchan.lock);
 680                 }
 681         }
 682         return IRQ_HANDLED;
 683 }
 684
 685 static irqreturn_t fsl_edma_err_handler(int irq, void *dev_id)
 686 {
 687         struct fsl_edma_engine *fsl_edma = dev_id;
 688         unsigned int err, ch;
 689
 690         err = edma_readl(fsl_edma, fsl_edma->membase + EDMA_ERR);
 691         if (!err)
 692                 return IRQ_NONE;
 693
 694         for (ch = 0; ch < fsl_edma->n_chans; ch++) {
 695                 if (err & (0x1 << ch)) {
 696                         fsl_edma_disable_request(&fsl_edma->chans[ch]);
 697                         edma_writeb(fsl_edma, EDMA_CERR_CERR(ch),
 698                                 fsl_edma->membase + EDMA_CERR);
 699                         fsl_edma->chans[ch].status = DMA_ERROR;
 700                 }
 701         }
 702         return IRQ_HANDLED;
 703 }
 704
 705 static irqreturn_t fsl_edma_irq_handler(int irq, void *dev_id)
 706 {
 707         if (fsl_edma_tx_handler(irq, dev_id) == IRQ_HANDLED)
 708                 return IRQ_HANDLED;
 709
 710         return fsl_edma_err_handler(irq, dev_id);
 711 }
 712
 713 static void fsl_edma_issue_pending(struct dma_chan *chan)
 714 {
 715         struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
 716         unsigned long flags;
 717
 718         spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
 719
 720         if (vchan_issue_pending(&fsl_chan->vchan) && !fsl_chan->edesc)
 721                 fsl_edma_xfer_desc(fsl_chan);
 722
 723         spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
 724 }
 725
 726 static struct dma_chan *fsl_edma_xlate(struct of_phandle_args *dma_spec,
 727                 struct of_dma *ofdma)
 728 {
 729         struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data;
 730         struct dma_chan *chan, *_chan;
 731         unsigned long chans_per_mux = fsl_edma->n_chans / DMAMUX_NR;
 732
 733         if (dma_spec->args_count != 2)
 734                 return NULL;
 735
 736         mutex_lock(&fsl_edma->fsl_edma_mutex);
 737         list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, device_node) {
 738                 if (chan->client_count)
 739                         continue;
 740                 if ((chan->chan_id / chans_per_mux) == dma_spec->args[0]) {
 741                         chan = dma_get_slave_channel(chan);
 742                         if (chan) {
 743                                 chan->device->privatecnt++;
 744                                 fsl_edma_chan_mux(to_fsl_edma_chan(chan),
 745                                         dma_spec->args[1], true);
 746                                 mutex_unlock(&fsl_edma->fsl_edma_mutex);
 747                                 return chan;
 748                         }
 749                 }
 750         }
 751         mutex_unlock(&fsl_edma->fsl_edma_mutex);
 752         return NULL;
 753 }
 754
 755 static int fsl_edma_alloc_chan_resources(struct dma_chan *chan)
 756 {
 757         struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
 758
 759         fsl_chan->tcd_pool = dma_pool_create("tcd_pool", chan->device->dev,
 760                                 sizeof(struct fsl_edma_hw_tcd),
 761                                 32, 0);
 762         return 0;
 763 }
 764
 765 static void fsl_edma_free_chan_resources(struct dma_chan *chan)
 766 {
 767         struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
 768         unsigned long flags;
 769         LIST_HEAD(head);
 770
 771         spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
 772         fsl_edma_disable_request(fsl_chan);
 773         fsl_edma_chan_mux(fsl_chan, 0, false);
 774         fsl_chan->edesc = NULL;
 775         vchan_get_all_descriptors(&fsl_chan->vchan, &head);
 776         spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
 777
 778         vchan_dma_desc_free_list(&fsl_chan->vchan, &head);
 779         dma_pool_destroy(fsl_chan->tcd_pool);
 780         fsl_chan->tcd_pool = NULL;
 781 }
 782
 783 static int fsl_dma_device_slave_caps(struct dma_chan *dchan,
 784                 struct dma_slave_caps *caps)
 785 {
 786         caps->src_addr_widths = FSL_EDMA_BUSWIDTHS;
 787         caps->dstn_addr_widths = FSL_EDMA_BUSWIDTHS;
 788         caps->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
 789         caps->cmd_pause = true;
 790         caps->cmd_terminate = true;
 791
 792         return 0;
 793 }
 794
 795 static int
 796 fsl_edma_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma)
 797 {
 798         int ret;
 799
 800         fsl_edma->txirq = platform_get_irq_byname(pdev, "edma-tx");
 801         if (fsl_edma->txirq < 0) {
 802                 dev_err(&pdev->dev, "Can't get edma-tx irq.\n");
 803                 return fsl_edma->txirq;
 804         }
 805
 806         fsl_edma->errirq = platform_get_irq_byname(pdev, "edma-err");
 807         if (fsl_edma->errirq < 0) {
 808                 dev_err(&pdev->dev, "Can't get edma-err irq.\n");
 809                 return fsl_edma->errirq;
 810         }
 811
 812         if (fsl_edma->txirq == fsl_edma->errirq) {
 813                 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq,
 814                                 fsl_edma_irq_handler, 0, "eDMA", fsl_edma);
 815                 if (ret) {
 816                         dev_err(&pdev->dev, "Can't register eDMA IRQ.\n");
 817                          return  ret;
 818                 }
 819         } else {
 820                 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq,
 821                                 fsl_edma_tx_handler, 0, "eDMA tx", fsl_edma);
 822                 if (ret) {
 823                         dev_err(&pdev->dev, "Can't register eDMA tx IRQ.\n");
 824                         return  ret;
 825                 }
 826
 827                 ret = devm_request_irq(&pdev->dev, fsl_edma->errirq,
 828                                 fsl_edma_err_handler, 0, "eDMA err", fsl_edma);
 829                 if (ret) {
 830                         dev_err(&pdev->dev, "Can't register eDMA err IRQ.\n");
 831                         return  ret;
 832                 }
 833         }
 834
 835         return 0;
 836 }
 837
 838 static int fsl_edma_probe(struct platform_device *pdev)
 839 {
 840         struct device_node *np = pdev->dev.of_node;
 841         struct fsl_edma_engine *fsl_edma;
 842         struct fsl_edma_chan *fsl_chan;
 843         struct resource *res;
 844         int len, chans;
 845         int ret, i;
 846
 847         ret = of_property_read_u32(np, "dma-channels", &chans);
 848         if (ret) {
 849                 dev_err(&pdev->dev, "Can't get dma-channels.\n");
 850                 return ret;
 851         }
 852
 853         len = sizeof(*fsl_edma) + sizeof(*fsl_chan) * chans;
 854         fsl_edma = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
 855         if (!fsl_edma)
 856                 return -ENOMEM;
 857
 858         fsl_edma->n_chans = chans;
 859         mutex_init(&fsl_edma->fsl_edma_mutex);
 860
 861         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 862         fsl_edma->membase = devm_ioremap_resource(&pdev->dev, res);
 863         if (IS_ERR(fsl_edma->membase))
 864                 return PTR_ERR(fsl_edma->membase);
 865
 866         for (i = 0; i < DMAMUX_NR; i++) {
 867                 char clkname[32];
 868
 869                 res = platform_get_resource(pdev, IORESOURCE_MEM, 1 + i);
 870                 fsl_edma->muxbase[i] = devm_ioremap_resource(&pdev->dev, res);
 871                 if (IS_ERR(fsl_edma->muxbase[i]))
 872                         return PTR_ERR(fsl_edma->muxbase[i]);
 873
 874                 sprintf(clkname, "dmamux%d", i);
 875                 fsl_edma->muxclk[i] = devm_clk_get(&pdev->dev, clkname);
 876                 if (IS_ERR(fsl_edma->muxclk[i])) {
 877                         dev_err(&pdev->dev, "Missing DMAMUX block clock.\n");
 878                         return PTR_ERR(fsl_edma->muxclk[i]);
 879                 }
 880
 881                 ret = clk_prepare_enable(fsl_edma->muxclk[i]);
 882                 if (ret) {
 883                         dev_err(&pdev->dev, "DMAMUX clk block failed.\n");
 884                         return ret;
 885                 }
 886
 887         }
 888
 889         ret = fsl_edma_irq_init(pdev, fsl_edma);
 890         if (ret)
 891                 return ret;
 892
 893         fsl_edma->big_endian = of_property_read_bool(np, "big-endian");
 894
 895         INIT_LIST_HEAD(&fsl_edma->dma_dev.channels);
 896         for (i = 0; i < fsl_edma->n_chans; i++) {
 897                 struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i];
 898
 899                 fsl_chan->edma = fsl_edma;
 900
 901                 fsl_chan->vchan.desc_free = fsl_edma_free_desc;
 902                 vchan_init(&fsl_chan->vchan, &fsl_edma->dma_dev);
 903
 904                 edma_writew(fsl_edma, 0x0, fsl_edma->membase + EDMA_TCD_CSR(i));
 905                 fsl_edma_chan_mux(fsl_chan, 0, false);
 906         }
 907
 908         dma_cap_set(DMA_PRIVATE, fsl_edma->dma_dev.cap_mask);
 909         dma_cap_set(DMA_SLAVE, fsl_edma->dma_dev.cap_mask);
 910         dma_cap_set(DMA_CYCLIC, fsl_edma->dma_dev.cap_mask);
 911
 912         fsl_edma->dma_dev.dev = &pdev->dev;
 913         fsl_edma->dma_dev.device_alloc_chan_resources
 914                 = fsl_edma_alloc_chan_resources;
 915         fsl_edma->dma_dev.device_free_chan_resources
 916                 = fsl_edma_free_chan_resources;
 917         fsl_edma->dma_dev.device_tx_status = fsl_edma_tx_status;
 918         fsl_edma->dma_dev.device_prep_slave_sg = fsl_edma_prep_slave_sg;
 919         fsl_edma->dma_dev.device_prep_dma_cyclic = fsl_edma_prep_dma_cyclic;
 920         fsl_edma->dma_dev.device_control = fsl_edma_control;
 921         fsl_edma->dma_dev.device_issue_pending = fsl_edma_issue_pending;
 922         fsl_edma->dma_dev.device_slave_caps = fsl_dma_device_slave_caps;
 923
 924         platform_set_drvdata(pdev, fsl_edma);
 925
 926         ret = dma_async_device_register(&fsl_edma->dma_dev);
 927         if (ret) {
 928                 dev_err(&pdev->dev, "Can't register Freescale eDMA engine.\n");
 929                 return ret;
 930         }
 931
 932         ret = of_dma_controller_register(np, fsl_edma_xlate, fsl_edma);
 933         if (ret) {
 934                 dev_err(&pdev->dev, "Can't register Freescale eDMA of_dma.\n");
 935                 dma_async_device_unregister(&fsl_edma->dma_dev);
 936                 return ret;
 937         }
 938
 939         /* enable round robin arbitration */
 940         edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, fsl_edma->membase + EDMA_CR);
 941
 942         return 0;
 943 }
 944
 945 static int fsl_edma_remove(struct platform_device *pdev)
 946 {
 947         struct device_node *np = pdev->dev.of_node;
 948         struct fsl_edma_engine *fsl_edma = platform_get_drvdata(pdev);
 949         int i;
 950
 951         of_dma_controller_free(np);
 952         dma_async_device_unregister(&fsl_edma->dma_dev);
 953
 954         for (i = 0; i < DMAMUX_NR; i++)
 955                 clk_disable_unprepare(fsl_edma->muxclk[i]);
 956
 957         return 0;
 958 }
 959
 960 static const struct of_device_id fsl_edma_dt_ids[] = {
 961         { .compatible = "fsl,vf610-edma", },
 962         { /* sentinel */ }
 963 };
 964 MODULE_DEVICE_TABLE(of, fsl_edma_dt_ids);
 965
 966 static struct platform_driver fsl_edma_driver = {
 967         .driver         = {
 968                 .name   = "fsl-edma",
 969                 .of_match_table = fsl_edma_dt_ids,
 970         },
 971         .probe          = fsl_edma_probe,
 972         .remove         = fsl_edma_remove,
 973 };
 974
 975 static int __init fsl_edma_init(void)
 976 {
 977         return platform_driver_register(&fsl_edma_driver);
 978 }
 979 subsys_initcall(fsl_edma_init);
 980
 981 static void __exit fsl_edma_exit(void)
 982 {
 983         platform_driver_unregister(&fsl_edma_driver);
 984 }
 985 module_exit(fsl_edma_exit);
 986
 987 MODULE_ALIAS("platform:fsl-edma");
 988 MODULE_DESCRIPTION("Freescale eDMA engine driver");
 989 MODULE_LICENSE("GPL v2");