drivers/dma/imx-sdma.c

   1 /*
   2  * drivers/dma/imx-sdma.c
   3  *
   4  * This file contains a driver for the Freescale Smart DMA engine
   5  *
   6  * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
   7  *
   8  * Based on code from Freescale:
   9  *
  10  * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
  11  *
  12  * The code contained herein is licensed under the GNU General Public
  13  * License. You may obtain a copy of the GNU General Public License
  14  * Version 2 or later at the following locations:
  15  *
  16  * http://www.opensource.org/licenses/gpl-license.html
  17  * http://www.gnu.org/copyleft/gpl.html
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/module.h>
  22 #include <linux/types.h>
  23 #include <linux/bitops.h>
  24 #include <linux/mm.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/clk.h>
  27 #include <linux/delay.h>
  28 #include <linux/sched.h>
  29 #include <linux/semaphore.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/device.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/firmware.h>
  34 #include <linux/slab.h>
  35 #include <linux/platform_device.h>
  36 #include <linux/dmaengine.h>
  37 #include <linux/of.h>
  38 #include <linux/of_device.h>
  39 #include <linux/of_dma.h>
  40
  41 #include <asm/irq.h>
  42 #include <linux/platform_data/dma-imx-sdma.h>
  43 #include <linux/platform_data/dma-imx.h>
  44
  45 #include "dmaengine.h"
  46
  47 /* SDMA registers */
  48 #define SDMA_H_C0PTR            0x000
  49 #define SDMA_H_INTR             0x004
  50 #define SDMA_H_STATSTOP         0x008
  51 #define SDMA_H_START            0x00c
  52 #define SDMA_H_EVTOVR           0x010
  53 #define SDMA_H_DSPOVR           0x014
  54 #define SDMA_H_HOSTOVR          0x018
  55 #define SDMA_H_EVTPEND          0x01c
  56 #define SDMA_H_DSPENBL          0x020
  57 #define SDMA_H_RESET            0x024
  58 #define SDMA_H_EVTERR           0x028
  59 #define SDMA_H_INTRMSK          0x02c
  60 #define SDMA_H_PSW              0x030
  61 #define SDMA_H_EVTERRDBG        0x034
  62 #define SDMA_H_CONFIG           0x038
  63 #define SDMA_ONCE_ENB           0x040
  64 #define SDMA_ONCE_DATA          0x044
  65 #define SDMA_ONCE_INSTR         0x048
  66 #define SDMA_ONCE_STAT          0x04c
  67 #define SDMA_ONCE_CMD           0x050
  68 #define SDMA_EVT_MIRROR         0x054
  69 #define SDMA_ILLINSTADDR        0x058
  70 #define SDMA_CHN0ADDR           0x05c
  71 #define SDMA_ONCE_RTB           0x060
  72 #define SDMA_XTRIG_CONF1        0x070
  73 #define SDMA_XTRIG_CONF2        0x074
  74 #define SDMA_CHNENBL0_IMX35     0x200
  75 #define SDMA_CHNENBL0_IMX31     0x080
  76 #define SDMA_CHNPRI_0           0x100
  77
  78 /*
  79  * Buffer descriptor status values.
  80  */
  81 #define BD_DONE  0x01
  82 #define BD_WRAP  0x02
  83 #define BD_CONT  0x04
  84 #define BD_INTR  0x08
  85 #define BD_RROR  0x10
  86 #define BD_LAST  0x20
  87 #define BD_EXTD  0x80
  88
  89 /*
  90  * Data Node descriptor status values.
  91  */
  92 #define DND_END_OF_FRAME  0x80
  93 #define DND_END_OF_XFER   0x40
  94 #define DND_DONE          0x20
  95 #define DND_UNUSED        0x01
  96
  97 /*
  98  * IPCV2 descriptor status values.
  99  */
 100 #define BD_IPCV2_END_OF_FRAME  0x40
 101
 102 #define IPCV2_MAX_NODES        50
 103 /*
 104  * Error bit set in the CCB status field by the SDMA,
 105  * in setbd routine, in case of a transfer error
 106  */
 107 #define DATA_ERROR  0x10000000
 108
 109 /*
 110  * Buffer descriptor commands.
 111  */
 112 #define C0_ADDR             0x01
 113 #define C0_LOAD             0x02
 114 #define C0_DUMP             0x03
 115 #define C0_SETCTX           0x07
 116 #define C0_GETCTX           0x03
 117 #define C0_SETDM            0x01
 118 #define C0_SETPM            0x04
 119 #define C0_GETDM            0x02
 120 #define C0_GETPM            0x08
 121 /*
 122  * Change endianness indicator in the BD command field
 123  */
 124 #define CHANGE_ENDIANNESS   0x80
 125
 126 /*
 127  * Mode/Count of data node descriptors - IPCv2
 128  */
 129 struct sdma_mode_count {
 130         u32 count   : 16; /* size of the buffer pointed by this BD */
 131         u32 status  :  8; /* E,R,I,C,W,D status bits stored here */
 132         u32 command :  8; /* command mostlky used for channel 0 */
 133 };
 134
 135 /*
 136  * Buffer descriptor
 137  */
 138 struct sdma_buffer_descriptor {
 139         struct sdma_mode_count  mode;
 140         u32 buffer_addr;        /* address of the buffer described */
 141         u32 ext_buffer_addr;    /* extended buffer address */
 142 } __attribute__ ((packed));
 143
 144 /**
 145  * struct sdma_channel_control - Channel control Block
 146  *
 147  * @current_bd_ptr      current buffer descriptor processed
 148  * @base_bd_ptr         first element of buffer descriptor array
 149  * @unused              padding. The SDMA engine expects an array of 128 byte
 150  *                      control blocks
 151  */
 152 struct sdma_channel_control {
 153         u32 current_bd_ptr;
 154         u32 base_bd_ptr;
 155         u32 unused[2];
 156 } __attribute__ ((packed));
 157
 158 /**
 159  * struct sdma_state_registers - SDMA context for a channel
 160  *
 161  * @pc:         program counter
 162  * @t:          test bit: status of arithmetic & test instruction
 163  * @rpc:        return program counter
 164  * @sf:         source fault while loading data
 165  * @spc:        loop start program counter
 166  * @df:         destination fault while storing data
 167  * @epc:        loop end program counter
 168  * @lm:         loop mode
 169  */
 170 struct sdma_state_registers {
 171         u32 pc     :14;
 172         u32 unused1: 1;
 173         u32 t      : 1;
 174         u32 rpc    :14;
 175         u32 unused0: 1;
 176         u32 sf     : 1;
 177         u32 spc    :14;
 178         u32 unused2: 1;
 179         u32 df     : 1;
 180         u32 epc    :14;
 181         u32 lm     : 2;
 182 } __attribute__ ((packed));
 183
 184 /**
 185  * struct sdma_context_data - sdma context specific to a channel
 186  *
 187  * @channel_state:      channel state bits
 188  * @gReg:               general registers
 189  * @mda:                burst dma destination address register
 190  * @msa:                burst dma source address register
 191  * @ms:                 burst dma status register
 192  * @md:                 burst dma data register
 193  * @pda:                peripheral dma destination address register
 194  * @psa:                peripheral dma source address register
 195  * @ps:                 peripheral dma status register
 196  * @pd:                 peripheral dma data register
 197  * @ca:                 CRC polynomial register
 198  * @cs:                 CRC accumulator register
 199  * @dda:                dedicated core destination address register
 200  * @dsa:                dedicated core source address register
 201  * @ds:                 dedicated core status register
 202  * @dd:                 dedicated core data register
 203  */
 204 struct sdma_context_data {
 205         struct sdma_state_registers  channel_state;
 206         u32  gReg[8];
 207         u32  mda;
 208         u32  msa;
 209         u32  ms;
 210         u32  md;
 211         u32  pda;
 212         u32  psa;
 213         u32  ps;
 214         u32  pd;
 215         u32  ca;
 216         u32  cs;
 217         u32  dda;
 218         u32  dsa;
 219         u32  ds;
 220         u32  dd;
 221         u32  scratch0;
 222         u32  scratch1;
 223         u32  scratch2;
 224         u32  scratch3;
 225         u32  scratch4;
 226         u32  scratch5;
 227         u32  scratch6;
 228         u32  scratch7;
 229 } __attribute__ ((packed));
 230
 231 #define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor))
 232
 233 struct sdma_engine;
 234
 235 /**
 236  * struct sdma_channel - housekeeping for a SDMA channel
 237  *
 238  * @sdma                pointer to the SDMA engine for this channel
 239  * @channel             the channel number, matches dmaengine chan_id + 1
 240  * @direction           transfer type. Needed for setting SDMA script
 241  * @peripheral_type     Peripheral type. Needed for setting SDMA script
 242  * @event_id0           aka dma request line
 243  * @event_id1           for channels that use 2 events
 244  * @word_size           peripheral access size
 245  * @buf_tail            ID of the buffer that was processed
 246  * @num_bd              max NUM_BD. number of descriptors currently handling
 247  */
 248 struct sdma_channel {
 249         struct sdma_engine              *sdma;
 250         unsigned int                    channel;
 251         enum dma_transfer_direction             direction;
 252         enum sdma_peripheral_type       peripheral_type;
 253         unsigned int                    event_id0;
 254         unsigned int                    event_id1;
 255         enum dma_slave_buswidth         word_size;
 256         unsigned int                    buf_tail;
 257         unsigned int                    num_bd;
 258         struct sdma_buffer_descriptor   *bd;
 259         dma_addr_t                      bd_phys;
 260         unsigned int                    pc_from_device, pc_to_device;
 261         unsigned long                   flags;
 262         dma_addr_t                      per_address;
 263         unsigned long                   event_mask[2];
 264         unsigned long                   watermark_level;
 265         u32                             shp_addr, per_addr;
 266         struct dma_chan                 chan;
 267         spinlock_t                      lock;
 268         struct dma_async_tx_descriptor  desc;
 269         enum dma_status                 status;
 270         unsigned int                    chn_count;
 271         unsigned int                    chn_real_count;
 272         struct tasklet_struct           tasklet;
 273 };
 274
 275 #define IMX_DMA_SG_LOOP         BIT(0)
 276
 277 #define MAX_DMA_CHANNELS 32
 278 #define MXC_SDMA_DEFAULT_PRIORITY 1
 279 #define MXC_SDMA_MIN_PRIORITY 1
 280 #define MXC_SDMA_MAX_PRIORITY 7
 281
 282 #define SDMA_FIRMWARE_MAGIC 0x414d4453
 283
 284 /**
 285  * struct sdma_firmware_header - Layout of the firmware image
 286  *
 287  * @magic               "SDMA"
 288  * @version_major       increased whenever layout of struct sdma_script_start_addrs
 289  *                      changes.
 290  * @version_minor       firmware minor version (for binary compatible changes)
 291  * @script_addrs_start  offset of struct sdma_script_start_addrs in this image
 292  * @num_script_addrs    Number of script addresses in this image
 293  * @ram_code_start      offset of SDMA ram image in this firmware image
 294  * @ram_code_size       size of SDMA ram image
 295  * @script_addrs        Stores the start address of the SDMA scripts
 296  *                      (in SDMA memory space)
 297  */
 298 struct sdma_firmware_header {
 299         u32     magic;
 300         u32     version_major;
 301         u32     version_minor;
 302         u32     script_addrs_start;
 303         u32     num_script_addrs;
 304         u32     ram_code_start;
 305         u32     ram_code_size;
 306 };
 307
 308 struct sdma_driver_data {
 309         int chnenbl0;
 310         int num_events;
 311         struct sdma_script_start_addrs  *script_addrs;
 312 };
 313
 314 struct sdma_engine {
 315         struct device                   *dev;
 316         struct device_dma_parameters    dma_parms;
 317         struct sdma_channel             channel[MAX_DMA_CHANNELS];
 318         struct sdma_channel_control     *channel_control;
 319         void __iomem                    *regs;
 320         struct sdma_context_data        *context;
 321         dma_addr_t                      context_phys;
 322         struct dma_device               dma_device;
 323         struct clk                      *clk_ipg;
 324         struct clk                      *clk_ahb;
 325         spinlock_t                      channel_0_lock;
 326         u32                             script_number;
 327         struct sdma_script_start_addrs  *script_addrs;
 328         const struct sdma_driver_data   *drvdata;
 329 };
 330
 331 static struct sdma_driver_data sdma_imx31 = {
 332         .chnenbl0 = SDMA_CHNENBL0_IMX31,
 333         .num_events = 32,
 334 };
 335
 336 static struct sdma_script_start_addrs sdma_script_imx25 = {
 337         .ap_2_ap_addr = 729,
 338         .uart_2_mcu_addr = 904,
 339         .per_2_app_addr = 1255,
 340         .mcu_2_app_addr = 834,
 341         .uartsh_2_mcu_addr = 1120,
 342         .per_2_shp_addr = 1329,
 343         .mcu_2_shp_addr = 1048,
 344         .ata_2_mcu_addr = 1560,
 345         .mcu_2_ata_addr = 1479,
 346         .app_2_per_addr = 1189,
 347         .app_2_mcu_addr = 770,
 348         .shp_2_per_addr = 1407,
 349         .shp_2_mcu_addr = 979,
 350 };
 351
 352 static struct sdma_driver_data sdma_imx25 = {
 353         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 354         .num_events = 48,
 355         .script_addrs = &sdma_script_imx25,
 356 };
 357
 358 static struct sdma_driver_data sdma_imx35 = {
 359         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 360         .num_events = 48,
 361 };
 362
 363 static struct sdma_script_start_addrs sdma_script_imx51 = {
 364         .ap_2_ap_addr = 642,
 365         .uart_2_mcu_addr = 817,
 366         .mcu_2_app_addr = 747,
 367         .mcu_2_shp_addr = 961,
 368         .ata_2_mcu_addr = 1473,
 369         .mcu_2_ata_addr = 1392,
 370         .app_2_per_addr = 1033,
 371         .app_2_mcu_addr = 683,
 372         .shp_2_per_addr = 1251,
 373         .shp_2_mcu_addr = 892,
 374 };
 375
 376 static struct sdma_driver_data sdma_imx51 = {
 377         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 378         .num_events = 48,
 379         .script_addrs = &sdma_script_imx51,
 380 };
 381
 382 static struct sdma_script_start_addrs sdma_script_imx53 = {
 383         .ap_2_ap_addr = 642,
 384         .app_2_mcu_addr = 683,
 385         .mcu_2_app_addr = 747,
 386         .uart_2_mcu_addr = 817,
 387         .shp_2_mcu_addr = 891,
 388         .mcu_2_shp_addr = 960,
 389         .uartsh_2_mcu_addr = 1032,
 390         .spdif_2_mcu_addr = 1100,
 391         .mcu_2_spdif_addr = 1134,
 392         .firi_2_mcu_addr = 1193,
 393         .mcu_2_firi_addr = 1290,
 394 };
 395
 396 static struct sdma_driver_data sdma_imx53 = {
 397         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 398         .num_events = 48,
 399         .script_addrs = &sdma_script_imx53,
 400 };
 401
 402 static struct sdma_script_start_addrs sdma_script_imx6q = {
 403         .ap_2_ap_addr = 642,
 404         .uart_2_mcu_addr = 817,
 405         .mcu_2_app_addr = 747,
 406         .per_2_per_addr = 6331,
 407         .uartsh_2_mcu_addr = 1032,
 408         .mcu_2_shp_addr = 960,
 409         .app_2_mcu_addr = 683,
 410         .shp_2_mcu_addr = 891,
 411         .spdif_2_mcu_addr = 1100,
 412         .mcu_2_spdif_addr = 1134,
 413 };
 414
 415 static struct sdma_driver_data sdma_imx6q = {
 416         .chnenbl0 = SDMA_CHNENBL0_IMX35,
 417         .num_events = 48,
 418         .script_addrs = &sdma_script_imx6q,
 419 };
 420
 421 static struct platform_device_id sdma_devtypes[] = {
 422         {
 423                 .name = "imx25-sdma",
 424                 .driver_data = (unsigned long)&sdma_imx25,
 425         }, {
 426                 .name = "imx31-sdma",
 427                 .driver_data = (unsigned long)&sdma_imx31,
 428         }, {
 429                 .name = "imx35-sdma",
 430                 .driver_data = (unsigned long)&sdma_imx35,
 431         }, {
 432                 .name = "imx51-sdma",
 433                 .driver_data = (unsigned long)&sdma_imx51,
 434         }, {
 435                 .name = "imx53-sdma",
 436                 .driver_data = (unsigned long)&sdma_imx53,
 437         }, {
 438                 .name = "imx6q-sdma",
 439                 .driver_data = (unsigned long)&sdma_imx6q,
 440         }, {
 441                 /* sentinel */
 442         }
 443 };
 444 MODULE_DEVICE_TABLE(platform, sdma_devtypes);
 445
 446 static const struct of_device_id sdma_dt_ids[] = {
 447         { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, },
 448         { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, },
 449         { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, },
 450         { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, },
 451         { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
 452         { /* sentinel */ }
 453 };
 454 MODULE_DEVICE_TABLE(of, sdma_dt_ids);
 455
 456 #define SDMA_H_CONFIG_DSPDMA    BIT(12) /* indicates if the DSPDMA is used */
 457 #define SDMA_H_CONFIG_RTD_PINS  BIT(11) /* indicates if Real-Time Debug pins are enabled */
 458 #define SDMA_H_CONFIG_ACR       BIT(4)  /* indicates if AHB freq /core freq = 2 or 1 */
 459 #define SDMA_H_CONFIG_CSM       (3)       /* indicates which context switch mode is selected*/
 460
 461 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
 462 {
 463         u32 chnenbl0 = sdma->drvdata->chnenbl0;
 464         return chnenbl0 + event * 4;
 465 }
 466
 467 static int sdma_config_ownership(struct sdma_channel *sdmac,
 468                 bool event_override, bool mcu_override, bool dsp_override)
 469 {
 470         struct sdma_engine *sdma = sdmac->sdma;
 471         int channel = sdmac->channel;
 472         unsigned long evt, mcu, dsp;
 473
 474         if (event_override && mcu_override && dsp_override)
 475                 return -EINVAL;
 476
 477         evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR);
 478         mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR);
 479         dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR);
 480
 481         if (dsp_override)
 482                 __clear_bit(channel, &dsp);
 483         else
 484                 __set_bit(channel, &dsp);
 485
 486         if (event_override)
 487                 __clear_bit(channel, &evt);
 488         else
 489                 __set_bit(channel, &evt);
 490
 491         if (mcu_override)
 492                 __clear_bit(channel, &mcu);
 493         else
 494                 __set_bit(channel, &mcu);
 495
 496         writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR);
 497         writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR);
 498         writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR);
 499
 500         return 0;
 501 }
 502
 503 static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
 504 {
 505         writel(BIT(channel), sdma->regs + SDMA_H_START);
 506 }
 507
 508 /*
 509  * sdma_run_channel0 - run a channel and wait till it's done
 510  */
 511 static int sdma_run_channel0(struct sdma_engine *sdma)
 512 {
 513         int ret;
 514         unsigned long timeout = 500;
 515
 516         sdma_enable_channel(sdma, 0);
 517
 518         while (!(ret = readl_relaxed(sdma->regs + SDMA_H_INTR) & 1)) {
 519                 if (timeout-- <= 0)
 520                         break;
 521                 udelay(1);
 522         }
 523
 524         if (ret) {
 525                 /* Clear the interrupt status */
 526                 writel_relaxed(ret, sdma->regs + SDMA_H_INTR);
 527         } else {
 528                 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n");
 529         }
 530
 531         return ret ? 0 : -ETIMEDOUT;
 532 }
 533
 534 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
 535                 u32 address)
 536 {
 537         struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
 538         void *buf_virt;
 539         dma_addr_t buf_phys;
 540         int ret;
 541         unsigned long flags;
 542
 543         buf_virt = dma_alloc_coherent(NULL,
 544                         size,
 545                         &buf_phys, GFP_KERNEL);
 546         if (!buf_virt) {
 547                 return -ENOMEM;
 548         }
 549
 550         spin_lock_irqsave(&sdma->channel_0_lock, flags);
 551
 552         bd0->mode.command = C0_SETPM;
 553         bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
 554         bd0->mode.count = size / 2;
 555         bd0->buffer_addr = buf_phys;
 556         bd0->ext_buffer_addr = address;
 557
 558         memcpy(buf_virt, buf, size);
 559
 560         ret = sdma_run_channel0(sdma);
 561
 562         spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
 563
 564         dma_free_coherent(NULL, size, buf_virt, buf_phys);
 565
 566         return ret;
 567 }
 568
 569 static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
 570 {
 571         struct sdma_engine *sdma = sdmac->sdma;
 572         int channel = sdmac->channel;
 573         unsigned long val;
 574         u32 chnenbl = chnenbl_ofs(sdma, event);
 575
 576         val = readl_relaxed(sdma->regs + chnenbl);
 577         __set_bit(channel, &val);
 578         writel_relaxed(val, sdma->regs + chnenbl);
 579 }
 580
 581 static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
 582 {
 583         struct sdma_engine *sdma = sdmac->sdma;
 584         int channel = sdmac->channel;
 585         u32 chnenbl = chnenbl_ofs(sdma, event);
 586         unsigned long val;
 587
 588         val = readl_relaxed(sdma->regs + chnenbl);
 589         __clear_bit(channel, &val);
 590         writel_relaxed(val, sdma->regs + chnenbl);
 591 }
 592
 593 static void sdma_handle_channel_loop(struct sdma_channel *sdmac)
 594 {
 595         struct sdma_buffer_descriptor *bd;
 596
 597         /*
 598          * loop mode. Iterate over descriptors, re-setup them and
 599          * call callback function.
 600          */
 601         while (1) {
 602                 bd = &sdmac->bd[sdmac->buf_tail];
 603
 604                 if (bd->mode.status & BD_DONE)
 605                         break;
 606
 607                 if (bd->mode.status & BD_RROR)
 608                         sdmac->status = DMA_ERROR;
 609                 else
 610                         sdmac->status = DMA_IN_PROGRESS;
 611
 612                 bd->mode.status |= BD_DONE;
 613                 sdmac->buf_tail++;
 614                 sdmac->buf_tail %= sdmac->num_bd;
 615
 616                 if (sdmac->desc.callback)
 617                         sdmac->desc.callback(sdmac->desc.callback_param);
 618         }
 619 }
 620
 621 static void mxc_sdma_handle_channel_normal(struct sdma_channel *sdmac)
 622 {
 623         struct sdma_buffer_descriptor *bd;
 624         int i, error = 0;
 625
 626         sdmac->chn_real_count = 0;
 627         /*
 628          * non loop mode. Iterate over all descriptors, collect
 629          * errors and call callback function
 630          */
 631         for (i = 0; i < sdmac->num_bd; i++) {
 632                 bd = &sdmac->bd[i];
 633
 634                  if (bd->mode.status & (BD_DONE | BD_RROR))
 635                         error = -EIO;
 636                  sdmac->chn_real_count += bd->mode.count;
 637         }
 638
 639         if (error)
 640                 sdmac->status = DMA_ERROR;
 641         else
 642                 sdmac->status = DMA_COMPLETE;
 643
 644         dma_cookie_complete(&sdmac->desc);
 645         if (sdmac->desc.callback)
 646                 sdmac->desc.callback(sdmac->desc.callback_param);
 647 }
 648
 649 static void sdma_tasklet(unsigned long data)
 650 {
 651         struct sdma_channel *sdmac = (struct sdma_channel *) data;
 652
 653         if (sdmac->flags & IMX_DMA_SG_LOOP)
 654                 sdma_handle_channel_loop(sdmac);
 655         else
 656                 mxc_sdma_handle_channel_normal(sdmac);
 657 }
 658
 659 static irqreturn_t sdma_int_handler(int irq, void *dev_id)
 660 {
 661         struct sdma_engine *sdma = dev_id;
 662         unsigned long stat;
 663
 664         stat = readl_relaxed(sdma->regs + SDMA_H_INTR);
 665         /* not interested in channel 0 interrupts */
 666         stat &= ~1;
 667         writel_relaxed(stat, sdma->regs + SDMA_H_INTR);
 668
 669         while (stat) {
 670                 int channel = fls(stat) - 1;
 671                 struct sdma_channel *sdmac = &sdma->channel[channel];
 672
 673                 tasklet_schedule(&sdmac->tasklet);
 674
 675                 __clear_bit(channel, &stat);
 676         }
 677
 678         return IRQ_HANDLED;
 679 }
 680
 681 /*
 682  * sets the pc of SDMA script according to the peripheral type
 683  */
 684 static void sdma_get_pc(struct sdma_channel *sdmac,
 685                 enum sdma_peripheral_type peripheral_type)
 686 {
 687         struct sdma_engine *sdma = sdmac->sdma;
 688         int per_2_emi = 0, emi_2_per = 0;
 689         /*
 690          * These are needed once we start to support transfers between
 691          * two peripherals or memory-to-memory transfers
 692          */
 693         int per_2_per = 0, emi_2_emi = 0;
 694
 695         sdmac->pc_from_device = 0;
 696         sdmac->pc_to_device = 0;
 697
 698         switch (peripheral_type) {
 699         case IMX_DMATYPE_MEMORY:
 700                 emi_2_emi = sdma->script_addrs->ap_2_ap_addr;
 701                 break;
 702         case IMX_DMATYPE_DSP:
 703                 emi_2_per = sdma->script_addrs->bp_2_ap_addr;
 704                 per_2_emi = sdma->script_addrs->ap_2_bp_addr;
 705                 break;
 706         case IMX_DMATYPE_FIRI:
 707                 per_2_emi = sdma->script_addrs->firi_2_mcu_addr;
 708                 emi_2_per = sdma->script_addrs->mcu_2_firi_addr;
 709                 break;
 710         case IMX_DMATYPE_UART:
 711                 per_2_emi = sdma->script_addrs->uart_2_mcu_addr;
 712                 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
 713                 break;
 714         case IMX_DMATYPE_UART_SP:
 715                 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr;
 716                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
 717                 break;
 718         case IMX_DMATYPE_ATA:
 719                 per_2_emi = sdma->script_addrs->ata_2_mcu_addr;
 720                 emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
 721                 break;
 722         case IMX_DMATYPE_CSPI:
 723         case IMX_DMATYPE_EXT:
 724         case IMX_DMATYPE_SSI:
 725                 per_2_emi = sdma->script_addrs->app_2_mcu_addr;
 726                 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
 727                 break;
 728         case IMX_DMATYPE_SSI_DUAL:
 729                 per_2_emi = sdma->script_addrs->ssish_2_mcu_addr;
 730                 emi_2_per = sdma->script_addrs->mcu_2_ssish_addr;
 731                 break;
 732         case IMX_DMATYPE_SSI_SP:
 733         case IMX_DMATYPE_MMC:
 734         case IMX_DMATYPE_SDHC:
 735         case IMX_DMATYPE_CSPI_SP:
 736         case IMX_DMATYPE_ESAI:
 737         case IMX_DMATYPE_MSHC_SP:
 738                 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
 739                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
 740                 break;
 741         case IMX_DMATYPE_ASRC:
 742                 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
 743                 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
 744                 per_2_per = sdma->script_addrs->per_2_per_addr;
 745                 break;
 746         case IMX_DMATYPE_MSHC:
 747                 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr;
 748                 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr;
 749                 break;
 750         case IMX_DMATYPE_CCM:
 751                 per_2_emi = sdma->script_addrs->dptc_dvfs_addr;
 752                 break;
 753         case IMX_DMATYPE_SPDIF:
 754                 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr;
 755                 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr;
 756                 break;
 757         case IMX_DMATYPE_IPU_MEMORY:
 758                 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
 759                 break;
 760         default:
 761                 break;
 762         }
 763
 764         sdmac->pc_from_device = per_2_emi;
 765         sdmac->pc_to_device = emi_2_per;
 766 }
 767
 768 static int sdma_load_context(struct sdma_channel *sdmac)
 769 {
 770         struct sdma_engine *sdma = sdmac->sdma;
 771         int channel = sdmac->channel;
 772         int load_address;
 773         struct sdma_context_data *context = sdma->context;
 774         struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
 775         int ret;
 776         unsigned long flags;
 777
 778         if (sdmac->direction == DMA_DEV_TO_MEM) {
 779                 load_address = sdmac->pc_from_device;
 780         } else {
 781                 load_address = sdmac->pc_to_device;
 782         }
 783
 784         if (load_address < 0)
 785                 return load_address;
 786
 787         dev_dbg(sdma->dev, "load_address = %d\n", load_address);
 788         dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level);
 789         dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
 790         dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
 791         dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]);
 792         dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]);
 793
 794         spin_lock_irqsave(&sdma->channel_0_lock, flags);
 795
 796         memset(context, 0, sizeof(*context));
 797         context->channel_state.pc = load_address;
 798
 799         /* Send by context the event mask,base address for peripheral
 800          * and watermark level
 801          */
 802         context->gReg[0] = sdmac->event_mask[1];
 803         context->gReg[1] = sdmac->event_mask[0];
 804         context->gReg[2] = sdmac->per_addr;
 805         context->gReg[6] = sdmac->shp_addr;
 806         context->gReg[7] = sdmac->watermark_level;
 807
 808         bd0->mode.command = C0_SETDM;
 809         bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
 810         bd0->mode.count = sizeof(*context) / 4;
 811         bd0->buffer_addr = sdma->context_phys;
 812         bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel;
 813         ret = sdma_run_channel0(sdma);
 814
 815         spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
 816
 817         return ret;
 818 }
 819
 820 static void sdma_disable_channel(struct sdma_channel *sdmac)
 821 {
 822         struct sdma_engine *sdma = sdmac->sdma;
 823         int channel = sdmac->channel;
 824
 825         writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
 826         sdmac->status = DMA_ERROR;
 827 }
 828
 829 static int sdma_config_channel(struct sdma_channel *sdmac)
 830 {
 831         int ret;
 832
 833         sdma_disable_channel(sdmac);
 834
 835         sdmac->event_mask[0] = 0;
 836         sdmac->event_mask[1] = 0;
 837         sdmac->shp_addr = 0;
 838         sdmac->per_addr = 0;
 839
 840         if (sdmac->event_id0) {
 841                 if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events)
 842                         return -EINVAL;
 843                 sdma_event_enable(sdmac, sdmac->event_id0);
 844         }
 845
 846         switch (sdmac->peripheral_type) {
 847         case IMX_DMATYPE_DSP:
 848                 sdma_config_ownership(sdmac, false, true, true);
 849                 break;
 850         case IMX_DMATYPE_MEMORY:
 851                 sdma_config_ownership(sdmac, false, true, false);
 852                 break;
 853         default:
 854                 sdma_config_ownership(sdmac, true, true, false);
 855                 break;
 856         }
 857
 858         sdma_get_pc(sdmac, sdmac->peripheral_type);
 859
 860         if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
 861                         (sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
 862                 /* Handle multiple event channels differently */
 863                 if (sdmac->event_id1) {
 864                         sdmac->event_mask[1] = BIT(sdmac->event_id1 % 32);
 865                         if (sdmac->event_id1 > 31)
 866                                 __set_bit(31, &sdmac->watermark_level);
 867                         sdmac->event_mask[0] = BIT(sdmac->event_id0 % 32);
 868                         if (sdmac->event_id0 > 31)
 869                                 __set_bit(30, &sdmac->watermark_level);
 870                 } else {
 871                         __set_bit(sdmac->event_id0, sdmac->event_mask);
 872                 }
 873                 /* Watermark Level */
 874                 sdmac->watermark_level |= sdmac->watermark_level;
 875                 /* Address */
 876                 sdmac->shp_addr = sdmac->per_address;
 877         } else {
 878                 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
 879         }
 880
 881         ret = sdma_load_context(sdmac);
 882
 883         return ret;
 884 }
 885
 886 static int sdma_set_channel_priority(struct sdma_channel *sdmac,
 887                 unsigned int priority)
 888 {
 889         struct sdma_engine *sdma = sdmac->sdma;
 890         int channel = sdmac->channel;
 891
 892         if (priority < MXC_SDMA_MIN_PRIORITY
 893             || priority > MXC_SDMA_MAX_PRIORITY) {
 894                 return -EINVAL;
 895         }
 896
 897         writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
 898
 899         return 0;
 900 }
 901
 902 static int sdma_request_channel(struct sdma_channel *sdmac)
 903 {
 904         struct sdma_engine *sdma = sdmac->sdma;
 905         int channel = sdmac->channel;
 906         int ret = -EBUSY;
 907
 908         sdmac->bd = dma_alloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys, GFP_KERNEL);
 909         if (!sdmac->bd) {
 910                 ret = -ENOMEM;
 911                 goto out;
 912         }
 913
 914         memset(sdmac->bd, 0, PAGE_SIZE);
 915
 916         sdma->channel_control[channel].base_bd_ptr = sdmac->bd_phys;
 917         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
 918
 919         sdma_set_channel_priority(sdmac, MXC_SDMA_DEFAULT_PRIORITY);
 920         return 0;
 921 out:
 922
 923         return ret;
 924 }
 925
 926 static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
 927 {
 928         return container_of(chan, struct sdma_channel, chan);
 929 }
 930
 931 static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx)
 932 {
 933         unsigned long flags;
 934         struct sdma_channel *sdmac = to_sdma_chan(tx->chan);
 935         dma_cookie_t cookie;
 936
 937         spin_lock_irqsave(&sdmac->lock, flags);
 938
 939         cookie = dma_cookie_assign(tx);
 940
 941         spin_unlock_irqrestore(&sdmac->lock, flags);
 942
 943         return cookie;
 944 }
 945
 946 static int sdma_alloc_chan_resources(struct dma_chan *chan)
 947 {
 948         struct sdma_channel *sdmac = to_sdma_chan(chan);
 949         struct imx_dma_data *data = chan->private;
 950         int prio, ret;
 951
 952         if (!data)
 953                 return -EINVAL;
 954
 955         switch (data->priority) {
 956         case DMA_PRIO_HIGH:
 957                 prio = 3;
 958                 break;
 959         case DMA_PRIO_MEDIUM:
 960                 prio = 2;
 961                 break;
 962         case DMA_PRIO_LOW:
 963         default:
 964                 prio = 1;
 965                 break;
 966         }
 967
 968         sdmac->peripheral_type = data->peripheral_type;
 969         sdmac->event_id0 = data->dma_request;
 970
 971         clk_enable(sdmac->sdma->clk_ipg);
 972         clk_enable(sdmac->sdma->clk_ahb);
 973
 974         ret = sdma_request_channel(sdmac);
 975         if (ret)
 976                 return ret;
 977
 978         ret = sdma_set_channel_priority(sdmac, prio);
 979         if (ret)
 980                 return ret;
 981
 982         dma_async_tx_descriptor_init(&sdmac->desc, chan);
 983         sdmac->desc.tx_submit = sdma_tx_submit;
 984         /* txd.flags will be overwritten in prep funcs */
 985         sdmac->desc.flags = DMA_CTRL_ACK;
 986
 987         return 0;
 988 }
 989
 990 static void sdma_free_chan_resources(struct dma_chan *chan)
 991 {
 992         struct sdma_channel *sdmac = to_sdma_chan(chan);
 993         struct sdma_engine *sdma = sdmac->sdma;
 994
 995         sdma_disable_channel(sdmac);
 996
 997         if (sdmac->event_id0)
 998                 sdma_event_disable(sdmac, sdmac->event_id0);
 999         if (sdmac->event_id1)
1000                 sdma_event_disable(sdmac, sdmac->event_id1);
1001
1002         sdmac->event_id0 = 0;
1003         sdmac->event_id1 = 0;
1004
1005         sdma_set_channel_priority(sdmac, 0);
1006
1007         dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys);
1008
1009         clk_disable(sdma->clk_ipg);
1010         clk_disable(sdma->clk_ahb);
1011 }
1012
1013 static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
1014                 struct dma_chan *chan, struct scatterlist *sgl,
1015                 unsigned int sg_len, enum dma_transfer_direction direction,
1016                 unsigned long flags, void *context)
1017 {
1018         struct sdma_channel *sdmac = to_sdma_chan(chan);
1019         struct sdma_engine *sdma = sdmac->sdma;
1020         int ret, i, count;
1021         int channel = sdmac->channel;
1022         struct scatterlist *sg;
1023
1024         if (sdmac->status == DMA_IN_PROGRESS)
1025                 return NULL;
1026         sdmac->status = DMA_IN_PROGRESS;
1027
1028         sdmac->flags = 0;
1029
1030         sdmac->buf_tail = 0;
1031
1032         dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
1033                         sg_len, channel);
1034
1035         sdmac->direction = direction;
1036         ret = sdma_load_context(sdmac);
1037         if (ret)
1038                 goto err_out;
1039
1040         if (sg_len > NUM_BD) {
1041                 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
1042                                 channel, sg_len, NUM_BD);
1043                 ret = -EINVAL;
1044                 goto err_out;
1045         }
1046
1047         sdmac->chn_count = 0;
1048         for_each_sg(sgl, sg, sg_len, i) {
1049                 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
1050                 int param;
1051
1052                 bd->buffer_addr = sg->dma_address;
1053
1054                 count = sg_dma_len(sg);
1055
1056                 if (count > 0xffff) {
1057                         dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
1058                                         channel, count, 0xffff);
1059                         ret = -EINVAL;
1060                         goto err_out;
1061                 }
1062
1063                 bd->mode.count = count;
1064                 sdmac->chn_count += count;
1065
1066                 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) {
1067                         ret =  -EINVAL;
1068                         goto err_out;
1069                 }
1070
1071                 switch (sdmac->word_size) {
1072                 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1073                         bd->mode.command = 0;
1074                         if (count & 3 || sg->dma_address & 3)
1075                                 return NULL;
1076                         break;
1077                 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1078                         bd->mode.command = 2;
1079                         if (count & 1 || sg->dma_address & 1)
1080                                 return NULL;
1081                         break;
1082                 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1083                         bd->mode.command = 1;
1084                         break;
1085                 default:
1086                         return NULL;
1087                 }
1088
1089                 param = BD_DONE | BD_EXTD | BD_CONT;
1090
1091                 if (i + 1 == sg_len) {
1092                         param |= BD_INTR;
1093                         param |= BD_LAST;
1094                         param &= ~BD_CONT;
1095                 }
1096
1097                 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n",
1098                                 i, count, (u64)sg->dma_address,
1099                                 param & BD_WRAP ? "wrap" : "",
1100                                 param & BD_INTR ? " intr" : "");
1101
1102                 bd->mode.status = param;
1103         }
1104
1105         sdmac->num_bd = sg_len;
1106         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1107
1108         return &sdmac->desc;
1109 err_out:
1110         sdmac->status = DMA_ERROR;
1111         return NULL;
1112 }
1113
1114 static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
1115                 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
1116                 size_t period_len, enum dma_transfer_direction direction,
1117                 unsigned long flags, void *context)
1118 {
1119         struct sdma_channel *sdmac = to_sdma_chan(chan);
1120         struct sdma_engine *sdma = sdmac->sdma;
1121         int num_periods = buf_len / period_len;
1122         int channel = sdmac->channel;
1123         int ret, i = 0, buf = 0;
1124
1125         dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
1126
1127         if (sdmac->status == DMA_IN_PROGRESS)
1128                 return NULL;
1129
1130         sdmac->status = DMA_IN_PROGRESS;
1131
1132         sdmac->buf_tail = 0;
1133
1134         sdmac->flags |= IMX_DMA_SG_LOOP;
1135         sdmac->direction = direction;
1136         ret = sdma_load_context(sdmac);
1137         if (ret)
1138                 goto err_out;
1139
1140         if (num_periods > NUM_BD) {
1141                 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
1142                                 channel, num_periods, NUM_BD);
1143                 goto err_out;
1144         }
1145
1146         if (period_len > 0xffff) {
1147                 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %d > %d\n",
1148                                 channel, period_len, 0xffff);
1149                 goto err_out;
1150         }
1151
1152         while (buf < buf_len) {
1153                 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
1154                 int param;
1155
1156                 bd->buffer_addr = dma_addr;
1157
1158                 bd->mode.count = period_len;
1159
1160                 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1161                         goto err_out;
1162                 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES)
1163                         bd->mode.command = 0;
1164                 else
1165                         bd->mode.command = sdmac->word_size;
1166
1167                 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
1168                 if (i + 1 == num_periods)
1169                         param |= BD_WRAP;
1170
1171                 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n",
1172                                 i, period_len, (u64)dma_addr,
1173                                 param & BD_WRAP ? "wrap" : "",
1174                                 param & BD_INTR ? " intr" : "");
1175
1176                 bd->mode.status = param;
1177
1178                 dma_addr += period_len;
1179                 buf += period_len;
1180
1181                 i++;
1182         }
1183
1184         sdmac->num_bd = num_periods;
1185         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1186
1187         return &sdmac->desc;
1188 err_out:
1189         sdmac->status = DMA_ERROR;
1190         return NULL;
1191 }
1192
1193 static int sdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1194                 unsigned long arg)
1195 {
1196         struct sdma_channel *sdmac = to_sdma_chan(chan);
1197         struct dma_slave_config *dmaengine_cfg = (void *)arg;
1198
1199         switch (cmd) {
1200         case DMA_TERMINATE_ALL:
1201                 sdma_disable_channel(sdmac);
1202                 return 0;
1203         case DMA_SLAVE_CONFIG:
1204                 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
1205                         sdmac->per_address = dmaengine_cfg->src_addr;
1206                         sdmac->watermark_level = dmaengine_cfg->src_maxburst *
1207                                                 dmaengine_cfg->src_addr_width;
1208                         sdmac->word_size = dmaengine_cfg->src_addr_width;
1209                 } else {
1210                         sdmac->per_address = dmaengine_cfg->dst_addr;
1211                         sdmac->watermark_level = dmaengine_cfg->dst_maxburst *
1212                                                 dmaengine_cfg->dst_addr_width;
1213                         sdmac->word_size = dmaengine_cfg->dst_addr_width;
1214                 }
1215                 sdmac->direction = dmaengine_cfg->direction;
1216                 return sdma_config_channel(sdmac);
1217         default:
1218                 return -ENOSYS;
1219         }
1220
1221         return -EINVAL;
1222 }
1223
1224 static enum dma_status sdma_tx_status(struct dma_chan *chan,
1225                                       dma_cookie_t cookie,
1226                                       struct dma_tx_state *txstate)
1227 {
1228         struct sdma_channel *sdmac = to_sdma_chan(chan);
1229
1230         dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
1231                         sdmac->chn_count - sdmac->chn_real_count);
1232
1233         return sdmac->status;
1234 }
1235
1236 static void sdma_issue_pending(struct dma_chan *chan)
1237 {
1238         struct sdma_channel *sdmac = to_sdma_chan(chan);
1239         struct sdma_engine *sdma = sdmac->sdma;
1240
1241         if (sdmac->status == DMA_IN_PROGRESS)
1242                 sdma_enable_channel(sdma, sdmac->channel);
1243 }
1244
1245 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
1246 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2 38
1247
1248 static void sdma_add_scripts(struct sdma_engine *sdma,
1249                 const struct sdma_script_start_addrs *addr)
1250 {
1251         s32 *addr_arr = (u32 *)addr;
1252         s32 *saddr_arr = (u32 *)sdma->script_addrs;
1253         int i;
1254
1255         /* use the default firmware in ROM if missing external firmware */
1256         if (!sdma->script_number)
1257                 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1258
1259         for (i = 0; i < sdma->script_number; i++)
1260                 if (addr_arr[i] > 0)
1261                         saddr_arr[i] = addr_arr[i];
1262 }
1263
1264 static void sdma_load_firmware(const struct firmware *fw, void *context)
1265 {
1266         struct sdma_engine *sdma = context;
1267         const struct sdma_firmware_header *header;
1268         const struct sdma_script_start_addrs *addr;
1269         unsigned short *ram_code;
1270
1271         if (!fw) {
1272                 dev_err(sdma->dev, "firmware not found\n");
1273                 return;
1274         }
1275
1276         if (fw->size < sizeof(*header))
1277                 goto err_firmware;
1278
1279         header = (struct sdma_firmware_header *)fw->data;
1280
1281         if (header->magic != SDMA_FIRMWARE_MAGIC)
1282                 goto err_firmware;
1283         if (header->ram_code_start + header->ram_code_size > fw->size)
1284                 goto err_firmware;
1285         switch (header->version_major) {
1286                 case 1:
1287                         sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1288                         break;
1289                 case 2:
1290                         sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2;
1291                         break;
1292                 default:
1293                         dev_err(sdma->dev, "unknown firmware version\n");
1294                         goto err_firmware;
1295         }
1296
1297         addr = (void *)header + header->script_addrs_start;
1298         ram_code = (void *)header + header->ram_code_start;
1299
1300         clk_enable(sdma->clk_ipg);
1301         clk_enable(sdma->clk_ahb);
1302         /* download the RAM image for SDMA */
1303         sdma_load_script(sdma, ram_code,
1304                         header->ram_code_size,
1305                         addr->ram_code_start_addr);
1306         clk_disable(sdma->clk_ipg);
1307         clk_disable(sdma->clk_ahb);
1308
1309         sdma_add_scripts(sdma, addr);
1310
1311         dev_info(sdma->dev, "loaded firmware %d.%d\n",
1312                         header->version_major,
1313                         header->version_minor);
1314
1315 err_firmware:
1316         release_firmware(fw);
1317 }
1318
1319 static int __init sdma_get_firmware(struct sdma_engine *sdma,
1320                 const char *fw_name)
1321 {
1322         int ret;
1323
1324         ret = request_firmware_nowait(THIS_MODULE,
1325                         FW_ACTION_HOTPLUG, fw_name, sdma->dev,
1326                         GFP_KERNEL, sdma, sdma_load_firmware);
1327
1328         return ret;
1329 }
1330
1331 static int __init sdma_init(struct sdma_engine *sdma)
1332 {
1333         int i, ret;
1334         dma_addr_t ccb_phys;
1335
1336         clk_enable(sdma->clk_ipg);
1337         clk_enable(sdma->clk_ahb);
1338
1339         /* Be sure SDMA has not started yet */
1340         writel_relaxed(0, sdma->regs + SDMA_H_C0PTR);
1341
1342         sdma->channel_control = dma_alloc_coherent(NULL,
1343                         MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
1344                         sizeof(struct sdma_context_data),
1345                         &ccb_phys, GFP_KERNEL);
1346
1347         if (!sdma->channel_control) {
1348                 ret = -ENOMEM;
1349                 goto err_dma_alloc;
1350         }
1351
1352         sdma->context = (void *)sdma->channel_control +
1353                 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1354         sdma->context_phys = ccb_phys +
1355                 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1356
1357         /* Zero-out the CCB structures array just allocated */
1358         memset(sdma->channel_control, 0,
1359                         MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control));
1360
1361         /* disable all channels */
1362         for (i = 0; i < sdma->drvdata->num_events; i++)
1363                 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i));
1364
1365         /* All channels have priority 0 */
1366         for (i = 0; i < MAX_DMA_CHANNELS; i++)
1367                 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
1368
1369         ret = sdma_request_channel(&sdma->channel[0]);
1370         if (ret)
1371                 goto err_dma_alloc;
1372
1373         sdma_config_ownership(&sdma->channel[0], false, true, false);
1374
1375         /* Set Command Channel (Channel Zero) */
1376         writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR);
1377
1378         /* Set bits of CONFIG register but with static context switching */
1379         /* FIXME: Check whether to set ACR bit depending on clock ratios */
1380         writel_relaxed(0, sdma->regs + SDMA_H_CONFIG);
1381
1382         writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR);
1383
1384         /* Set bits of CONFIG register with given context switching mode */
1385         writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG);
1386
1387         /* Initializes channel's priorities */
1388         sdma_set_channel_priority(&sdma->channel[0], 7);
1389
1390         clk_disable(sdma->clk_ipg);
1391         clk_disable(sdma->clk_ahb);
1392
1393         return 0;
1394
1395 err_dma_alloc:
1396         clk_disable(sdma->clk_ipg);
1397         clk_disable(sdma->clk_ahb);
1398         dev_err(sdma->dev, "initialisation failed with %d\n", ret);
1399         return ret;
1400 }
1401
1402 static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param)
1403 {
1404         struct imx_dma_data *data = fn_param;
1405
1406         if (!imx_dma_is_general_purpose(chan))
1407                 return false;
1408
1409         chan->private = data;
1410
1411         return true;
1412 }
1413
1414 static struct dma_chan *sdma_xlate(struct of_phandle_args *dma_spec,
1415                                    struct of_dma *ofdma)
1416 {
1417         struct sdma_engine *sdma = ofdma->of_dma_data;
1418         dma_cap_mask_t mask = sdma->dma_device.cap_mask;
1419         struct imx_dma_data data;
1420
1421         if (dma_spec->args_count != 3)
1422                 return NULL;
1423
1424         data.dma_request = dma_spec->args[0];
1425         data.peripheral_type = dma_spec->args[1];
1426         data.priority = dma_spec->args[2];
1427
1428         return dma_request_channel(mask, sdma_filter_fn, &data);
1429 }
1430
1431 static int __init sdma_probe(struct platform_device *pdev)
1432 {
1433         const struct of_device_id *of_id =
1434                         of_match_device(sdma_dt_ids, &pdev->dev);
1435         struct device_node *np = pdev->dev.of_node;
1436         const char *fw_name;
1437         int ret;
1438         int irq;
1439         struct resource *iores;
1440         struct sdma_platform_data *pdata = dev_get_platdata(&pdev->dev);
1441         int i;
1442         struct sdma_engine *sdma;
1443         s32 *saddr_arr;
1444         const struct sdma_driver_data *drvdata = NULL;
1445
1446         if (of_id)
1447                 drvdata = of_id->data;
1448         else if (pdev->id_entry)
1449                 drvdata = (void *)pdev->id_entry->driver_data;
1450
1451         if (!drvdata) {
1452                 dev_err(&pdev->dev, "unable to find driver data\n");
1453                 return -EINVAL;
1454         }
1455
1456         ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1457         if (ret)
1458                 return ret;
1459
1460         sdma = kzalloc(sizeof(*sdma), GFP_KERNEL);
1461         if (!sdma)
1462                 return -ENOMEM;
1463
1464         spin_lock_init(&sdma->channel_0_lock);
1465
1466         sdma->dev = &pdev->dev;
1467         sdma->drvdata = drvdata;
1468
1469         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1470         irq = platform_get_irq(pdev, 0);
1471         if (!iores || irq < 0) {
1472                 ret = -EINVAL;
1473                 goto err_irq;
1474         }
1475
1476         if (!request_mem_region(iores->start, resource_size(iores), pdev->name)) {
1477                 ret = -EBUSY;
1478                 goto err_request_region;
1479         }
1480
1481         sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1482         if (IS_ERR(sdma->clk_ipg)) {
1483                 ret = PTR_ERR(sdma->clk_ipg);
1484                 goto err_clk;
1485         }
1486
1487         sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1488         if (IS_ERR(sdma->clk_ahb)) {
1489                 ret = PTR_ERR(sdma->clk_ahb);
1490                 goto err_clk;
1491         }
1492
1493         clk_prepare(sdma->clk_ipg);
1494         clk_prepare(sdma->clk_ahb);
1495
1496         sdma->regs = ioremap(iores->start, resource_size(iores));
1497         if (!sdma->regs) {
1498                 ret = -ENOMEM;
1499                 goto err_ioremap;
1500         }
1501
1502         ret = request_irq(irq, sdma_int_handler, 0, "sdma", sdma);
1503         if (ret)
1504                 goto err_request_irq;
1505
1506         sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL);
1507         if (!sdma->script_addrs) {
1508                 ret = -ENOMEM;
1509                 goto err_alloc;
1510         }
1511
1512         /* initially no scripts available */
1513         saddr_arr = (s32 *)sdma->script_addrs;
1514         for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
1515                 saddr_arr[i] = -EINVAL;
1516
1517         dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
1518         dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);
1519
1520         INIT_LIST_HEAD(&sdma->dma_device.channels);
1521         /* Initialize channel parameters */
1522         for (i = 0; i < MAX_DMA_CHANNELS; i++) {
1523                 struct sdma_channel *sdmac = &sdma->channel[i];
1524
1525                 sdmac->sdma = sdma;
1526                 spin_lock_init(&sdmac->lock);
1527
1528                 sdmac->chan.device = &sdma->dma_device;
1529                 dma_cookie_init(&sdmac->chan);
1530                 sdmac->channel = i;
1531
1532                 tasklet_init(&sdmac->tasklet, sdma_tasklet,
1533                              (unsigned long) sdmac);
1534                 /*
1535                  * Add the channel to the DMAC list. Do not add channel 0 though
1536                  * because we need it internally in the SDMA driver. This also means
1537                  * that channel 0 in dmaengine counting matches sdma channel 1.
1538                  */
1539                 if (i)
1540                         list_add_tail(&sdmac->chan.device_node,
1541                                         &sdma->dma_device.channels);
1542         }
1543
1544         ret = sdma_init(sdma);
1545         if (ret)
1546                 goto err_init;
1547
1548         if (sdma->drvdata->script_addrs)
1549                 sdma_add_scripts(sdma, sdma->drvdata->script_addrs);
1550         if (pdata && pdata->script_addrs)
1551                 sdma_add_scripts(sdma, pdata->script_addrs);
1552
1553         if (pdata) {
1554                 ret = sdma_get_firmware(sdma, pdata->fw_name);
1555                 if (ret)
1556                         dev_warn(&pdev->dev, "failed to get firmware from platform data\n");
1557         } else {
1558                 /*
1559                  * Because that device tree does not encode ROM script address,
1560                  * the RAM script in firmware is mandatory for device tree
1561                  * probe, otherwise it fails.
1562                  */
1563                 ret = of_property_read_string(np, "fsl,sdma-ram-script-name",
1564                                               &fw_name);
1565                 if (ret)
1566                         dev_warn(&pdev->dev, "failed to get firmware name\n");
1567                 else {
1568                         ret = sdma_get_firmware(sdma, fw_name);
1569                         if (ret)
1570                                 dev_warn(&pdev->dev, "failed to get firmware from device tree\n");
1571                 }
1572         }
1573
1574         sdma->dma_device.dev = &pdev->dev;
1575
1576         sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources;
1577         sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources;
1578         sdma->dma_device.device_tx_status = sdma_tx_status;
1579         sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
1580         sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
1581         sdma->dma_device.device_control = sdma_control;
1582         sdma->dma_device.device_issue_pending = sdma_issue_pending;
1583         sdma->dma_device.dev->dma_parms = &sdma->dma_parms;
1584         dma_set_max_seg_size(sdma->dma_device.dev, 65535);
1585
1586         ret = dma_async_device_register(&sdma->dma_device);
1587         if (ret) {
1588                 dev_err(&pdev->dev, "unable to register\n");
1589                 goto err_init;
1590         }
1591
1592         if (np) {
1593                 ret = of_dma_controller_register(np, sdma_xlate, sdma);
1594                 if (ret) {
1595                         dev_err(&pdev->dev, "failed to register controller\n");
1596                         goto err_register;
1597                 }
1598         }
1599
1600         dev_info(sdma->dev, "initialized\n");
1601
1602         return 0;
1603
1604 err_register:
1605         dma_async_device_unregister(&sdma->dma_device);
1606 err_init:
1607         kfree(sdma->script_addrs);
1608 err_alloc:
1609         free_irq(irq, sdma);
1610 err_request_irq:
1611         iounmap(sdma->regs);
1612 err_ioremap:
1613 err_clk:
1614         release_mem_region(iores->start, resource_size(iores));
1615 err_request_region:
1616 err_irq:
1617         kfree(sdma);
1618         return ret;
1619 }
1620
1621 static int sdma_remove(struct platform_device *pdev)
1622 {
1623         return -EBUSY;
1624 }
1625
1626 static struct platform_driver sdma_driver = {
1627         .driver         = {
1628                 .name   = "imx-sdma",
1629                 .of_match_table = sdma_dt_ids,
1630         },
1631         .id_table       = sdma_devtypes,
1632         .remove         = sdma_remove,
1633 };
1634
1635 static int __init sdma_module_init(void)
1636 {
1637         return platform_driver_probe(&sdma_driver, sdma_probe);
1638 }
1639 module_init(sdma_module_init);
1640
1641 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1642 MODULE_DESCRIPTION("i.MX SDMA driver");
1643 MODULE_LICENSE("GPL");