drivers/dma/pch_dma.c

   1 /*
   2  * Topcliff PCH DMA controller driver
   3  * Copyright (c) 2010 Intel Corporation
   4  * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/dmaengine.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/init.h>
  19 #include <linux/pci.h>
  20 #include <linux/slab.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/module.h>
  23 #include <linux/pch_dma.h>
  24
  25 #include "dmaengine.h"
  26
  27 #define DRV_NAME "pch-dma"
  28
  29 #define DMA_CTL0_DISABLE                0x0
  30 #define DMA_CTL0_SG                     0x1
  31 #define DMA_CTL0_ONESHOT                0x2
  32 #define DMA_CTL0_MODE_MASK_BITS         0x3
  33 #define DMA_CTL0_DIR_SHIFT_BITS         2
  34 #define DMA_CTL0_BITS_PER_CH            4
  35
  36 #define DMA_CTL2_START_SHIFT_BITS       8
  37 #define DMA_CTL2_IRQ_ENABLE_MASK        ((1UL << DMA_CTL2_START_SHIFT_BITS) - 1)
  38
  39 #define DMA_STATUS_IDLE                 0x0
  40 #define DMA_STATUS_DESC_READ            0x1
  41 #define DMA_STATUS_WAIT                 0x2
  42 #define DMA_STATUS_ACCESS               0x3
  43 #define DMA_STATUS_BITS_PER_CH          2
  44 #define DMA_STATUS_MASK_BITS            0x3
  45 #define DMA_STATUS_SHIFT_BITS           16
  46 #define DMA_STATUS_IRQ(x)               (0x1 << (x))
  47 #define DMA_STATUS0_ERR(x)              (0x1 << ((x) + 8))
  48 #define DMA_STATUS2_ERR(x)              (0x1 << (x))
  49
  50 #define DMA_DESC_WIDTH_SHIFT_BITS       12
  51 #define DMA_DESC_WIDTH_1_BYTE           (0x3 << DMA_DESC_WIDTH_SHIFT_BITS)
  52 #define DMA_DESC_WIDTH_2_BYTES          (0x2 << DMA_DESC_WIDTH_SHIFT_BITS)
  53 #define DMA_DESC_WIDTH_4_BYTES          (0x0 << DMA_DESC_WIDTH_SHIFT_BITS)
  54 #define DMA_DESC_MAX_COUNT_1_BYTE       0x3FF
  55 #define DMA_DESC_MAX_COUNT_2_BYTES      0x3FF
  56 #define DMA_DESC_MAX_COUNT_4_BYTES      0x7FF
  57 #define DMA_DESC_END_WITHOUT_IRQ        0x0
  58 #define DMA_DESC_END_WITH_IRQ           0x1
  59 #define DMA_DESC_FOLLOW_WITHOUT_IRQ     0x2
  60 #define DMA_DESC_FOLLOW_WITH_IRQ        0x3
  61
  62 #define MAX_CHAN_NR                     12
  63
  64 #define DMA_MASK_CTL0_MODE      0x33333333
  65 #define DMA_MASK_CTL2_MODE      0x00003333
  66
  67 static unsigned int init_nr_desc_per_channel = 64;
  68 module_param(init_nr_desc_per_channel, uint, 0644);
  69 MODULE_PARM_DESC(init_nr_desc_per_channel,
  70                  "initial descriptors per channel (default: 64)");
  71
  72 struct pch_dma_desc_regs {
  73         u32     dev_addr;
  74         u32     mem_addr;
  75         u32     size;
  76         u32     next;
  77 };
  78
  79 struct pch_dma_regs {
  80         u32     dma_ctl0;
  81         u32     dma_ctl1;
  82         u32     dma_ctl2;
  83         u32     dma_ctl3;
  84         u32     dma_sts0;
  85         u32     dma_sts1;
  86         u32     dma_sts2;
  87         u32     reserved3;
  88         struct pch_dma_desc_regs desc[MAX_CHAN_NR];
  89 };
  90
  91 struct pch_dma_desc {
  92         struct pch_dma_desc_regs regs;
  93         struct dma_async_tx_descriptor txd;
  94         struct list_head        desc_node;
  95         struct list_head        tx_list;
  96 };
  97
  98 struct pch_dma_chan {
  99         struct dma_chan         chan;
 100         void __iomem *membase;
 101         enum dma_transfer_direction dir;
 102         struct tasklet_struct   tasklet;
 103         unsigned long           err_status;
 104
 105         spinlock_t              lock;
 106
 107         struct list_head        active_list;
 108         struct list_head        queue;
 109         struct list_head        free_list;
 110         unsigned int            descs_allocated;
 111 };
 112
 113 #define PDC_DEV_ADDR    0x00
 114 #define PDC_MEM_ADDR    0x04
 115 #define PDC_SIZE        0x08
 116 #define PDC_NEXT        0x0C
 117
 118 #define channel_readl(pdc, name) \
 119         readl((pdc)->membase + PDC_##name)
 120 #define channel_writel(pdc, name, val) \
 121         writel((val), (pdc)->membase + PDC_##name)
 122
 123 struct pch_dma {
 124         struct dma_device       dma;
 125         void __iomem *membase;
 126         struct pci_pool         *pool;
 127         struct pch_dma_regs     regs;
 128         struct pch_dma_desc_regs ch_regs[MAX_CHAN_NR];
 129         struct pch_dma_chan     channels[MAX_CHAN_NR];
 130 };
 131
 132 #define PCH_DMA_CTL0    0x00
 133 #define PCH_DMA_CTL1    0x04
 134 #define PCH_DMA_CTL2    0x08
 135 #define PCH_DMA_CTL3    0x0C
 136 #define PCH_DMA_STS0    0x10
 137 #define PCH_DMA_STS1    0x14
 138 #define PCH_DMA_STS2    0x18
 139
 140 #define dma_readl(pd, name) \
 141         readl((pd)->membase + PCH_DMA_##name)
 142 #define dma_writel(pd, name, val) \
 143         writel((val), (pd)->membase + PCH_DMA_##name)
 144
 145 static inline
 146 struct pch_dma_desc *to_pd_desc(struct dma_async_tx_descriptor *txd)
 147 {
 148         return container_of(txd, struct pch_dma_desc, txd);
 149 }
 150
 151 static inline struct pch_dma_chan *to_pd_chan(struct dma_chan *chan)
 152 {
 153         return container_of(chan, struct pch_dma_chan, chan);
 154 }
 155
 156 static inline struct pch_dma *to_pd(struct dma_device *ddev)
 157 {
 158         return container_of(ddev, struct pch_dma, dma);
 159 }
 160
 161 static inline struct device *chan2dev(struct dma_chan *chan)
 162 {
 163         return &chan->dev->device;
 164 }
 165
 166 static inline struct device *chan2parent(struct dma_chan *chan)
 167 {
 168         return chan->dev->device.parent;
 169 }
 170
 171 static inline
 172 struct pch_dma_desc *pdc_first_active(struct pch_dma_chan *pd_chan)
 173 {
 174         return list_first_entry(&pd_chan->active_list,
 175                                 struct pch_dma_desc, desc_node);
 176 }
 177
 178 static inline
 179 struct pch_dma_desc *pdc_first_queued(struct pch_dma_chan *pd_chan)
 180 {
 181         return list_first_entry(&pd_chan->queue,
 182                                 struct pch_dma_desc, desc_node);
 183 }
 184
 185 static void pdc_enable_irq(struct dma_chan *chan, int enable)
 186 {
 187         struct pch_dma *pd = to_pd(chan->device);
 188         u32 val;
 189         int pos;
 190
 191         if (chan->chan_id < 8)
 192                 pos = chan->chan_id;
 193         else
 194                 pos = chan->chan_id + 8;
 195
 196         val = dma_readl(pd, CTL2);
 197
 198         if (enable)
 199                 val |= 0x1 << pos;
 200         else
 201                 val &= ~(0x1 << pos);
 202
 203         dma_writel(pd, CTL2, val);
 204
 205         dev_dbg(chan2dev(chan), "pdc_enable_irq: chan %d -> %x\n",
 206                 chan->chan_id, val);
 207 }
 208
 209 static void pdc_set_dir(struct dma_chan *chan)
 210 {
 211         struct pch_dma_chan *pd_chan = to_pd_chan(chan);
 212         struct pch_dma *pd = to_pd(chan->device);
 213         u32 val;
 214         u32 mask_mode;
 215         u32 mask_ctl;
 216
 217         if (chan->chan_id < 8) {
 218                 val = dma_readl(pd, CTL0);
 219
 220                 mask_mode = DMA_CTL0_MODE_MASK_BITS <<
 221                                         (DMA_CTL0_BITS_PER_CH * chan->chan_id);
 222                 mask_ctl = DMA_MASK_CTL0_MODE & ~(DMA_CTL0_MODE_MASK_BITS <<
 223                                        (DMA_CTL0_BITS_PER_CH * chan->chan_id));
 224                 val &= mask_mode;
 225                 if (pd_chan->dir == DMA_MEM_TO_DEV)
 226                         val |= 0x1 << (DMA_CTL0_BITS_PER_CH * chan->chan_id +
 227                                        DMA_CTL0_DIR_SHIFT_BITS);
 228                 else
 229                         val &= ~(0x1 << (DMA_CTL0_BITS_PER_CH * chan->chan_id +
 230                                          DMA_CTL0_DIR_SHIFT_BITS));
 231
 232                 val |= mask_ctl;
 233                 dma_writel(pd, CTL0, val);
 234         } else {
 235                 int ch = chan->chan_id - 8; /* ch8-->0 ch9-->1 ... ch11->3 */
 236                 val = dma_readl(pd, CTL3);
 237
 238                 mask_mode = DMA_CTL0_MODE_MASK_BITS <<
 239                                                 (DMA_CTL0_BITS_PER_CH * ch);
 240                 mask_ctl = DMA_MASK_CTL2_MODE & ~(DMA_CTL0_MODE_MASK_BITS <<
 241                                                  (DMA_CTL0_BITS_PER_CH * ch));
 242                 val &= mask_mode;
 243                 if (pd_chan->dir == DMA_MEM_TO_DEV)
 244                         val |= 0x1 << (DMA_CTL0_BITS_PER_CH * ch +
 245                                        DMA_CTL0_DIR_SHIFT_BITS);
 246                 else
 247                         val &= ~(0x1 << (DMA_CTL0_BITS_PER_CH * ch +
 248                                          DMA_CTL0_DIR_SHIFT_BITS));
 249                 val |= mask_ctl;
 250                 dma_writel(pd, CTL3, val);
 251         }
 252
 253         dev_dbg(chan2dev(chan), "pdc_set_dir: chan %d -> %x\n",
 254                 chan->chan_id, val);
 255 }
 256
 257 static void pdc_set_mode(struct dma_chan *chan, u32 mode)
 258 {
 259         struct pch_dma *pd = to_pd(chan->device);
 260         u32 val;
 261         u32 mask_ctl;
 262         u32 mask_dir;
 263
 264         if (chan->chan_id < 8) {
 265                 mask_ctl = DMA_MASK_CTL0_MODE & ~(DMA_CTL0_MODE_MASK_BITS <<
 266                            (DMA_CTL0_BITS_PER_CH * chan->chan_id));
 267                 mask_dir = 1 << (DMA_CTL0_BITS_PER_CH * chan->chan_id +\
 268                                  DMA_CTL0_DIR_SHIFT_BITS);
 269                 val = dma_readl(pd, CTL0);
 270                 val &= mask_dir;
 271                 val |= mode << (DMA_CTL0_BITS_PER_CH * chan->chan_id);
 272                 val |= mask_ctl;
 273                 dma_writel(pd, CTL0, val);
 274         } else {
 275                 int ch = chan->chan_id - 8; /* ch8-->0 ch9-->1 ... ch11->3 */
 276                 mask_ctl = DMA_MASK_CTL2_MODE & ~(DMA_CTL0_MODE_MASK_BITS <<
 277                                                  (DMA_CTL0_BITS_PER_CH * ch));
 278                 mask_dir = 1 << (DMA_CTL0_BITS_PER_CH * ch +\
 279                                  DMA_CTL0_DIR_SHIFT_BITS);
 280                 val = dma_readl(pd, CTL3);
 281                 val &= mask_dir;
 282                 val |= mode << (DMA_CTL0_BITS_PER_CH * ch);
 283                 val |= mask_ctl;
 284                 dma_writel(pd, CTL3, val);
 285         }
 286
 287         dev_dbg(chan2dev(chan), "pdc_set_mode: chan %d -> %x\n",
 288                 chan->chan_id, val);
 289 }
 290
 291 static u32 pdc_get_status0(struct pch_dma_chan *pd_chan)
 292 {
 293         struct pch_dma *pd = to_pd(pd_chan->chan.device);
 294         u32 val;
 295
 296         val = dma_readl(pd, STS0);
 297         return DMA_STATUS_MASK_BITS & (val >> (DMA_STATUS_SHIFT_BITS +
 298                         DMA_STATUS_BITS_PER_CH * pd_chan->chan.chan_id));
 299 }
 300
 301 static u32 pdc_get_status2(struct pch_dma_chan *pd_chan)
 302 {
 303         struct pch_dma *pd = to_pd(pd_chan->chan.device);
 304         u32 val;
 305
 306         val = dma_readl(pd, STS2);
 307         return DMA_STATUS_MASK_BITS & (val >> (DMA_STATUS_SHIFT_BITS +
 308                         DMA_STATUS_BITS_PER_CH * (pd_chan->chan.chan_id - 8)));
 309 }
 310
 311 static bool pdc_is_idle(struct pch_dma_chan *pd_chan)
 312 {
 313         u32 sts;
 314
 315         if (pd_chan->chan.chan_id < 8)
 316                 sts = pdc_get_status0(pd_chan);
 317         else
 318                 sts = pdc_get_status2(pd_chan);
 319
 320
 321         if (sts == DMA_STATUS_IDLE)
 322                 return true;
 323         else
 324                 return false;
 325 }
 326
 327 static void pdc_dostart(struct pch_dma_chan *pd_chan, struct pch_dma_desc* desc)
 328 {
 329         if (!pdc_is_idle(pd_chan)) {
 330                 dev_err(chan2dev(&pd_chan->chan),
 331                         "BUG: Attempt to start non-idle channel\n");
 332                 return;
 333         }
 334
 335         dev_dbg(chan2dev(&pd_chan->chan), "chan %d -> dev_addr: %x\n",
 336                 pd_chan->chan.chan_id, desc->regs.dev_addr);
 337         dev_dbg(chan2dev(&pd_chan->chan), "chan %d -> mem_addr: %x\n",
 338                 pd_chan->chan.chan_id, desc->regs.mem_addr);
 339         dev_dbg(chan2dev(&pd_chan->chan), "chan %d -> size: %x\n",
 340                 pd_chan->chan.chan_id, desc->regs.size);
 341         dev_dbg(chan2dev(&pd_chan->chan), "chan %d -> next: %x\n",
 342                 pd_chan->chan.chan_id, desc->regs.next);
 343
 344         if (list_empty(&desc->tx_list)) {
 345                 channel_writel(pd_chan, DEV_ADDR, desc->regs.dev_addr);
 346                 channel_writel(pd_chan, MEM_ADDR, desc->regs.mem_addr);
 347                 channel_writel(pd_chan, SIZE, desc->regs.size);
 348                 channel_writel(pd_chan, NEXT, desc->regs.next);
 349                 pdc_set_mode(&pd_chan->chan, DMA_CTL0_ONESHOT);
 350         } else {
 351                 channel_writel(pd_chan, NEXT, desc->txd.phys);
 352                 pdc_set_mode(&pd_chan->chan, DMA_CTL0_SG);
 353         }
 354 }
 355
 356 static void pdc_chain_complete(struct pch_dma_chan *pd_chan,
 357                                struct pch_dma_desc *desc)
 358 {
 359         struct dma_async_tx_descriptor *txd = &desc->txd;
 360         struct dmaengine_desc_callback cb;
 361
 362         dmaengine_desc_get_callback(txd, &cb);
 363         list_splice_init(&desc->tx_list, &pd_chan->free_list);
 364         list_move(&desc->desc_node, &pd_chan->free_list);
 365
 366         dmaengine_desc_callback_invoke(&cb, NULL);
 367 }
 368
 369 static void pdc_complete_all(struct pch_dma_chan *pd_chan)
 370 {
 371         struct pch_dma_desc *desc, *_d;
 372         LIST_HEAD(list);
 373
 374         BUG_ON(!pdc_is_idle(pd_chan));
 375
 376         if (!list_empty(&pd_chan->queue))
 377                 pdc_dostart(pd_chan, pdc_first_queued(pd_chan));
 378
 379         list_splice_init(&pd_chan->active_list, &list);
 380         list_splice_init(&pd_chan->queue, &pd_chan->active_list);
 381
 382         list_for_each_entry_safe(desc, _d, &list, desc_node)
 383                 pdc_chain_complete(pd_chan, desc);
 384 }
 385
 386 static void pdc_handle_error(struct pch_dma_chan *pd_chan)
 387 {
 388         struct pch_dma_desc *bad_desc;
 389
 390         bad_desc = pdc_first_active(pd_chan);
 391         list_del(&bad_desc->desc_node);
 392
 393         list_splice_init(&pd_chan->queue, pd_chan->active_list.prev);
 394
 395         if (!list_empty(&pd_chan->active_list))
 396                 pdc_dostart(pd_chan, pdc_first_active(pd_chan));
 397
 398         dev_crit(chan2dev(&pd_chan->chan), "Bad descriptor submitted\n");
 399         dev_crit(chan2dev(&pd_chan->chan), "descriptor cookie: %d\n",
 400                  bad_desc->txd.cookie);
 401
 402         pdc_chain_complete(pd_chan, bad_desc);
 403 }
 404
 405 static void pdc_advance_work(struct pch_dma_chan *pd_chan)
 406 {
 407         if (list_empty(&pd_chan->active_list) ||
 408                 list_is_singular(&pd_chan->active_list)) {
 409                 pdc_complete_all(pd_chan);
 410         } else {
 411                 pdc_chain_complete(pd_chan, pdc_first_active(pd_chan));
 412                 pdc_dostart(pd_chan, pdc_first_active(pd_chan));
 413         }
 414 }
 415
 416 static dma_cookie_t pd_tx_submit(struct dma_async_tx_descriptor *txd)
 417 {
 418         struct pch_dma_desc *desc = to_pd_desc(txd);
 419         struct pch_dma_chan *pd_chan = to_pd_chan(txd->chan);
 420         dma_cookie_t cookie;
 421
 422         spin_lock(&pd_chan->lock);
 423         cookie = dma_cookie_assign(txd);
 424
 425         if (list_empty(&pd_chan->active_list)) {
 426                 list_add_tail(&desc->desc_node, &pd_chan->active_list);
 427                 pdc_dostart(pd_chan, desc);
 428         } else {
 429                 list_add_tail(&desc->desc_node, &pd_chan->queue);
 430         }
 431
 432         spin_unlock(&pd_chan->lock);
 433         return 0;
 434 }
 435
 436 static struct pch_dma_desc *pdc_alloc_desc(struct dma_chan *chan, gfp_t flags)
 437 {
 438         struct pch_dma_desc *desc = NULL;
 439         struct pch_dma *pd = to_pd(chan->device);
 440         dma_addr_t addr;
 441
 442         desc = pci_pool_alloc(pd->pool, flags, &addr);
 443         if (desc) {
 444                 memset(desc, 0, sizeof(struct pch_dma_desc));
 445                 INIT_LIST_HEAD(&desc->tx_list);
 446                 dma_async_tx_descriptor_init(&desc->txd, chan);
 447                 desc->txd.tx_submit = pd_tx_submit;
 448                 desc->txd.flags = DMA_CTRL_ACK;
 449                 desc->txd.phys = addr;
 450         }
 451
 452         return desc;
 453 }
 454
 455 static struct pch_dma_desc *pdc_desc_get(struct pch_dma_chan *pd_chan)
 456 {
 457         struct pch_dma_desc *desc, *_d;
 458         struct pch_dma_desc *ret = NULL;
 459         int i = 0;
 460
 461         spin_lock(&pd_chan->lock);
 462         list_for_each_entry_safe(desc, _d, &pd_chan->free_list, desc_node) {
 463                 i++;
 464                 if (async_tx_test_ack(&desc->txd)) {
 465                         list_del(&desc->desc_node);
 466                         ret = desc;
 467                         break;
 468                 }
 469                 dev_dbg(chan2dev(&pd_chan->chan), "desc %p not ACKed\n", desc);
 470         }
 471         spin_unlock(&pd_chan->lock);
 472         dev_dbg(chan2dev(&pd_chan->chan), "scanned %d descriptors\n", i);
 473
 474         if (!ret) {
 475                 ret = pdc_alloc_desc(&pd_chan->chan, GFP_ATOMIC);
 476                 if (ret) {
 477                         spin_lock(&pd_chan->lock);
 478                         pd_chan->descs_allocated++;
 479                         spin_unlock(&pd_chan->lock);
 480                 } else {
 481                         dev_err(chan2dev(&pd_chan->chan),
 482                                 "failed to alloc desc\n");
 483                 }
 484         }
 485
 486         return ret;
 487 }
 488
 489 static void pdc_desc_put(struct pch_dma_chan *pd_chan,
 490                          struct pch_dma_desc *desc)
 491 {
 492         if (desc) {
 493                 spin_lock(&pd_chan->lock);
 494                 list_splice_init(&desc->tx_list, &pd_chan->free_list);
 495                 list_add(&desc->desc_node, &pd_chan->free_list);
 496                 spin_unlock(&pd_chan->lock);
 497         }
 498 }
 499
 500 static int pd_alloc_chan_resources(struct dma_chan *chan)
 501 {
 502         struct pch_dma_chan *pd_chan = to_pd_chan(chan);
 503         struct pch_dma_desc *desc;
 504         LIST_HEAD(tmp_list);
 505         int i;
 506
 507         if (!pdc_is_idle(pd_chan)) {
 508                 dev_dbg(chan2dev(chan), "DMA channel not idle ?\n");
 509                 return -EIO;
 510         }
 511
 512         if (!list_empty(&pd_chan->free_list))
 513                 return pd_chan->descs_allocated;
 514
 515         for (i = 0; i < init_nr_desc_per_channel; i++) {
 516                 desc = pdc_alloc_desc(chan, GFP_KERNEL);
 517
 518                 if (!desc) {
 519                         dev_warn(chan2dev(chan),
 520                                 "Only allocated %d initial descriptors\n", i);
 521                         break;
 522                 }
 523
 524                 list_add_tail(&desc->desc_node, &tmp_list);
 525         }
 526
 527         spin_lock_irq(&pd_chan->lock);
 528         list_splice(&tmp_list, &pd_chan->free_list);
 529         pd_chan->descs_allocated = i;
 530         dma_cookie_init(chan);
 531         spin_unlock_irq(&pd_chan->lock);
 532
 533         pdc_enable_irq(chan, 1);
 534
 535         return pd_chan->descs_allocated;
 536 }
 537
 538 static void pd_free_chan_resources(struct dma_chan *chan)
 539 {
 540         struct pch_dma_chan *pd_chan = to_pd_chan(chan);
 541         struct pch_dma *pd = to_pd(chan->device);
 542         struct pch_dma_desc *desc, *_d;
 543         LIST_HEAD(tmp_list);
 544
 545         BUG_ON(!pdc_is_idle(pd_chan));
 546         BUG_ON(!list_empty(&pd_chan->active_list));
 547         BUG_ON(!list_empty(&pd_chan->queue));
 548
 549         spin_lock_irq(&pd_chan->lock);
 550         list_splice_init(&pd_chan->free_list, &tmp_list);
 551         pd_chan->descs_allocated = 0;
 552         spin_unlock_irq(&pd_chan->lock);
 553
 554         list_for_each_entry_safe(desc, _d, &tmp_list, desc_node)
 555                 pci_pool_free(pd->pool, desc, desc->txd.phys);
 556
 557         pdc_enable_irq(chan, 0);
 558 }
 559
 560 static enum dma_status pd_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
 561                                     struct dma_tx_state *txstate)
 562 {
 563         return dma_cookie_status(chan, cookie, txstate);
 564 }
 565
 566 static void pd_issue_pending(struct dma_chan *chan)
 567 {
 568         struct pch_dma_chan *pd_chan = to_pd_chan(chan);
 569
 570         if (pdc_is_idle(pd_chan)) {
 571                 spin_lock(&pd_chan->lock);
 572                 pdc_advance_work(pd_chan);
 573                 spin_unlock(&pd_chan->lock);
 574         }
 575 }
 576
 577 static struct dma_async_tx_descriptor *pd_prep_slave_sg(struct dma_chan *chan,
 578                         struct scatterlist *sgl, unsigned int sg_len,
 579                         enum dma_transfer_direction direction, unsigned long flags,
 580                         void *context)
 581 {
 582         struct pch_dma_chan *pd_chan = to_pd_chan(chan);
 583         struct pch_dma_slave *pd_slave = chan->private;
 584         struct pch_dma_desc *first = NULL;
 585         struct pch_dma_desc *prev = NULL;
 586         struct pch_dma_desc *desc = NULL;
 587         struct scatterlist *sg;
 588         dma_addr_t reg;
 589         int i;
 590
 591         if (unlikely(!sg_len)) {
 592                 dev_info(chan2dev(chan), "prep_slave_sg: length is zero!\n");
 593                 return NULL;
 594         }
 595
 596         if (direction == DMA_DEV_TO_MEM)
 597                 reg = pd_slave->rx_reg;
 598         else if (direction == DMA_MEM_TO_DEV)
 599                 reg = pd_slave->tx_reg;
 600         else
 601                 return NULL;
 602
 603         pd_chan->dir = direction;
 604         pdc_set_dir(chan);
 605
 606         for_each_sg(sgl, sg, sg_len, i) {
 607                 desc = pdc_desc_get(pd_chan);
 608
 609                 if (!desc)
 610                         goto err_desc_get;
 611
 612                 desc->regs.dev_addr = reg;
 613                 desc->regs.mem_addr = sg_dma_address(sg);
 614                 desc->regs.size = sg_dma_len(sg);
 615                 desc->regs.next = DMA_DESC_FOLLOW_WITHOUT_IRQ;
 616
 617                 switch (pd_slave->width) {
 618                 case PCH_DMA_WIDTH_1_BYTE:
 619                         if (desc->regs.size > DMA_DESC_MAX_COUNT_1_BYTE)
 620                                 goto err_desc_get;
 621                         desc->regs.size |= DMA_DESC_WIDTH_1_BYTE;
 622                         break;
 623                 case PCH_DMA_WIDTH_2_BYTES:
 624                         if (desc->regs.size > DMA_DESC_MAX_COUNT_2_BYTES)
 625                                 goto err_desc_get;
 626                         desc->regs.size |= DMA_DESC_WIDTH_2_BYTES;
 627                         break;
 628                 case PCH_DMA_WIDTH_4_BYTES:
 629                         if (desc->regs.size > DMA_DESC_MAX_COUNT_4_BYTES)
 630                                 goto err_desc_get;
 631                         desc->regs.size |= DMA_DESC_WIDTH_4_BYTES;
 632                         break;
 633                 default:
 634                         goto err_desc_get;
 635                 }
 636
 637                 if (!first) {
 638                         first = desc;
 639                 } else {
 640                         prev->regs.next |= desc->txd.phys;
 641                         list_add_tail(&desc->desc_node, &first->tx_list);
 642                 }
 643
 644                 prev = desc;
 645         }
 646
 647         if (flags & DMA_PREP_INTERRUPT)
 648                 desc->regs.next = DMA_DESC_END_WITH_IRQ;
 649         else
 650                 desc->regs.next = DMA_DESC_END_WITHOUT_IRQ;
 651
 652         first->txd.cookie = -EBUSY;
 653         desc->txd.flags = flags;
 654
 655         return &first->txd;
 656
 657 err_desc_get:
 658         dev_err(chan2dev(chan), "failed to get desc or wrong parameters\n");
 659         pdc_desc_put(pd_chan, first);
 660         return NULL;
 661 }
 662
 663 static int pd_device_terminate_all(struct dma_chan *chan)
 664 {
 665         struct pch_dma_chan *pd_chan = to_pd_chan(chan);
 666         struct pch_dma_desc *desc, *_d;
 667         LIST_HEAD(list);
 668
 669         spin_lock_irq(&pd_chan->lock);
 670
 671         pdc_set_mode(&pd_chan->chan, DMA_CTL0_DISABLE);
 672
 673         list_splice_init(&pd_chan->active_list, &list);
 674         list_splice_init(&pd_chan->queue, &list);
 675
 676         list_for_each_entry_safe(desc, _d, &list, desc_node)
 677                 pdc_chain_complete(pd_chan, desc);
 678
 679         spin_unlock_irq(&pd_chan->lock);
 680
 681         return 0;
 682 }
 683
 684 static void pdc_tasklet(unsigned long data)
 685 {
 686         struct pch_dma_chan *pd_chan = (struct pch_dma_chan *)data;
 687         unsigned long flags;
 688
 689         if (!pdc_is_idle(pd_chan)) {
 690                 dev_err(chan2dev(&pd_chan->chan),
 691                         "BUG: handle non-idle channel in tasklet\n");
 692                 return;
 693         }
 694
 695         spin_lock_irqsave(&pd_chan->lock, flags);
 696         if (test_and_clear_bit(0, &pd_chan->err_status))
 697                 pdc_handle_error(pd_chan);
 698         else
 699                 pdc_advance_work(pd_chan);
 700         spin_unlock_irqrestore(&pd_chan->lock, flags);
 701 }
 702
 703 static irqreturn_t pd_irq(int irq, void *devid)
 704 {
 705         struct pch_dma *pd = (struct pch_dma *)devid;
 706         struct pch_dma_chan *pd_chan;
 707         u32 sts0;
 708         u32 sts2;
 709         int i;
 710         int ret0 = IRQ_NONE;
 711         int ret2 = IRQ_NONE;
 712
 713         sts0 = dma_readl(pd, STS0);
 714         sts2 = dma_readl(pd, STS2);
 715
 716         dev_dbg(pd->dma.dev, "pd_irq sts0: %x\n", sts0);
 717
 718         for (i = 0; i < pd->dma.chancnt; i++) {
 719                 pd_chan = &pd->channels[i];
 720
 721                 if (i < 8) {
 722                         if (sts0 & DMA_STATUS_IRQ(i)) {
 723                                 if (sts0 & DMA_STATUS0_ERR(i))
 724                                         set_bit(0, &pd_chan->err_status);
 725
 726                                 tasklet_schedule(&pd_chan->tasklet);
 727                                 ret0 = IRQ_HANDLED;
 728                         }
 729                 } else {
 730                         if (sts2 & DMA_STATUS_IRQ(i - 8)) {
 731                                 if (sts2 & DMA_STATUS2_ERR(i))
 732                                         set_bit(0, &pd_chan->err_status);
 733
 734                                 tasklet_schedule(&pd_chan->tasklet);
 735                                 ret2 = IRQ_HANDLED;
 736                         }
 737                 }
 738         }
 739
 740         /* clear interrupt bits in status register */
 741         if (ret0)
 742                 dma_writel(pd, STS0, sts0);
 743         if (ret2)
 744                 dma_writel(pd, STS2, sts2);
 745
 746         return ret0 | ret2;
 747 }
 748
 749 #ifdef  CONFIG_PM
 750 static void pch_dma_save_regs(struct pch_dma *pd)
 751 {
 752         struct pch_dma_chan *pd_chan;
 753         struct dma_chan *chan, *_c;
 754         int i = 0;
 755
 756         pd->regs.dma_ctl0 = dma_readl(pd, CTL0);
 757         pd->regs.dma_ctl1 = dma_readl(pd, CTL1);
 758         pd->regs.dma_ctl2 = dma_readl(pd, CTL2);
 759         pd->regs.dma_ctl3 = dma_readl(pd, CTL3);
 760
 761         list_for_each_entry_safe(chan, _c, &pd->dma.channels, device_node) {
 762                 pd_chan = to_pd_chan(chan);
 763
 764                 pd->ch_regs[i].dev_addr = channel_readl(pd_chan, DEV_ADDR);
 765                 pd->ch_regs[i].mem_addr = channel_readl(pd_chan, MEM_ADDR);
 766                 pd->ch_regs[i].size = channel_readl(pd_chan, SIZE);
 767                 pd->ch_regs[i].next = channel_readl(pd_chan, NEXT);
 768
 769                 i++;
 770         }
 771 }
 772
 773 static void pch_dma_restore_regs(struct pch_dma *pd)
 774 {
 775         struct pch_dma_chan *pd_chan;
 776         struct dma_chan *chan, *_c;
 777         int i = 0;
 778
 779         dma_writel(pd, CTL0, pd->regs.dma_ctl0);
 780         dma_writel(pd, CTL1, pd->regs.dma_ctl1);
 781         dma_writel(pd, CTL2, pd->regs.dma_ctl2);
 782         dma_writel(pd, CTL3, pd->regs.dma_ctl3);
 783
 784         list_for_each_entry_safe(chan, _c, &pd->dma.channels, device_node) {
 785                 pd_chan = to_pd_chan(chan);
 786
 787                 channel_writel(pd_chan, DEV_ADDR, pd->ch_regs[i].dev_addr);
 788                 channel_writel(pd_chan, MEM_ADDR, pd->ch_regs[i].mem_addr);
 789                 channel_writel(pd_chan, SIZE, pd->ch_regs[i].size);
 790                 channel_writel(pd_chan, NEXT, pd->ch_regs[i].next);
 791
 792                 i++;
 793         }
 794 }
 795
 796 static int pch_dma_suspend(struct pci_dev *pdev, pm_message_t state)
 797 {
 798         struct pch_dma *pd = pci_get_drvdata(pdev);
 799
 800         if (pd)
 801                 pch_dma_save_regs(pd);
 802
 803         pci_save_state(pdev);
 804         pci_disable_device(pdev);
 805         pci_set_power_state(pdev, pci_choose_state(pdev, state));
 806
 807         return 0;
 808 }
 809
 810 static int pch_dma_resume(struct pci_dev *pdev)
 811 {
 812         struct pch_dma *pd = pci_get_drvdata(pdev);
 813         int err;
 814
 815         pci_set_power_state(pdev, PCI_D0);
 816         pci_restore_state(pdev);
 817
 818         err = pci_enable_device(pdev);
 819         if (err) {
 820                 dev_dbg(&pdev->dev, "failed to enable device\n");
 821                 return err;
 822         }
 823
 824         if (pd)
 825                 pch_dma_restore_regs(pd);
 826
 827         return 0;
 828 }
 829 #endif
 830
 831 static int pch_dma_probe(struct pci_dev *pdev,
 832                                    const struct pci_device_id *id)
 833 {
 834         struct pch_dma *pd;
 835         struct pch_dma_regs *regs;
 836         unsigned int nr_channels;
 837         int err;
 838         int i;
 839
 840         nr_channels = id->driver_data;
 841         pd = kzalloc(sizeof(*pd), GFP_KERNEL);
 842         if (!pd)
 843                 return -ENOMEM;
 844
 845         pci_set_drvdata(pdev, pd);
 846
 847         err = pci_enable_device(pdev);
 848         if (err) {
 849                 dev_err(&pdev->dev, "Cannot enable PCI device\n");
 850                 goto err_free_mem;
 851         }
 852
 853         if (!(pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
 854                 dev_err(&pdev->dev, "Cannot find proper base address\n");
 855                 err = -ENODEV;
 856                 goto err_disable_pdev;
 857         }
 858
 859         err = pci_request_regions(pdev, DRV_NAME);
 860         if (err) {
 861                 dev_err(&pdev->dev, "Cannot obtain PCI resources\n");
 862                 goto err_disable_pdev;
 863         }
 864
 865         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
 866         if (err) {
 867                 dev_err(&pdev->dev, "Cannot set proper DMA config\n");
 868                 goto err_free_res;
 869         }
 870
 871         regs = pd->membase = pci_iomap(pdev, 1, 0);
 872         if (!pd->membase) {
 873                 dev_err(&pdev->dev, "Cannot map MMIO registers\n");
 874                 err = -ENOMEM;
 875                 goto err_free_res;
 876         }
 877
 878         pci_set_master(pdev);
 879
 880         err = request_irq(pdev->irq, pd_irq, IRQF_SHARED, DRV_NAME, pd);
 881         if (err) {
 882                 dev_err(&pdev->dev, "Failed to request IRQ\n");
 883                 goto err_iounmap;
 884         }
 885
 886         pd->pool = pci_pool_create("pch_dma_desc_pool", pdev,
 887                                    sizeof(struct pch_dma_desc), 4, 0);
 888         if (!pd->pool) {
 889                 dev_err(&pdev->dev, "Failed to alloc DMA descriptors\n");
 890                 err = -ENOMEM;
 891                 goto err_free_irq;
 892         }
 893
 894         pd->dma.dev = &pdev->dev;
 895
 896         INIT_LIST_HEAD(&pd->dma.channels);
 897
 898         for (i = 0; i < nr_channels; i++) {
 899                 struct pch_dma_chan *pd_chan = &pd->channels[i];
 900
 901                 pd_chan->chan.device = &pd->dma;
 902                 dma_cookie_init(&pd_chan->chan);
 903
 904                 pd_chan->membase = &regs->desc[i];
 905
 906                 spin_lock_init(&pd_chan->lock);
 907
 908                 INIT_LIST_HEAD(&pd_chan->active_list);
 909                 INIT_LIST_HEAD(&pd_chan->queue);
 910                 INIT_LIST_HEAD(&pd_chan->free_list);
 911
 912                 tasklet_init(&pd_chan->tasklet, pdc_tasklet,
 913                              (unsigned long)pd_chan);
 914                 list_add_tail(&pd_chan->chan.device_node, &pd->dma.channels);
 915         }
 916
 917         dma_cap_zero(pd->dma.cap_mask);
 918         dma_cap_set(DMA_PRIVATE, pd->dma.cap_mask);
 919         dma_cap_set(DMA_SLAVE, pd->dma.cap_mask);
 920
 921         pd->dma.device_alloc_chan_resources = pd_alloc_chan_resources;
 922         pd->dma.device_free_chan_resources = pd_free_chan_resources;
 923         pd->dma.device_tx_status = pd_tx_status;
 924         pd->dma.device_issue_pending = pd_issue_pending;
 925         pd->dma.device_prep_slave_sg = pd_prep_slave_sg;
 926         pd->dma.device_terminate_all = pd_device_terminate_all;
 927
 928         err = dma_async_device_register(&pd->dma);
 929         if (err) {
 930                 dev_err(&pdev->dev, "Failed to register DMA device\n");
 931                 goto err_free_pool;
 932         }
 933
 934         return 0;
 935
 936 err_free_pool:
 937         pci_pool_destroy(pd->pool);
 938 err_free_irq:
 939         free_irq(pdev->irq, pd);
 940 err_iounmap:
 941         pci_iounmap(pdev, pd->membase);
 942 err_free_res:
 943         pci_release_regions(pdev);
 944 err_disable_pdev:
 945         pci_disable_device(pdev);
 946 err_free_mem:
 947         kfree(pd);
 948         return err;
 949 }
 950
 951 static void pch_dma_remove(struct pci_dev *pdev)
 952 {
 953         struct pch_dma *pd = pci_get_drvdata(pdev);
 954         struct pch_dma_chan *pd_chan;
 955         struct dma_chan *chan, *_c;
 956
 957         if (pd) {
 958                 dma_async_device_unregister(&pd->dma);
 959
 960                 free_irq(pdev->irq, pd);
 961
 962                 list_for_each_entry_safe(chan, _c, &pd->dma.channels,
 963                                          device_node) {
 964                         pd_chan = to_pd_chan(chan);
 965
 966                         tasklet_kill(&pd_chan->tasklet);
 967                 }
 968
 969                 pci_pool_destroy(pd->pool);
 970                 pci_iounmap(pdev, pd->membase);
 971                 pci_release_regions(pdev);
 972                 pci_disable_device(pdev);
 973                 kfree(pd);
 974         }
 975 }
 976
 977 /* PCI Device ID of DMA device */
 978 #define PCI_VENDOR_ID_ROHM             0x10DB
 979 #define PCI_DEVICE_ID_EG20T_PCH_DMA_8CH        0x8810
 980 #define PCI_DEVICE_ID_EG20T_PCH_DMA_4CH        0x8815
 981 #define PCI_DEVICE_ID_ML7213_DMA1_8CH   0x8026
 982 #define PCI_DEVICE_ID_ML7213_DMA2_8CH   0x802B
 983 #define PCI_DEVICE_ID_ML7213_DMA3_4CH   0x8034
 984 #define PCI_DEVICE_ID_ML7213_DMA4_12CH  0x8032
 985 #define PCI_DEVICE_ID_ML7223_DMA1_4CH   0x800B
 986 #define PCI_DEVICE_ID_ML7223_DMA2_4CH   0x800E
 987 #define PCI_DEVICE_ID_ML7223_DMA3_4CH   0x8017
 988 #define PCI_DEVICE_ID_ML7223_DMA4_4CH   0x803B
 989 #define PCI_DEVICE_ID_ML7831_DMA1_8CH   0x8810
 990 #define PCI_DEVICE_ID_ML7831_DMA2_4CH   0x8815
 991
 992 static const struct pci_device_id pch_dma_id_table[] = {
 993         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_EG20T_PCH_DMA_8CH), 8 },
 994         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_EG20T_PCH_DMA_4CH), 4 },
 995         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_DMA1_8CH), 8}, /* UART Video */
 996         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_DMA2_8CH), 8}, /* PCMIF SPI */
 997         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_DMA3_4CH), 4}, /* FPGA */
 998         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_DMA4_12CH), 12}, /* I2S */
 999         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_DMA1_4CH), 4}, /* UART */
1000         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_DMA2_4CH), 4}, /* Video SPI */
1001         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_DMA3_4CH), 4}, /* Security */
1002         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_DMA4_4CH), 4}, /* FPGA */
1003         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_DMA1_8CH), 8}, /* UART */
1004         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_DMA2_4CH), 4}, /* SPI */
1005         { 0, },
1006 };
1007
1008 static struct pci_driver pch_dma_driver = {
1009         .name           = DRV_NAME,
1010         .id_table       = pch_dma_id_table,
1011         .probe          = pch_dma_probe,
1012         .remove         = pch_dma_remove,
1013 #ifdef CONFIG_PM
1014         .suspend        = pch_dma_suspend,
1015         .resume         = pch_dma_resume,
1016 #endif
1017 };
1018
1019 module_pci_driver(pch_dma_driver);
1020
1021 MODULE_DESCRIPTION("Intel EG20T PCH / LAPIS Semicon ML7213/ML7223/ML7831 IOH "
1022                    "DMA controller driver");
1023 MODULE_AUTHOR("Yong Wang <yong.y.wang@intel.com>");
1024 MODULE_LICENSE("GPL v2");
1025 MODULE_DEVICE_TABLE(pci, pch_dma_id_table);