drivers/gpio/gpio-stmpe.c

   1 /*
   2  * Copyright (C) ST-Ericsson SA 2010
   3  *
   4  * License Terms: GNU General Public License, version 2
   5  * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
   6  */
   7
   8 #include <linux/init.h>
   9 #include <linux/platform_device.h>
  10 #include <linux/slab.h>
  11 #include <linux/gpio.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/of.h>
  14 #include <linux/mfd/stmpe.h>
  15 #include <linux/seq_file.h>
  16 #include <linux/bitops.h>
  17
  18 /*
  19  * These registers are modified under the irq bus lock and cached to avoid
  20  * unnecessary writes in bus_sync_unlock.
  21  */
  22 enum { REG_RE, REG_FE, REG_IE };
  23
  24 enum { LSB, CSB, MSB };
  25
  26 #define CACHE_NR_REGS   3
  27 /* No variant has more than 24 GPIOs */
  28 #define CACHE_NR_BANKS  (24 / 8)
  29
  30 struct stmpe_gpio {
  31         struct gpio_chip chip;
  32         struct stmpe *stmpe;
  33         struct device *dev;
  34         struct mutex irq_lock;
  35         u32 norequest_mask;
  36         /* Caches of interrupt control registers for bus_lock */
  37         u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
  38         u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
  39 };
  40
  41 static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
  42 {
  43         struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
  44         struct stmpe *stmpe = stmpe_gpio->stmpe;
  45         u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB + (offset / 8)];
  46         u8 mask = BIT(offset % 8);
  47         int ret;
  48
  49         ret = stmpe_reg_read(stmpe, reg);
  50         if (ret < 0)
  51                 return ret;
  52
  53         return !!(ret & mask);
  54 }
  55
  56 static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
  57 {
  58         struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
  59         struct stmpe *stmpe = stmpe_gpio->stmpe;
  60         int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
  61         u8 reg = stmpe->regs[which + (offset / 8)];
  62         u8 mask = BIT(offset % 8);
  63
  64         /*
  65          * Some variants have single register for gpio set/clear functionality.
  66          * For them we need to write 0 to clear and 1 to set.
  67          */
  68         if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
  69                 stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
  70         else
  71                 stmpe_reg_write(stmpe, reg, mask);
  72 }
  73
  74 static int stmpe_gpio_get_direction(struct gpio_chip *chip,
  75                                     unsigned offset)
  76 {
  77         struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
  78         struct stmpe *stmpe = stmpe_gpio->stmpe;
  79         u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
  80         u8 mask = BIT(offset % 8);
  81         int ret;
  82
  83         ret = stmpe_reg_read(stmpe, reg);
  84         if (ret < 0)
  85                 return ret;
  86
  87         return !(ret & mask);
  88 }
  89
  90 static int stmpe_gpio_direction_output(struct gpio_chip *chip,
  91                                          unsigned offset, int val)
  92 {
  93         struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
  94         struct stmpe *stmpe = stmpe_gpio->stmpe;
  95         u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
  96         u8 mask = BIT(offset % 8);
  97
  98         stmpe_gpio_set(chip, offset, val);
  99
 100         return stmpe_set_bits(stmpe, reg, mask, mask);
 101 }
 102
 103 static int stmpe_gpio_direction_input(struct gpio_chip *chip,
 104                                         unsigned offset)
 105 {
 106         struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
 107         struct stmpe *stmpe = stmpe_gpio->stmpe;
 108         u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
 109         u8 mask = BIT(offset % 8);
 110
 111         return stmpe_set_bits(stmpe, reg, mask, 0);
 112 }
 113
 114 static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
 115 {
 116         struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
 117         struct stmpe *stmpe = stmpe_gpio->stmpe;
 118
 119         if (stmpe_gpio->norequest_mask & BIT(offset))
 120                 return -EINVAL;
 121
 122         return stmpe_set_altfunc(stmpe, BIT(offset), STMPE_BLOCK_GPIO);
 123 }
 124
 125 static const struct gpio_chip template_chip = {
 126         .label                  = "stmpe",
 127         .owner                  = THIS_MODULE,
 128         .get_direction          = stmpe_gpio_get_direction,
 129         .direction_input        = stmpe_gpio_direction_input,
 130         .get                    = stmpe_gpio_get,
 131         .direction_output       = stmpe_gpio_direction_output,
 132         .set                    = stmpe_gpio_set,
 133         .request                = stmpe_gpio_request,
 134         .can_sleep              = true,
 135 };
 136
 137 static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 138 {
 139         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 140         struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
 141         int offset = d->hwirq;
 142         int regoffset = offset / 8;
 143         int mask = BIT(offset % 8);
 144
 145         if (type & IRQ_TYPE_LEVEL_LOW || type & IRQ_TYPE_LEVEL_HIGH)
 146                 return -EINVAL;
 147
 148         /* STMPE801 and STMPE 1600 don't have RE and FE registers */
 149         if (stmpe_gpio->stmpe->partnum == STMPE801 ||
 150             stmpe_gpio->stmpe->partnum == STMPE1600)
 151                 return 0;
 152
 153         if (type & IRQ_TYPE_EDGE_RISING)
 154                 stmpe_gpio->regs[REG_RE][regoffset] |= mask;
 155         else
 156                 stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;
 157
 158         if (type & IRQ_TYPE_EDGE_FALLING)
 159                 stmpe_gpio->regs[REG_FE][regoffset] |= mask;
 160         else
 161                 stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;
 162
 163         return 0;
 164 }
 165
 166 static void stmpe_gpio_irq_lock(struct irq_data *d)
 167 {
 168         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 169         struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
 170
 171         mutex_lock(&stmpe_gpio->irq_lock);
 172 }
 173
 174 static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
 175 {
 176         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 177         struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
 178         struct stmpe *stmpe = stmpe_gpio->stmpe;
 179         int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
 180         static const u8 regmap[CACHE_NR_REGS][CACHE_NR_BANKS] = {
 181                 [REG_RE][LSB] = STMPE_IDX_GPRER_LSB,
 182                 [REG_RE][CSB] = STMPE_IDX_GPRER_CSB,
 183                 [REG_RE][MSB] = STMPE_IDX_GPRER_MSB,
 184                 [REG_FE][LSB] = STMPE_IDX_GPFER_LSB,
 185                 [REG_FE][CSB] = STMPE_IDX_GPFER_CSB,
 186                 [REG_FE][MSB] = STMPE_IDX_GPFER_MSB,
 187                 [REG_IE][LSB] = STMPE_IDX_IEGPIOR_LSB,
 188                 [REG_IE][CSB] = STMPE_IDX_IEGPIOR_CSB,
 189                 [REG_IE][MSB] = STMPE_IDX_IEGPIOR_MSB,
 190         };
 191         int i, j;
 192
 193         for (i = 0; i < CACHE_NR_REGS; i++) {
 194                 /* STMPE801 and STMPE1600 don't have RE and FE registers */
 195                 if ((stmpe->partnum == STMPE801 ||
 196                      stmpe->partnum == STMPE1600) &&
 197                      (i != REG_IE))
 198                         continue;
 199
 200                 for (j = 0; j < num_banks; j++) {
 201                         u8 old = stmpe_gpio->oldregs[i][j];
 202                         u8 new = stmpe_gpio->regs[i][j];
 203
 204                         if (new == old)
 205                                 continue;
 206
 207                         stmpe_gpio->oldregs[i][j] = new;
 208                         stmpe_reg_write(stmpe, stmpe->regs[regmap[i][j]], new);
 209                 }
 210         }
 211
 212         mutex_unlock(&stmpe_gpio->irq_lock);
 213 }
 214
 215 static void stmpe_gpio_irq_mask(struct irq_data *d)
 216 {
 217         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 218         struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
 219         int offset = d->hwirq;
 220         int regoffset = offset / 8;
 221         int mask = BIT(offset % 8);
 222
 223         stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
 224 }
 225
 226 static void stmpe_gpio_irq_unmask(struct irq_data *d)
 227 {
 228         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 229         struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
 230         struct stmpe *stmpe = stmpe_gpio->stmpe;
 231         int offset = d->hwirq;
 232         int regoffset = offset / 8;
 233         int mask = BIT(offset % 8);
 234
 235         stmpe_gpio->regs[REG_IE][regoffset] |= mask;
 236
 237         /*
 238          * STMPE1600 workaround: to be able to get IRQ from pins,
 239          * a read must be done on GPMR register, or a write in
 240          * GPSR or GPCR registers
 241          */
 242         if (stmpe->partnum == STMPE1600)
 243                 stmpe_reg_read(stmpe,
 244                                stmpe->regs[STMPE_IDX_GPMR_LSB + regoffset]);
 245 }
 246
 247 static void stmpe_dbg_show_one(struct seq_file *s,
 248                                struct gpio_chip *gc,
 249                                unsigned offset, unsigned gpio)
 250 {
 251         struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
 252         struct stmpe *stmpe = stmpe_gpio->stmpe;
 253         const char *label = gpiochip_is_requested(gc, offset);
 254         bool val = !!stmpe_gpio_get(gc, offset);
 255         u8 bank = offset / 8;
 256         u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB + bank];
 257         u8 mask = BIT(offset % 8);
 258         int ret;
 259         u8 dir;
 260
 261         ret = stmpe_reg_read(stmpe, dir_reg);
 262         if (ret < 0)
 263                 return;
 264         dir = !!(ret & mask);
 265
 266         if (dir) {
 267                 seq_printf(s, " gpio-%-3d (%-20.20s) out %s",
 268                            gpio, label ?: "(none)",
 269                            val ? "hi" : "lo");
 270         } else {
 271                 u8 edge_det_reg;
 272                 u8 rise_reg;
 273                 u8 fall_reg;
 274                 u8 irqen_reg;
 275
 276                 char *edge_det_values[] = {"edge-inactive",
 277                                            "edge-asserted",
 278                                            "not-supported"};
 279                 char *rise_values[] = {"no-rising-edge-detection",
 280                                        "rising-edge-detection",
 281                                        "not-supported"};
 282                 char *fall_values[] = {"no-falling-edge-detection",
 283                                        "falling-edge-detection",
 284                                        "not-supported"};
 285                 #define NOT_SUPPORTED_IDX 2
 286                 u8 edge_det = NOT_SUPPORTED_IDX;
 287                 u8 rise = NOT_SUPPORTED_IDX;
 288                 u8 fall = NOT_SUPPORTED_IDX;
 289                 bool irqen;
 290
 291                 switch (stmpe->partnum) {
 292                 case STMPE610:
 293                 case STMPE811:
 294                 case STMPE1601:
 295                 case STMPE2401:
 296                 case STMPE2403:
 297                         edge_det_reg = stmpe->regs[STMPE_IDX_GPEDR_LSB + bank];
 298                         ret = stmpe_reg_read(stmpe, edge_det_reg);
 299                         if (ret < 0)
 300                                 return;
 301                         edge_det = !!(ret & mask);
 302
 303                 case STMPE1801:
 304                         rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB + bank];
 305                         fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB + bank];
 306
 307                         ret = stmpe_reg_read(stmpe, rise_reg);
 308                         if (ret < 0)
 309                                 return;
 310                         rise = !!(ret & mask);
 311                         ret = stmpe_reg_read(stmpe, fall_reg);
 312                         if (ret < 0)
 313                                 return;
 314                         fall = !!(ret & mask);
 315
 316                 case STMPE801:
 317                 case STMPE1600:
 318                         irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB + bank];
 319                         break;
 320
 321                 default:
 322                         return;
 323                 }
 324
 325                 ret = stmpe_reg_read(stmpe, irqen_reg);
 326                 if (ret < 0)
 327                         return;
 328                 irqen = !!(ret & mask);
 329
 330                 seq_printf(s, " gpio-%-3d (%-20.20s) in  %s %13s %13s %25s %25s",
 331                            gpio, label ?: "(none)",
 332                            val ? "hi" : "lo",
 333                            edge_det_values[edge_det],
 334                            irqen ? "IRQ-enabled" : "IRQ-disabled",
 335                            rise_values[rise],
 336                            fall_values[fall]);
 337         }
 338 }
 339
 340 static void stmpe_dbg_show(struct seq_file *s, struct gpio_chip *gc)
 341 {
 342         unsigned i;
 343         unsigned gpio = gc->base;
 344
 345         for (i = 0; i < gc->ngpio; i++, gpio++) {
 346                 stmpe_dbg_show_one(s, gc, i, gpio);
 347                 seq_printf(s, "\n");
 348         }
 349 }
 350
 351 static struct irq_chip stmpe_gpio_irq_chip = {
 352         .name                   = "stmpe-gpio",
 353         .irq_bus_lock           = stmpe_gpio_irq_lock,
 354         .irq_bus_sync_unlock    = stmpe_gpio_irq_sync_unlock,
 355         .irq_mask               = stmpe_gpio_irq_mask,
 356         .irq_unmask             = stmpe_gpio_irq_unmask,
 357         .irq_set_type           = stmpe_gpio_irq_set_type,
 358 };
 359
 360 static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
 361 {
 362         struct stmpe_gpio *stmpe_gpio = dev;
 363         struct stmpe *stmpe = stmpe_gpio->stmpe;
 364         u8 statmsbreg;
 365         int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
 366         u8 status[num_banks];
 367         int ret;
 368         int i;
 369
 370         /*
 371          * the stmpe_block_read() call below, imposes to set statmsbreg
 372          * with the register located at the lowest address. As STMPE1600
 373          * variant is the only one which respect registers address's order
 374          * (LSB regs located at lowest address than MSB ones) whereas all
 375          * the others have a registers layout with MSB located before the
 376          * LSB regs.
 377          */
 378         if (stmpe->partnum == STMPE1600)
 379                 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_LSB];
 380         else
 381                 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
 382
 383         ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
 384         if (ret < 0)
 385                 return IRQ_NONE;
 386
 387         for (i = 0; i < num_banks; i++) {
 388                 int bank = (stmpe_gpio->stmpe->partnum == STMPE1600) ? i :
 389                            num_banks - i - 1;
 390                 unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
 391                 unsigned int stat = status[i];
 392
 393                 stat &= enabled;
 394                 if (!stat)
 395                         continue;
 396
 397                 while (stat) {
 398                         int bit = __ffs(stat);
 399                         int line = bank * 8 + bit;
 400                         int child_irq = irq_find_mapping(stmpe_gpio->chip.irqdomain,
 401                                                          line);
 402
 403                         handle_nested_irq(child_irq);
 404                         stat &= ~BIT(bit);
 405                 }
 406
 407                 /*
 408                  * interrupt status register write has no effect on
 409                  * 801/1801/1600, bits are cleared when read.
 410                  * Edge detect register is not present on 801/1600/1801
 411                  */
 412                 if (stmpe->partnum != STMPE801 && stmpe->partnum != STMPE1600 &&
 413                     stmpe->partnum != STMPE1801) {
 414                         stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
 415                         stmpe_reg_write(stmpe,
 416                                         stmpe->regs[STMPE_IDX_GPEDR_LSB + i],
 417                                         status[i]);
 418                 }
 419         }
 420
 421         return IRQ_HANDLED;
 422 }
 423
 424 static int stmpe_gpio_probe(struct platform_device *pdev)
 425 {
 426         struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
 427         struct device_node *np = pdev->dev.of_node;
 428         struct stmpe_gpio *stmpe_gpio;
 429         int ret;
 430         int irq = 0;
 431
 432         irq = platform_get_irq(pdev, 0);
 433
 434         stmpe_gpio = kzalloc(sizeof(struct stmpe_gpio), GFP_KERNEL);
 435         if (!stmpe_gpio)
 436                 return -ENOMEM;
 437
 438         mutex_init(&stmpe_gpio->irq_lock);
 439
 440         stmpe_gpio->dev = &pdev->dev;
 441         stmpe_gpio->stmpe = stmpe;
 442         stmpe_gpio->chip = template_chip;
 443         stmpe_gpio->chip.ngpio = stmpe->num_gpios;
 444         stmpe_gpio->chip.parent = &pdev->dev;
 445         stmpe_gpio->chip.of_node = np;
 446         stmpe_gpio->chip.base = -1;
 447
 448         if (IS_ENABLED(CONFIG_DEBUG_FS))
 449                 stmpe_gpio->chip.dbg_show = stmpe_dbg_show;
 450
 451         of_property_read_u32(np, "st,norequest-mask",
 452                         &stmpe_gpio->norequest_mask);
 453         if (stmpe_gpio->norequest_mask)
 454                 stmpe_gpio->chip.irq_need_valid_mask = true;
 455
 456         if (irq < 0)
 457                 dev_info(&pdev->dev,
 458                         "device configured in no-irq mode: "
 459                         "irqs are not available\n");
 460
 461         ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
 462         if (ret)
 463                 goto out_free;
 464
 465         ret = gpiochip_add_data(&stmpe_gpio->chip, stmpe_gpio);
 466         if (ret) {
 467                 dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
 468                 goto out_disable;
 469         }
 470
 471         if (irq > 0) {
 472                 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
 473                                 stmpe_gpio_irq, IRQF_ONESHOT,
 474                                 "stmpe-gpio", stmpe_gpio);
 475                 if (ret) {
 476                         dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
 477                         goto out_disable;
 478                 }
 479                 if (stmpe_gpio->norequest_mask) {
 480                         int i;
 481
 482                         /* Forbid unused lines to be mapped as IRQs */
 483                         for (i = 0; i < sizeof(u32); i++)
 484                                 if (stmpe_gpio->norequest_mask & BIT(i))
 485                                         clear_bit(i, stmpe_gpio->chip.irq_valid_mask);
 486                 }
 487                 ret =  gpiochip_irqchip_add(&stmpe_gpio->chip,
 488                                             &stmpe_gpio_irq_chip,
 489                                             0,
 490                                             handle_simple_irq,
 491                                             IRQ_TYPE_NONE);
 492                 if (ret) {
 493                         dev_err(&pdev->dev,
 494                                 "could not connect irqchip to gpiochip\n");
 495                         goto out_disable;
 496                 }
 497
 498                 gpiochip_set_chained_irqchip(&stmpe_gpio->chip,
 499                                              &stmpe_gpio_irq_chip,
 500                                              irq,
 501                                              NULL);
 502         }
 503
 504         platform_set_drvdata(pdev, stmpe_gpio);
 505
 506         return 0;
 507
 508 out_disable:
 509         stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
 510         gpiochip_remove(&stmpe_gpio->chip);
 511 out_free:
 512         kfree(stmpe_gpio);
 513         return ret;
 514 }
 515
 516 static struct platform_driver stmpe_gpio_driver = {
 517         .driver = {
 518                 .suppress_bind_attrs    = true,
 519                 .name                   = "stmpe-gpio",
 520         },
 521         .probe          = stmpe_gpio_probe,
 522 };
 523
 524 static int __init stmpe_gpio_init(void)
 525 {
 526         return platform_driver_register(&stmpe_gpio_driver);
 527 }
 528 subsys_initcall(stmpe_gpio_init);