2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/kthread.h>
29 #include <linux/console.h>
30 #include <linux/slab.h>
31 #include <linux/debugfs.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/amdgpu_drm.h>
35 #include <linux/vgaarb.h>
36 #include <linux/vga_switcheroo.h>
37 #include <linux/efi.h>
39 #include "amdgpu_trace.h"
40 #include "amdgpu_i2c.h"
42 #include "amdgpu_atombios.h"
44 #ifdef CONFIG_DRM_AMDGPU_SI
47 #ifdef CONFIG_DRM_AMDGPU_CIK
51 #include "bif/bif_4_1_d.h"
52 #include <linux/pci.h>
54 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev);
55 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev);
57 static const char *amdgpu_asic_name[] = {
78 bool amdgpu_device_is_px(struct drm_device *dev)
80 struct amdgpu_device *adev = dev->dev_private;
82 if (adev->flags & AMD_IS_PX)
88 * MMIO register access helper functions.
90 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
95 if ((reg * 4) < adev->rmmio_size && !always_indirect)
96 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
100 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
101 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
102 ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
103 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
105 trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret);
109 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
110 bool always_indirect)
112 trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
114 if ((reg * 4) < adev->rmmio_size && !always_indirect)
115 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
119 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
120 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
121 writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
122 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
126 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
128 if ((reg * 4) < adev->rio_mem_size)
129 return ioread32(adev->rio_mem + (reg * 4));
131 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
132 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
136 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
139 if ((reg * 4) < adev->rio_mem_size)
140 iowrite32(v, adev->rio_mem + (reg * 4));
142 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
143 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
148 * amdgpu_mm_rdoorbell - read a doorbell dword
150 * @adev: amdgpu_device pointer
151 * @index: doorbell index
153 * Returns the value in the doorbell aperture at the
154 * requested doorbell index (CIK).
156 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
158 if (index < adev->doorbell.num_doorbells) {
159 return readl(adev->doorbell.ptr + index);
161 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
167 * amdgpu_mm_wdoorbell - write a doorbell dword
169 * @adev: amdgpu_device pointer
170 * @index: doorbell index
173 * Writes @v to the doorbell aperture at the
174 * requested doorbell index (CIK).
176 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
178 if (index < adev->doorbell.num_doorbells) {
179 writel(v, adev->doorbell.ptr + index);
181 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
186 * amdgpu_invalid_rreg - dummy reg read function
188 * @adev: amdgpu device pointer
189 * @reg: offset of register
191 * Dummy register read function. Used for register blocks
192 * that certain asics don't have (all asics).
193 * Returns the value in the register.
195 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
197 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
203 * amdgpu_invalid_wreg - dummy reg write function
205 * @adev: amdgpu device pointer
206 * @reg: offset of register
207 * @v: value to write to the register
209 * Dummy register read function. Used for register blocks
210 * that certain asics don't have (all asics).
212 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
214 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
220 * amdgpu_block_invalid_rreg - dummy reg read function
222 * @adev: amdgpu device pointer
223 * @block: offset of instance
224 * @reg: offset of register
226 * Dummy register read function. Used for register blocks
227 * that certain asics don't have (all asics).
228 * Returns the value in the register.
230 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
231 uint32_t block, uint32_t reg)
233 DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
240 * amdgpu_block_invalid_wreg - dummy reg write function
242 * @adev: amdgpu device pointer
243 * @block: offset of instance
244 * @reg: offset of register
245 * @v: value to write to the register
247 * Dummy register read function. Used for register blocks
248 * that certain asics don't have (all asics).
250 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
252 uint32_t reg, uint32_t v)
254 DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
259 static int amdgpu_vram_scratch_init(struct amdgpu_device *adev)
263 if (adev->vram_scratch.robj == NULL) {
264 r = amdgpu_bo_create(adev, AMDGPU_GPU_PAGE_SIZE,
265 PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM,
266 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
267 NULL, NULL, &adev->vram_scratch.robj);
273 r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
274 if (unlikely(r != 0))
276 r = amdgpu_bo_pin(adev->vram_scratch.robj,
277 AMDGPU_GEM_DOMAIN_VRAM, &adev->vram_scratch.gpu_addr);
279 amdgpu_bo_unreserve(adev->vram_scratch.robj);
282 r = amdgpu_bo_kmap(adev->vram_scratch.robj,
283 (void **)&adev->vram_scratch.ptr);
285 amdgpu_bo_unpin(adev->vram_scratch.robj);
286 amdgpu_bo_unreserve(adev->vram_scratch.robj);
291 static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev)
295 if (adev->vram_scratch.robj == NULL) {
298 r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
299 if (likely(r == 0)) {
300 amdgpu_bo_kunmap(adev->vram_scratch.robj);
301 amdgpu_bo_unpin(adev->vram_scratch.robj);
302 amdgpu_bo_unreserve(adev->vram_scratch.robj);
304 amdgpu_bo_unref(&adev->vram_scratch.robj);
308 * amdgpu_program_register_sequence - program an array of registers.
310 * @adev: amdgpu_device pointer
311 * @registers: pointer to the register array
312 * @array_size: size of the register array
314 * Programs an array or registers with and and or masks.
315 * This is a helper for setting golden registers.
317 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
318 const u32 *registers,
319 const u32 array_size)
321 u32 tmp, reg, and_mask, or_mask;
327 for (i = 0; i < array_size; i +=3) {
328 reg = registers[i + 0];
329 and_mask = registers[i + 1];
330 or_mask = registers[i + 2];
332 if (and_mask == 0xffffffff) {
343 void amdgpu_pci_config_reset(struct amdgpu_device *adev)
345 pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
349 * GPU doorbell aperture helpers function.
352 * amdgpu_doorbell_init - Init doorbell driver information.
354 * @adev: amdgpu_device pointer
356 * Init doorbell driver information (CIK)
357 * Returns 0 on success, error on failure.
359 static int amdgpu_doorbell_init(struct amdgpu_device *adev)
361 /* doorbell bar mapping */
362 adev->doorbell.base = pci_resource_start(adev->pdev, 2);
363 adev->doorbell.size = pci_resource_len(adev->pdev, 2);
365 adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
366 AMDGPU_DOORBELL_MAX_ASSIGNMENT+1);
367 if (adev->doorbell.num_doorbells == 0)
370 adev->doorbell.ptr = ioremap(adev->doorbell.base, adev->doorbell.num_doorbells * sizeof(u32));
371 if (adev->doorbell.ptr == NULL) {
374 DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)adev->doorbell.base);
375 DRM_INFO("doorbell mmio size: %u\n", (unsigned)adev->doorbell.size);
381 * amdgpu_doorbell_fini - Tear down doorbell driver information.
383 * @adev: amdgpu_device pointer
385 * Tear down doorbell driver information (CIK)
387 static void amdgpu_doorbell_fini(struct amdgpu_device *adev)
389 iounmap(adev->doorbell.ptr);
390 adev->doorbell.ptr = NULL;
394 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
397 * @adev: amdgpu_device pointer
398 * @aperture_base: output returning doorbell aperture base physical address
399 * @aperture_size: output returning doorbell aperture size in bytes
400 * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
402 * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
403 * takes doorbells required for its own rings and reports the setup to amdkfd.
404 * amdgpu reserved doorbells are at the start of the doorbell aperture.
406 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
407 phys_addr_t *aperture_base,
408 size_t *aperture_size,
409 size_t *start_offset)
412 * The first num_doorbells are used by amdgpu.
413 * amdkfd takes whatever's left in the aperture.
415 if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
416 *aperture_base = adev->doorbell.base;
417 *aperture_size = adev->doorbell.size;
418 *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
428 * Writeback is the the method by which the the GPU updates special pages
429 * in memory with the status of certain GPU events (fences, ring pointers,
434 * amdgpu_wb_fini - Disable Writeback and free memory
436 * @adev: amdgpu_device pointer
438 * Disables Writeback and frees the Writeback memory (all asics).
439 * Used at driver shutdown.
441 static void amdgpu_wb_fini(struct amdgpu_device *adev)
443 if (adev->wb.wb_obj) {
444 if (!amdgpu_bo_reserve(adev->wb.wb_obj, false)) {
445 amdgpu_bo_kunmap(adev->wb.wb_obj);
446 amdgpu_bo_unpin(adev->wb.wb_obj);
447 amdgpu_bo_unreserve(adev->wb.wb_obj);
449 amdgpu_bo_unref(&adev->wb.wb_obj);
451 adev->wb.wb_obj = NULL;
456 * amdgpu_wb_init- Init Writeback driver info and allocate memory
458 * @adev: amdgpu_device pointer
460 * Disables Writeback and frees the Writeback memory (all asics).
461 * Used at driver startup.
462 * Returns 0 on success or an -error on failure.
464 static int amdgpu_wb_init(struct amdgpu_device *adev)
468 if (adev->wb.wb_obj == NULL) {
469 r = amdgpu_bo_create(adev, AMDGPU_MAX_WB * 4, PAGE_SIZE, true,
470 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
473 dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
476 r = amdgpu_bo_reserve(adev->wb.wb_obj, false);
477 if (unlikely(r != 0)) {
478 amdgpu_wb_fini(adev);
481 r = amdgpu_bo_pin(adev->wb.wb_obj, AMDGPU_GEM_DOMAIN_GTT,
484 amdgpu_bo_unreserve(adev->wb.wb_obj);
485 dev_warn(adev->dev, "(%d) pin WB bo failed\n", r);
486 amdgpu_wb_fini(adev);
489 r = amdgpu_bo_kmap(adev->wb.wb_obj, (void **)&adev->wb.wb);
490 amdgpu_bo_unreserve(adev->wb.wb_obj);
492 dev_warn(adev->dev, "(%d) map WB bo failed\n", r);
493 amdgpu_wb_fini(adev);
497 adev->wb.num_wb = AMDGPU_MAX_WB;
498 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
500 /* clear wb memory */
501 memset((char *)adev->wb.wb, 0, AMDGPU_GPU_PAGE_SIZE);
508 * amdgpu_wb_get - Allocate a wb entry
510 * @adev: amdgpu_device pointer
513 * Allocate a wb slot for use by the driver (all asics).
514 * Returns 0 on success or -EINVAL on failure.
516 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb)
518 unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
519 if (offset < adev->wb.num_wb) {
520 __set_bit(offset, adev->wb.used);
529 * amdgpu_wb_free - Free a wb entry
531 * @adev: amdgpu_device pointer
534 * Free a wb slot allocated for use by the driver (all asics)
536 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb)
538 if (wb < adev->wb.num_wb)
539 __clear_bit(wb, adev->wb.used);
543 * amdgpu_vram_location - try to find VRAM location
544 * @adev: amdgpu device structure holding all necessary informations
545 * @mc: memory controller structure holding memory informations
546 * @base: base address at which to put VRAM
548 * Function will place try to place VRAM at base address provided
549 * as parameter (which is so far either PCI aperture address or
550 * for IGP TOM base address).
552 * If there is not enough space to fit the unvisible VRAM in the 32bits
553 * address space then we limit the VRAM size to the aperture.
555 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
556 * this shouldn't be a problem as we are using the PCI aperture as a reference.
557 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
560 * Note: we use mc_vram_size as on some board we need to program the mc to
561 * cover the whole aperture even if VRAM size is inferior to aperture size
562 * Novell bug 204882 + along with lots of ubuntu ones
564 * Note: when limiting vram it's safe to overwritte real_vram_size because
565 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
566 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
569 * Note: IGP TOM addr should be the same as the aperture addr, we don't
570 * explicitly check for that thought.
572 * FIXME: when reducing VRAM size align new size on power of 2.
574 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base)
576 uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
578 mc->vram_start = base;
579 if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) {
580 dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n");
581 mc->real_vram_size = mc->aper_size;
582 mc->mc_vram_size = mc->aper_size;
584 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
585 if (limit && limit < mc->real_vram_size)
586 mc->real_vram_size = limit;
587 dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
588 mc->mc_vram_size >> 20, mc->vram_start,
589 mc->vram_end, mc->real_vram_size >> 20);
593 * amdgpu_gtt_location - try to find GTT location
594 * @adev: amdgpu device structure holding all necessary informations
595 * @mc: memory controller structure holding memory informations
597 * Function will place try to place GTT before or after VRAM.
599 * If GTT size is bigger than space left then we ajust GTT size.
600 * Thus function will never fails.
602 * FIXME: when reducing GTT size align new size on power of 2.
604 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc)
606 u64 size_af, size_bf;
608 size_af = ((adev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
609 size_bf = mc->vram_start & ~mc->gtt_base_align;
610 if (size_bf > size_af) {
611 if (mc->gtt_size > size_bf) {
612 dev_warn(adev->dev, "limiting GTT\n");
613 mc->gtt_size = size_bf;
615 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
617 if (mc->gtt_size > size_af) {
618 dev_warn(adev->dev, "limiting GTT\n");
619 mc->gtt_size = size_af;
621 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
623 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
624 dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
625 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
629 * GPU helpers function.
632 * amdgpu_card_posted - check if the hw has already been initialized
634 * @adev: amdgpu_device pointer
636 * Check if the asic has been initialized (all asics).
637 * Used at driver startup.
638 * Returns true if initialized or false if not.
640 bool amdgpu_card_posted(struct amdgpu_device *adev)
644 /* then check MEM_SIZE, in case the crtcs are off */
645 reg = RREG32(mmCONFIG_MEMSIZE);
655 * amdgpu_dummy_page_init - init dummy page used by the driver
657 * @adev: amdgpu_device pointer
659 * Allocate the dummy page used by the driver (all asics).
660 * This dummy page is used by the driver as a filler for gart entries
661 * when pages are taken out of the GART
662 * Returns 0 on sucess, -ENOMEM on failure.
664 int amdgpu_dummy_page_init(struct amdgpu_device *adev)
666 if (adev->dummy_page.page)
668 adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
669 if (adev->dummy_page.page == NULL)
671 adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page,
672 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
673 if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) {
674 dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
675 __free_page(adev->dummy_page.page);
676 adev->dummy_page.page = NULL;
683 * amdgpu_dummy_page_fini - free dummy page used by the driver
685 * @adev: amdgpu_device pointer
687 * Frees the dummy page used by the driver (all asics).
689 void amdgpu_dummy_page_fini(struct amdgpu_device *adev)
691 if (adev->dummy_page.page == NULL)
693 pci_unmap_page(adev->pdev, adev->dummy_page.addr,
694 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
695 __free_page(adev->dummy_page.page);
696 adev->dummy_page.page = NULL;
700 /* ATOM accessor methods */
702 * ATOM is an interpreted byte code stored in tables in the vbios. The
703 * driver registers callbacks to access registers and the interpreter
704 * in the driver parses the tables and executes then to program specific
705 * actions (set display modes, asic init, etc.). See amdgpu_atombios.c,
706 * atombios.h, and atom.c
710 * cail_pll_read - read PLL register
712 * @info: atom card_info pointer
713 * @reg: PLL register offset
715 * Provides a PLL register accessor for the atom interpreter (r4xx+).
716 * Returns the value of the PLL register.
718 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
724 * cail_pll_write - write PLL register
726 * @info: atom card_info pointer
727 * @reg: PLL register offset
728 * @val: value to write to the pll register
730 * Provides a PLL register accessor for the atom interpreter (r4xx+).
732 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
738 * cail_mc_read - read MC (Memory Controller) register
740 * @info: atom card_info pointer
741 * @reg: MC register offset
743 * Provides an MC register accessor for the atom interpreter (r4xx+).
744 * Returns the value of the MC register.
746 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
752 * cail_mc_write - write MC (Memory Controller) register
754 * @info: atom card_info pointer
755 * @reg: MC register offset
756 * @val: value to write to the pll register
758 * Provides a MC register accessor for the atom interpreter (r4xx+).
760 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
766 * cail_reg_write - write MMIO register
768 * @info: atom card_info pointer
769 * @reg: MMIO register offset
770 * @val: value to write to the pll register
772 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
774 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
776 struct amdgpu_device *adev = info->dev->dev_private;
782 * cail_reg_read - read MMIO register
784 * @info: atom card_info pointer
785 * @reg: MMIO register offset
787 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
788 * Returns the value of the MMIO register.
790 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
792 struct amdgpu_device *adev = info->dev->dev_private;
800 * cail_ioreg_write - write IO register
802 * @info: atom card_info pointer
803 * @reg: IO register offset
804 * @val: value to write to the pll register
806 * Provides a IO register accessor for the atom interpreter (r4xx+).
808 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
810 struct amdgpu_device *adev = info->dev->dev_private;
816 * cail_ioreg_read - read IO register
818 * @info: atom card_info pointer
819 * @reg: IO register offset
821 * Provides an IO register accessor for the atom interpreter (r4xx+).
822 * Returns the value of the IO register.
824 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
826 struct amdgpu_device *adev = info->dev->dev_private;
834 * amdgpu_atombios_fini - free the driver info and callbacks for atombios
836 * @adev: amdgpu_device pointer
838 * Frees the driver info and register access callbacks for the ATOM
839 * interpreter (r4xx+).
840 * Called at driver shutdown.
842 static void amdgpu_atombios_fini(struct amdgpu_device *adev)
844 if (adev->mode_info.atom_context) {
845 kfree(adev->mode_info.atom_context->scratch);
846 kfree(adev->mode_info.atom_context->iio);
848 kfree(adev->mode_info.atom_context);
849 adev->mode_info.atom_context = NULL;
850 kfree(adev->mode_info.atom_card_info);
851 adev->mode_info.atom_card_info = NULL;
855 * amdgpu_atombios_init - init the driver info and callbacks for atombios
857 * @adev: amdgpu_device pointer
859 * Initializes the driver info and register access callbacks for the
860 * ATOM interpreter (r4xx+).
861 * Returns 0 on sucess, -ENOMEM on failure.
862 * Called at driver startup.
864 static int amdgpu_atombios_init(struct amdgpu_device *adev)
866 struct card_info *atom_card_info =
867 kzalloc(sizeof(struct card_info), GFP_KERNEL);
872 adev->mode_info.atom_card_info = atom_card_info;
873 atom_card_info->dev = adev->ddev;
874 atom_card_info->reg_read = cail_reg_read;
875 atom_card_info->reg_write = cail_reg_write;
876 /* needed for iio ops */
878 atom_card_info->ioreg_read = cail_ioreg_read;
879 atom_card_info->ioreg_write = cail_ioreg_write;
881 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
882 atom_card_info->ioreg_read = cail_reg_read;
883 atom_card_info->ioreg_write = cail_reg_write;
885 atom_card_info->mc_read = cail_mc_read;
886 atom_card_info->mc_write = cail_mc_write;
887 atom_card_info->pll_read = cail_pll_read;
888 atom_card_info->pll_write = cail_pll_write;
890 adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios);
891 if (!adev->mode_info.atom_context) {
892 amdgpu_atombios_fini(adev);
896 mutex_init(&adev->mode_info.atom_context->mutex);
897 amdgpu_atombios_scratch_regs_init(adev);
898 amdgpu_atom_allocate_fb_scratch(adev->mode_info.atom_context);
902 /* if we get transitioned to only one device, take VGA back */
904 * amdgpu_vga_set_decode - enable/disable vga decode
906 * @cookie: amdgpu_device pointer
907 * @state: enable/disable vga decode
909 * Enable/disable vga decode (all asics).
910 * Returns VGA resource flags.
912 static unsigned int amdgpu_vga_set_decode(void *cookie, bool state)
914 struct amdgpu_device *adev = cookie;
915 amdgpu_asic_set_vga_state(adev, state);
917 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
918 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
920 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
924 * amdgpu_check_pot_argument - check that argument is a power of two
926 * @arg: value to check
928 * Validates that a certain argument is a power of two (all asics).
929 * Returns true if argument is valid.
931 static bool amdgpu_check_pot_argument(int arg)
933 return (arg & (arg - 1)) == 0;
937 * amdgpu_check_arguments - validate module params
939 * @adev: amdgpu_device pointer
941 * Validates certain module parameters and updates
942 * the associated values used by the driver (all asics).
944 static void amdgpu_check_arguments(struct amdgpu_device *adev)
946 if (amdgpu_sched_jobs < 4) {
947 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
949 amdgpu_sched_jobs = 4;
950 } else if (!amdgpu_check_pot_argument(amdgpu_sched_jobs)){
951 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
953 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
956 if (amdgpu_gart_size != -1) {
957 /* gtt size must be greater or equal to 32M */
958 if (amdgpu_gart_size < 32) {
959 dev_warn(adev->dev, "gart size (%d) too small\n",
961 amdgpu_gart_size = -1;
965 if (!amdgpu_check_pot_argument(amdgpu_vm_size)) {
966 dev_warn(adev->dev, "VM size (%d) must be a power of 2\n",
971 if (amdgpu_vm_size < 1) {
972 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
978 * Max GPUVM size for Cayman, SI and CI are 40 bits.
980 if (amdgpu_vm_size > 1024) {
981 dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n",
986 /* defines number of bits in page table versus page directory,
987 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
988 * page table and the remaining bits are in the page directory */
989 if (amdgpu_vm_block_size == -1) {
991 /* Total bits covered by PD + PTs */
992 unsigned bits = ilog2(amdgpu_vm_size) + 18;
994 /* Make sure the PD is 4K in size up to 8GB address space.
995 Above that split equal between PD and PTs */
996 if (amdgpu_vm_size <= 8)
997 amdgpu_vm_block_size = bits - 9;
999 amdgpu_vm_block_size = (bits + 3) / 2;
1001 } else if (amdgpu_vm_block_size < 9) {
1002 dev_warn(adev->dev, "VM page table size (%d) too small\n",
1003 amdgpu_vm_block_size);
1004 amdgpu_vm_block_size = 9;
1007 if (amdgpu_vm_block_size > 24 ||
1008 (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) {
1009 dev_warn(adev->dev, "VM page table size (%d) too large\n",
1010 amdgpu_vm_block_size);
1011 amdgpu_vm_block_size = 9;
1016 * amdgpu_switcheroo_set_state - set switcheroo state
1018 * @pdev: pci dev pointer
1019 * @state: vga_switcheroo state
1021 * Callback for the switcheroo driver. Suspends or resumes the
1022 * the asics before or after it is powered up using ACPI methods.
1024 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1026 struct drm_device *dev = pci_get_drvdata(pdev);
1028 if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1031 if (state == VGA_SWITCHEROO_ON) {
1032 unsigned d3_delay = dev->pdev->d3_delay;
1034 printk(KERN_INFO "amdgpu: switched on\n");
1035 /* don't suspend or resume card normally */
1036 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1038 amdgpu_device_resume(dev, true, true);
1040 dev->pdev->d3_delay = d3_delay;
1042 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1043 drm_kms_helper_poll_enable(dev);
1045 printk(KERN_INFO "amdgpu: switched off\n");
1046 drm_kms_helper_poll_disable(dev);
1047 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1048 amdgpu_device_suspend(dev, true, true);
1049 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1054 * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1056 * @pdev: pci dev pointer
1058 * Callback for the switcheroo driver. Check of the switcheroo
1059 * state can be changed.
1060 * Returns true if the state can be changed, false if not.
1062 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1064 struct drm_device *dev = pci_get_drvdata(pdev);
1067 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1068 * locking inversion with the driver load path. And the access here is
1069 * completely racy anyway. So don't bother with locking for now.
1071 return dev->open_count == 0;
1074 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1075 .set_gpu_state = amdgpu_switcheroo_set_state,
1077 .can_switch = amdgpu_switcheroo_can_switch,
1080 int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
1081 enum amd_ip_block_type block_type,
1082 enum amd_clockgating_state state)
1086 for (i = 0; i < adev->num_ip_blocks; i++) {
1087 if (!adev->ip_block_status[i].valid)
1089 if (adev->ip_blocks[i].type == block_type) {
1090 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1100 int amdgpu_set_powergating_state(struct amdgpu_device *adev,
1101 enum amd_ip_block_type block_type,
1102 enum amd_powergating_state state)
1106 for (i = 0; i < adev->num_ip_blocks; i++) {
1107 if (!adev->ip_block_status[i].valid)
1109 if (adev->ip_blocks[i].type == block_type) {
1110 r = adev->ip_blocks[i].funcs->set_powergating_state((void *)adev,
1120 int amdgpu_wait_for_idle(struct amdgpu_device *adev,
1121 enum amd_ip_block_type block_type)
1125 for (i = 0; i < adev->num_ip_blocks; i++) {
1126 if (!adev->ip_block_status[i].valid)
1128 if (adev->ip_blocks[i].type == block_type) {
1129 r = adev->ip_blocks[i].funcs->wait_for_idle((void *)adev);
1139 bool amdgpu_is_idle(struct amdgpu_device *adev,
1140 enum amd_ip_block_type block_type)
1144 for (i = 0; i < adev->num_ip_blocks; i++) {
1145 if (!adev->ip_block_status[i].valid)
1147 if (adev->ip_blocks[i].type == block_type)
1148 return adev->ip_blocks[i].funcs->is_idle((void *)adev);
1154 const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
1155 struct amdgpu_device *adev,
1156 enum amd_ip_block_type type)
1160 for (i = 0; i < adev->num_ip_blocks; i++)
1161 if (adev->ip_blocks[i].type == type)
1162 return &adev->ip_blocks[i];
1168 * amdgpu_ip_block_version_cmp
1170 * @adev: amdgpu_device pointer
1171 * @type: enum amd_ip_block_type
1172 * @major: major version
1173 * @minor: minor version
1175 * return 0 if equal or greater
1176 * return 1 if smaller or the ip_block doesn't exist
1178 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
1179 enum amd_ip_block_type type,
1180 u32 major, u32 minor)
1182 const struct amdgpu_ip_block_version *ip_block;
1183 ip_block = amdgpu_get_ip_block(adev, type);
1185 if (ip_block && ((ip_block->major > major) ||
1186 ((ip_block->major == major) &&
1187 (ip_block->minor >= minor))))
1193 static void amdgpu_whether_enable_virtual_display(struct amdgpu_device *adev)
1195 adev->enable_virtual_display = false;
1197 if (amdgpu_virtual_display) {
1198 struct drm_device *ddev = adev->ddev;
1199 const char *pci_address_name = pci_name(ddev->pdev);
1200 char *pciaddstr, *pciaddstr_tmp, *pciaddname;
1202 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
1203 pciaddstr_tmp = pciaddstr;
1204 while ((pciaddname = strsep(&pciaddstr_tmp, ";"))) {
1205 if (!strcmp(pci_address_name, pciaddname)) {
1206 adev->enable_virtual_display = true;
1211 DRM_INFO("virtual display string:%s, %s:virtual_display:%d\n",
1212 amdgpu_virtual_display, pci_address_name,
1213 adev->enable_virtual_display);
1219 static int amdgpu_early_init(struct amdgpu_device *adev)
1223 amdgpu_whether_enable_virtual_display(adev);
1225 switch (adev->asic_type) {
1229 case CHIP_POLARIS11:
1230 case CHIP_POLARIS10:
1233 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
1234 adev->family = AMDGPU_FAMILY_CZ;
1236 adev->family = AMDGPU_FAMILY_VI;
1238 r = vi_set_ip_blocks(adev);
1242 #ifdef CONFIG_DRM_AMDGPU_SI
1248 adev->family = AMDGPU_FAMILY_SI;
1249 r = si_set_ip_blocks(adev);
1254 #ifdef CONFIG_DRM_AMDGPU_CIK
1260 if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
1261 adev->family = AMDGPU_FAMILY_CI;
1263 adev->family = AMDGPU_FAMILY_KV;
1265 r = cik_set_ip_blocks(adev);
1271 /* FIXME: not supported yet */
1275 adev->ip_block_status = kcalloc(adev->num_ip_blocks,
1276 sizeof(struct amdgpu_ip_block_status), GFP_KERNEL);
1277 if (adev->ip_block_status == NULL)
1280 if (adev->ip_blocks == NULL) {
1281 DRM_ERROR("No IP blocks found!\n");
1285 for (i = 0; i < adev->num_ip_blocks; i++) {
1286 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1287 DRM_ERROR("disabled ip block: %d\n", i);
1288 adev->ip_block_status[i].valid = false;
1290 if (adev->ip_blocks[i].funcs->early_init) {
1291 r = adev->ip_blocks[i].funcs->early_init((void *)adev);
1293 adev->ip_block_status[i].valid = false;
1295 DRM_ERROR("early_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1298 adev->ip_block_status[i].valid = true;
1301 adev->ip_block_status[i].valid = true;
1306 adev->cg_flags &= amdgpu_cg_mask;
1307 adev->pg_flags &= amdgpu_pg_mask;
1312 static int amdgpu_init(struct amdgpu_device *adev)
1316 for (i = 0; i < adev->num_ip_blocks; i++) {
1317 if (!adev->ip_block_status[i].valid)
1319 r = adev->ip_blocks[i].funcs->sw_init((void *)adev);
1321 DRM_ERROR("sw_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1324 adev->ip_block_status[i].sw = true;
1325 /* need to do gmc hw init early so we can allocate gpu mem */
1326 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
1327 r = amdgpu_vram_scratch_init(adev);
1329 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
1332 r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
1334 DRM_ERROR("hw_init %d failed %d\n", i, r);
1337 r = amdgpu_wb_init(adev);
1339 DRM_ERROR("amdgpu_wb_init failed %d\n", r);
1342 adev->ip_block_status[i].hw = true;
1346 for (i = 0; i < adev->num_ip_blocks; i++) {
1347 if (!adev->ip_block_status[i].sw)
1349 /* gmc hw init is done early */
1350 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC)
1352 r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
1354 DRM_ERROR("hw_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1357 adev->ip_block_status[i].hw = true;
1363 static int amdgpu_late_init(struct amdgpu_device *adev)
1367 for (i = 0; i < adev->num_ip_blocks; i++) {
1368 if (!adev->ip_block_status[i].valid)
1370 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_UVD ||
1371 adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_VCE)
1373 /* enable clockgating to save power */
1374 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1377 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1380 if (adev->ip_blocks[i].funcs->late_init) {
1381 r = adev->ip_blocks[i].funcs->late_init((void *)adev);
1383 DRM_ERROR("late_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1392 static int amdgpu_fini(struct amdgpu_device *adev)
1396 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1397 if (!adev->ip_block_status[i].hw)
1399 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
1400 amdgpu_wb_fini(adev);
1401 amdgpu_vram_scratch_fini(adev);
1403 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1404 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1405 AMD_CG_STATE_UNGATE);
1407 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1410 r = adev->ip_blocks[i].funcs->hw_fini((void *)adev);
1411 /* XXX handle errors */
1413 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1415 adev->ip_block_status[i].hw = false;
1418 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1419 if (!adev->ip_block_status[i].sw)
1421 r = adev->ip_blocks[i].funcs->sw_fini((void *)adev);
1422 /* XXX handle errors */
1424 DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1426 adev->ip_block_status[i].sw = false;
1427 adev->ip_block_status[i].valid = false;
1430 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1431 if (adev->ip_blocks[i].funcs->late_fini)
1432 adev->ip_blocks[i].funcs->late_fini((void *)adev);
1438 static int amdgpu_suspend(struct amdgpu_device *adev)
1442 /* ungate SMC block first */
1443 r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC,
1444 AMD_CG_STATE_UNGATE);
1446 DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r);
1449 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1450 if (!adev->ip_block_status[i].valid)
1452 /* ungate blocks so that suspend can properly shut them down */
1453 if (i != AMD_IP_BLOCK_TYPE_SMC) {
1454 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1455 AMD_CG_STATE_UNGATE);
1457 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1460 /* XXX handle errors */
1461 r = adev->ip_blocks[i].funcs->suspend(adev);
1462 /* XXX handle errors */
1464 DRM_ERROR("suspend of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1471 static int amdgpu_resume(struct amdgpu_device *adev)
1475 for (i = 0; i < adev->num_ip_blocks; i++) {
1476 if (!adev->ip_block_status[i].valid)
1478 r = adev->ip_blocks[i].funcs->resume(adev);
1480 DRM_ERROR("resume of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1488 static bool amdgpu_device_is_virtual(void)
1491 return boot_cpu_has(X86_FEATURE_HYPERVISOR);
1498 * amdgpu_device_init - initialize the driver
1500 * @adev: amdgpu_device pointer
1501 * @pdev: drm dev pointer
1502 * @pdev: pci dev pointer
1503 * @flags: driver flags
1505 * Initializes the driver info and hw (all asics).
1506 * Returns 0 for success or an error on failure.
1507 * Called at driver startup.
1509 int amdgpu_device_init(struct amdgpu_device *adev,
1510 struct drm_device *ddev,
1511 struct pci_dev *pdev,
1515 bool runtime = false;
1518 adev->shutdown = false;
1519 adev->dev = &pdev->dev;
1522 adev->flags = flags;
1523 adev->asic_type = flags & AMD_ASIC_MASK;
1524 adev->is_atom_bios = false;
1525 adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
1526 adev->mc.gtt_size = 512 * 1024 * 1024;
1527 adev->accel_working = false;
1528 adev->num_rings = 0;
1529 adev->mman.buffer_funcs = NULL;
1530 adev->mman.buffer_funcs_ring = NULL;
1531 adev->vm_manager.vm_pte_funcs = NULL;
1532 adev->vm_manager.vm_pte_num_rings = 0;
1533 adev->gart.gart_funcs = NULL;
1534 adev->fence_context = fence_context_alloc(AMDGPU_MAX_RINGS);
1536 adev->smc_rreg = &amdgpu_invalid_rreg;
1537 adev->smc_wreg = &amdgpu_invalid_wreg;
1538 adev->pcie_rreg = &amdgpu_invalid_rreg;
1539 adev->pcie_wreg = &amdgpu_invalid_wreg;
1540 adev->pciep_rreg = &amdgpu_invalid_rreg;
1541 adev->pciep_wreg = &amdgpu_invalid_wreg;
1542 adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
1543 adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
1544 adev->didt_rreg = &amdgpu_invalid_rreg;
1545 adev->didt_wreg = &amdgpu_invalid_wreg;
1546 adev->gc_cac_rreg = &amdgpu_invalid_rreg;
1547 adev->gc_cac_wreg = &amdgpu_invalid_wreg;
1548 adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
1549 adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
1552 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
1553 amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
1554 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
1556 /* mutex initialization are all done here so we
1557 * can recall function without having locking issues */
1558 mutex_init(&adev->vm_manager.lock);
1559 atomic_set(&adev->irq.ih.lock, 0);
1560 mutex_init(&adev->pm.mutex);
1561 mutex_init(&adev->gfx.gpu_clock_mutex);
1562 mutex_init(&adev->srbm_mutex);
1563 mutex_init(&adev->grbm_idx_mutex);
1564 mutex_init(&adev->mn_lock);
1565 hash_init(adev->mn_hash);
1567 amdgpu_check_arguments(adev);
1569 /* Registers mapping */
1570 /* TODO: block userspace mapping of io register */
1571 spin_lock_init(&adev->mmio_idx_lock);
1572 spin_lock_init(&adev->smc_idx_lock);
1573 spin_lock_init(&adev->pcie_idx_lock);
1574 spin_lock_init(&adev->uvd_ctx_idx_lock);
1575 spin_lock_init(&adev->didt_idx_lock);
1576 spin_lock_init(&adev->gc_cac_idx_lock);
1577 spin_lock_init(&adev->audio_endpt_idx_lock);
1578 spin_lock_init(&adev->mm_stats.lock);
1580 INIT_LIST_HEAD(&adev->shadow_list);
1581 mutex_init(&adev->shadow_list_lock);
1583 INIT_LIST_HEAD(&adev->gtt_list);
1584 spin_lock_init(&adev->gtt_list_lock);
1586 if (adev->asic_type >= CHIP_BONAIRE) {
1587 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
1588 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
1590 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
1591 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
1594 adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
1595 if (adev->rmmio == NULL) {
1598 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
1599 DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
1601 if (adev->asic_type >= CHIP_BONAIRE)
1602 /* doorbell bar mapping */
1603 amdgpu_doorbell_init(adev);
1605 /* io port mapping */
1606 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1607 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
1608 adev->rio_mem_size = pci_resource_len(adev->pdev, i);
1609 adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
1613 if (adev->rio_mem == NULL)
1614 DRM_ERROR("Unable to find PCI I/O BAR\n");
1616 /* early init functions */
1617 r = amdgpu_early_init(adev);
1621 /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
1622 /* this will fail for cards that aren't VGA class devices, just
1624 vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode);
1626 if (amdgpu_runtime_pm == 1)
1628 if (amdgpu_device_is_px(ddev))
1630 vga_switcheroo_register_client(adev->pdev, &amdgpu_switcheroo_ops, runtime);
1632 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
1635 if (!amdgpu_get_bios(adev)) {
1639 /* Must be an ATOMBIOS */
1640 if (!adev->is_atom_bios) {
1641 dev_err(adev->dev, "Expecting atombios for GPU\n");
1645 r = amdgpu_atombios_init(adev);
1647 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
1651 /* See if the asic supports SR-IOV */
1652 adev->virtualization.supports_sr_iov =
1653 amdgpu_atombios_has_gpu_virtualization_table(adev);
1655 /* Check if we are executing in a virtualized environment */
1656 adev->virtualization.is_virtual = amdgpu_device_is_virtual();
1657 adev->virtualization.caps = amdgpu_asic_get_virtual_caps(adev);
1659 /* Post card if necessary */
1660 if (!amdgpu_card_posted(adev) ||
1661 (adev->virtualization.is_virtual &&
1662 !(adev->virtualization.caps & AMDGPU_VIRT_CAPS_SRIOV_EN))) {
1664 dev_err(adev->dev, "Card not posted and no BIOS - ignoring\n");
1668 DRM_INFO("GPU not posted. posting now...\n");
1669 amdgpu_atom_asic_init(adev->mode_info.atom_context);
1672 /* Initialize clocks */
1673 r = amdgpu_atombios_get_clock_info(adev);
1675 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
1678 /* init i2c buses */
1679 amdgpu_atombios_i2c_init(adev);
1682 r = amdgpu_fence_driver_init(adev);
1684 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
1688 /* init the mode config */
1689 drm_mode_config_init(adev->ddev);
1691 r = amdgpu_init(adev);
1693 dev_err(adev->dev, "amdgpu_init failed\n");
1698 adev->accel_working = true;
1700 /* Initialize the buffer migration limit. */
1701 if (amdgpu_moverate >= 0)
1702 max_MBps = amdgpu_moverate;
1704 max_MBps = 8; /* Allow 8 MB/s. */
1705 /* Get a log2 for easy divisions. */
1706 adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
1708 amdgpu_fbdev_init(adev);
1710 r = amdgpu_ib_pool_init(adev);
1712 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
1716 r = amdgpu_ib_ring_tests(adev);
1718 DRM_ERROR("ib ring test failed (%d).\n", r);
1720 r = amdgpu_gem_debugfs_init(adev);
1722 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
1725 r = amdgpu_debugfs_regs_init(adev);
1727 DRM_ERROR("registering register debugfs failed (%d).\n", r);
1730 r = amdgpu_debugfs_firmware_init(adev);
1732 DRM_ERROR("registering firmware debugfs failed (%d).\n", r);
1736 if ((amdgpu_testing & 1)) {
1737 if (adev->accel_working)
1738 amdgpu_test_moves(adev);
1740 DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
1742 if ((amdgpu_testing & 2)) {
1743 if (adev->accel_working)
1744 amdgpu_test_syncing(adev);
1746 DRM_INFO("amdgpu: acceleration disabled, skipping sync tests\n");
1748 if (amdgpu_benchmarking) {
1749 if (adev->accel_working)
1750 amdgpu_benchmark(adev, amdgpu_benchmarking);
1752 DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
1755 /* enable clockgating, etc. after ib tests, etc. since some blocks require
1756 * explicit gating rather than handling it automatically.
1758 r = amdgpu_late_init(adev);
1760 dev_err(adev->dev, "amdgpu_late_init failed\n");
1768 vga_switcheroo_fini_domain_pm_ops(adev->dev);
1772 static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev);
1775 * amdgpu_device_fini - tear down the driver
1777 * @adev: amdgpu_device pointer
1779 * Tear down the driver info (all asics).
1780 * Called at driver shutdown.
1782 void amdgpu_device_fini(struct amdgpu_device *adev)
1786 DRM_INFO("amdgpu: finishing device.\n");
1787 adev->shutdown = true;
1788 /* evict vram memory */
1789 amdgpu_bo_evict_vram(adev);
1790 amdgpu_ib_pool_fini(adev);
1791 amdgpu_fence_driver_fini(adev);
1792 drm_crtc_force_disable_all(adev->ddev);
1793 amdgpu_fbdev_fini(adev);
1794 r = amdgpu_fini(adev);
1795 kfree(adev->ip_block_status);
1796 adev->ip_block_status = NULL;
1797 adev->accel_working = false;
1798 /* free i2c buses */
1799 amdgpu_i2c_fini(adev);
1800 amdgpu_atombios_fini(adev);
1803 vga_switcheroo_unregister_client(adev->pdev);
1804 if (adev->flags & AMD_IS_PX)
1805 vga_switcheroo_fini_domain_pm_ops(adev->dev);
1806 vga_client_register(adev->pdev, NULL, NULL, NULL);
1808 pci_iounmap(adev->pdev, adev->rio_mem);
1809 adev->rio_mem = NULL;
1810 iounmap(adev->rmmio);
1812 if (adev->asic_type >= CHIP_BONAIRE)
1813 amdgpu_doorbell_fini(adev);
1814 amdgpu_debugfs_regs_cleanup(adev);
1815 amdgpu_debugfs_remove_files(adev);
1823 * amdgpu_device_suspend - initiate device suspend
1825 * @pdev: drm dev pointer
1826 * @state: suspend state
1828 * Puts the hw in the suspend state (all asics).
1829 * Returns 0 for success or an error on failure.
1830 * Called at driver suspend.
1832 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
1834 struct amdgpu_device *adev;
1835 struct drm_crtc *crtc;
1836 struct drm_connector *connector;
1839 if (dev == NULL || dev->dev_private == NULL) {
1843 adev = dev->dev_private;
1845 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
1846 dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
1849 drm_kms_helper_poll_disable(dev);
1851 /* turn off display hw */
1852 drm_modeset_lock_all(dev);
1853 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1854 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
1856 drm_modeset_unlock_all(dev);
1858 /* unpin the front buffers and cursors */
1859 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1860 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1861 struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb);
1862 struct amdgpu_bo *robj;
1864 if (amdgpu_crtc->cursor_bo) {
1865 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1866 r = amdgpu_bo_reserve(aobj, false);
1868 amdgpu_bo_unpin(aobj);
1869 amdgpu_bo_unreserve(aobj);
1873 if (rfb == NULL || rfb->obj == NULL) {
1876 robj = gem_to_amdgpu_bo(rfb->obj);
1877 /* don't unpin kernel fb objects */
1878 if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
1879 r = amdgpu_bo_reserve(robj, false);
1881 amdgpu_bo_unpin(robj);
1882 amdgpu_bo_unreserve(robj);
1886 /* evict vram memory */
1887 amdgpu_bo_evict_vram(adev);
1889 amdgpu_fence_driver_suspend(adev);
1891 r = amdgpu_suspend(adev);
1893 /* evict remaining vram memory */
1894 amdgpu_bo_evict_vram(adev);
1896 pci_save_state(dev->pdev);
1898 /* Shut down the device */
1899 pci_disable_device(dev->pdev);
1900 pci_set_power_state(dev->pdev, PCI_D3hot);
1902 r = amdgpu_asic_reset(adev);
1904 DRM_ERROR("amdgpu asic reset failed\n");
1909 amdgpu_fbdev_set_suspend(adev, 1);
1916 * amdgpu_device_resume - initiate device resume
1918 * @pdev: drm dev pointer
1920 * Bring the hw back to operating state (all asics).
1921 * Returns 0 for success or an error on failure.
1922 * Called at driver resume.
1924 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
1926 struct drm_connector *connector;
1927 struct amdgpu_device *adev = dev->dev_private;
1928 struct drm_crtc *crtc;
1931 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
1932 dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
1939 pci_set_power_state(dev->pdev, PCI_D0);
1940 pci_restore_state(dev->pdev);
1941 r = pci_enable_device(dev->pdev);
1950 if (!amdgpu_card_posted(adev) || !resume) {
1951 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
1953 DRM_ERROR("amdgpu asic init failed\n");
1956 r = amdgpu_resume(adev);
1958 DRM_ERROR("amdgpu_resume failed (%d).\n", r);
1960 amdgpu_fence_driver_resume(adev);
1963 r = amdgpu_ib_ring_tests(adev);
1965 DRM_ERROR("ib ring test failed (%d).\n", r);
1968 r = amdgpu_late_init(adev);
1973 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1974 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1976 if (amdgpu_crtc->cursor_bo) {
1977 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1978 r = amdgpu_bo_reserve(aobj, false);
1980 r = amdgpu_bo_pin(aobj,
1981 AMDGPU_GEM_DOMAIN_VRAM,
1982 &amdgpu_crtc->cursor_addr);
1984 DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
1985 amdgpu_bo_unreserve(aobj);
1990 /* blat the mode back in */
1992 drm_helper_resume_force_mode(dev);
1993 /* turn on display hw */
1994 drm_modeset_lock_all(dev);
1995 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1996 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
1998 drm_modeset_unlock_all(dev);
2001 drm_kms_helper_poll_enable(dev);
2004 * Most of the connector probing functions try to acquire runtime pm
2005 * refs to ensure that the GPU is powered on when connector polling is
2006 * performed. Since we're calling this from a runtime PM callback,
2007 * trying to acquire rpm refs will cause us to deadlock.
2009 * Since we're guaranteed to be holding the rpm lock, it's safe to
2010 * temporarily disable the rpm helpers so this doesn't deadlock us.
2013 dev->dev->power.disable_depth++;
2015 drm_helper_hpd_irq_event(dev);
2017 dev->dev->power.disable_depth--;
2021 amdgpu_fbdev_set_suspend(adev, 0);
2028 static bool amdgpu_check_soft_reset(struct amdgpu_device *adev)
2031 bool asic_hang = false;
2033 for (i = 0; i < adev->num_ip_blocks; i++) {
2034 if (!adev->ip_block_status[i].valid)
2036 if (adev->ip_blocks[i].funcs->check_soft_reset)
2037 adev->ip_blocks[i].funcs->check_soft_reset(adev);
2038 if (adev->ip_block_status[i].hang) {
2039 DRM_INFO("IP block:%d is hang!\n", i);
2046 int amdgpu_pre_soft_reset(struct amdgpu_device *adev)
2050 for (i = 0; i < adev->num_ip_blocks; i++) {
2051 if (!adev->ip_block_status[i].valid)
2053 if (adev->ip_block_status[i].hang &&
2054 adev->ip_blocks[i].funcs->pre_soft_reset) {
2055 r = adev->ip_blocks[i].funcs->pre_soft_reset(adev);
2064 static bool amdgpu_need_full_reset(struct amdgpu_device *adev)
2066 if (adev->ip_block_status[AMD_IP_BLOCK_TYPE_GMC].hang ||
2067 adev->ip_block_status[AMD_IP_BLOCK_TYPE_SMC].hang ||
2068 adev->ip_block_status[AMD_IP_BLOCK_TYPE_ACP].hang ||
2069 adev->ip_block_status[AMD_IP_BLOCK_TYPE_DCE].hang) {
2070 DRM_INFO("Some block need full reset!\n");
2076 static int amdgpu_soft_reset(struct amdgpu_device *adev)
2080 for (i = 0; i < adev->num_ip_blocks; i++) {
2081 if (!adev->ip_block_status[i].valid)
2083 if (adev->ip_block_status[i].hang &&
2084 adev->ip_blocks[i].funcs->soft_reset) {
2085 r = adev->ip_blocks[i].funcs->soft_reset(adev);
2094 static int amdgpu_post_soft_reset(struct amdgpu_device *adev)
2098 for (i = 0; i < adev->num_ip_blocks; i++) {
2099 if (!adev->ip_block_status[i].valid)
2101 if (adev->ip_block_status[i].hang &&
2102 adev->ip_blocks[i].funcs->post_soft_reset)
2103 r = adev->ip_blocks[i].funcs->post_soft_reset(adev);
2111 bool amdgpu_need_backup(struct amdgpu_device *adev)
2113 if (adev->flags & AMD_IS_APU)
2116 return amdgpu_lockup_timeout > 0 ? true : false;
2119 static int amdgpu_recover_vram_from_shadow(struct amdgpu_device *adev,
2120 struct amdgpu_ring *ring,
2121 struct amdgpu_bo *bo,
2122 struct fence **fence)
2130 r = amdgpu_bo_reserve(bo, false);
2133 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
2134 /* if bo has been evicted, then no need to recover */
2135 if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
2136 r = amdgpu_bo_restore_from_shadow(adev, ring, bo,
2139 DRM_ERROR("recover page table failed!\n");
2144 amdgpu_bo_unreserve(bo);
2149 * amdgpu_gpu_reset - reset the asic
2151 * @adev: amdgpu device pointer
2153 * Attempt the reset the GPU if it has hung (all asics).
2154 * Returns 0 for success or an error on failure.
2156 int amdgpu_gpu_reset(struct amdgpu_device *adev)
2160 bool need_full_reset;
2162 if (!amdgpu_check_soft_reset(adev)) {
2163 DRM_INFO("No hardware hang detected. Did some blocks stall?\n");
2167 atomic_inc(&adev->gpu_reset_counter);
2170 resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
2172 /* block scheduler */
2173 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2174 struct amdgpu_ring *ring = adev->rings[i];
2178 kthread_park(ring->sched.thread);
2179 amd_sched_hw_job_reset(&ring->sched);
2181 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
2182 amdgpu_fence_driver_force_completion(adev);
2184 need_full_reset = amdgpu_need_full_reset(adev);
2186 if (!need_full_reset) {
2187 amdgpu_pre_soft_reset(adev);
2188 r = amdgpu_soft_reset(adev);
2189 amdgpu_post_soft_reset(adev);
2190 if (r || amdgpu_check_soft_reset(adev)) {
2191 DRM_INFO("soft reset failed, will fallback to full reset!\n");
2192 need_full_reset = true;
2196 if (need_full_reset) {
2198 amdgpu_atombios_scratch_regs_save(adev);
2199 r = amdgpu_suspend(adev);
2202 /* Disable fb access */
2203 if (adev->mode_info.num_crtc) {
2204 struct amdgpu_mode_mc_save save;
2205 amdgpu_display_stop_mc_access(adev, &save);
2206 amdgpu_wait_for_idle(adev, AMD_IP_BLOCK_TYPE_GMC);
2209 r = amdgpu_asic_reset(adev);
2211 amdgpu_atom_asic_init(adev->mode_info.atom_context);
2214 dev_info(adev->dev, "GPU reset succeeded, trying to resume\n");
2215 r = amdgpu_resume(adev);
2217 /* restore scratch */
2218 amdgpu_atombios_scratch_regs_restore(adev);
2221 amdgpu_irq_gpu_reset_resume_helper(adev);
2222 if (need_full_reset && amdgpu_need_backup(adev)) {
2223 r = amdgpu_ttm_recover_gart(adev);
2225 DRM_ERROR("gart recovery failed!!!\n");
2227 r = amdgpu_ib_ring_tests(adev);
2229 dev_err(adev->dev, "ib ring test failed (%d).\n", r);
2230 r = amdgpu_suspend(adev);
2231 need_full_reset = true;
2235 * recovery vm page tables, since we cannot depend on VRAM is
2236 * consistent after gpu full reset.
2238 if (need_full_reset && amdgpu_need_backup(adev)) {
2239 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2240 struct amdgpu_bo *bo, *tmp;
2241 struct fence *fence = NULL, *next = NULL;
2243 DRM_INFO("recover vram bo from shadow\n");
2244 mutex_lock(&adev->shadow_list_lock);
2245 list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) {
2246 amdgpu_recover_vram_from_shadow(adev, ring, bo, &next);
2248 r = fence_wait(fence, false);
2250 WARN(r, "recovery from shadow isn't comleted\n");
2258 mutex_unlock(&adev->shadow_list_lock);
2260 r = fence_wait(fence, false);
2262 WARN(r, "recovery from shadow isn't comleted\n");
2266 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2267 struct amdgpu_ring *ring = adev->rings[i];
2271 amd_sched_job_recovery(&ring->sched);
2272 kthread_unpark(ring->sched.thread);
2275 dev_err(adev->dev, "asic resume failed (%d).\n", r);
2276 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2277 if (adev->rings[i]) {
2278 kthread_unpark(adev->rings[i]->sched.thread);
2283 drm_helper_resume_force_mode(adev->ddev);
2285 ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
2287 /* bad news, how to tell it to userspace ? */
2288 dev_info(adev->dev, "GPU reset failed\n");
2294 void amdgpu_get_pcie_info(struct amdgpu_device *adev)
2299 if (amdgpu_pcie_gen_cap)
2300 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
2302 if (amdgpu_pcie_lane_cap)
2303 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
2305 /* covers APUs as well */
2306 if (pci_is_root_bus(adev->pdev->bus)) {
2307 if (adev->pm.pcie_gen_mask == 0)
2308 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
2309 if (adev->pm.pcie_mlw_mask == 0)
2310 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
2314 if (adev->pm.pcie_gen_mask == 0) {
2315 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
2317 adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
2318 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
2319 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
2321 if (mask & DRM_PCIE_SPEED_25)
2322 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
2323 if (mask & DRM_PCIE_SPEED_50)
2324 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;
2325 if (mask & DRM_PCIE_SPEED_80)
2326 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;
2328 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
2331 if (adev->pm.pcie_mlw_mask == 0) {
2332 ret = drm_pcie_get_max_link_width(adev->ddev, &mask);
2336 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
2337 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
2338 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2339 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2340 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2341 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2342 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2345 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
2346 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2347 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2348 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2349 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2350 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2353 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2354 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2355 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2356 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2357 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2360 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2361 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2362 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2363 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2366 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2367 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2368 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2371 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2372 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2375 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
2381 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
2389 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
2390 const struct drm_info_list *files,
2395 for (i = 0; i < adev->debugfs_count; i++) {
2396 if (adev->debugfs[i].files == files) {
2397 /* Already registered */
2402 i = adev->debugfs_count + 1;
2403 if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) {
2404 DRM_ERROR("Reached maximum number of debugfs components.\n");
2405 DRM_ERROR("Report so we increase "
2406 "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n");
2409 adev->debugfs[adev->debugfs_count].files = files;
2410 adev->debugfs[adev->debugfs_count].num_files = nfiles;
2411 adev->debugfs_count = i;
2412 #if defined(CONFIG_DEBUG_FS)
2413 drm_debugfs_create_files(files, nfiles,
2414 adev->ddev->control->debugfs_root,
2415 adev->ddev->control);
2416 drm_debugfs_create_files(files, nfiles,
2417 adev->ddev->primary->debugfs_root,
2418 adev->ddev->primary);
2423 static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev)
2425 #if defined(CONFIG_DEBUG_FS)
2428 for (i = 0; i < adev->debugfs_count; i++) {
2429 drm_debugfs_remove_files(adev->debugfs[i].files,
2430 adev->debugfs[i].num_files,
2431 adev->ddev->control);
2432 drm_debugfs_remove_files(adev->debugfs[i].files,
2433 adev->debugfs[i].num_files,
2434 adev->ddev->primary);
2439 #if defined(CONFIG_DEBUG_FS)
2441 static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
2442 size_t size, loff_t *pos)
2444 struct amdgpu_device *adev = f->f_inode->i_private;
2447 bool pm_pg_lock, use_bank;
2448 unsigned instance_bank, sh_bank, se_bank;
2450 if (size & 0x3 || *pos & 0x3)
2453 /* are we reading registers for which a PG lock is necessary? */
2454 pm_pg_lock = (*pos >> 23) & 1;
2456 if (*pos & (1ULL << 62)) {
2457 se_bank = (*pos >> 24) & 0x3FF;
2458 sh_bank = (*pos >> 34) & 0x3FF;
2459 instance_bank = (*pos >> 44) & 0x3FF;
2468 if (sh_bank >= adev->gfx.config.max_sh_per_se ||
2469 se_bank >= adev->gfx.config.max_shader_engines)
2471 mutex_lock(&adev->grbm_idx_mutex);
2472 amdgpu_gfx_select_se_sh(adev, se_bank,
2473 sh_bank, instance_bank);
2477 mutex_lock(&adev->pm.mutex);
2482 if (*pos > adev->rmmio_size)
2485 value = RREG32(*pos >> 2);
2486 r = put_user(value, (uint32_t *)buf);
2500 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2501 mutex_unlock(&adev->grbm_idx_mutex);
2505 mutex_unlock(&adev->pm.mutex);
2510 static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
2511 size_t size, loff_t *pos)
2513 struct amdgpu_device *adev = f->f_inode->i_private;
2517 if (size & 0x3 || *pos & 0x3)
2523 if (*pos > adev->rmmio_size)
2526 r = get_user(value, (uint32_t *)buf);
2530 WREG32(*pos >> 2, value);
2541 static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf,
2542 size_t size, loff_t *pos)
2544 struct amdgpu_device *adev = f->f_inode->i_private;
2548 if (size & 0x3 || *pos & 0x3)
2554 value = RREG32_PCIE(*pos >> 2);
2555 r = put_user(value, (uint32_t *)buf);
2568 static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf,
2569 size_t size, loff_t *pos)
2571 struct amdgpu_device *adev = f->f_inode->i_private;
2575 if (size & 0x3 || *pos & 0x3)
2581 r = get_user(value, (uint32_t *)buf);
2585 WREG32_PCIE(*pos >> 2, value);
2596 static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf,
2597 size_t size, loff_t *pos)
2599 struct amdgpu_device *adev = f->f_inode->i_private;
2603 if (size & 0x3 || *pos & 0x3)
2609 value = RREG32_DIDT(*pos >> 2);
2610 r = put_user(value, (uint32_t *)buf);
2623 static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf,
2624 size_t size, loff_t *pos)
2626 struct amdgpu_device *adev = f->f_inode->i_private;
2630 if (size & 0x3 || *pos & 0x3)
2636 r = get_user(value, (uint32_t *)buf);
2640 WREG32_DIDT(*pos >> 2, value);
2651 static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf,
2652 size_t size, loff_t *pos)
2654 struct amdgpu_device *adev = f->f_inode->i_private;
2658 if (size & 0x3 || *pos & 0x3)
2664 value = RREG32_SMC(*pos);
2665 r = put_user(value, (uint32_t *)buf);
2678 static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf,
2679 size_t size, loff_t *pos)
2681 struct amdgpu_device *adev = f->f_inode->i_private;
2685 if (size & 0x3 || *pos & 0x3)
2691 r = get_user(value, (uint32_t *)buf);
2695 WREG32_SMC(*pos, value);
2706 static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf,
2707 size_t size, loff_t *pos)
2709 struct amdgpu_device *adev = f->f_inode->i_private;
2712 uint32_t *config, no_regs = 0;
2714 if (size & 0x3 || *pos & 0x3)
2717 config = kmalloc(256 * sizeof(*config), GFP_KERNEL);
2721 /* version, increment each time something is added */
2722 config[no_regs++] = 2;
2723 config[no_regs++] = adev->gfx.config.max_shader_engines;
2724 config[no_regs++] = adev->gfx.config.max_tile_pipes;
2725 config[no_regs++] = adev->gfx.config.max_cu_per_sh;
2726 config[no_regs++] = adev->gfx.config.max_sh_per_se;
2727 config[no_regs++] = adev->gfx.config.max_backends_per_se;
2728 config[no_regs++] = adev->gfx.config.max_texture_channel_caches;
2729 config[no_regs++] = adev->gfx.config.max_gprs;
2730 config[no_regs++] = adev->gfx.config.max_gs_threads;
2731 config[no_regs++] = adev->gfx.config.max_hw_contexts;
2732 config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend;
2733 config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend;
2734 config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size;
2735 config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size;
2736 config[no_regs++] = adev->gfx.config.num_tile_pipes;
2737 config[no_regs++] = adev->gfx.config.backend_enable_mask;
2738 config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes;
2739 config[no_regs++] = adev->gfx.config.mem_row_size_in_kb;
2740 config[no_regs++] = adev->gfx.config.shader_engine_tile_size;
2741 config[no_regs++] = adev->gfx.config.num_gpus;
2742 config[no_regs++] = adev->gfx.config.multi_gpu_tile_size;
2743 config[no_regs++] = adev->gfx.config.mc_arb_ramcfg;
2744 config[no_regs++] = adev->gfx.config.gb_addr_config;
2745 config[no_regs++] = adev->gfx.config.num_rbs;
2748 config[no_regs++] = adev->rev_id;
2749 config[no_regs++] = adev->pg_flags;
2750 config[no_regs++] = adev->cg_flags;
2753 config[no_regs++] = adev->family;
2754 config[no_regs++] = adev->external_rev_id;
2756 while (size && (*pos < no_regs * 4)) {
2759 value = config[*pos >> 2];
2760 r = put_user(value, (uint32_t *)buf);
2777 static const struct file_operations amdgpu_debugfs_regs_fops = {
2778 .owner = THIS_MODULE,
2779 .read = amdgpu_debugfs_regs_read,
2780 .write = amdgpu_debugfs_regs_write,
2781 .llseek = default_llseek
2783 static const struct file_operations amdgpu_debugfs_regs_didt_fops = {
2784 .owner = THIS_MODULE,
2785 .read = amdgpu_debugfs_regs_didt_read,
2786 .write = amdgpu_debugfs_regs_didt_write,
2787 .llseek = default_llseek
2789 static const struct file_operations amdgpu_debugfs_regs_pcie_fops = {
2790 .owner = THIS_MODULE,
2791 .read = amdgpu_debugfs_regs_pcie_read,
2792 .write = amdgpu_debugfs_regs_pcie_write,
2793 .llseek = default_llseek
2795 static const struct file_operations amdgpu_debugfs_regs_smc_fops = {
2796 .owner = THIS_MODULE,
2797 .read = amdgpu_debugfs_regs_smc_read,
2798 .write = amdgpu_debugfs_regs_smc_write,
2799 .llseek = default_llseek
2802 static const struct file_operations amdgpu_debugfs_gca_config_fops = {
2803 .owner = THIS_MODULE,
2804 .read = amdgpu_debugfs_gca_config_read,
2805 .llseek = default_llseek
2808 static const struct file_operations *debugfs_regs[] = {
2809 &amdgpu_debugfs_regs_fops,
2810 &amdgpu_debugfs_regs_didt_fops,
2811 &amdgpu_debugfs_regs_pcie_fops,
2812 &amdgpu_debugfs_regs_smc_fops,
2813 &amdgpu_debugfs_gca_config_fops,
2816 static const char *debugfs_regs_names[] = {
2821 "amdgpu_gca_config",
2824 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
2826 struct drm_minor *minor = adev->ddev->primary;
2827 struct dentry *ent, *root = minor->debugfs_root;
2830 for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
2831 ent = debugfs_create_file(debugfs_regs_names[i],
2832 S_IFREG | S_IRUGO, root,
2833 adev, debugfs_regs[i]);
2835 for (j = 0; j < i; j++) {
2836 debugfs_remove(adev->debugfs_regs[i]);
2837 adev->debugfs_regs[i] = NULL;
2839 return PTR_ERR(ent);
2843 i_size_write(ent->d_inode, adev->rmmio_size);
2844 adev->debugfs_regs[i] = ent;
2850 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev)
2854 for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
2855 if (adev->debugfs_regs[i]) {
2856 debugfs_remove(adev->debugfs_regs[i]);
2857 adev->debugfs_regs[i] = NULL;
2862 int amdgpu_debugfs_init(struct drm_minor *minor)
2867 void amdgpu_debugfs_cleanup(struct drm_minor *minor)
2871 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
2875 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { }