drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/console.h>
  29 #include <linux/slab.h>
  30 #include <linux/debugfs.h>
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc_helper.h>
  33 #include <drm/amdgpu_drm.h>
  34 #include <linux/vgaarb.h>
  35 #include <linux/vga_switcheroo.h>
  36 #include <linux/efi.h>
  37 #include "amdgpu.h"
  38 #include "amdgpu_i2c.h"
  39 #include "atom.h"
  40 #include "amdgpu_atombios.h"
  41 #include "amd_pcie.h"
  42 #ifdef CONFIG_DRM_AMDGPU_CIK
  43 #include "cik.h"
  44 #endif
  45 #include "vi.h"
  46 #include "bif/bif_4_1_d.h"
  47
  48 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev);
  49 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev);
  50
  51 static const char *amdgpu_asic_name[] = {
  52         "BONAIRE",
  53         "KAVERI",
  54         "KABINI",
  55         "HAWAII",
  56         "MULLINS",
  57         "TOPAZ",
  58         "TONGA",
  59         "FIJI",
  60         "CARRIZO",
  61         "STONEY",
  62         "LAST",
  63 };
  64
  65 bool amdgpu_device_is_px(struct drm_device *dev)
  66 {
  67         struct amdgpu_device *adev = dev->dev_private;
  68
  69         if (adev->flags & AMD_IS_PX)
  70                 return true;
  71         return false;
  72 }
  73
  74 /*
  75  * MMIO register access helper functions.
  76  */
  77 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
  78                         bool always_indirect)
  79 {
  80         if ((reg * 4) < adev->rmmio_size && !always_indirect)
  81                 return readl(((void __iomem *)adev->rmmio) + (reg * 4));
  82         else {
  83                 unsigned long flags;
  84                 uint32_t ret;
  85
  86                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
  87                 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
  88                 ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
  89                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
  90
  91                 return ret;
  92         }
  93 }
  94
  95 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
  96                     bool always_indirect)
  97 {
  98         if ((reg * 4) < adev->rmmio_size && !always_indirect)
  99                 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
 100         else {
 101                 unsigned long flags;
 102
 103                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
 104                 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
 105                 writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
 106                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
 107         }
 108 }
 109
 110 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
 111 {
 112         if ((reg * 4) < adev->rio_mem_size)
 113                 return ioread32(adev->rio_mem + (reg * 4));
 114         else {
 115                 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
 116                 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
 117         }
 118 }
 119
 120 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 121 {
 122
 123         if ((reg * 4) < adev->rio_mem_size)
 124                 iowrite32(v, adev->rio_mem + (reg * 4));
 125         else {
 126                 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
 127                 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
 128         }
 129 }
 130
 131 /**
 132  * amdgpu_mm_rdoorbell - read a doorbell dword
 133  *
 134  * @adev: amdgpu_device pointer
 135  * @index: doorbell index
 136  *
 137  * Returns the value in the doorbell aperture at the
 138  * requested doorbell index (CIK).
 139  */
 140 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
 141 {
 142         if (index < adev->doorbell.num_doorbells) {
 143                 return readl(adev->doorbell.ptr + index);
 144         } else {
 145                 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
 146                 return 0;
 147         }
 148 }
 149
 150 /**
 151  * amdgpu_mm_wdoorbell - write a doorbell dword
 152  *
 153  * @adev: amdgpu_device pointer
 154  * @index: doorbell index
 155  * @v: value to write
 156  *
 157  * Writes @v to the doorbell aperture at the
 158  * requested doorbell index (CIK).
 159  */
 160 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
 161 {
 162         if (index < adev->doorbell.num_doorbells) {
 163                 writel(v, adev->doorbell.ptr + index);
 164         } else {
 165                 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
 166         }
 167 }
 168
 169 /**
 170  * amdgpu_invalid_rreg - dummy reg read function
 171  *
 172  * @adev: amdgpu device pointer
 173  * @reg: offset of register
 174  *
 175  * Dummy register read function.  Used for register blocks
 176  * that certain asics don't have (all asics).
 177  * Returns the value in the register.
 178  */
 179 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
 180 {
 181         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
 182         BUG();
 183         return 0;
 184 }
 185
 186 /**
 187  * amdgpu_invalid_wreg - dummy reg write function
 188  *
 189  * @adev: amdgpu device pointer
 190  * @reg: offset of register
 191  * @v: value to write to the register
 192  *
 193  * Dummy register read function.  Used for register blocks
 194  * that certain asics don't have (all asics).
 195  */
 196 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
 197 {
 198         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
 199                   reg, v);
 200         BUG();
 201 }
 202
 203 /**
 204  * amdgpu_block_invalid_rreg - dummy reg read function
 205  *
 206  * @adev: amdgpu device pointer
 207  * @block: offset of instance
 208  * @reg: offset of register
 209  *
 210  * Dummy register read function.  Used for register blocks
 211  * that certain asics don't have (all asics).
 212  * Returns the value in the register.
 213  */
 214 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
 215                                           uint32_t block, uint32_t reg)
 216 {
 217         DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
 218                   reg, block);
 219         BUG();
 220         return 0;
 221 }
 222
 223 /**
 224  * amdgpu_block_invalid_wreg - dummy reg write function
 225  *
 226  * @adev: amdgpu device pointer
 227  * @block: offset of instance
 228  * @reg: offset of register
 229  * @v: value to write to the register
 230  *
 231  * Dummy register read function.  Used for register blocks
 232  * that certain asics don't have (all asics).
 233  */
 234 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
 235                                       uint32_t block,
 236                                       uint32_t reg, uint32_t v)
 237 {
 238         DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
 239                   reg, block, v);
 240         BUG();
 241 }
 242
 243 static int amdgpu_vram_scratch_init(struct amdgpu_device *adev)
 244 {
 245         int r;
 246
 247         if (adev->vram_scratch.robj == NULL) {
 248                 r = amdgpu_bo_create(adev, AMDGPU_GPU_PAGE_SIZE,
 249                                      PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM,
 250                                      AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
 251                                      NULL, NULL, &adev->vram_scratch.robj);
 252                 if (r) {
 253                         return r;
 254                 }
 255         }
 256
 257         r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
 258         if (unlikely(r != 0))
 259                 return r;
 260         r = amdgpu_bo_pin(adev->vram_scratch.robj,
 261                           AMDGPU_GEM_DOMAIN_VRAM, &adev->vram_scratch.gpu_addr);
 262         if (r) {
 263                 amdgpu_bo_unreserve(adev->vram_scratch.robj);
 264                 return r;
 265         }
 266         r = amdgpu_bo_kmap(adev->vram_scratch.robj,
 267                                 (void **)&adev->vram_scratch.ptr);
 268         if (r)
 269                 amdgpu_bo_unpin(adev->vram_scratch.robj);
 270         amdgpu_bo_unreserve(adev->vram_scratch.robj);
 271
 272         return r;
 273 }
 274
 275 static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev)
 276 {
 277         int r;
 278
 279         if (adev->vram_scratch.robj == NULL) {
 280                 return;
 281         }
 282         r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
 283         if (likely(r == 0)) {
 284                 amdgpu_bo_kunmap(adev->vram_scratch.robj);
 285                 amdgpu_bo_unpin(adev->vram_scratch.robj);
 286                 amdgpu_bo_unreserve(adev->vram_scratch.robj);
 287         }
 288         amdgpu_bo_unref(&adev->vram_scratch.robj);
 289 }
 290
 291 /**
 292  * amdgpu_program_register_sequence - program an array of registers.
 293  *
 294  * @adev: amdgpu_device pointer
 295  * @registers: pointer to the register array
 296  * @array_size: size of the register array
 297  *
 298  * Programs an array or registers with and and or masks.
 299  * This is a helper for setting golden registers.
 300  */
 301 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
 302                                       const u32 *registers,
 303                                       const u32 array_size)
 304 {
 305         u32 tmp, reg, and_mask, or_mask;
 306         int i;
 307
 308         if (array_size % 3)
 309                 return;
 310
 311         for (i = 0; i < array_size; i +=3) {
 312                 reg = registers[i + 0];
 313                 and_mask = registers[i + 1];
 314                 or_mask = registers[i + 2];
 315
 316                 if (and_mask == 0xffffffff) {
 317                         tmp = or_mask;
 318                 } else {
 319                         tmp = RREG32(reg);
 320                         tmp &= ~and_mask;
 321                         tmp |= or_mask;
 322                 }
 323                 WREG32(reg, tmp);
 324         }
 325 }
 326
 327 void amdgpu_pci_config_reset(struct amdgpu_device *adev)
 328 {
 329         pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
 330 }
 331
 332 /*
 333  * GPU doorbell aperture helpers function.
 334  */
 335 /**
 336  * amdgpu_doorbell_init - Init doorbell driver information.
 337  *
 338  * @adev: amdgpu_device pointer
 339  *
 340  * Init doorbell driver information (CIK)
 341  * Returns 0 on success, error on failure.
 342  */
 343 static int amdgpu_doorbell_init(struct amdgpu_device *adev)
 344 {
 345         /* doorbell bar mapping */
 346         adev->doorbell.base = pci_resource_start(adev->pdev, 2);
 347         adev->doorbell.size = pci_resource_len(adev->pdev, 2);
 348
 349         adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
 350                                              AMDGPU_DOORBELL_MAX_ASSIGNMENT+1);
 351         if (adev->doorbell.num_doorbells == 0)
 352                 return -EINVAL;
 353
 354         adev->doorbell.ptr = ioremap(adev->doorbell.base, adev->doorbell.num_doorbells * sizeof(u32));
 355         if (adev->doorbell.ptr == NULL) {
 356                 return -ENOMEM;
 357         }
 358         DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)adev->doorbell.base);
 359         DRM_INFO("doorbell mmio size: %u\n", (unsigned)adev->doorbell.size);
 360
 361         return 0;
 362 }
 363
 364 /**
 365  * amdgpu_doorbell_fini - Tear down doorbell driver information.
 366  *
 367  * @adev: amdgpu_device pointer
 368  *
 369  * Tear down doorbell driver information (CIK)
 370  */
 371 static void amdgpu_doorbell_fini(struct amdgpu_device *adev)
 372 {
 373         iounmap(adev->doorbell.ptr);
 374         adev->doorbell.ptr = NULL;
 375 }
 376
 377 /**
 378  * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
 379  *                                setup amdkfd
 380  *
 381  * @adev: amdgpu_device pointer
 382  * @aperture_base: output returning doorbell aperture base physical address
 383  * @aperture_size: output returning doorbell aperture size in bytes
 384  * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
 385  *
 386  * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
 387  * takes doorbells required for its own rings and reports the setup to amdkfd.
 388  * amdgpu reserved doorbells are at the start of the doorbell aperture.
 389  */
 390 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
 391                                 phys_addr_t *aperture_base,
 392                                 size_t *aperture_size,
 393                                 size_t *start_offset)
 394 {
 395         /*
 396          * The first num_doorbells are used by amdgpu.
 397          * amdkfd takes whatever's left in the aperture.
 398          */
 399         if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
 400                 *aperture_base = adev->doorbell.base;
 401                 *aperture_size = adev->doorbell.size;
 402                 *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
 403         } else {
 404                 *aperture_base = 0;
 405                 *aperture_size = 0;
 406                 *start_offset = 0;
 407         }
 408 }
 409
 410 /*
 411  * amdgpu_wb_*()
 412  * Writeback is the the method by which the the GPU updates special pages
 413  * in memory with the status of certain GPU events (fences, ring pointers,
 414  * etc.).
 415  */
 416
 417 /**
 418  * amdgpu_wb_fini - Disable Writeback and free memory
 419  *
 420  * @adev: amdgpu_device pointer
 421  *
 422  * Disables Writeback and frees the Writeback memory (all asics).
 423  * Used at driver shutdown.
 424  */
 425 static void amdgpu_wb_fini(struct amdgpu_device *adev)
 426 {
 427         if (adev->wb.wb_obj) {
 428                 if (!amdgpu_bo_reserve(adev->wb.wb_obj, false)) {
 429                         amdgpu_bo_kunmap(adev->wb.wb_obj);
 430                         amdgpu_bo_unpin(adev->wb.wb_obj);
 431                         amdgpu_bo_unreserve(adev->wb.wb_obj);
 432                 }
 433                 amdgpu_bo_unref(&adev->wb.wb_obj);
 434                 adev->wb.wb = NULL;
 435                 adev->wb.wb_obj = NULL;
 436         }
 437 }
 438
 439 /**
 440  * amdgpu_wb_init- Init Writeback driver info and allocate memory
 441  *
 442  * @adev: amdgpu_device pointer
 443  *
 444  * Disables Writeback and frees the Writeback memory (all asics).
 445  * Used at driver startup.
 446  * Returns 0 on success or an -error on failure.
 447  */
 448 static int amdgpu_wb_init(struct amdgpu_device *adev)
 449 {
 450         int r;
 451
 452         if (adev->wb.wb_obj == NULL) {
 453                 r = amdgpu_bo_create(adev, AMDGPU_MAX_WB * 4, PAGE_SIZE, true,
 454                                      AMDGPU_GEM_DOMAIN_GTT, 0,  NULL, NULL,
 455                                      &adev->wb.wb_obj);
 456                 if (r) {
 457                         dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
 458                         return r;
 459                 }
 460                 r = amdgpu_bo_reserve(adev->wb.wb_obj, false);
 461                 if (unlikely(r != 0)) {
 462                         amdgpu_wb_fini(adev);
 463                         return r;
 464                 }
 465                 r = amdgpu_bo_pin(adev->wb.wb_obj, AMDGPU_GEM_DOMAIN_GTT,
 466                                 &adev->wb.gpu_addr);
 467                 if (r) {
 468                         amdgpu_bo_unreserve(adev->wb.wb_obj);
 469                         dev_warn(adev->dev, "(%d) pin WB bo failed\n", r);
 470                         amdgpu_wb_fini(adev);
 471                         return r;
 472                 }
 473                 r = amdgpu_bo_kmap(adev->wb.wb_obj, (void **)&adev->wb.wb);
 474                 amdgpu_bo_unreserve(adev->wb.wb_obj);
 475                 if (r) {
 476                         dev_warn(adev->dev, "(%d) map WB bo failed\n", r);
 477                         amdgpu_wb_fini(adev);
 478                         return r;
 479                 }
 480
 481                 adev->wb.num_wb = AMDGPU_MAX_WB;
 482                 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
 483
 484                 /* clear wb memory */
 485                 memset((char *)adev->wb.wb, 0, AMDGPU_GPU_PAGE_SIZE);
 486         }
 487
 488         return 0;
 489 }
 490
 491 /**
 492  * amdgpu_wb_get - Allocate a wb entry
 493  *
 494  * @adev: amdgpu_device pointer
 495  * @wb: wb index
 496  *
 497  * Allocate a wb slot for use by the driver (all asics).
 498  * Returns 0 on success or -EINVAL on failure.
 499  */
 500 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb)
 501 {
 502         unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
 503         if (offset < adev->wb.num_wb) {
 504                 __set_bit(offset, adev->wb.used);
 505                 *wb = offset;
 506                 return 0;
 507         } else {
 508                 return -EINVAL;
 509         }
 510 }
 511
 512 /**
 513  * amdgpu_wb_free - Free a wb entry
 514  *
 515  * @adev: amdgpu_device pointer
 516  * @wb: wb index
 517  *
 518  * Free a wb slot allocated for use by the driver (all asics)
 519  */
 520 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb)
 521 {
 522         if (wb < adev->wb.num_wb)
 523                 __clear_bit(wb, adev->wb.used);
 524 }
 525
 526 /**
 527  * amdgpu_vram_location - try to find VRAM location
 528  * @adev: amdgpu device structure holding all necessary informations
 529  * @mc: memory controller structure holding memory informations
 530  * @base: base address at which to put VRAM
 531  *
 532  * Function will place try to place VRAM at base address provided
 533  * as parameter (which is so far either PCI aperture address or
 534  * for IGP TOM base address).
 535  *
 536  * If there is not enough space to fit the unvisible VRAM in the 32bits
 537  * address space then we limit the VRAM size to the aperture.
 538  *
 539  * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
 540  * this shouldn't be a problem as we are using the PCI aperture as a reference.
 541  * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
 542  * not IGP.
 543  *
 544  * Note: we use mc_vram_size as on some board we need to program the mc to
 545  * cover the whole aperture even if VRAM size is inferior to aperture size
 546  * Novell bug 204882 + along with lots of ubuntu ones
 547  *
 548  * Note: when limiting vram it's safe to overwritte real_vram_size because
 549  * we are not in case where real_vram_size is inferior to mc_vram_size (ie
 550  * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
 551  * ones)
 552  *
 553  * Note: IGP TOM addr should be the same as the aperture addr, we don't
 554  * explicitly check for that thought.
 555  *
 556  * FIXME: when reducing VRAM size align new size on power of 2.
 557  */
 558 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base)
 559 {
 560         uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
 561
 562         mc->vram_start = base;
 563         if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) {
 564                 dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n");
 565                 mc->real_vram_size = mc->aper_size;
 566                 mc->mc_vram_size = mc->aper_size;
 567         }
 568         mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
 569         if (limit && limit < mc->real_vram_size)
 570                 mc->real_vram_size = limit;
 571         dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
 572                         mc->mc_vram_size >> 20, mc->vram_start,
 573                         mc->vram_end, mc->real_vram_size >> 20);
 574 }
 575
 576 /**
 577  * amdgpu_gtt_location - try to find GTT location
 578  * @adev: amdgpu device structure holding all necessary informations
 579  * @mc: memory controller structure holding memory informations
 580  *
 581  * Function will place try to place GTT before or after VRAM.
 582  *
 583  * If GTT size is bigger than space left then we ajust GTT size.
 584  * Thus function will never fails.
 585  *
 586  * FIXME: when reducing GTT size align new size on power of 2.
 587  */
 588 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc)
 589 {
 590         u64 size_af, size_bf;
 591
 592         size_af = ((adev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
 593         size_bf = mc->vram_start & ~mc->gtt_base_align;
 594         if (size_bf > size_af) {
 595                 if (mc->gtt_size > size_bf) {
 596                         dev_warn(adev->dev, "limiting GTT\n");
 597                         mc->gtt_size = size_bf;
 598                 }
 599                 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
 600         } else {
 601                 if (mc->gtt_size > size_af) {
 602                         dev_warn(adev->dev, "limiting GTT\n");
 603                         mc->gtt_size = size_af;
 604                 }
 605                 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
 606         }
 607         mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
 608         dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
 609                         mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
 610 }
 611
 612 /*
 613  * GPU helpers function.
 614  */
 615 /**
 616  * amdgpu_card_posted - check if the hw has already been initialized
 617  *
 618  * @adev: amdgpu_device pointer
 619  *
 620  * Check if the asic has been initialized (all asics).
 621  * Used at driver startup.
 622  * Returns true if initialized or false if not.
 623  */
 624 bool amdgpu_card_posted(struct amdgpu_device *adev)
 625 {
 626         uint32_t reg;
 627
 628         /* then check MEM_SIZE, in case the crtcs are off */
 629         reg = RREG32(mmCONFIG_MEMSIZE);
 630
 631         if (reg)
 632                 return true;
 633
 634         return false;
 635
 636 }
 637
 638 /**
 639  * amdgpu_boot_test_post_card - check and possibly initialize the hw
 640  *
 641  * @adev: amdgpu_device pointer
 642  *
 643  * Check if the asic is initialized and if not, attempt to initialize
 644  * it (all asics).
 645  * Returns true if initialized or false if not.
 646  */
 647 bool amdgpu_boot_test_post_card(struct amdgpu_device *adev)
 648 {
 649         if (amdgpu_card_posted(adev))
 650                 return true;
 651
 652         if (adev->bios) {
 653                 DRM_INFO("GPU not posted. posting now...\n");
 654                 if (adev->is_atom_bios)
 655                         amdgpu_atom_asic_init(adev->mode_info.atom_context);
 656                 return true;
 657         } else {
 658                 dev_err(adev->dev, "Card not posted and no BIOS - ignoring\n");
 659                 return false;
 660         }
 661 }
 662
 663 /**
 664  * amdgpu_dummy_page_init - init dummy page used by the driver
 665  *
 666  * @adev: amdgpu_device pointer
 667  *
 668  * Allocate the dummy page used by the driver (all asics).
 669  * This dummy page is used by the driver as a filler for gart entries
 670  * when pages are taken out of the GART
 671  * Returns 0 on sucess, -ENOMEM on failure.
 672  */
 673 int amdgpu_dummy_page_init(struct amdgpu_device *adev)
 674 {
 675         if (adev->dummy_page.page)
 676                 return 0;
 677         adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
 678         if (adev->dummy_page.page == NULL)
 679                 return -ENOMEM;
 680         adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page,
 681                                         0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 682         if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) {
 683                 dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
 684                 __free_page(adev->dummy_page.page);
 685                 adev->dummy_page.page = NULL;
 686                 return -ENOMEM;
 687         }
 688         return 0;
 689 }
 690
 691 /**
 692  * amdgpu_dummy_page_fini - free dummy page used by the driver
 693  *
 694  * @adev: amdgpu_device pointer
 695  *
 696  * Frees the dummy page used by the driver (all asics).
 697  */
 698 void amdgpu_dummy_page_fini(struct amdgpu_device *adev)
 699 {
 700         if (adev->dummy_page.page == NULL)
 701                 return;
 702         pci_unmap_page(adev->pdev, adev->dummy_page.addr,
 703                         PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 704         __free_page(adev->dummy_page.page);
 705         adev->dummy_page.page = NULL;
 706 }
 707
 708
 709 /* ATOM accessor methods */
 710 /*
 711  * ATOM is an interpreted byte code stored in tables in the vbios.  The
 712  * driver registers callbacks to access registers and the interpreter
 713  * in the driver parses the tables and executes then to program specific
 714  * actions (set display modes, asic init, etc.).  See amdgpu_atombios.c,
 715  * atombios.h, and atom.c
 716  */
 717
 718 /**
 719  * cail_pll_read - read PLL register
 720  *
 721  * @info: atom card_info pointer
 722  * @reg: PLL register offset
 723  *
 724  * Provides a PLL register accessor for the atom interpreter (r4xx+).
 725  * Returns the value of the PLL register.
 726  */
 727 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
 728 {
 729         return 0;
 730 }
 731
 732 /**
 733  * cail_pll_write - write PLL register
 734  *
 735  * @info: atom card_info pointer
 736  * @reg: PLL register offset
 737  * @val: value to write to the pll register
 738  *
 739  * Provides a PLL register accessor for the atom interpreter (r4xx+).
 740  */
 741 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
 742 {
 743
 744 }
 745
 746 /**
 747  * cail_mc_read - read MC (Memory Controller) register
 748  *
 749  * @info: atom card_info pointer
 750  * @reg: MC register offset
 751  *
 752  * Provides an MC register accessor for the atom interpreter (r4xx+).
 753  * Returns the value of the MC register.
 754  */
 755 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
 756 {
 757         return 0;
 758 }
 759
 760 /**
 761  * cail_mc_write - write MC (Memory Controller) register
 762  *
 763  * @info: atom card_info pointer
 764  * @reg: MC register offset
 765  * @val: value to write to the pll register
 766  *
 767  * Provides a MC register accessor for the atom interpreter (r4xx+).
 768  */
 769 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
 770 {
 771
 772 }
 773
 774 /**
 775  * cail_reg_write - write MMIO register
 776  *
 777  * @info: atom card_info pointer
 778  * @reg: MMIO register offset
 779  * @val: value to write to the pll register
 780  *
 781  * Provides a MMIO register accessor for the atom interpreter (r4xx+).
 782  */
 783 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
 784 {
 785         struct amdgpu_device *adev = info->dev->dev_private;
 786
 787         WREG32(reg, val);
 788 }
 789
 790 /**
 791  * cail_reg_read - read MMIO register
 792  *
 793  * @info: atom card_info pointer
 794  * @reg: MMIO register offset
 795  *
 796  * Provides an MMIO register accessor for the atom interpreter (r4xx+).
 797  * Returns the value of the MMIO register.
 798  */
 799 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
 800 {
 801         struct amdgpu_device *adev = info->dev->dev_private;
 802         uint32_t r;
 803
 804         r = RREG32(reg);
 805         return r;
 806 }
 807
 808 /**
 809  * cail_ioreg_write - write IO register
 810  *
 811  * @info: atom card_info pointer
 812  * @reg: IO register offset
 813  * @val: value to write to the pll register
 814  *
 815  * Provides a IO register accessor for the atom interpreter (r4xx+).
 816  */
 817 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
 818 {
 819         struct amdgpu_device *adev = info->dev->dev_private;
 820
 821         WREG32_IO(reg, val);
 822 }
 823
 824 /**
 825  * cail_ioreg_read - read IO register
 826  *
 827  * @info: atom card_info pointer
 828  * @reg: IO register offset
 829  *
 830  * Provides an IO register accessor for the atom interpreter (r4xx+).
 831  * Returns the value of the IO register.
 832  */
 833 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
 834 {
 835         struct amdgpu_device *adev = info->dev->dev_private;
 836         uint32_t r;
 837
 838         r = RREG32_IO(reg);
 839         return r;
 840 }
 841
 842 /**
 843  * amdgpu_atombios_fini - free the driver info and callbacks for atombios
 844  *
 845  * @adev: amdgpu_device pointer
 846  *
 847  * Frees the driver info and register access callbacks for the ATOM
 848  * interpreter (r4xx+).
 849  * Called at driver shutdown.
 850  */
 851 static void amdgpu_atombios_fini(struct amdgpu_device *adev)
 852 {
 853         if (adev->mode_info.atom_context)
 854                 kfree(adev->mode_info.atom_context->scratch);
 855         kfree(adev->mode_info.atom_context);
 856         adev->mode_info.atom_context = NULL;
 857         kfree(adev->mode_info.atom_card_info);
 858         adev->mode_info.atom_card_info = NULL;
 859 }
 860
 861 /**
 862  * amdgpu_atombios_init - init the driver info and callbacks for atombios
 863  *
 864  * @adev: amdgpu_device pointer
 865  *
 866  * Initializes the driver info and register access callbacks for the
 867  * ATOM interpreter (r4xx+).
 868  * Returns 0 on sucess, -ENOMEM on failure.
 869  * Called at driver startup.
 870  */
 871 static int amdgpu_atombios_init(struct amdgpu_device *adev)
 872 {
 873         struct card_info *atom_card_info =
 874             kzalloc(sizeof(struct card_info), GFP_KERNEL);
 875
 876         if (!atom_card_info)
 877                 return -ENOMEM;
 878
 879         adev->mode_info.atom_card_info = atom_card_info;
 880         atom_card_info->dev = adev->ddev;
 881         atom_card_info->reg_read = cail_reg_read;
 882         atom_card_info->reg_write = cail_reg_write;
 883         /* needed for iio ops */
 884         if (adev->rio_mem) {
 885                 atom_card_info->ioreg_read = cail_ioreg_read;
 886                 atom_card_info->ioreg_write = cail_ioreg_write;
 887         } else {
 888                 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
 889                 atom_card_info->ioreg_read = cail_reg_read;
 890                 atom_card_info->ioreg_write = cail_reg_write;
 891         }
 892         atom_card_info->mc_read = cail_mc_read;
 893         atom_card_info->mc_write = cail_mc_write;
 894         atom_card_info->pll_read = cail_pll_read;
 895         atom_card_info->pll_write = cail_pll_write;
 896
 897         adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios);
 898         if (!adev->mode_info.atom_context) {
 899                 amdgpu_atombios_fini(adev);
 900                 return -ENOMEM;
 901         }
 902
 903         mutex_init(&adev->mode_info.atom_context->mutex);
 904         amdgpu_atombios_scratch_regs_init(adev);
 905         amdgpu_atom_allocate_fb_scratch(adev->mode_info.atom_context);
 906         return 0;
 907 }
 908
 909 /* if we get transitioned to only one device, take VGA back */
 910 /**
 911  * amdgpu_vga_set_decode - enable/disable vga decode
 912  *
 913  * @cookie: amdgpu_device pointer
 914  * @state: enable/disable vga decode
 915  *
 916  * Enable/disable vga decode (all asics).
 917  * Returns VGA resource flags.
 918  */
 919 static unsigned int amdgpu_vga_set_decode(void *cookie, bool state)
 920 {
 921         struct amdgpu_device *adev = cookie;
 922         amdgpu_asic_set_vga_state(adev, state);
 923         if (state)
 924                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 925                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 926         else
 927                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 928 }
 929
 930 /**
 931  * amdgpu_check_pot_argument - check that argument is a power of two
 932  *
 933  * @arg: value to check
 934  *
 935  * Validates that a certain argument is a power of two (all asics).
 936  * Returns true if argument is valid.
 937  */
 938 static bool amdgpu_check_pot_argument(int arg)
 939 {
 940         return (arg & (arg - 1)) == 0;
 941 }
 942
 943 /**
 944  * amdgpu_check_arguments - validate module params
 945  *
 946  * @adev: amdgpu_device pointer
 947  *
 948  * Validates certain module parameters and updates
 949  * the associated values used by the driver (all asics).
 950  */
 951 static void amdgpu_check_arguments(struct amdgpu_device *adev)
 952 {
 953         if (amdgpu_sched_jobs < 4) {
 954                 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
 955                          amdgpu_sched_jobs);
 956                 amdgpu_sched_jobs = 4;
 957         } else if (!amdgpu_check_pot_argument(amdgpu_sched_jobs)){
 958                 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
 959                          amdgpu_sched_jobs);
 960                 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
 961         }
 962         /* vramlimit must be a power of two */
 963         if (!amdgpu_check_pot_argument(amdgpu_vram_limit)) {
 964                 dev_warn(adev->dev, "vram limit (%d) must be a power of 2\n",
 965                                 amdgpu_vram_limit);
 966                 amdgpu_vram_limit = 0;
 967         }
 968
 969         if (amdgpu_gart_size != -1) {
 970                 /* gtt size must be power of two and greater or equal to 32M */
 971                 if (amdgpu_gart_size < 32) {
 972                         dev_warn(adev->dev, "gart size (%d) too small\n",
 973                                  amdgpu_gart_size);
 974                         amdgpu_gart_size = -1;
 975                 } else if (!amdgpu_check_pot_argument(amdgpu_gart_size)) {
 976                         dev_warn(adev->dev, "gart size (%d) must be a power of 2\n",
 977                                  amdgpu_gart_size);
 978                         amdgpu_gart_size = -1;
 979                 }
 980         }
 981
 982         if (!amdgpu_check_pot_argument(amdgpu_vm_size)) {
 983                 dev_warn(adev->dev, "VM size (%d) must be a power of 2\n",
 984                          amdgpu_vm_size);
 985                 amdgpu_vm_size = 8;
 986         }
 987
 988         if (amdgpu_vm_size < 1) {
 989                 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
 990                          amdgpu_vm_size);
 991                 amdgpu_vm_size = 8;
 992         }
 993
 994         /*
 995          * Max GPUVM size for Cayman, SI and CI are 40 bits.
 996          */
 997         if (amdgpu_vm_size > 1024) {
 998                 dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n",
 999                          amdgpu_vm_size);
1000                 amdgpu_vm_size = 8;
1001         }
1002
1003         /* defines number of bits in page table versus page directory,
1004          * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1005          * page table and the remaining bits are in the page directory */
1006         if (amdgpu_vm_block_size == -1) {
1007
1008                 /* Total bits covered by PD + PTs */
1009                 unsigned bits = ilog2(amdgpu_vm_size) + 18;
1010
1011                 /* Make sure the PD is 4K in size up to 8GB address space.
1012                    Above that split equal between PD and PTs */
1013                 if (amdgpu_vm_size <= 8)
1014                         amdgpu_vm_block_size = bits - 9;
1015                 else
1016                         amdgpu_vm_block_size = (bits + 3) / 2;
1017
1018         } else if (amdgpu_vm_block_size < 9) {
1019                 dev_warn(adev->dev, "VM page table size (%d) too small\n",
1020                          amdgpu_vm_block_size);
1021                 amdgpu_vm_block_size = 9;
1022         }
1023
1024         if (amdgpu_vm_block_size > 24 ||
1025             (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) {
1026                 dev_warn(adev->dev, "VM page table size (%d) too large\n",
1027                          amdgpu_vm_block_size);
1028                 amdgpu_vm_block_size = 9;
1029         }
1030 }
1031
1032 /**
1033  * amdgpu_switcheroo_set_state - set switcheroo state
1034  *
1035  * @pdev: pci dev pointer
1036  * @state: vga_switcheroo state
1037  *
1038  * Callback for the switcheroo driver.  Suspends or resumes the
1039  * the asics before or after it is powered up using ACPI methods.
1040  */
1041 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1042 {
1043         struct drm_device *dev = pci_get_drvdata(pdev);
1044
1045         if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1046                 return;
1047
1048         if (state == VGA_SWITCHEROO_ON) {
1049                 unsigned d3_delay = dev->pdev->d3_delay;
1050
1051                 printk(KERN_INFO "amdgpu: switched on\n");
1052                 /* don't suspend or resume card normally */
1053                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1054
1055                 amdgpu_resume_kms(dev, true, true);
1056
1057                 dev->pdev->d3_delay = d3_delay;
1058
1059                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1060                 drm_kms_helper_poll_enable(dev);
1061         } else {
1062                 printk(KERN_INFO "amdgpu: switched off\n");
1063                 drm_kms_helper_poll_disable(dev);
1064                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1065                 amdgpu_suspend_kms(dev, true, true);
1066                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1067         }
1068 }
1069
1070 /**
1071  * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1072  *
1073  * @pdev: pci dev pointer
1074  *
1075  * Callback for the switcheroo driver.  Check of the switcheroo
1076  * state can be changed.
1077  * Returns true if the state can be changed, false if not.
1078  */
1079 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1080 {
1081         struct drm_device *dev = pci_get_drvdata(pdev);
1082
1083         /*
1084         * FIXME: open_count is protected by drm_global_mutex but that would lead to
1085         * locking inversion with the driver load path. And the access here is
1086         * completely racy anyway. So don't bother with locking for now.
1087         */
1088         return dev->open_count == 0;
1089 }
1090
1091 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1092         .set_gpu_state = amdgpu_switcheroo_set_state,
1093         .reprobe = NULL,
1094         .can_switch = amdgpu_switcheroo_can_switch,
1095 };
1096
1097 int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
1098                                   enum amd_ip_block_type block_type,
1099                                   enum amd_clockgating_state state)
1100 {
1101         int i, r = 0;
1102
1103         for (i = 0; i < adev->num_ip_blocks; i++) {
1104                 if (adev->ip_blocks[i].type == block_type) {
1105                         r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1106                                                                             state);
1107                         if (r)
1108                                 return r;
1109                 }
1110         }
1111         return r;
1112 }
1113
1114 int amdgpu_set_powergating_state(struct amdgpu_device *adev,
1115                                   enum amd_ip_block_type block_type,
1116                                   enum amd_powergating_state state)
1117 {
1118         int i, r = 0;
1119
1120         for (i = 0; i < adev->num_ip_blocks; i++) {
1121                 if (adev->ip_blocks[i].type == block_type) {
1122                         r = adev->ip_blocks[i].funcs->set_powergating_state((void *)adev,
1123                                                                             state);
1124                         if (r)
1125                                 return r;
1126                 }
1127         }
1128         return r;
1129 }
1130
1131 const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
1132                                         struct amdgpu_device *adev,
1133                                         enum amd_ip_block_type type)
1134 {
1135         int i;
1136
1137         for (i = 0; i < adev->num_ip_blocks; i++)
1138                 if (adev->ip_blocks[i].type == type)
1139                         return &adev->ip_blocks[i];
1140
1141         return NULL;
1142 }
1143
1144 /**
1145  * amdgpu_ip_block_version_cmp
1146  *
1147  * @adev: amdgpu_device pointer
1148  * @type: enum amd_ip_block_type
1149  * @major: major version
1150  * @minor: minor version
1151  *
1152  * return 0 if equal or greater
1153  * return 1 if smaller or the ip_block doesn't exist
1154  */
1155 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
1156                                 enum amd_ip_block_type type,
1157                                 u32 major, u32 minor)
1158 {
1159         const struct amdgpu_ip_block_version *ip_block;
1160         ip_block = amdgpu_get_ip_block(adev, type);
1161
1162         if (ip_block && ((ip_block->major > major) ||
1163                         ((ip_block->major == major) &&
1164                         (ip_block->minor >= minor))))
1165                 return 0;
1166
1167         return 1;
1168 }
1169
1170 static int amdgpu_early_init(struct amdgpu_device *adev)
1171 {
1172         int i, r;
1173
1174         switch (adev->asic_type) {
1175         case CHIP_TOPAZ:
1176         case CHIP_TONGA:
1177         case CHIP_FIJI:
1178         case CHIP_CARRIZO:
1179         case CHIP_STONEY:
1180                 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
1181                         adev->family = AMDGPU_FAMILY_CZ;
1182                 else
1183                         adev->family = AMDGPU_FAMILY_VI;
1184
1185                 r = vi_set_ip_blocks(adev);
1186                 if (r)
1187                         return r;
1188                 break;
1189 #ifdef CONFIG_DRM_AMDGPU_CIK
1190         case CHIP_BONAIRE:
1191         case CHIP_HAWAII:
1192         case CHIP_KAVERI:
1193         case CHIP_KABINI:
1194         case CHIP_MULLINS:
1195                 if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
1196                         adev->family = AMDGPU_FAMILY_CI;
1197                 else
1198                         adev->family = AMDGPU_FAMILY_KV;
1199
1200                 r = cik_set_ip_blocks(adev);
1201                 if (r)
1202                         return r;
1203                 break;
1204 #endif
1205         default:
1206                 /* FIXME: not supported yet */
1207                 return -EINVAL;
1208         }
1209
1210         adev->ip_block_status = kcalloc(adev->num_ip_blocks,
1211                                         sizeof(struct amdgpu_ip_block_status), GFP_KERNEL);
1212         if (adev->ip_block_status == NULL)
1213                 return -ENOMEM;
1214
1215         if (adev->ip_blocks == NULL) {
1216                 DRM_ERROR("No IP blocks found!\n");
1217                 return r;
1218         }
1219
1220         for (i = 0; i < adev->num_ip_blocks; i++) {
1221                 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1222                         DRM_ERROR("disabled ip block: %d\n", i);
1223                         adev->ip_block_status[i].valid = false;
1224                 } else {
1225                         if (adev->ip_blocks[i].funcs->early_init) {
1226                                 r = adev->ip_blocks[i].funcs->early_init((void *)adev);
1227                                 if (r == -ENOENT) {
1228                                         adev->ip_block_status[i].valid = false;
1229                                 } else if (r) {
1230                                         DRM_ERROR("early_init %d failed %d\n", i, r);
1231                                         return r;
1232                                 } else {
1233                                         adev->ip_block_status[i].valid = true;
1234                                 }
1235                         } else {
1236                                 adev->ip_block_status[i].valid = true;
1237                         }
1238                 }
1239         }
1240
1241         return 0;
1242 }
1243
1244 static int amdgpu_init(struct amdgpu_device *adev)
1245 {
1246         int i, r;
1247
1248         for (i = 0; i < adev->num_ip_blocks; i++) {
1249                 if (!adev->ip_block_status[i].valid)
1250                         continue;
1251                 r = adev->ip_blocks[i].funcs->sw_init((void *)adev);
1252                 if (r) {
1253                         DRM_ERROR("sw_init %d failed %d\n", i, r);
1254                         return r;
1255                 }
1256                 adev->ip_block_status[i].sw = true;
1257                 /* need to do gmc hw init early so we can allocate gpu mem */
1258                 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
1259                         r = amdgpu_vram_scratch_init(adev);
1260                         if (r) {
1261                                 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
1262                                 return r;
1263                         }
1264                         r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
1265                         if (r) {
1266                                 DRM_ERROR("hw_init %d failed %d\n", i, r);
1267                                 return r;
1268                         }
1269                         r = amdgpu_wb_init(adev);
1270                         if (r) {
1271                                 DRM_ERROR("amdgpu_wb_init failed %d\n", r);
1272                                 return r;
1273                         }
1274                         adev->ip_block_status[i].hw = true;
1275                 }
1276         }
1277
1278         for (i = 0; i < adev->num_ip_blocks; i++) {
1279                 if (!adev->ip_block_status[i].sw)
1280                         continue;
1281                 /* gmc hw init is done early */
1282                 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC)
1283                         continue;
1284                 r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
1285                 if (r) {
1286                         DRM_ERROR("hw_init %d failed %d\n", i, r);
1287                         return r;
1288                 }
1289                 adev->ip_block_status[i].hw = true;
1290         }
1291
1292         return 0;
1293 }
1294
1295 static int amdgpu_late_init(struct amdgpu_device *adev)
1296 {
1297         int i = 0, r;
1298
1299         for (i = 0; i < adev->num_ip_blocks; i++) {
1300                 if (!adev->ip_block_status[i].valid)
1301                         continue;
1302                 /* enable clockgating to save power */
1303                 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1304                                                                     AMD_CG_STATE_GATE);
1305                 if (r) {
1306                         DRM_ERROR("set_clockgating_state(gate) %d failed %d\n", i, r);
1307                         return r;
1308                 }
1309                 if (adev->ip_blocks[i].funcs->late_init) {
1310                         r = adev->ip_blocks[i].funcs->late_init((void *)adev);
1311                         if (r) {
1312                                 DRM_ERROR("late_init %d failed %d\n", i, r);
1313                                 return r;
1314                         }
1315                 }
1316         }
1317
1318         return 0;
1319 }
1320
1321 static int amdgpu_fini(struct amdgpu_device *adev)
1322 {
1323         int i, r;
1324
1325         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1326                 if (!adev->ip_block_status[i].hw)
1327                         continue;
1328                 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
1329                         amdgpu_wb_fini(adev);
1330                         amdgpu_vram_scratch_fini(adev);
1331                 }
1332                 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1333                 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1334                                                                     AMD_CG_STATE_UNGATE);
1335                 if (r) {
1336                         DRM_ERROR("set_clockgating_state(ungate) %d failed %d\n", i, r);
1337                         return r;
1338                 }
1339                 r = adev->ip_blocks[i].funcs->hw_fini((void *)adev);
1340                 /* XXX handle errors */
1341                 if (r) {
1342                         DRM_DEBUG("hw_fini %d failed %d\n", i, r);
1343                 }
1344                 adev->ip_block_status[i].hw = false;
1345         }
1346
1347         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1348                 if (!adev->ip_block_status[i].sw)
1349                         continue;
1350                 r = adev->ip_blocks[i].funcs->sw_fini((void *)adev);
1351                 /* XXX handle errors */
1352                 if (r) {
1353                         DRM_DEBUG("sw_fini %d failed %d\n", i, r);
1354                 }
1355                 adev->ip_block_status[i].sw = false;
1356                 adev->ip_block_status[i].valid = false;
1357         }
1358
1359         return 0;
1360 }
1361
1362 static int amdgpu_suspend(struct amdgpu_device *adev)
1363 {
1364         int i, r;
1365
1366         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1367                 if (!adev->ip_block_status[i].valid)
1368                         continue;
1369                 /* ungate blocks so that suspend can properly shut them down */
1370                 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1371                                                                     AMD_CG_STATE_UNGATE);
1372                 if (r) {
1373                         DRM_ERROR("set_clockgating_state(ungate) %d failed %d\n", i, r);
1374                 }
1375                 /* XXX handle errors */
1376                 r = adev->ip_blocks[i].funcs->suspend(adev);
1377                 /* XXX handle errors */
1378                 if (r) {
1379                         DRM_ERROR("suspend %d failed %d\n", i, r);
1380                 }
1381         }
1382
1383         return 0;
1384 }
1385
1386 static int amdgpu_resume(struct amdgpu_device *adev)
1387 {
1388         int i, r;
1389
1390         for (i = 0; i < adev->num_ip_blocks; i++) {
1391                 if (!adev->ip_block_status[i].valid)
1392                         continue;
1393                 r = adev->ip_blocks[i].funcs->resume(adev);
1394                 if (r) {
1395                         DRM_ERROR("resume %d failed %d\n", i, r);
1396                         return r;
1397                 }
1398         }
1399
1400         return 0;
1401 }
1402
1403 /**
1404  * amdgpu_device_init - initialize the driver
1405  *
1406  * @adev: amdgpu_device pointer
1407  * @pdev: drm dev pointer
1408  * @pdev: pci dev pointer
1409  * @flags: driver flags
1410  *
1411  * Initializes the driver info and hw (all asics).
1412  * Returns 0 for success or an error on failure.
1413  * Called at driver startup.
1414  */
1415 int amdgpu_device_init(struct amdgpu_device *adev,
1416                        struct drm_device *ddev,
1417                        struct pci_dev *pdev,
1418                        uint32_t flags)
1419 {
1420         int r, i;
1421         bool runtime = false;
1422
1423         adev->shutdown = false;
1424         adev->dev = &pdev->dev;
1425         adev->ddev = ddev;
1426         adev->pdev = pdev;
1427         adev->flags = flags;
1428         adev->asic_type = flags & AMD_ASIC_MASK;
1429         adev->is_atom_bios = false;
1430         adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
1431         adev->mc.gtt_size = 512 * 1024 * 1024;
1432         adev->accel_working = false;
1433         adev->num_rings = 0;
1434         adev->mman.buffer_funcs = NULL;
1435         adev->mman.buffer_funcs_ring = NULL;
1436         adev->vm_manager.vm_pte_funcs = NULL;
1437         adev->vm_manager.vm_pte_funcs_ring = NULL;
1438         adev->gart.gart_funcs = NULL;
1439         adev->fence_context = fence_context_alloc(AMDGPU_MAX_RINGS);
1440
1441         adev->smc_rreg = &amdgpu_invalid_rreg;
1442         adev->smc_wreg = &amdgpu_invalid_wreg;
1443         adev->pcie_rreg = &amdgpu_invalid_rreg;
1444         adev->pcie_wreg = &amdgpu_invalid_wreg;
1445         adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
1446         adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
1447         adev->didt_rreg = &amdgpu_invalid_rreg;
1448         adev->didt_wreg = &amdgpu_invalid_wreg;
1449         adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
1450         adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
1451
1452         DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
1453                  amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
1454                  pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
1455
1456         /* mutex initialization are all done here so we
1457          * can recall function without having locking issues */
1458         mutex_init(&adev->ring_lock);
1459         atomic_set(&adev->irq.ih.lock, 0);
1460         mutex_init(&adev->gem.mutex);
1461         mutex_init(&adev->pm.mutex);
1462         mutex_init(&adev->gfx.gpu_clock_mutex);
1463         mutex_init(&adev->srbm_mutex);
1464         mutex_init(&adev->grbm_idx_mutex);
1465         mutex_init(&adev->mn_lock);
1466         hash_init(adev->mn_hash);
1467
1468         amdgpu_check_arguments(adev);
1469
1470         /* Registers mapping */
1471         /* TODO: block userspace mapping of io register */
1472         spin_lock_init(&adev->mmio_idx_lock);
1473         spin_lock_init(&adev->smc_idx_lock);
1474         spin_lock_init(&adev->pcie_idx_lock);
1475         spin_lock_init(&adev->uvd_ctx_idx_lock);
1476         spin_lock_init(&adev->didt_idx_lock);
1477         spin_lock_init(&adev->audio_endpt_idx_lock);
1478
1479         adev->rmmio_base = pci_resource_start(adev->pdev, 5);
1480         adev->rmmio_size = pci_resource_len(adev->pdev, 5);
1481         adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
1482         if (adev->rmmio == NULL) {
1483                 return -ENOMEM;
1484         }
1485         DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
1486         DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
1487
1488         /* doorbell bar mapping */
1489         amdgpu_doorbell_init(adev);
1490
1491         /* io port mapping */
1492         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1493                 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
1494                         adev->rio_mem_size = pci_resource_len(adev->pdev, i);
1495                         adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
1496                         break;
1497                 }
1498         }
1499         if (adev->rio_mem == NULL)
1500                 DRM_ERROR("Unable to find PCI I/O BAR\n");
1501
1502         /* early init functions */
1503         r = amdgpu_early_init(adev);
1504         if (r)
1505                 return r;
1506
1507         /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
1508         /* this will fail for cards that aren't VGA class devices, just
1509          * ignore it */
1510         vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode);
1511
1512         if (amdgpu_runtime_pm == 1)
1513                 runtime = true;
1514         if (amdgpu_device_is_px(ddev))
1515                 runtime = true;
1516         vga_switcheroo_register_client(adev->pdev, &amdgpu_switcheroo_ops, runtime);
1517         if (runtime)
1518                 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
1519
1520         /* Read BIOS */
1521         if (!amdgpu_get_bios(adev))
1522                 return -EINVAL;
1523         /* Must be an ATOMBIOS */
1524         if (!adev->is_atom_bios) {
1525                 dev_err(adev->dev, "Expecting atombios for GPU\n");
1526                 return -EINVAL;
1527         }
1528         r = amdgpu_atombios_init(adev);
1529         if (r) {
1530                 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
1531                 return r;
1532         }
1533
1534         /* Post card if necessary */
1535         if (!amdgpu_card_posted(adev)) {
1536                 if (!adev->bios) {
1537                         dev_err(adev->dev, "Card not posted and no BIOS - ignoring\n");
1538                         return -EINVAL;
1539                 }
1540                 DRM_INFO("GPU not posted. posting now...\n");
1541                 amdgpu_atom_asic_init(adev->mode_info.atom_context);
1542         }
1543
1544         /* Initialize clocks */
1545         r = amdgpu_atombios_get_clock_info(adev);
1546         if (r) {
1547                 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
1548                 return r;
1549         }
1550         /* init i2c buses */
1551         amdgpu_atombios_i2c_init(adev);
1552
1553         /* Fence driver */
1554         r = amdgpu_fence_driver_init(adev);
1555         if (r) {
1556                 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
1557                 return r;
1558         }
1559
1560         /* init the mode config */
1561         drm_mode_config_init(adev->ddev);
1562
1563         r = amdgpu_init(adev);
1564         if (r) {
1565                 dev_err(adev->dev, "amdgpu_init failed\n");
1566                 amdgpu_fini(adev);
1567                 return r;
1568         }
1569
1570         adev->accel_working = true;
1571
1572         amdgpu_fbdev_init(adev);
1573
1574         r = amdgpu_ib_pool_init(adev);
1575         if (r) {
1576                 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
1577                 return r;
1578         }
1579
1580         r = amdgpu_ctx_init(adev, AMD_SCHED_PRIORITY_KERNEL, &adev->kernel_ctx);
1581         if (r) {
1582                 dev_err(adev->dev, "failed to create kernel context (%d).\n", r);
1583                 return r;
1584         }
1585         r = amdgpu_ib_ring_tests(adev);
1586         if (r)
1587                 DRM_ERROR("ib ring test failed (%d).\n", r);
1588
1589         r = amdgpu_gem_debugfs_init(adev);
1590         if (r) {
1591                 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
1592         }
1593
1594         r = amdgpu_debugfs_regs_init(adev);
1595         if (r) {
1596                 DRM_ERROR("registering register debugfs failed (%d).\n", r);
1597         }
1598
1599         if ((amdgpu_testing & 1)) {
1600                 if (adev->accel_working)
1601                         amdgpu_test_moves(adev);
1602                 else
1603                         DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
1604         }
1605         if ((amdgpu_testing & 2)) {
1606                 if (adev->accel_working)
1607                         amdgpu_test_syncing(adev);
1608                 else
1609                         DRM_INFO("amdgpu: acceleration disabled, skipping sync tests\n");
1610         }
1611         if (amdgpu_benchmarking) {
1612                 if (adev->accel_working)
1613                         amdgpu_benchmark(adev, amdgpu_benchmarking);
1614                 else
1615                         DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
1616         }
1617
1618         /* enable clockgating, etc. after ib tests, etc. since some blocks require
1619          * explicit gating rather than handling it automatically.
1620          */
1621         r = amdgpu_late_init(adev);
1622         if (r) {
1623                 dev_err(adev->dev, "amdgpu_late_init failed\n");
1624                 return r;
1625         }
1626
1627         return 0;
1628 }
1629
1630 static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev);
1631
1632 /**
1633  * amdgpu_device_fini - tear down the driver
1634  *
1635  * @adev: amdgpu_device pointer
1636  *
1637  * Tear down the driver info (all asics).
1638  * Called at driver shutdown.
1639  */
1640 void amdgpu_device_fini(struct amdgpu_device *adev)
1641 {
1642         int r;
1643
1644         DRM_INFO("amdgpu: finishing device.\n");
1645         adev->shutdown = true;
1646         /* evict vram memory */
1647         amdgpu_bo_evict_vram(adev);
1648         amdgpu_ctx_fini(&adev->kernel_ctx);
1649         amdgpu_ib_pool_fini(adev);
1650         amdgpu_fence_driver_fini(adev);
1651         amdgpu_fbdev_fini(adev);
1652         r = amdgpu_fini(adev);
1653         kfree(adev->ip_block_status);
1654         adev->ip_block_status = NULL;
1655         adev->accel_working = false;
1656         /* free i2c buses */
1657         amdgpu_i2c_fini(adev);
1658         amdgpu_atombios_fini(adev);
1659         kfree(adev->bios);
1660         adev->bios = NULL;
1661         vga_switcheroo_unregister_client(adev->pdev);
1662         vga_client_register(adev->pdev, NULL, NULL, NULL);
1663         if (adev->rio_mem)
1664                 pci_iounmap(adev->pdev, adev->rio_mem);
1665         adev->rio_mem = NULL;
1666         iounmap(adev->rmmio);
1667         adev->rmmio = NULL;
1668         amdgpu_doorbell_fini(adev);
1669         amdgpu_debugfs_regs_cleanup(adev);
1670         amdgpu_debugfs_remove_files(adev);
1671 }
1672
1673
1674 /*
1675  * Suspend & resume.
1676  */
1677 /**
1678  * amdgpu_suspend_kms - initiate device suspend
1679  *
1680  * @pdev: drm dev pointer
1681  * @state: suspend state
1682  *
1683  * Puts the hw in the suspend state (all asics).
1684  * Returns 0 for success or an error on failure.
1685  * Called at driver suspend.
1686  */
1687 int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon)
1688 {
1689         struct amdgpu_device *adev;
1690         struct drm_crtc *crtc;
1691         struct drm_connector *connector;
1692         int r;
1693
1694         if (dev == NULL || dev->dev_private == NULL) {
1695                 return -ENODEV;
1696         }
1697
1698         adev = dev->dev_private;
1699
1700         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1701                 return 0;
1702
1703         drm_kms_helper_poll_disable(dev);
1704
1705         /* turn off display hw */
1706         drm_modeset_lock_all(dev);
1707         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1708                 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
1709         }
1710         drm_modeset_unlock_all(dev);
1711
1712         /* unpin the front buffers and cursors */
1713         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1714                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1715                 struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb);
1716                 struct amdgpu_bo *robj;
1717
1718                 if (amdgpu_crtc->cursor_bo) {
1719                         struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1720                         r = amdgpu_bo_reserve(aobj, false);
1721                         if (r == 0) {
1722                                 amdgpu_bo_unpin(aobj);
1723                                 amdgpu_bo_unreserve(aobj);
1724                         }
1725                 }
1726
1727                 if (rfb == NULL || rfb->obj == NULL) {
1728                         continue;
1729                 }
1730                 robj = gem_to_amdgpu_bo(rfb->obj);
1731                 /* don't unpin kernel fb objects */
1732                 if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
1733                         r = amdgpu_bo_reserve(robj, false);
1734                         if (r == 0) {
1735                                 amdgpu_bo_unpin(robj);
1736                                 amdgpu_bo_unreserve(robj);
1737                         }
1738                 }
1739         }
1740         /* evict vram memory */
1741         amdgpu_bo_evict_vram(adev);
1742
1743         amdgpu_fence_driver_suspend(adev);
1744
1745         r = amdgpu_suspend(adev);
1746
1747         /* evict remaining vram memory */
1748         amdgpu_bo_evict_vram(adev);
1749
1750         pci_save_state(dev->pdev);
1751         if (suspend) {
1752                 /* Shut down the device */
1753                 pci_disable_device(dev->pdev);
1754                 pci_set_power_state(dev->pdev, PCI_D3hot);
1755         }
1756
1757         if (fbcon) {
1758                 console_lock();
1759                 amdgpu_fbdev_set_suspend(adev, 1);
1760                 console_unlock();
1761         }
1762         return 0;
1763 }
1764
1765 /**
1766  * amdgpu_resume_kms - initiate device resume
1767  *
1768  * @pdev: drm dev pointer
1769  *
1770  * Bring the hw back to operating state (all asics).
1771  * Returns 0 for success or an error on failure.
1772  * Called at driver resume.
1773  */
1774 int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
1775 {
1776         struct drm_connector *connector;
1777         struct amdgpu_device *adev = dev->dev_private;
1778         struct drm_crtc *crtc;
1779         int r;
1780
1781         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1782                 return 0;
1783
1784         if (fbcon) {
1785                 console_lock();
1786         }
1787         if (resume) {
1788                 pci_set_power_state(dev->pdev, PCI_D0);
1789                 pci_restore_state(dev->pdev);
1790                 if (pci_enable_device(dev->pdev)) {
1791                         if (fbcon)
1792                                 console_unlock();
1793                         return -1;
1794                 }
1795         }
1796
1797         /* post card */
1798         if (!amdgpu_card_posted(adev))
1799                 amdgpu_atom_asic_init(adev->mode_info.atom_context);
1800
1801         r = amdgpu_resume(adev);
1802         if (r)
1803                 DRM_ERROR("amdgpu_resume failed (%d).\n", r);
1804
1805         amdgpu_fence_driver_resume(adev);
1806
1807         if (resume) {
1808                 r = amdgpu_ib_ring_tests(adev);
1809                 if (r)
1810                         DRM_ERROR("ib ring test failed (%d).\n", r);
1811         }
1812
1813         r = amdgpu_late_init(adev);
1814         if (r)
1815                 return r;
1816
1817         /* pin cursors */
1818         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1819                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1820
1821                 if (amdgpu_crtc->cursor_bo) {
1822                         struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1823                         r = amdgpu_bo_reserve(aobj, false);
1824                         if (r == 0) {
1825                                 r = amdgpu_bo_pin(aobj,
1826                                                   AMDGPU_GEM_DOMAIN_VRAM,
1827                                                   &amdgpu_crtc->cursor_addr);
1828                                 if (r != 0)
1829                                         DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
1830                                 amdgpu_bo_unreserve(aobj);
1831                         }
1832                 }
1833         }
1834
1835         /* blat the mode back in */
1836         if (fbcon) {
1837                 drm_helper_resume_force_mode(dev);
1838                 /* turn on display hw */
1839                 drm_modeset_lock_all(dev);
1840                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1841                         drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
1842                 }
1843                 drm_modeset_unlock_all(dev);
1844         }
1845
1846         drm_kms_helper_poll_enable(dev);
1847         drm_helper_hpd_irq_event(dev);
1848
1849         if (fbcon) {
1850                 amdgpu_fbdev_set_suspend(adev, 0);
1851                 console_unlock();
1852         }
1853
1854         return 0;
1855 }
1856
1857 /**
1858  * amdgpu_gpu_reset - reset the asic
1859  *
1860  * @adev: amdgpu device pointer
1861  *
1862  * Attempt the reset the GPU if it has hung (all asics).
1863  * Returns 0 for success or an error on failure.
1864  */
1865 int amdgpu_gpu_reset(struct amdgpu_device *adev)
1866 {
1867         unsigned ring_sizes[AMDGPU_MAX_RINGS];
1868         uint32_t *ring_data[AMDGPU_MAX_RINGS];
1869
1870         bool saved = false;
1871
1872         int i, r;
1873         int resched;
1874
1875         atomic_inc(&adev->gpu_reset_counter);
1876
1877         /* block TTM */
1878         resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
1879
1880         r = amdgpu_suspend(adev);
1881
1882         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1883                 struct amdgpu_ring *ring = adev->rings[i];
1884                 if (!ring)
1885                         continue;
1886
1887                 ring_sizes[i] = amdgpu_ring_backup(ring, &ring_data[i]);
1888                 if (ring_sizes[i]) {
1889                         saved = true;
1890                         dev_info(adev->dev, "Saved %d dwords of commands "
1891                                  "on ring %d.\n", ring_sizes[i], i);
1892                 }
1893         }
1894
1895 retry:
1896         r = amdgpu_asic_reset(adev);
1897         if (!r) {
1898                 dev_info(adev->dev, "GPU reset succeeded, trying to resume\n");
1899                 r = amdgpu_resume(adev);
1900         }
1901
1902         if (!r) {
1903                 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1904                         struct amdgpu_ring *ring = adev->rings[i];
1905                         if (!ring)
1906                                 continue;
1907
1908                         amdgpu_ring_restore(ring, ring_sizes[i], ring_data[i]);
1909                         ring_sizes[i] = 0;
1910                         ring_data[i] = NULL;
1911                 }
1912
1913                 r = amdgpu_ib_ring_tests(adev);
1914                 if (r) {
1915                         dev_err(adev->dev, "ib ring test failed (%d).\n", r);
1916                         if (saved) {
1917                                 saved = false;
1918                                 r = amdgpu_suspend(adev);
1919                                 goto retry;
1920                         }
1921                 }
1922         } else {
1923                 amdgpu_fence_driver_force_completion(adev);
1924                 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1925                         if (adev->rings[i])
1926                                 kfree(ring_data[i]);
1927                 }
1928         }
1929
1930         drm_helper_resume_force_mode(adev->ddev);
1931
1932         ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
1933         if (r) {
1934                 /* bad news, how to tell it to userspace ? */
1935                 dev_info(adev->dev, "GPU reset failed\n");
1936         }
1937
1938         return r;
1939 }
1940
1941 #define AMDGPU_DEFAULT_PCIE_GEN_MASK 0x30007  /* gen: chipset 1/2, asic 1/2/3 */
1942 #define AMDGPU_DEFAULT_PCIE_MLW_MASK 0x2f0000 /* 1/2/4/8/16 lanes */
1943
1944 void amdgpu_get_pcie_info(struct amdgpu_device *adev)
1945 {
1946         u32 mask;
1947         int ret;
1948
1949         if (amdgpu_pcie_gen_cap)
1950                 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
1951
1952         if (amdgpu_pcie_lane_cap)
1953                 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
1954
1955         /* covers APUs as well */
1956         if (pci_is_root_bus(adev->pdev->bus)) {
1957                 if (adev->pm.pcie_gen_mask == 0)
1958                         adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
1959                 if (adev->pm.pcie_mlw_mask == 0)
1960                         adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
1961                 return;
1962         }
1963
1964         if (adev->pm.pcie_gen_mask == 0) {
1965                 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
1966                 if (!ret) {
1967                         adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
1968                                                   CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
1969                                                   CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
1970
1971                         if (mask & DRM_PCIE_SPEED_25)
1972                                 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
1973                         if (mask & DRM_PCIE_SPEED_50)
1974                                 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;
1975                         if (mask & DRM_PCIE_SPEED_80)
1976                                 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;
1977                 } else {
1978                         adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
1979                 }
1980         }
1981         if (adev->pm.pcie_mlw_mask == 0) {
1982                 ret = drm_pcie_get_max_link_width(adev->ddev, &mask);
1983                 if (!ret) {
1984                         switch (mask) {
1985                         case 32:
1986                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
1987                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
1988                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
1989                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
1990                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
1991                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
1992                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
1993                                 break;
1994                         case 16:
1995                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
1996                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
1997                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
1998                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
1999                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2000                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2001                                 break;
2002                         case 12:
2003                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2004                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2005                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2006                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2007                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2008                                 break;
2009                         case 8:
2010                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2011                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2012                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2013                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2014                                 break;
2015                         case 4:
2016                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2017                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2018                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2019                                 break;
2020                         case 2:
2021                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2022                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2023                                 break;
2024                         case 1:
2025                                 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
2026                                 break;
2027                         default:
2028                                 break;
2029                         }
2030                 } else {
2031                         adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
2032                 }
2033         }
2034 }
2035
2036 /*
2037  * Debugfs
2038  */
2039 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
2040                              struct drm_info_list *files,
2041                              unsigned nfiles)
2042 {
2043         unsigned i;
2044
2045         for (i = 0; i < adev->debugfs_count; i++) {
2046                 if (adev->debugfs[i].files == files) {
2047                         /* Already registered */
2048                         return 0;
2049                 }
2050         }
2051
2052         i = adev->debugfs_count + 1;
2053         if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) {
2054                 DRM_ERROR("Reached maximum number of debugfs components.\n");
2055                 DRM_ERROR("Report so we increase "
2056                           "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n");
2057                 return -EINVAL;
2058         }
2059         adev->debugfs[adev->debugfs_count].files = files;
2060         adev->debugfs[adev->debugfs_count].num_files = nfiles;
2061         adev->debugfs_count = i;
2062 #if defined(CONFIG_DEBUG_FS)
2063         drm_debugfs_create_files(files, nfiles,
2064                                  adev->ddev->control->debugfs_root,
2065                                  adev->ddev->control);
2066         drm_debugfs_create_files(files, nfiles,
2067                                  adev->ddev->primary->debugfs_root,
2068                                  adev->ddev->primary);
2069 #endif
2070         return 0;
2071 }
2072
2073 static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev)
2074 {
2075 #if defined(CONFIG_DEBUG_FS)
2076         unsigned i;
2077
2078         for (i = 0; i < adev->debugfs_count; i++) {
2079                 drm_debugfs_remove_files(adev->debugfs[i].files,
2080                                          adev->debugfs[i].num_files,
2081                                          adev->ddev->control);
2082                 drm_debugfs_remove_files(adev->debugfs[i].files,
2083                                          adev->debugfs[i].num_files,
2084                                          adev->ddev->primary);
2085         }
2086 #endif
2087 }
2088
2089 #if defined(CONFIG_DEBUG_FS)
2090
2091 static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
2092                                         size_t size, loff_t *pos)
2093 {
2094         struct amdgpu_device *adev = f->f_inode->i_private;
2095         ssize_t result = 0;
2096         int r;
2097
2098         if (size & 0x3 || *pos & 0x3)
2099                 return -EINVAL;
2100
2101         while (size) {
2102                 uint32_t value;
2103
2104                 if (*pos > adev->rmmio_size)
2105                         return result;
2106
2107                 value = RREG32(*pos >> 2);
2108                 r = put_user(value, (uint32_t *)buf);
2109                 if (r)
2110                         return r;
2111
2112                 result += 4;
2113                 buf += 4;
2114                 *pos += 4;
2115                 size -= 4;
2116         }
2117
2118         return result;
2119 }
2120
2121 static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
2122                                          size_t size, loff_t *pos)
2123 {
2124         struct amdgpu_device *adev = f->f_inode->i_private;
2125         ssize_t result = 0;
2126         int r;
2127
2128         if (size & 0x3 || *pos & 0x3)
2129                 return -EINVAL;
2130
2131         while (size) {
2132                 uint32_t value;
2133
2134                 if (*pos > adev->rmmio_size)
2135                         return result;
2136
2137                 r = get_user(value, (uint32_t *)buf);
2138                 if (r)
2139                         return r;
2140
2141                 WREG32(*pos >> 2, value);
2142
2143                 result += 4;
2144                 buf += 4;
2145                 *pos += 4;
2146                 size -= 4;
2147         }
2148
2149         return result;
2150 }
2151
2152 static const struct file_operations amdgpu_debugfs_regs_fops = {
2153         .owner = THIS_MODULE,
2154         .read = amdgpu_debugfs_regs_read,
2155         .write = amdgpu_debugfs_regs_write,
2156         .llseek = default_llseek
2157 };
2158
2159 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
2160 {
2161         struct drm_minor *minor = adev->ddev->primary;
2162         struct dentry *ent, *root = minor->debugfs_root;
2163
2164         ent = debugfs_create_file("amdgpu_regs", S_IFREG | S_IRUGO, root,
2165                                   adev, &amdgpu_debugfs_regs_fops);
2166         if (IS_ERR(ent))
2167                 return PTR_ERR(ent);
2168         i_size_write(ent->d_inode, adev->rmmio_size);
2169         adev->debugfs_regs = ent;
2170
2171         return 0;
2172 }
2173
2174 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev)
2175 {
2176         debugfs_remove(adev->debugfs_regs);
2177         adev->debugfs_regs = NULL;
2178 }
2179
2180 int amdgpu_debugfs_init(struct drm_minor *minor)
2181 {
2182         return 0;
2183 }
2184
2185 void amdgpu_debugfs_cleanup(struct drm_minor *minor)
2186 {
2187 }
2188 #else
2189 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
2190 {
2191         return 0;
2192 }
2193 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { }
2194 #endif