drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/console.h>
  29 #include <linux/slab.h>
  30 #include <linux/debugfs.h>
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc_helper.h>
  33 #include <drm/amdgpu_drm.h>
  34 #include <linux/vgaarb.h>
  35 #include <linux/vga_switcheroo.h>
  36 #include <linux/efi.h>
  37 #include "amdgpu.h"
  38 #include "amdgpu_i2c.h"
  39 #include "atom.h"
  40 #include "amdgpu_atombios.h"
  41 #ifdef CONFIG_DRM_AMDGPU_CIK
  42 #include "cik.h"
  43 #endif
  44 #include "vi.h"
  45 #include "bif/bif_4_1_d.h"
  46
  47 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev);
  48 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev);
  49
  50 static const char *amdgpu_asic_name[] = {
  51         "BONAIRE",
  52         "KAVERI",
  53         "KABINI",
  54         "HAWAII",
  55         "MULLINS",
  56         "TOPAZ",
  57         "TONGA",
  58         "FIJI",
  59         "CARRIZO",
  60         "LAST",
  61 };
  62
  63 bool amdgpu_device_is_px(struct drm_device *dev)
  64 {
  65         struct amdgpu_device *adev = dev->dev_private;
  66
  67         if (adev->flags & AMD_IS_PX)
  68                 return true;
  69         return false;
  70 }
  71
  72 /*
  73  * MMIO register access helper functions.
  74  */
  75 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
  76                         bool always_indirect)
  77 {
  78         if ((reg * 4) < adev->rmmio_size && !always_indirect)
  79                 return readl(((void __iomem *)adev->rmmio) + (reg * 4));
  80         else {
  81                 unsigned long flags;
  82                 uint32_t ret;
  83
  84                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
  85                 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
  86                 ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
  87                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
  88
  89                 return ret;
  90         }
  91 }
  92
  93 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
  94                     bool always_indirect)
  95 {
  96         if ((reg * 4) < adev->rmmio_size && !always_indirect)
  97                 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
  98         else {
  99                 unsigned long flags;
 100
 101                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
 102                 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
 103                 writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
 104                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
 105         }
 106 }
 107
 108 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
 109 {
 110         if ((reg * 4) < adev->rio_mem_size)
 111                 return ioread32(adev->rio_mem + (reg * 4));
 112         else {
 113                 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
 114                 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
 115         }
 116 }
 117
 118 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 119 {
 120
 121         if ((reg * 4) < adev->rio_mem_size)
 122                 iowrite32(v, adev->rio_mem + (reg * 4));
 123         else {
 124                 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
 125                 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
 126         }
 127 }
 128
 129 /**
 130  * amdgpu_mm_rdoorbell - read a doorbell dword
 131  *
 132  * @adev: amdgpu_device pointer
 133  * @index: doorbell index
 134  *
 135  * Returns the value in the doorbell aperture at the
 136  * requested doorbell index (CIK).
 137  */
 138 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
 139 {
 140         if (index < adev->doorbell.num_doorbells) {
 141                 return readl(adev->doorbell.ptr + index);
 142         } else {
 143                 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
 144                 return 0;
 145         }
 146 }
 147
 148 /**
 149  * amdgpu_mm_wdoorbell - write a doorbell dword
 150  *
 151  * @adev: amdgpu_device pointer
 152  * @index: doorbell index
 153  * @v: value to write
 154  *
 155  * Writes @v to the doorbell aperture at the
 156  * requested doorbell index (CIK).
 157  */
 158 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
 159 {
 160         if (index < adev->doorbell.num_doorbells) {
 161                 writel(v, adev->doorbell.ptr + index);
 162         } else {
 163                 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
 164         }
 165 }
 166
 167 /**
 168  * amdgpu_invalid_rreg - dummy reg read function
 169  *
 170  * @adev: amdgpu device pointer
 171  * @reg: offset of register
 172  *
 173  * Dummy register read function.  Used for register blocks
 174  * that certain asics don't have (all asics).
 175  * Returns the value in the register.
 176  */
 177 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
 178 {
 179         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
 180         BUG();
 181         return 0;
 182 }
 183
 184 /**
 185  * amdgpu_invalid_wreg - dummy reg write function
 186  *
 187  * @adev: amdgpu device pointer
 188  * @reg: offset of register
 189  * @v: value to write to the register
 190  *
 191  * Dummy register read function.  Used for register blocks
 192  * that certain asics don't have (all asics).
 193  */
 194 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
 195 {
 196         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
 197                   reg, v);
 198         BUG();
 199 }
 200
 201 /**
 202  * amdgpu_block_invalid_rreg - dummy reg read function
 203  *
 204  * @adev: amdgpu device pointer
 205  * @block: offset of instance
 206  * @reg: offset of register
 207  *
 208  * Dummy register read function.  Used for register blocks
 209  * that certain asics don't have (all asics).
 210  * Returns the value in the register.
 211  */
 212 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
 213                                           uint32_t block, uint32_t reg)
 214 {
 215         DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
 216                   reg, block);
 217         BUG();
 218         return 0;
 219 }
 220
 221 /**
 222  * amdgpu_block_invalid_wreg - dummy reg write function
 223  *
 224  * @adev: amdgpu device pointer
 225  * @block: offset of instance
 226  * @reg: offset of register
 227  * @v: value to write to the register
 228  *
 229  * Dummy register read function.  Used for register blocks
 230  * that certain asics don't have (all asics).
 231  */
 232 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
 233                                       uint32_t block,
 234                                       uint32_t reg, uint32_t v)
 235 {
 236         DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
 237                   reg, block, v);
 238         BUG();
 239 }
 240
 241 static int amdgpu_vram_scratch_init(struct amdgpu_device *adev)
 242 {
 243         int r;
 244
 245         if (adev->vram_scratch.robj == NULL) {
 246                 r = amdgpu_bo_create(adev, AMDGPU_GPU_PAGE_SIZE,
 247                                      PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM,
 248                                      AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
 249                                      NULL, &adev->vram_scratch.robj);
 250                 if (r) {
 251                         return r;
 252                 }
 253         }
 254
 255         r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
 256         if (unlikely(r != 0))
 257                 return r;
 258         r = amdgpu_bo_pin(adev->vram_scratch.robj,
 259                           AMDGPU_GEM_DOMAIN_VRAM, &adev->vram_scratch.gpu_addr);
 260         if (r) {
 261                 amdgpu_bo_unreserve(adev->vram_scratch.robj);
 262                 return r;
 263         }
 264         r = amdgpu_bo_kmap(adev->vram_scratch.robj,
 265                                 (void **)&adev->vram_scratch.ptr);
 266         if (r)
 267                 amdgpu_bo_unpin(adev->vram_scratch.robj);
 268         amdgpu_bo_unreserve(adev->vram_scratch.robj);
 269
 270         return r;
 271 }
 272
 273 static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev)
 274 {
 275         int r;
 276
 277         if (adev->vram_scratch.robj == NULL) {
 278                 return;
 279         }
 280         r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
 281         if (likely(r == 0)) {
 282                 amdgpu_bo_kunmap(adev->vram_scratch.robj);
 283                 amdgpu_bo_unpin(adev->vram_scratch.robj);
 284                 amdgpu_bo_unreserve(adev->vram_scratch.robj);
 285         }
 286         amdgpu_bo_unref(&adev->vram_scratch.robj);
 287 }
 288
 289 /**
 290  * amdgpu_program_register_sequence - program an array of registers.
 291  *
 292  * @adev: amdgpu_device pointer
 293  * @registers: pointer to the register array
 294  * @array_size: size of the register array
 295  *
 296  * Programs an array or registers with and and or masks.
 297  * This is a helper for setting golden registers.
 298  */
 299 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
 300                                       const u32 *registers,
 301                                       const u32 array_size)
 302 {
 303         u32 tmp, reg, and_mask, or_mask;
 304         int i;
 305
 306         if (array_size % 3)
 307                 return;
 308
 309         for (i = 0; i < array_size; i +=3) {
 310                 reg = registers[i + 0];
 311                 and_mask = registers[i + 1];
 312                 or_mask = registers[i + 2];
 313
 314                 if (and_mask == 0xffffffff) {
 315                         tmp = or_mask;
 316                 } else {
 317                         tmp = RREG32(reg);
 318                         tmp &= ~and_mask;
 319                         tmp |= or_mask;
 320                 }
 321                 WREG32(reg, tmp);
 322         }
 323 }
 324
 325 void amdgpu_pci_config_reset(struct amdgpu_device *adev)
 326 {
 327         pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
 328 }
 329
 330 /*
 331  * GPU doorbell aperture helpers function.
 332  */
 333 /**
 334  * amdgpu_doorbell_init - Init doorbell driver information.
 335  *
 336  * @adev: amdgpu_device pointer
 337  *
 338  * Init doorbell driver information (CIK)
 339  * Returns 0 on success, error on failure.
 340  */
 341 static int amdgpu_doorbell_init(struct amdgpu_device *adev)
 342 {
 343         /* doorbell bar mapping */
 344         adev->doorbell.base = pci_resource_start(adev->pdev, 2);
 345         adev->doorbell.size = pci_resource_len(adev->pdev, 2);
 346
 347         adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
 348                                              AMDGPU_DOORBELL_MAX_ASSIGNMENT+1);
 349         if (adev->doorbell.num_doorbells == 0)
 350                 return -EINVAL;
 351
 352         adev->doorbell.ptr = ioremap(adev->doorbell.base, adev->doorbell.num_doorbells * sizeof(u32));
 353         if (adev->doorbell.ptr == NULL) {
 354                 return -ENOMEM;
 355         }
 356         DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)adev->doorbell.base);
 357         DRM_INFO("doorbell mmio size: %u\n", (unsigned)adev->doorbell.size);
 358
 359         return 0;
 360 }
 361
 362 /**
 363  * amdgpu_doorbell_fini - Tear down doorbell driver information.
 364  *
 365  * @adev: amdgpu_device pointer
 366  *
 367  * Tear down doorbell driver information (CIK)
 368  */
 369 static void amdgpu_doorbell_fini(struct amdgpu_device *adev)
 370 {
 371         iounmap(adev->doorbell.ptr);
 372         adev->doorbell.ptr = NULL;
 373 }
 374
 375 /**
 376  * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
 377  *                                setup amdkfd
 378  *
 379  * @adev: amdgpu_device pointer
 380  * @aperture_base: output returning doorbell aperture base physical address
 381  * @aperture_size: output returning doorbell aperture size in bytes
 382  * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
 383  *
 384  * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
 385  * takes doorbells required for its own rings and reports the setup to amdkfd.
 386  * amdgpu reserved doorbells are at the start of the doorbell aperture.
 387  */
 388 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
 389                                 phys_addr_t *aperture_base,
 390                                 size_t *aperture_size,
 391                                 size_t *start_offset)
 392 {
 393         /*
 394          * The first num_doorbells are used by amdgpu.
 395          * amdkfd takes whatever's left in the aperture.
 396          */
 397         if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
 398                 *aperture_base = adev->doorbell.base;
 399                 *aperture_size = adev->doorbell.size;
 400                 *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
 401         } else {
 402                 *aperture_base = 0;
 403                 *aperture_size = 0;
 404                 *start_offset = 0;
 405         }
 406 }
 407
 408 /*
 409  * amdgpu_wb_*()
 410  * Writeback is the the method by which the the GPU updates special pages
 411  * in memory with the status of certain GPU events (fences, ring pointers,
 412  * etc.).
 413  */
 414
 415 /**
 416  * amdgpu_wb_fini - Disable Writeback and free memory
 417  *
 418  * @adev: amdgpu_device pointer
 419  *
 420  * Disables Writeback and frees the Writeback memory (all asics).
 421  * Used at driver shutdown.
 422  */
 423 static void amdgpu_wb_fini(struct amdgpu_device *adev)
 424 {
 425         if (adev->wb.wb_obj) {
 426                 if (!amdgpu_bo_reserve(adev->wb.wb_obj, false)) {
 427                         amdgpu_bo_kunmap(adev->wb.wb_obj);
 428                         amdgpu_bo_unpin(adev->wb.wb_obj);
 429                         amdgpu_bo_unreserve(adev->wb.wb_obj);
 430                 }
 431                 amdgpu_bo_unref(&adev->wb.wb_obj);
 432                 adev->wb.wb = NULL;
 433                 adev->wb.wb_obj = NULL;
 434         }
 435 }
 436
 437 /**
 438  * amdgpu_wb_init- Init Writeback driver info and allocate memory
 439  *
 440  * @adev: amdgpu_device pointer
 441  *
 442  * Disables Writeback and frees the Writeback memory (all asics).
 443  * Used at driver startup.
 444  * Returns 0 on success or an -error on failure.
 445  */
 446 static int amdgpu_wb_init(struct amdgpu_device *adev)
 447 {
 448         int r;
 449
 450         if (adev->wb.wb_obj == NULL) {
 451                 r = amdgpu_bo_create(adev, AMDGPU_MAX_WB * 4, PAGE_SIZE, true,
 452                                      AMDGPU_GEM_DOMAIN_GTT, 0,  NULL, &adev->wb.wb_obj);
 453                 if (r) {
 454                         dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
 455                         return r;
 456                 }
 457                 r = amdgpu_bo_reserve(adev->wb.wb_obj, false);
 458                 if (unlikely(r != 0)) {
 459                         amdgpu_wb_fini(adev);
 460                         return r;
 461                 }
 462                 r = amdgpu_bo_pin(adev->wb.wb_obj, AMDGPU_GEM_DOMAIN_GTT,
 463                                 &adev->wb.gpu_addr);
 464                 if (r) {
 465                         amdgpu_bo_unreserve(adev->wb.wb_obj);
 466                         dev_warn(adev->dev, "(%d) pin WB bo failed\n", r);
 467                         amdgpu_wb_fini(adev);
 468                         return r;
 469                 }
 470                 r = amdgpu_bo_kmap(adev->wb.wb_obj, (void **)&adev->wb.wb);
 471                 amdgpu_bo_unreserve(adev->wb.wb_obj);
 472                 if (r) {
 473                         dev_warn(adev->dev, "(%d) map WB bo failed\n", r);
 474                         amdgpu_wb_fini(adev);
 475                         return r;
 476                 }
 477
 478                 adev->wb.num_wb = AMDGPU_MAX_WB;
 479                 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
 480
 481                 /* clear wb memory */
 482                 memset((char *)adev->wb.wb, 0, AMDGPU_GPU_PAGE_SIZE);
 483         }
 484
 485         return 0;
 486 }
 487
 488 /**
 489  * amdgpu_wb_get - Allocate a wb entry
 490  *
 491  * @adev: amdgpu_device pointer
 492  * @wb: wb index
 493  *
 494  * Allocate a wb slot for use by the driver (all asics).
 495  * Returns 0 on success or -EINVAL on failure.
 496  */
 497 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb)
 498 {
 499         unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
 500         if (offset < adev->wb.num_wb) {
 501                 __set_bit(offset, adev->wb.used);
 502                 *wb = offset;
 503                 return 0;
 504         } else {
 505                 return -EINVAL;
 506         }
 507 }
 508
 509 /**
 510  * amdgpu_wb_free - Free a wb entry
 511  *
 512  * @adev: amdgpu_device pointer
 513  * @wb: wb index
 514  *
 515  * Free a wb slot allocated for use by the driver (all asics)
 516  */
 517 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb)
 518 {
 519         if (wb < adev->wb.num_wb)
 520                 __clear_bit(wb, adev->wb.used);
 521 }
 522
 523 /**
 524  * amdgpu_vram_location - try to find VRAM location
 525  * @adev: amdgpu device structure holding all necessary informations
 526  * @mc: memory controller structure holding memory informations
 527  * @base: base address at which to put VRAM
 528  *
 529  * Function will place try to place VRAM at base address provided
 530  * as parameter (which is so far either PCI aperture address or
 531  * for IGP TOM base address).
 532  *
 533  * If there is not enough space to fit the unvisible VRAM in the 32bits
 534  * address space then we limit the VRAM size to the aperture.
 535  *
 536  * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
 537  * this shouldn't be a problem as we are using the PCI aperture as a reference.
 538  * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
 539  * not IGP.
 540  *
 541  * Note: we use mc_vram_size as on some board we need to program the mc to
 542  * cover the whole aperture even if VRAM size is inferior to aperture size
 543  * Novell bug 204882 + along with lots of ubuntu ones
 544  *
 545  * Note: when limiting vram it's safe to overwritte real_vram_size because
 546  * we are not in case where real_vram_size is inferior to mc_vram_size (ie
 547  * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
 548  * ones)
 549  *
 550  * Note: IGP TOM addr should be the same as the aperture addr, we don't
 551  * explicitly check for that thought.
 552  *
 553  * FIXME: when reducing VRAM size align new size on power of 2.
 554  */
 555 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base)
 556 {
 557         uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
 558
 559         mc->vram_start = base;
 560         if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) {
 561                 dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n");
 562                 mc->real_vram_size = mc->aper_size;
 563                 mc->mc_vram_size = mc->aper_size;
 564         }
 565         mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
 566         if (limit && limit < mc->real_vram_size)
 567                 mc->real_vram_size = limit;
 568         dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
 569                         mc->mc_vram_size >> 20, mc->vram_start,
 570                         mc->vram_end, mc->real_vram_size >> 20);
 571 }
 572
 573 /**
 574  * amdgpu_gtt_location - try to find GTT location
 575  * @adev: amdgpu device structure holding all necessary informations
 576  * @mc: memory controller structure holding memory informations
 577  *
 578  * Function will place try to place GTT before or after VRAM.
 579  *
 580  * If GTT size is bigger than space left then we ajust GTT size.
 581  * Thus function will never fails.
 582  *
 583  * FIXME: when reducing GTT size align new size on power of 2.
 584  */
 585 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc)
 586 {
 587         u64 size_af, size_bf;
 588
 589         size_af = ((adev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
 590         size_bf = mc->vram_start & ~mc->gtt_base_align;
 591         if (size_bf > size_af) {
 592                 if (mc->gtt_size > size_bf) {
 593                         dev_warn(adev->dev, "limiting GTT\n");
 594                         mc->gtt_size = size_bf;
 595                 }
 596                 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
 597         } else {
 598                 if (mc->gtt_size > size_af) {
 599                         dev_warn(adev->dev, "limiting GTT\n");
 600                         mc->gtt_size = size_af;
 601                 }
 602                 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
 603         }
 604         mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
 605         dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
 606                         mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
 607 }
 608
 609 /*
 610  * GPU helpers function.
 611  */
 612 /**
 613  * amdgpu_card_posted - check if the hw has already been initialized
 614  *
 615  * @adev: amdgpu_device pointer
 616  *
 617  * Check if the asic has been initialized (all asics).
 618  * Used at driver startup.
 619  * Returns true if initialized or false if not.
 620  */
 621 bool amdgpu_card_posted(struct amdgpu_device *adev)
 622 {
 623         uint32_t reg;
 624
 625         /* then check MEM_SIZE, in case the crtcs are off */
 626         reg = RREG32(mmCONFIG_MEMSIZE);
 627
 628         if (reg)
 629                 return true;
 630
 631         return false;
 632
 633 }
 634
 635 /**
 636  * amdgpu_boot_test_post_card - check and possibly initialize the hw
 637  *
 638  * @adev: amdgpu_device pointer
 639  *
 640  * Check if the asic is initialized and if not, attempt to initialize
 641  * it (all asics).
 642  * Returns true if initialized or false if not.
 643  */
 644 bool amdgpu_boot_test_post_card(struct amdgpu_device *adev)
 645 {
 646         if (amdgpu_card_posted(adev))
 647                 return true;
 648
 649         if (adev->bios) {
 650                 DRM_INFO("GPU not posted. posting now...\n");
 651                 if (adev->is_atom_bios)
 652                         amdgpu_atom_asic_init(adev->mode_info.atom_context);
 653                 return true;
 654         } else {
 655                 dev_err(adev->dev, "Card not posted and no BIOS - ignoring\n");
 656                 return false;
 657         }
 658 }
 659
 660 /**
 661  * amdgpu_dummy_page_init - init dummy page used by the driver
 662  *
 663  * @adev: amdgpu_device pointer
 664  *
 665  * Allocate the dummy page used by the driver (all asics).
 666  * This dummy page is used by the driver as a filler for gart entries
 667  * when pages are taken out of the GART
 668  * Returns 0 on sucess, -ENOMEM on failure.
 669  */
 670 int amdgpu_dummy_page_init(struct amdgpu_device *adev)
 671 {
 672         if (adev->dummy_page.page)
 673                 return 0;
 674         adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
 675         if (adev->dummy_page.page == NULL)
 676                 return -ENOMEM;
 677         adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page,
 678                                         0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 679         if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) {
 680                 dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
 681                 __free_page(adev->dummy_page.page);
 682                 adev->dummy_page.page = NULL;
 683                 return -ENOMEM;
 684         }
 685         return 0;
 686 }
 687
 688 /**
 689  * amdgpu_dummy_page_fini - free dummy page used by the driver
 690  *
 691  * @adev: amdgpu_device pointer
 692  *
 693  * Frees the dummy page used by the driver (all asics).
 694  */
 695 void amdgpu_dummy_page_fini(struct amdgpu_device *adev)
 696 {
 697         if (adev->dummy_page.page == NULL)
 698                 return;
 699         pci_unmap_page(adev->pdev, adev->dummy_page.addr,
 700                         PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 701         __free_page(adev->dummy_page.page);
 702         adev->dummy_page.page = NULL;
 703 }
 704
 705
 706 /* ATOM accessor methods */
 707 /*
 708  * ATOM is an interpreted byte code stored in tables in the vbios.  The
 709  * driver registers callbacks to access registers and the interpreter
 710  * in the driver parses the tables and executes then to program specific
 711  * actions (set display modes, asic init, etc.).  See amdgpu_atombios.c,
 712  * atombios.h, and atom.c
 713  */
 714
 715 /**
 716  * cail_pll_read - read PLL register
 717  *
 718  * @info: atom card_info pointer
 719  * @reg: PLL register offset
 720  *
 721  * Provides a PLL register accessor for the atom interpreter (r4xx+).
 722  * Returns the value of the PLL register.
 723  */
 724 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
 725 {
 726         return 0;
 727 }
 728
 729 /**
 730  * cail_pll_write - write PLL register
 731  *
 732  * @info: atom card_info pointer
 733  * @reg: PLL register offset
 734  * @val: value to write to the pll register
 735  *
 736  * Provides a PLL register accessor for the atom interpreter (r4xx+).
 737  */
 738 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
 739 {
 740
 741 }
 742
 743 /**
 744  * cail_mc_read - read MC (Memory Controller) register
 745  *
 746  * @info: atom card_info pointer
 747  * @reg: MC register offset
 748  *
 749  * Provides an MC register accessor for the atom interpreter (r4xx+).
 750  * Returns the value of the MC register.
 751  */
 752 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
 753 {
 754         return 0;
 755 }
 756
 757 /**
 758  * cail_mc_write - write MC (Memory Controller) register
 759  *
 760  * @info: atom card_info pointer
 761  * @reg: MC register offset
 762  * @val: value to write to the pll register
 763  *
 764  * Provides a MC register accessor for the atom interpreter (r4xx+).
 765  */
 766 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
 767 {
 768
 769 }
 770
 771 /**
 772  * cail_reg_write - write MMIO register
 773  *
 774  * @info: atom card_info pointer
 775  * @reg: MMIO register offset
 776  * @val: value to write to the pll register
 777  *
 778  * Provides a MMIO register accessor for the atom interpreter (r4xx+).
 779  */
 780 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
 781 {
 782         struct amdgpu_device *adev = info->dev->dev_private;
 783
 784         WREG32(reg, val);
 785 }
 786
 787 /**
 788  * cail_reg_read - read MMIO register
 789  *
 790  * @info: atom card_info pointer
 791  * @reg: MMIO register offset
 792  *
 793  * Provides an MMIO register accessor for the atom interpreter (r4xx+).
 794  * Returns the value of the MMIO register.
 795  */
 796 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
 797 {
 798         struct amdgpu_device *adev = info->dev->dev_private;
 799         uint32_t r;
 800
 801         r = RREG32(reg);
 802         return r;
 803 }
 804
 805 /**
 806  * cail_ioreg_write - write IO register
 807  *
 808  * @info: atom card_info pointer
 809  * @reg: IO register offset
 810  * @val: value to write to the pll register
 811  *
 812  * Provides a IO register accessor for the atom interpreter (r4xx+).
 813  */
 814 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
 815 {
 816         struct amdgpu_device *adev = info->dev->dev_private;
 817
 818         WREG32_IO(reg, val);
 819 }
 820
 821 /**
 822  * cail_ioreg_read - read IO register
 823  *
 824  * @info: atom card_info pointer
 825  * @reg: IO register offset
 826  *
 827  * Provides an IO register accessor for the atom interpreter (r4xx+).
 828  * Returns the value of the IO register.
 829  */
 830 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
 831 {
 832         struct amdgpu_device *adev = info->dev->dev_private;
 833         uint32_t r;
 834
 835         r = RREG32_IO(reg);
 836         return r;
 837 }
 838
 839 /**
 840  * amdgpu_atombios_fini - free the driver info and callbacks for atombios
 841  *
 842  * @adev: amdgpu_device pointer
 843  *
 844  * Frees the driver info and register access callbacks for the ATOM
 845  * interpreter (r4xx+).
 846  * Called at driver shutdown.
 847  */
 848 static void amdgpu_atombios_fini(struct amdgpu_device *adev)
 849 {
 850         if (adev->mode_info.atom_context)
 851                 kfree(adev->mode_info.atom_context->scratch);
 852         kfree(adev->mode_info.atom_context);
 853         adev->mode_info.atom_context = NULL;
 854         kfree(adev->mode_info.atom_card_info);
 855         adev->mode_info.atom_card_info = NULL;
 856 }
 857
 858 /**
 859  * amdgpu_atombios_init - init the driver info and callbacks for atombios
 860  *
 861  * @adev: amdgpu_device pointer
 862  *
 863  * Initializes the driver info and register access callbacks for the
 864  * ATOM interpreter (r4xx+).
 865  * Returns 0 on sucess, -ENOMEM on failure.
 866  * Called at driver startup.
 867  */
 868 static int amdgpu_atombios_init(struct amdgpu_device *adev)
 869 {
 870         struct card_info *atom_card_info =
 871             kzalloc(sizeof(struct card_info), GFP_KERNEL);
 872
 873         if (!atom_card_info)
 874                 return -ENOMEM;
 875
 876         adev->mode_info.atom_card_info = atom_card_info;
 877         atom_card_info->dev = adev->ddev;
 878         atom_card_info->reg_read = cail_reg_read;
 879         atom_card_info->reg_write = cail_reg_write;
 880         /* needed for iio ops */
 881         if (adev->rio_mem) {
 882                 atom_card_info->ioreg_read = cail_ioreg_read;
 883                 atom_card_info->ioreg_write = cail_ioreg_write;
 884         } else {
 885                 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
 886                 atom_card_info->ioreg_read = cail_reg_read;
 887                 atom_card_info->ioreg_write = cail_reg_write;
 888         }
 889         atom_card_info->mc_read = cail_mc_read;
 890         atom_card_info->mc_write = cail_mc_write;
 891         atom_card_info->pll_read = cail_pll_read;
 892         atom_card_info->pll_write = cail_pll_write;
 893
 894         adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios);
 895         if (!adev->mode_info.atom_context) {
 896                 amdgpu_atombios_fini(adev);
 897                 return -ENOMEM;
 898         }
 899
 900         mutex_init(&adev->mode_info.atom_context->mutex);
 901         amdgpu_atombios_scratch_regs_init(adev);
 902         amdgpu_atom_allocate_fb_scratch(adev->mode_info.atom_context);
 903         return 0;
 904 }
 905
 906 /* if we get transitioned to only one device, take VGA back */
 907 /**
 908  * amdgpu_vga_set_decode - enable/disable vga decode
 909  *
 910  * @cookie: amdgpu_device pointer
 911  * @state: enable/disable vga decode
 912  *
 913  * Enable/disable vga decode (all asics).
 914  * Returns VGA resource flags.
 915  */
 916 static unsigned int amdgpu_vga_set_decode(void *cookie, bool state)
 917 {
 918         struct amdgpu_device *adev = cookie;
 919         amdgpu_asic_set_vga_state(adev, state);
 920         if (state)
 921                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 922                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 923         else
 924                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 925 }
 926
 927 /**
 928  * amdgpu_check_pot_argument - check that argument is a power of two
 929  *
 930  * @arg: value to check
 931  *
 932  * Validates that a certain argument is a power of two (all asics).
 933  * Returns true if argument is valid.
 934  */
 935 static bool amdgpu_check_pot_argument(int arg)
 936 {
 937         return (arg & (arg - 1)) == 0;
 938 }
 939
 940 /**
 941  * amdgpu_check_arguments - validate module params
 942  *
 943  * @adev: amdgpu_device pointer
 944  *
 945  * Validates certain module parameters and updates
 946  * the associated values used by the driver (all asics).
 947  */
 948 static void amdgpu_check_arguments(struct amdgpu_device *adev)
 949 {
 950         /* vramlimit must be a power of two */
 951         if (!amdgpu_check_pot_argument(amdgpu_vram_limit)) {
 952                 dev_warn(adev->dev, "vram limit (%d) must be a power of 2\n",
 953                                 amdgpu_vram_limit);
 954                 amdgpu_vram_limit = 0;
 955         }
 956
 957         if (amdgpu_gart_size != -1) {
 958                 /* gtt size must be power of two and greater or equal to 32M */
 959                 if (amdgpu_gart_size < 32) {
 960                         dev_warn(adev->dev, "gart size (%d) too small\n",
 961                                  amdgpu_gart_size);
 962                         amdgpu_gart_size = -1;
 963                 } else if (!amdgpu_check_pot_argument(amdgpu_gart_size)) {
 964                         dev_warn(adev->dev, "gart size (%d) must be a power of 2\n",
 965                                  amdgpu_gart_size);
 966                         amdgpu_gart_size = -1;
 967                 }
 968         }
 969
 970         if (!amdgpu_check_pot_argument(amdgpu_vm_size)) {
 971                 dev_warn(adev->dev, "VM size (%d) must be a power of 2\n",
 972                          amdgpu_vm_size);
 973                 amdgpu_vm_size = 8;
 974         }
 975
 976         if (amdgpu_vm_size < 1) {
 977                 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
 978                          amdgpu_vm_size);
 979                 amdgpu_vm_size = 8;
 980         }
 981
 982         /*
 983          * Max GPUVM size for Cayman, SI and CI are 40 bits.
 984          */
 985         if (amdgpu_vm_size > 1024) {
 986                 dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n",
 987                          amdgpu_vm_size);
 988                 amdgpu_vm_size = 8;
 989         }
 990
 991         /* defines number of bits in page table versus page directory,
 992          * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
 993          * page table and the remaining bits are in the page directory */
 994         if (amdgpu_vm_block_size == -1) {
 995
 996                 /* Total bits covered by PD + PTs */
 997                 unsigned bits = ilog2(amdgpu_vm_size) + 18;
 998
 999                 /* Make sure the PD is 4K in size up to 8GB address space.
1000                    Above that split equal between PD and PTs */
1001                 if (amdgpu_vm_size <= 8)
1002                         amdgpu_vm_block_size = bits - 9;
1003                 else
1004                         amdgpu_vm_block_size = (bits + 3) / 2;
1005
1006         } else if (amdgpu_vm_block_size < 9) {
1007                 dev_warn(adev->dev, "VM page table size (%d) too small\n",
1008                          amdgpu_vm_block_size);
1009                 amdgpu_vm_block_size = 9;
1010         }
1011
1012         if (amdgpu_vm_block_size > 24 ||
1013             (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) {
1014                 dev_warn(adev->dev, "VM page table size (%d) too large\n",
1015                          amdgpu_vm_block_size);
1016                 amdgpu_vm_block_size = 9;
1017         }
1018 }
1019
1020 /**
1021  * amdgpu_switcheroo_set_state - set switcheroo state
1022  *
1023  * @pdev: pci dev pointer
1024  * @state: vga switcheroo state
1025  *
1026  * Callback for the switcheroo driver.  Suspends or resumes the
1027  * the asics before or after it is powered up using ACPI methods.
1028  */
1029 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1030 {
1031         struct drm_device *dev = pci_get_drvdata(pdev);
1032
1033         if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1034                 return;
1035
1036         if (state == VGA_SWITCHEROO_ON) {
1037                 unsigned d3_delay = dev->pdev->d3_delay;
1038
1039                 printk(KERN_INFO "amdgpu: switched on\n");
1040                 /* don't suspend or resume card normally */
1041                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1042
1043                 amdgpu_resume_kms(dev, true, true);
1044
1045                 dev->pdev->d3_delay = d3_delay;
1046
1047                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1048                 drm_kms_helper_poll_enable(dev);
1049         } else {
1050                 printk(KERN_INFO "amdgpu: switched off\n");
1051                 drm_kms_helper_poll_disable(dev);
1052                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1053                 amdgpu_suspend_kms(dev, true, true);
1054                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1055         }
1056 }
1057
1058 /**
1059  * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1060  *
1061  * @pdev: pci dev pointer
1062  *
1063  * Callback for the switcheroo driver.  Check of the switcheroo
1064  * state can be changed.
1065  * Returns true if the state can be changed, false if not.
1066  */
1067 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1068 {
1069         struct drm_device *dev = pci_get_drvdata(pdev);
1070
1071         /*
1072         * FIXME: open_count is protected by drm_global_mutex but that would lead to
1073         * locking inversion with the driver load path. And the access here is
1074         * completely racy anyway. So don't bother with locking for now.
1075         */
1076         return dev->open_count == 0;
1077 }
1078
1079 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1080         .set_gpu_state = amdgpu_switcheroo_set_state,
1081         .reprobe = NULL,
1082         .can_switch = amdgpu_switcheroo_can_switch,
1083 };
1084
1085 int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
1086                                   enum amd_ip_block_type block_type,
1087                                   enum amd_clockgating_state state)
1088 {
1089         int i, r = 0;
1090
1091         for (i = 0; i < adev->num_ip_blocks; i++) {
1092                 if (adev->ip_blocks[i].type == block_type) {
1093                         r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1094                                                                             state);
1095                         if (r)
1096                                 return r;
1097                 }
1098         }
1099         return r;
1100 }
1101
1102 int amdgpu_set_powergating_state(struct amdgpu_device *adev,
1103                                   enum amd_ip_block_type block_type,
1104                                   enum amd_powergating_state state)
1105 {
1106         int i, r = 0;
1107
1108         for (i = 0; i < adev->num_ip_blocks; i++) {
1109                 if (adev->ip_blocks[i].type == block_type) {
1110                         r = adev->ip_blocks[i].funcs->set_powergating_state((void *)adev,
1111                                                                             state);
1112                         if (r)
1113                                 return r;
1114                 }
1115         }
1116         return r;
1117 }
1118
1119 const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
1120                                         struct amdgpu_device *adev,
1121                                         enum amd_ip_block_type type)
1122 {
1123         int i;
1124
1125         for (i = 0; i < adev->num_ip_blocks; i++)
1126                 if (adev->ip_blocks[i].type == type)
1127                         return &adev->ip_blocks[i];
1128
1129         return NULL;
1130 }
1131
1132 /**
1133  * amdgpu_ip_block_version_cmp
1134  *
1135  * @adev: amdgpu_device pointer
1136  * @type: enum amd_ip_block_type
1137  * @major: major version
1138  * @minor: minor version
1139  *
1140  * return 0 if equal or greater
1141  * return 1 if smaller or the ip_block doesn't exist
1142  */
1143 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
1144                                 enum amd_ip_block_type type,
1145                                 u32 major, u32 minor)
1146 {
1147         const struct amdgpu_ip_block_version *ip_block;
1148         ip_block = amdgpu_get_ip_block(adev, type);
1149
1150         if (ip_block && ((ip_block->major > major) ||
1151                         ((ip_block->major == major) &&
1152                         (ip_block->minor >= minor))))
1153                 return 0;
1154
1155         return 1;
1156 }
1157
1158 static int amdgpu_early_init(struct amdgpu_device *adev)
1159 {
1160         int i, r;
1161
1162         switch (adev->asic_type) {
1163         case CHIP_TOPAZ:
1164         case CHIP_TONGA:
1165         case CHIP_FIJI:
1166         case CHIP_CARRIZO:
1167                 if (adev->asic_type == CHIP_CARRIZO)
1168                         adev->family = AMDGPU_FAMILY_CZ;
1169                 else
1170                         adev->family = AMDGPU_FAMILY_VI;
1171
1172                 r = vi_set_ip_blocks(adev);
1173                 if (r)
1174                         return r;
1175                 break;
1176 #ifdef CONFIG_DRM_AMDGPU_CIK
1177         case CHIP_BONAIRE:
1178         case CHIP_HAWAII:
1179         case CHIP_KAVERI:
1180         case CHIP_KABINI:
1181         case CHIP_MULLINS:
1182                 if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
1183                         adev->family = AMDGPU_FAMILY_CI;
1184                 else
1185                         adev->family = AMDGPU_FAMILY_KV;
1186
1187                 r = cik_set_ip_blocks(adev);
1188                 if (r)
1189                         return r;
1190                 break;
1191 #endif
1192         default:
1193                 /* FIXME: not supported yet */
1194                 return -EINVAL;
1195         }
1196
1197         adev->ip_block_status = kcalloc(adev->num_ip_blocks,
1198                                         sizeof(struct amdgpu_ip_block_status), GFP_KERNEL);
1199         if (adev->ip_block_status == NULL)
1200                 return -ENOMEM;
1201
1202         if (adev->ip_blocks == NULL) {
1203                 DRM_ERROR("No IP blocks found!\n");
1204                 return r;
1205         }
1206
1207         for (i = 0; i < adev->num_ip_blocks; i++) {
1208                 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1209                         DRM_ERROR("disabled ip block: %d\n", i);
1210                         adev->ip_block_status[i].valid = false;
1211                 } else {
1212                         if (adev->ip_blocks[i].funcs->early_init) {
1213                                 r = adev->ip_blocks[i].funcs->early_init((void *)adev);
1214                                 if (r == -ENOENT)
1215                                         adev->ip_block_status[i].valid = false;
1216                                 else if (r)
1217                                         return r;
1218                                 else
1219                                         adev->ip_block_status[i].valid = true;
1220                         } else {
1221                                 adev->ip_block_status[i].valid = true;
1222                         }
1223                 }
1224         }
1225
1226         return 0;
1227 }
1228
1229 static int amdgpu_init(struct amdgpu_device *adev)
1230 {
1231         int i, r;
1232
1233         for (i = 0; i < adev->num_ip_blocks; i++) {
1234                 if (!adev->ip_block_status[i].valid)
1235                         continue;
1236                 r = adev->ip_blocks[i].funcs->sw_init((void *)adev);
1237                 if (r)
1238                         return r;
1239                 adev->ip_block_status[i].sw = true;
1240                 /* need to do gmc hw init early so we can allocate gpu mem */
1241                 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
1242                         r = amdgpu_vram_scratch_init(adev);
1243                         if (r)
1244                                 return r;
1245                         r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
1246                         if (r)
1247                                 return r;
1248                         r = amdgpu_wb_init(adev);
1249                         if (r)
1250                                 return r;
1251                         adev->ip_block_status[i].hw = true;
1252                 }
1253         }
1254
1255         for (i = 0; i < adev->num_ip_blocks; i++) {
1256                 if (!adev->ip_block_status[i].sw)
1257                         continue;
1258                 /* gmc hw init is done early */
1259                 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC)
1260                         continue;
1261                 r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
1262                 if (r)
1263                         return r;
1264                 adev->ip_block_status[i].hw = true;
1265         }
1266
1267         return 0;
1268 }
1269
1270 static int amdgpu_late_init(struct amdgpu_device *adev)
1271 {
1272         int i = 0, r;
1273
1274         for (i = 0; i < adev->num_ip_blocks; i++) {
1275                 if (!adev->ip_block_status[i].valid)
1276                         continue;
1277                 /* enable clockgating to save power */
1278                 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1279                                                                     AMD_CG_STATE_GATE);
1280                 if (r)
1281                         return r;
1282                 if (adev->ip_blocks[i].funcs->late_init) {
1283                         r = adev->ip_blocks[i].funcs->late_init((void *)adev);
1284                         if (r)
1285                                 return r;
1286                 }
1287         }
1288
1289         return 0;
1290 }
1291
1292 static int amdgpu_fini(struct amdgpu_device *adev)
1293 {
1294         int i, r;
1295
1296         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1297                 if (!adev->ip_block_status[i].hw)
1298                         continue;
1299                 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
1300                         amdgpu_wb_fini(adev);
1301                         amdgpu_vram_scratch_fini(adev);
1302                 }
1303                 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1304                 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1305                                                                     AMD_CG_STATE_UNGATE);
1306                 if (r)
1307                         return r;
1308                 r = adev->ip_blocks[i].funcs->hw_fini((void *)adev);
1309                 /* XXX handle errors */
1310                 adev->ip_block_status[i].hw = false;
1311         }
1312
1313         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1314                 if (!adev->ip_block_status[i].sw)
1315                         continue;
1316                 r = adev->ip_blocks[i].funcs->sw_fini((void *)adev);
1317                 /* XXX handle errors */
1318                 adev->ip_block_status[i].sw = false;
1319                 adev->ip_block_status[i].valid = false;
1320         }
1321
1322         return 0;
1323 }
1324
1325 static int amdgpu_suspend(struct amdgpu_device *adev)
1326 {
1327         int i, r;
1328
1329         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1330                 if (!adev->ip_block_status[i].valid)
1331                         continue;
1332                 /* ungate blocks so that suspend can properly shut them down */
1333                 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1334                                                                     AMD_CG_STATE_UNGATE);
1335                 /* XXX handle errors */
1336                 r = adev->ip_blocks[i].funcs->suspend(adev);
1337                 /* XXX handle errors */
1338         }
1339
1340         return 0;
1341 }
1342
1343 static int amdgpu_resume(struct amdgpu_device *adev)
1344 {
1345         int i, r;
1346
1347         for (i = 0; i < adev->num_ip_blocks; i++) {
1348                 if (!adev->ip_block_status[i].valid)
1349                         continue;
1350                 r = adev->ip_blocks[i].funcs->resume(adev);
1351                 if (r)
1352                         return r;
1353         }
1354
1355         return 0;
1356 }
1357
1358 /**
1359  * amdgpu_device_init - initialize the driver
1360  *
1361  * @adev: amdgpu_device pointer
1362  * @pdev: drm dev pointer
1363  * @pdev: pci dev pointer
1364  * @flags: driver flags
1365  *
1366  * Initializes the driver info and hw (all asics).
1367  * Returns 0 for success or an error on failure.
1368  * Called at driver startup.
1369  */
1370 int amdgpu_device_init(struct amdgpu_device *adev,
1371                        struct drm_device *ddev,
1372                        struct pci_dev *pdev,
1373                        uint32_t flags)
1374 {
1375         int r, i;
1376         bool runtime = false;
1377
1378         adev->shutdown = false;
1379         adev->dev = &pdev->dev;
1380         adev->ddev = ddev;
1381         adev->pdev = pdev;
1382         adev->flags = flags;
1383         adev->asic_type = flags & AMD_ASIC_MASK;
1384         adev->is_atom_bios = false;
1385         adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
1386         adev->mc.gtt_size = 512 * 1024 * 1024;
1387         adev->accel_working = false;
1388         adev->num_rings = 0;
1389         adev->mman.buffer_funcs = NULL;
1390         adev->mman.buffer_funcs_ring = NULL;
1391         adev->vm_manager.vm_pte_funcs = NULL;
1392         adev->vm_manager.vm_pte_funcs_ring = NULL;
1393         adev->gart.gart_funcs = NULL;
1394         adev->fence_context = fence_context_alloc(AMDGPU_MAX_RINGS);
1395
1396         adev->smc_rreg = &amdgpu_invalid_rreg;
1397         adev->smc_wreg = &amdgpu_invalid_wreg;
1398         adev->pcie_rreg = &amdgpu_invalid_rreg;
1399         adev->pcie_wreg = &amdgpu_invalid_wreg;
1400         adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
1401         adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
1402         adev->didt_rreg = &amdgpu_invalid_rreg;
1403         adev->didt_wreg = &amdgpu_invalid_wreg;
1404         adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
1405         adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
1406
1407         DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
1408                  amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
1409                  pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
1410
1411         /* mutex initialization are all done here so we
1412          * can recall function without having locking issues */
1413         mutex_init(&adev->ring_lock);
1414         atomic_set(&adev->irq.ih.lock, 0);
1415         mutex_init(&adev->gem.mutex);
1416         mutex_init(&adev->pm.mutex);
1417         mutex_init(&adev->gfx.gpu_clock_mutex);
1418         mutex_init(&adev->srbm_mutex);
1419         mutex_init(&adev->grbm_idx_mutex);
1420         init_rwsem(&adev->exclusive_lock);
1421         mutex_init(&adev->mn_lock);
1422         hash_init(adev->mn_hash);
1423
1424         amdgpu_check_arguments(adev);
1425
1426         /* Registers mapping */
1427         /* TODO: block userspace mapping of io register */
1428         spin_lock_init(&adev->mmio_idx_lock);
1429         spin_lock_init(&adev->smc_idx_lock);
1430         spin_lock_init(&adev->pcie_idx_lock);
1431         spin_lock_init(&adev->uvd_ctx_idx_lock);
1432         spin_lock_init(&adev->didt_idx_lock);
1433         spin_lock_init(&adev->audio_endpt_idx_lock);
1434
1435         adev->rmmio_base = pci_resource_start(adev->pdev, 5);
1436         adev->rmmio_size = pci_resource_len(adev->pdev, 5);
1437         adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
1438         if (adev->rmmio == NULL) {
1439                 return -ENOMEM;
1440         }
1441         DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
1442         DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
1443
1444         /* doorbell bar mapping */
1445         amdgpu_doorbell_init(adev);
1446
1447         /* io port mapping */
1448         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1449                 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
1450                         adev->rio_mem_size = pci_resource_len(adev->pdev, i);
1451                         adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
1452                         break;
1453                 }
1454         }
1455         if (adev->rio_mem == NULL)
1456                 DRM_ERROR("Unable to find PCI I/O BAR\n");
1457
1458         /* early init functions */
1459         r = amdgpu_early_init(adev);
1460         if (r)
1461                 return r;
1462
1463         /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
1464         /* this will fail for cards that aren't VGA class devices, just
1465          * ignore it */
1466         vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode);
1467
1468         if (amdgpu_runtime_pm == 1)
1469                 runtime = true;
1470         if (amdgpu_device_is_px(ddev))
1471                 runtime = true;
1472         vga_switcheroo_register_client(adev->pdev, &amdgpu_switcheroo_ops, runtime);
1473         if (runtime)
1474                 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
1475
1476         /* Read BIOS */
1477         if (!amdgpu_get_bios(adev))
1478                 return -EINVAL;
1479         /* Must be an ATOMBIOS */
1480         if (!adev->is_atom_bios) {
1481                 dev_err(adev->dev, "Expecting atombios for GPU\n");
1482                 return -EINVAL;
1483         }
1484         r = amdgpu_atombios_init(adev);
1485         if (r)
1486                 return r;
1487
1488         /* Post card if necessary */
1489         if (!amdgpu_card_posted(adev)) {
1490                 if (!adev->bios) {
1491                         dev_err(adev->dev, "Card not posted and no BIOS - ignoring\n");
1492                         return -EINVAL;
1493                 }
1494                 DRM_INFO("GPU not posted. posting now...\n");
1495                 amdgpu_atom_asic_init(adev->mode_info.atom_context);
1496         }
1497
1498         /* Initialize clocks */
1499         r = amdgpu_atombios_get_clock_info(adev);
1500         if (r)
1501                 return r;
1502         /* init i2c buses */
1503         amdgpu_atombios_i2c_init(adev);
1504
1505         /* Fence driver */
1506         r = amdgpu_fence_driver_init(adev);
1507         if (r)
1508                 return r;
1509
1510         /* init the mode config */
1511         drm_mode_config_init(adev->ddev);
1512
1513         r = amdgpu_init(adev);
1514         if (r) {
1515                 amdgpu_fini(adev);
1516                 return r;
1517         }
1518
1519         adev->accel_working = true;
1520
1521         amdgpu_fbdev_init(adev);
1522
1523         r = amdgpu_ib_pool_init(adev);
1524         if (r) {
1525                 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
1526                 return r;
1527         }
1528
1529         r = amdgpu_ctx_init(adev, true, &adev->kernel_ctx);
1530         if (r) {
1531                 dev_err(adev->dev, "failed to create kernel context (%d).\n", r);
1532                 return r;
1533         }
1534         r = amdgpu_ib_ring_tests(adev);
1535         if (r)
1536                 DRM_ERROR("ib ring test failed (%d).\n", r);
1537
1538         r = amdgpu_gem_debugfs_init(adev);
1539         if (r) {
1540                 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
1541         }
1542
1543         r = amdgpu_debugfs_regs_init(adev);
1544         if (r) {
1545                 DRM_ERROR("registering register debugfs failed (%d).\n", r);
1546         }
1547
1548         if ((amdgpu_testing & 1)) {
1549                 if (adev->accel_working)
1550                         amdgpu_test_moves(adev);
1551                 else
1552                         DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
1553         }
1554         if ((amdgpu_testing & 2)) {
1555                 if (adev->accel_working)
1556                         amdgpu_test_syncing(adev);
1557                 else
1558                         DRM_INFO("amdgpu: acceleration disabled, skipping sync tests\n");
1559         }
1560         if (amdgpu_benchmarking) {
1561                 if (adev->accel_working)
1562                         amdgpu_benchmark(adev, amdgpu_benchmarking);
1563                 else
1564                         DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
1565         }
1566
1567         /* enable clockgating, etc. after ib tests, etc. since some blocks require
1568          * explicit gating rather than handling it automatically.
1569          */
1570         r = amdgpu_late_init(adev);
1571         if (r)
1572                 return r;
1573
1574         return 0;
1575 }
1576
1577 static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev);
1578
1579 /**
1580  * amdgpu_device_fini - tear down the driver
1581  *
1582  * @adev: amdgpu_device pointer
1583  *
1584  * Tear down the driver info (all asics).
1585  * Called at driver shutdown.
1586  */
1587 void amdgpu_device_fini(struct amdgpu_device *adev)
1588 {
1589         int r;
1590
1591         DRM_INFO("amdgpu: finishing device.\n");
1592         adev->shutdown = true;
1593         /* evict vram memory */
1594         amdgpu_bo_evict_vram(adev);
1595         amdgpu_ctx_fini(&adev->kernel_ctx);
1596         amdgpu_ib_pool_fini(adev);
1597         amdgpu_fence_driver_fini(adev);
1598         amdgpu_fbdev_fini(adev);
1599         r = amdgpu_fini(adev);
1600         kfree(adev->ip_block_status);
1601         adev->ip_block_status = NULL;
1602         adev->accel_working = false;
1603         /* free i2c buses */
1604         amdgpu_i2c_fini(adev);
1605         amdgpu_atombios_fini(adev);
1606         kfree(adev->bios);
1607         adev->bios = NULL;
1608         vga_switcheroo_unregister_client(adev->pdev);
1609         vga_client_register(adev->pdev, NULL, NULL, NULL);
1610         if (adev->rio_mem)
1611                 pci_iounmap(adev->pdev, adev->rio_mem);
1612         adev->rio_mem = NULL;
1613         iounmap(adev->rmmio);
1614         adev->rmmio = NULL;
1615         amdgpu_doorbell_fini(adev);
1616         amdgpu_debugfs_regs_cleanup(adev);
1617         amdgpu_debugfs_remove_files(adev);
1618 }
1619
1620
1621 /*
1622  * Suspend & resume.
1623  */
1624 /**
1625  * amdgpu_suspend_kms - initiate device suspend
1626  *
1627  * @pdev: drm dev pointer
1628  * @state: suspend state
1629  *
1630  * Puts the hw in the suspend state (all asics).
1631  * Returns 0 for success or an error on failure.
1632  * Called at driver suspend.
1633  */
1634 int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon)
1635 {
1636         struct amdgpu_device *adev;
1637         struct drm_crtc *crtc;
1638         struct drm_connector *connector;
1639         int r;
1640
1641         if (dev == NULL || dev->dev_private == NULL) {
1642                 return -ENODEV;
1643         }
1644
1645         adev = dev->dev_private;
1646
1647         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1648                 return 0;
1649
1650         drm_kms_helper_poll_disable(dev);
1651
1652         /* turn off display hw */
1653         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1654                 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
1655         }
1656
1657         /* unpin the front buffers */
1658         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1659                 struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb);
1660                 struct amdgpu_bo *robj;
1661
1662                 if (rfb == NULL || rfb->obj == NULL) {
1663                         continue;
1664                 }
1665                 robj = gem_to_amdgpu_bo(rfb->obj);
1666                 /* don't unpin kernel fb objects */
1667                 if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
1668                         r = amdgpu_bo_reserve(robj, false);
1669                         if (r == 0) {
1670                                 amdgpu_bo_unpin(robj);
1671                                 amdgpu_bo_unreserve(robj);
1672                         }
1673                 }
1674         }
1675         /* evict vram memory */
1676         amdgpu_bo_evict_vram(adev);
1677
1678         amdgpu_fence_driver_suspend(adev);
1679
1680         r = amdgpu_suspend(adev);
1681
1682         /* evict remaining vram memory */
1683         amdgpu_bo_evict_vram(adev);
1684
1685         pci_save_state(dev->pdev);
1686         if (suspend) {
1687                 /* Shut down the device */
1688                 pci_disable_device(dev->pdev);
1689                 pci_set_power_state(dev->pdev, PCI_D3hot);
1690         }
1691
1692         if (fbcon) {
1693                 console_lock();
1694                 amdgpu_fbdev_set_suspend(adev, 1);
1695                 console_unlock();
1696         }
1697         return 0;
1698 }
1699
1700 /**
1701  * amdgpu_resume_kms - initiate device resume
1702  *
1703  * @pdev: drm dev pointer
1704  *
1705  * Bring the hw back to operating state (all asics).
1706  * Returns 0 for success or an error on failure.
1707  * Called at driver resume.
1708  */
1709 int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
1710 {
1711         struct drm_connector *connector;
1712         struct amdgpu_device *adev = dev->dev_private;
1713         int r;
1714
1715         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1716                 return 0;
1717
1718         if (fbcon) {
1719                 console_lock();
1720         }
1721         if (resume) {
1722                 pci_set_power_state(dev->pdev, PCI_D0);
1723                 pci_restore_state(dev->pdev);
1724                 if (pci_enable_device(dev->pdev)) {
1725                         if (fbcon)
1726                                 console_unlock();
1727                         return -1;
1728                 }
1729         }
1730
1731         /* post card */
1732         amdgpu_atom_asic_init(adev->mode_info.atom_context);
1733
1734         r = amdgpu_resume(adev);
1735
1736         amdgpu_fence_driver_resume(adev);
1737
1738         r = amdgpu_ib_ring_tests(adev);
1739         if (r)
1740                 DRM_ERROR("ib ring test failed (%d).\n", r);
1741
1742         r = amdgpu_late_init(adev);
1743         if (r)
1744                 return r;
1745
1746         /* blat the mode back in */
1747         if (fbcon) {
1748                 drm_helper_resume_force_mode(dev);
1749                 /* turn on display hw */
1750                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1751                         drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
1752                 }
1753         }
1754
1755         drm_kms_helper_poll_enable(dev);
1756
1757         if (fbcon) {
1758                 amdgpu_fbdev_set_suspend(adev, 0);
1759                 console_unlock();
1760         }
1761
1762         return 0;
1763 }
1764
1765 /**
1766  * amdgpu_gpu_reset - reset the asic
1767  *
1768  * @adev: amdgpu device pointer
1769  *
1770  * Attempt the reset the GPU if it has hung (all asics).
1771  * Returns 0 for success or an error on failure.
1772  */
1773 int amdgpu_gpu_reset(struct amdgpu_device *adev)
1774 {
1775         unsigned ring_sizes[AMDGPU_MAX_RINGS];
1776         uint32_t *ring_data[AMDGPU_MAX_RINGS];
1777
1778         bool saved = false;
1779
1780         int i, r;
1781         int resched;
1782
1783         down_write(&adev->exclusive_lock);
1784
1785         if (!adev->needs_reset) {
1786                 up_write(&adev->exclusive_lock);
1787                 return 0;
1788         }
1789
1790         adev->needs_reset = false;
1791         atomic_inc(&adev->gpu_reset_counter);
1792
1793         /* block TTM */
1794         resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
1795
1796         r = amdgpu_suspend(adev);
1797
1798         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1799                 struct amdgpu_ring *ring = adev->rings[i];
1800                 if (!ring)
1801                         continue;
1802
1803                 ring_sizes[i] = amdgpu_ring_backup(ring, &ring_data[i]);
1804                 if (ring_sizes[i]) {
1805                         saved = true;
1806                         dev_info(adev->dev, "Saved %d dwords of commands "
1807                                  "on ring %d.\n", ring_sizes[i], i);
1808                 }
1809         }
1810
1811 retry:
1812         r = amdgpu_asic_reset(adev);
1813         if (!r) {
1814                 dev_info(adev->dev, "GPU reset succeeded, trying to resume\n");
1815                 r = amdgpu_resume(adev);
1816         }
1817
1818         if (!r) {
1819                 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1820                         struct amdgpu_ring *ring = adev->rings[i];
1821                         if (!ring)
1822                                 continue;
1823
1824                         amdgpu_ring_restore(ring, ring_sizes[i], ring_data[i]);
1825                         ring_sizes[i] = 0;
1826                         ring_data[i] = NULL;
1827                 }
1828
1829                 r = amdgpu_ib_ring_tests(adev);
1830                 if (r) {
1831                         dev_err(adev->dev, "ib ring test failed (%d).\n", r);
1832                         if (saved) {
1833                                 saved = false;
1834                                 r = amdgpu_suspend(adev);
1835                                 goto retry;
1836                         }
1837                 }
1838         } else {
1839                 amdgpu_fence_driver_force_completion(adev);
1840                 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1841                         if (adev->rings[i])
1842                                 kfree(ring_data[i]);
1843                 }
1844         }
1845
1846         drm_helper_resume_force_mode(adev->ddev);
1847
1848         ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
1849         if (r) {
1850                 /* bad news, how to tell it to userspace ? */
1851                 dev_info(adev->dev, "GPU reset failed\n");
1852         }
1853
1854         up_write(&adev->exclusive_lock);
1855         return r;
1856 }
1857
1858
1859 /*
1860  * Debugfs
1861  */
1862 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
1863                              struct drm_info_list *files,
1864                              unsigned nfiles)
1865 {
1866         unsigned i;
1867
1868         for (i = 0; i < adev->debugfs_count; i++) {
1869                 if (adev->debugfs[i].files == files) {
1870                         /* Already registered */
1871                         return 0;
1872                 }
1873         }
1874
1875         i = adev->debugfs_count + 1;
1876         if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) {
1877                 DRM_ERROR("Reached maximum number of debugfs components.\n");
1878                 DRM_ERROR("Report so we increase "
1879                           "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n");
1880                 return -EINVAL;
1881         }
1882         adev->debugfs[adev->debugfs_count].files = files;
1883         adev->debugfs[adev->debugfs_count].num_files = nfiles;
1884         adev->debugfs_count = i;
1885 #if defined(CONFIG_DEBUG_FS)
1886         drm_debugfs_create_files(files, nfiles,
1887                                  adev->ddev->control->debugfs_root,
1888                                  adev->ddev->control);
1889         drm_debugfs_create_files(files, nfiles,
1890                                  adev->ddev->primary->debugfs_root,
1891                                  adev->ddev->primary);
1892 #endif
1893         return 0;
1894 }
1895
1896 static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev)
1897 {
1898 #if defined(CONFIG_DEBUG_FS)
1899         unsigned i;
1900
1901         for (i = 0; i < adev->debugfs_count; i++) {
1902                 drm_debugfs_remove_files(adev->debugfs[i].files,
1903                                          adev->debugfs[i].num_files,
1904                                          adev->ddev->control);
1905                 drm_debugfs_remove_files(adev->debugfs[i].files,
1906                                          adev->debugfs[i].num_files,
1907                                          adev->ddev->primary);
1908         }
1909 #endif
1910 }
1911
1912 #if defined(CONFIG_DEBUG_FS)
1913
1914 static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
1915                                         size_t size, loff_t *pos)
1916 {
1917         struct amdgpu_device *adev = f->f_inode->i_private;
1918         ssize_t result = 0;
1919         int r;
1920
1921         if (size & 0x3 || *pos & 0x3)
1922                 return -EINVAL;
1923
1924         while (size) {
1925                 uint32_t value;
1926
1927                 if (*pos > adev->rmmio_size)
1928                         return result;
1929
1930                 value = RREG32(*pos >> 2);
1931                 r = put_user(value, (uint32_t *)buf);
1932                 if (r)
1933                         return r;
1934
1935                 result += 4;
1936                 buf += 4;
1937                 *pos += 4;
1938                 size -= 4;
1939         }
1940
1941         return result;
1942 }
1943
1944 static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
1945                                          size_t size, loff_t *pos)
1946 {
1947         struct amdgpu_device *adev = f->f_inode->i_private;
1948         ssize_t result = 0;
1949         int r;
1950
1951         if (size & 0x3 || *pos & 0x3)
1952                 return -EINVAL;
1953
1954         while (size) {
1955                 uint32_t value;
1956
1957                 if (*pos > adev->rmmio_size)
1958                         return result;
1959
1960                 r = get_user(value, (uint32_t *)buf);
1961                 if (r)
1962                         return r;
1963
1964                 WREG32(*pos >> 2, value);
1965
1966                 result += 4;
1967                 buf += 4;
1968                 *pos += 4;
1969                 size -= 4;
1970         }
1971
1972         return result;
1973 }
1974
1975 static const struct file_operations amdgpu_debugfs_regs_fops = {
1976         .owner = THIS_MODULE,
1977         .read = amdgpu_debugfs_regs_read,
1978         .write = amdgpu_debugfs_regs_write,
1979         .llseek = default_llseek
1980 };
1981
1982 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
1983 {
1984         struct drm_minor *minor = adev->ddev->primary;
1985         struct dentry *ent, *root = minor->debugfs_root;
1986
1987         ent = debugfs_create_file("amdgpu_regs", S_IFREG | S_IRUGO, root,
1988                                   adev, &amdgpu_debugfs_regs_fops);
1989         if (IS_ERR(ent))
1990                 return PTR_ERR(ent);
1991         i_size_write(ent->d_inode, adev->rmmio_size);
1992         adev->debugfs_regs = ent;
1993
1994         return 0;
1995 }
1996
1997 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev)
1998 {
1999         debugfs_remove(adev->debugfs_regs);
2000         adev->debugfs_regs = NULL;
2001 }
2002
2003 int amdgpu_debugfs_init(struct drm_minor *minor)
2004 {
2005         return 0;
2006 }
2007
2008 void amdgpu_debugfs_cleanup(struct drm_minor *minor)
2009 {
2010 }
2011 #else
2012 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
2013 {
2014         return 0;
2015 }
2016 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { }
2017 #endif