drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/console.h>
  29 #include <linux/slab.h>
  30 #include <linux/debugfs.h>
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc_helper.h>
  33 #include <drm/amdgpu_drm.h>
  34 #include <linux/vgaarb.h>
  35 #include <linux/vga_switcheroo.h>
  36 #include <linux/efi.h>
  37 #include "amdgpu.h"
  38 #include "amdgpu_i2c.h"
  39 #include "atom.h"
  40 #include "amdgpu_atombios.h"
  41 #include "amd_pcie.h"
  42 #ifdef CONFIG_DRM_AMDGPU_CIK
  43 #include "cik.h"
  44 #endif
  45 #include "vi.h"
  46 #include "bif/bif_4_1_d.h"
  47
  48 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev);
  49 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev);
  50
  51 static const char *amdgpu_asic_name[] = {
  52         "BONAIRE",
  53         "KAVERI",
  54         "KABINI",
  55         "HAWAII",
  56         "MULLINS",
  57         "TOPAZ",
  58         "TONGA",
  59         "FIJI",
  60         "CARRIZO",
  61         "STONEY",
  62         "POLARIS10",
  63         "POLARIS11",
  64         "LAST",
  65 };
  66
  67 bool amdgpu_device_is_px(struct drm_device *dev)
  68 {
  69         struct amdgpu_device *adev = dev->dev_private;
  70
  71         if (adev->flags & AMD_IS_PX)
  72                 return true;
  73         return false;
  74 }
  75
  76 /*
  77  * MMIO register access helper functions.
  78  */
  79 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
  80                         bool always_indirect)
  81 {
  82         if ((reg * 4) < adev->rmmio_size && !always_indirect)
  83                 return readl(((void __iomem *)adev->rmmio) + (reg * 4));
  84         else {
  85                 unsigned long flags;
  86                 uint32_t ret;
  87
  88                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
  89                 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
  90                 ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
  91                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
  92
  93                 return ret;
  94         }
  95 }
  96
  97 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
  98                     bool always_indirect)
  99 {
 100         if ((reg * 4) < adev->rmmio_size && !always_indirect)
 101                 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
 102         else {
 103                 unsigned long flags;
 104
 105                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
 106                 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
 107                 writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
 108                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
 109         }
 110 }
 111
 112 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
 113 {
 114         if ((reg * 4) < adev->rio_mem_size)
 115                 return ioread32(adev->rio_mem + (reg * 4));
 116         else {
 117                 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
 118                 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
 119         }
 120 }
 121
 122 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 123 {
 124
 125         if ((reg * 4) < adev->rio_mem_size)
 126                 iowrite32(v, adev->rio_mem + (reg * 4));
 127         else {
 128                 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
 129                 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
 130         }
 131 }
 132
 133 /**
 134  * amdgpu_mm_rdoorbell - read a doorbell dword
 135  *
 136  * @adev: amdgpu_device pointer
 137  * @index: doorbell index
 138  *
 139  * Returns the value in the doorbell aperture at the
 140  * requested doorbell index (CIK).
 141  */
 142 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
 143 {
 144         if (index < adev->doorbell.num_doorbells) {
 145                 return readl(adev->doorbell.ptr + index);
 146         } else {
 147                 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
 148                 return 0;
 149         }
 150 }
 151
 152 /**
 153  * amdgpu_mm_wdoorbell - write a doorbell dword
 154  *
 155  * @adev: amdgpu_device pointer
 156  * @index: doorbell index
 157  * @v: value to write
 158  *
 159  * Writes @v to the doorbell aperture at the
 160  * requested doorbell index (CIK).
 161  */
 162 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
 163 {
 164         if (index < adev->doorbell.num_doorbells) {
 165                 writel(v, adev->doorbell.ptr + index);
 166         } else {
 167                 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
 168         }
 169 }
 170
 171 /**
 172  * amdgpu_invalid_rreg - dummy reg read function
 173  *
 174  * @adev: amdgpu device pointer
 175  * @reg: offset of register
 176  *
 177  * Dummy register read function.  Used for register blocks
 178  * that certain asics don't have (all asics).
 179  * Returns the value in the register.
 180  */
 181 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
 182 {
 183         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
 184         BUG();
 185         return 0;
 186 }
 187
 188 /**
 189  * amdgpu_invalid_wreg - dummy reg write function
 190  *
 191  * @adev: amdgpu device pointer
 192  * @reg: offset of register
 193  * @v: value to write to the register
 194  *
 195  * Dummy register read function.  Used for register blocks
 196  * that certain asics don't have (all asics).
 197  */
 198 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
 199 {
 200         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
 201                   reg, v);
 202         BUG();
 203 }
 204
 205 /**
 206  * amdgpu_block_invalid_rreg - dummy reg read function
 207  *
 208  * @adev: amdgpu device pointer
 209  * @block: offset of instance
 210  * @reg: offset of register
 211  *
 212  * Dummy register read function.  Used for register blocks
 213  * that certain asics don't have (all asics).
 214  * Returns the value in the register.
 215  */
 216 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
 217                                           uint32_t block, uint32_t reg)
 218 {
 219         DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
 220                   reg, block);
 221         BUG();
 222         return 0;
 223 }
 224
 225 /**
 226  * amdgpu_block_invalid_wreg - dummy reg write function
 227  *
 228  * @adev: amdgpu device pointer
 229  * @block: offset of instance
 230  * @reg: offset of register
 231  * @v: value to write to the register
 232  *
 233  * Dummy register read function.  Used for register blocks
 234  * that certain asics don't have (all asics).
 235  */
 236 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
 237                                       uint32_t block,
 238                                       uint32_t reg, uint32_t v)
 239 {
 240         DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
 241                   reg, block, v);
 242         BUG();
 243 }
 244
 245 static int amdgpu_vram_scratch_init(struct amdgpu_device *adev)
 246 {
 247         int r;
 248
 249         if (adev->vram_scratch.robj == NULL) {
 250                 r = amdgpu_bo_create(adev, AMDGPU_GPU_PAGE_SIZE,
 251                                      PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM,
 252                                      AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
 253                                      NULL, NULL, &adev->vram_scratch.robj);
 254                 if (r) {
 255                         return r;
 256                 }
 257         }
 258
 259         r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
 260         if (unlikely(r != 0))
 261                 return r;
 262         r = amdgpu_bo_pin(adev->vram_scratch.robj,
 263                           AMDGPU_GEM_DOMAIN_VRAM, &adev->vram_scratch.gpu_addr);
 264         if (r) {
 265                 amdgpu_bo_unreserve(adev->vram_scratch.robj);
 266                 return r;
 267         }
 268         r = amdgpu_bo_kmap(adev->vram_scratch.robj,
 269                                 (void **)&adev->vram_scratch.ptr);
 270         if (r)
 271                 amdgpu_bo_unpin(adev->vram_scratch.robj);
 272         amdgpu_bo_unreserve(adev->vram_scratch.robj);
 273
 274         return r;
 275 }
 276
 277 static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev)
 278 {
 279         int r;
 280
 281         if (adev->vram_scratch.robj == NULL) {
 282                 return;
 283         }
 284         r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
 285         if (likely(r == 0)) {
 286                 amdgpu_bo_kunmap(adev->vram_scratch.robj);
 287                 amdgpu_bo_unpin(adev->vram_scratch.robj);
 288                 amdgpu_bo_unreserve(adev->vram_scratch.robj);
 289         }
 290         amdgpu_bo_unref(&adev->vram_scratch.robj);
 291 }
 292
 293 /**
 294  * amdgpu_program_register_sequence - program an array of registers.
 295  *
 296  * @adev: amdgpu_device pointer
 297  * @registers: pointer to the register array
 298  * @array_size: size of the register array
 299  *
 300  * Programs an array or registers with and and or masks.
 301  * This is a helper for setting golden registers.
 302  */
 303 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
 304                                       const u32 *registers,
 305                                       const u32 array_size)
 306 {
 307         u32 tmp, reg, and_mask, or_mask;
 308         int i;
 309
 310         if (array_size % 3)
 311                 return;
 312
 313         for (i = 0; i < array_size; i +=3) {
 314                 reg = registers[i + 0];
 315                 and_mask = registers[i + 1];
 316                 or_mask = registers[i + 2];
 317
 318                 if (and_mask == 0xffffffff) {
 319                         tmp = or_mask;
 320                 } else {
 321                         tmp = RREG32(reg);
 322                         tmp &= ~and_mask;
 323                         tmp |= or_mask;
 324                 }
 325                 WREG32(reg, tmp);
 326         }
 327 }
 328
 329 void amdgpu_pci_config_reset(struct amdgpu_device *adev)
 330 {
 331         pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
 332 }
 333
 334 /*
 335  * GPU doorbell aperture helpers function.
 336  */
 337 /**
 338  * amdgpu_doorbell_init - Init doorbell driver information.
 339  *
 340  * @adev: amdgpu_device pointer
 341  *
 342  * Init doorbell driver information (CIK)
 343  * Returns 0 on success, error on failure.
 344  */
 345 static int amdgpu_doorbell_init(struct amdgpu_device *adev)
 346 {
 347         /* doorbell bar mapping */
 348         adev->doorbell.base = pci_resource_start(adev->pdev, 2);
 349         adev->doorbell.size = pci_resource_len(adev->pdev, 2);
 350
 351         adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
 352                                              AMDGPU_DOORBELL_MAX_ASSIGNMENT+1);
 353         if (adev->doorbell.num_doorbells == 0)
 354                 return -EINVAL;
 355
 356         adev->doorbell.ptr = ioremap(adev->doorbell.base, adev->doorbell.num_doorbells * sizeof(u32));
 357         if (adev->doorbell.ptr == NULL) {
 358                 return -ENOMEM;
 359         }
 360         DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)adev->doorbell.base);
 361         DRM_INFO("doorbell mmio size: %u\n", (unsigned)adev->doorbell.size);
 362
 363         return 0;
 364 }
 365
 366 /**
 367  * amdgpu_doorbell_fini - Tear down doorbell driver information.
 368  *
 369  * @adev: amdgpu_device pointer
 370  *
 371  * Tear down doorbell driver information (CIK)
 372  */
 373 static void amdgpu_doorbell_fini(struct amdgpu_device *adev)
 374 {
 375         iounmap(adev->doorbell.ptr);
 376         adev->doorbell.ptr = NULL;
 377 }
 378
 379 /**
 380  * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
 381  *                                setup amdkfd
 382  *
 383  * @adev: amdgpu_device pointer
 384  * @aperture_base: output returning doorbell aperture base physical address
 385  * @aperture_size: output returning doorbell aperture size in bytes
 386  * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
 387  *
 388  * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
 389  * takes doorbells required for its own rings and reports the setup to amdkfd.
 390  * amdgpu reserved doorbells are at the start of the doorbell aperture.
 391  */
 392 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
 393                                 phys_addr_t *aperture_base,
 394                                 size_t *aperture_size,
 395                                 size_t *start_offset)
 396 {
 397         /*
 398          * The first num_doorbells are used by amdgpu.
 399          * amdkfd takes whatever's left in the aperture.
 400          */
 401         if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
 402                 *aperture_base = adev->doorbell.base;
 403                 *aperture_size = adev->doorbell.size;
 404                 *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
 405         } else {
 406                 *aperture_base = 0;
 407                 *aperture_size = 0;
 408                 *start_offset = 0;
 409         }
 410 }
 411
 412 /*
 413  * amdgpu_wb_*()
 414  * Writeback is the the method by which the the GPU updates special pages
 415  * in memory with the status of certain GPU events (fences, ring pointers,
 416  * etc.).
 417  */
 418
 419 /**
 420  * amdgpu_wb_fini - Disable Writeback and free memory
 421  *
 422  * @adev: amdgpu_device pointer
 423  *
 424  * Disables Writeback and frees the Writeback memory (all asics).
 425  * Used at driver shutdown.
 426  */
 427 static void amdgpu_wb_fini(struct amdgpu_device *adev)
 428 {
 429         if (adev->wb.wb_obj) {
 430                 if (!amdgpu_bo_reserve(adev->wb.wb_obj, false)) {
 431                         amdgpu_bo_kunmap(adev->wb.wb_obj);
 432                         amdgpu_bo_unpin(adev->wb.wb_obj);
 433                         amdgpu_bo_unreserve(adev->wb.wb_obj);
 434                 }
 435                 amdgpu_bo_unref(&adev->wb.wb_obj);
 436                 adev->wb.wb = NULL;
 437                 adev->wb.wb_obj = NULL;
 438         }
 439 }
 440
 441 /**
 442  * amdgpu_wb_init- Init Writeback driver info and allocate memory
 443  *
 444  * @adev: amdgpu_device pointer
 445  *
 446  * Disables Writeback and frees the Writeback memory (all asics).
 447  * Used at driver startup.
 448  * Returns 0 on success or an -error on failure.
 449  */
 450 static int amdgpu_wb_init(struct amdgpu_device *adev)
 451 {
 452         int r;
 453
 454         if (adev->wb.wb_obj == NULL) {
 455                 r = amdgpu_bo_create(adev, AMDGPU_MAX_WB * 4, PAGE_SIZE, true,
 456                                      AMDGPU_GEM_DOMAIN_GTT, 0,  NULL, NULL,
 457                                      &adev->wb.wb_obj);
 458                 if (r) {
 459                         dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
 460                         return r;
 461                 }
 462                 r = amdgpu_bo_reserve(adev->wb.wb_obj, false);
 463                 if (unlikely(r != 0)) {
 464                         amdgpu_wb_fini(adev);
 465                         return r;
 466                 }
 467                 r = amdgpu_bo_pin(adev->wb.wb_obj, AMDGPU_GEM_DOMAIN_GTT,
 468                                 &adev->wb.gpu_addr);
 469                 if (r) {
 470                         amdgpu_bo_unreserve(adev->wb.wb_obj);
 471                         dev_warn(adev->dev, "(%d) pin WB bo failed\n", r);
 472                         amdgpu_wb_fini(adev);
 473                         return r;
 474                 }
 475                 r = amdgpu_bo_kmap(adev->wb.wb_obj, (void **)&adev->wb.wb);
 476                 amdgpu_bo_unreserve(adev->wb.wb_obj);
 477                 if (r) {
 478                         dev_warn(adev->dev, "(%d) map WB bo failed\n", r);
 479                         amdgpu_wb_fini(adev);
 480                         return r;
 481                 }
 482
 483                 adev->wb.num_wb = AMDGPU_MAX_WB;
 484                 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
 485
 486                 /* clear wb memory */
 487                 memset((char *)adev->wb.wb, 0, AMDGPU_GPU_PAGE_SIZE);
 488         }
 489
 490         return 0;
 491 }
 492
 493 /**
 494  * amdgpu_wb_get - Allocate a wb entry
 495  *
 496  * @adev: amdgpu_device pointer
 497  * @wb: wb index
 498  *
 499  * Allocate a wb slot for use by the driver (all asics).
 500  * Returns 0 on success or -EINVAL on failure.
 501  */
 502 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb)
 503 {
 504         unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
 505         if (offset < adev->wb.num_wb) {
 506                 __set_bit(offset, adev->wb.used);
 507                 *wb = offset;
 508                 return 0;
 509         } else {
 510                 return -EINVAL;
 511         }
 512 }
 513
 514 /**
 515  * amdgpu_wb_free - Free a wb entry
 516  *
 517  * @adev: amdgpu_device pointer
 518  * @wb: wb index
 519  *
 520  * Free a wb slot allocated for use by the driver (all asics)
 521  */
 522 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb)
 523 {
 524         if (wb < adev->wb.num_wb)
 525                 __clear_bit(wb, adev->wb.used);
 526 }
 527
 528 /**
 529  * amdgpu_vram_location - try to find VRAM location
 530  * @adev: amdgpu device structure holding all necessary informations
 531  * @mc: memory controller structure holding memory informations
 532  * @base: base address at which to put VRAM
 533  *
 534  * Function will place try to place VRAM at base address provided
 535  * as parameter (which is so far either PCI aperture address or
 536  * for IGP TOM base address).
 537  *
 538  * If there is not enough space to fit the unvisible VRAM in the 32bits
 539  * address space then we limit the VRAM size to the aperture.
 540  *
 541  * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
 542  * this shouldn't be a problem as we are using the PCI aperture as a reference.
 543  * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
 544  * not IGP.
 545  *
 546  * Note: we use mc_vram_size as on some board we need to program the mc to
 547  * cover the whole aperture even if VRAM size is inferior to aperture size
 548  * Novell bug 204882 + along with lots of ubuntu ones
 549  *
 550  * Note: when limiting vram it's safe to overwritte real_vram_size because
 551  * we are not in case where real_vram_size is inferior to mc_vram_size (ie
 552  * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
 553  * ones)
 554  *
 555  * Note: IGP TOM addr should be the same as the aperture addr, we don't
 556  * explicitly check for that thought.
 557  *
 558  * FIXME: when reducing VRAM size align new size on power of 2.
 559  */
 560 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base)
 561 {
 562         uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
 563
 564         mc->vram_start = base;
 565         if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) {
 566                 dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n");
 567                 mc->real_vram_size = mc->aper_size;
 568                 mc->mc_vram_size = mc->aper_size;
 569         }
 570         mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
 571         if (limit && limit < mc->real_vram_size)
 572                 mc->real_vram_size = limit;
 573         dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
 574                         mc->mc_vram_size >> 20, mc->vram_start,
 575                         mc->vram_end, mc->real_vram_size >> 20);
 576 }
 577
 578 /**
 579  * amdgpu_gtt_location - try to find GTT location
 580  * @adev: amdgpu device structure holding all necessary informations
 581  * @mc: memory controller structure holding memory informations
 582  *
 583  * Function will place try to place GTT before or after VRAM.
 584  *
 585  * If GTT size is bigger than space left then we ajust GTT size.
 586  * Thus function will never fails.
 587  *
 588  * FIXME: when reducing GTT size align new size on power of 2.
 589  */
 590 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc)
 591 {
 592         u64 size_af, size_bf;
 593
 594         size_af = ((adev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
 595         size_bf = mc->vram_start & ~mc->gtt_base_align;
 596         if (size_bf > size_af) {
 597                 if (mc->gtt_size > size_bf) {
 598                         dev_warn(adev->dev, "limiting GTT\n");
 599                         mc->gtt_size = size_bf;
 600                 }
 601                 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
 602         } else {
 603                 if (mc->gtt_size > size_af) {
 604                         dev_warn(adev->dev, "limiting GTT\n");
 605                         mc->gtt_size = size_af;
 606                 }
 607                 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
 608         }
 609         mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
 610         dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
 611                         mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
 612 }
 613
 614 /*
 615  * GPU helpers function.
 616  */
 617 /**
 618  * amdgpu_card_posted - check if the hw has already been initialized
 619  *
 620  * @adev: amdgpu_device pointer
 621  *
 622  * Check if the asic has been initialized (all asics).
 623  * Used at driver startup.
 624  * Returns true if initialized or false if not.
 625  */
 626 bool amdgpu_card_posted(struct amdgpu_device *adev)
 627 {
 628         uint32_t reg;
 629
 630         /* then check MEM_SIZE, in case the crtcs are off */
 631         reg = RREG32(mmCONFIG_MEMSIZE);
 632
 633         if (reg)
 634                 return true;
 635
 636         return false;
 637
 638 }
 639
 640 /**
 641  * amdgpu_dummy_page_init - init dummy page used by the driver
 642  *
 643  * @adev: amdgpu_device pointer
 644  *
 645  * Allocate the dummy page used by the driver (all asics).
 646  * This dummy page is used by the driver as a filler for gart entries
 647  * when pages are taken out of the GART
 648  * Returns 0 on sucess, -ENOMEM on failure.
 649  */
 650 int amdgpu_dummy_page_init(struct amdgpu_device *adev)
 651 {
 652         if (adev->dummy_page.page)
 653                 return 0;
 654         adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
 655         if (adev->dummy_page.page == NULL)
 656                 return -ENOMEM;
 657         adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page,
 658                                         0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 659         if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) {
 660                 dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
 661                 __free_page(adev->dummy_page.page);
 662                 adev->dummy_page.page = NULL;
 663                 return -ENOMEM;
 664         }
 665         return 0;
 666 }
 667
 668 /**
 669  * amdgpu_dummy_page_fini - free dummy page used by the driver
 670  *
 671  * @adev: amdgpu_device pointer
 672  *
 673  * Frees the dummy page used by the driver (all asics).
 674  */
 675 void amdgpu_dummy_page_fini(struct amdgpu_device *adev)
 676 {
 677         if (adev->dummy_page.page == NULL)
 678                 return;
 679         pci_unmap_page(adev->pdev, adev->dummy_page.addr,
 680                         PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 681         __free_page(adev->dummy_page.page);
 682         adev->dummy_page.page = NULL;
 683 }
 684
 685
 686 /* ATOM accessor methods */
 687 /*
 688  * ATOM is an interpreted byte code stored in tables in the vbios.  The
 689  * driver registers callbacks to access registers and the interpreter
 690  * in the driver parses the tables and executes then to program specific
 691  * actions (set display modes, asic init, etc.).  See amdgpu_atombios.c,
 692  * atombios.h, and atom.c
 693  */
 694
 695 /**
 696  * cail_pll_read - read PLL register
 697  *
 698  * @info: atom card_info pointer
 699  * @reg: PLL register offset
 700  *
 701  * Provides a PLL register accessor for the atom interpreter (r4xx+).
 702  * Returns the value of the PLL register.
 703  */
 704 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
 705 {
 706         return 0;
 707 }
 708
 709 /**
 710  * cail_pll_write - write PLL register
 711  *
 712  * @info: atom card_info pointer
 713  * @reg: PLL register offset
 714  * @val: value to write to the pll register
 715  *
 716  * Provides a PLL register accessor for the atom interpreter (r4xx+).
 717  */
 718 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
 719 {
 720
 721 }
 722
 723 /**
 724  * cail_mc_read - read MC (Memory Controller) register
 725  *
 726  * @info: atom card_info pointer
 727  * @reg: MC register offset
 728  *
 729  * Provides an MC register accessor for the atom interpreter (r4xx+).
 730  * Returns the value of the MC register.
 731  */
 732 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
 733 {
 734         return 0;
 735 }
 736
 737 /**
 738  * cail_mc_write - write MC (Memory Controller) register
 739  *
 740  * @info: atom card_info pointer
 741  * @reg: MC register offset
 742  * @val: value to write to the pll register
 743  *
 744  * Provides a MC register accessor for the atom interpreter (r4xx+).
 745  */
 746 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
 747 {
 748
 749 }
 750
 751 /**
 752  * cail_reg_write - write MMIO register
 753  *
 754  * @info: atom card_info pointer
 755  * @reg: MMIO register offset
 756  * @val: value to write to the pll register
 757  *
 758  * Provides a MMIO register accessor for the atom interpreter (r4xx+).
 759  */
 760 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
 761 {
 762         struct amdgpu_device *adev = info->dev->dev_private;
 763
 764         WREG32(reg, val);
 765 }
 766
 767 /**
 768  * cail_reg_read - read MMIO register
 769  *
 770  * @info: atom card_info pointer
 771  * @reg: MMIO register offset
 772  *
 773  * Provides an MMIO register accessor for the atom interpreter (r4xx+).
 774  * Returns the value of the MMIO register.
 775  */
 776 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
 777 {
 778         struct amdgpu_device *adev = info->dev->dev_private;
 779         uint32_t r;
 780
 781         r = RREG32(reg);
 782         return r;
 783 }
 784
 785 /**
 786  * cail_ioreg_write - write IO register
 787  *
 788  * @info: atom card_info pointer
 789  * @reg: IO register offset
 790  * @val: value to write to the pll register
 791  *
 792  * Provides a IO register accessor for the atom interpreter (r4xx+).
 793  */
 794 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
 795 {
 796         struct amdgpu_device *adev = info->dev->dev_private;
 797
 798         WREG32_IO(reg, val);
 799 }
 800
 801 /**
 802  * cail_ioreg_read - read IO register
 803  *
 804  * @info: atom card_info pointer
 805  * @reg: IO register offset
 806  *
 807  * Provides an IO register accessor for the atom interpreter (r4xx+).
 808  * Returns the value of the IO register.
 809  */
 810 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
 811 {
 812         struct amdgpu_device *adev = info->dev->dev_private;
 813         uint32_t r;
 814
 815         r = RREG32_IO(reg);
 816         return r;
 817 }
 818
 819 /**
 820  * amdgpu_atombios_fini - free the driver info and callbacks for atombios
 821  *
 822  * @adev: amdgpu_device pointer
 823  *
 824  * Frees the driver info and register access callbacks for the ATOM
 825  * interpreter (r4xx+).
 826  * Called at driver shutdown.
 827  */
 828 static void amdgpu_atombios_fini(struct amdgpu_device *adev)
 829 {
 830         if (adev->mode_info.atom_context) {
 831                 kfree(adev->mode_info.atom_context->scratch);
 832                 kfree(adev->mode_info.atom_context->iio);
 833         }
 834         kfree(adev->mode_info.atom_context);
 835         adev->mode_info.atom_context = NULL;
 836         kfree(adev->mode_info.atom_card_info);
 837         adev->mode_info.atom_card_info = NULL;
 838 }
 839
 840 /**
 841  * amdgpu_atombios_init - init the driver info and callbacks for atombios
 842  *
 843  * @adev: amdgpu_device pointer
 844  *
 845  * Initializes the driver info and register access callbacks for the
 846  * ATOM interpreter (r4xx+).
 847  * Returns 0 on sucess, -ENOMEM on failure.
 848  * Called at driver startup.
 849  */
 850 static int amdgpu_atombios_init(struct amdgpu_device *adev)
 851 {
 852         struct card_info *atom_card_info =
 853             kzalloc(sizeof(struct card_info), GFP_KERNEL);
 854
 855         if (!atom_card_info)
 856                 return -ENOMEM;
 857
 858         adev->mode_info.atom_card_info = atom_card_info;
 859         atom_card_info->dev = adev->ddev;
 860         atom_card_info->reg_read = cail_reg_read;
 861         atom_card_info->reg_write = cail_reg_write;
 862         /* needed for iio ops */
 863         if (adev->rio_mem) {
 864                 atom_card_info->ioreg_read = cail_ioreg_read;
 865                 atom_card_info->ioreg_write = cail_ioreg_write;
 866         } else {
 867                 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
 868                 atom_card_info->ioreg_read = cail_reg_read;
 869                 atom_card_info->ioreg_write = cail_reg_write;
 870         }
 871         atom_card_info->mc_read = cail_mc_read;
 872         atom_card_info->mc_write = cail_mc_write;
 873         atom_card_info->pll_read = cail_pll_read;
 874         atom_card_info->pll_write = cail_pll_write;
 875
 876         adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios);
 877         if (!adev->mode_info.atom_context) {
 878                 amdgpu_atombios_fini(adev);
 879                 return -ENOMEM;
 880         }
 881
 882         mutex_init(&adev->mode_info.atom_context->mutex);
 883         amdgpu_atombios_scratch_regs_init(adev);
 884         amdgpu_atom_allocate_fb_scratch(adev->mode_info.atom_context);
 885         return 0;
 886 }
 887
 888 /* if we get transitioned to only one device, take VGA back */
 889 /**
 890  * amdgpu_vga_set_decode - enable/disable vga decode
 891  *
 892  * @cookie: amdgpu_device pointer
 893  * @state: enable/disable vga decode
 894  *
 895  * Enable/disable vga decode (all asics).
 896  * Returns VGA resource flags.
 897  */
 898 static unsigned int amdgpu_vga_set_decode(void *cookie, bool state)
 899 {
 900         struct amdgpu_device *adev = cookie;
 901         amdgpu_asic_set_vga_state(adev, state);
 902         if (state)
 903                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 904                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 905         else
 906                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 907 }
 908
 909 /**
 910  * amdgpu_check_pot_argument - check that argument is a power of two
 911  *
 912  * @arg: value to check
 913  *
 914  * Validates that a certain argument is a power of two (all asics).
 915  * Returns true if argument is valid.
 916  */
 917 static bool amdgpu_check_pot_argument(int arg)
 918 {
 919         return (arg & (arg - 1)) == 0;
 920 }
 921
 922 /**
 923  * amdgpu_check_arguments - validate module params
 924  *
 925  * @adev: amdgpu_device pointer
 926  *
 927  * Validates certain module parameters and updates
 928  * the associated values used by the driver (all asics).
 929  */
 930 static void amdgpu_check_arguments(struct amdgpu_device *adev)
 931 {
 932         if (amdgpu_sched_jobs < 4) {
 933                 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
 934                          amdgpu_sched_jobs);
 935                 amdgpu_sched_jobs = 4;
 936         } else if (!amdgpu_check_pot_argument(amdgpu_sched_jobs)){
 937                 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
 938                          amdgpu_sched_jobs);
 939                 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
 940         }
 941
 942         if (amdgpu_gart_size != -1) {
 943                 /* gtt size must be greater or equal to 32M */
 944                 if (amdgpu_gart_size < 32) {
 945                         dev_warn(adev->dev, "gart size (%d) too small\n",
 946                                  amdgpu_gart_size);
 947                         amdgpu_gart_size = -1;
 948                 }
 949         }
 950
 951         if (!amdgpu_check_pot_argument(amdgpu_vm_size)) {
 952                 dev_warn(adev->dev, "VM size (%d) must be a power of 2\n",
 953                          amdgpu_vm_size);
 954                 amdgpu_vm_size = 8;
 955         }
 956
 957         if (amdgpu_vm_size < 1) {
 958                 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
 959                          amdgpu_vm_size);
 960                 amdgpu_vm_size = 8;
 961         }
 962
 963         /*
 964          * Max GPUVM size for Cayman, SI and CI are 40 bits.
 965          */
 966         if (amdgpu_vm_size > 1024) {
 967                 dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n",
 968                          amdgpu_vm_size);
 969                 amdgpu_vm_size = 8;
 970         }
 971
 972         /* defines number of bits in page table versus page directory,
 973          * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
 974          * page table and the remaining bits are in the page directory */
 975         if (amdgpu_vm_block_size == -1) {
 976
 977                 /* Total bits covered by PD + PTs */
 978                 unsigned bits = ilog2(amdgpu_vm_size) + 18;
 979
 980                 /* Make sure the PD is 4K in size up to 8GB address space.
 981                    Above that split equal between PD and PTs */
 982                 if (amdgpu_vm_size <= 8)
 983                         amdgpu_vm_block_size = bits - 9;
 984                 else
 985                         amdgpu_vm_block_size = (bits + 3) / 2;
 986
 987         } else if (amdgpu_vm_block_size < 9) {
 988                 dev_warn(adev->dev, "VM page table size (%d) too small\n",
 989                          amdgpu_vm_block_size);
 990                 amdgpu_vm_block_size = 9;
 991         }
 992
 993         if (amdgpu_vm_block_size > 24 ||
 994             (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) {
 995                 dev_warn(adev->dev, "VM page table size (%d) too large\n",
 996                          amdgpu_vm_block_size);
 997                 amdgpu_vm_block_size = 9;
 998         }
 999 }
1000
1001 /**
1002  * amdgpu_switcheroo_set_state - set switcheroo state
1003  *
1004  * @pdev: pci dev pointer
1005  * @state: vga_switcheroo state
1006  *
1007  * Callback for the switcheroo driver.  Suspends or resumes the
1008  * the asics before or after it is powered up using ACPI methods.
1009  */
1010 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1011 {
1012         struct drm_device *dev = pci_get_drvdata(pdev);
1013
1014         if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1015                 return;
1016
1017         if (state == VGA_SWITCHEROO_ON) {
1018                 unsigned d3_delay = dev->pdev->d3_delay;
1019
1020                 printk(KERN_INFO "amdgpu: switched on\n");
1021                 /* don't suspend or resume card normally */
1022                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1023
1024                 amdgpu_resume_kms(dev, true, true);
1025
1026                 dev->pdev->d3_delay = d3_delay;
1027
1028                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1029                 drm_kms_helper_poll_enable(dev);
1030         } else {
1031                 printk(KERN_INFO "amdgpu: switched off\n");
1032                 drm_kms_helper_poll_disable(dev);
1033                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1034                 amdgpu_suspend_kms(dev, true, true);
1035                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1036         }
1037 }
1038
1039 /**
1040  * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1041  *
1042  * @pdev: pci dev pointer
1043  *
1044  * Callback for the switcheroo driver.  Check of the switcheroo
1045  * state can be changed.
1046  * Returns true if the state can be changed, false if not.
1047  */
1048 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1049 {
1050         struct drm_device *dev = pci_get_drvdata(pdev);
1051
1052         /*
1053         * FIXME: open_count is protected by drm_global_mutex but that would lead to
1054         * locking inversion with the driver load path. And the access here is
1055         * completely racy anyway. So don't bother with locking for now.
1056         */
1057         return dev->open_count == 0;
1058 }
1059
1060 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1061         .set_gpu_state = amdgpu_switcheroo_set_state,
1062         .reprobe = NULL,
1063         .can_switch = amdgpu_switcheroo_can_switch,
1064 };
1065
1066 int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
1067                                   enum amd_ip_block_type block_type,
1068                                   enum amd_clockgating_state state)
1069 {
1070         int i, r = 0;
1071
1072         for (i = 0; i < adev->num_ip_blocks; i++) {
1073                 if (adev->ip_blocks[i].type == block_type) {
1074                         r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1075                                                                             state);
1076                         if (r)
1077                                 return r;
1078                 }
1079         }
1080         return r;
1081 }
1082
1083 int amdgpu_set_powergating_state(struct amdgpu_device *adev,
1084                                   enum amd_ip_block_type block_type,
1085                                   enum amd_powergating_state state)
1086 {
1087         int i, r = 0;
1088
1089         for (i = 0; i < adev->num_ip_blocks; i++) {
1090                 if (adev->ip_blocks[i].type == block_type) {
1091                         r = adev->ip_blocks[i].funcs->set_powergating_state((void *)adev,
1092                                                                             state);
1093                         if (r)
1094                                 return r;
1095                 }
1096         }
1097         return r;
1098 }
1099
1100 const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
1101                                         struct amdgpu_device *adev,
1102                                         enum amd_ip_block_type type)
1103 {
1104         int i;
1105
1106         for (i = 0; i < adev->num_ip_blocks; i++)
1107                 if (adev->ip_blocks[i].type == type)
1108                         return &adev->ip_blocks[i];
1109
1110         return NULL;
1111 }
1112
1113 /**
1114  * amdgpu_ip_block_version_cmp
1115  *
1116  * @adev: amdgpu_device pointer
1117  * @type: enum amd_ip_block_type
1118  * @major: major version
1119  * @minor: minor version
1120  *
1121  * return 0 if equal or greater
1122  * return 1 if smaller or the ip_block doesn't exist
1123  */
1124 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
1125                                 enum amd_ip_block_type type,
1126                                 u32 major, u32 minor)
1127 {
1128         const struct amdgpu_ip_block_version *ip_block;
1129         ip_block = amdgpu_get_ip_block(adev, type);
1130
1131         if (ip_block && ((ip_block->major > major) ||
1132                         ((ip_block->major == major) &&
1133                         (ip_block->minor >= minor))))
1134                 return 0;
1135
1136         return 1;
1137 }
1138
1139 static int amdgpu_early_init(struct amdgpu_device *adev)
1140 {
1141         int i, r;
1142
1143         switch (adev->asic_type) {
1144         case CHIP_TOPAZ:
1145         case CHIP_TONGA:
1146         case CHIP_FIJI:
1147         case CHIP_POLARIS11:
1148         case CHIP_POLARIS10:
1149         case CHIP_CARRIZO:
1150         case CHIP_STONEY:
1151                 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
1152                         adev->family = AMDGPU_FAMILY_CZ;
1153                 else
1154                         adev->family = AMDGPU_FAMILY_VI;
1155
1156                 r = vi_set_ip_blocks(adev);
1157                 if (r)
1158                         return r;
1159                 break;
1160 #ifdef CONFIG_DRM_AMDGPU_CIK
1161         case CHIP_BONAIRE:
1162         case CHIP_HAWAII:
1163         case CHIP_KAVERI:
1164         case CHIP_KABINI:
1165         case CHIP_MULLINS:
1166                 if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
1167                         adev->family = AMDGPU_FAMILY_CI;
1168                 else
1169                         adev->family = AMDGPU_FAMILY_KV;
1170
1171                 r = cik_set_ip_blocks(adev);
1172                 if (r)
1173                         return r;
1174                 break;
1175 #endif
1176         default:
1177                 /* FIXME: not supported yet */
1178                 return -EINVAL;
1179         }
1180
1181         adev->ip_block_status = kcalloc(adev->num_ip_blocks,
1182                                         sizeof(struct amdgpu_ip_block_status), GFP_KERNEL);
1183         if (adev->ip_block_status == NULL)
1184                 return -ENOMEM;
1185
1186         if (adev->ip_blocks == NULL) {
1187                 DRM_ERROR("No IP blocks found!\n");
1188                 return r;
1189         }
1190
1191         for (i = 0; i < adev->num_ip_blocks; i++) {
1192                 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1193                         DRM_ERROR("disabled ip block: %d\n", i);
1194                         adev->ip_block_status[i].valid = false;
1195                 } else {
1196                         if (adev->ip_blocks[i].funcs->early_init) {
1197                                 r = adev->ip_blocks[i].funcs->early_init((void *)adev);
1198                                 if (r == -ENOENT) {
1199                                         adev->ip_block_status[i].valid = false;
1200                                 } else if (r) {
1201                                         DRM_ERROR("early_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1202                                         return r;
1203                                 } else {
1204                                         adev->ip_block_status[i].valid = true;
1205                                 }
1206                         } else {
1207                                 adev->ip_block_status[i].valid = true;
1208                         }
1209                 }
1210         }
1211
1212         return 0;
1213 }
1214
1215 static int amdgpu_init(struct amdgpu_device *adev)
1216 {
1217         int i, r;
1218
1219         for (i = 0; i < adev->num_ip_blocks; i++) {
1220                 if (!adev->ip_block_status[i].valid)
1221                         continue;
1222                 r = adev->ip_blocks[i].funcs->sw_init((void *)adev);
1223                 if (r) {
1224                         DRM_ERROR("sw_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1225                         return r;
1226                 }
1227                 adev->ip_block_status[i].sw = true;
1228                 /* need to do gmc hw init early so we can allocate gpu mem */
1229                 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
1230                         r = amdgpu_vram_scratch_init(adev);
1231                         if (r) {
1232                                 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
1233                                 return r;
1234                         }
1235                         r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
1236                         if (r) {
1237                                 DRM_ERROR("hw_init %d failed %d\n", i, r);
1238                                 return r;
1239                         }
1240                         r = amdgpu_wb_init(adev);
1241                         if (r) {
1242                                 DRM_ERROR("amdgpu_wb_init failed %d\n", r);
1243                                 return r;
1244                         }
1245                         adev->ip_block_status[i].hw = true;
1246                 }
1247         }
1248
1249         for (i = 0; i < adev->num_ip_blocks; i++) {
1250                 if (!adev->ip_block_status[i].sw)
1251                         continue;
1252                 /* gmc hw init is done early */
1253                 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC)
1254                         continue;
1255                 r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
1256                 if (r) {
1257                         DRM_ERROR("hw_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1258                         return r;
1259                 }
1260                 adev->ip_block_status[i].hw = true;
1261         }
1262
1263         return 0;
1264 }
1265
1266 static int amdgpu_late_init(struct amdgpu_device *adev)
1267 {
1268         int i = 0, r;
1269
1270         for (i = 0; i < adev->num_ip_blocks; i++) {
1271                 if (!adev->ip_block_status[i].valid)
1272                         continue;
1273                 /* enable clockgating to save power */
1274                 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1275                                                                     AMD_CG_STATE_GATE);
1276                 if (r) {
1277                         DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1278                         return r;
1279                 }
1280                 if (adev->ip_blocks[i].funcs->late_init) {
1281                         r = adev->ip_blocks[i].funcs->late_init((void *)adev);
1282                         if (r) {
1283                                 DRM_ERROR("late_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1284                                 return r;
1285                         }
1286                 }
1287         }
1288
1289         return 0;
1290 }
1291
1292 static int amdgpu_fini(struct amdgpu_device *adev)
1293 {
1294         int i, r;
1295
1296         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1297                 if (!adev->ip_block_status[i].hw)
1298                         continue;
1299                 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
1300                         amdgpu_wb_fini(adev);
1301                         amdgpu_vram_scratch_fini(adev);
1302                 }
1303                 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1304                 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1305                                                                     AMD_CG_STATE_UNGATE);
1306                 if (r) {
1307                         DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1308                         return r;
1309                 }
1310                 r = adev->ip_blocks[i].funcs->hw_fini((void *)adev);
1311                 /* XXX handle errors */
1312                 if (r) {
1313                         DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1314                 }
1315                 adev->ip_block_status[i].hw = false;
1316         }
1317
1318         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1319                 if (!adev->ip_block_status[i].sw)
1320                         continue;
1321                 r = adev->ip_blocks[i].funcs->sw_fini((void *)adev);
1322                 /* XXX handle errors */
1323                 if (r) {
1324                         DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1325                 }
1326                 adev->ip_block_status[i].sw = false;
1327                 adev->ip_block_status[i].valid = false;
1328         }
1329
1330         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1331                 if (adev->ip_blocks[i].funcs->late_fini)
1332                         adev->ip_blocks[i].funcs->late_fini((void *)adev);
1333         }
1334
1335         return 0;
1336 }
1337
1338 static int amdgpu_suspend(struct amdgpu_device *adev)
1339 {
1340         int i, r;
1341
1342         /* ungate SMC block first */
1343         r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC,
1344                                          AMD_CG_STATE_UNGATE);
1345         if (r) {
1346                 DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r);
1347         }
1348
1349         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1350                 if (!adev->ip_block_status[i].valid)
1351                         continue;
1352                 /* ungate blocks so that suspend can properly shut them down */
1353                 if (i != AMD_IP_BLOCK_TYPE_SMC) {
1354                         r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1355                                                                             AMD_CG_STATE_UNGATE);
1356                         if (r) {
1357                                 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1358                         }
1359                 }
1360                 /* XXX handle errors */
1361                 r = adev->ip_blocks[i].funcs->suspend(adev);
1362                 /* XXX handle errors */
1363                 if (r) {
1364                         DRM_ERROR("suspend of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1365                 }
1366         }
1367
1368         return 0;
1369 }
1370
1371 static int amdgpu_resume(struct amdgpu_device *adev)
1372 {
1373         int i, r;
1374
1375         for (i = 0; i < adev->num_ip_blocks; i++) {
1376                 if (!adev->ip_block_status[i].valid)
1377                         continue;
1378                 r = adev->ip_blocks[i].funcs->resume(adev);
1379                 if (r) {
1380                         DRM_ERROR("resume of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1381                         return r;
1382                 }
1383         }
1384
1385         return 0;
1386 }
1387
1388 /**
1389  * amdgpu_device_init - initialize the driver
1390  *
1391  * @adev: amdgpu_device pointer
1392  * @pdev: drm dev pointer
1393  * @pdev: pci dev pointer
1394  * @flags: driver flags
1395  *
1396  * Initializes the driver info and hw (all asics).
1397  * Returns 0 for success or an error on failure.
1398  * Called at driver startup.
1399  */
1400 int amdgpu_device_init(struct amdgpu_device *adev,
1401                        struct drm_device *ddev,
1402                        struct pci_dev *pdev,
1403                        uint32_t flags)
1404 {
1405         int r, i;
1406         bool runtime = false;
1407
1408         adev->shutdown = false;
1409         adev->dev = &pdev->dev;
1410         adev->ddev = ddev;
1411         adev->pdev = pdev;
1412         adev->flags = flags;
1413         adev->asic_type = flags & AMD_ASIC_MASK;
1414         adev->is_atom_bios = false;
1415         adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
1416         adev->mc.gtt_size = 512 * 1024 * 1024;
1417         adev->accel_working = false;
1418         adev->num_rings = 0;
1419         adev->mman.buffer_funcs = NULL;
1420         adev->mman.buffer_funcs_ring = NULL;
1421         adev->vm_manager.vm_pte_funcs = NULL;
1422         adev->vm_manager.vm_pte_num_rings = 0;
1423         adev->gart.gart_funcs = NULL;
1424         adev->fence_context = fence_context_alloc(AMDGPU_MAX_RINGS);
1425
1426         adev->smc_rreg = &amdgpu_invalid_rreg;
1427         adev->smc_wreg = &amdgpu_invalid_wreg;
1428         adev->pcie_rreg = &amdgpu_invalid_rreg;
1429         adev->pcie_wreg = &amdgpu_invalid_wreg;
1430         adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
1431         adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
1432         adev->didt_rreg = &amdgpu_invalid_rreg;
1433         adev->didt_wreg = &amdgpu_invalid_wreg;
1434         adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
1435         adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
1436
1437         DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
1438                  amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
1439                  pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
1440
1441         /* mutex initialization are all done here so we
1442          * can recall function without having locking issues */
1443         mutex_init(&adev->vm_manager.lock);
1444         atomic_set(&adev->irq.ih.lock, 0);
1445         mutex_init(&adev->pm.mutex);
1446         mutex_init(&adev->gfx.gpu_clock_mutex);
1447         mutex_init(&adev->srbm_mutex);
1448         mutex_init(&adev->grbm_idx_mutex);
1449         mutex_init(&adev->mn_lock);
1450         hash_init(adev->mn_hash);
1451
1452         amdgpu_check_arguments(adev);
1453
1454         /* Registers mapping */
1455         /* TODO: block userspace mapping of io register */
1456         spin_lock_init(&adev->mmio_idx_lock);
1457         spin_lock_init(&adev->smc_idx_lock);
1458         spin_lock_init(&adev->pcie_idx_lock);
1459         spin_lock_init(&adev->uvd_ctx_idx_lock);
1460         spin_lock_init(&adev->didt_idx_lock);
1461         spin_lock_init(&adev->audio_endpt_idx_lock);
1462
1463         adev->rmmio_base = pci_resource_start(adev->pdev, 5);
1464         adev->rmmio_size = pci_resource_len(adev->pdev, 5);
1465         adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
1466         if (adev->rmmio == NULL) {
1467                 return -ENOMEM;
1468         }
1469         DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
1470         DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
1471
1472         /* doorbell bar mapping */
1473         amdgpu_doorbell_init(adev);
1474
1475         /* io port mapping */
1476         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1477                 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
1478                         adev->rio_mem_size = pci_resource_len(adev->pdev, i);
1479                         adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
1480                         break;
1481                 }
1482         }
1483         if (adev->rio_mem == NULL)
1484                 DRM_ERROR("Unable to find PCI I/O BAR\n");
1485
1486         /* early init functions */
1487         r = amdgpu_early_init(adev);
1488         if (r)
1489                 return r;
1490
1491         /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
1492         /* this will fail for cards that aren't VGA class devices, just
1493          * ignore it */
1494         vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode);
1495
1496         if (amdgpu_runtime_pm == 1)
1497                 runtime = true;
1498         if (amdgpu_device_is_px(ddev))
1499                 runtime = true;
1500         vga_switcheroo_register_client(adev->pdev, &amdgpu_switcheroo_ops, runtime);
1501         if (runtime)
1502                 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
1503
1504         /* Read BIOS */
1505         if (!amdgpu_get_bios(adev))
1506                 return -EINVAL;
1507         /* Must be an ATOMBIOS */
1508         if (!adev->is_atom_bios) {
1509                 dev_err(adev->dev, "Expecting atombios for GPU\n");
1510                 return -EINVAL;
1511         }
1512         r = amdgpu_atombios_init(adev);
1513         if (r) {
1514                 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
1515                 return r;
1516         }
1517
1518         /* See if the asic supports SR-IOV */
1519         adev->virtualization.supports_sr_iov =
1520                 amdgpu_atombios_has_gpu_virtualization_table(adev);
1521
1522         /* Post card if necessary */
1523         if (!amdgpu_card_posted(adev)) {
1524                 if (!adev->bios) {
1525                         dev_err(adev->dev, "Card not posted and no BIOS - ignoring\n");
1526                         return -EINVAL;
1527                 }
1528                 DRM_INFO("GPU not posted. posting now...\n");
1529                 amdgpu_atom_asic_init(adev->mode_info.atom_context);
1530         }
1531
1532         /* Initialize clocks */
1533         r = amdgpu_atombios_get_clock_info(adev);
1534         if (r) {
1535                 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
1536                 return r;
1537         }
1538         /* init i2c buses */
1539         amdgpu_atombios_i2c_init(adev);
1540
1541         /* Fence driver */
1542         r = amdgpu_fence_driver_init(adev);
1543         if (r) {
1544                 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
1545                 return r;
1546         }
1547
1548         /* init the mode config */
1549         drm_mode_config_init(adev->ddev);
1550
1551         r = amdgpu_init(adev);
1552         if (r) {
1553                 dev_err(adev->dev, "amdgpu_init failed\n");
1554                 amdgpu_fini(adev);
1555                 return r;
1556         }
1557
1558         adev->accel_working = true;
1559
1560         amdgpu_fbdev_init(adev);
1561
1562         r = amdgpu_ib_pool_init(adev);
1563         if (r) {
1564                 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
1565                 return r;
1566         }
1567
1568         r = amdgpu_ib_ring_tests(adev);
1569         if (r)
1570                 DRM_ERROR("ib ring test failed (%d).\n", r);
1571
1572         r = amdgpu_gem_debugfs_init(adev);
1573         if (r) {
1574                 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
1575         }
1576
1577         r = amdgpu_debugfs_regs_init(adev);
1578         if (r) {
1579                 DRM_ERROR("registering register debugfs failed (%d).\n", r);
1580         }
1581
1582         if ((amdgpu_testing & 1)) {
1583                 if (adev->accel_working)
1584                         amdgpu_test_moves(adev);
1585                 else
1586                         DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
1587         }
1588         if ((amdgpu_testing & 2)) {
1589                 if (adev->accel_working)
1590                         amdgpu_test_syncing(adev);
1591                 else
1592                         DRM_INFO("amdgpu: acceleration disabled, skipping sync tests\n");
1593         }
1594         if (amdgpu_benchmarking) {
1595                 if (adev->accel_working)
1596                         amdgpu_benchmark(adev, amdgpu_benchmarking);
1597                 else
1598                         DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
1599         }
1600
1601         /* enable clockgating, etc. after ib tests, etc. since some blocks require
1602          * explicit gating rather than handling it automatically.
1603          */
1604         r = amdgpu_late_init(adev);
1605         if (r) {
1606                 dev_err(adev->dev, "amdgpu_late_init failed\n");
1607                 return r;
1608         }
1609
1610         return 0;
1611 }
1612
1613 static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev);
1614
1615 /**
1616  * amdgpu_device_fini - tear down the driver
1617  *
1618  * @adev: amdgpu_device pointer
1619  *
1620  * Tear down the driver info (all asics).
1621  * Called at driver shutdown.
1622  */
1623 void amdgpu_device_fini(struct amdgpu_device *adev)
1624 {
1625         int r;
1626
1627         DRM_INFO("amdgpu: finishing device.\n");
1628         adev->shutdown = true;
1629         /* evict vram memory */
1630         amdgpu_bo_evict_vram(adev);
1631         amdgpu_ib_pool_fini(adev);
1632         amdgpu_fence_driver_fini(adev);
1633         amdgpu_fbdev_fini(adev);
1634         r = amdgpu_fini(adev);
1635         kfree(adev->ip_block_status);
1636         adev->ip_block_status = NULL;
1637         adev->accel_working = false;
1638         /* free i2c buses */
1639         amdgpu_i2c_fini(adev);
1640         amdgpu_atombios_fini(adev);
1641         kfree(adev->bios);
1642         adev->bios = NULL;
1643         vga_switcheroo_unregister_client(adev->pdev);
1644         vga_client_register(adev->pdev, NULL, NULL, NULL);
1645         if (adev->rio_mem)
1646                 pci_iounmap(adev->pdev, adev->rio_mem);
1647         adev->rio_mem = NULL;
1648         iounmap(adev->rmmio);
1649         adev->rmmio = NULL;
1650         amdgpu_doorbell_fini(adev);
1651         amdgpu_debugfs_regs_cleanup(adev);
1652         amdgpu_debugfs_remove_files(adev);
1653 }
1654
1655
1656 /*
1657  * Suspend & resume.
1658  */
1659 /**
1660  * amdgpu_suspend_kms - initiate device suspend
1661  *
1662  * @pdev: drm dev pointer
1663  * @state: suspend state
1664  *
1665  * Puts the hw in the suspend state (all asics).
1666  * Returns 0 for success or an error on failure.
1667  * Called at driver suspend.
1668  */
1669 int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon)
1670 {
1671         struct amdgpu_device *adev;
1672         struct drm_crtc *crtc;
1673         struct drm_connector *connector;
1674         int r;
1675
1676         if (dev == NULL || dev->dev_private == NULL) {
1677                 return -ENODEV;
1678         }
1679
1680         adev = dev->dev_private;
1681
1682         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1683                 return 0;
1684
1685         drm_kms_helper_poll_disable(dev);
1686
1687         /* turn off display hw */
1688         drm_modeset_lock_all(dev);
1689         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1690                 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
1691         }
1692         drm_modeset_unlock_all(dev);
1693
1694         /* unpin the front buffers and cursors */
1695         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1696                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1697                 struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb);
1698                 struct amdgpu_bo *robj;
1699
1700                 if (amdgpu_crtc->cursor_bo) {
1701                         struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1702                         r = amdgpu_bo_reserve(aobj, false);
1703                         if (r == 0) {
1704                                 amdgpu_bo_unpin(aobj);
1705                                 amdgpu_bo_unreserve(aobj);
1706                         }
1707                 }
1708
1709                 if (rfb == NULL || rfb->obj == NULL) {
1710                         continue;
1711                 }
1712                 robj = gem_to_amdgpu_bo(rfb->obj);
1713                 /* don't unpin kernel fb objects */
1714                 if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
1715                         r = amdgpu_bo_reserve(robj, false);
1716                         if (r == 0) {
1717                                 amdgpu_bo_unpin(robj);
1718                                 amdgpu_bo_unreserve(robj);
1719                         }
1720                 }
1721         }
1722         /* evict vram memory */
1723         amdgpu_bo_evict_vram(adev);
1724
1725         amdgpu_fence_driver_suspend(adev);
1726
1727         r = amdgpu_suspend(adev);
1728
1729         /* evict remaining vram memory */
1730         amdgpu_bo_evict_vram(adev);
1731
1732         pci_save_state(dev->pdev);
1733         if (suspend) {
1734                 /* Shut down the device */
1735                 pci_disable_device(dev->pdev);
1736                 pci_set_power_state(dev->pdev, PCI_D3hot);
1737         }
1738
1739         if (fbcon) {
1740                 console_lock();
1741                 amdgpu_fbdev_set_suspend(adev, 1);
1742                 console_unlock();
1743         }
1744         return 0;
1745 }
1746
1747 /**
1748  * amdgpu_resume_kms - initiate device resume
1749  *
1750  * @pdev: drm dev pointer
1751  *
1752  * Bring the hw back to operating state (all asics).
1753  * Returns 0 for success or an error on failure.
1754  * Called at driver resume.
1755  */
1756 int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
1757 {
1758         struct drm_connector *connector;
1759         struct amdgpu_device *adev = dev->dev_private;
1760         struct drm_crtc *crtc;
1761         int r;
1762
1763         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1764                 return 0;
1765
1766         if (fbcon) {
1767                 console_lock();
1768         }
1769         if (resume) {
1770                 pci_set_power_state(dev->pdev, PCI_D0);
1771                 pci_restore_state(dev->pdev);
1772                 if (pci_enable_device(dev->pdev)) {
1773                         if (fbcon)
1774                                 console_unlock();
1775                         return -1;
1776                 }
1777         }
1778
1779         /* post card */
1780         if (!amdgpu_card_posted(adev))
1781                 amdgpu_atom_asic_init(adev->mode_info.atom_context);
1782
1783         r = amdgpu_resume(adev);
1784         if (r)
1785                 DRM_ERROR("amdgpu_resume failed (%d).\n", r);
1786
1787         amdgpu_fence_driver_resume(adev);
1788
1789         if (resume) {
1790                 r = amdgpu_ib_ring_tests(adev);
1791                 if (r)
1792                         DRM_ERROR("ib ring test failed (%d).\n", r);
1793         }
1794
1795         r = amdgpu_late_init(adev);
1796         if (r)
1797                 return r;
1798
1799         /* pin cursors */
1800         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1801                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1802
1803                 if (amdgpu_crtc->cursor_bo) {
1804                         struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1805                         r = amdgpu_bo_reserve(aobj, false);
1806                         if (r == 0) {
1807                                 r = amdgpu_bo_pin(aobj,
1808                                                   AMDGPU_GEM_DOMAIN_VRAM,
1809                                                   &amdgpu_crtc->cursor_addr);
1810                                 if (r != 0)
1811                                         DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
1812                                 amdgpu_bo_unreserve(aobj);
1813                         }
1814                 }
1815         }
1816
1817         /* blat the mode back in */
1818         if (fbcon) {
1819                 drm_helper_resume_force_mode(dev);
1820                 /* turn on display hw */
1821                 drm_modeset_lock_all(dev);
1822                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1823                         drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
1824                 }
1825                 drm_modeset_unlock_all(dev);
1826         }
1827
1828         drm_kms_helper_poll_enable(dev);
1829         drm_helper_hpd_irq_event(dev);
1830
1831         if (fbcon) {
1832                 amdgpu_fbdev_set_suspend(adev, 0);
1833                 console_unlock();
1834         }
1835
1836         return 0;
1837 }
1838
1839 /**
1840  * amdgpu_gpu_reset - reset the asic
1841  *
1842  * @adev: amdgpu device pointer
1843  *
1844  * Attempt the reset the GPU if it has hung (all asics).
1845  * Returns 0 for success or an error on failure.
1846  */
1847 int amdgpu_gpu_reset(struct amdgpu_device *adev)
1848 {
1849         unsigned ring_sizes[AMDGPU_MAX_RINGS];
1850         uint32_t *ring_data[AMDGPU_MAX_RINGS];
1851
1852         bool saved = false;
1853
1854         int i, r;
1855         int resched;
1856
1857         atomic_inc(&adev->gpu_reset_counter);
1858
1859         /* block TTM */
1860         resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
1861
1862         r = amdgpu_suspend(adev);
1863
1864         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1865                 struct amdgpu_ring *ring = adev->rings[i];
1866                 if (!ring)
1867                         continue;
1868
1869                 ring_sizes[i] = amdgpu_ring_backup(ring, &ring_data[i]);
1870                 if (ring_sizes[i]) {
1871                         saved = true;
1872                         dev_info(adev->dev, "Saved %d dwords of commands "
1873                                  "on ring %d.\n", ring_sizes[i], i);
1874                 }
1875         }
1876
1877 retry:
1878         r = amdgpu_asic_reset(adev);
1879         /* post card */
1880         amdgpu_atom_asic_init(adev->mode_info.atom_context);
1881
1882         if (!r) {
1883                 dev_info(adev->dev, "GPU reset succeeded, trying to resume\n");
1884                 r = amdgpu_resume(adev);
1885         }
1886
1887         if (!r) {
1888                 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1889                         struct amdgpu_ring *ring = adev->rings[i];
1890                         if (!ring)
1891                                 continue;
1892
1893                         amdgpu_ring_restore(ring, ring_sizes[i], ring_data[i]);
1894                         ring_sizes[i] = 0;
1895                         ring_data[i] = NULL;
1896                 }
1897
1898                 r = amdgpu_ib_ring_tests(adev);
1899                 if (r) {
1900                         dev_err(adev->dev, "ib ring test failed (%d).\n", r);
1901                         if (saved) {
1902                                 saved = false;
1903                                 r = amdgpu_suspend(adev);
1904                                 goto retry;
1905                         }
1906                 }
1907         } else {
1908                 amdgpu_fence_driver_force_completion(adev);
1909                 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1910                         if (adev->rings[i])
1911                                 kfree(ring_data[i]);
1912                 }
1913         }
1914
1915         drm_helper_resume_force_mode(adev->ddev);
1916
1917         ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
1918         if (r) {
1919                 /* bad news, how to tell it to userspace ? */
1920                 dev_info(adev->dev, "GPU reset failed\n");
1921         }
1922
1923         return r;
1924 }
1925
1926 #define AMDGPU_DEFAULT_PCIE_GEN_MASK 0x30007  /* gen: chipset 1/2, asic 1/2/3 */
1927 #define AMDGPU_DEFAULT_PCIE_MLW_MASK 0x2f0000 /* 1/2/4/8/16 lanes */
1928
1929 void amdgpu_get_pcie_info(struct amdgpu_device *adev)
1930 {
1931         u32 mask;
1932         int ret;
1933
1934         if (amdgpu_pcie_gen_cap)
1935                 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
1936
1937         if (amdgpu_pcie_lane_cap)
1938                 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
1939
1940         /* covers APUs as well */
1941         if (pci_is_root_bus(adev->pdev->bus)) {
1942                 if (adev->pm.pcie_gen_mask == 0)
1943                         adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
1944                 if (adev->pm.pcie_mlw_mask == 0)
1945                         adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
1946                 return;
1947         }
1948
1949         if (adev->pm.pcie_gen_mask == 0) {
1950                 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
1951                 if (!ret) {
1952                         adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
1953                                                   CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
1954                                                   CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
1955
1956                         if (mask & DRM_PCIE_SPEED_25)
1957                                 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
1958                         if (mask & DRM_PCIE_SPEED_50)
1959                                 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;
1960                         if (mask & DRM_PCIE_SPEED_80)
1961                                 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;
1962                 } else {
1963                         adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
1964                 }
1965         }
1966         if (adev->pm.pcie_mlw_mask == 0) {
1967                 ret = drm_pcie_get_max_link_width(adev->ddev, &mask);
1968                 if (!ret) {
1969                         switch (mask) {
1970                         case 32:
1971                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
1972                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
1973                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
1974                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
1975                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
1976                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
1977                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
1978                                 break;
1979                         case 16:
1980                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
1981                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
1982                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
1983                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
1984                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
1985                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
1986                                 break;
1987                         case 12:
1988                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
1989                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
1990                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
1991                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
1992                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
1993                                 break;
1994                         case 8:
1995                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
1996                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
1997                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
1998                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
1999                                 break;
2000                         case 4:
2001                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2002                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2003                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2004                                 break;
2005                         case 2:
2006                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2007                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2008                                 break;
2009                         case 1:
2010                                 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
2011                                 break;
2012                         default:
2013                                 break;
2014                         }
2015                 } else {
2016                         adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
2017                 }
2018         }
2019 }
2020
2021 /*
2022  * Debugfs
2023  */
2024 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
2025                              const struct drm_info_list *files,
2026                              unsigned nfiles)
2027 {
2028         unsigned i;
2029
2030         for (i = 0; i < adev->debugfs_count; i++) {
2031                 if (adev->debugfs[i].files == files) {
2032                         /* Already registered */
2033                         return 0;
2034                 }
2035         }
2036
2037         i = adev->debugfs_count + 1;
2038         if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) {
2039                 DRM_ERROR("Reached maximum number of debugfs components.\n");
2040                 DRM_ERROR("Report so we increase "
2041                           "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n");
2042                 return -EINVAL;
2043         }
2044         adev->debugfs[adev->debugfs_count].files = files;
2045         adev->debugfs[adev->debugfs_count].num_files = nfiles;
2046         adev->debugfs_count = i;
2047 #if defined(CONFIG_DEBUG_FS)
2048         drm_debugfs_create_files(files, nfiles,
2049                                  adev->ddev->control->debugfs_root,
2050                                  adev->ddev->control);
2051         drm_debugfs_create_files(files, nfiles,
2052                                  adev->ddev->primary->debugfs_root,
2053                                  adev->ddev->primary);
2054 #endif
2055         return 0;
2056 }
2057
2058 static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev)
2059 {
2060 #if defined(CONFIG_DEBUG_FS)
2061         unsigned i;
2062
2063         for (i = 0; i < adev->debugfs_count; i++) {
2064                 drm_debugfs_remove_files(adev->debugfs[i].files,
2065                                          adev->debugfs[i].num_files,
2066                                          adev->ddev->control);
2067                 drm_debugfs_remove_files(adev->debugfs[i].files,
2068                                          adev->debugfs[i].num_files,
2069                                          adev->ddev->primary);
2070         }
2071 #endif
2072 }
2073
2074 #if defined(CONFIG_DEBUG_FS)
2075
2076 static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
2077                                         size_t size, loff_t *pos)
2078 {
2079         struct amdgpu_device *adev = f->f_inode->i_private;
2080         ssize_t result = 0;
2081         int r;
2082
2083         if (size & 0x3 || *pos & 0x3)
2084                 return -EINVAL;
2085
2086         while (size) {
2087                 uint32_t value;
2088
2089                 if (*pos > adev->rmmio_size)
2090                         return result;
2091
2092                 value = RREG32(*pos >> 2);
2093                 r = put_user(value, (uint32_t *)buf);
2094                 if (r)
2095                         return r;
2096
2097                 result += 4;
2098                 buf += 4;
2099                 *pos += 4;
2100                 size -= 4;
2101         }
2102
2103         return result;
2104 }
2105
2106 static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
2107                                          size_t size, loff_t *pos)
2108 {
2109         struct amdgpu_device *adev = f->f_inode->i_private;
2110         ssize_t result = 0;
2111         int r;
2112
2113         if (size & 0x3 || *pos & 0x3)
2114                 return -EINVAL;
2115
2116         while (size) {
2117                 uint32_t value;
2118
2119                 if (*pos > adev->rmmio_size)
2120                         return result;
2121
2122                 r = get_user(value, (uint32_t *)buf);
2123                 if (r)
2124                         return r;
2125
2126                 WREG32(*pos >> 2, value);
2127
2128                 result += 4;
2129                 buf += 4;
2130                 *pos += 4;
2131                 size -= 4;
2132         }
2133
2134         return result;
2135 }
2136
2137 static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf,
2138                                         size_t size, loff_t *pos)
2139 {
2140         struct amdgpu_device *adev = f->f_inode->i_private;
2141         ssize_t result = 0;
2142         int r;
2143
2144         if (size & 0x3 || *pos & 0x3)
2145                 return -EINVAL;
2146
2147         while (size) {
2148                 uint32_t value;
2149
2150                 value = RREG32_PCIE(*pos >> 2);
2151                 r = put_user(value, (uint32_t *)buf);
2152                 if (r)
2153                         return r;
2154
2155                 result += 4;
2156                 buf += 4;
2157                 *pos += 4;
2158                 size -= 4;
2159         }
2160
2161         return result;
2162 }
2163
2164 static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf,
2165                                          size_t size, loff_t *pos)
2166 {
2167         struct amdgpu_device *adev = f->f_inode->i_private;
2168         ssize_t result = 0;
2169         int r;
2170
2171         if (size & 0x3 || *pos & 0x3)
2172                 return -EINVAL;
2173
2174         while (size) {
2175                 uint32_t value;
2176
2177                 r = get_user(value, (uint32_t *)buf);
2178                 if (r)
2179                         return r;
2180
2181                 WREG32_PCIE(*pos >> 2, value);
2182
2183                 result += 4;
2184                 buf += 4;
2185                 *pos += 4;
2186                 size -= 4;
2187         }
2188
2189         return result;
2190 }
2191
2192 static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf,
2193                                         size_t size, loff_t *pos)
2194 {
2195         struct amdgpu_device *adev = f->f_inode->i_private;
2196         ssize_t result = 0;
2197         int r;
2198
2199         if (size & 0x3 || *pos & 0x3)
2200                 return -EINVAL;
2201
2202         while (size) {
2203                 uint32_t value;
2204
2205                 value = RREG32_DIDT(*pos >> 2);
2206                 r = put_user(value, (uint32_t *)buf);
2207                 if (r)
2208                         return r;
2209
2210                 result += 4;
2211                 buf += 4;
2212                 *pos += 4;
2213                 size -= 4;
2214         }
2215
2216         return result;
2217 }
2218
2219 static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf,
2220                                          size_t size, loff_t *pos)
2221 {
2222         struct amdgpu_device *adev = f->f_inode->i_private;
2223         ssize_t result = 0;
2224         int r;
2225
2226         if (size & 0x3 || *pos & 0x3)
2227                 return -EINVAL;
2228
2229         while (size) {
2230                 uint32_t value;
2231
2232                 r = get_user(value, (uint32_t *)buf);
2233                 if (r)
2234                         return r;
2235
2236                 WREG32_DIDT(*pos >> 2, value);
2237
2238                 result += 4;
2239                 buf += 4;
2240                 *pos += 4;
2241                 size -= 4;
2242         }
2243
2244         return result;
2245 }
2246
2247 static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf,
2248                                         size_t size, loff_t *pos)
2249 {
2250         struct amdgpu_device *adev = f->f_inode->i_private;
2251         ssize_t result = 0;
2252         int r;
2253
2254         if (size & 0x3 || *pos & 0x3)
2255                 return -EINVAL;
2256
2257         while (size) {
2258                 uint32_t value;
2259
2260                 value = RREG32_SMC(*pos >> 2);
2261                 r = put_user(value, (uint32_t *)buf);
2262                 if (r)
2263                         return r;
2264
2265                 result += 4;
2266                 buf += 4;
2267                 *pos += 4;
2268                 size -= 4;
2269         }
2270
2271         return result;
2272 }
2273
2274 static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf,
2275                                          size_t size, loff_t *pos)
2276 {
2277         struct amdgpu_device *adev = f->f_inode->i_private;
2278         ssize_t result = 0;
2279         int r;
2280
2281         if (size & 0x3 || *pos & 0x3)
2282                 return -EINVAL;
2283
2284         while (size) {
2285                 uint32_t value;
2286
2287                 r = get_user(value, (uint32_t *)buf);
2288                 if (r)
2289                         return r;
2290
2291                 WREG32_SMC(*pos >> 2, value);
2292
2293                 result += 4;
2294                 buf += 4;
2295                 *pos += 4;
2296                 size -= 4;
2297         }
2298
2299         return result;
2300 }
2301
2302 static const struct file_operations amdgpu_debugfs_regs_fops = {
2303         .owner = THIS_MODULE,
2304         .read = amdgpu_debugfs_regs_read,
2305         .write = amdgpu_debugfs_regs_write,
2306         .llseek = default_llseek
2307 };
2308 static const struct file_operations amdgpu_debugfs_regs_didt_fops = {
2309         .owner = THIS_MODULE,
2310         .read = amdgpu_debugfs_regs_didt_read,
2311         .write = amdgpu_debugfs_regs_didt_write,
2312         .llseek = default_llseek
2313 };
2314 static const struct file_operations amdgpu_debugfs_regs_pcie_fops = {
2315         .owner = THIS_MODULE,
2316         .read = amdgpu_debugfs_regs_pcie_read,
2317         .write = amdgpu_debugfs_regs_pcie_write,
2318         .llseek = default_llseek
2319 };
2320 static const struct file_operations amdgpu_debugfs_regs_smc_fops = {
2321         .owner = THIS_MODULE,
2322         .read = amdgpu_debugfs_regs_smc_read,
2323         .write = amdgpu_debugfs_regs_smc_write,
2324         .llseek = default_llseek
2325 };
2326
2327 static const struct file_operations *debugfs_regs[] = {
2328         &amdgpu_debugfs_regs_fops,
2329         &amdgpu_debugfs_regs_didt_fops,
2330         &amdgpu_debugfs_regs_pcie_fops,
2331         &amdgpu_debugfs_regs_smc_fops,
2332 };
2333
2334 static const char *debugfs_regs_names[] = {
2335         "amdgpu_regs",
2336         "amdgpu_regs_didt",
2337         "amdgpu_regs_pcie",
2338         "amdgpu_regs_smc",
2339 };
2340
2341 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
2342 {
2343         struct drm_minor *minor = adev->ddev->primary;
2344         struct dentry *ent, *root = minor->debugfs_root;
2345         unsigned i, j;
2346
2347         for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
2348                 ent = debugfs_create_file(debugfs_regs_names[i],
2349                                           S_IFREG | S_IRUGO, root,
2350                                           adev, debugfs_regs[i]);
2351                 if (IS_ERR(ent)) {
2352                         for (j = 0; j < i; j++) {
2353                                 debugfs_remove(adev->debugfs_regs[i]);
2354                                 adev->debugfs_regs[i] = NULL;
2355                         }
2356                         return PTR_ERR(ent);
2357                 }
2358
2359                 if (!i)
2360                         i_size_write(ent->d_inode, adev->rmmio_size);
2361                 adev->debugfs_regs[i] = ent;
2362         }
2363
2364         return 0;
2365 }
2366
2367 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev)
2368 {
2369         unsigned i;
2370
2371         for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
2372                 if (adev->debugfs_regs[i]) {
2373                         debugfs_remove(adev->debugfs_regs[i]);
2374                         adev->debugfs_regs[i] = NULL;
2375                 }
2376         }
2377 }
2378
2379 int amdgpu_debugfs_init(struct drm_minor *minor)
2380 {
2381         return 0;
2382 }
2383
2384 void amdgpu_debugfs_cleanup(struct drm_minor *minor)
2385 {
2386 }
2387 #else
2388 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
2389 {
2390         return 0;
2391 }
2392 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { }
2393 #endif