2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/kthread.h>
29 #include <linux/console.h>
30 #include <linux/slab.h>
31 #include <linux/debugfs.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/amdgpu_drm.h>
35 #include <linux/vgaarb.h>
36 #include <linux/vga_switcheroo.h>
37 #include <linux/efi.h>
39 #include "amdgpu_trace.h"
40 #include "amdgpu_i2c.h"
42 #include "amdgpu_atombios.h"
44 #ifdef CONFIG_DRM_AMDGPU_SI
47 #ifdef CONFIG_DRM_AMDGPU_CIK
51 #include "bif/bif_4_1_d.h"
52 #include <linux/pci.h>
53 #include <linux/firmware.h>
55 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev);
56 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev);
58 static const char *amdgpu_asic_name[] = {
79 bool amdgpu_device_is_px(struct drm_device *dev)
81 struct amdgpu_device *adev = dev->dev_private;
83 if (adev->flags & AMD_IS_PX)
89 * MMIO register access helper functions.
91 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
96 if ((reg * 4) < adev->rmmio_size && !always_indirect)
97 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
101 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
102 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
103 ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
104 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
106 trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret);
110 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
111 bool always_indirect)
113 trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
115 if ((reg * 4) < adev->rmmio_size && !always_indirect)
116 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
120 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
121 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
122 writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
123 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
127 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
129 if ((reg * 4) < adev->rio_mem_size)
130 return ioread32(adev->rio_mem + (reg * 4));
132 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
133 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
137 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
140 if ((reg * 4) < adev->rio_mem_size)
141 iowrite32(v, adev->rio_mem + (reg * 4));
143 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
144 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
149 * amdgpu_mm_rdoorbell - read a doorbell dword
151 * @adev: amdgpu_device pointer
152 * @index: doorbell index
154 * Returns the value in the doorbell aperture at the
155 * requested doorbell index (CIK).
157 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
159 if (index < adev->doorbell.num_doorbells) {
160 return readl(adev->doorbell.ptr + index);
162 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
168 * amdgpu_mm_wdoorbell - write a doorbell dword
170 * @adev: amdgpu_device pointer
171 * @index: doorbell index
174 * Writes @v to the doorbell aperture at the
175 * requested doorbell index (CIK).
177 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
179 if (index < adev->doorbell.num_doorbells) {
180 writel(v, adev->doorbell.ptr + index);
182 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
187 * amdgpu_invalid_rreg - dummy reg read function
189 * @adev: amdgpu device pointer
190 * @reg: offset of register
192 * Dummy register read function. Used for register blocks
193 * that certain asics don't have (all asics).
194 * Returns the value in the register.
196 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
198 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
204 * amdgpu_invalid_wreg - dummy reg write function
206 * @adev: amdgpu device pointer
207 * @reg: offset of register
208 * @v: value to write to the register
210 * Dummy register read function. Used for register blocks
211 * that certain asics don't have (all asics).
213 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
215 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
221 * amdgpu_block_invalid_rreg - dummy reg read function
223 * @adev: amdgpu device pointer
224 * @block: offset of instance
225 * @reg: offset of register
227 * Dummy register read function. Used for register blocks
228 * that certain asics don't have (all asics).
229 * Returns the value in the register.
231 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
232 uint32_t block, uint32_t reg)
234 DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
241 * amdgpu_block_invalid_wreg - dummy reg write function
243 * @adev: amdgpu device pointer
244 * @block: offset of instance
245 * @reg: offset of register
246 * @v: value to write to the register
248 * Dummy register read function. Used for register blocks
249 * that certain asics don't have (all asics).
251 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
253 uint32_t reg, uint32_t v)
255 DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
260 static int amdgpu_vram_scratch_init(struct amdgpu_device *adev)
264 if (adev->vram_scratch.robj == NULL) {
265 r = amdgpu_bo_create(adev, AMDGPU_GPU_PAGE_SIZE,
266 PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM,
267 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
268 NULL, NULL, &adev->vram_scratch.robj);
274 r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
275 if (unlikely(r != 0))
277 r = amdgpu_bo_pin(adev->vram_scratch.robj,
278 AMDGPU_GEM_DOMAIN_VRAM, &adev->vram_scratch.gpu_addr);
280 amdgpu_bo_unreserve(adev->vram_scratch.robj);
283 r = amdgpu_bo_kmap(adev->vram_scratch.robj,
284 (void **)&adev->vram_scratch.ptr);
286 amdgpu_bo_unpin(adev->vram_scratch.robj);
287 amdgpu_bo_unreserve(adev->vram_scratch.robj);
292 static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev)
296 if (adev->vram_scratch.robj == NULL) {
299 r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
300 if (likely(r == 0)) {
301 amdgpu_bo_kunmap(adev->vram_scratch.robj);
302 amdgpu_bo_unpin(adev->vram_scratch.robj);
303 amdgpu_bo_unreserve(adev->vram_scratch.robj);
305 amdgpu_bo_unref(&adev->vram_scratch.robj);
309 * amdgpu_program_register_sequence - program an array of registers.
311 * @adev: amdgpu_device pointer
312 * @registers: pointer to the register array
313 * @array_size: size of the register array
315 * Programs an array or registers with and and or masks.
316 * This is a helper for setting golden registers.
318 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
319 const u32 *registers,
320 const u32 array_size)
322 u32 tmp, reg, and_mask, or_mask;
328 for (i = 0; i < array_size; i +=3) {
329 reg = registers[i + 0];
330 and_mask = registers[i + 1];
331 or_mask = registers[i + 2];
333 if (and_mask == 0xffffffff) {
344 void amdgpu_pci_config_reset(struct amdgpu_device *adev)
346 pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
350 * GPU doorbell aperture helpers function.
353 * amdgpu_doorbell_init - Init doorbell driver information.
355 * @adev: amdgpu_device pointer
357 * Init doorbell driver information (CIK)
358 * Returns 0 on success, error on failure.
360 static int amdgpu_doorbell_init(struct amdgpu_device *adev)
362 /* doorbell bar mapping */
363 adev->doorbell.base = pci_resource_start(adev->pdev, 2);
364 adev->doorbell.size = pci_resource_len(adev->pdev, 2);
366 adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
367 AMDGPU_DOORBELL_MAX_ASSIGNMENT+1);
368 if (adev->doorbell.num_doorbells == 0)
371 adev->doorbell.ptr = ioremap(adev->doorbell.base, adev->doorbell.num_doorbells * sizeof(u32));
372 if (adev->doorbell.ptr == NULL) {
375 DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)adev->doorbell.base);
376 DRM_INFO("doorbell mmio size: %u\n", (unsigned)adev->doorbell.size);
382 * amdgpu_doorbell_fini - Tear down doorbell driver information.
384 * @adev: amdgpu_device pointer
386 * Tear down doorbell driver information (CIK)
388 static void amdgpu_doorbell_fini(struct amdgpu_device *adev)
390 iounmap(adev->doorbell.ptr);
391 adev->doorbell.ptr = NULL;
395 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
398 * @adev: amdgpu_device pointer
399 * @aperture_base: output returning doorbell aperture base physical address
400 * @aperture_size: output returning doorbell aperture size in bytes
401 * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
403 * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
404 * takes doorbells required for its own rings and reports the setup to amdkfd.
405 * amdgpu reserved doorbells are at the start of the doorbell aperture.
407 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
408 phys_addr_t *aperture_base,
409 size_t *aperture_size,
410 size_t *start_offset)
413 * The first num_doorbells are used by amdgpu.
414 * amdkfd takes whatever's left in the aperture.
416 if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
417 *aperture_base = adev->doorbell.base;
418 *aperture_size = adev->doorbell.size;
419 *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
429 * Writeback is the the method by which the the GPU updates special pages
430 * in memory with the status of certain GPU events (fences, ring pointers,
435 * amdgpu_wb_fini - Disable Writeback and free memory
437 * @adev: amdgpu_device pointer
439 * Disables Writeback and frees the Writeback memory (all asics).
440 * Used at driver shutdown.
442 static void amdgpu_wb_fini(struct amdgpu_device *adev)
444 if (adev->wb.wb_obj) {
445 if (!amdgpu_bo_reserve(adev->wb.wb_obj, false)) {
446 amdgpu_bo_kunmap(adev->wb.wb_obj);
447 amdgpu_bo_unpin(adev->wb.wb_obj);
448 amdgpu_bo_unreserve(adev->wb.wb_obj);
450 amdgpu_bo_unref(&adev->wb.wb_obj);
452 adev->wb.wb_obj = NULL;
457 * amdgpu_wb_init- Init Writeback driver info and allocate memory
459 * @adev: amdgpu_device pointer
461 * Disables Writeback and frees the Writeback memory (all asics).
462 * Used at driver startup.
463 * Returns 0 on success or an -error on failure.
465 static int amdgpu_wb_init(struct amdgpu_device *adev)
469 if (adev->wb.wb_obj == NULL) {
470 r = amdgpu_bo_create(adev, AMDGPU_MAX_WB * 4, PAGE_SIZE, true,
471 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
474 dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
477 r = amdgpu_bo_reserve(adev->wb.wb_obj, false);
478 if (unlikely(r != 0)) {
479 amdgpu_wb_fini(adev);
482 r = amdgpu_bo_pin(adev->wb.wb_obj, AMDGPU_GEM_DOMAIN_GTT,
485 amdgpu_bo_unreserve(adev->wb.wb_obj);
486 dev_warn(adev->dev, "(%d) pin WB bo failed\n", r);
487 amdgpu_wb_fini(adev);
490 r = amdgpu_bo_kmap(adev->wb.wb_obj, (void **)&adev->wb.wb);
491 amdgpu_bo_unreserve(adev->wb.wb_obj);
493 dev_warn(adev->dev, "(%d) map WB bo failed\n", r);
494 amdgpu_wb_fini(adev);
498 adev->wb.num_wb = AMDGPU_MAX_WB;
499 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
501 /* clear wb memory */
502 memset((char *)adev->wb.wb, 0, AMDGPU_GPU_PAGE_SIZE);
509 * amdgpu_wb_get - Allocate a wb entry
511 * @adev: amdgpu_device pointer
514 * Allocate a wb slot for use by the driver (all asics).
515 * Returns 0 on success or -EINVAL on failure.
517 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb)
519 unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
520 if (offset < adev->wb.num_wb) {
521 __set_bit(offset, adev->wb.used);
530 * amdgpu_wb_free - Free a wb entry
532 * @adev: amdgpu_device pointer
535 * Free a wb slot allocated for use by the driver (all asics)
537 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb)
539 if (wb < adev->wb.num_wb)
540 __clear_bit(wb, adev->wb.used);
544 * amdgpu_vram_location - try to find VRAM location
545 * @adev: amdgpu device structure holding all necessary informations
546 * @mc: memory controller structure holding memory informations
547 * @base: base address at which to put VRAM
549 * Function will place try to place VRAM at base address provided
550 * as parameter (which is so far either PCI aperture address or
551 * for IGP TOM base address).
553 * If there is not enough space to fit the unvisible VRAM in the 32bits
554 * address space then we limit the VRAM size to the aperture.
556 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
557 * this shouldn't be a problem as we are using the PCI aperture as a reference.
558 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
561 * Note: we use mc_vram_size as on some board we need to program the mc to
562 * cover the whole aperture even if VRAM size is inferior to aperture size
563 * Novell bug 204882 + along with lots of ubuntu ones
565 * Note: when limiting vram it's safe to overwritte real_vram_size because
566 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
567 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
570 * Note: IGP TOM addr should be the same as the aperture addr, we don't
571 * explicitly check for that thought.
573 * FIXME: when reducing VRAM size align new size on power of 2.
575 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base)
577 uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
579 mc->vram_start = base;
580 if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) {
581 dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n");
582 mc->real_vram_size = mc->aper_size;
583 mc->mc_vram_size = mc->aper_size;
585 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
586 if (limit && limit < mc->real_vram_size)
587 mc->real_vram_size = limit;
588 dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
589 mc->mc_vram_size >> 20, mc->vram_start,
590 mc->vram_end, mc->real_vram_size >> 20);
594 * amdgpu_gtt_location - try to find GTT location
595 * @adev: amdgpu device structure holding all necessary informations
596 * @mc: memory controller structure holding memory informations
598 * Function will place try to place GTT before or after VRAM.
600 * If GTT size is bigger than space left then we ajust GTT size.
601 * Thus function will never fails.
603 * FIXME: when reducing GTT size align new size on power of 2.
605 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc)
607 u64 size_af, size_bf;
609 size_af = ((adev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
610 size_bf = mc->vram_start & ~mc->gtt_base_align;
611 if (size_bf > size_af) {
612 if (mc->gtt_size > size_bf) {
613 dev_warn(adev->dev, "limiting GTT\n");
614 mc->gtt_size = size_bf;
616 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
618 if (mc->gtt_size > size_af) {
619 dev_warn(adev->dev, "limiting GTT\n");
620 mc->gtt_size = size_af;
622 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
624 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
625 dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
626 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
630 * GPU helpers function.
633 * amdgpu_card_posted - check if the hw has already been initialized
635 * @adev: amdgpu_device pointer
637 * Check if the asic has been initialized (all asics).
638 * Used at driver startup.
639 * Returns true if initialized or false if not.
641 bool amdgpu_card_posted(struct amdgpu_device *adev)
645 /* then check MEM_SIZE, in case the crtcs are off */
646 reg = RREG32(mmCONFIG_MEMSIZE);
655 static bool amdgpu_vpost_needed(struct amdgpu_device *adev)
657 if (amdgpu_sriov_vf(adev))
660 if (amdgpu_passthrough(adev)) {
661 /* for FIJI: In whole GPU pass-through virtualization case
662 * old smc fw won't clear some registers (e.g. MEM_SIZE, BIOS_SCRATCH)
663 * so amdgpu_card_posted return false and driver will incorrectly skip vPost.
664 * but if we force vPost do in pass-through case, the driver reload will hang.
665 * whether doing vPost depends on amdgpu_card_posted if smc version is above
668 if (adev->asic_type == CHIP_FIJI) {
671 err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
672 /* force vPost if error occured */
676 fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
677 if (fw_ver >= 0x00160e00)
678 return !amdgpu_card_posted(adev);
681 /* in bare-metal case, amdgpu_card_posted return false
682 * after system reboot/boot, and return true if driver
684 * we shouldn't do vPost after driver reload otherwise GPU
687 if (amdgpu_card_posted(adev))
691 /* we assume vPost is neede for all other cases */
696 * amdgpu_dummy_page_init - init dummy page used by the driver
698 * @adev: amdgpu_device pointer
700 * Allocate the dummy page used by the driver (all asics).
701 * This dummy page is used by the driver as a filler for gart entries
702 * when pages are taken out of the GART
703 * Returns 0 on sucess, -ENOMEM on failure.
705 int amdgpu_dummy_page_init(struct amdgpu_device *adev)
707 if (adev->dummy_page.page)
709 adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
710 if (adev->dummy_page.page == NULL)
712 adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page,
713 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
714 if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) {
715 dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
716 __free_page(adev->dummy_page.page);
717 adev->dummy_page.page = NULL;
724 * amdgpu_dummy_page_fini - free dummy page used by the driver
726 * @adev: amdgpu_device pointer
728 * Frees the dummy page used by the driver (all asics).
730 void amdgpu_dummy_page_fini(struct amdgpu_device *adev)
732 if (adev->dummy_page.page == NULL)
734 pci_unmap_page(adev->pdev, adev->dummy_page.addr,
735 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
736 __free_page(adev->dummy_page.page);
737 adev->dummy_page.page = NULL;
741 /* ATOM accessor methods */
743 * ATOM is an interpreted byte code stored in tables in the vbios. The
744 * driver registers callbacks to access registers and the interpreter
745 * in the driver parses the tables and executes then to program specific
746 * actions (set display modes, asic init, etc.). See amdgpu_atombios.c,
747 * atombios.h, and atom.c
751 * cail_pll_read - read PLL register
753 * @info: atom card_info pointer
754 * @reg: PLL register offset
756 * Provides a PLL register accessor for the atom interpreter (r4xx+).
757 * Returns the value of the PLL register.
759 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
765 * cail_pll_write - write PLL register
767 * @info: atom card_info pointer
768 * @reg: PLL register offset
769 * @val: value to write to the pll register
771 * Provides a PLL register accessor for the atom interpreter (r4xx+).
773 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
779 * cail_mc_read - read MC (Memory Controller) register
781 * @info: atom card_info pointer
782 * @reg: MC register offset
784 * Provides an MC register accessor for the atom interpreter (r4xx+).
785 * Returns the value of the MC register.
787 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
793 * cail_mc_write - write MC (Memory Controller) register
795 * @info: atom card_info pointer
796 * @reg: MC register offset
797 * @val: value to write to the pll register
799 * Provides a MC register accessor for the atom interpreter (r4xx+).
801 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
807 * cail_reg_write - write MMIO register
809 * @info: atom card_info pointer
810 * @reg: MMIO register offset
811 * @val: value to write to the pll register
813 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
815 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
817 struct amdgpu_device *adev = info->dev->dev_private;
823 * cail_reg_read - read MMIO register
825 * @info: atom card_info pointer
826 * @reg: MMIO register offset
828 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
829 * Returns the value of the MMIO register.
831 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
833 struct amdgpu_device *adev = info->dev->dev_private;
841 * cail_ioreg_write - write IO register
843 * @info: atom card_info pointer
844 * @reg: IO register offset
845 * @val: value to write to the pll register
847 * Provides a IO register accessor for the atom interpreter (r4xx+).
849 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
851 struct amdgpu_device *adev = info->dev->dev_private;
857 * cail_ioreg_read - read IO register
859 * @info: atom card_info pointer
860 * @reg: IO register offset
862 * Provides an IO register accessor for the atom interpreter (r4xx+).
863 * Returns the value of the IO register.
865 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
867 struct amdgpu_device *adev = info->dev->dev_private;
875 * amdgpu_atombios_fini - free the driver info and callbacks for atombios
877 * @adev: amdgpu_device pointer
879 * Frees the driver info and register access callbacks for the ATOM
880 * interpreter (r4xx+).
881 * Called at driver shutdown.
883 static void amdgpu_atombios_fini(struct amdgpu_device *adev)
885 if (adev->mode_info.atom_context) {
886 kfree(adev->mode_info.atom_context->scratch);
887 kfree(adev->mode_info.atom_context->iio);
889 kfree(adev->mode_info.atom_context);
890 adev->mode_info.atom_context = NULL;
891 kfree(adev->mode_info.atom_card_info);
892 adev->mode_info.atom_card_info = NULL;
896 * amdgpu_atombios_init - init the driver info and callbacks for atombios
898 * @adev: amdgpu_device pointer
900 * Initializes the driver info and register access callbacks for the
901 * ATOM interpreter (r4xx+).
902 * Returns 0 on sucess, -ENOMEM on failure.
903 * Called at driver startup.
905 static int amdgpu_atombios_init(struct amdgpu_device *adev)
907 struct card_info *atom_card_info =
908 kzalloc(sizeof(struct card_info), GFP_KERNEL);
913 adev->mode_info.atom_card_info = atom_card_info;
914 atom_card_info->dev = adev->ddev;
915 atom_card_info->reg_read = cail_reg_read;
916 atom_card_info->reg_write = cail_reg_write;
917 /* needed for iio ops */
919 atom_card_info->ioreg_read = cail_ioreg_read;
920 atom_card_info->ioreg_write = cail_ioreg_write;
922 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
923 atom_card_info->ioreg_read = cail_reg_read;
924 atom_card_info->ioreg_write = cail_reg_write;
926 atom_card_info->mc_read = cail_mc_read;
927 atom_card_info->mc_write = cail_mc_write;
928 atom_card_info->pll_read = cail_pll_read;
929 atom_card_info->pll_write = cail_pll_write;
931 adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios);
932 if (!adev->mode_info.atom_context) {
933 amdgpu_atombios_fini(adev);
937 mutex_init(&adev->mode_info.atom_context->mutex);
938 amdgpu_atombios_scratch_regs_init(adev);
939 amdgpu_atom_allocate_fb_scratch(adev->mode_info.atom_context);
943 /* if we get transitioned to only one device, take VGA back */
945 * amdgpu_vga_set_decode - enable/disable vga decode
947 * @cookie: amdgpu_device pointer
948 * @state: enable/disable vga decode
950 * Enable/disable vga decode (all asics).
951 * Returns VGA resource flags.
953 static unsigned int amdgpu_vga_set_decode(void *cookie, bool state)
955 struct amdgpu_device *adev = cookie;
956 amdgpu_asic_set_vga_state(adev, state);
958 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
959 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
961 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
965 * amdgpu_check_pot_argument - check that argument is a power of two
967 * @arg: value to check
969 * Validates that a certain argument is a power of two (all asics).
970 * Returns true if argument is valid.
972 static bool amdgpu_check_pot_argument(int arg)
974 return (arg & (arg - 1)) == 0;
978 * amdgpu_check_arguments - validate module params
980 * @adev: amdgpu_device pointer
982 * Validates certain module parameters and updates
983 * the associated values used by the driver (all asics).
985 static void amdgpu_check_arguments(struct amdgpu_device *adev)
987 if (amdgpu_sched_jobs < 4) {
988 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
990 amdgpu_sched_jobs = 4;
991 } else if (!amdgpu_check_pot_argument(amdgpu_sched_jobs)){
992 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
994 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
997 if (amdgpu_gart_size != -1) {
998 /* gtt size must be greater or equal to 32M */
999 if (amdgpu_gart_size < 32) {
1000 dev_warn(adev->dev, "gart size (%d) too small\n",
1002 amdgpu_gart_size = -1;
1006 if (!amdgpu_check_pot_argument(amdgpu_vm_size)) {
1007 dev_warn(adev->dev, "VM size (%d) must be a power of 2\n",
1012 if (amdgpu_vm_size < 1) {
1013 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
1019 * Max GPUVM size for Cayman, SI and CI are 40 bits.
1021 if (amdgpu_vm_size > 1024) {
1022 dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n",
1027 /* defines number of bits in page table versus page directory,
1028 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1029 * page table and the remaining bits are in the page directory */
1030 if (amdgpu_vm_block_size == -1) {
1032 /* Total bits covered by PD + PTs */
1033 unsigned bits = ilog2(amdgpu_vm_size) + 18;
1035 /* Make sure the PD is 4K in size up to 8GB address space.
1036 Above that split equal between PD and PTs */
1037 if (amdgpu_vm_size <= 8)
1038 amdgpu_vm_block_size = bits - 9;
1040 amdgpu_vm_block_size = (bits + 3) / 2;
1042 } else if (amdgpu_vm_block_size < 9) {
1043 dev_warn(adev->dev, "VM page table size (%d) too small\n",
1044 amdgpu_vm_block_size);
1045 amdgpu_vm_block_size = 9;
1048 if (amdgpu_vm_block_size > 24 ||
1049 (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) {
1050 dev_warn(adev->dev, "VM page table size (%d) too large\n",
1051 amdgpu_vm_block_size);
1052 amdgpu_vm_block_size = 9;
1057 * amdgpu_switcheroo_set_state - set switcheroo state
1059 * @pdev: pci dev pointer
1060 * @state: vga_switcheroo state
1062 * Callback for the switcheroo driver. Suspends or resumes the
1063 * the asics before or after it is powered up using ACPI methods.
1065 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1067 struct drm_device *dev = pci_get_drvdata(pdev);
1069 if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1072 if (state == VGA_SWITCHEROO_ON) {
1073 unsigned d3_delay = dev->pdev->d3_delay;
1075 printk(KERN_INFO "amdgpu: switched on\n");
1076 /* don't suspend or resume card normally */
1077 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1079 amdgpu_device_resume(dev, true, true);
1081 dev->pdev->d3_delay = d3_delay;
1083 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1084 drm_kms_helper_poll_enable(dev);
1086 printk(KERN_INFO "amdgpu: switched off\n");
1087 drm_kms_helper_poll_disable(dev);
1088 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1089 amdgpu_device_suspend(dev, true, true);
1090 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1095 * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1097 * @pdev: pci dev pointer
1099 * Callback for the switcheroo driver. Check of the switcheroo
1100 * state can be changed.
1101 * Returns true if the state can be changed, false if not.
1103 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1105 struct drm_device *dev = pci_get_drvdata(pdev);
1108 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1109 * locking inversion with the driver load path. And the access here is
1110 * completely racy anyway. So don't bother with locking for now.
1112 return dev->open_count == 0;
1115 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1116 .set_gpu_state = amdgpu_switcheroo_set_state,
1118 .can_switch = amdgpu_switcheroo_can_switch,
1121 int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
1122 enum amd_ip_block_type block_type,
1123 enum amd_clockgating_state state)
1127 for (i = 0; i < adev->num_ip_blocks; i++) {
1128 if (!adev->ip_block_status[i].valid)
1130 if (adev->ip_blocks[i].type == block_type) {
1131 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1141 int amdgpu_set_powergating_state(struct amdgpu_device *adev,
1142 enum amd_ip_block_type block_type,
1143 enum amd_powergating_state state)
1147 for (i = 0; i < adev->num_ip_blocks; i++) {
1148 if (!adev->ip_block_status[i].valid)
1150 if (adev->ip_blocks[i].type == block_type) {
1151 r = adev->ip_blocks[i].funcs->set_powergating_state((void *)adev,
1161 int amdgpu_wait_for_idle(struct amdgpu_device *adev,
1162 enum amd_ip_block_type block_type)
1166 for (i = 0; i < adev->num_ip_blocks; i++) {
1167 if (!adev->ip_block_status[i].valid)
1169 if (adev->ip_blocks[i].type == block_type) {
1170 r = adev->ip_blocks[i].funcs->wait_for_idle((void *)adev);
1180 bool amdgpu_is_idle(struct amdgpu_device *adev,
1181 enum amd_ip_block_type block_type)
1185 for (i = 0; i < adev->num_ip_blocks; i++) {
1186 if (!adev->ip_block_status[i].valid)
1188 if (adev->ip_blocks[i].type == block_type)
1189 return adev->ip_blocks[i].funcs->is_idle((void *)adev);
1195 const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
1196 struct amdgpu_device *adev,
1197 enum amd_ip_block_type type)
1201 for (i = 0; i < adev->num_ip_blocks; i++)
1202 if (adev->ip_blocks[i].type == type)
1203 return &adev->ip_blocks[i];
1209 * amdgpu_ip_block_version_cmp
1211 * @adev: amdgpu_device pointer
1212 * @type: enum amd_ip_block_type
1213 * @major: major version
1214 * @minor: minor version
1216 * return 0 if equal or greater
1217 * return 1 if smaller or the ip_block doesn't exist
1219 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
1220 enum amd_ip_block_type type,
1221 u32 major, u32 minor)
1223 const struct amdgpu_ip_block_version *ip_block;
1224 ip_block = amdgpu_get_ip_block(adev, type);
1226 if (ip_block && ((ip_block->major > major) ||
1227 ((ip_block->major == major) &&
1228 (ip_block->minor >= minor))))
1234 static void amdgpu_whether_enable_virtual_display(struct amdgpu_device *adev)
1236 adev->enable_virtual_display = false;
1238 if (amdgpu_virtual_display) {
1239 struct drm_device *ddev = adev->ddev;
1240 const char *pci_address_name = pci_name(ddev->pdev);
1241 char *pciaddstr, *pciaddstr_tmp, *pciaddname;
1243 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
1244 pciaddstr_tmp = pciaddstr;
1245 while ((pciaddname = strsep(&pciaddstr_tmp, ";"))) {
1246 if (!strcmp(pci_address_name, pciaddname)) {
1247 adev->enable_virtual_display = true;
1252 DRM_INFO("virtual display string:%s, %s:virtual_display:%d\n",
1253 amdgpu_virtual_display, pci_address_name,
1254 adev->enable_virtual_display);
1260 static int amdgpu_early_init(struct amdgpu_device *adev)
1264 amdgpu_whether_enable_virtual_display(adev);
1266 switch (adev->asic_type) {
1270 case CHIP_POLARIS11:
1271 case CHIP_POLARIS10:
1274 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
1275 adev->family = AMDGPU_FAMILY_CZ;
1277 adev->family = AMDGPU_FAMILY_VI;
1279 r = vi_set_ip_blocks(adev);
1283 #ifdef CONFIG_DRM_AMDGPU_SI
1289 adev->family = AMDGPU_FAMILY_SI;
1290 r = si_set_ip_blocks(adev);
1295 #ifdef CONFIG_DRM_AMDGPU_CIK
1301 if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
1302 adev->family = AMDGPU_FAMILY_CI;
1304 adev->family = AMDGPU_FAMILY_KV;
1306 r = cik_set_ip_blocks(adev);
1312 /* FIXME: not supported yet */
1316 adev->ip_block_status = kcalloc(adev->num_ip_blocks,
1317 sizeof(struct amdgpu_ip_block_status), GFP_KERNEL);
1318 if (adev->ip_block_status == NULL)
1321 if (adev->ip_blocks == NULL) {
1322 DRM_ERROR("No IP blocks found!\n");
1326 for (i = 0; i < adev->num_ip_blocks; i++) {
1327 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1328 DRM_ERROR("disabled ip block: %d\n", i);
1329 adev->ip_block_status[i].valid = false;
1331 if (adev->ip_blocks[i].funcs->early_init) {
1332 r = adev->ip_blocks[i].funcs->early_init((void *)adev);
1334 adev->ip_block_status[i].valid = false;
1336 DRM_ERROR("early_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1339 adev->ip_block_status[i].valid = true;
1342 adev->ip_block_status[i].valid = true;
1347 adev->cg_flags &= amdgpu_cg_mask;
1348 adev->pg_flags &= amdgpu_pg_mask;
1353 static int amdgpu_init(struct amdgpu_device *adev)
1357 for (i = 0; i < adev->num_ip_blocks; i++) {
1358 if (!adev->ip_block_status[i].valid)
1360 r = adev->ip_blocks[i].funcs->sw_init((void *)adev);
1362 DRM_ERROR("sw_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1365 adev->ip_block_status[i].sw = true;
1366 /* need to do gmc hw init early so we can allocate gpu mem */
1367 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
1368 r = amdgpu_vram_scratch_init(adev);
1370 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
1373 r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
1375 DRM_ERROR("hw_init %d failed %d\n", i, r);
1378 r = amdgpu_wb_init(adev);
1380 DRM_ERROR("amdgpu_wb_init failed %d\n", r);
1383 adev->ip_block_status[i].hw = true;
1387 for (i = 0; i < adev->num_ip_blocks; i++) {
1388 if (!adev->ip_block_status[i].sw)
1390 /* gmc hw init is done early */
1391 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC)
1393 r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
1395 DRM_ERROR("hw_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1398 adev->ip_block_status[i].hw = true;
1404 static int amdgpu_late_init(struct amdgpu_device *adev)
1408 for (i = 0; i < adev->num_ip_blocks; i++) {
1409 if (!adev->ip_block_status[i].valid)
1411 if (adev->ip_blocks[i].funcs->late_init) {
1412 r = adev->ip_blocks[i].funcs->late_init((void *)adev);
1414 DRM_ERROR("late_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1417 adev->ip_block_status[i].late_initialized = true;
1419 /* skip CG for VCE/UVD, it's handled specially */
1420 if (adev->ip_blocks[i].type != AMD_IP_BLOCK_TYPE_UVD &&
1421 adev->ip_blocks[i].type != AMD_IP_BLOCK_TYPE_VCE) {
1422 /* enable clockgating to save power */
1423 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1426 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
1427 adev->ip_blocks[i].funcs->name, r);
1436 static int amdgpu_fini(struct amdgpu_device *adev)
1440 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1441 if (!adev->ip_block_status[i].hw)
1443 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
1444 amdgpu_wb_fini(adev);
1445 amdgpu_vram_scratch_fini(adev);
1447 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1448 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1449 AMD_CG_STATE_UNGATE);
1451 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1454 r = adev->ip_blocks[i].funcs->hw_fini((void *)adev);
1455 /* XXX handle errors */
1457 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1459 adev->ip_block_status[i].hw = false;
1462 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1463 if (!adev->ip_block_status[i].sw)
1465 r = adev->ip_blocks[i].funcs->sw_fini((void *)adev);
1466 /* XXX handle errors */
1468 DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1470 adev->ip_block_status[i].sw = false;
1471 adev->ip_block_status[i].valid = false;
1474 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1475 if (!adev->ip_block_status[i].late_initialized)
1477 if (adev->ip_blocks[i].funcs->late_fini)
1478 adev->ip_blocks[i].funcs->late_fini((void *)adev);
1479 adev->ip_block_status[i].late_initialized = false;
1485 static int amdgpu_suspend(struct amdgpu_device *adev)
1489 /* ungate SMC block first */
1490 r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC,
1491 AMD_CG_STATE_UNGATE);
1493 DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r);
1496 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1497 if (!adev->ip_block_status[i].valid)
1499 /* ungate blocks so that suspend can properly shut them down */
1500 if (i != AMD_IP_BLOCK_TYPE_SMC) {
1501 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1502 AMD_CG_STATE_UNGATE);
1504 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1507 /* XXX handle errors */
1508 r = adev->ip_blocks[i].funcs->suspend(adev);
1509 /* XXX handle errors */
1511 DRM_ERROR("suspend of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1518 static int amdgpu_resume(struct amdgpu_device *adev)
1522 for (i = 0; i < adev->num_ip_blocks; i++) {
1523 if (!adev->ip_block_status[i].valid)
1525 r = adev->ip_blocks[i].funcs->resume(adev);
1527 DRM_ERROR("resume of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
1535 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
1537 if (amdgpu_atombios_has_gpu_virtualization_table(adev))
1538 adev->virtualization.virtual_caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
1542 * amdgpu_device_init - initialize the driver
1544 * @adev: amdgpu_device pointer
1545 * @pdev: drm dev pointer
1546 * @pdev: pci dev pointer
1547 * @flags: driver flags
1549 * Initializes the driver info and hw (all asics).
1550 * Returns 0 for success or an error on failure.
1551 * Called at driver startup.
1553 int amdgpu_device_init(struct amdgpu_device *adev,
1554 struct drm_device *ddev,
1555 struct pci_dev *pdev,
1559 bool runtime = false;
1562 adev->shutdown = false;
1563 adev->dev = &pdev->dev;
1566 adev->flags = flags;
1567 adev->asic_type = flags & AMD_ASIC_MASK;
1568 adev->is_atom_bios = false;
1569 adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
1570 adev->mc.gtt_size = 512 * 1024 * 1024;
1571 adev->accel_working = false;
1572 adev->num_rings = 0;
1573 adev->mman.buffer_funcs = NULL;
1574 adev->mman.buffer_funcs_ring = NULL;
1575 adev->vm_manager.vm_pte_funcs = NULL;
1576 adev->vm_manager.vm_pte_num_rings = 0;
1577 adev->gart.gart_funcs = NULL;
1578 adev->fence_context = fence_context_alloc(AMDGPU_MAX_RINGS);
1580 adev->smc_rreg = &amdgpu_invalid_rreg;
1581 adev->smc_wreg = &amdgpu_invalid_wreg;
1582 adev->pcie_rreg = &amdgpu_invalid_rreg;
1583 adev->pcie_wreg = &amdgpu_invalid_wreg;
1584 adev->pciep_rreg = &amdgpu_invalid_rreg;
1585 adev->pciep_wreg = &amdgpu_invalid_wreg;
1586 adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
1587 adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
1588 adev->didt_rreg = &amdgpu_invalid_rreg;
1589 adev->didt_wreg = &amdgpu_invalid_wreg;
1590 adev->gc_cac_rreg = &amdgpu_invalid_rreg;
1591 adev->gc_cac_wreg = &amdgpu_invalid_wreg;
1592 adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
1593 adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
1596 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
1597 amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
1598 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
1600 /* mutex initialization are all done here so we
1601 * can recall function without having locking issues */
1602 mutex_init(&adev->vm_manager.lock);
1603 atomic_set(&adev->irq.ih.lock, 0);
1604 mutex_init(&adev->pm.mutex);
1605 mutex_init(&adev->gfx.gpu_clock_mutex);
1606 mutex_init(&adev->srbm_mutex);
1607 mutex_init(&adev->grbm_idx_mutex);
1608 mutex_init(&adev->mn_lock);
1609 hash_init(adev->mn_hash);
1611 amdgpu_check_arguments(adev);
1613 /* Registers mapping */
1614 /* TODO: block userspace mapping of io register */
1615 spin_lock_init(&adev->mmio_idx_lock);
1616 spin_lock_init(&adev->smc_idx_lock);
1617 spin_lock_init(&adev->pcie_idx_lock);
1618 spin_lock_init(&adev->uvd_ctx_idx_lock);
1619 spin_lock_init(&adev->didt_idx_lock);
1620 spin_lock_init(&adev->gc_cac_idx_lock);
1621 spin_lock_init(&adev->audio_endpt_idx_lock);
1622 spin_lock_init(&adev->mm_stats.lock);
1624 INIT_LIST_HEAD(&adev->shadow_list);
1625 mutex_init(&adev->shadow_list_lock);
1627 INIT_LIST_HEAD(&adev->gtt_list);
1628 spin_lock_init(&adev->gtt_list_lock);
1630 if (adev->asic_type >= CHIP_BONAIRE) {
1631 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
1632 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
1634 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
1635 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
1638 adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
1639 if (adev->rmmio == NULL) {
1642 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
1643 DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
1645 if (adev->asic_type >= CHIP_BONAIRE)
1646 /* doorbell bar mapping */
1647 amdgpu_doorbell_init(adev);
1649 /* io port mapping */
1650 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1651 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
1652 adev->rio_mem_size = pci_resource_len(adev->pdev, i);
1653 adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
1657 if (adev->rio_mem == NULL)
1658 DRM_ERROR("Unable to find PCI I/O BAR\n");
1660 /* early init functions */
1661 r = amdgpu_early_init(adev);
1665 /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
1666 /* this will fail for cards that aren't VGA class devices, just
1668 vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode);
1670 if (amdgpu_runtime_pm == 1)
1672 if (amdgpu_device_is_px(ddev))
1674 vga_switcheroo_register_client(adev->pdev, &amdgpu_switcheroo_ops, runtime);
1676 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
1679 if (!amdgpu_get_bios(adev)) {
1683 /* Must be an ATOMBIOS */
1684 if (!adev->is_atom_bios) {
1685 dev_err(adev->dev, "Expecting atombios for GPU\n");
1689 r = amdgpu_atombios_init(adev);
1691 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
1695 /* detect if we are with an SRIOV vbios */
1696 amdgpu_device_detect_sriov_bios(adev);
1698 /* Post card if necessary */
1699 if (amdgpu_vpost_needed(adev)) {
1701 dev_err(adev->dev, "no vBIOS found\n");
1705 DRM_INFO("GPU posting now...\n");
1706 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
1708 dev_err(adev->dev, "gpu post error!\n");
1712 DRM_INFO("GPU post is not needed\n");
1715 /* Initialize clocks */
1716 r = amdgpu_atombios_get_clock_info(adev);
1718 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
1721 /* init i2c buses */
1722 amdgpu_atombios_i2c_init(adev);
1725 r = amdgpu_fence_driver_init(adev);
1727 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
1731 /* init the mode config */
1732 drm_mode_config_init(adev->ddev);
1734 r = amdgpu_init(adev);
1736 dev_err(adev->dev, "amdgpu_init failed\n");
1741 adev->accel_working = true;
1743 /* Initialize the buffer migration limit. */
1744 if (amdgpu_moverate >= 0)
1745 max_MBps = amdgpu_moverate;
1747 max_MBps = 8; /* Allow 8 MB/s. */
1748 /* Get a log2 for easy divisions. */
1749 adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
1751 amdgpu_fbdev_init(adev);
1753 r = amdgpu_ib_pool_init(adev);
1755 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
1759 r = amdgpu_ib_ring_tests(adev);
1761 DRM_ERROR("ib ring test failed (%d).\n", r);
1763 r = amdgpu_gem_debugfs_init(adev);
1765 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
1768 r = amdgpu_debugfs_regs_init(adev);
1770 DRM_ERROR("registering register debugfs failed (%d).\n", r);
1773 r = amdgpu_debugfs_firmware_init(adev);
1775 DRM_ERROR("registering firmware debugfs failed (%d).\n", r);
1779 if ((amdgpu_testing & 1)) {
1780 if (adev->accel_working)
1781 amdgpu_test_moves(adev);
1783 DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
1785 if ((amdgpu_testing & 2)) {
1786 if (adev->accel_working)
1787 amdgpu_test_syncing(adev);
1789 DRM_INFO("amdgpu: acceleration disabled, skipping sync tests\n");
1791 if (amdgpu_benchmarking) {
1792 if (adev->accel_working)
1793 amdgpu_benchmark(adev, amdgpu_benchmarking);
1795 DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
1798 /* enable clockgating, etc. after ib tests, etc. since some blocks require
1799 * explicit gating rather than handling it automatically.
1801 r = amdgpu_late_init(adev);
1803 dev_err(adev->dev, "amdgpu_late_init failed\n");
1811 vga_switcheroo_fini_domain_pm_ops(adev->dev);
1815 static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev);
1818 * amdgpu_device_fini - tear down the driver
1820 * @adev: amdgpu_device pointer
1822 * Tear down the driver info (all asics).
1823 * Called at driver shutdown.
1825 void amdgpu_device_fini(struct amdgpu_device *adev)
1829 DRM_INFO("amdgpu: finishing device.\n");
1830 adev->shutdown = true;
1831 /* evict vram memory */
1832 amdgpu_bo_evict_vram(adev);
1833 amdgpu_ib_pool_fini(adev);
1834 amdgpu_fence_driver_fini(adev);
1835 drm_crtc_force_disable_all(adev->ddev);
1836 amdgpu_fbdev_fini(adev);
1837 r = amdgpu_fini(adev);
1838 kfree(adev->ip_block_status);
1839 adev->ip_block_status = NULL;
1840 adev->accel_working = false;
1841 /* free i2c buses */
1842 amdgpu_i2c_fini(adev);
1843 amdgpu_atombios_fini(adev);
1846 vga_switcheroo_unregister_client(adev->pdev);
1847 if (adev->flags & AMD_IS_PX)
1848 vga_switcheroo_fini_domain_pm_ops(adev->dev);
1849 vga_client_register(adev->pdev, NULL, NULL, NULL);
1851 pci_iounmap(adev->pdev, adev->rio_mem);
1852 adev->rio_mem = NULL;
1853 iounmap(adev->rmmio);
1855 if (adev->asic_type >= CHIP_BONAIRE)
1856 amdgpu_doorbell_fini(adev);
1857 amdgpu_debugfs_regs_cleanup(adev);
1858 amdgpu_debugfs_remove_files(adev);
1866 * amdgpu_device_suspend - initiate device suspend
1868 * @pdev: drm dev pointer
1869 * @state: suspend state
1871 * Puts the hw in the suspend state (all asics).
1872 * Returns 0 for success or an error on failure.
1873 * Called at driver suspend.
1875 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
1877 struct amdgpu_device *adev;
1878 struct drm_crtc *crtc;
1879 struct drm_connector *connector;
1882 if (dev == NULL || dev->dev_private == NULL) {
1886 adev = dev->dev_private;
1888 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1891 drm_kms_helper_poll_disable(dev);
1893 /* turn off display hw */
1894 drm_modeset_lock_all(dev);
1895 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1896 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
1898 drm_modeset_unlock_all(dev);
1900 /* unpin the front buffers and cursors */
1901 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1902 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1903 struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb);
1904 struct amdgpu_bo *robj;
1906 if (amdgpu_crtc->cursor_bo) {
1907 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1908 r = amdgpu_bo_reserve(aobj, false);
1910 amdgpu_bo_unpin(aobj);
1911 amdgpu_bo_unreserve(aobj);
1915 if (rfb == NULL || rfb->obj == NULL) {
1918 robj = gem_to_amdgpu_bo(rfb->obj);
1919 /* don't unpin kernel fb objects */
1920 if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
1921 r = amdgpu_bo_reserve(robj, false);
1923 amdgpu_bo_unpin(robj);
1924 amdgpu_bo_unreserve(robj);
1928 /* evict vram memory */
1929 amdgpu_bo_evict_vram(adev);
1931 amdgpu_fence_driver_suspend(adev);
1933 r = amdgpu_suspend(adev);
1935 /* evict remaining vram memory */
1936 amdgpu_bo_evict_vram(adev);
1938 pci_save_state(dev->pdev);
1940 /* Shut down the device */
1941 pci_disable_device(dev->pdev);
1942 pci_set_power_state(dev->pdev, PCI_D3hot);
1944 r = amdgpu_asic_reset(adev);
1946 DRM_ERROR("amdgpu asic reset failed\n");
1951 amdgpu_fbdev_set_suspend(adev, 1);
1958 * amdgpu_device_resume - initiate device resume
1960 * @pdev: drm dev pointer
1962 * Bring the hw back to operating state (all asics).
1963 * Returns 0 for success or an error on failure.
1964 * Called at driver resume.
1966 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
1968 struct drm_connector *connector;
1969 struct amdgpu_device *adev = dev->dev_private;
1970 struct drm_crtc *crtc;
1973 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1980 pci_set_power_state(dev->pdev, PCI_D0);
1981 pci_restore_state(dev->pdev);
1982 r = pci_enable_device(dev->pdev);
1991 if (!amdgpu_card_posted(adev) || !resume) {
1992 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
1994 DRM_ERROR("amdgpu asic init failed\n");
1997 r = amdgpu_resume(adev);
1999 DRM_ERROR("amdgpu_resume failed (%d).\n", r);
2001 amdgpu_fence_driver_resume(adev);
2004 r = amdgpu_ib_ring_tests(adev);
2006 DRM_ERROR("ib ring test failed (%d).\n", r);
2009 r = amdgpu_late_init(adev);
2014 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2015 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2017 if (amdgpu_crtc->cursor_bo) {
2018 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2019 r = amdgpu_bo_reserve(aobj, false);
2021 r = amdgpu_bo_pin(aobj,
2022 AMDGPU_GEM_DOMAIN_VRAM,
2023 &amdgpu_crtc->cursor_addr);
2025 DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
2026 amdgpu_bo_unreserve(aobj);
2031 /* blat the mode back in */
2033 drm_helper_resume_force_mode(dev);
2034 /* turn on display hw */
2035 drm_modeset_lock_all(dev);
2036 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2037 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
2039 drm_modeset_unlock_all(dev);
2042 drm_kms_helper_poll_enable(dev);
2045 * Most of the connector probing functions try to acquire runtime pm
2046 * refs to ensure that the GPU is powered on when connector polling is
2047 * performed. Since we're calling this from a runtime PM callback,
2048 * trying to acquire rpm refs will cause us to deadlock.
2050 * Since we're guaranteed to be holding the rpm lock, it's safe to
2051 * temporarily disable the rpm helpers so this doesn't deadlock us.
2054 dev->dev->power.disable_depth++;
2056 drm_helper_hpd_irq_event(dev);
2058 dev->dev->power.disable_depth--;
2062 amdgpu_fbdev_set_suspend(adev, 0);
2069 static bool amdgpu_check_soft_reset(struct amdgpu_device *adev)
2072 bool asic_hang = false;
2074 for (i = 0; i < adev->num_ip_blocks; i++) {
2075 if (!adev->ip_block_status[i].valid)
2077 if (adev->ip_blocks[i].funcs->check_soft_reset)
2078 adev->ip_block_status[i].hang =
2079 adev->ip_blocks[i].funcs->check_soft_reset(adev);
2080 if (adev->ip_block_status[i].hang) {
2081 DRM_INFO("IP block:%d is hang!\n", i);
2088 static int amdgpu_pre_soft_reset(struct amdgpu_device *adev)
2092 for (i = 0; i < adev->num_ip_blocks; i++) {
2093 if (!adev->ip_block_status[i].valid)
2095 if (adev->ip_block_status[i].hang &&
2096 adev->ip_blocks[i].funcs->pre_soft_reset) {
2097 r = adev->ip_blocks[i].funcs->pre_soft_reset(adev);
2106 static bool amdgpu_need_full_reset(struct amdgpu_device *adev)
2110 for (i = 0; i < adev->num_ip_blocks; i++) {
2111 if (!adev->ip_block_status[i].valid)
2113 if ((adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) ||
2114 (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_SMC) ||
2115 (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_ACP) ||
2116 (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_DCE)) {
2117 if (adev->ip_block_status[i].hang) {
2118 DRM_INFO("Some block need full reset!\n");
2126 static int amdgpu_soft_reset(struct amdgpu_device *adev)
2130 for (i = 0; i < adev->num_ip_blocks; i++) {
2131 if (!adev->ip_block_status[i].valid)
2133 if (adev->ip_block_status[i].hang &&
2134 adev->ip_blocks[i].funcs->soft_reset) {
2135 r = adev->ip_blocks[i].funcs->soft_reset(adev);
2144 static int amdgpu_post_soft_reset(struct amdgpu_device *adev)
2148 for (i = 0; i < adev->num_ip_blocks; i++) {
2149 if (!adev->ip_block_status[i].valid)
2151 if (adev->ip_block_status[i].hang &&
2152 adev->ip_blocks[i].funcs->post_soft_reset)
2153 r = adev->ip_blocks[i].funcs->post_soft_reset(adev);
2161 bool amdgpu_need_backup(struct amdgpu_device *adev)
2163 if (adev->flags & AMD_IS_APU)
2166 return amdgpu_lockup_timeout > 0 ? true : false;
2169 static int amdgpu_recover_vram_from_shadow(struct amdgpu_device *adev,
2170 struct amdgpu_ring *ring,
2171 struct amdgpu_bo *bo,
2172 struct fence **fence)
2180 r = amdgpu_bo_reserve(bo, false);
2183 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
2184 /* if bo has been evicted, then no need to recover */
2185 if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
2186 r = amdgpu_bo_restore_from_shadow(adev, ring, bo,
2189 DRM_ERROR("recover page table failed!\n");
2194 amdgpu_bo_unreserve(bo);
2199 * amdgpu_gpu_reset - reset the asic
2201 * @adev: amdgpu device pointer
2203 * Attempt the reset the GPU if it has hung (all asics).
2204 * Returns 0 for success or an error on failure.
2206 int amdgpu_gpu_reset(struct amdgpu_device *adev)
2210 bool need_full_reset;
2212 if (!amdgpu_check_soft_reset(adev)) {
2213 DRM_INFO("No hardware hang detected. Did some blocks stall?\n");
2217 atomic_inc(&adev->gpu_reset_counter);
2220 resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
2222 /* block scheduler */
2223 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2224 struct amdgpu_ring *ring = adev->rings[i];
2228 kthread_park(ring->sched.thread);
2229 amd_sched_hw_job_reset(&ring->sched);
2231 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
2232 amdgpu_fence_driver_force_completion(adev);
2234 need_full_reset = amdgpu_need_full_reset(adev);
2236 if (!need_full_reset) {
2237 amdgpu_pre_soft_reset(adev);
2238 r = amdgpu_soft_reset(adev);
2239 amdgpu_post_soft_reset(adev);
2240 if (r || amdgpu_check_soft_reset(adev)) {
2241 DRM_INFO("soft reset failed, will fallback to full reset!\n");
2242 need_full_reset = true;
2246 if (need_full_reset) {
2248 amdgpu_atombios_scratch_regs_save(adev);
2249 r = amdgpu_suspend(adev);
2252 /* Disable fb access */
2253 if (adev->mode_info.num_crtc) {
2254 struct amdgpu_mode_mc_save save;
2255 amdgpu_display_stop_mc_access(adev, &save);
2256 amdgpu_wait_for_idle(adev, AMD_IP_BLOCK_TYPE_GMC);
2259 r = amdgpu_asic_reset(adev);
2261 amdgpu_atom_asic_init(adev->mode_info.atom_context);
2264 dev_info(adev->dev, "GPU reset succeeded, trying to resume\n");
2265 r = amdgpu_resume(adev);
2267 /* restore scratch */
2268 amdgpu_atombios_scratch_regs_restore(adev);
2271 amdgpu_irq_gpu_reset_resume_helper(adev);
2272 if (need_full_reset && amdgpu_need_backup(adev)) {
2273 r = amdgpu_ttm_recover_gart(adev);
2275 DRM_ERROR("gart recovery failed!!!\n");
2277 r = amdgpu_ib_ring_tests(adev);
2279 dev_err(adev->dev, "ib ring test failed (%d).\n", r);
2280 r = amdgpu_suspend(adev);
2281 need_full_reset = true;
2285 * recovery vm page tables, since we cannot depend on VRAM is
2286 * consistent after gpu full reset.
2288 if (need_full_reset && amdgpu_need_backup(adev)) {
2289 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2290 struct amdgpu_bo *bo, *tmp;
2291 struct fence *fence = NULL, *next = NULL;
2293 DRM_INFO("recover vram bo from shadow\n");
2294 mutex_lock(&adev->shadow_list_lock);
2295 list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) {
2296 amdgpu_recover_vram_from_shadow(adev, ring, bo, &next);
2298 r = fence_wait(fence, false);
2300 WARN(r, "recovery from shadow isn't comleted\n");
2308 mutex_unlock(&adev->shadow_list_lock);
2310 r = fence_wait(fence, false);
2312 WARN(r, "recovery from shadow isn't comleted\n");
2316 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2317 struct amdgpu_ring *ring = adev->rings[i];
2321 amd_sched_job_recovery(&ring->sched);
2322 kthread_unpark(ring->sched.thread);
2325 dev_err(adev->dev, "asic resume failed (%d).\n", r);
2326 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2327 if (adev->rings[i]) {
2328 kthread_unpark(adev->rings[i]->sched.thread);
2333 drm_helper_resume_force_mode(adev->ddev);
2335 ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
2337 /* bad news, how to tell it to userspace ? */
2338 dev_info(adev->dev, "GPU reset failed\n");
2344 void amdgpu_get_pcie_info(struct amdgpu_device *adev)
2349 if (amdgpu_pcie_gen_cap)
2350 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
2352 if (amdgpu_pcie_lane_cap)
2353 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
2355 /* covers APUs as well */
2356 if (pci_is_root_bus(adev->pdev->bus)) {
2357 if (adev->pm.pcie_gen_mask == 0)
2358 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
2359 if (adev->pm.pcie_mlw_mask == 0)
2360 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
2364 if (adev->pm.pcie_gen_mask == 0) {
2365 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
2367 adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
2368 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
2369 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
2371 if (mask & DRM_PCIE_SPEED_25)
2372 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
2373 if (mask & DRM_PCIE_SPEED_50)
2374 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;
2375 if (mask & DRM_PCIE_SPEED_80)
2376 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;
2378 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
2381 if (adev->pm.pcie_mlw_mask == 0) {
2382 ret = drm_pcie_get_max_link_width(adev->ddev, &mask);
2386 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
2387 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
2388 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2389 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2390 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2391 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2392 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2395 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
2396 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2397 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2398 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2399 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2400 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2403 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2404 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2405 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2406 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2407 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2410 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2411 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2412 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2413 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2416 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2417 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2418 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2421 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2422 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2425 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
2431 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
2439 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
2440 const struct drm_info_list *files,
2445 for (i = 0; i < adev->debugfs_count; i++) {
2446 if (adev->debugfs[i].files == files) {
2447 /* Already registered */
2452 i = adev->debugfs_count + 1;
2453 if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) {
2454 DRM_ERROR("Reached maximum number of debugfs components.\n");
2455 DRM_ERROR("Report so we increase "
2456 "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n");
2459 adev->debugfs[adev->debugfs_count].files = files;
2460 adev->debugfs[adev->debugfs_count].num_files = nfiles;
2461 adev->debugfs_count = i;
2462 #if defined(CONFIG_DEBUG_FS)
2463 drm_debugfs_create_files(files, nfiles,
2464 adev->ddev->control->debugfs_root,
2465 adev->ddev->control);
2466 drm_debugfs_create_files(files, nfiles,
2467 adev->ddev->primary->debugfs_root,
2468 adev->ddev->primary);
2473 static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev)
2475 #if defined(CONFIG_DEBUG_FS)
2478 for (i = 0; i < adev->debugfs_count; i++) {
2479 drm_debugfs_remove_files(adev->debugfs[i].files,
2480 adev->debugfs[i].num_files,
2481 adev->ddev->control);
2482 drm_debugfs_remove_files(adev->debugfs[i].files,
2483 adev->debugfs[i].num_files,
2484 adev->ddev->primary);
2489 #if defined(CONFIG_DEBUG_FS)
2491 static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
2492 size_t size, loff_t *pos)
2494 struct amdgpu_device *adev = f->f_inode->i_private;
2497 bool pm_pg_lock, use_bank;
2498 unsigned instance_bank, sh_bank, se_bank;
2500 if (size & 0x3 || *pos & 0x3)
2503 /* are we reading registers for which a PG lock is necessary? */
2504 pm_pg_lock = (*pos >> 23) & 1;
2506 if (*pos & (1ULL << 62)) {
2507 se_bank = (*pos >> 24) & 0x3FF;
2508 sh_bank = (*pos >> 34) & 0x3FF;
2509 instance_bank = (*pos >> 44) & 0x3FF;
2518 if (sh_bank >= adev->gfx.config.max_sh_per_se ||
2519 se_bank >= adev->gfx.config.max_shader_engines)
2521 mutex_lock(&adev->grbm_idx_mutex);
2522 amdgpu_gfx_select_se_sh(adev, se_bank,
2523 sh_bank, instance_bank);
2527 mutex_lock(&adev->pm.mutex);
2532 if (*pos > adev->rmmio_size)
2535 value = RREG32(*pos >> 2);
2536 r = put_user(value, (uint32_t *)buf);
2550 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2551 mutex_unlock(&adev->grbm_idx_mutex);
2555 mutex_unlock(&adev->pm.mutex);
2560 static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
2561 size_t size, loff_t *pos)
2563 struct amdgpu_device *adev = f->f_inode->i_private;
2567 if (size & 0x3 || *pos & 0x3)
2573 if (*pos > adev->rmmio_size)
2576 r = get_user(value, (uint32_t *)buf);
2580 WREG32(*pos >> 2, value);
2591 static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf,
2592 size_t size, loff_t *pos)
2594 struct amdgpu_device *adev = f->f_inode->i_private;
2598 if (size & 0x3 || *pos & 0x3)
2604 value = RREG32_PCIE(*pos >> 2);
2605 r = put_user(value, (uint32_t *)buf);
2618 static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf,
2619 size_t size, loff_t *pos)
2621 struct amdgpu_device *adev = f->f_inode->i_private;
2625 if (size & 0x3 || *pos & 0x3)
2631 r = get_user(value, (uint32_t *)buf);
2635 WREG32_PCIE(*pos >> 2, value);
2646 static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf,
2647 size_t size, loff_t *pos)
2649 struct amdgpu_device *adev = f->f_inode->i_private;
2653 if (size & 0x3 || *pos & 0x3)
2659 value = RREG32_DIDT(*pos >> 2);
2660 r = put_user(value, (uint32_t *)buf);
2673 static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf,
2674 size_t size, loff_t *pos)
2676 struct amdgpu_device *adev = f->f_inode->i_private;
2680 if (size & 0x3 || *pos & 0x3)
2686 r = get_user(value, (uint32_t *)buf);
2690 WREG32_DIDT(*pos >> 2, value);
2701 static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf,
2702 size_t size, loff_t *pos)
2704 struct amdgpu_device *adev = f->f_inode->i_private;
2708 if (size & 0x3 || *pos & 0x3)
2714 value = RREG32_SMC(*pos);
2715 r = put_user(value, (uint32_t *)buf);
2728 static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf,
2729 size_t size, loff_t *pos)
2731 struct amdgpu_device *adev = f->f_inode->i_private;
2735 if (size & 0x3 || *pos & 0x3)
2741 r = get_user(value, (uint32_t *)buf);
2745 WREG32_SMC(*pos, value);
2756 static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf,
2757 size_t size, loff_t *pos)
2759 struct amdgpu_device *adev = f->f_inode->i_private;
2762 uint32_t *config, no_regs = 0;
2764 if (size & 0x3 || *pos & 0x3)
2767 config = kmalloc_array(256, sizeof(*config), GFP_KERNEL);
2771 /* version, increment each time something is added */
2772 config[no_regs++] = 2;
2773 config[no_regs++] = adev->gfx.config.max_shader_engines;
2774 config[no_regs++] = adev->gfx.config.max_tile_pipes;
2775 config[no_regs++] = adev->gfx.config.max_cu_per_sh;
2776 config[no_regs++] = adev->gfx.config.max_sh_per_se;
2777 config[no_regs++] = adev->gfx.config.max_backends_per_se;
2778 config[no_regs++] = adev->gfx.config.max_texture_channel_caches;
2779 config[no_regs++] = adev->gfx.config.max_gprs;
2780 config[no_regs++] = adev->gfx.config.max_gs_threads;
2781 config[no_regs++] = adev->gfx.config.max_hw_contexts;
2782 config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend;
2783 config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend;
2784 config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size;
2785 config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size;
2786 config[no_regs++] = adev->gfx.config.num_tile_pipes;
2787 config[no_regs++] = adev->gfx.config.backend_enable_mask;
2788 config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes;
2789 config[no_regs++] = adev->gfx.config.mem_row_size_in_kb;
2790 config[no_regs++] = adev->gfx.config.shader_engine_tile_size;
2791 config[no_regs++] = adev->gfx.config.num_gpus;
2792 config[no_regs++] = adev->gfx.config.multi_gpu_tile_size;
2793 config[no_regs++] = adev->gfx.config.mc_arb_ramcfg;
2794 config[no_regs++] = adev->gfx.config.gb_addr_config;
2795 config[no_regs++] = adev->gfx.config.num_rbs;
2798 config[no_regs++] = adev->rev_id;
2799 config[no_regs++] = adev->pg_flags;
2800 config[no_regs++] = adev->cg_flags;
2803 config[no_regs++] = adev->family;
2804 config[no_regs++] = adev->external_rev_id;
2806 while (size && (*pos < no_regs * 4)) {
2809 value = config[*pos >> 2];
2810 r = put_user(value, (uint32_t *)buf);
2826 static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf,
2827 size_t size, loff_t *pos)
2829 struct amdgpu_device *adev = f->f_inode->i_private;
2833 if (size != 4 || *pos & 0x3)
2836 /* convert offset to sensor number */
2839 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
2840 r = adev->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, idx, &value);
2845 r = put_user(value, (int32_t *)buf);
2850 static const struct file_operations amdgpu_debugfs_regs_fops = {
2851 .owner = THIS_MODULE,
2852 .read = amdgpu_debugfs_regs_read,
2853 .write = amdgpu_debugfs_regs_write,
2854 .llseek = default_llseek
2856 static const struct file_operations amdgpu_debugfs_regs_didt_fops = {
2857 .owner = THIS_MODULE,
2858 .read = amdgpu_debugfs_regs_didt_read,
2859 .write = amdgpu_debugfs_regs_didt_write,
2860 .llseek = default_llseek
2862 static const struct file_operations amdgpu_debugfs_regs_pcie_fops = {
2863 .owner = THIS_MODULE,
2864 .read = amdgpu_debugfs_regs_pcie_read,
2865 .write = amdgpu_debugfs_regs_pcie_write,
2866 .llseek = default_llseek
2868 static const struct file_operations amdgpu_debugfs_regs_smc_fops = {
2869 .owner = THIS_MODULE,
2870 .read = amdgpu_debugfs_regs_smc_read,
2871 .write = amdgpu_debugfs_regs_smc_write,
2872 .llseek = default_llseek
2875 static const struct file_operations amdgpu_debugfs_gca_config_fops = {
2876 .owner = THIS_MODULE,
2877 .read = amdgpu_debugfs_gca_config_read,
2878 .llseek = default_llseek
2881 static const struct file_operations amdgpu_debugfs_sensors_fops = {
2882 .owner = THIS_MODULE,
2883 .read = amdgpu_debugfs_sensor_read,
2884 .llseek = default_llseek
2887 static const struct file_operations *debugfs_regs[] = {
2888 &amdgpu_debugfs_regs_fops,
2889 &amdgpu_debugfs_regs_didt_fops,
2890 &amdgpu_debugfs_regs_pcie_fops,
2891 &amdgpu_debugfs_regs_smc_fops,
2892 &amdgpu_debugfs_gca_config_fops,
2893 &amdgpu_debugfs_sensors_fops,
2896 static const char *debugfs_regs_names[] = {
2901 "amdgpu_gca_config",
2905 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
2907 struct drm_minor *minor = adev->ddev->primary;
2908 struct dentry *ent, *root = minor->debugfs_root;
2911 for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
2912 ent = debugfs_create_file(debugfs_regs_names[i],
2913 S_IFREG | S_IRUGO, root,
2914 adev, debugfs_regs[i]);
2916 for (j = 0; j < i; j++) {
2917 debugfs_remove(adev->debugfs_regs[i]);
2918 adev->debugfs_regs[i] = NULL;
2920 return PTR_ERR(ent);
2924 i_size_write(ent->d_inode, adev->rmmio_size);
2925 adev->debugfs_regs[i] = ent;
2931 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev)
2935 for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
2936 if (adev->debugfs_regs[i]) {
2937 debugfs_remove(adev->debugfs_regs[i]);
2938 adev->debugfs_regs[i] = NULL;
2943 int amdgpu_debugfs_init(struct drm_minor *minor)
2948 void amdgpu_debugfs_cleanup(struct drm_minor *minor)
2952 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
2956 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { }