drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 #include "atom.h"
  26 #include "amdgpu.h"
  27 #include "amd_shared.h"
  28 #include <linux/module.h>
  29 #include <linux/moduleparam.h>
  30 #include "amdgpu_pm.h"
  31 #include <drm/amdgpu_drm.h>
  32 #include "amdgpu_powerplay.h"
  33 #include "cik_dpm.h"
  34 #include "vi_dpm.h"
  35
  36 static int amdgpu_powerplay_init(struct amdgpu_device *adev)
  37 {
  38         int ret = 0;
  39         struct amd_powerplay *amd_pp;
  40
  41         amd_pp = &(adev->powerplay);
  42
  43         if (adev->pp_enabled) {
  44 #ifdef CONFIG_DRM_AMD_POWERPLAY
  45                 struct amd_pp_init *pp_init;
  46
  47                 pp_init = kzalloc(sizeof(struct amd_pp_init), GFP_KERNEL);
  48
  49                 if (pp_init == NULL)
  50                         return -ENOMEM;
  51
  52                 pp_init->chip_family = adev->family;
  53                 pp_init->chip_id = adev->asic_type;
  54                 pp_init->device = amdgpu_cgs_create_device(adev);
  55
  56                 ret = amd_powerplay_init(pp_init, amd_pp);
  57                 kfree(pp_init);
  58 #endif
  59         } else {
  60                 amd_pp->pp_handle = (void *)adev;
  61
  62                 switch (adev->asic_type) {
  63 #ifdef CONFIG_DRM_AMDGPU_CIK
  64                 case CHIP_BONAIRE:
  65                 case CHIP_HAWAII:
  66                         amd_pp->ip_funcs = &ci_dpm_ip_funcs;
  67                         break;
  68                 case CHIP_KABINI:
  69                 case CHIP_MULLINS:
  70                 case CHIP_KAVERI:
  71                         amd_pp->ip_funcs = &kv_dpm_ip_funcs;
  72                         break;
  73 #endif
  74                 case CHIP_TOPAZ:
  75                         amd_pp->ip_funcs = &iceland_dpm_ip_funcs;
  76                         break;
  77                 case CHIP_TONGA:
  78                         amd_pp->ip_funcs = &tonga_dpm_ip_funcs;
  79                         break;
  80                 case CHIP_FIJI:
  81                         amd_pp->ip_funcs = &fiji_dpm_ip_funcs;
  82                         break;
  83                 case CHIP_CARRIZO:
  84                 case CHIP_STONEY:
  85                         amd_pp->ip_funcs = &cz_dpm_ip_funcs;
  86                         break;
  87                 default:
  88                         ret = -EINVAL;
  89                         break;
  90                 }
  91         }
  92         return ret;
  93 }
  94
  95 static int amdgpu_pp_early_init(void *handle)
  96 {
  97         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  98         int ret = 0;
  99
 100 #ifdef CONFIG_DRM_AMD_POWERPLAY
 101         switch (adev->asic_type) {
 102         case CHIP_POLARIS11:
 103         case CHIP_POLARIS10:
 104                 adev->pp_enabled = true;
 105                 break;
 106         case CHIP_TONGA:
 107         case CHIP_FIJI:
 108                 adev->pp_enabled = (amdgpu_powerplay == 0) ? false : true;
 109                 break;
 110         case CHIP_CARRIZO:
 111         case CHIP_STONEY:
 112                 adev->pp_enabled = (amdgpu_powerplay > 0) ? true : false;
 113                 break;
 114         /* These chips don't have powerplay implemenations */
 115         case CHIP_BONAIRE:
 116         case CHIP_HAWAII:
 117         case CHIP_KABINI:
 118         case CHIP_MULLINS:
 119         case CHIP_KAVERI:
 120         case CHIP_TOPAZ:
 121         default:
 122                 adev->pp_enabled = false;
 123                 break;
 124         }
 125 #else
 126         adev->pp_enabled = false;
 127 #endif
 128
 129         ret = amdgpu_powerplay_init(adev);
 130         if (ret)
 131                 return ret;
 132
 133         if (adev->powerplay.ip_funcs->early_init)
 134                 ret = adev->powerplay.ip_funcs->early_init(
 135                                         adev->powerplay.pp_handle);
 136         return ret;
 137 }
 138
 139
 140 static int amdgpu_pp_late_init(void *handle)
 141 {
 142         int ret = 0;
 143         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 144
 145         if (adev->powerplay.ip_funcs->late_init)
 146                 ret = adev->powerplay.ip_funcs->late_init(
 147                                         adev->powerplay.pp_handle);
 148
 149 #ifdef CONFIG_DRM_AMD_POWERPLAY
 150         if (adev->pp_enabled && adev->pm.dpm_enabled) {
 151                 amdgpu_pm_sysfs_init(adev);
 152                 amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_COMPLETE_INIT, NULL, NULL);
 153         }
 154 #endif
 155         return ret;
 156 }
 157
 158 static int amdgpu_pp_sw_init(void *handle)
 159 {
 160         int ret = 0;
 161         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 162
 163         if (adev->powerplay.ip_funcs->sw_init)
 164                 ret = adev->powerplay.ip_funcs->sw_init(
 165                                         adev->powerplay.pp_handle);
 166
 167 #ifdef CONFIG_DRM_AMD_POWERPLAY
 168         if (adev->pp_enabled)
 169                 adev->pm.dpm_enabled = true;
 170 #endif
 171
 172         return ret;
 173 }
 174
 175 static int amdgpu_pp_sw_fini(void *handle)
 176 {
 177         int ret = 0;
 178         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 179
 180         if (adev->powerplay.ip_funcs->sw_fini)
 181                 ret = adev->powerplay.ip_funcs->sw_fini(
 182                                         adev->powerplay.pp_handle);
 183         if (ret)
 184                 return ret;
 185
 186 #ifdef CONFIG_DRM_AMD_POWERPLAY
 187         if (adev->pp_enabled) {
 188                 amdgpu_pm_sysfs_fini(adev);
 189                 amd_powerplay_fini(adev->powerplay.pp_handle);
 190         }
 191 #endif
 192
 193         return ret;
 194 }
 195
 196 static int amdgpu_pp_hw_init(void *handle)
 197 {
 198         int ret = 0;
 199         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 200
 201         if (adev->pp_enabled && adev->firmware.smu_load)
 202                 amdgpu_ucode_init_bo(adev);
 203
 204         if (adev->powerplay.ip_funcs->hw_init)
 205                 ret = adev->powerplay.ip_funcs->hw_init(
 206                                         adev->powerplay.pp_handle);
 207
 208         return ret;
 209 }
 210
 211 static int amdgpu_pp_hw_fini(void *handle)
 212 {
 213         int ret = 0;
 214         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 215
 216         if (adev->powerplay.ip_funcs->hw_fini)
 217                 ret = adev->powerplay.ip_funcs->hw_fini(
 218                                         adev->powerplay.pp_handle);
 219
 220         if (adev->pp_enabled && adev->firmware.smu_load)
 221                 amdgpu_ucode_fini_bo(adev);
 222
 223         return ret;
 224 }
 225
 226 static int amdgpu_pp_suspend(void *handle)
 227 {
 228         int ret = 0;
 229         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 230
 231         if (adev->powerplay.ip_funcs->suspend)
 232                 ret = adev->powerplay.ip_funcs->suspend(
 233                                          adev->powerplay.pp_handle);
 234         return ret;
 235 }
 236
 237 static int amdgpu_pp_resume(void *handle)
 238 {
 239         int ret = 0;
 240         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 241
 242         if (adev->powerplay.ip_funcs->resume)
 243                 ret = adev->powerplay.ip_funcs->resume(
 244                                         adev->powerplay.pp_handle);
 245         return ret;
 246 }
 247
 248 static int amdgpu_pp_set_clockgating_state(void *handle,
 249                                         enum amd_clockgating_state state)
 250 {
 251         int ret = 0;
 252         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 253
 254         if (adev->powerplay.ip_funcs->set_clockgating_state)
 255                 ret = adev->powerplay.ip_funcs->set_clockgating_state(
 256                                 adev->powerplay.pp_handle, state);
 257         return ret;
 258 }
 259
 260 static int amdgpu_pp_set_powergating_state(void *handle,
 261                                         enum amd_powergating_state state)
 262 {
 263         int ret = 0;
 264         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 265
 266         if (adev->powerplay.ip_funcs->set_powergating_state)
 267                 ret = adev->powerplay.ip_funcs->set_powergating_state(
 268                                  adev->powerplay.pp_handle, state);
 269         return ret;
 270 }
 271
 272
 273 static bool amdgpu_pp_is_idle(void *handle)
 274 {
 275         bool ret = true;
 276         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 277
 278         if (adev->powerplay.ip_funcs->is_idle)
 279                 ret = adev->powerplay.ip_funcs->is_idle(
 280                                         adev->powerplay.pp_handle);
 281         return ret;
 282 }
 283
 284 static int amdgpu_pp_wait_for_idle(void *handle)
 285 {
 286         int ret = 0;
 287         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 288
 289         if (adev->powerplay.ip_funcs->wait_for_idle)
 290                 ret = adev->powerplay.ip_funcs->wait_for_idle(
 291                                         adev->powerplay.pp_handle);
 292         return ret;
 293 }
 294
 295 static int amdgpu_pp_soft_reset(void *handle)
 296 {
 297         int ret = 0;
 298         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 299
 300         if (adev->powerplay.ip_funcs->soft_reset)
 301                 ret = adev->powerplay.ip_funcs->soft_reset(
 302                                         adev->powerplay.pp_handle);
 303         return ret;
 304 }
 305
 306 const struct amd_ip_funcs amdgpu_pp_ip_funcs = {
 307         .name = "amdgpu_powerplay",
 308         .early_init = amdgpu_pp_early_init,
 309         .late_init = amdgpu_pp_late_init,
 310         .sw_init = amdgpu_pp_sw_init,
 311         .sw_fini = amdgpu_pp_sw_fini,
 312         .hw_init = amdgpu_pp_hw_init,
 313         .hw_fini = amdgpu_pp_hw_fini,
 314         .suspend = amdgpu_pp_suspend,
 315         .resume = amdgpu_pp_resume,
 316         .is_idle = amdgpu_pp_is_idle,
 317         .wait_for_idle = amdgpu_pp_wait_for_idle,
 318         .soft_reset = amdgpu_pp_soft_reset,
 319         .set_clockgating_state = amdgpu_pp_set_clockgating_state,
 320         .set_powergating_state = amdgpu_pp_set_powergating_state,
 321 };