drivers/gpu/drm/amd/amdgpu/cz_dpm.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <linux/seq_file.h>
  26 #include "drmP.h"
  27 #include "amdgpu.h"
  28 #include "amdgpu_pm.h"
  29 #include "amdgpu_atombios.h"
  30 #include "vid.h"
  31 #include "vi_dpm.h"
  32 #include "amdgpu_dpm.h"
  33 #include "cz_dpm.h"
  34 #include "cz_ppsmc.h"
  35 #include "atom.h"
  36
  37 #include "smu/smu_8_0_d.h"
  38 #include "smu/smu_8_0_sh_mask.h"
  39 #include "gca/gfx_8_0_d.h"
  40 #include "gca/gfx_8_0_sh_mask.h"
  41 #include "gmc/gmc_8_1_d.h"
  42 #include "bif/bif_5_1_d.h"
  43 #include "gfx_v8_0.h"
  44
  45 static void cz_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate);
  46 static void cz_dpm_powergate_vce(struct amdgpu_device *adev, bool gate);
  47 static void cz_dpm_fini(struct amdgpu_device *adev);
  48
  49 static struct cz_ps *cz_get_ps(struct amdgpu_ps *rps)
  50 {
  51         struct cz_ps *ps = rps->ps_priv;
  52
  53         return ps;
  54 }
  55
  56 static struct cz_power_info *cz_get_pi(struct amdgpu_device *adev)
  57 {
  58         struct cz_power_info *pi = adev->pm.dpm.priv;
  59
  60         return pi;
  61 }
  62
  63 static uint16_t cz_convert_8bit_index_to_voltage(struct amdgpu_device *adev,
  64                                                         uint16_t voltage)
  65 {
  66         uint16_t tmp = 6200 - voltage * 25;
  67
  68         return tmp;
  69 }
  70
  71 static void cz_construct_max_power_limits_table(struct amdgpu_device *adev,
  72                                 struct amdgpu_clock_and_voltage_limits *table)
  73 {
  74         struct cz_power_info *pi = cz_get_pi(adev);
  75         struct amdgpu_clock_voltage_dependency_table *dep_table =
  76                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
  77
  78         if (dep_table->count > 0) {
  79                 table->sclk = dep_table->entries[dep_table->count - 1].clk;
  80                 table->vddc = cz_convert_8bit_index_to_voltage(adev,
  81                                 dep_table->entries[dep_table->count - 1].v);
  82         }
  83
  84         table->mclk = pi->sys_info.nbp_memory_clock[0];
  85
  86 }
  87
  88 union igp_info {
  89         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
  90         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
  91         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
  92         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9 info_9;
  93 };
  94
  95 static int cz_parse_sys_info_table(struct amdgpu_device *adev)
  96 {
  97         struct cz_power_info *pi = cz_get_pi(adev);
  98         struct amdgpu_mode_info *mode_info = &adev->mode_info;
  99         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
 100         union igp_info *igp_info;
 101         u8 frev, crev;
 102         u16 data_offset;
 103         int i = 0;
 104
 105         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 106                                    &frev, &crev, &data_offset)) {
 107                 igp_info = (union igp_info *)(mode_info->atom_context->bios +
 108                                               data_offset);
 109
 110                 if (crev != 9) {
 111                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
 112                         return -EINVAL;
 113                 }
 114                 pi->sys_info.bootup_sclk =
 115                         le32_to_cpu(igp_info->info_9.ulBootUpEngineClock);
 116                 pi->sys_info.bootup_uma_clk =
 117                         le32_to_cpu(igp_info->info_9.ulBootUpUMAClock);
 118                 pi->sys_info.dentist_vco_freq =
 119                         le32_to_cpu(igp_info->info_9.ulDentistVCOFreq);
 120                 pi->sys_info.bootup_nb_voltage_index =
 121                         le16_to_cpu(igp_info->info_9.usBootUpNBVoltage);
 122
 123                 if (igp_info->info_9.ucHtcTmpLmt == 0)
 124                         pi->sys_info.htc_tmp_lmt = 203;
 125                 else
 126                         pi->sys_info.htc_tmp_lmt = igp_info->info_9.ucHtcTmpLmt;
 127
 128                 if (igp_info->info_9.ucHtcHystLmt == 0)
 129                         pi->sys_info.htc_hyst_lmt = 5;
 130                 else
 131                         pi->sys_info.htc_hyst_lmt = igp_info->info_9.ucHtcHystLmt;
 132
 133                 if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) {
 134                         DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n");
 135                         return -EINVAL;
 136                 }
 137
 138                 if (le32_to_cpu(igp_info->info_9.ulSystemConfig) & (1 << 3) &&
 139                                 pi->enable_nb_ps_policy)
 140                         pi->sys_info.nb_dpm_enable = true;
 141                 else
 142                         pi->sys_info.nb_dpm_enable = false;
 143
 144                 for (i = 0; i < CZ_NUM_NBPSTATES; i++) {
 145                         if (i < CZ_NUM_NBPMEMORY_CLOCK)
 146                                 pi->sys_info.nbp_memory_clock[i] =
 147                                 le32_to_cpu(igp_info->info_9.ulNbpStateMemclkFreq[i]);
 148                         pi->sys_info.nbp_n_clock[i] =
 149                         le32_to_cpu(igp_info->info_9.ulNbpStateNClkFreq[i]);
 150                 }
 151
 152                 for (i = 0; i < CZ_MAX_DISPLAY_CLOCK_LEVEL; i++)
 153                         pi->sys_info.display_clock[i] =
 154                         le32_to_cpu(igp_info->info_9.sDispClkVoltageMapping[i].ulMaximumSupportedCLK);
 155
 156                 for (i = 0; i < CZ_NUM_NBPSTATES; i++)
 157                         pi->sys_info.nbp_voltage_index[i] =
 158                                 le32_to_cpu(igp_info->info_9.usNBPStateVoltage[i]);
 159
 160                 if (le32_to_cpu(igp_info->info_9.ulGPUCapInfo) &
 161                         SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS)
 162                         pi->caps_enable_dfs_bypass = true;
 163
 164                 pi->sys_info.uma_channel_number =
 165                         igp_info->info_9.ucUMAChannelNumber;
 166
 167                 cz_construct_max_power_limits_table(adev,
 168                         &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
 169         }
 170
 171         return 0;
 172 }
 173
 174 static void cz_patch_voltage_values(struct amdgpu_device *adev)
 175 {
 176         int i;
 177         struct amdgpu_uvd_clock_voltage_dependency_table *uvd_table =
 178                 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
 179         struct amdgpu_vce_clock_voltage_dependency_table *vce_table =
 180                 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
 181         struct amdgpu_clock_voltage_dependency_table *acp_table =
 182                 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
 183
 184         if (uvd_table->count) {
 185                 for (i = 0; i < uvd_table->count; i++)
 186                         uvd_table->entries[i].v =
 187                                 cz_convert_8bit_index_to_voltage(adev,
 188                                                 uvd_table->entries[i].v);
 189         }
 190
 191         if (vce_table->count) {
 192                 for (i = 0; i < vce_table->count; i++)
 193                         vce_table->entries[i].v =
 194                                 cz_convert_8bit_index_to_voltage(adev,
 195                                                 vce_table->entries[i].v);
 196         }
 197
 198         if (acp_table->count) {
 199                 for (i = 0; i < acp_table->count; i++)
 200                         acp_table->entries[i].v =
 201                                 cz_convert_8bit_index_to_voltage(adev,
 202                                                 acp_table->entries[i].v);
 203         }
 204
 205 }
 206
 207 static void cz_construct_boot_state(struct amdgpu_device *adev)
 208 {
 209         struct cz_power_info *pi = cz_get_pi(adev);
 210
 211         pi->boot_pl.sclk = pi->sys_info.bootup_sclk;
 212         pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index;
 213         pi->boot_pl.ds_divider_index = 0;
 214         pi->boot_pl.ss_divider_index = 0;
 215         pi->boot_pl.allow_gnb_slow = 1;
 216         pi->boot_pl.force_nbp_state = 0;
 217         pi->boot_pl.display_wm = 0;
 218         pi->boot_pl.vce_wm = 0;
 219
 220 }
 221
 222 static void cz_patch_boot_state(struct amdgpu_device *adev,
 223                                 struct cz_ps *ps)
 224 {
 225         struct cz_power_info *pi = cz_get_pi(adev);
 226
 227         ps->num_levels = 1;
 228         ps->levels[0] = pi->boot_pl;
 229 }
 230
 231 union pplib_clock_info {
 232         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
 233         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
 234         struct _ATOM_PPLIB_CZ_CLOCK_INFO carrizo;
 235 };
 236
 237 static void cz_parse_pplib_clock_info(struct amdgpu_device *adev,
 238                                         struct amdgpu_ps *rps, int index,
 239                                         union pplib_clock_info *clock_info)
 240 {
 241         struct cz_power_info *pi = cz_get_pi(adev);
 242         struct cz_ps *ps = cz_get_ps(rps);
 243         struct cz_pl *pl = &ps->levels[index];
 244         struct amdgpu_clock_voltage_dependency_table *table =
 245                         &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
 246
 247         pl->sclk = table->entries[clock_info->carrizo.index].clk;
 248         pl->vddc_index = table->entries[clock_info->carrizo.index].v;
 249
 250         ps->num_levels = index + 1;
 251
 252         if (pi->caps_sclk_ds) {
 253                 pl->ds_divider_index = 5;
 254                 pl->ss_divider_index = 5;
 255         }
 256
 257 }
 258
 259 static void cz_parse_pplib_non_clock_info(struct amdgpu_device *adev,
 260                         struct amdgpu_ps *rps,
 261                         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
 262                         u8 table_rev)
 263 {
 264         struct cz_ps *ps = cz_get_ps(rps);
 265
 266         rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
 267         rps->class = le16_to_cpu(non_clock_info->usClassification);
 268         rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
 269
 270         if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
 271                 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
 272                 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
 273         } else {
 274                 rps->vclk = 0;
 275                 rps->dclk = 0;
 276         }
 277
 278         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
 279                 adev->pm.dpm.boot_ps = rps;
 280                 cz_patch_boot_state(adev, ps);
 281         }
 282         if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
 283                 adev->pm.dpm.uvd_ps = rps;
 284
 285 }
 286
 287 union power_info {
 288         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
 289         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
 290         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
 291         struct _ATOM_PPLIB_POWERPLAYTABLE4 pplib4;
 292         struct _ATOM_PPLIB_POWERPLAYTABLE5 pplib5;
 293 };
 294
 295 union pplib_power_state {
 296         struct _ATOM_PPLIB_STATE v1;
 297         struct _ATOM_PPLIB_STATE_V2 v2;
 298 };
 299
 300 static int cz_parse_power_table(struct amdgpu_device *adev)
 301 {
 302         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 303         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
 304         union pplib_power_state *power_state;
 305         int i, j, k, non_clock_array_index, clock_array_index;
 306         union pplib_clock_info *clock_info;
 307         struct _StateArray *state_array;
 308         struct _ClockInfoArray *clock_info_array;
 309         struct _NonClockInfoArray *non_clock_info_array;
 310         union power_info *power_info;
 311         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
 312         u16 data_offset;
 313         u8 frev, crev;
 314         u8 *power_state_offset;
 315         struct cz_ps *ps;
 316
 317         if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 318                                     &frev, &crev, &data_offset))
 319                 return -EINVAL;
 320         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
 321
 322         state_array = (struct _StateArray *)
 323                 (mode_info->atom_context->bios + data_offset +
 324                 le16_to_cpu(power_info->pplib.usStateArrayOffset));
 325         clock_info_array = (struct _ClockInfoArray *)
 326                 (mode_info->atom_context->bios + data_offset +
 327                 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
 328         non_clock_info_array = (struct _NonClockInfoArray *)
 329                 (mode_info->atom_context->bios + data_offset +
 330                 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
 331
 332         adev->pm.dpm.ps = kzalloc(sizeof(struct amdgpu_ps) *
 333                                         state_array->ucNumEntries, GFP_KERNEL);
 334
 335         if (!adev->pm.dpm.ps)
 336                 return -ENOMEM;
 337
 338         power_state_offset = (u8 *)state_array->states;
 339         adev->pm.dpm.platform_caps =
 340                         le32_to_cpu(power_info->pplib.ulPlatformCaps);
 341         adev->pm.dpm.backbias_response_time =
 342                         le16_to_cpu(power_info->pplib.usBackbiasTime);
 343         adev->pm.dpm.voltage_response_time =
 344                         le16_to_cpu(power_info->pplib.usVoltageTime);
 345
 346         for (i = 0; i < state_array->ucNumEntries; i++) {
 347                 power_state = (union pplib_power_state *)power_state_offset;
 348                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
 349                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
 350                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
 351
 352                 ps = kzalloc(sizeof(struct cz_ps), GFP_KERNEL);
 353                 if (ps == NULL) {
 354                         for (j = 0; j < i; j++)
 355                                 kfree(adev->pm.dpm.ps[j].ps_priv);
 356                         kfree(adev->pm.dpm.ps);
 357                         return -ENOMEM;
 358                 }
 359
 360                 adev->pm.dpm.ps[i].ps_priv = ps;
 361                 k = 0;
 362                 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
 363                         clock_array_index = power_state->v2.clockInfoIndex[j];
 364                         if (clock_array_index >= clock_info_array->ucNumEntries)
 365                                 continue;
 366                         if (k >= CZ_MAX_HARDWARE_POWERLEVELS)
 367                                 break;
 368                         clock_info = (union pplib_clock_info *)
 369                                 &clock_info_array->clockInfo[clock_array_index *
 370                                 clock_info_array->ucEntrySize];
 371                         cz_parse_pplib_clock_info(adev, &adev->pm.dpm.ps[i],
 372                                 k, clock_info);
 373                         k++;
 374                 }
 375                 cz_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],
 376                                         non_clock_info,
 377                                         non_clock_info_array->ucEntrySize);
 378                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
 379         }
 380         adev->pm.dpm.num_ps = state_array->ucNumEntries;
 381
 382         return 0;
 383 }
 384
 385 static int cz_process_firmware_header(struct amdgpu_device *adev)
 386 {
 387         struct cz_power_info *pi = cz_get_pi(adev);
 388         u32 tmp;
 389         int ret;
 390
 391         ret = cz_read_smc_sram_dword(adev, SMU8_FIRMWARE_HEADER_LOCATION +
 392                                      offsetof(struct SMU8_Firmware_Header,
 393                                      DpmTable),
 394                                      &tmp, pi->sram_end);
 395
 396         if (ret == 0)
 397                 pi->dpm_table_start = tmp;
 398
 399         return ret;
 400 }
 401
 402 static int cz_dpm_init(struct amdgpu_device *adev)
 403 {
 404         struct cz_power_info *pi;
 405         int ret, i;
 406
 407         pi = kzalloc(sizeof(struct cz_power_info), GFP_KERNEL);
 408         if (NULL == pi)
 409                 return -ENOMEM;
 410
 411         adev->pm.dpm.priv = pi;
 412
 413         ret = amdgpu_get_platform_caps(adev);
 414         if (ret)
 415                 goto err;
 416
 417         ret = amdgpu_parse_extended_power_table(adev);
 418         if (ret)
 419                 goto err;
 420
 421         pi->sram_end = SMC_RAM_END;
 422
 423         /* set up DPM defaults */
 424         for (i = 0; i < CZ_MAX_HARDWARE_POWERLEVELS; i++)
 425                 pi->active_target[i] = CZ_AT_DFLT;
 426
 427         pi->mgcg_cgtt_local0 = 0x0;
 428         pi->mgcg_cgtt_local1 = 0x0;
 429         pi->clock_slow_down_step = 25000;
 430         pi->skip_clock_slow_down = 1;
 431         pi->enable_nb_ps_policy = false;
 432         pi->caps_power_containment = true;
 433         pi->caps_cac = true;
 434         pi->didt_enabled = false;
 435         if (pi->didt_enabled) {
 436                 pi->caps_sq_ramping = true;
 437                 pi->caps_db_ramping = true;
 438                 pi->caps_td_ramping = true;
 439                 pi->caps_tcp_ramping = true;
 440         }
 441         if (amdgpu_sclk_deep_sleep_en)
 442                 pi->caps_sclk_ds = true;
 443         else
 444                 pi->caps_sclk_ds = false;
 445
 446         pi->voting_clients = 0x00c00033;
 447         pi->auto_thermal_throttling_enabled = true;
 448         pi->bapm_enabled = false;
 449         pi->disable_nb_ps3_in_battery = false;
 450         pi->voltage_drop_threshold = 0;
 451         pi->caps_sclk_throttle_low_notification = false;
 452         pi->gfx_pg_threshold = 500;
 453         pi->caps_fps = true;
 454         /* uvd */
 455         pi->caps_uvd_pg = (adev->pg_flags & AMD_PG_SUPPORT_UVD) ? true : false;
 456         pi->caps_uvd_dpm = true;
 457         /* vce */
 458         pi->caps_vce_pg = (adev->pg_flags & AMD_PG_SUPPORT_VCE) ? true : false;
 459         pi->caps_vce_dpm = true;
 460         /* acp */
 461         pi->caps_acp_pg = (adev->pg_flags & AMD_PG_SUPPORT_ACP) ? true : false;
 462         pi->caps_acp_dpm = true;
 463
 464         pi->caps_stable_power_state = false;
 465         pi->nb_dpm_enabled_by_driver = true;
 466         pi->nb_dpm_enabled = false;
 467         pi->caps_voltage_island = false;
 468         /* flags which indicate need to upload pptable */
 469         pi->need_pptable_upload = true;
 470
 471         ret = cz_parse_sys_info_table(adev);
 472         if (ret)
 473                 goto err;
 474
 475         cz_patch_voltage_values(adev);
 476         cz_construct_boot_state(adev);
 477
 478         ret = cz_parse_power_table(adev);
 479         if (ret)
 480                 goto err;
 481
 482         ret = cz_process_firmware_header(adev);
 483         if (ret)
 484                 goto err;
 485
 486         pi->dpm_enabled = true;
 487         pi->uvd_dynamic_pg = false;
 488
 489         return 0;
 490 err:
 491         cz_dpm_fini(adev);
 492         return ret;
 493 }
 494
 495 static void cz_dpm_fini(struct amdgpu_device *adev)
 496 {
 497         int i;
 498
 499         for (i = 0; i < adev->pm.dpm.num_ps; i++)
 500                 kfree(adev->pm.dpm.ps[i].ps_priv);
 501
 502         kfree(adev->pm.dpm.ps);
 503         kfree(adev->pm.dpm.priv);
 504         amdgpu_free_extended_power_table(adev);
 505 }
 506
 507 #define ixSMUSVI_NB_CURRENTVID 0xD8230044
 508 #define CURRENT_NB_VID_MASK 0xff000000
 509 #define CURRENT_NB_VID__SHIFT 24
 510 #define ixSMUSVI_GFX_CURRENTVID  0xD8230048
 511 #define CURRENT_GFX_VID_MASK 0xff000000
 512 #define CURRENT_GFX_VID__SHIFT 24
 513
 514 static void
 515 cz_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
 516                                                struct seq_file *m)
 517 {
 518         struct cz_power_info *pi = cz_get_pi(adev);
 519         struct amdgpu_clock_voltage_dependency_table *table =
 520                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
 521         struct amdgpu_uvd_clock_voltage_dependency_table *uvd_table =
 522                 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
 523         struct amdgpu_vce_clock_voltage_dependency_table *vce_table =
 524                 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
 525         u32 sclk_index = REG_GET_FIELD(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX),
 526                                        TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX);
 527         u32 uvd_index = REG_GET_FIELD(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
 528                                       TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_UVD_INDEX);
 529         u32 vce_index = REG_GET_FIELD(RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
 530                                       TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_VCE_INDEX);
 531         u32 sclk, vclk, dclk, ecclk, tmp;
 532         u16 vddnb, vddgfx;
 533
 534         if (sclk_index >= NUM_SCLK_LEVELS) {
 535                 seq_printf(m, "invalid sclk dpm profile %d\n", sclk_index);
 536         } else {
 537                 sclk = table->entries[sclk_index].clk;
 538                 seq_printf(m, "%u sclk: %u\n", sclk_index, sclk);
 539         }
 540
 541         tmp = (RREG32_SMC(ixSMUSVI_NB_CURRENTVID) &
 542                CURRENT_NB_VID_MASK) >> CURRENT_NB_VID__SHIFT;
 543         vddnb = cz_convert_8bit_index_to_voltage(adev, (u16)tmp);
 544         tmp = (RREG32_SMC(ixSMUSVI_GFX_CURRENTVID) &
 545                CURRENT_GFX_VID_MASK) >> CURRENT_GFX_VID__SHIFT;
 546         vddgfx = cz_convert_8bit_index_to_voltage(adev, (u16)tmp);
 547         seq_printf(m, "vddnb: %u vddgfx: %u\n", vddnb, vddgfx);
 548
 549         seq_printf(m, "uvd    %sabled\n", pi->uvd_power_gated ? "dis" : "en");
 550         if (!pi->uvd_power_gated) {
 551                 if (uvd_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
 552                         seq_printf(m, "invalid uvd dpm level %d\n", uvd_index);
 553                 } else {
 554                         vclk = uvd_table->entries[uvd_index].vclk;
 555                         dclk = uvd_table->entries[uvd_index].dclk;
 556                         seq_printf(m, "%u uvd vclk: %u dclk: %u\n", uvd_index, vclk, dclk);
 557                 }
 558         }
 559
 560         seq_printf(m, "vce    %sabled\n", pi->vce_power_gated ? "dis" : "en");
 561         if (!pi->vce_power_gated) {
 562                 if (vce_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
 563                         seq_printf(m, "invalid vce dpm level %d\n", vce_index);
 564                 } else {
 565                         ecclk = vce_table->entries[vce_index].ecclk;
 566                         seq_printf(m, "%u vce ecclk: %u\n", vce_index, ecclk);
 567                 }
 568         }
 569 }
 570
 571 static void cz_dpm_print_power_state(struct amdgpu_device *adev,
 572                                         struct amdgpu_ps *rps)
 573 {
 574         int i;
 575         struct cz_ps *ps = cz_get_ps(rps);
 576
 577         amdgpu_dpm_print_class_info(rps->class, rps->class2);
 578         amdgpu_dpm_print_cap_info(rps->caps);
 579
 580         DRM_INFO("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
 581         for (i = 0; i < ps->num_levels; i++) {
 582                 struct cz_pl *pl = &ps->levels[i];
 583
 584                 DRM_INFO("\t\tpower level %d    sclk: %u vddc: %u\n",
 585                        i, pl->sclk,
 586                        cz_convert_8bit_index_to_voltage(adev, pl->vddc_index));
 587         }
 588
 589         amdgpu_dpm_print_ps_status(adev, rps);
 590 }
 591
 592 static void cz_dpm_set_funcs(struct amdgpu_device *adev);
 593
 594 static int cz_dpm_early_init(void *handle)
 595 {
 596         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 597
 598         cz_dpm_set_funcs(adev);
 599
 600         return 0;
 601 }
 602
 603
 604 static int cz_dpm_late_init(void *handle)
 605 {
 606         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 607
 608         if (amdgpu_dpm) {
 609                 int ret;
 610                 /* init the sysfs and debugfs files late */
 611                 ret = amdgpu_pm_sysfs_init(adev);
 612                 if (ret)
 613                         return ret;
 614
 615                 /* powerdown unused blocks for now */
 616                 cz_dpm_powergate_uvd(adev, true);
 617                 cz_dpm_powergate_vce(adev, true);
 618         }
 619
 620         return 0;
 621 }
 622
 623 static int cz_dpm_sw_init(void *handle)
 624 {
 625         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 626         int ret = 0;
 627         /* fix me to add thermal support TODO */
 628
 629         /* default to balanced state */
 630         adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
 631         adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
 632         adev->pm.dpm.forced_level = AMDGPU_DPM_FORCED_LEVEL_AUTO;
 633         adev->pm.default_sclk = adev->clock.default_sclk;
 634         adev->pm.default_mclk = adev->clock.default_mclk;
 635         adev->pm.current_sclk = adev->clock.default_sclk;
 636         adev->pm.current_mclk = adev->clock.default_mclk;
 637         adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
 638
 639         if (amdgpu_dpm == 0)
 640                 return 0;
 641
 642         mutex_lock(&adev->pm.mutex);
 643         ret = cz_dpm_init(adev);
 644         if (ret)
 645                 goto dpm_init_failed;
 646
 647         adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
 648         if (amdgpu_dpm == 1)
 649                 amdgpu_pm_print_power_states(adev);
 650
 651         mutex_unlock(&adev->pm.mutex);
 652         DRM_INFO("amdgpu: dpm initialized\n");
 653
 654         return 0;
 655
 656 dpm_init_failed:
 657         cz_dpm_fini(adev);
 658         mutex_unlock(&adev->pm.mutex);
 659         DRM_ERROR("amdgpu: dpm initialization failed\n");
 660
 661         return ret;
 662 }
 663
 664 static int cz_dpm_sw_fini(void *handle)
 665 {
 666         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 667
 668         mutex_lock(&adev->pm.mutex);
 669         amdgpu_pm_sysfs_fini(adev);
 670         cz_dpm_fini(adev);
 671         mutex_unlock(&adev->pm.mutex);
 672
 673         return 0;
 674 }
 675
 676 static void cz_reset_ap_mask(struct amdgpu_device *adev)
 677 {
 678         struct cz_power_info *pi = cz_get_pi(adev);
 679
 680         pi->active_process_mask = 0;
 681 }
 682
 683 static int cz_dpm_download_pptable_from_smu(struct amdgpu_device *adev,
 684                                                         void **table)
 685 {
 686         return cz_smu_download_pptable(adev, table);
 687 }
 688
 689 static int cz_dpm_upload_pptable_to_smu(struct amdgpu_device *adev)
 690 {
 691         struct cz_power_info *pi = cz_get_pi(adev);
 692         struct SMU8_Fusion_ClkTable *clock_table;
 693         struct atom_clock_dividers dividers;
 694         void *table = NULL;
 695         uint8_t i = 0;
 696         int ret = 0;
 697
 698         struct amdgpu_clock_voltage_dependency_table *vddc_table =
 699                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
 700         struct amdgpu_clock_voltage_dependency_table *vddgfx_table =
 701                 &adev->pm.dpm.dyn_state.vddgfx_dependency_on_sclk;
 702         struct amdgpu_uvd_clock_voltage_dependency_table *uvd_table =
 703                 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
 704         struct amdgpu_vce_clock_voltage_dependency_table *vce_table =
 705                 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
 706         struct amdgpu_clock_voltage_dependency_table *acp_table =
 707                 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
 708
 709         if (!pi->need_pptable_upload)
 710                 return 0;
 711
 712         ret = cz_dpm_download_pptable_from_smu(adev, &table);
 713         if (ret) {
 714                 DRM_ERROR("amdgpu: Failed to get power play table from SMU!\n");
 715                 return -EINVAL;
 716         }
 717
 718         clock_table = (struct SMU8_Fusion_ClkTable *)table;
 719         /* patch clock table */
 720         if (vddc_table->count > CZ_MAX_HARDWARE_POWERLEVELS ||
 721                         vddgfx_table->count > CZ_MAX_HARDWARE_POWERLEVELS ||
 722                         uvd_table->count > CZ_MAX_HARDWARE_POWERLEVELS ||
 723                         vce_table->count > CZ_MAX_HARDWARE_POWERLEVELS ||
 724                         acp_table->count > CZ_MAX_HARDWARE_POWERLEVELS) {
 725                 DRM_ERROR("amdgpu: Invalid Clock Voltage Dependency Table!\n");
 726                 return -EINVAL;
 727         }
 728
 729         for (i = 0; i < CZ_MAX_HARDWARE_POWERLEVELS; i++) {
 730
 731                 /* vddc sclk */
 732                 clock_table->SclkBreakdownTable.ClkLevel[i].GnbVid =
 733                         (i < vddc_table->count) ? (uint8_t)vddc_table->entries[i].v : 0;
 734                 clock_table->SclkBreakdownTable.ClkLevel[i].Frequency =
 735                         (i < vddc_table->count) ? vddc_table->entries[i].clk : 0;
 736                 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
 737                                 clock_table->SclkBreakdownTable.ClkLevel[i].Frequency,
 738                                 false, &dividers);
 739                 if (ret)
 740                         return ret;
 741                 clock_table->SclkBreakdownTable.ClkLevel[i].DfsDid =
 742                                                 (uint8_t)dividers.post_divider;
 743
 744                 /* vddgfx sclk */
 745                 clock_table->SclkBreakdownTable.ClkLevel[i].GfxVid =
 746                         (i < vddgfx_table->count) ? (uint8_t)vddgfx_table->entries[i].v : 0;
 747
 748                 /* acp breakdown */
 749                 clock_table->AclkBreakdownTable.ClkLevel[i].GfxVid =
 750                         (i < acp_table->count) ? (uint8_t)acp_table->entries[i].v : 0;
 751                 clock_table->AclkBreakdownTable.ClkLevel[i].Frequency =
 752                         (i < acp_table->count) ? acp_table->entries[i].clk : 0;
 753                 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
 754                                 clock_table->SclkBreakdownTable.ClkLevel[i].Frequency,
 755                                 false, &dividers);
 756                 if (ret)
 757                         return ret;
 758                 clock_table->AclkBreakdownTable.ClkLevel[i].DfsDid =
 759                                                 (uint8_t)dividers.post_divider;
 760
 761                 /* uvd breakdown */
 762                 clock_table->VclkBreakdownTable.ClkLevel[i].GfxVid =
 763                         (i < uvd_table->count) ? (uint8_t)uvd_table->entries[i].v : 0;
 764                 clock_table->VclkBreakdownTable.ClkLevel[i].Frequency =
 765                         (i < uvd_table->count) ? uvd_table->entries[i].vclk : 0;
 766                 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
 767                                 clock_table->VclkBreakdownTable.ClkLevel[i].Frequency,
 768                                 false, &dividers);
 769                 if (ret)
 770                         return ret;
 771                 clock_table->VclkBreakdownTable.ClkLevel[i].DfsDid =
 772                                                 (uint8_t)dividers.post_divider;
 773
 774                 clock_table->DclkBreakdownTable.ClkLevel[i].GfxVid =
 775                         (i < uvd_table->count) ? (uint8_t)uvd_table->entries[i].v : 0;
 776                 clock_table->DclkBreakdownTable.ClkLevel[i].Frequency =
 777                         (i < uvd_table->count) ? uvd_table->entries[i].dclk : 0;
 778                 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
 779                                 clock_table->DclkBreakdownTable.ClkLevel[i].Frequency,
 780                                 false, &dividers);
 781                 if (ret)
 782                         return ret;
 783                 clock_table->DclkBreakdownTable.ClkLevel[i].DfsDid =
 784                                                 (uint8_t)dividers.post_divider;
 785
 786                 /* vce breakdown */
 787                 clock_table->EclkBreakdownTable.ClkLevel[i].GfxVid =
 788                         (i < vce_table->count) ? (uint8_t)vce_table->entries[i].v : 0;
 789                 clock_table->EclkBreakdownTable.ClkLevel[i].Frequency =
 790                         (i < vce_table->count) ? vce_table->entries[i].ecclk : 0;
 791                 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
 792                                 clock_table->EclkBreakdownTable.ClkLevel[i].Frequency,
 793                                 false, &dividers);
 794                 if (ret)
 795                         return ret;
 796                 clock_table->EclkBreakdownTable.ClkLevel[i].DfsDid =
 797                                                 (uint8_t)dividers.post_divider;
 798         }
 799
 800         /* its time to upload to SMU */
 801         ret = cz_smu_upload_pptable(adev);
 802         if (ret) {
 803                 DRM_ERROR("amdgpu: Failed to put power play table to SMU!\n");
 804                 return ret;
 805         }
 806
 807         return 0;
 808 }
 809
 810 static void cz_init_sclk_limit(struct amdgpu_device *adev)
 811 {
 812         struct cz_power_info *pi = cz_get_pi(adev);
 813         struct amdgpu_clock_voltage_dependency_table *table =
 814                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
 815         uint32_t clock = 0, level;
 816
 817         if (!table || !table->count) {
 818                 DRM_ERROR("Invalid Voltage Dependency table.\n");
 819                 return;
 820         }
 821
 822         pi->sclk_dpm.soft_min_clk = 0;
 823         pi->sclk_dpm.hard_min_clk = 0;
 824         cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxSclkLevel);
 825         level = cz_get_argument(adev);
 826         if (level < table->count) {
 827                 clock = table->entries[level].clk;
 828         } else {
 829                 DRM_ERROR("Invalid SLCK Voltage Dependency table entry.\n");
 830                 clock = table->entries[table->count - 1].clk;
 831         }
 832
 833         pi->sclk_dpm.soft_max_clk = clock;
 834         pi->sclk_dpm.hard_max_clk = clock;
 835
 836 }
 837
 838 static void cz_init_uvd_limit(struct amdgpu_device *adev)
 839 {
 840         struct cz_power_info *pi = cz_get_pi(adev);
 841         struct amdgpu_uvd_clock_voltage_dependency_table *table =
 842                 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
 843         uint32_t clock = 0, level;
 844
 845         if (!table || !table->count) {
 846                 DRM_ERROR("Invalid Voltage Dependency table.\n");
 847                 return;
 848         }
 849
 850         pi->uvd_dpm.soft_min_clk = 0;
 851         pi->uvd_dpm.hard_min_clk = 0;
 852         cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxUvdLevel);
 853         level = cz_get_argument(adev);
 854         if (level < table->count) {
 855                 clock = table->entries[level].vclk;
 856         } else {
 857                 DRM_ERROR("Invalid UVD Voltage Dependency table entry.\n");
 858                 clock = table->entries[table->count - 1].vclk;
 859         }
 860
 861         pi->uvd_dpm.soft_max_clk = clock;
 862         pi->uvd_dpm.hard_max_clk = clock;
 863
 864 }
 865
 866 static void cz_init_vce_limit(struct amdgpu_device *adev)
 867 {
 868         struct cz_power_info *pi = cz_get_pi(adev);
 869         struct amdgpu_vce_clock_voltage_dependency_table *table =
 870                 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
 871         uint32_t clock = 0, level;
 872
 873         if (!table || !table->count) {
 874                 DRM_ERROR("Invalid Voltage Dependency table.\n");
 875                 return;
 876         }
 877
 878         pi->vce_dpm.soft_min_clk = table->entries[0].ecclk;
 879         pi->vce_dpm.hard_min_clk = table->entries[0].ecclk;
 880         cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxEclkLevel);
 881         level = cz_get_argument(adev);
 882         if (level < table->count) {
 883                 clock = table->entries[level].ecclk;
 884         } else {
 885                 /* future BIOS would fix this error */
 886                 DRM_ERROR("Invalid VCE Voltage Dependency table entry.\n");
 887                 clock = table->entries[table->count - 1].ecclk;
 888         }
 889
 890         pi->vce_dpm.soft_max_clk = clock;
 891         pi->vce_dpm.hard_max_clk = clock;
 892
 893 }
 894
 895 static void cz_init_acp_limit(struct amdgpu_device *adev)
 896 {
 897         struct cz_power_info *pi = cz_get_pi(adev);
 898         struct amdgpu_clock_voltage_dependency_table *table =
 899                 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
 900         uint32_t clock = 0, level;
 901
 902         if (!table || !table->count) {
 903                 DRM_ERROR("Invalid Voltage Dependency table.\n");
 904                 return;
 905         }
 906
 907         pi->acp_dpm.soft_min_clk = 0;
 908         pi->acp_dpm.hard_min_clk = 0;
 909         cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxAclkLevel);
 910         level = cz_get_argument(adev);
 911         if (level < table->count) {
 912                 clock = table->entries[level].clk;
 913         } else {
 914                 DRM_ERROR("Invalid ACP Voltage Dependency table entry.\n");
 915                 clock = table->entries[table->count - 1].clk;
 916         }
 917
 918         pi->acp_dpm.soft_max_clk = clock;
 919         pi->acp_dpm.hard_max_clk = clock;
 920
 921 }
 922
 923 static void cz_init_pg_state(struct amdgpu_device *adev)
 924 {
 925         struct cz_power_info *pi = cz_get_pi(adev);
 926
 927         pi->uvd_power_gated = false;
 928         pi->vce_power_gated = false;
 929         pi->acp_power_gated = false;
 930
 931 }
 932
 933 static void cz_init_sclk_threshold(struct amdgpu_device *adev)
 934 {
 935         struct cz_power_info *pi = cz_get_pi(adev);
 936
 937         pi->low_sclk_interrupt_threshold = 0;
 938 }
 939
 940 static void cz_dpm_setup_asic(struct amdgpu_device *adev)
 941 {
 942         cz_reset_ap_mask(adev);
 943         cz_dpm_upload_pptable_to_smu(adev);
 944         cz_init_sclk_limit(adev);
 945         cz_init_uvd_limit(adev);
 946         cz_init_vce_limit(adev);
 947         cz_init_acp_limit(adev);
 948         cz_init_pg_state(adev);
 949         cz_init_sclk_threshold(adev);
 950
 951 }
 952
 953 static bool cz_check_smu_feature(struct amdgpu_device *adev,
 954                                 uint32_t feature)
 955 {
 956         uint32_t smu_feature = 0;
 957         int ret;
 958
 959         ret = cz_send_msg_to_smc_with_parameter(adev,
 960                                 PPSMC_MSG_GetFeatureStatus, 0);
 961         if (ret) {
 962                 DRM_ERROR("Failed to get SMU features from SMC.\n");
 963                 return false;
 964         } else {
 965                 smu_feature = cz_get_argument(adev);
 966                 if (feature & smu_feature)
 967                         return true;
 968         }
 969
 970         return false;
 971 }
 972
 973 static bool cz_check_for_dpm_enabled(struct amdgpu_device *adev)
 974 {
 975         if (cz_check_smu_feature(adev,
 976                                 SMU_EnabledFeatureScoreboard_SclkDpmOn))
 977                 return true;
 978
 979         return false;
 980 }
 981
 982 static void cz_program_voting_clients(struct amdgpu_device *adev)
 983 {
 984         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, PPCZ_VOTINGRIGHTSCLIENTS_DFLT0);
 985 }
 986
 987 static void cz_clear_voting_clients(struct amdgpu_device *adev)
 988 {
 989         WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, 0);
 990 }
 991
 992 static int cz_start_dpm(struct amdgpu_device *adev)
 993 {
 994         int ret = 0;
 995
 996         if (amdgpu_dpm) {
 997                 ret = cz_send_msg_to_smc_with_parameter(adev,
 998                                 PPSMC_MSG_EnableAllSmuFeatures, SCLK_DPM_MASK);
 999                 if (ret) {
1000                         DRM_ERROR("SMU feature: SCLK_DPM enable failed\n");
1001                         return -EINVAL;
1002                 }
1003         }
1004
1005         return 0;
1006 }
1007
1008 static int cz_stop_dpm(struct amdgpu_device *adev)
1009 {
1010         int ret = 0;
1011
1012         if (amdgpu_dpm && adev->pm.dpm_enabled) {
1013                 ret = cz_send_msg_to_smc_with_parameter(adev,
1014                                 PPSMC_MSG_DisableAllSmuFeatures, SCLK_DPM_MASK);
1015                 if (ret) {
1016                         DRM_ERROR("SMU feature: SCLK_DPM disable failed\n");
1017                         return -EINVAL;
1018                 }
1019         }
1020
1021         return 0;
1022 }
1023
1024 static uint32_t cz_get_sclk_level(struct amdgpu_device *adev,
1025                                 uint32_t clock, uint16_t msg)
1026 {
1027         int i = 0;
1028         struct amdgpu_clock_voltage_dependency_table *table =
1029                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1030
1031         switch (msg) {
1032         case PPSMC_MSG_SetSclkSoftMin:
1033         case PPSMC_MSG_SetSclkHardMin:
1034                 for (i = 0; i < table->count; i++)
1035                         if (clock <= table->entries[i].clk)
1036                                 break;
1037                 if (i == table->count)
1038                         i = table->count - 1;
1039                 break;
1040         case PPSMC_MSG_SetSclkSoftMax:
1041         case PPSMC_MSG_SetSclkHardMax:
1042                 for (i = table->count - 1; i >= 0; i--)
1043                         if (clock >= table->entries[i].clk)
1044                                 break;
1045                 if (i < 0)
1046                         i = 0;
1047                 break;
1048         default:
1049                 break;
1050         }
1051
1052         return i;
1053 }
1054
1055 static uint32_t cz_get_eclk_level(struct amdgpu_device *adev,
1056                                 uint32_t clock, uint16_t msg)
1057 {
1058         int i = 0;
1059         struct amdgpu_vce_clock_voltage_dependency_table *table =
1060                 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1061
1062         if (table->count == 0)
1063                 return 0;
1064
1065         switch (msg) {
1066         case PPSMC_MSG_SetEclkSoftMin:
1067         case PPSMC_MSG_SetEclkHardMin:
1068                 for (i = 0; i < table->count-1; i++)
1069                         if (clock <= table->entries[i].ecclk)
1070                                 break;
1071                 break;
1072         case PPSMC_MSG_SetEclkSoftMax:
1073         case PPSMC_MSG_SetEclkHardMax:
1074                 for (i = table->count - 1; i > 0; i--)
1075                         if (clock >= table->entries[i].ecclk)
1076                                 break;
1077                 break;
1078         default:
1079                 break;
1080         }
1081
1082         return i;
1083 }
1084
1085 static uint32_t cz_get_uvd_level(struct amdgpu_device *adev,
1086                                  uint32_t clock, uint16_t msg)
1087 {
1088         int i = 0;
1089         struct amdgpu_uvd_clock_voltage_dependency_table *table =
1090                 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
1091
1092         switch (msg) {
1093         case PPSMC_MSG_SetUvdSoftMin:
1094         case PPSMC_MSG_SetUvdHardMin:
1095                 for (i = 0; i < table->count; i++)
1096                         if (clock <= table->entries[i].vclk)
1097                                 break;
1098                 if (i == table->count)
1099                         i = table->count - 1;
1100                 break;
1101         case PPSMC_MSG_SetUvdSoftMax:
1102         case PPSMC_MSG_SetUvdHardMax:
1103                 for (i = table->count - 1; i >= 0; i--)
1104                         if (clock >= table->entries[i].vclk)
1105                                 break;
1106                 if (i < 0)
1107                         i = 0;
1108                 break;
1109         default:
1110                 break;
1111         }
1112
1113         return i;
1114 }
1115
1116 static int cz_program_bootup_state(struct amdgpu_device *adev)
1117 {
1118         struct cz_power_info *pi = cz_get_pi(adev);
1119         uint32_t soft_min_clk = 0;
1120         uint32_t soft_max_clk = 0;
1121         int ret = 0;
1122
1123         pi->sclk_dpm.soft_min_clk = pi->sys_info.bootup_sclk;
1124         pi->sclk_dpm.soft_max_clk = pi->sys_info.bootup_sclk;
1125
1126         soft_min_clk = cz_get_sclk_level(adev,
1127                                 pi->sclk_dpm.soft_min_clk,
1128                                 PPSMC_MSG_SetSclkSoftMin);
1129         soft_max_clk = cz_get_sclk_level(adev,
1130                                 pi->sclk_dpm.soft_max_clk,
1131                                 PPSMC_MSG_SetSclkSoftMax);
1132
1133         ret = cz_send_msg_to_smc_with_parameter(adev,
1134                                 PPSMC_MSG_SetSclkSoftMin, soft_min_clk);
1135         if (ret)
1136                 return -EINVAL;
1137
1138         ret = cz_send_msg_to_smc_with_parameter(adev,
1139                                 PPSMC_MSG_SetSclkSoftMax, soft_max_clk);
1140         if (ret)
1141                 return -EINVAL;
1142
1143         return 0;
1144 }
1145
1146 /* TODO */
1147 static int cz_disable_cgpg(struct amdgpu_device *adev)
1148 {
1149         return 0;
1150 }
1151
1152 /* TODO */
1153 static int cz_enable_cgpg(struct amdgpu_device *adev)
1154 {
1155         return 0;
1156 }
1157
1158 /* TODO */
1159 static int cz_program_pt_config_registers(struct amdgpu_device *adev)
1160 {
1161         return 0;
1162 }
1163
1164 static void cz_do_enable_didt(struct amdgpu_device *adev, bool enable)
1165 {
1166         struct cz_power_info *pi = cz_get_pi(adev);
1167         uint32_t reg = 0;
1168
1169         if (pi->caps_sq_ramping) {
1170                 reg = RREG32_DIDT(ixDIDT_SQ_CTRL0);
1171                 if (enable)
1172                         reg = REG_SET_FIELD(reg, DIDT_SQ_CTRL0, DIDT_CTRL_EN, 1);
1173                 else
1174                         reg = REG_SET_FIELD(reg, DIDT_SQ_CTRL0, DIDT_CTRL_EN, 0);
1175                 WREG32_DIDT(ixDIDT_SQ_CTRL0, reg);
1176         }
1177         if (pi->caps_db_ramping) {
1178                 reg = RREG32_DIDT(ixDIDT_DB_CTRL0);
1179                 if (enable)
1180                         reg = REG_SET_FIELD(reg, DIDT_DB_CTRL0, DIDT_CTRL_EN, 1);
1181                 else
1182                         reg = REG_SET_FIELD(reg, DIDT_DB_CTRL0, DIDT_CTRL_EN, 0);
1183                 WREG32_DIDT(ixDIDT_DB_CTRL0, reg);
1184         }
1185         if (pi->caps_td_ramping) {
1186                 reg = RREG32_DIDT(ixDIDT_TD_CTRL0);
1187                 if (enable)
1188                         reg = REG_SET_FIELD(reg, DIDT_TD_CTRL0, DIDT_CTRL_EN, 1);
1189                 else
1190                         reg = REG_SET_FIELD(reg, DIDT_TD_CTRL0, DIDT_CTRL_EN, 0);
1191                 WREG32_DIDT(ixDIDT_TD_CTRL0, reg);
1192         }
1193         if (pi->caps_tcp_ramping) {
1194                 reg = RREG32_DIDT(ixDIDT_TCP_CTRL0);
1195                 if (enable)
1196                         reg = REG_SET_FIELD(reg, DIDT_SQ_CTRL0, DIDT_CTRL_EN, 1);
1197                 else
1198                         reg = REG_SET_FIELD(reg, DIDT_SQ_CTRL0, DIDT_CTRL_EN, 0);
1199                 WREG32_DIDT(ixDIDT_TCP_CTRL0, reg);
1200         }
1201
1202 }
1203
1204 static int cz_enable_didt(struct amdgpu_device *adev, bool enable)
1205 {
1206         struct cz_power_info *pi = cz_get_pi(adev);
1207         int ret;
1208
1209         if (pi->caps_sq_ramping || pi->caps_db_ramping ||
1210             pi->caps_td_ramping || pi->caps_tcp_ramping) {
1211                 if (adev->gfx.gfx_current_status != AMDGPU_GFX_SAFE_MODE) {
1212                         ret = cz_disable_cgpg(adev);
1213                         if (ret) {
1214                                 DRM_ERROR("Pre Di/Dt disable cg/pg failed\n");
1215                                 return -EINVAL;
1216                         }
1217                         adev->gfx.gfx_current_status = AMDGPU_GFX_SAFE_MODE;
1218                 }
1219
1220                 ret = cz_program_pt_config_registers(adev);
1221                 if (ret) {
1222                         DRM_ERROR("Di/Dt config failed\n");
1223                         return -EINVAL;
1224                 }
1225                 cz_do_enable_didt(adev, enable);
1226
1227                 if (adev->gfx.gfx_current_status == AMDGPU_GFX_SAFE_MODE) {
1228                         ret = cz_enable_cgpg(adev);
1229                         if (ret) {
1230                                 DRM_ERROR("Post Di/Dt enable cg/pg failed\n");
1231                                 return -EINVAL;
1232                         }
1233                         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1234                 }
1235         }
1236
1237         return 0;
1238 }
1239
1240 /* TODO */
1241 static void cz_reset_acp_boot_level(struct amdgpu_device *adev)
1242 {
1243 }
1244
1245 static void cz_update_current_ps(struct amdgpu_device *adev,
1246                                         struct amdgpu_ps *rps)
1247 {
1248         struct cz_power_info *pi = cz_get_pi(adev);
1249         struct cz_ps *ps = cz_get_ps(rps);
1250
1251         pi->current_ps = *ps;
1252         pi->current_rps = *rps;
1253         pi->current_rps.ps_priv = ps;
1254
1255 }
1256
1257 static void cz_update_requested_ps(struct amdgpu_device *adev,
1258                                         struct amdgpu_ps *rps)
1259 {
1260         struct cz_power_info *pi = cz_get_pi(adev);
1261         struct cz_ps *ps = cz_get_ps(rps);
1262
1263         pi->requested_ps = *ps;
1264         pi->requested_rps = *rps;
1265         pi->requested_rps.ps_priv = ps;
1266
1267 }
1268
1269 /* PP arbiter support needed TODO */
1270 static void cz_apply_state_adjust_rules(struct amdgpu_device *adev,
1271                                         struct amdgpu_ps *new_rps,
1272                                         struct amdgpu_ps *old_rps)
1273 {
1274         struct cz_ps *ps = cz_get_ps(new_rps);
1275         struct cz_power_info *pi = cz_get_pi(adev);
1276         struct amdgpu_clock_and_voltage_limits *limits =
1277                 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
1278         /* 10kHz memory clock */
1279         uint32_t mclk = 0;
1280
1281         ps->force_high = false;
1282         ps->need_dfs_bypass = true;
1283         pi->video_start = new_rps->dclk || new_rps->vclk ||
1284                           new_rps->evclk || new_rps->ecclk;
1285
1286         if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
1287                         ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
1288                 pi->battery_state = true;
1289         else
1290                 pi->battery_state = false;
1291
1292         if (pi->caps_stable_power_state)
1293                 mclk = limits->mclk;
1294
1295         if (mclk > pi->sys_info.nbp_memory_clock[CZ_NUM_NBPMEMORY_CLOCK - 1])
1296                 ps->force_high = true;
1297
1298 }
1299
1300 static int cz_dpm_enable(struct amdgpu_device *adev)
1301 {
1302         const char *chip_name;
1303         int ret = 0;
1304
1305         /* renable will hang up SMU, so check first */
1306         if (cz_check_for_dpm_enabled(adev))
1307                 return -EINVAL;
1308
1309         cz_program_voting_clients(adev);
1310
1311         switch (adev->asic_type) {
1312         case CHIP_CARRIZO:
1313                 chip_name = "carrizo";
1314                 break;
1315         case CHIP_STONEY:
1316                 chip_name = "stoney";
1317                 break;
1318         default:
1319                 BUG();
1320         }
1321
1322
1323         ret = cz_start_dpm(adev);
1324         if (ret) {
1325                 DRM_ERROR("%s DPM enable failed\n", chip_name);
1326                 return -EINVAL;
1327         }
1328
1329         ret = cz_program_bootup_state(adev);
1330         if (ret) {
1331                 DRM_ERROR("%s bootup state program failed\n", chip_name);
1332                 return -EINVAL;
1333         }
1334
1335         ret = cz_enable_didt(adev, true);
1336         if (ret) {
1337                 DRM_ERROR("%s enable di/dt failed\n", chip_name);
1338                 return -EINVAL;
1339         }
1340
1341         cz_reset_acp_boot_level(adev);
1342         cz_update_current_ps(adev, adev->pm.dpm.boot_ps);
1343
1344         return 0;
1345 }
1346
1347 static int cz_dpm_hw_init(void *handle)
1348 {
1349         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1350         int ret = 0;
1351
1352         mutex_lock(&adev->pm.mutex);
1353
1354         /* smu init only needs to be called at startup, not resume.
1355          * It should be in sw_init, but requires the fw info gathered
1356          * in sw_init from other IP modules.
1357          */
1358         ret = cz_smu_init(adev);
1359         if (ret) {
1360                 DRM_ERROR("amdgpu: smc initialization failed\n");
1361                 mutex_unlock(&adev->pm.mutex);
1362                 return ret;
1363         }
1364
1365         /* do the actual fw loading */
1366         ret = cz_smu_start(adev);
1367         if (ret) {
1368                 DRM_ERROR("amdgpu: smc start failed\n");
1369                 mutex_unlock(&adev->pm.mutex);
1370                 return ret;
1371         }
1372
1373         if (!amdgpu_dpm) {
1374                 adev->pm.dpm_enabled = false;
1375                 mutex_unlock(&adev->pm.mutex);
1376                 return ret;
1377         }
1378
1379         /* cz dpm setup asic */
1380         cz_dpm_setup_asic(adev);
1381
1382         /* cz dpm enable */
1383         ret = cz_dpm_enable(adev);
1384         if (ret)
1385                 adev->pm.dpm_enabled = false;
1386         else
1387                 adev->pm.dpm_enabled = true;
1388
1389         mutex_unlock(&adev->pm.mutex);
1390
1391         return 0;
1392 }
1393
1394 static int cz_dpm_disable(struct amdgpu_device *adev)
1395 {
1396         int ret = 0;
1397
1398         if (!cz_check_for_dpm_enabled(adev))
1399                 return -EINVAL;
1400
1401         ret = cz_enable_didt(adev, false);
1402         if (ret) {
1403                 DRM_ERROR("disable di/dt failed\n");
1404                 return -EINVAL;
1405         }
1406
1407         /* powerup blocks */
1408         cz_dpm_powergate_uvd(adev, false);
1409         cz_dpm_powergate_vce(adev, false);
1410
1411         cz_clear_voting_clients(adev);
1412         cz_stop_dpm(adev);
1413         cz_update_current_ps(adev, adev->pm.dpm.boot_ps);
1414
1415         return 0;
1416 }
1417
1418 static int cz_dpm_hw_fini(void *handle)
1419 {
1420         int ret = 0;
1421         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1422
1423         mutex_lock(&adev->pm.mutex);
1424
1425         /* smu fini only needs to be called at teardown, not suspend.
1426          * It should be in sw_fini, but we put it here for symmetry
1427          * with smu init.
1428          */
1429         cz_smu_fini(adev);
1430
1431         if (adev->pm.dpm_enabled) {
1432                 ret = cz_dpm_disable(adev);
1433
1434                 adev->pm.dpm.current_ps =
1435                         adev->pm.dpm.requested_ps =
1436                         adev->pm.dpm.boot_ps;
1437         }
1438
1439         adev->pm.dpm_enabled = false;
1440
1441         mutex_unlock(&adev->pm.mutex);
1442
1443         return ret;
1444 }
1445
1446 static int cz_dpm_suspend(void *handle)
1447 {
1448         int ret = 0;
1449         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1450
1451         if (adev->pm.dpm_enabled) {
1452                 mutex_lock(&adev->pm.mutex);
1453
1454                 ret = cz_dpm_disable(adev);
1455
1456                 adev->pm.dpm.current_ps =
1457                         adev->pm.dpm.requested_ps =
1458                         adev->pm.dpm.boot_ps;
1459
1460                 mutex_unlock(&adev->pm.mutex);
1461         }
1462
1463         return ret;
1464 }
1465
1466 static int cz_dpm_resume(void *handle)
1467 {
1468         int ret = 0;
1469         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1470
1471         mutex_lock(&adev->pm.mutex);
1472
1473         /* do the actual fw loading */
1474         ret = cz_smu_start(adev);
1475         if (ret) {
1476                 DRM_ERROR("amdgpu: smc start failed\n");
1477                 mutex_unlock(&adev->pm.mutex);
1478                 return ret;
1479         }
1480
1481         if (!amdgpu_dpm) {
1482                 adev->pm.dpm_enabled = false;
1483                 mutex_unlock(&adev->pm.mutex);
1484                 return ret;
1485         }
1486
1487         /* cz dpm setup asic */
1488         cz_dpm_setup_asic(adev);
1489
1490         /* cz dpm enable */
1491         ret = cz_dpm_enable(adev);
1492         if (ret)
1493                 adev->pm.dpm_enabled = false;
1494         else
1495                 adev->pm.dpm_enabled = true;
1496
1497         mutex_unlock(&adev->pm.mutex);
1498         /* upon resume, re-compute the clocks */
1499         if (adev->pm.dpm_enabled)
1500                 amdgpu_pm_compute_clocks(adev);
1501
1502         return 0;
1503 }
1504
1505 static int cz_dpm_set_clockgating_state(void *handle,
1506                                         enum amd_clockgating_state state)
1507 {
1508         return 0;
1509 }
1510
1511 static int cz_dpm_set_powergating_state(void *handle,
1512                                         enum amd_powergating_state state)
1513 {
1514         return 0;
1515 }
1516
1517 static int cz_dpm_get_temperature(struct amdgpu_device *adev)
1518 {
1519         int actual_temp = 0;
1520         uint32_t val = RREG32_SMC(ixTHM_TCON_CUR_TMP);
1521         uint32_t temp = REG_GET_FIELD(val, THM_TCON_CUR_TMP, CUR_TEMP);
1522
1523         if (REG_GET_FIELD(val, THM_TCON_CUR_TMP, CUR_TEMP_RANGE_SEL))
1524                 actual_temp = 1000 * ((temp / 8) - 49);
1525         else
1526                 actual_temp = 1000 * (temp / 8);
1527
1528         return actual_temp;
1529 }
1530
1531 static int cz_dpm_pre_set_power_state(struct amdgpu_device *adev)
1532 {
1533         struct cz_power_info *pi = cz_get_pi(adev);
1534         struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
1535         struct amdgpu_ps *new_ps = &requested_ps;
1536
1537         cz_update_requested_ps(adev, new_ps);
1538         cz_apply_state_adjust_rules(adev, &pi->requested_rps,
1539                                         &pi->current_rps);
1540
1541         return 0;
1542 }
1543
1544 static int cz_dpm_update_sclk_limit(struct amdgpu_device *adev)
1545 {
1546         struct cz_power_info *pi = cz_get_pi(adev);
1547         struct amdgpu_clock_and_voltage_limits *limits =
1548                 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
1549         uint32_t clock, stable_ps_clock = 0;
1550
1551         clock = pi->sclk_dpm.soft_min_clk;
1552
1553         if (pi->caps_stable_power_state) {
1554                 stable_ps_clock = limits->sclk * 75 / 100;
1555                 if (clock < stable_ps_clock)
1556                         clock = stable_ps_clock;
1557         }
1558
1559         if (clock != pi->sclk_dpm.soft_min_clk) {
1560                 pi->sclk_dpm.soft_min_clk = clock;
1561                 cz_send_msg_to_smc_with_parameter(adev,
1562                                 PPSMC_MSG_SetSclkSoftMin,
1563                                 cz_get_sclk_level(adev, clock,
1564                                         PPSMC_MSG_SetSclkSoftMin));
1565         }
1566
1567         if (pi->caps_stable_power_state &&
1568                         pi->sclk_dpm.soft_max_clk != clock) {
1569                 pi->sclk_dpm.soft_max_clk = clock;
1570                 cz_send_msg_to_smc_with_parameter(adev,
1571                                 PPSMC_MSG_SetSclkSoftMax,
1572                                 cz_get_sclk_level(adev, clock,
1573                                         PPSMC_MSG_SetSclkSoftMax));
1574         } else {
1575                 cz_send_msg_to_smc_with_parameter(adev,
1576                                 PPSMC_MSG_SetSclkSoftMax,
1577                                 cz_get_sclk_level(adev,
1578                                         pi->sclk_dpm.soft_max_clk,
1579                                         PPSMC_MSG_SetSclkSoftMax));
1580         }
1581
1582         return 0;
1583 }
1584
1585 static int cz_dpm_set_deep_sleep_sclk_threshold(struct amdgpu_device *adev)
1586 {
1587         struct cz_power_info *pi = cz_get_pi(adev);
1588
1589         if (pi->caps_sclk_ds) {
1590                 cz_send_msg_to_smc_with_parameter(adev,
1591                                 PPSMC_MSG_SetMinDeepSleepSclk,
1592                                 CZ_MIN_DEEP_SLEEP_SCLK);
1593         }
1594
1595         return 0;
1596 }
1597
1598 /* ?? without dal support, is this still needed in setpowerstate list*/
1599 static int cz_dpm_set_watermark_threshold(struct amdgpu_device *adev)
1600 {
1601         struct cz_power_info *pi = cz_get_pi(adev);
1602
1603         cz_send_msg_to_smc_with_parameter(adev,
1604                         PPSMC_MSG_SetWatermarkFrequency,
1605                         pi->sclk_dpm.soft_max_clk);
1606
1607         return 0;
1608 }
1609
1610 static int cz_dpm_enable_nbdpm(struct amdgpu_device *adev)
1611 {
1612         int ret = 0;
1613         struct cz_power_info *pi = cz_get_pi(adev);
1614
1615         /* also depend on dal NBPStateDisableRequired */
1616         if (pi->nb_dpm_enabled_by_driver && !pi->nb_dpm_enabled) {
1617                 ret = cz_send_msg_to_smc_with_parameter(adev,
1618                                 PPSMC_MSG_EnableAllSmuFeatures,
1619                                 NB_DPM_MASK);
1620                 if (ret) {
1621                         DRM_ERROR("amdgpu: nb dpm enable failed\n");
1622                         return ret;
1623                 }
1624                 pi->nb_dpm_enabled = true;
1625         }
1626
1627         return ret;
1628 }
1629
1630 static void cz_dpm_nbdpm_lm_pstate_enable(struct amdgpu_device *adev,
1631                                                         bool enable)
1632 {
1633         if (enable)
1634                 cz_send_msg_to_smc(adev, PPSMC_MSG_EnableLowMemoryPstate);
1635         else
1636                 cz_send_msg_to_smc(adev, PPSMC_MSG_DisableLowMemoryPstate);
1637
1638 }
1639
1640 static int cz_dpm_update_low_memory_pstate(struct amdgpu_device *adev)
1641 {
1642         struct cz_power_info *pi = cz_get_pi(adev);
1643         struct cz_ps *ps = &pi->requested_ps;
1644
1645         if (pi->sys_info.nb_dpm_enable) {
1646                 if (ps->force_high)
1647                         cz_dpm_nbdpm_lm_pstate_enable(adev, false);
1648                 else
1649                         cz_dpm_nbdpm_lm_pstate_enable(adev, true);
1650         }
1651
1652         return 0;
1653 }
1654
1655 /* with dpm enabled */
1656 static int cz_dpm_set_power_state(struct amdgpu_device *adev)
1657 {
1658         cz_dpm_update_sclk_limit(adev);
1659         cz_dpm_set_deep_sleep_sclk_threshold(adev);
1660         cz_dpm_set_watermark_threshold(adev);
1661         cz_dpm_enable_nbdpm(adev);
1662         cz_dpm_update_low_memory_pstate(adev);
1663
1664         return 0;
1665 }
1666
1667 static void cz_dpm_post_set_power_state(struct amdgpu_device *adev)
1668 {
1669         struct cz_power_info *pi = cz_get_pi(adev);
1670         struct amdgpu_ps *ps = &pi->requested_rps;
1671
1672         cz_update_current_ps(adev, ps);
1673 }
1674
1675 static int cz_dpm_force_highest(struct amdgpu_device *adev)
1676 {
1677         struct cz_power_info *pi = cz_get_pi(adev);
1678         int ret = 0;
1679
1680         if (pi->sclk_dpm.soft_min_clk != pi->sclk_dpm.soft_max_clk) {
1681                 pi->sclk_dpm.soft_min_clk =
1682                         pi->sclk_dpm.soft_max_clk;
1683                 ret = cz_send_msg_to_smc_with_parameter(adev,
1684                                 PPSMC_MSG_SetSclkSoftMin,
1685                                 cz_get_sclk_level(adev,
1686                                         pi->sclk_dpm.soft_min_clk,
1687                                         PPSMC_MSG_SetSclkSoftMin));
1688                 if (ret)
1689                         return ret;
1690         }
1691
1692         return ret;
1693 }
1694
1695 static int cz_dpm_force_lowest(struct amdgpu_device *adev)
1696 {
1697         struct cz_power_info *pi = cz_get_pi(adev);
1698         int ret = 0;
1699
1700         if (pi->sclk_dpm.soft_max_clk != pi->sclk_dpm.soft_min_clk) {
1701                 pi->sclk_dpm.soft_max_clk = pi->sclk_dpm.soft_min_clk;
1702                 ret = cz_send_msg_to_smc_with_parameter(adev,
1703                                 PPSMC_MSG_SetSclkSoftMax,
1704                                 cz_get_sclk_level(adev,
1705                                         pi->sclk_dpm.soft_max_clk,
1706                                         PPSMC_MSG_SetSclkSoftMax));
1707                 if (ret)
1708                         return ret;
1709         }
1710
1711         return ret;
1712 }
1713
1714 static uint32_t cz_dpm_get_max_sclk_level(struct amdgpu_device *adev)
1715 {
1716         struct cz_power_info *pi = cz_get_pi(adev);
1717
1718         if (!pi->max_sclk_level) {
1719                 cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxSclkLevel);
1720                 pi->max_sclk_level = cz_get_argument(adev) + 1;
1721         }
1722
1723         if (pi->max_sclk_level > CZ_MAX_HARDWARE_POWERLEVELS) {
1724                 DRM_ERROR("Invalid max sclk level!\n");
1725                 return -EINVAL;
1726         }
1727
1728         return pi->max_sclk_level;
1729 }
1730
1731 static int cz_dpm_unforce_dpm_levels(struct amdgpu_device *adev)
1732 {
1733         struct cz_power_info *pi = cz_get_pi(adev);
1734         struct amdgpu_clock_voltage_dependency_table *dep_table =
1735                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1736         uint32_t level = 0;
1737         int ret = 0;
1738
1739         pi->sclk_dpm.soft_min_clk = dep_table->entries[0].clk;
1740         level = cz_dpm_get_max_sclk_level(adev) - 1;
1741         if (level < dep_table->count)
1742                 pi->sclk_dpm.soft_max_clk = dep_table->entries[level].clk;
1743         else
1744                 pi->sclk_dpm.soft_max_clk =
1745                         dep_table->entries[dep_table->count - 1].clk;
1746
1747         /* get min/max sclk soft value
1748          * notify SMU to execute */
1749         ret = cz_send_msg_to_smc_with_parameter(adev,
1750                                 PPSMC_MSG_SetSclkSoftMin,
1751                                 cz_get_sclk_level(adev,
1752                                         pi->sclk_dpm.soft_min_clk,
1753                                         PPSMC_MSG_SetSclkSoftMin));
1754         if (ret)
1755                 return ret;
1756
1757         ret = cz_send_msg_to_smc_with_parameter(adev,
1758                                 PPSMC_MSG_SetSclkSoftMax,
1759                                 cz_get_sclk_level(adev,
1760                                         pi->sclk_dpm.soft_max_clk,
1761                                         PPSMC_MSG_SetSclkSoftMax));
1762         if (ret)
1763                 return ret;
1764
1765         DRM_DEBUG("DPM unforce state min=%d, max=%d.\n",
1766                   pi->sclk_dpm.soft_min_clk,
1767                   pi->sclk_dpm.soft_max_clk);
1768
1769         return 0;
1770 }
1771
1772 static int cz_dpm_uvd_force_highest(struct amdgpu_device *adev)
1773 {
1774         struct cz_power_info *pi = cz_get_pi(adev);
1775         int ret = 0;
1776
1777         if (pi->uvd_dpm.soft_min_clk != pi->uvd_dpm.soft_max_clk) {
1778                 pi->uvd_dpm.soft_min_clk =
1779                         pi->uvd_dpm.soft_max_clk;
1780                 ret = cz_send_msg_to_smc_with_parameter(adev,
1781                                 PPSMC_MSG_SetUvdSoftMin,
1782                                 cz_get_uvd_level(adev,
1783                                         pi->uvd_dpm.soft_min_clk,
1784                                         PPSMC_MSG_SetUvdSoftMin));
1785                 if (ret)
1786                         return ret;
1787         }
1788
1789         return ret;
1790 }
1791
1792 static int cz_dpm_uvd_force_lowest(struct amdgpu_device *adev)
1793 {
1794         struct cz_power_info *pi = cz_get_pi(adev);
1795         int ret = 0;
1796
1797         if (pi->uvd_dpm.soft_max_clk != pi->uvd_dpm.soft_min_clk) {
1798                 pi->uvd_dpm.soft_max_clk = pi->uvd_dpm.soft_min_clk;
1799                 ret = cz_send_msg_to_smc_with_parameter(adev,
1800                                 PPSMC_MSG_SetUvdSoftMax,
1801                                 cz_get_uvd_level(adev,
1802                                         pi->uvd_dpm.soft_max_clk,
1803                                         PPSMC_MSG_SetUvdSoftMax));
1804                 if (ret)
1805                         return ret;
1806         }
1807
1808         return ret;
1809 }
1810
1811 static uint32_t cz_dpm_get_max_uvd_level(struct amdgpu_device *adev)
1812 {
1813         struct cz_power_info *pi = cz_get_pi(adev);
1814
1815         if (!pi->max_uvd_level) {
1816                 cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxUvdLevel);
1817                 pi->max_uvd_level = cz_get_argument(adev) + 1;
1818         }
1819
1820         if (pi->max_uvd_level > CZ_MAX_HARDWARE_POWERLEVELS) {
1821                 DRM_ERROR("Invalid max uvd level!\n");
1822                 return -EINVAL;
1823         }
1824
1825         return pi->max_uvd_level;
1826 }
1827
1828 static int cz_dpm_unforce_uvd_dpm_levels(struct amdgpu_device *adev)
1829 {
1830         struct cz_power_info *pi = cz_get_pi(adev);
1831         struct amdgpu_uvd_clock_voltage_dependency_table *dep_table =
1832                 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
1833         uint32_t level = 0;
1834         int ret = 0;
1835
1836         pi->uvd_dpm.soft_min_clk = dep_table->entries[0].vclk;
1837         level = cz_dpm_get_max_uvd_level(adev) - 1;
1838         if (level < dep_table->count)
1839                 pi->uvd_dpm.soft_max_clk = dep_table->entries[level].vclk;
1840         else
1841                 pi->uvd_dpm.soft_max_clk =
1842                         dep_table->entries[dep_table->count - 1].vclk;
1843
1844         /* get min/max sclk soft value
1845          * notify SMU to execute */
1846         ret = cz_send_msg_to_smc_with_parameter(adev,
1847                                 PPSMC_MSG_SetUvdSoftMin,
1848                                 cz_get_uvd_level(adev,
1849                                         pi->uvd_dpm.soft_min_clk,
1850                                         PPSMC_MSG_SetUvdSoftMin));
1851         if (ret)
1852                 return ret;
1853
1854         ret = cz_send_msg_to_smc_with_parameter(adev,
1855                                 PPSMC_MSG_SetUvdSoftMax,
1856                                 cz_get_uvd_level(adev,
1857                                         pi->uvd_dpm.soft_max_clk,
1858                                         PPSMC_MSG_SetUvdSoftMax));
1859         if (ret)
1860                 return ret;
1861
1862         DRM_DEBUG("DPM uvd unforce state min=%d, max=%d.\n",
1863                   pi->uvd_dpm.soft_min_clk,
1864                   pi->uvd_dpm.soft_max_clk);
1865
1866         return 0;
1867 }
1868
1869 static int cz_dpm_vce_force_highest(struct amdgpu_device *adev)
1870 {
1871         struct cz_power_info *pi = cz_get_pi(adev);
1872         int ret = 0;
1873
1874         if (pi->vce_dpm.soft_min_clk != pi->vce_dpm.soft_max_clk) {
1875                 pi->vce_dpm.soft_min_clk =
1876                         pi->vce_dpm.soft_max_clk;
1877                 ret = cz_send_msg_to_smc_with_parameter(adev,
1878                                 PPSMC_MSG_SetEclkSoftMin,
1879                                 cz_get_eclk_level(adev,
1880                                         pi->vce_dpm.soft_min_clk,
1881                                         PPSMC_MSG_SetEclkSoftMin));
1882                 if (ret)
1883                         return ret;
1884         }
1885
1886         return ret;
1887 }
1888
1889 static int cz_dpm_vce_force_lowest(struct amdgpu_device *adev)
1890 {
1891         struct cz_power_info *pi = cz_get_pi(adev);
1892         int ret = 0;
1893
1894         if (pi->vce_dpm.soft_max_clk != pi->vce_dpm.soft_min_clk) {
1895                 pi->vce_dpm.soft_max_clk = pi->vce_dpm.soft_min_clk;
1896                 ret = cz_send_msg_to_smc_with_parameter(adev,
1897                                 PPSMC_MSG_SetEclkSoftMax,
1898                                 cz_get_uvd_level(adev,
1899                                         pi->vce_dpm.soft_max_clk,
1900                                         PPSMC_MSG_SetEclkSoftMax));
1901                 if (ret)
1902                         return ret;
1903         }
1904
1905         return ret;
1906 }
1907
1908 static uint32_t cz_dpm_get_max_vce_level(struct amdgpu_device *adev)
1909 {
1910         struct cz_power_info *pi = cz_get_pi(adev);
1911
1912         if (!pi->max_vce_level) {
1913                 cz_send_msg_to_smc(adev, PPSMC_MSG_GetMaxEclkLevel);
1914                 pi->max_vce_level = cz_get_argument(adev) + 1;
1915         }
1916
1917         if (pi->max_vce_level > CZ_MAX_HARDWARE_POWERLEVELS) {
1918                 DRM_ERROR("Invalid max vce level!\n");
1919                 return -EINVAL;
1920         }
1921
1922         return pi->max_vce_level;
1923 }
1924
1925 static int cz_dpm_unforce_vce_dpm_levels(struct amdgpu_device *adev)
1926 {
1927         struct cz_power_info *pi = cz_get_pi(adev);
1928         struct amdgpu_vce_clock_voltage_dependency_table *dep_table =
1929                 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1930         uint32_t level = 0;
1931         int ret = 0;
1932
1933         pi->vce_dpm.soft_min_clk = dep_table->entries[0].ecclk;
1934         level = cz_dpm_get_max_vce_level(adev) - 1;
1935         if (level < dep_table->count)
1936                 pi->vce_dpm.soft_max_clk = dep_table->entries[level].ecclk;
1937         else
1938                 pi->vce_dpm.soft_max_clk =
1939                         dep_table->entries[dep_table->count - 1].ecclk;
1940
1941         /* get min/max sclk soft value
1942          * notify SMU to execute */
1943         ret = cz_send_msg_to_smc_with_parameter(adev,
1944                                 PPSMC_MSG_SetEclkSoftMin,
1945                                 cz_get_eclk_level(adev,
1946                                         pi->vce_dpm.soft_min_clk,
1947                                         PPSMC_MSG_SetEclkSoftMin));
1948         if (ret)
1949                 return ret;
1950
1951         ret = cz_send_msg_to_smc_with_parameter(adev,
1952                                 PPSMC_MSG_SetEclkSoftMax,
1953                                 cz_get_eclk_level(adev,
1954                                         pi->vce_dpm.soft_max_clk,
1955                                         PPSMC_MSG_SetEclkSoftMax));
1956         if (ret)
1957                 return ret;
1958
1959         DRM_DEBUG("DPM vce unforce state min=%d, max=%d.\n",
1960                   pi->vce_dpm.soft_min_clk,
1961                   pi->vce_dpm.soft_max_clk);
1962
1963         return 0;
1964 }
1965
1966 static int cz_dpm_force_dpm_level(struct amdgpu_device *adev,
1967                                   enum amdgpu_dpm_forced_level level)
1968 {
1969         int ret = 0;
1970
1971         switch (level) {
1972         case AMDGPU_DPM_FORCED_LEVEL_HIGH:
1973                 /* sclk */
1974                 ret = cz_dpm_unforce_dpm_levels(adev);
1975                 if (ret)
1976                         return ret;
1977                 ret = cz_dpm_force_highest(adev);
1978                 if (ret)
1979                         return ret;
1980
1981                 /* uvd */
1982                 ret = cz_dpm_unforce_uvd_dpm_levels(adev);
1983                 if (ret)
1984                         return ret;
1985                 ret = cz_dpm_uvd_force_highest(adev);
1986                 if (ret)
1987                         return ret;
1988
1989                 /* vce */
1990                 ret = cz_dpm_unforce_vce_dpm_levels(adev);
1991                 if (ret)
1992                         return ret;
1993                 ret = cz_dpm_vce_force_highest(adev);
1994                 if (ret)
1995                         return ret;
1996                 break;
1997         case AMDGPU_DPM_FORCED_LEVEL_LOW:
1998                 /* sclk */
1999                 ret = cz_dpm_unforce_dpm_levels(adev);
2000                 if (ret)
2001                         return ret;
2002                 ret = cz_dpm_force_lowest(adev);
2003                 if (ret)
2004                         return ret;
2005
2006                 /* uvd */
2007                 ret = cz_dpm_unforce_uvd_dpm_levels(adev);
2008                 if (ret)
2009                         return ret;
2010                 ret = cz_dpm_uvd_force_lowest(adev);
2011                 if (ret)
2012                         return ret;
2013
2014                 /* vce */
2015                 ret = cz_dpm_unforce_vce_dpm_levels(adev);
2016                 if (ret)
2017                         return ret;
2018                 ret = cz_dpm_vce_force_lowest(adev);
2019                 if (ret)
2020                         return ret;
2021                 break;
2022         case AMDGPU_DPM_FORCED_LEVEL_AUTO:
2023                 /* sclk */
2024                 ret = cz_dpm_unforce_dpm_levels(adev);
2025                 if (ret)
2026                         return ret;
2027
2028                 /* uvd */
2029                 ret = cz_dpm_unforce_uvd_dpm_levels(adev);
2030                 if (ret)
2031                         return ret;
2032
2033                 /* vce */
2034                 ret = cz_dpm_unforce_vce_dpm_levels(adev);
2035                 if (ret)
2036                         return ret;
2037                 break;
2038         default:
2039                 break;
2040         }
2041
2042         adev->pm.dpm.forced_level = level;
2043
2044         return ret;
2045 }
2046
2047 /* fix me, display configuration change lists here
2048  * mostly dal related*/
2049 static void cz_dpm_display_configuration_changed(struct amdgpu_device *adev)
2050 {
2051 }
2052
2053 static uint32_t cz_dpm_get_sclk(struct amdgpu_device *adev, bool low)
2054 {
2055         struct cz_power_info *pi = cz_get_pi(adev);
2056         struct cz_ps *requested_state = cz_get_ps(&pi->requested_rps);
2057
2058         if (low)
2059                 return requested_state->levels[0].sclk;
2060         else
2061                 return requested_state->levels[requested_state->num_levels - 1].sclk;
2062
2063 }
2064
2065 static uint32_t cz_dpm_get_mclk(struct amdgpu_device *adev, bool low)
2066 {
2067         struct cz_power_info *pi = cz_get_pi(adev);
2068
2069         return pi->sys_info.bootup_uma_clk;
2070 }
2071
2072 static int cz_enable_uvd_dpm(struct amdgpu_device *adev, bool enable)
2073 {
2074         struct cz_power_info *pi = cz_get_pi(adev);
2075         int ret = 0;
2076
2077         if (enable && pi->caps_uvd_dpm ) {
2078                 pi->dpm_flags |= DPMFlags_UVD_Enabled;
2079                 DRM_DEBUG("UVD DPM Enabled.\n");
2080
2081                 ret = cz_send_msg_to_smc_with_parameter(adev,
2082                         PPSMC_MSG_EnableAllSmuFeatures, UVD_DPM_MASK);
2083         } else {
2084                 pi->dpm_flags &= ~DPMFlags_UVD_Enabled;
2085                 DRM_DEBUG("UVD DPM Stopped\n");
2086
2087                 ret = cz_send_msg_to_smc_with_parameter(adev,
2088                         PPSMC_MSG_DisableAllSmuFeatures, UVD_DPM_MASK);
2089         }
2090
2091         return ret;
2092 }
2093
2094 static int cz_update_uvd_dpm(struct amdgpu_device *adev, bool gate)
2095 {
2096         return cz_enable_uvd_dpm(adev, !gate);
2097 }
2098
2099
2100 static void cz_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate)
2101 {
2102         struct cz_power_info *pi = cz_get_pi(adev);
2103         int ret;
2104
2105         if (pi->uvd_power_gated == gate)
2106                 return;
2107
2108         pi->uvd_power_gated = gate;
2109
2110         if (gate) {
2111                 if (pi->caps_uvd_pg) {
2112                         /* disable clockgating so we can properly shut down the block */
2113                         ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
2114                                                             AMD_CG_STATE_UNGATE);
2115                         if (ret) {
2116                                 DRM_ERROR("UVD DPM Power Gating failed to set clockgating state\n");
2117                                 return;
2118                         }
2119
2120                         /* shutdown the UVD block */
2121                         ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
2122                                                             AMD_PG_STATE_GATE);
2123
2124                         if (ret) {
2125                                 DRM_ERROR("UVD DPM Power Gating failed to set powergating state\n");
2126                                 return;
2127                         }
2128                 }
2129                 cz_update_uvd_dpm(adev, gate);
2130                 if (pi->caps_uvd_pg) {
2131                         /* power off the UVD block */
2132                         ret = cz_send_msg_to_smc(adev, PPSMC_MSG_UVDPowerOFF);
2133                         if (ret) {
2134                                 DRM_ERROR("UVD DPM Power Gating failed to send SMU PowerOFF message\n");
2135                                 return;
2136                         }
2137                 }
2138         } else {
2139                 if (pi->caps_uvd_pg) {
2140                         /* power on the UVD block */
2141                         if (pi->uvd_dynamic_pg)
2142                                 ret = cz_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_UVDPowerON, 1);
2143                         else
2144                                 ret = cz_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_UVDPowerON, 0);
2145
2146                         if (ret) {
2147                                 DRM_ERROR("UVD DPM Power Gating Failed to send SMU PowerON message\n");
2148                                 return;
2149                         }
2150
2151                         /* re-init the UVD block */
2152                         ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
2153                                                             AMD_PG_STATE_UNGATE);
2154
2155                         if (ret) {
2156                                 DRM_ERROR("UVD DPM Power Gating Failed to set powergating state\n");
2157                                 return;
2158                         }
2159
2160                         /* enable clockgating. hw will dynamically gate/ungate clocks on the fly */
2161                         ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
2162                                                             AMD_CG_STATE_GATE);
2163                         if (ret) {
2164                                 DRM_ERROR("UVD DPM Power Gating Failed to set clockgating state\n");
2165                                 return;
2166                         }
2167                 }
2168                 cz_update_uvd_dpm(adev, gate);
2169         }
2170 }
2171
2172 static int cz_enable_vce_dpm(struct amdgpu_device *adev, bool enable)
2173 {
2174         struct cz_power_info *pi = cz_get_pi(adev);
2175         int ret = 0;
2176
2177         if (enable && pi->caps_vce_dpm) {
2178                 pi->dpm_flags |= DPMFlags_VCE_Enabled;
2179                 DRM_DEBUG("VCE DPM Enabled.\n");
2180
2181                 ret = cz_send_msg_to_smc_with_parameter(adev,
2182                         PPSMC_MSG_EnableAllSmuFeatures, VCE_DPM_MASK);
2183
2184         } else {
2185                 pi->dpm_flags &= ~DPMFlags_VCE_Enabled;
2186                 DRM_DEBUG("VCE DPM Stopped\n");
2187
2188                 ret = cz_send_msg_to_smc_with_parameter(adev,
2189                         PPSMC_MSG_DisableAllSmuFeatures, VCE_DPM_MASK);
2190         }
2191
2192         return ret;
2193 }
2194
2195 static int cz_update_vce_dpm(struct amdgpu_device *adev)
2196 {
2197         struct cz_power_info *pi = cz_get_pi(adev);
2198         struct amdgpu_vce_clock_voltage_dependency_table *table =
2199                 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
2200
2201         /* Stable Pstate is enabled and we need to set the VCE DPM to highest level */
2202         if (pi->caps_stable_power_state) {
2203                 pi->vce_dpm.hard_min_clk = table->entries[table->count-1].ecclk;
2204         } else { /* non-stable p-state cases. without vce.Arbiter.EcclkHardMin */
2205                 /* leave it as set by user */
2206                 /*pi->vce_dpm.hard_min_clk = table->entries[0].ecclk;*/
2207         }
2208
2209         cz_send_msg_to_smc_with_parameter(adev,
2210                 PPSMC_MSG_SetEclkHardMin,
2211                 cz_get_eclk_level(adev,
2212                         pi->vce_dpm.hard_min_clk,
2213                         PPSMC_MSG_SetEclkHardMin));
2214         return 0;
2215 }
2216
2217 static void cz_dpm_powergate_vce(struct amdgpu_device *adev, bool gate)
2218 {
2219         struct cz_power_info *pi = cz_get_pi(adev);
2220
2221         if (pi->caps_vce_pg) {
2222                 if (pi->vce_power_gated != gate) {
2223                         if (gate) {
2224                                 /* disable clockgating so we can properly shut down the block */
2225                                 amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
2226                                                             AMD_CG_STATE_UNGATE);
2227                                 /* shutdown the VCE block */
2228                                 amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
2229                                                             AMD_PG_STATE_GATE);
2230
2231                                 cz_enable_vce_dpm(adev, false);
2232                                 cz_send_msg_to_smc(adev, PPSMC_MSG_VCEPowerOFF);
2233                                 pi->vce_power_gated = true;
2234                         } else {
2235                                 cz_send_msg_to_smc(adev, PPSMC_MSG_VCEPowerON);
2236                                 pi->vce_power_gated = false;
2237
2238                                 /* re-init the VCE block */
2239                                 amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
2240                                                             AMD_PG_STATE_UNGATE);
2241                                 /* enable clockgating. hw will dynamically gate/ungate clocks on the fly */
2242                                 amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
2243                                                             AMD_CG_STATE_GATE);
2244
2245                                 cz_update_vce_dpm(adev);
2246                                 cz_enable_vce_dpm(adev, true);
2247                         }
2248                 } else {
2249                         if (! pi->vce_power_gated) {
2250                                 cz_update_vce_dpm(adev);
2251                         }
2252                 }
2253         } else { /*pi->caps_vce_pg*/
2254                 pi->vce_power_gated = gate;
2255                 cz_update_vce_dpm(adev);
2256                 cz_enable_vce_dpm(adev, !gate);
2257         }
2258 }
2259
2260 const struct amd_ip_funcs cz_dpm_ip_funcs = {
2261         .name = "cz_dpm",
2262         .early_init = cz_dpm_early_init,
2263         .late_init = cz_dpm_late_init,
2264         .sw_init = cz_dpm_sw_init,
2265         .sw_fini = cz_dpm_sw_fini,
2266         .hw_init = cz_dpm_hw_init,
2267         .hw_fini = cz_dpm_hw_fini,
2268         .suspend = cz_dpm_suspend,
2269         .resume = cz_dpm_resume,
2270         .is_idle = NULL,
2271         .wait_for_idle = NULL,
2272         .soft_reset = NULL,
2273         .set_clockgating_state = cz_dpm_set_clockgating_state,
2274         .set_powergating_state = cz_dpm_set_powergating_state,
2275 };
2276
2277 static const struct amdgpu_dpm_funcs cz_dpm_funcs = {
2278         .get_temperature = cz_dpm_get_temperature,
2279         .pre_set_power_state = cz_dpm_pre_set_power_state,
2280         .set_power_state = cz_dpm_set_power_state,
2281         .post_set_power_state = cz_dpm_post_set_power_state,
2282         .display_configuration_changed = cz_dpm_display_configuration_changed,
2283         .get_sclk = cz_dpm_get_sclk,
2284         .get_mclk = cz_dpm_get_mclk,
2285         .print_power_state = cz_dpm_print_power_state,
2286         .debugfs_print_current_performance_level =
2287                                 cz_dpm_debugfs_print_current_performance_level,
2288         .force_performance_level = cz_dpm_force_dpm_level,
2289         .vblank_too_short = NULL,
2290         .powergate_uvd = cz_dpm_powergate_uvd,
2291         .powergate_vce = cz_dpm_powergate_vce,
2292 };
2293
2294 static void cz_dpm_set_funcs(struct amdgpu_device *adev)
2295 {
2296         if (NULL == adev->pm.funcs)
2297                 adev->pm.funcs = &cz_dpm_funcs;
2298 }