drivers/gpu/drm/amd/amdgpu/dce_v11_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "drmP.h"
  24 #include "amdgpu.h"
  25 #include "amdgpu_pm.h"
  26 #include "amdgpu_i2c.h"
  27 #include "vid.h"
  28 #include "atom.h"
  29 #include "amdgpu_atombios.h"
  30 #include "atombios_crtc.h"
  31 #include "atombios_encoders.h"
  32 #include "amdgpu_pll.h"
  33 #include "amdgpu_connectors.h"
  34
  35 #include "dce/dce_11_0_d.h"
  36 #include "dce/dce_11_0_sh_mask.h"
  37 #include "dce/dce_11_0_enum.h"
  38 #include "oss/oss_3_0_d.h"
  39 #include "oss/oss_3_0_sh_mask.h"
  40 #include "gmc/gmc_8_1_d.h"
  41 #include "gmc/gmc_8_1_sh_mask.h"
  42
  43 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev);
  44 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev);
  45
  46 static const u32 crtc_offsets[] =
  47 {
  48         CRTC0_REGISTER_OFFSET,
  49         CRTC1_REGISTER_OFFSET,
  50         CRTC2_REGISTER_OFFSET,
  51         CRTC3_REGISTER_OFFSET,
  52         CRTC4_REGISTER_OFFSET,
  53         CRTC5_REGISTER_OFFSET,
  54         CRTC6_REGISTER_OFFSET
  55 };
  56
  57 static const u32 hpd_offsets[] =
  58 {
  59         HPD0_REGISTER_OFFSET,
  60         HPD1_REGISTER_OFFSET,
  61         HPD2_REGISTER_OFFSET,
  62         HPD3_REGISTER_OFFSET,
  63         HPD4_REGISTER_OFFSET,
  64         HPD5_REGISTER_OFFSET
  65 };
  66
  67 static const uint32_t dig_offsets[] = {
  68         DIG0_REGISTER_OFFSET,
  69         DIG1_REGISTER_OFFSET,
  70         DIG2_REGISTER_OFFSET,
  71         DIG3_REGISTER_OFFSET,
  72         DIG4_REGISTER_OFFSET,
  73         DIG5_REGISTER_OFFSET,
  74         DIG6_REGISTER_OFFSET,
  75         DIG7_REGISTER_OFFSET,
  76         DIG8_REGISTER_OFFSET
  77 };
  78
  79 static const struct {
  80         uint32_t        reg;
  81         uint32_t        vblank;
  82         uint32_t        vline;
  83         uint32_t        hpd;
  84
  85 } interrupt_status_offsets[] = { {
  86         .reg = mmDISP_INTERRUPT_STATUS,
  87         .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
  88         .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
  89         .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
  90 }, {
  91         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
  92         .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
  93         .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
  94         .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
  95 }, {
  96         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
  97         .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
  98         .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
  99         .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
 100 }, {
 101         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
 102         .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
 103         .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
 104         .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
 105 }, {
 106         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
 107         .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
 108         .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
 109         .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
 110 }, {
 111         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
 112         .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
 113         .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
 114         .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
 115 } };
 116
 117 static const u32 cz_golden_settings_a11[] =
 118 {
 119         mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
 120         mmFBC_MISC, 0x1f311fff, 0x14300000,
 121 };
 122
 123 static const u32 cz_mgcg_cgcg_init[] =
 124 {
 125         mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
 126         mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
 127 };
 128
 129 static const u32 stoney_golden_settings_a11[] =
 130 {
 131         mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
 132         mmFBC_MISC, 0x1f311fff, 0x14302000,
 133 };
 134
 135
 136 static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
 137 {
 138         switch (adev->asic_type) {
 139         case CHIP_CARRIZO:
 140                 amdgpu_program_register_sequence(adev,
 141                                                  cz_mgcg_cgcg_init,
 142                                                  (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
 143                 amdgpu_program_register_sequence(adev,
 144                                                  cz_golden_settings_a11,
 145                                                  (const u32)ARRAY_SIZE(cz_golden_settings_a11));
 146                 break;
 147         case CHIP_STONEY:
 148                 amdgpu_program_register_sequence(adev,
 149                                                  stoney_golden_settings_a11,
 150                                                  (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
 151                 break;
 152         default:
 153                 break;
 154         }
 155 }
 156
 157 static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev,
 158                                      u32 block_offset, u32 reg)
 159 {
 160         unsigned long flags;
 161         u32 r;
 162
 163         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 164         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 165         r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
 166         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 167
 168         return r;
 169 }
 170
 171 static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev,
 172                                       u32 block_offset, u32 reg, u32 v)
 173 {
 174         unsigned long flags;
 175
 176         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 177         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 178         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
 179         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 180 }
 181
 182 static bool dce_v11_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
 183 {
 184         if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &
 185                         CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK)
 186                 return true;
 187         else
 188                 return false;
 189 }
 190
 191 static bool dce_v11_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
 192 {
 193         u32 pos1, pos2;
 194
 195         pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 196         pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 197
 198         if (pos1 != pos2)
 199                 return true;
 200         else
 201                 return false;
 202 }
 203
 204 /**
 205  * dce_v11_0_vblank_wait - vblank wait asic callback.
 206  *
 207  * @adev: amdgpu_device pointer
 208  * @crtc: crtc to wait for vblank on
 209  *
 210  * Wait for vblank on the requested crtc (evergreen+).
 211  */
 212 static void dce_v11_0_vblank_wait(struct amdgpu_device *adev, int crtc)
 213 {
 214         unsigned i = 0;
 215
 216         if (crtc >= adev->mode_info.num_crtc)
 217                 return;
 218
 219         if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
 220                 return;
 221
 222         /* depending on when we hit vblank, we may be close to active; if so,
 223          * wait for another frame.
 224          */
 225         while (dce_v11_0_is_in_vblank(adev, crtc)) {
 226                 if (i++ % 100 == 0) {
 227                         if (!dce_v11_0_is_counter_moving(adev, crtc))
 228                                 break;
 229                 }
 230         }
 231
 232         while (!dce_v11_0_is_in_vblank(adev, crtc)) {
 233                 if (i++ % 100 == 0) {
 234                         if (!dce_v11_0_is_counter_moving(adev, crtc))
 235                                 break;
 236                 }
 237         }
 238 }
 239
 240 static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 241 {
 242         if (crtc >= adev->mode_info.num_crtc)
 243                 return 0;
 244         else
 245                 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
 246 }
 247
 248 static void dce_v11_0_pageflip_interrupt_init(struct amdgpu_device *adev)
 249 {
 250         unsigned i;
 251
 252         /* Enable pflip interrupts */
 253         for (i = 0; i < adev->mode_info.num_crtc; i++)
 254                 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
 255 }
 256
 257 static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
 258 {
 259         unsigned i;
 260
 261         /* Disable pflip interrupts */
 262         for (i = 0; i < adev->mode_info.num_crtc; i++)
 263                 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
 264 }
 265
 266 /**
 267  * dce_v11_0_page_flip - pageflip callback.
 268  *
 269  * @adev: amdgpu_device pointer
 270  * @crtc_id: crtc to cleanup pageflip on
 271  * @crtc_base: new address of the crtc (GPU MC address)
 272  *
 273  * Triggers the actual pageflip by updating the primary
 274  * surface base address.
 275  */
 276 static void dce_v11_0_page_flip(struct amdgpu_device *adev,
 277                               int crtc_id, u64 crtc_base)
 278 {
 279         struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
 280
 281         /* update the scanout addresses */
 282         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
 283                upper_32_bits(crtc_base));
 284         /* writing to the low address triggers the update */
 285         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
 286                lower_32_bits(crtc_base));
 287         /* post the write */
 288         RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
 289 }
 290
 291 static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 292                                         u32 *vbl, u32 *position)
 293 {
 294         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 295                 return -EINVAL;
 296
 297         *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
 298         *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 299
 300         return 0;
 301 }
 302
 303 /**
 304  * dce_v11_0_hpd_sense - hpd sense callback.
 305  *
 306  * @adev: amdgpu_device pointer
 307  * @hpd: hpd (hotplug detect) pin
 308  *
 309  * Checks if a digital monitor is connected (evergreen+).
 310  * Returns true if connected, false if not connected.
 311  */
 312 static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev,
 313                                enum amdgpu_hpd_id hpd)
 314 {
 315         int idx;
 316         bool connected = false;
 317
 318         switch (hpd) {
 319         case AMDGPU_HPD_1:
 320                 idx = 0;
 321                 break;
 322         case AMDGPU_HPD_2:
 323                 idx = 1;
 324                 break;
 325         case AMDGPU_HPD_3:
 326                 idx = 2;
 327                 break;
 328         case AMDGPU_HPD_4:
 329                 idx = 3;
 330                 break;
 331         case AMDGPU_HPD_5:
 332                 idx = 4;
 333                 break;
 334         case AMDGPU_HPD_6:
 335                 idx = 5;
 336                 break;
 337         default:
 338                 return connected;
 339         }
 340
 341         if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[idx]) &
 342             DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
 343                 connected = true;
 344
 345         return connected;
 346 }
 347
 348 /**
 349  * dce_v11_0_hpd_set_polarity - hpd set polarity callback.
 350  *
 351  * @adev: amdgpu_device pointer
 352  * @hpd: hpd (hotplug detect) pin
 353  *
 354  * Set the polarity of the hpd pin (evergreen+).
 355  */
 356 static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev,
 357                                       enum amdgpu_hpd_id hpd)
 358 {
 359         u32 tmp;
 360         bool connected = dce_v11_0_hpd_sense(adev, hpd);
 361         int idx;
 362
 363         switch (hpd) {
 364         case AMDGPU_HPD_1:
 365                 idx = 0;
 366                 break;
 367         case AMDGPU_HPD_2:
 368                 idx = 1;
 369                 break;
 370         case AMDGPU_HPD_3:
 371                 idx = 2;
 372                 break;
 373         case AMDGPU_HPD_4:
 374                 idx = 3;
 375                 break;
 376         case AMDGPU_HPD_5:
 377                 idx = 4;
 378                 break;
 379         case AMDGPU_HPD_6:
 380                 idx = 5;
 381                 break;
 382         default:
 383                 return;
 384         }
 385
 386         tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]);
 387         if (connected)
 388                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
 389         else
 390                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
 391         WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp);
 392 }
 393
 394 /**
 395  * dce_v11_0_hpd_init - hpd setup callback.
 396  *
 397  * @adev: amdgpu_device pointer
 398  *
 399  * Setup the hpd pins used by the card (evergreen+).
 400  * Enable the pin, set the polarity, and enable the hpd interrupts.
 401  */
 402 static void dce_v11_0_hpd_init(struct amdgpu_device *adev)
 403 {
 404         struct drm_device *dev = adev->ddev;
 405         struct drm_connector *connector;
 406         u32 tmp;
 407         int idx;
 408
 409         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 410                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 411
 412                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
 413                     connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
 414                         /* don't try to enable hpd on eDP or LVDS avoid breaking the
 415                          * aux dp channel on imac and help (but not completely fix)
 416                          * https://bugzilla.redhat.com/show_bug.cgi?id=726143
 417                          * also avoid interrupt storms during dpms.
 418                          */
 419                         continue;
 420                 }
 421
 422                 switch (amdgpu_connector->hpd.hpd) {
 423                 case AMDGPU_HPD_1:
 424                         idx = 0;
 425                         break;
 426                 case AMDGPU_HPD_2:
 427                         idx = 1;
 428                         break;
 429                 case AMDGPU_HPD_3:
 430                         idx = 2;
 431                         break;
 432                 case AMDGPU_HPD_4:
 433                         idx = 3;
 434                         break;
 435                 case AMDGPU_HPD_5:
 436                         idx = 4;
 437                         break;
 438                 case AMDGPU_HPD_6:
 439                         idx = 5;
 440                         break;
 441                 default:
 442                         continue;
 443                 }
 444
 445                 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
 446                 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
 447                 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
 448
 449                 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx]);
 450                 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
 451                                     DC_HPD_CONNECT_INT_DELAY,
 452                                     AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
 453                 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
 454                                     DC_HPD_DISCONNECT_INT_DELAY,
 455                                     AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
 456                 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx], tmp);
 457
 458                 dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
 459                 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
 460         }
 461 }
 462
 463 /**
 464  * dce_v11_0_hpd_fini - hpd tear down callback.
 465  *
 466  * @adev: amdgpu_device pointer
 467  *
 468  * Tear down the hpd pins used by the card (evergreen+).
 469  * Disable the hpd interrupts.
 470  */
 471 static void dce_v11_0_hpd_fini(struct amdgpu_device *adev)
 472 {
 473         struct drm_device *dev = adev->ddev;
 474         struct drm_connector *connector;
 475         u32 tmp;
 476         int idx;
 477
 478         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 479                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 480
 481                 switch (amdgpu_connector->hpd.hpd) {
 482                 case AMDGPU_HPD_1:
 483                         idx = 0;
 484                         break;
 485                 case AMDGPU_HPD_2:
 486                         idx = 1;
 487                         break;
 488                 case AMDGPU_HPD_3:
 489                         idx = 2;
 490                         break;
 491                 case AMDGPU_HPD_4:
 492                         idx = 3;
 493                         break;
 494                 case AMDGPU_HPD_5:
 495                         idx = 4;
 496                         break;
 497                 case AMDGPU_HPD_6:
 498                         idx = 5;
 499                         break;
 500                 default:
 501                         continue;
 502                 }
 503
 504                 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]);
 505                 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
 506                 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp);
 507
 508                 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
 509         }
 510 }
 511
 512 static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
 513 {
 514         return mmDC_GPIO_HPD_A;
 515 }
 516
 517 static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev)
 518 {
 519         u32 crtc_hung = 0;
 520         u32 crtc_status[6];
 521         u32 i, j, tmp;
 522
 523         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 524                 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 525                 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
 526                         crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
 527                         crtc_hung |= (1 << i);
 528                 }
 529         }
 530
 531         for (j = 0; j < 10; j++) {
 532                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
 533                         if (crtc_hung & (1 << i)) {
 534                                 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
 535                                 if (tmp != crtc_status[i])
 536                                         crtc_hung &= ~(1 << i);
 537                         }
 538                 }
 539                 if (crtc_hung == 0)
 540                         return false;
 541                 udelay(100);
 542         }
 543
 544         return true;
 545 }
 546
 547 static void dce_v11_0_stop_mc_access(struct amdgpu_device *adev,
 548                                      struct amdgpu_mode_mc_save *save)
 549 {
 550         u32 crtc_enabled, tmp;
 551         int i;
 552
 553         save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
 554         save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
 555
 556         /* disable VGA render */
 557         tmp = RREG32(mmVGA_RENDER_CONTROL);
 558         tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 559         WREG32(mmVGA_RENDER_CONTROL, tmp);
 560
 561         /* blank the display controllers */
 562         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 563                 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
 564                                              CRTC_CONTROL, CRTC_MASTER_EN);
 565                 if (crtc_enabled) {
 566 #if 0
 567                         u32 frame_count;
 568                         int j;
 569
 570                         save->crtc_enabled[i] = true;
 571                         tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
 572                         if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
 573                                 amdgpu_display_vblank_wait(adev, i);
 574                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 575                                 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
 576                                 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
 577                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 578                         }
 579                         /* wait for the next frame */
 580                         frame_count = amdgpu_display_vblank_get_counter(adev, i);
 581                         for (j = 0; j < adev->usec_timeout; j++) {
 582                                 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
 583                                         break;
 584                                 udelay(1);
 585                         }
 586                         tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
 587                         if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) {
 588                                 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
 589                                 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
 590                         }
 591                         tmp = RREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i]);
 592                         if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) {
 593                                 tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1);
 594                                 WREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
 595                         }
 596 #else
 597                         /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
 598                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 599                         tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 600                         tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
 601                         WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
 602                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 603                         save->crtc_enabled[i] = false;
 604                         /* ***** */
 605 #endif
 606                 } else {
 607                         save->crtc_enabled[i] = false;
 608                 }
 609         }
 610 }
 611
 612 static void dce_v11_0_resume_mc_access(struct amdgpu_device *adev,
 613                                        struct amdgpu_mode_mc_save *save)
 614 {
 615         u32 tmp, frame_count;
 616         int i, j;
 617
 618         /* update crtc base addresses */
 619         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 620                 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
 621                        upper_32_bits(adev->mc.vram_start));
 622                 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
 623                        upper_32_bits(adev->mc.vram_start));
 624                 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
 625                        (u32)adev->mc.vram_start);
 626                 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
 627                        (u32)adev->mc.vram_start);
 628
 629                 if (save->crtc_enabled[i]) {
 630                         tmp = RREG32(mmCRTC_MASTER_UPDATE_MODE + crtc_offsets[i]);
 631                         if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 3) {
 632                                 tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 3);
 633                                 WREG32(mmCRTC_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
 634                         }
 635                         tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
 636                         if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) {
 637                                 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);
 638                                 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
 639                         }
 640                         tmp = RREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i]);
 641                         if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) {
 642                                 tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0);
 643                                 WREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
 644                         }
 645                         for (j = 0; j < adev->usec_timeout; j++) {
 646                                 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
 647                                 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0)
 648                                         break;
 649                                 udelay(1);
 650                         }
 651                         tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
 652                         tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
 653                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 654                         WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
 655                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 656                         /* wait for the next frame */
 657                         frame_count = amdgpu_display_vblank_get_counter(adev, i);
 658                         for (j = 0; j < adev->usec_timeout; j++) {
 659                                 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
 660                                         break;
 661                                 udelay(1);
 662                         }
 663                 }
 664         }
 665
 666         WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
 667         WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));
 668
 669         /* Unlock vga access */
 670         WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
 671         mdelay(1);
 672         WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
 673 }
 674
 675 static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev,
 676                                            bool render)
 677 {
 678         u32 tmp;
 679
 680         /* Lockout access through VGA aperture*/
 681         tmp = RREG32(mmVGA_HDP_CONTROL);
 682         if (render)
 683                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
 684         else
 685                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
 686         WREG32(mmVGA_HDP_CONTROL, tmp);
 687
 688         /* disable VGA render */
 689         tmp = RREG32(mmVGA_RENDER_CONTROL);
 690         if (render)
 691                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
 692         else
 693                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 694         WREG32(mmVGA_RENDER_CONTROL, tmp);
 695 }
 696
 697 static void dce_v11_0_program_fmt(struct drm_encoder *encoder)
 698 {
 699         struct drm_device *dev = encoder->dev;
 700         struct amdgpu_device *adev = dev->dev_private;
 701         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 702         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
 703         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
 704         int bpc = 0;
 705         u32 tmp = 0;
 706         enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
 707
 708         if (connector) {
 709                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 710                 bpc = amdgpu_connector_get_monitor_bpc(connector);
 711                 dither = amdgpu_connector->dither;
 712         }
 713
 714         /* LVDS/eDP FMT is set up by atom */
 715         if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
 716                 return;
 717
 718         /* not needed for analog */
 719         if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
 720             (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
 721                 return;
 722
 723         if (bpc == 0)
 724                 return;
 725
 726         switch (bpc) {
 727         case 6:
 728                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 729                         /* XXX sort out optimal dither settings */
 730                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 731                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 732                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 733                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
 734                 } else {
 735                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 736                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
 737                 }
 738                 break;
 739         case 8:
 740                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 741                         /* XXX sort out optimal dither settings */
 742                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 743                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 744                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
 745                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 746                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
 747                 } else {
 748                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 749                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
 750                 }
 751                 break;
 752         case 10:
 753                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 754                         /* XXX sort out optimal dither settings */
 755                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 756                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 757                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
 758                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 759                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
 760                 } else {
 761                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 762                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
 763                 }
 764                 break;
 765         default:
 766                 /* not needed */
 767                 break;
 768         }
 769
 770         WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
 771 }
 772
 773
 774 /* display watermark setup */
 775 /**
 776  * dce_v11_0_line_buffer_adjust - Set up the line buffer
 777  *
 778  * @adev: amdgpu_device pointer
 779  * @amdgpu_crtc: the selected display controller
 780  * @mode: the current display mode on the selected display
 781  * controller
 782  *
 783  * Setup up the line buffer allocation for
 784  * the selected display controller (CIK).
 785  * Returns the line buffer size in pixels.
 786  */
 787 static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev,
 788                                        struct amdgpu_crtc *amdgpu_crtc,
 789                                        struct drm_display_mode *mode)
 790 {
 791         u32 tmp, buffer_alloc, i, mem_cfg;
 792         u32 pipe_offset = amdgpu_crtc->crtc_id;
 793         /*
 794          * Line Buffer Setup
 795          * There are 6 line buffers, one for each display controllers.
 796          * There are 3 partitions per LB. Select the number of partitions
 797          * to enable based on the display width.  For display widths larger
 798          * than 4096, you need use to use 2 display controllers and combine
 799          * them using the stereo blender.
 800          */
 801         if (amdgpu_crtc->base.enabled && mode) {
 802                 if (mode->crtc_hdisplay < 1920) {
 803                         mem_cfg = 1;
 804                         buffer_alloc = 2;
 805                 } else if (mode->crtc_hdisplay < 2560) {
 806                         mem_cfg = 2;
 807                         buffer_alloc = 2;
 808                 } else if (mode->crtc_hdisplay < 4096) {
 809                         mem_cfg = 0;
 810                         buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
 811                 } else {
 812                         DRM_DEBUG_KMS("Mode too big for LB!\n");
 813                         mem_cfg = 0;
 814                         buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
 815                 }
 816         } else {
 817                 mem_cfg = 1;
 818                 buffer_alloc = 0;
 819         }
 820
 821         tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
 822         tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
 823         WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
 824
 825         tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
 826         tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
 827         WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
 828
 829         for (i = 0; i < adev->usec_timeout; i++) {
 830                 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
 831                 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
 832                         break;
 833                 udelay(1);
 834         }
 835
 836         if (amdgpu_crtc->base.enabled && mode) {
 837                 switch (mem_cfg) {
 838                 case 0:
 839                 default:
 840                         return 4096 * 2;
 841                 case 1:
 842                         return 1920 * 2;
 843                 case 2:
 844                         return 2560 * 2;
 845                 }
 846         }
 847
 848         /* controller not enabled, so no lb used */
 849         return 0;
 850 }
 851
 852 /**
 853  * cik_get_number_of_dram_channels - get the number of dram channels
 854  *
 855  * @adev: amdgpu_device pointer
 856  *
 857  * Look up the number of video ram channels (CIK).
 858  * Used for display watermark bandwidth calculations
 859  * Returns the number of dram channels
 860  */
 861 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
 862 {
 863         u32 tmp = RREG32(mmMC_SHARED_CHMAP);
 864
 865         switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 866         case 0:
 867         default:
 868                 return 1;
 869         case 1:
 870                 return 2;
 871         case 2:
 872                 return 4;
 873         case 3:
 874                 return 8;
 875         case 4:
 876                 return 3;
 877         case 5:
 878                 return 6;
 879         case 6:
 880                 return 10;
 881         case 7:
 882                 return 12;
 883         case 8:
 884                 return 16;
 885         }
 886 }
 887
 888 struct dce10_wm_params {
 889         u32 dram_channels; /* number of dram channels */
 890         u32 yclk;          /* bandwidth per dram data pin in kHz */
 891         u32 sclk;          /* engine clock in kHz */
 892         u32 disp_clk;      /* display clock in kHz */
 893         u32 src_width;     /* viewport width */
 894         u32 active_time;   /* active display time in ns */
 895         u32 blank_time;    /* blank time in ns */
 896         bool interlaced;    /* mode is interlaced */
 897         fixed20_12 vsc;    /* vertical scale ratio */
 898         u32 num_heads;     /* number of active crtcs */
 899         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
 900         u32 lb_size;       /* line buffer allocated to pipe */
 901         u32 vtaps;         /* vertical scaler taps */
 902 };
 903
 904 /**
 905  * dce_v11_0_dram_bandwidth - get the dram bandwidth
 906  *
 907  * @wm: watermark calculation data
 908  *
 909  * Calculate the raw dram bandwidth (CIK).
 910  * Used for display watermark bandwidth calculations
 911  * Returns the dram bandwidth in MBytes/s
 912  */
 913 static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm)
 914 {
 915         /* Calculate raw DRAM Bandwidth */
 916         fixed20_12 dram_efficiency; /* 0.7 */
 917         fixed20_12 yclk, dram_channels, bandwidth;
 918         fixed20_12 a;
 919
 920         a.full = dfixed_const(1000);
 921         yclk.full = dfixed_const(wm->yclk);
 922         yclk.full = dfixed_div(yclk, a);
 923         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 924         a.full = dfixed_const(10);
 925         dram_efficiency.full = dfixed_const(7);
 926         dram_efficiency.full = dfixed_div(dram_efficiency, a);
 927         bandwidth.full = dfixed_mul(dram_channels, yclk);
 928         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
 929
 930         return dfixed_trunc(bandwidth);
 931 }
 932
 933 /**
 934  * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display
 935  *
 936  * @wm: watermark calculation data
 937  *
 938  * Calculate the dram bandwidth used for display (CIK).
 939  * Used for display watermark bandwidth calculations
 940  * Returns the dram bandwidth for display in MBytes/s
 941  */
 942 static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
 943 {
 944         /* Calculate DRAM Bandwidth and the part allocated to display. */
 945         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
 946         fixed20_12 yclk, dram_channels, bandwidth;
 947         fixed20_12 a;
 948
 949         a.full = dfixed_const(1000);
 950         yclk.full = dfixed_const(wm->yclk);
 951         yclk.full = dfixed_div(yclk, a);
 952         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 953         a.full = dfixed_const(10);
 954         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
 955         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
 956         bandwidth.full = dfixed_mul(dram_channels, yclk);
 957         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
 958
 959         return dfixed_trunc(bandwidth);
 960 }
 961
 962 /**
 963  * dce_v11_0_data_return_bandwidth - get the data return bandwidth
 964  *
 965  * @wm: watermark calculation data
 966  *
 967  * Calculate the data return bandwidth used for display (CIK).
 968  * Used for display watermark bandwidth calculations
 969  * Returns the data return bandwidth in MBytes/s
 970  */
 971 static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm)
 972 {
 973         /* Calculate the display Data return Bandwidth */
 974         fixed20_12 return_efficiency; /* 0.8 */
 975         fixed20_12 sclk, bandwidth;
 976         fixed20_12 a;
 977
 978         a.full = dfixed_const(1000);
 979         sclk.full = dfixed_const(wm->sclk);
 980         sclk.full = dfixed_div(sclk, a);
 981         a.full = dfixed_const(10);
 982         return_efficiency.full = dfixed_const(8);
 983         return_efficiency.full = dfixed_div(return_efficiency, a);
 984         a.full = dfixed_const(32);
 985         bandwidth.full = dfixed_mul(a, sclk);
 986         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
 987
 988         return dfixed_trunc(bandwidth);
 989 }
 990
 991 /**
 992  * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth
 993  *
 994  * @wm: watermark calculation data
 995  *
 996  * Calculate the dmif bandwidth used for display (CIK).
 997  * Used for display watermark bandwidth calculations
 998  * Returns the dmif bandwidth in MBytes/s
 999  */
1000 static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
1001 {
1002         /* Calculate the DMIF Request Bandwidth */
1003         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
1004         fixed20_12 disp_clk, bandwidth;
1005         fixed20_12 a, b;
1006
1007         a.full = dfixed_const(1000);
1008         disp_clk.full = dfixed_const(wm->disp_clk);
1009         disp_clk.full = dfixed_div(disp_clk, a);
1010         a.full = dfixed_const(32);
1011         b.full = dfixed_mul(a, disp_clk);
1012
1013         a.full = dfixed_const(10);
1014         disp_clk_request_efficiency.full = dfixed_const(8);
1015         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
1016
1017         bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
1018
1019         return dfixed_trunc(bandwidth);
1020 }
1021
1022 /**
1023  * dce_v11_0_available_bandwidth - get the min available bandwidth
1024  *
1025  * @wm: watermark calculation data
1026  *
1027  * Calculate the min available bandwidth used for display (CIK).
1028  * Used for display watermark bandwidth calculations
1029  * Returns the min available bandwidth in MBytes/s
1030  */
1031 static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm)
1032 {
1033         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
1034         u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm);
1035         u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm);
1036         u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm);
1037
1038         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
1039 }
1040
1041 /**
1042  * dce_v11_0_average_bandwidth - get the average available bandwidth
1043  *
1044  * @wm: watermark calculation data
1045  *
1046  * Calculate the average available bandwidth used for display (CIK).
1047  * Used for display watermark bandwidth calculations
1048  * Returns the average available bandwidth in MBytes/s
1049  */
1050 static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm)
1051 {
1052         /* Calculate the display mode Average Bandwidth
1053          * DisplayMode should contain the source and destination dimensions,
1054          * timing, etc.
1055          */
1056         fixed20_12 bpp;
1057         fixed20_12 line_time;
1058         fixed20_12 src_width;
1059         fixed20_12 bandwidth;
1060         fixed20_12 a;
1061
1062         a.full = dfixed_const(1000);
1063         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
1064         line_time.full = dfixed_div(line_time, a);
1065         bpp.full = dfixed_const(wm->bytes_per_pixel);
1066         src_width.full = dfixed_const(wm->src_width);
1067         bandwidth.full = dfixed_mul(src_width, bpp);
1068         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
1069         bandwidth.full = dfixed_div(bandwidth, line_time);
1070
1071         return dfixed_trunc(bandwidth);
1072 }
1073
1074 /**
1075  * dce_v11_0_latency_watermark - get the latency watermark
1076  *
1077  * @wm: watermark calculation data
1078  *
1079  * Calculate the latency watermark (CIK).
1080  * Used for display watermark bandwidth calculations
1081  * Returns the latency watermark in ns
1082  */
1083 static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm)
1084 {
1085         /* First calculate the latency in ns */
1086         u32 mc_latency = 2000; /* 2000 ns. */
1087         u32 available_bandwidth = dce_v11_0_available_bandwidth(wm);
1088         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
1089         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
1090         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
1091         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
1092                 (wm->num_heads * cursor_line_pair_return_time);
1093         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
1094         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
1095         u32 tmp, dmif_size = 12288;
1096         fixed20_12 a, b, c;
1097
1098         if (wm->num_heads == 0)
1099                 return 0;
1100
1101         a.full = dfixed_const(2);
1102         b.full = dfixed_const(1);
1103         if ((wm->vsc.full > a.full) ||
1104             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
1105             (wm->vtaps >= 5) ||
1106             ((wm->vsc.full >= a.full) && wm->interlaced))
1107                 max_src_lines_per_dst_line = 4;
1108         else
1109                 max_src_lines_per_dst_line = 2;
1110
1111         a.full = dfixed_const(available_bandwidth);
1112         b.full = dfixed_const(wm->num_heads);
1113         a.full = dfixed_div(a, b);
1114
1115         b.full = dfixed_const(mc_latency + 512);
1116         c.full = dfixed_const(wm->disp_clk);
1117         b.full = dfixed_div(b, c);
1118
1119         c.full = dfixed_const(dmif_size);
1120         b.full = dfixed_div(c, b);
1121
1122         tmp = min(dfixed_trunc(a), dfixed_trunc(b));
1123
1124         b.full = dfixed_const(1000);
1125         c.full = dfixed_const(wm->disp_clk);
1126         b.full = dfixed_div(c, b);
1127         c.full = dfixed_const(wm->bytes_per_pixel);
1128         b.full = dfixed_mul(b, c);
1129
1130         lb_fill_bw = min(tmp, dfixed_trunc(b));
1131
1132         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
1133         b.full = dfixed_const(1000);
1134         c.full = dfixed_const(lb_fill_bw);
1135         b.full = dfixed_div(c, b);
1136         a.full = dfixed_div(a, b);
1137         line_fill_time = dfixed_trunc(a);
1138
1139         if (line_fill_time < wm->active_time)
1140                 return latency;
1141         else
1142                 return latency + (line_fill_time - wm->active_time);
1143
1144 }
1145
1146 /**
1147  * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1148  * average and available dram bandwidth
1149  *
1150  * @wm: watermark calculation data
1151  *
1152  * Check if the display average bandwidth fits in the display
1153  * dram bandwidth (CIK).
1154  * Used for display watermark bandwidth calculations
1155  * Returns true if the display fits, false if not.
1156  */
1157 static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
1158 {
1159         if (dce_v11_0_average_bandwidth(wm) <=
1160             (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads))
1161                 return true;
1162         else
1163                 return false;
1164 }
1165
1166 /**
1167  * dce_v11_0_average_bandwidth_vs_available_bandwidth - check
1168  * average and available bandwidth
1169  *
1170  * @wm: watermark calculation data
1171  *
1172  * Check if the display average bandwidth fits in the display
1173  * available bandwidth (CIK).
1174  * Used for display watermark bandwidth calculations
1175  * Returns true if the display fits, false if not.
1176  */
1177 static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
1178 {
1179         if (dce_v11_0_average_bandwidth(wm) <=
1180             (dce_v11_0_available_bandwidth(wm) / wm->num_heads))
1181                 return true;
1182         else
1183                 return false;
1184 }
1185
1186 /**
1187  * dce_v11_0_check_latency_hiding - check latency hiding
1188  *
1189  * @wm: watermark calculation data
1190  *
1191  * Check latency hiding (CIK).
1192  * Used for display watermark bandwidth calculations
1193  * Returns true if the display fits, false if not.
1194  */
1195 static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm)
1196 {
1197         u32 lb_partitions = wm->lb_size / wm->src_width;
1198         u32 line_time = wm->active_time + wm->blank_time;
1199         u32 latency_tolerant_lines;
1200         u32 latency_hiding;
1201         fixed20_12 a;
1202
1203         a.full = dfixed_const(1);
1204         if (wm->vsc.full > a.full)
1205                 latency_tolerant_lines = 1;
1206         else {
1207                 if (lb_partitions <= (wm->vtaps + 1))
1208                         latency_tolerant_lines = 1;
1209                 else
1210                         latency_tolerant_lines = 2;
1211         }
1212
1213         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1214
1215         if (dce_v11_0_latency_watermark(wm) <= latency_hiding)
1216                 return true;
1217         else
1218                 return false;
1219 }
1220
1221 /**
1222  * dce_v11_0_program_watermarks - program display watermarks
1223  *
1224  * @adev: amdgpu_device pointer
1225  * @amdgpu_crtc: the selected display controller
1226  * @lb_size: line buffer size
1227  * @num_heads: number of display controllers in use
1228  *
1229  * Calculate and program the display watermarks for the
1230  * selected display controller (CIK).
1231  */
1232 static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
1233                                         struct amdgpu_crtc *amdgpu_crtc,
1234                                         u32 lb_size, u32 num_heads)
1235 {
1236         struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1237         struct dce10_wm_params wm_low, wm_high;
1238         u32 pixel_period;
1239         u32 line_time = 0;
1240         u32 latency_watermark_a = 0, latency_watermark_b = 0;
1241         u32 tmp, wm_mask;
1242
1243         if (amdgpu_crtc->base.enabled && num_heads && mode) {
1244                 pixel_period = 1000000 / (u32)mode->clock;
1245                 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
1246
1247                 /* watermark for high clocks */
1248                 if (adev->pm.dpm_enabled) {
1249                         wm_high.yclk =
1250                                 amdgpu_dpm_get_mclk(adev, false) * 10;
1251                         wm_high.sclk =
1252                                 amdgpu_dpm_get_sclk(adev, false) * 10;
1253                 } else {
1254                         wm_high.yclk = adev->pm.current_mclk * 10;
1255                         wm_high.sclk = adev->pm.current_sclk * 10;
1256                 }
1257
1258                 wm_high.disp_clk = mode->clock;
1259                 wm_high.src_width = mode->crtc_hdisplay;
1260                 wm_high.active_time = mode->crtc_hdisplay * pixel_period;
1261                 wm_high.blank_time = line_time - wm_high.active_time;
1262                 wm_high.interlaced = false;
1263                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1264                         wm_high.interlaced = true;
1265                 wm_high.vsc = amdgpu_crtc->vsc;
1266                 wm_high.vtaps = 1;
1267                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1268                         wm_high.vtaps = 2;
1269                 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1270                 wm_high.lb_size = lb_size;
1271                 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1272                 wm_high.num_heads = num_heads;
1273
1274                 /* set for high clocks */
1275                 latency_watermark_a = min(dce_v11_0_latency_watermark(&wm_high), (u32)65535);
1276
1277                 /* possibly force display priority to high */
1278                 /* should really do this at mode validation time... */
1279                 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1280                     !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1281                     !dce_v11_0_check_latency_hiding(&wm_high) ||
1282                     (adev->mode_info.disp_priority == 2)) {
1283                         DRM_DEBUG_KMS("force priority to high\n");
1284                 }
1285
1286                 /* watermark for low clocks */
1287                 if (adev->pm.dpm_enabled) {
1288                         wm_low.yclk =
1289                                 amdgpu_dpm_get_mclk(adev, true) * 10;
1290                         wm_low.sclk =
1291                                 amdgpu_dpm_get_sclk(adev, true) * 10;
1292                 } else {
1293                         wm_low.yclk = adev->pm.current_mclk * 10;
1294                         wm_low.sclk = adev->pm.current_sclk * 10;
1295                 }
1296
1297                 wm_low.disp_clk = mode->clock;
1298                 wm_low.src_width = mode->crtc_hdisplay;
1299                 wm_low.active_time = mode->crtc_hdisplay * pixel_period;
1300                 wm_low.blank_time = line_time - wm_low.active_time;
1301                 wm_low.interlaced = false;
1302                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1303                         wm_low.interlaced = true;
1304                 wm_low.vsc = amdgpu_crtc->vsc;
1305                 wm_low.vtaps = 1;
1306                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1307                         wm_low.vtaps = 2;
1308                 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1309                 wm_low.lb_size = lb_size;
1310                 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1311                 wm_low.num_heads = num_heads;
1312
1313                 /* set for low clocks */
1314                 latency_watermark_b = min(dce_v11_0_latency_watermark(&wm_low), (u32)65535);
1315
1316                 /* possibly force display priority to high */
1317                 /* should really do this at mode validation time... */
1318                 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1319                     !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1320                     !dce_v11_0_check_latency_hiding(&wm_low) ||
1321                     (adev->mode_info.disp_priority == 2)) {
1322                         DRM_DEBUG_KMS("force priority to high\n");
1323                 }
1324         }
1325
1326         /* select wm A */
1327         wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1328         tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1329         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1330         tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1331         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1332         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1333         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1334         /* select wm B */
1335         tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1336         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1337         tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1338         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
1339         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1340         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1341         /* restore original selection */
1342         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1343
1344         /* save values for DPM */
1345         amdgpu_crtc->line_time = line_time;
1346         amdgpu_crtc->wm_high = latency_watermark_a;
1347         amdgpu_crtc->wm_low = latency_watermark_b;
1348 }
1349
1350 /**
1351  * dce_v11_0_bandwidth_update - program display watermarks
1352  *
1353  * @adev: amdgpu_device pointer
1354  *
1355  * Calculate and program the display watermarks and line
1356  * buffer allocation (CIK).
1357  */
1358 static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev)
1359 {
1360         struct drm_display_mode *mode = NULL;
1361         u32 num_heads = 0, lb_size;
1362         int i;
1363
1364         amdgpu_update_display_priority(adev);
1365
1366         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1367                 if (adev->mode_info.crtcs[i]->base.enabled)
1368                         num_heads++;
1369         }
1370         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1371                 mode = &adev->mode_info.crtcs[i]->base.mode;
1372                 lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1373                 dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1374                                             lb_size, num_heads);
1375         }
1376 }
1377
1378 static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev)
1379 {
1380         int i;
1381         u32 offset, tmp;
1382
1383         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1384                 offset = adev->mode_info.audio.pin[i].offset;
1385                 tmp = RREG32_AUDIO_ENDPT(offset,
1386                                          ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1387                 if (((tmp &
1388                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1389                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1390                         adev->mode_info.audio.pin[i].connected = false;
1391                 else
1392                         adev->mode_info.audio.pin[i].connected = true;
1393         }
1394 }
1395
1396 static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev)
1397 {
1398         int i;
1399
1400         dce_v11_0_audio_get_connected_pins(adev);
1401
1402         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1403                 if (adev->mode_info.audio.pin[i].connected)
1404                         return &adev->mode_info.audio.pin[i];
1405         }
1406         DRM_ERROR("No connected audio pins found!\n");
1407         return NULL;
1408 }
1409
1410 static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1411 {
1412         struct amdgpu_device *adev = encoder->dev->dev_private;
1413         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1414         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1415         u32 tmp;
1416
1417         if (!dig || !dig->afmt || !dig->afmt->pin)
1418                 return;
1419
1420         tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1421         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1422         WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1423 }
1424
1425 static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder,
1426                                                 struct drm_display_mode *mode)
1427 {
1428         struct amdgpu_device *adev = encoder->dev->dev_private;
1429         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1430         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1431         struct drm_connector *connector;
1432         struct amdgpu_connector *amdgpu_connector = NULL;
1433         u32 tmp;
1434         int interlace = 0;
1435
1436         if (!dig || !dig->afmt || !dig->afmt->pin)
1437                 return;
1438
1439         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1440                 if (connector->encoder == encoder) {
1441                         amdgpu_connector = to_amdgpu_connector(connector);
1442                         break;
1443                 }
1444         }
1445
1446         if (!amdgpu_connector) {
1447                 DRM_ERROR("Couldn't find encoder's connector\n");
1448                 return;
1449         }
1450
1451         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1452                 interlace = 1;
1453         if (connector->latency_present[interlace]) {
1454                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1455                                     VIDEO_LIPSYNC, connector->video_latency[interlace]);
1456                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1457                                     AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1458         } else {
1459                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1460                                     VIDEO_LIPSYNC, 0);
1461                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1462                                     AUDIO_LIPSYNC, 0);
1463         }
1464         WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1465                            ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1466 }
1467
1468 static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1469 {
1470         struct amdgpu_device *adev = encoder->dev->dev_private;
1471         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1472         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1473         struct drm_connector *connector;
1474         struct amdgpu_connector *amdgpu_connector = NULL;
1475         u32 tmp;
1476         u8 *sadb = NULL;
1477         int sad_count;
1478
1479         if (!dig || !dig->afmt || !dig->afmt->pin)
1480                 return;
1481
1482         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1483                 if (connector->encoder == encoder) {
1484                         amdgpu_connector = to_amdgpu_connector(connector);
1485                         break;
1486                 }
1487         }
1488
1489         if (!amdgpu_connector) {
1490                 DRM_ERROR("Couldn't find encoder's connector\n");
1491                 return;
1492         }
1493
1494         sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1495         if (sad_count < 0) {
1496                 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1497                 sad_count = 0;
1498         }
1499
1500         /* program the speaker allocation */
1501         tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1502                                  ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1503         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1504                             DP_CONNECTION, 0);
1505         /* set HDMI mode */
1506         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1507                             HDMI_CONNECTION, 1);
1508         if (sad_count)
1509                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1510                                     SPEAKER_ALLOCATION, sadb[0]);
1511         else
1512                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1513                                     SPEAKER_ALLOCATION, 5); /* stereo */
1514         WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1515                            ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1516
1517         kfree(sadb);
1518 }
1519
1520 static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder)
1521 {
1522         struct amdgpu_device *adev = encoder->dev->dev_private;
1523         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1524         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1525         struct drm_connector *connector;
1526         struct amdgpu_connector *amdgpu_connector = NULL;
1527         struct cea_sad *sads;
1528         int i, sad_count;
1529
1530         static const u16 eld_reg_to_type[][2] = {
1531                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1532                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1533                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1534                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1535                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1536                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1537                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1538                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1539                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1540                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1541                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1542                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1543         };
1544
1545         if (!dig || !dig->afmt || !dig->afmt->pin)
1546                 return;
1547
1548         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1549                 if (connector->encoder == encoder) {
1550                         amdgpu_connector = to_amdgpu_connector(connector);
1551                         break;
1552                 }
1553         }
1554
1555         if (!amdgpu_connector) {
1556                 DRM_ERROR("Couldn't find encoder's connector\n");
1557                 return;
1558         }
1559
1560         sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1561         if (sad_count <= 0) {
1562                 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1563                 return;
1564         }
1565         BUG_ON(!sads);
1566
1567         for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1568                 u32 tmp = 0;
1569                 u8 stereo_freqs = 0;
1570                 int max_channels = -1;
1571                 int j;
1572
1573                 for (j = 0; j < sad_count; j++) {
1574                         struct cea_sad *sad = &sads[j];
1575
1576                         if (sad->format == eld_reg_to_type[i][1]) {
1577                                 if (sad->channels > max_channels) {
1578                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1579                                                             MAX_CHANNELS, sad->channels);
1580                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1581                                                             DESCRIPTOR_BYTE_2, sad->byte2);
1582                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1583                                                             SUPPORTED_FREQUENCIES, sad->freq);
1584                                         max_channels = sad->channels;
1585                                 }
1586
1587                                 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1588                                         stereo_freqs |= sad->freq;
1589                                 else
1590                                         break;
1591                         }
1592                 }
1593
1594                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1595                                     SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1596                 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1597         }
1598
1599         kfree(sads);
1600 }
1601
1602 static void dce_v11_0_audio_enable(struct amdgpu_device *adev,
1603                                   struct amdgpu_audio_pin *pin,
1604                                   bool enable)
1605 {
1606         if (!pin)
1607                 return;
1608
1609         WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1610                            enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1611 }
1612
1613 static const u32 pin_offsets[] =
1614 {
1615         AUD0_REGISTER_OFFSET,
1616         AUD1_REGISTER_OFFSET,
1617         AUD2_REGISTER_OFFSET,
1618         AUD3_REGISTER_OFFSET,
1619         AUD4_REGISTER_OFFSET,
1620         AUD5_REGISTER_OFFSET,
1621         AUD6_REGISTER_OFFSET,
1622 };
1623
1624 static int dce_v11_0_audio_init(struct amdgpu_device *adev)
1625 {
1626         int i;
1627
1628         if (!amdgpu_audio)
1629                 return 0;
1630
1631         adev->mode_info.audio.enabled = true;
1632
1633         adev->mode_info.audio.num_pins = 7;
1634
1635         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1636                 adev->mode_info.audio.pin[i].channels = -1;
1637                 adev->mode_info.audio.pin[i].rate = -1;
1638                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1639                 adev->mode_info.audio.pin[i].status_bits = 0;
1640                 adev->mode_info.audio.pin[i].category_code = 0;
1641                 adev->mode_info.audio.pin[i].connected = false;
1642                 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1643                 adev->mode_info.audio.pin[i].id = i;
1644                 /* disable audio.  it will be set up later */
1645                 /* XXX remove once we switch to ip funcs */
1646                 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1647         }
1648
1649         return 0;
1650 }
1651
1652 static void dce_v11_0_audio_fini(struct amdgpu_device *adev)
1653 {
1654         int i;
1655
1656         if (!adev->mode_info.audio.enabled)
1657                 return;
1658
1659         for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1660                 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1661
1662         adev->mode_info.audio.enabled = false;
1663 }
1664
1665 /*
1666  * update the N and CTS parameters for a given pixel clock rate
1667  */
1668 static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1669 {
1670         struct drm_device *dev = encoder->dev;
1671         struct amdgpu_device *adev = dev->dev_private;
1672         struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1673         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1674         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1675         u32 tmp;
1676
1677         tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1678         tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1679         WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1680         tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1681         tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1682         WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1683
1684         tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1685         tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1686         WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1687         tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1688         tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1689         WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1690
1691         tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1692         tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1693         WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1694         tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1695         tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1696         WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1697
1698 }
1699
1700 /*
1701  * build a HDMI Video Info Frame
1702  */
1703 static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1704                                                void *buffer, size_t size)
1705 {
1706         struct drm_device *dev = encoder->dev;
1707         struct amdgpu_device *adev = dev->dev_private;
1708         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1709         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1710         uint8_t *frame = buffer + 3;
1711         uint8_t *header = buffer;
1712
1713         WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1714                 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1715         WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1716                 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1717         WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1718                 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1719         WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1720                 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1721 }
1722
1723 static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1724 {
1725         struct drm_device *dev = encoder->dev;
1726         struct amdgpu_device *adev = dev->dev_private;
1727         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1728         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1729         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1730         u32 dto_phase = 24 * 1000;
1731         u32 dto_modulo = clock;
1732         u32 tmp;
1733
1734         if (!dig || !dig->afmt)
1735                 return;
1736
1737         /* XXX two dtos; generally use dto0 for hdmi */
1738         /* Express [24MHz / target pixel clock] as an exact rational
1739          * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
1740          * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1741          */
1742         tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1743         tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1744                             amdgpu_crtc->crtc_id);
1745         WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1746         WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1747         WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1748 }
1749
1750 /*
1751  * update the info frames with the data from the current display mode
1752  */
1753 static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder,
1754                                   struct drm_display_mode *mode)
1755 {
1756         struct drm_device *dev = encoder->dev;
1757         struct amdgpu_device *adev = dev->dev_private;
1758         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1759         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1760         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1761         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1762         struct hdmi_avi_infoframe frame;
1763         ssize_t err;
1764         u32 tmp;
1765         int bpc = 8;
1766
1767         if (!dig || !dig->afmt)
1768                 return;
1769
1770         /* Silent, r600_hdmi_enable will raise WARN for us */
1771         if (!dig->afmt->enabled)
1772                 return;
1773
1774         /* hdmi deep color mode general control packets setup, if bpc > 8 */
1775         if (encoder->crtc) {
1776                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1777                 bpc = amdgpu_crtc->bpc;
1778         }
1779
1780         /* disable audio prior to setting up hw */
1781         dig->afmt->pin = dce_v11_0_audio_get_pin(adev);
1782         dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1783
1784         dce_v11_0_audio_set_dto(encoder, mode->clock);
1785
1786         tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1787         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1788         WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1789
1790         WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1791
1792         tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1793         switch (bpc) {
1794         case 0:
1795         case 6:
1796         case 8:
1797         case 16:
1798         default:
1799                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1800                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1801                 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1802                           connector->name, bpc);
1803                 break;
1804         case 10:
1805                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1806                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1807                 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1808                           connector->name);
1809                 break;
1810         case 12:
1811                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1812                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1813                 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1814                           connector->name);
1815                 break;
1816         }
1817         WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1818
1819         tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1820         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1821         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1822         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1823         WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1824
1825         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1826         /* enable audio info frames (frames won't be set until audio is enabled) */
1827         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1828         /* required for audio info values to be updated */
1829         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1830         WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1831
1832         tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1833         /* required for audio info values to be updated */
1834         tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1835         WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1836
1837         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1838         /* anything other than 0 */
1839         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1840         WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1841
1842         WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1843
1844         tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1845         /* set the default audio delay */
1846         tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1847         /* should be suffient for all audio modes and small enough for all hblanks */
1848         tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1849         WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1850
1851         tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1852         /* allow 60958 channel status fields to be updated */
1853         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1854         WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1855
1856         tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1857         if (bpc > 8)
1858                 /* clear SW CTS value */
1859                 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1860         else
1861                 /* select SW CTS value */
1862                 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1863         /* allow hw to sent ACR packets when required */
1864         tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1865         WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1866
1867         dce_v11_0_afmt_update_ACR(encoder, mode->clock);
1868
1869         tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1870         tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1871         WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1872
1873         tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1874         tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1875         WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1876
1877         tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1878         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1879         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1880         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1881         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1882         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1883         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1884         WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1885
1886         dce_v11_0_audio_write_speaker_allocation(encoder);
1887
1888         WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1889                (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1890
1891         dce_v11_0_afmt_audio_select_pin(encoder);
1892         dce_v11_0_audio_write_sad_regs(encoder);
1893         dce_v11_0_audio_write_latency_fields(encoder, mode);
1894
1895         err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1896         if (err < 0) {
1897                 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1898                 return;
1899         }
1900
1901         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1902         if (err < 0) {
1903                 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1904                 return;
1905         }
1906
1907         dce_v11_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1908
1909         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1910         /* enable AVI info frames */
1911         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1912         /* required for audio info values to be updated */
1913         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1914         WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1915
1916         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1917         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1918         WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1919
1920         tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1921         /* send audio packets */
1922         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1923         WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1924
1925         WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1926         WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1927         WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1928         WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1929
1930         /* enable audio after to setting up hw */
1931         dce_v11_0_audio_enable(adev, dig->afmt->pin, true);
1932 }
1933
1934 static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1935 {
1936         struct drm_device *dev = encoder->dev;
1937         struct amdgpu_device *adev = dev->dev_private;
1938         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1939         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1940
1941         if (!dig || !dig->afmt)
1942                 return;
1943
1944         /* Silent, r600_hdmi_enable will raise WARN for us */
1945         if (enable && dig->afmt->enabled)
1946                 return;
1947         if (!enable && !dig->afmt->enabled)
1948                 return;
1949
1950         if (!enable && dig->afmt->pin) {
1951                 dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1952                 dig->afmt->pin = NULL;
1953         }
1954
1955         dig->afmt->enabled = enable;
1956
1957         DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1958                   enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1959 }
1960
1961 static void dce_v11_0_afmt_init(struct amdgpu_device *adev)
1962 {
1963         int i;
1964
1965         for (i = 0; i < adev->mode_info.num_dig; i++)
1966                 adev->mode_info.afmt[i] = NULL;
1967
1968         /* DCE11 has audio blocks tied to DIG encoders */
1969         for (i = 0; i < adev->mode_info.num_dig; i++) {
1970                 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1971                 if (adev->mode_info.afmt[i]) {
1972                         adev->mode_info.afmt[i]->offset = dig_offsets[i];
1973                         adev->mode_info.afmt[i]->id = i;
1974                 }
1975         }
1976 }
1977
1978 static void dce_v11_0_afmt_fini(struct amdgpu_device *adev)
1979 {
1980         int i;
1981
1982         for (i = 0; i < adev->mode_info.num_dig; i++) {
1983                 kfree(adev->mode_info.afmt[i]);
1984                 adev->mode_info.afmt[i] = NULL;
1985         }
1986 }
1987
1988 static const u32 vga_control_regs[6] =
1989 {
1990         mmD1VGA_CONTROL,
1991         mmD2VGA_CONTROL,
1992         mmD3VGA_CONTROL,
1993         mmD4VGA_CONTROL,
1994         mmD5VGA_CONTROL,
1995         mmD6VGA_CONTROL,
1996 };
1997
1998 static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable)
1999 {
2000         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2001         struct drm_device *dev = crtc->dev;
2002         struct amdgpu_device *adev = dev->dev_private;
2003         u32 vga_control;
2004
2005         vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
2006         if (enable)
2007                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
2008         else
2009                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
2010 }
2011
2012 static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable)
2013 {
2014         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2015         struct drm_device *dev = crtc->dev;
2016         struct amdgpu_device *adev = dev->dev_private;
2017
2018         if (enable)
2019                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
2020         else
2021                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
2022 }
2023
2024 static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc,
2025                                      struct drm_framebuffer *fb,
2026                                      int x, int y, int atomic)
2027 {
2028         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2029         struct drm_device *dev = crtc->dev;
2030         struct amdgpu_device *adev = dev->dev_private;
2031         struct amdgpu_framebuffer *amdgpu_fb;
2032         struct drm_framebuffer *target_fb;
2033         struct drm_gem_object *obj;
2034         struct amdgpu_bo *rbo;
2035         uint64_t fb_location, tiling_flags;
2036         uint32_t fb_format, fb_pitch_pixels;
2037         u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
2038         u32 pipe_config;
2039         u32 tmp, viewport_w, viewport_h;
2040         int r;
2041         bool bypass_lut = false;
2042
2043         /* no fb bound */
2044         if (!atomic && !crtc->primary->fb) {
2045                 DRM_DEBUG_KMS("No FB bound\n");
2046                 return 0;
2047         }
2048
2049         if (atomic) {
2050                 amdgpu_fb = to_amdgpu_framebuffer(fb);
2051                 target_fb = fb;
2052         }
2053         else {
2054                 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2055                 target_fb = crtc->primary->fb;
2056         }
2057
2058         /* If atomic, assume fb object is pinned & idle & fenced and
2059          * just update base pointers
2060          */
2061         obj = amdgpu_fb->obj;
2062         rbo = gem_to_amdgpu_bo(obj);
2063         r = amdgpu_bo_reserve(rbo, false);
2064         if (unlikely(r != 0))
2065                 return r;
2066
2067         if (atomic)
2068                 fb_location = amdgpu_bo_gpu_offset(rbo);
2069         else {
2070                 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
2071                 if (unlikely(r != 0)) {
2072                         amdgpu_bo_unreserve(rbo);
2073                         return -EINVAL;
2074                 }
2075         }
2076
2077         amdgpu_bo_get_tiling_flags(rbo, &tiling_flags);
2078         amdgpu_bo_unreserve(rbo);
2079
2080         pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2081
2082         switch (target_fb->pixel_format) {
2083         case DRM_FORMAT_C8:
2084                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
2085                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2086                 break;
2087         case DRM_FORMAT_XRGB4444:
2088         case DRM_FORMAT_ARGB4444:
2089                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2090                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
2091 #ifdef __BIG_ENDIAN
2092                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2093                                         ENDIAN_8IN16);
2094 #endif
2095                 break;
2096         case DRM_FORMAT_XRGB1555:
2097         case DRM_FORMAT_ARGB1555:
2098                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2099                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2100 #ifdef __BIG_ENDIAN
2101                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2102                                         ENDIAN_8IN16);
2103 #endif
2104                 break;
2105         case DRM_FORMAT_BGRX5551:
2106         case DRM_FORMAT_BGRA5551:
2107                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2108                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
2109 #ifdef __BIG_ENDIAN
2110                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2111                                         ENDIAN_8IN16);
2112 #endif
2113                 break;
2114         case DRM_FORMAT_RGB565:
2115                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
2116                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2117 #ifdef __BIG_ENDIAN
2118                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2119                                         ENDIAN_8IN16);
2120 #endif
2121                 break;
2122         case DRM_FORMAT_XRGB8888:
2123         case DRM_FORMAT_ARGB8888:
2124                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2125                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2126 #ifdef __BIG_ENDIAN
2127                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2128                                         ENDIAN_8IN32);
2129 #endif
2130                 break;
2131         case DRM_FORMAT_XRGB2101010:
2132         case DRM_FORMAT_ARGB2101010:
2133                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2134                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
2135 #ifdef __BIG_ENDIAN
2136                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2137                                         ENDIAN_8IN32);
2138 #endif
2139                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2140                 bypass_lut = true;
2141                 break;
2142         case DRM_FORMAT_BGRX1010102:
2143         case DRM_FORMAT_BGRA1010102:
2144                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2145                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
2146 #ifdef __BIG_ENDIAN
2147                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2148                                         ENDIAN_8IN32);
2149 #endif
2150                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2151                 bypass_lut = true;
2152                 break;
2153         default:
2154                 DRM_ERROR("Unsupported screen format %s\n",
2155                         drm_get_format_name(target_fb->pixel_format));
2156                 return -EINVAL;
2157         }
2158
2159         if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2160                 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
2161
2162                 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2163                 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2164                 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2165                 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2166                 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2167
2168                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
2169                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2170                                           ARRAY_2D_TILED_THIN1);
2171                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
2172                                           tile_split);
2173                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
2174                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
2175                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
2176                                           mtaspect);
2177                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2178                                           ADDR_SURF_MICRO_TILING_DISPLAY);
2179         } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2180                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2181                                           ARRAY_1D_TILED_THIN1);
2182         }
2183
2184         fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2185                                   pipe_config);
2186
2187         dce_v11_0_vga_enable(crtc, false);
2188
2189         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2190                upper_32_bits(fb_location));
2191         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2192                upper_32_bits(fb_location));
2193         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2194                (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2195         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2196                (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2197         WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2198         WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2199
2200         /*
2201          * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2202          * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2203          * retain the full precision throughout the pipeline.
2204          */
2205         tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2206         if (bypass_lut)
2207                 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2208         else
2209                 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2210         WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2211
2212         if (bypass_lut)
2213                 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2214
2215         WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2216         WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2217         WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2218         WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2219         WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2220         WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2221
2222         fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
2223         WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2224
2225         dce_v11_0_grph_enable(crtc, true);
2226
2227         WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2228                target_fb->height);
2229
2230         x &= ~3;
2231         y &= ~1;
2232         WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2233                (x << 16) | y);
2234         viewport_w = crtc->mode.hdisplay;
2235         viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2236         WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2237                (viewport_w << 16) | viewport_h);
2238
2239         /* pageflip setup */
2240         /* make sure flip is at vb rather than hb */
2241         tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2242         tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2243                             GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2244         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2245
2246         /* set pageflip to happen only at start of vblank interval (front porch) */
2247         WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3);
2248
2249         if (!atomic && fb && fb != crtc->primary->fb) {
2250                 amdgpu_fb = to_amdgpu_framebuffer(fb);
2251                 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2252                 r = amdgpu_bo_reserve(rbo, false);
2253                 if (unlikely(r != 0))
2254                         return r;
2255                 amdgpu_bo_unpin(rbo);
2256                 amdgpu_bo_unreserve(rbo);
2257         }
2258
2259         /* Bytes per pixel may have changed */
2260         dce_v11_0_bandwidth_update(adev);
2261
2262         return 0;
2263 }
2264
2265 static void dce_v11_0_set_interleave(struct drm_crtc *crtc,
2266                                      struct drm_display_mode *mode)
2267 {
2268         struct drm_device *dev = crtc->dev;
2269         struct amdgpu_device *adev = dev->dev_private;
2270         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2271         u32 tmp;
2272
2273         tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2274         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2275                 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2276         else
2277                 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2278         WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2279 }
2280
2281 static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc)
2282 {
2283         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2284         struct drm_device *dev = crtc->dev;
2285         struct amdgpu_device *adev = dev->dev_private;
2286         int i;
2287         u32 tmp;
2288
2289         DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2290
2291         tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2292         tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2293         WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2294
2295         tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2296         tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2297         WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2298
2299         tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2300         tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2301         WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2302
2303         WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2304
2305         WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2306         WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2307         WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2308
2309         WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2310         WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2311         WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2312
2313         WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2314         WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2315
2316         WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2317         for (i = 0; i < 256; i++) {
2318                 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2319                        (amdgpu_crtc->lut_r[i] << 20) |
2320                        (amdgpu_crtc->lut_g[i] << 10) |
2321                        (amdgpu_crtc->lut_b[i] << 0));
2322         }
2323
2324         tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2325         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2326         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2327         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0);
2328         WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2329
2330         tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2331         tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2332         WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2333
2334         tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2335         tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2336         WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2337
2338         tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2339         tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2340         WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2341
2342         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2343         WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2344         /* XXX this only needs to be programmed once per crtc at startup,
2345          * not sure where the best place for it is
2346          */
2347         tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2348         tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2349         WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2350 }
2351
2352 static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder)
2353 {
2354         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2355         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2356
2357         switch (amdgpu_encoder->encoder_id) {
2358         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2359                 if (dig->linkb)
2360                         return 1;
2361                 else
2362                         return 0;
2363                 break;
2364         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2365                 if (dig->linkb)
2366                         return 3;
2367                 else
2368                         return 2;
2369                 break;
2370         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2371                 if (dig->linkb)
2372                         return 5;
2373                 else
2374                         return 4;
2375                 break;
2376         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2377                 return 6;
2378                 break;
2379         default:
2380                 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2381                 return 0;
2382         }
2383 }
2384
2385 /**
2386  * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc.
2387  *
2388  * @crtc: drm crtc
2389  *
2390  * Returns the PPLL (Pixel PLL) to be used by the crtc.  For DP monitors
2391  * a single PPLL can be used for all DP crtcs/encoders.  For non-DP
2392  * monitors a dedicated PPLL must be used.  If a particular board has
2393  * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2394  * as there is no need to program the PLL itself.  If we are not able to
2395  * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2396  * avoid messing up an existing monitor.
2397  *
2398  * Asic specific PLL information
2399  *
2400  * DCE 10.x
2401  * Tonga
2402  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2403  * CI
2404  * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2405  *
2406  */
2407 static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc)
2408 {
2409         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2410         struct drm_device *dev = crtc->dev;
2411         struct amdgpu_device *adev = dev->dev_private;
2412         u32 pll_in_use;
2413         int pll;
2414
2415         if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2416                 if (adev->clock.dp_extclk)
2417                         /* skip PPLL programming if using ext clock */
2418                         return ATOM_PPLL_INVALID;
2419                 else {
2420                         /* use the same PPLL for all DP monitors */
2421                         pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2422                         if (pll != ATOM_PPLL_INVALID)
2423                                 return pll;
2424                 }
2425         } else {
2426                 /* use the same PPLL for all monitors with the same clock */
2427                 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2428                 if (pll != ATOM_PPLL_INVALID)
2429                         return pll;
2430         }
2431
2432         /* XXX need to determine what plls are available on each DCE11 part */
2433         pll_in_use = amdgpu_pll_get_use_mask(crtc);
2434         if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) {
2435                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2436                         return ATOM_PPLL1;
2437                 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2438                         return ATOM_PPLL0;
2439                 DRM_ERROR("unable to allocate a PPLL\n");
2440                 return ATOM_PPLL_INVALID;
2441         } else {
2442                 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2443                         return ATOM_PPLL2;
2444                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2445                         return ATOM_PPLL1;
2446                 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2447                         return ATOM_PPLL0;
2448                 DRM_ERROR("unable to allocate a PPLL\n");
2449                 return ATOM_PPLL_INVALID;
2450         }
2451         return ATOM_PPLL_INVALID;
2452 }
2453
2454 static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2455 {
2456         struct amdgpu_device *adev = crtc->dev->dev_private;
2457         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2458         uint32_t cur_lock;
2459
2460         cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2461         if (lock)
2462                 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2463         else
2464                 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2465         WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2466 }
2467
2468 static void dce_v11_0_hide_cursor(struct drm_crtc *crtc)
2469 {
2470         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2471         struct amdgpu_device *adev = crtc->dev->dev_private;
2472         u32 tmp;
2473
2474         tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2475         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2476         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2477 }
2478
2479 static void dce_v11_0_show_cursor(struct drm_crtc *crtc)
2480 {
2481         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2482         struct amdgpu_device *adev = crtc->dev->dev_private;
2483         u32 tmp;
2484
2485         WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2486                upper_32_bits(amdgpu_crtc->cursor_addr));
2487         WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2488                lower_32_bits(amdgpu_crtc->cursor_addr));
2489
2490         tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2491         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2492         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2493         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2494 }
2495
2496 static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc,
2497                                         int x, int y)
2498 {
2499         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2500         struct amdgpu_device *adev = crtc->dev->dev_private;
2501         int xorigin = 0, yorigin = 0;
2502
2503         /* avivo cursor are offset into the total surface */
2504         x += crtc->x;
2505         y += crtc->y;
2506         DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2507
2508         if (x < 0) {
2509                 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2510                 x = 0;
2511         }
2512         if (y < 0) {
2513                 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2514                 y = 0;
2515         }
2516
2517         WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2518         WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2519         WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2520                ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2521
2522         amdgpu_crtc->cursor_x = x;
2523         amdgpu_crtc->cursor_y = y;
2524
2525         return 0;
2526 }
2527
2528 static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc,
2529                                       int x, int y)
2530 {
2531         int ret;
2532
2533         dce_v11_0_lock_cursor(crtc, true);
2534         ret = dce_v11_0_cursor_move_locked(crtc, x, y);
2535         dce_v11_0_lock_cursor(crtc, false);
2536
2537         return ret;
2538 }
2539
2540 static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc,
2541                                       struct drm_file *file_priv,
2542                                       uint32_t handle,
2543                                       uint32_t width,
2544                                       uint32_t height,
2545                                       int32_t hot_x,
2546                                       int32_t hot_y)
2547 {
2548         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2549         struct drm_gem_object *obj;
2550         struct amdgpu_bo *aobj;
2551         int ret;
2552
2553         if (!handle) {
2554                 /* turn off cursor */
2555                 dce_v11_0_hide_cursor(crtc);
2556                 obj = NULL;
2557                 goto unpin;
2558         }
2559
2560         if ((width > amdgpu_crtc->max_cursor_width) ||
2561             (height > amdgpu_crtc->max_cursor_height)) {
2562                 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2563                 return -EINVAL;
2564         }
2565
2566         obj = drm_gem_object_lookup(crtc->dev, file_priv, handle);
2567         if (!obj) {
2568                 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2569                 return -ENOENT;
2570         }
2571
2572         aobj = gem_to_amdgpu_bo(obj);
2573         ret = amdgpu_bo_reserve(aobj, false);
2574         if (ret != 0) {
2575                 drm_gem_object_unreference_unlocked(obj);
2576                 return ret;
2577         }
2578
2579         ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
2580         amdgpu_bo_unreserve(aobj);
2581         if (ret) {
2582                 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2583                 drm_gem_object_unreference_unlocked(obj);
2584                 return ret;
2585         }
2586
2587         amdgpu_crtc->cursor_width = width;
2588         amdgpu_crtc->cursor_height = height;
2589
2590         dce_v11_0_lock_cursor(crtc, true);
2591
2592         if (hot_x != amdgpu_crtc->cursor_hot_x ||
2593             hot_y != amdgpu_crtc->cursor_hot_y) {
2594                 int x, y;
2595
2596                 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2597                 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2598
2599                 dce_v11_0_cursor_move_locked(crtc, x, y);
2600
2601                 amdgpu_crtc->cursor_hot_x = hot_x;
2602                 amdgpu_crtc->cursor_hot_y = hot_y;
2603         }
2604
2605         dce_v11_0_show_cursor(crtc);
2606         dce_v11_0_lock_cursor(crtc, false);
2607
2608 unpin:
2609         if (amdgpu_crtc->cursor_bo) {
2610                 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2611                 ret = amdgpu_bo_reserve(aobj, false);
2612                 if (likely(ret == 0)) {
2613                         amdgpu_bo_unpin(aobj);
2614                         amdgpu_bo_unreserve(aobj);
2615                 }
2616                 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
2617         }
2618
2619         amdgpu_crtc->cursor_bo = obj;
2620         return 0;
2621 }
2622
2623 static void dce_v11_0_cursor_reset(struct drm_crtc *crtc)
2624 {
2625         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2626
2627         if (amdgpu_crtc->cursor_bo) {
2628                 dce_v11_0_lock_cursor(crtc, true);
2629
2630                 dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2631                                              amdgpu_crtc->cursor_y);
2632
2633                 dce_v11_0_show_cursor(crtc);
2634
2635                 dce_v11_0_lock_cursor(crtc, false);
2636         }
2637 }
2638
2639 static void dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2640                                     u16 *blue, uint32_t start, uint32_t size)
2641 {
2642         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2643         int end = (start + size > 256) ? 256 : start + size, i;
2644
2645         /* userspace palettes are always correct as is */
2646         for (i = start; i < end; i++) {
2647                 amdgpu_crtc->lut_r[i] = red[i] >> 6;
2648                 amdgpu_crtc->lut_g[i] = green[i] >> 6;
2649                 amdgpu_crtc->lut_b[i] = blue[i] >> 6;
2650         }
2651         dce_v11_0_crtc_load_lut(crtc);
2652 }
2653
2654 static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc)
2655 {
2656         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2657
2658         drm_crtc_cleanup(crtc);
2659         destroy_workqueue(amdgpu_crtc->pflip_queue);
2660         kfree(amdgpu_crtc);
2661 }
2662
2663 static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = {
2664         .cursor_set2 = dce_v11_0_crtc_cursor_set2,
2665         .cursor_move = dce_v11_0_crtc_cursor_move,
2666         .gamma_set = dce_v11_0_crtc_gamma_set,
2667         .set_config = amdgpu_crtc_set_config,
2668         .destroy = dce_v11_0_crtc_destroy,
2669         .page_flip = amdgpu_crtc_page_flip,
2670 };
2671
2672 static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2673 {
2674         struct drm_device *dev = crtc->dev;
2675         struct amdgpu_device *adev = dev->dev_private;
2676         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2677         unsigned type;
2678
2679         switch (mode) {
2680         case DRM_MODE_DPMS_ON:
2681                 amdgpu_crtc->enabled = true;
2682                 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2683                 dce_v11_0_vga_enable(crtc, true);
2684                 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2685                 dce_v11_0_vga_enable(crtc, false);
2686                 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2687                 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2688                 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2689                 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2690                 drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id);
2691                 dce_v11_0_crtc_load_lut(crtc);
2692                 break;
2693         case DRM_MODE_DPMS_STANDBY:
2694         case DRM_MODE_DPMS_SUSPEND:
2695         case DRM_MODE_DPMS_OFF:
2696                 drm_vblank_pre_modeset(dev, amdgpu_crtc->crtc_id);
2697                 if (amdgpu_crtc->enabled) {
2698                         dce_v11_0_vga_enable(crtc, true);
2699                         amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2700                         dce_v11_0_vga_enable(crtc, false);
2701                 }
2702                 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2703                 amdgpu_crtc->enabled = false;
2704                 break;
2705         }
2706         /* adjust pm to dpms */
2707         amdgpu_pm_compute_clocks(adev);
2708 }
2709
2710 static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc)
2711 {
2712         /* disable crtc pair power gating before programming */
2713         amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2714         amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2715         dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2716 }
2717
2718 static void dce_v11_0_crtc_commit(struct drm_crtc *crtc)
2719 {
2720         dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2721         amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2722 }
2723
2724 static void dce_v11_0_crtc_disable(struct drm_crtc *crtc)
2725 {
2726         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2727         struct drm_device *dev = crtc->dev;
2728         struct amdgpu_device *adev = dev->dev_private;
2729         struct amdgpu_atom_ss ss;
2730         int i;
2731
2732         dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2733         if (crtc->primary->fb) {
2734                 int r;
2735                 struct amdgpu_framebuffer *amdgpu_fb;
2736                 struct amdgpu_bo *rbo;
2737
2738                 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2739                 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2740                 r = amdgpu_bo_reserve(rbo, false);
2741                 if (unlikely(r))
2742                         DRM_ERROR("failed to reserve rbo before unpin\n");
2743                 else {
2744                         amdgpu_bo_unpin(rbo);
2745                         amdgpu_bo_unreserve(rbo);
2746                 }
2747         }
2748         /* disable the GRPH */
2749         dce_v11_0_grph_enable(crtc, false);
2750
2751         amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2752
2753         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2754                 if (adev->mode_info.crtcs[i] &&
2755                     adev->mode_info.crtcs[i]->enabled &&
2756                     i != amdgpu_crtc->crtc_id &&
2757                     amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2758                         /* one other crtc is using this pll don't turn
2759                          * off the pll
2760                          */
2761                         goto done;
2762                 }
2763         }
2764
2765         switch (amdgpu_crtc->pll_id) {
2766         case ATOM_PPLL0:
2767         case ATOM_PPLL1:
2768         case ATOM_PPLL2:
2769                 /* disable the ppll */
2770                 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2771                                           0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2772                 break;
2773         default:
2774                 break;
2775         }
2776 done:
2777         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2778         amdgpu_crtc->adjusted_clock = 0;
2779         amdgpu_crtc->encoder = NULL;
2780         amdgpu_crtc->connector = NULL;
2781 }
2782
2783 static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc,
2784                                   struct drm_display_mode *mode,
2785                                   struct drm_display_mode *adjusted_mode,
2786                                   int x, int y, struct drm_framebuffer *old_fb)
2787 {
2788         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2789
2790         if (!amdgpu_crtc->adjusted_clock)
2791                 return -EINVAL;
2792
2793         amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2794         amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2795         dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2796         amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2797         amdgpu_atombios_crtc_scaler_setup(crtc);
2798         dce_v11_0_cursor_reset(crtc);
2799         /* update the hw version fpr dpm */
2800         amdgpu_crtc->hw_mode = *adjusted_mode;
2801
2802         return 0;
2803 }
2804
2805 static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc *crtc,
2806                                      const struct drm_display_mode *mode,
2807                                      struct drm_display_mode *adjusted_mode)
2808 {
2809         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2810         struct drm_device *dev = crtc->dev;
2811         struct drm_encoder *encoder;
2812
2813         /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2814         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2815                 if (encoder->crtc == crtc) {
2816                         amdgpu_crtc->encoder = encoder;
2817                         amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2818                         break;
2819                 }
2820         }
2821         if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2822                 amdgpu_crtc->encoder = NULL;
2823                 amdgpu_crtc->connector = NULL;
2824                 return false;
2825         }
2826         if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2827                 return false;
2828         if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2829                 return false;
2830         /* pick pll */
2831         amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc);
2832         /* if we can't get a PPLL for a non-DP encoder, fail */
2833         if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2834             !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2835                 return false;
2836
2837         return true;
2838 }
2839
2840 static int dce_v11_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2841                                   struct drm_framebuffer *old_fb)
2842 {
2843         return dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2844 }
2845
2846 static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2847                                          struct drm_framebuffer *fb,
2848                                          int x, int y, enum mode_set_atomic state)
2849 {
2850        return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1);
2851 }
2852
2853 static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = {
2854         .dpms = dce_v11_0_crtc_dpms,
2855         .mode_fixup = dce_v11_0_crtc_mode_fixup,
2856         .mode_set = dce_v11_0_crtc_mode_set,
2857         .mode_set_base = dce_v11_0_crtc_set_base,
2858         .mode_set_base_atomic = dce_v11_0_crtc_set_base_atomic,
2859         .prepare = dce_v11_0_crtc_prepare,
2860         .commit = dce_v11_0_crtc_commit,
2861         .load_lut = dce_v11_0_crtc_load_lut,
2862         .disable = dce_v11_0_crtc_disable,
2863 };
2864
2865 static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index)
2866 {
2867         struct amdgpu_crtc *amdgpu_crtc;
2868         int i;
2869
2870         amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2871                               (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2872         if (amdgpu_crtc == NULL)
2873                 return -ENOMEM;
2874
2875         drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v11_0_crtc_funcs);
2876
2877         drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2878         amdgpu_crtc->crtc_id = index;
2879         amdgpu_crtc->pflip_queue = create_singlethread_workqueue("amdgpu-pageflip-queue");
2880         adev->mode_info.crtcs[index] = amdgpu_crtc;
2881
2882         amdgpu_crtc->max_cursor_width = 128;
2883         amdgpu_crtc->max_cursor_height = 128;
2884         adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2885         adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2886
2887         for (i = 0; i < 256; i++) {
2888                 amdgpu_crtc->lut_r[i] = i << 2;
2889                 amdgpu_crtc->lut_g[i] = i << 2;
2890                 amdgpu_crtc->lut_b[i] = i << 2;
2891         }
2892
2893         switch (amdgpu_crtc->crtc_id) {
2894         case 0:
2895         default:
2896                 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2897                 break;
2898         case 1:
2899                 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2900                 break;
2901         case 2:
2902                 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2903                 break;
2904         case 3:
2905                 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2906                 break;
2907         case 4:
2908                 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2909                 break;
2910         case 5:
2911                 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2912                 break;
2913         }
2914
2915         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2916         amdgpu_crtc->adjusted_clock = 0;
2917         amdgpu_crtc->encoder = NULL;
2918         amdgpu_crtc->connector = NULL;
2919         drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs);
2920
2921         return 0;
2922 }
2923
2924 static int dce_v11_0_early_init(void *handle)
2925 {
2926         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2927
2928         adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg;
2929         adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg;
2930
2931         dce_v11_0_set_display_funcs(adev);
2932         dce_v11_0_set_irq_funcs(adev);
2933
2934         switch (adev->asic_type) {
2935         case CHIP_CARRIZO:
2936                 adev->mode_info.num_crtc = 3;
2937                 adev->mode_info.num_hpd = 6;
2938                 adev->mode_info.num_dig = 9;
2939                 break;
2940         case CHIP_STONEY:
2941                 adev->mode_info.num_crtc = 2;
2942                 adev->mode_info.num_hpd = 6;
2943                 adev->mode_info.num_dig = 9;
2944                 break;
2945         default:
2946                 /* FIXME: not supported yet */
2947                 return -EINVAL;
2948         }
2949
2950         return 0;
2951 }
2952
2953 static int dce_v11_0_sw_init(void *handle)
2954 {
2955         int r, i;
2956         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2957
2958         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2959                 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
2960                 if (r)
2961                 return r;
2962         }
2963
2964         for (i = 8; i < 20; i += 2) {
2965                 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
2966                 if (r)
2967                         return r;
2968         }
2969
2970         /* HPD hotplug */
2971         r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
2972         if (r)
2973         return r;
2974
2975         adev->mode_info.mode_config_initialized = true;
2976
2977         adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2978
2979         adev->ddev->mode_config.max_width = 16384;
2980         adev->ddev->mode_config.max_height = 16384;
2981
2982         adev->ddev->mode_config.preferred_depth = 24;
2983         adev->ddev->mode_config.prefer_shadow = 1;
2984
2985         adev->ddev->mode_config.fb_base = adev->mc.aper_base;
2986
2987         r = amdgpu_modeset_create_props(adev);
2988         if (r)
2989                 return r;
2990
2991         adev->ddev->mode_config.max_width = 16384;
2992         adev->ddev->mode_config.max_height = 16384;
2993
2994         /* allocate crtcs */
2995         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2996                 r = dce_v11_0_crtc_init(adev, i);
2997                 if (r)
2998                         return r;
2999         }
3000
3001         if (amdgpu_atombios_get_connector_info_from_object_table(adev))
3002                 amdgpu_print_display_setup(adev->ddev);
3003         else
3004                 return -EINVAL;
3005
3006         /* setup afmt */
3007         dce_v11_0_afmt_init(adev);
3008
3009         r = dce_v11_0_audio_init(adev);
3010         if (r)
3011                 return r;
3012
3013         drm_kms_helper_poll_init(adev->ddev);
3014
3015         return r;
3016 }
3017
3018 static int dce_v11_0_sw_fini(void *handle)
3019 {
3020         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3021
3022         kfree(adev->mode_info.bios_hardcoded_edid);
3023
3024         drm_kms_helper_poll_fini(adev->ddev);
3025
3026         dce_v11_0_audio_fini(adev);
3027
3028         dce_v11_0_afmt_fini(adev);
3029
3030         adev->mode_info.mode_config_initialized = false;
3031
3032         return 0;
3033 }
3034
3035 static int dce_v11_0_hw_init(void *handle)
3036 {
3037         int i;
3038         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3039
3040         dce_v11_0_init_golden_registers(adev);
3041
3042         /* init dig PHYs, disp eng pll */
3043         amdgpu_atombios_crtc_powergate_init(adev);
3044         amdgpu_atombios_encoder_init_dig(adev);
3045         amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
3046
3047         /* initialize hpd */
3048         dce_v11_0_hpd_init(adev);
3049
3050         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3051                 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3052         }
3053
3054         dce_v11_0_pageflip_interrupt_init(adev);
3055
3056         return 0;
3057 }
3058
3059 static int dce_v11_0_hw_fini(void *handle)
3060 {
3061         int i;
3062         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3063
3064         dce_v11_0_hpd_fini(adev);
3065
3066         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3067                 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3068         }
3069
3070         dce_v11_0_pageflip_interrupt_fini(adev);
3071
3072         return 0;
3073 }
3074
3075 static int dce_v11_0_suspend(void *handle)
3076 {
3077         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3078
3079         amdgpu_atombios_scratch_regs_save(adev);
3080
3081         return dce_v11_0_hw_fini(handle);
3082 }
3083
3084 static int dce_v11_0_resume(void *handle)
3085 {
3086         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3087         int ret;
3088
3089         ret = dce_v11_0_hw_init(handle);
3090
3091         amdgpu_atombios_scratch_regs_restore(adev);
3092
3093         /* turn on the BL */
3094         if (adev->mode_info.bl_encoder) {
3095                 u8 bl_level = amdgpu_display_backlight_get_level(adev,
3096                                                                   adev->mode_info.bl_encoder);
3097                 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
3098                                                     bl_level);
3099         }
3100
3101         return ret;
3102 }
3103
3104 static bool dce_v11_0_is_idle(void *handle)
3105 {
3106         return true;
3107 }
3108
3109 static int dce_v11_0_wait_for_idle(void *handle)
3110 {
3111         return 0;
3112 }
3113
3114 static void dce_v11_0_print_status(void *handle)
3115 {
3116         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3117
3118         dev_info(adev->dev, "DCE 10.x registers\n");
3119         /* XXX todo */
3120 }
3121
3122 static int dce_v11_0_soft_reset(void *handle)
3123 {
3124         u32 srbm_soft_reset = 0, tmp;
3125         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3126
3127         if (dce_v11_0_is_display_hung(adev))
3128                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3129
3130         if (srbm_soft_reset) {
3131                 dce_v11_0_print_status((void *)adev);
3132
3133                 tmp = RREG32(mmSRBM_SOFT_RESET);
3134                 tmp |= srbm_soft_reset;
3135                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3136                 WREG32(mmSRBM_SOFT_RESET, tmp);
3137                 tmp = RREG32(mmSRBM_SOFT_RESET);
3138
3139                 udelay(50);
3140
3141                 tmp &= ~srbm_soft_reset;
3142                 WREG32(mmSRBM_SOFT_RESET, tmp);
3143                 tmp = RREG32(mmSRBM_SOFT_RESET);
3144
3145                 /* Wait a little for things to settle down */
3146                 udelay(50);
3147                 dce_v11_0_print_status((void *)adev);
3148         }
3149         return 0;
3150 }
3151
3152 static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3153                                                      int crtc,
3154                                                      enum amdgpu_interrupt_state state)
3155 {
3156         u32 lb_interrupt_mask;
3157
3158         if (crtc >= adev->mode_info.num_crtc) {
3159                 DRM_DEBUG("invalid crtc %d\n", crtc);
3160                 return;
3161         }
3162
3163         switch (state) {
3164         case AMDGPU_IRQ_STATE_DISABLE:
3165                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3166                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3167                                                   VBLANK_INTERRUPT_MASK, 0);
3168                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3169                 break;
3170         case AMDGPU_IRQ_STATE_ENABLE:
3171                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3172                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3173                                                   VBLANK_INTERRUPT_MASK, 1);
3174                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3175                 break;
3176         default:
3177                 break;
3178         }
3179 }
3180
3181 static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3182                                                     int crtc,
3183                                                     enum amdgpu_interrupt_state state)
3184 {
3185         u32 lb_interrupt_mask;
3186
3187         if (crtc >= adev->mode_info.num_crtc) {
3188                 DRM_DEBUG("invalid crtc %d\n", crtc);
3189                 return;
3190         }
3191
3192         switch (state) {
3193         case AMDGPU_IRQ_STATE_DISABLE:
3194                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3195                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3196                                                   VLINE_INTERRUPT_MASK, 0);
3197                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3198                 break;
3199         case AMDGPU_IRQ_STATE_ENABLE:
3200                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3201                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3202                                                   VLINE_INTERRUPT_MASK, 1);
3203                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3204                 break;
3205         default:
3206                 break;
3207         }
3208 }
3209
3210 static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev,
3211                                         struct amdgpu_irq_src *source,
3212                                         unsigned hpd,
3213                                         enum amdgpu_interrupt_state state)
3214 {
3215         u32 tmp;
3216
3217         if (hpd >= adev->mode_info.num_hpd) {
3218                 DRM_DEBUG("invalid hdp %d\n", hpd);
3219                 return 0;
3220         }
3221
3222         switch (state) {
3223         case AMDGPU_IRQ_STATE_DISABLE:
3224                 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3225                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3226                 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3227                 break;
3228         case AMDGPU_IRQ_STATE_ENABLE:
3229                 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3230                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3231                 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3232                 break;
3233         default:
3234                 break;
3235         }
3236
3237         return 0;
3238 }
3239
3240 static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev,
3241                                         struct amdgpu_irq_src *source,
3242                                         unsigned type,
3243                                         enum amdgpu_interrupt_state state)
3244 {
3245         switch (type) {
3246         case AMDGPU_CRTC_IRQ_VBLANK1:
3247                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3248                 break;
3249         case AMDGPU_CRTC_IRQ_VBLANK2:
3250                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3251                 break;
3252         case AMDGPU_CRTC_IRQ_VBLANK3:
3253                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3254                 break;
3255         case AMDGPU_CRTC_IRQ_VBLANK4:
3256                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3257                 break;
3258         case AMDGPU_CRTC_IRQ_VBLANK5:
3259                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3260                 break;
3261         case AMDGPU_CRTC_IRQ_VBLANK6:
3262                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3263                 break;
3264         case AMDGPU_CRTC_IRQ_VLINE1:
3265                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 0, state);
3266                 break;
3267         case AMDGPU_CRTC_IRQ_VLINE2:
3268                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 1, state);
3269                 break;
3270         case AMDGPU_CRTC_IRQ_VLINE3:
3271                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 2, state);
3272                 break;
3273         case AMDGPU_CRTC_IRQ_VLINE4:
3274                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 3, state);
3275                 break;
3276         case AMDGPU_CRTC_IRQ_VLINE5:
3277                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state);
3278                 break;
3279          case AMDGPU_CRTC_IRQ_VLINE6:
3280                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state);
3281                 break;
3282         default:
3283                 break;
3284         }
3285         return 0;
3286 }
3287
3288 static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3289                                             struct amdgpu_irq_src *src,
3290                                             unsigned type,
3291                                             enum amdgpu_interrupt_state state)
3292 {
3293         u32 reg;
3294
3295         if (type >= adev->mode_info.num_crtc) {
3296                 DRM_ERROR("invalid pageflip crtc %d\n", type);
3297                 return -EINVAL;
3298         }
3299
3300         reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3301         if (state == AMDGPU_IRQ_STATE_DISABLE)
3302                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3303                        reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3304         else
3305                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3306                        reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3307
3308         return 0;
3309 }
3310
3311 static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev,
3312                                   struct amdgpu_irq_src *source,
3313                                   struct amdgpu_iv_entry *entry)
3314 {
3315         unsigned long flags;
3316         unsigned crtc_id;
3317         struct amdgpu_crtc *amdgpu_crtc;
3318         struct amdgpu_flip_work *works;
3319
3320         crtc_id = (entry->src_id - 8) >> 1;
3321         amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3322
3323         if (crtc_id >= adev->mode_info.num_crtc) {
3324                 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3325                 return -EINVAL;
3326         }
3327
3328         if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3329             GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3330                 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3331                        GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3332
3333         /* IRQ could occur when in initial stage */
3334         if(amdgpu_crtc == NULL)
3335                 return 0;
3336
3337         spin_lock_irqsave(&adev->ddev->event_lock, flags);
3338         works = amdgpu_crtc->pflip_works;
3339         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3340                 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3341                                                  "AMDGPU_FLIP_SUBMITTED(%d)\n",
3342                                                  amdgpu_crtc->pflip_status,
3343                                                  AMDGPU_FLIP_SUBMITTED);
3344                 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3345                 return 0;
3346         }
3347
3348         /* page flip completed. clean up */
3349         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3350         amdgpu_crtc->pflip_works = NULL;
3351
3352         /* wakeup usersapce */
3353         if(works->event)
3354                 drm_send_vblank_event(adev->ddev, crtc_id, works->event);
3355
3356         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3357
3358         drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id);
3359         queue_work(amdgpu_crtc->pflip_queue, &works->unpin_work);
3360
3361         return 0;
3362 }
3363
3364 static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev,
3365                                   int hpd)
3366 {
3367         u32 tmp;
3368
3369         if (hpd >= adev->mode_info.num_hpd) {
3370                 DRM_DEBUG("invalid hdp %d\n", hpd);
3371                 return;
3372         }
3373
3374         tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3375         tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3376         WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3377 }
3378
3379 static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3380                                           int crtc)
3381 {
3382         u32 tmp;
3383
3384         if (crtc >= adev->mode_info.num_crtc) {
3385                 DRM_DEBUG("invalid crtc %d\n", crtc);
3386                 return;
3387         }
3388
3389         tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3390         tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3391         WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3392 }
3393
3394 static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3395                                          int crtc)
3396 {
3397         u32 tmp;
3398
3399         if (crtc >= adev->mode_info.num_crtc) {
3400                 DRM_DEBUG("invalid crtc %d\n", crtc);
3401                 return;
3402         }
3403
3404         tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3405         tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3406         WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3407 }
3408
3409 static int dce_v11_0_crtc_irq(struct amdgpu_device *adev,
3410                                 struct amdgpu_irq_src *source,
3411                                 struct amdgpu_iv_entry *entry)
3412 {
3413         unsigned crtc = entry->src_id - 1;
3414         uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3415         unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
3416
3417         switch (entry->src_data) {
3418         case 0: /* vblank */
3419                 if (disp_int & interrupt_status_offsets[crtc].vblank)
3420                         dce_v11_0_crtc_vblank_int_ack(adev, crtc);
3421                 else
3422                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3423
3424                 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3425                         drm_handle_vblank(adev->ddev, crtc);
3426                 }
3427                 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3428
3429                 break;
3430         case 1: /* vline */
3431                 if (disp_int & interrupt_status_offsets[crtc].vline)
3432                         dce_v11_0_crtc_vline_int_ack(adev, crtc);
3433                 else
3434                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3435
3436                 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3437
3438                 break;
3439         default:
3440                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3441                 break;
3442         }
3443
3444         return 0;
3445 }
3446
3447 static int dce_v11_0_hpd_irq(struct amdgpu_device *adev,
3448                              struct amdgpu_irq_src *source,
3449                              struct amdgpu_iv_entry *entry)
3450 {
3451         uint32_t disp_int, mask;
3452         unsigned hpd;
3453
3454         if (entry->src_data >= adev->mode_info.num_hpd) {
3455                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3456                 return 0;
3457         }
3458
3459         hpd = entry->src_data;
3460         disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3461         mask = interrupt_status_offsets[hpd].hpd;
3462
3463         if (disp_int & mask) {
3464                 dce_v11_0_hpd_int_ack(adev, hpd);
3465                 schedule_work(&adev->hotplug_work);
3466                 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3467         }
3468
3469         return 0;
3470 }
3471
3472 static int dce_v11_0_set_clockgating_state(void *handle,
3473                                           enum amd_clockgating_state state)
3474 {
3475         return 0;
3476 }
3477
3478 static int dce_v11_0_set_powergating_state(void *handle,
3479                                           enum amd_powergating_state state)
3480 {
3481         return 0;
3482 }
3483
3484 const struct amd_ip_funcs dce_v11_0_ip_funcs = {
3485         .early_init = dce_v11_0_early_init,
3486         .late_init = NULL,
3487         .sw_init = dce_v11_0_sw_init,
3488         .sw_fini = dce_v11_0_sw_fini,
3489         .hw_init = dce_v11_0_hw_init,
3490         .hw_fini = dce_v11_0_hw_fini,
3491         .suspend = dce_v11_0_suspend,
3492         .resume = dce_v11_0_resume,
3493         .is_idle = dce_v11_0_is_idle,
3494         .wait_for_idle = dce_v11_0_wait_for_idle,
3495         .soft_reset = dce_v11_0_soft_reset,
3496         .print_status = dce_v11_0_print_status,
3497         .set_clockgating_state = dce_v11_0_set_clockgating_state,
3498         .set_powergating_state = dce_v11_0_set_powergating_state,
3499 };
3500
3501 static void
3502 dce_v11_0_encoder_mode_set(struct drm_encoder *encoder,
3503                           struct drm_display_mode *mode,
3504                           struct drm_display_mode *adjusted_mode)
3505 {
3506         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3507
3508         amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3509
3510         /* need to call this here rather than in prepare() since we need some crtc info */
3511         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3512
3513         /* set scaler clears this on some chips */
3514         dce_v11_0_set_interleave(encoder->crtc, mode);
3515
3516         if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3517                 dce_v11_0_afmt_enable(encoder, true);
3518                 dce_v11_0_afmt_setmode(encoder, adjusted_mode);
3519         }
3520 }
3521
3522 static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder)
3523 {
3524         struct amdgpu_device *adev = encoder->dev->dev_private;
3525         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3526         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3527
3528         if ((amdgpu_encoder->active_device &
3529              (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3530             (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3531              ENCODER_OBJECT_ID_NONE)) {
3532                 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3533                 if (dig) {
3534                         dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder);
3535                         if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3536                                 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3537                 }
3538         }
3539
3540         amdgpu_atombios_scratch_regs_lock(adev, true);
3541
3542         if (connector) {
3543                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3544
3545                 /* select the clock/data port if it uses a router */
3546                 if (amdgpu_connector->router.cd_valid)
3547                         amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3548
3549                 /* turn eDP panel on for mode set */
3550                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3551                         amdgpu_atombios_encoder_set_edp_panel_power(connector,
3552                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
3553         }
3554
3555         /* this is needed for the pll/ss setup to work correctly in some cases */
3556         amdgpu_atombios_encoder_set_crtc_source(encoder);
3557         /* set up the FMT blocks */
3558         dce_v11_0_program_fmt(encoder);
3559 }
3560
3561 static void dce_v11_0_encoder_commit(struct drm_encoder *encoder)
3562 {
3563         struct drm_device *dev = encoder->dev;
3564         struct amdgpu_device *adev = dev->dev_private;
3565
3566         /* need to call this here as we need the crtc set up */
3567         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3568         amdgpu_atombios_scratch_regs_lock(adev, false);
3569 }
3570
3571 static void dce_v11_0_encoder_disable(struct drm_encoder *encoder)
3572 {
3573         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3574         struct amdgpu_encoder_atom_dig *dig;
3575
3576         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3577
3578         if (amdgpu_atombios_encoder_is_digital(encoder)) {
3579                 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3580                         dce_v11_0_afmt_enable(encoder, false);
3581                 dig = amdgpu_encoder->enc_priv;
3582                 dig->dig_encoder = -1;
3583         }
3584         amdgpu_encoder->active_device = 0;
3585 }
3586
3587 /* these are handled by the primary encoders */
3588 static void dce_v11_0_ext_prepare(struct drm_encoder *encoder)
3589 {
3590
3591 }
3592
3593 static void dce_v11_0_ext_commit(struct drm_encoder *encoder)
3594 {
3595
3596 }
3597
3598 static void
3599 dce_v11_0_ext_mode_set(struct drm_encoder *encoder,
3600                       struct drm_display_mode *mode,
3601                       struct drm_display_mode *adjusted_mode)
3602 {
3603
3604 }
3605
3606 static void dce_v11_0_ext_disable(struct drm_encoder *encoder)
3607 {
3608
3609 }
3610
3611 static void
3612 dce_v11_0_ext_dpms(struct drm_encoder *encoder, int mode)
3613 {
3614
3615 }
3616
3617 static bool dce_v11_0_ext_mode_fixup(struct drm_encoder *encoder,
3618                                     const struct drm_display_mode *mode,
3619                                     struct drm_display_mode *adjusted_mode)
3620 {
3621         return true;
3622 }
3623
3624 static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs = {
3625         .dpms = dce_v11_0_ext_dpms,
3626         .mode_fixup = dce_v11_0_ext_mode_fixup,
3627         .prepare = dce_v11_0_ext_prepare,
3628         .mode_set = dce_v11_0_ext_mode_set,
3629         .commit = dce_v11_0_ext_commit,
3630         .disable = dce_v11_0_ext_disable,
3631         /* no detect for TMDS/LVDS yet */
3632 };
3633
3634 static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs = {
3635         .dpms = amdgpu_atombios_encoder_dpms,
3636         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3637         .prepare = dce_v11_0_encoder_prepare,
3638         .mode_set = dce_v11_0_encoder_mode_set,
3639         .commit = dce_v11_0_encoder_commit,
3640         .disable = dce_v11_0_encoder_disable,
3641         .detect = amdgpu_atombios_encoder_dig_detect,
3642 };
3643
3644 static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs = {
3645         .dpms = amdgpu_atombios_encoder_dpms,
3646         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3647         .prepare = dce_v11_0_encoder_prepare,
3648         .mode_set = dce_v11_0_encoder_mode_set,
3649         .commit = dce_v11_0_encoder_commit,
3650         .detect = amdgpu_atombios_encoder_dac_detect,
3651 };
3652
3653 static void dce_v11_0_encoder_destroy(struct drm_encoder *encoder)
3654 {
3655         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3656         if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3657                 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3658         kfree(amdgpu_encoder->enc_priv);
3659         drm_encoder_cleanup(encoder);
3660         kfree(amdgpu_encoder);
3661 }
3662
3663 static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = {
3664         .destroy = dce_v11_0_encoder_destroy,
3665 };
3666
3667 static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
3668                                  uint32_t encoder_enum,
3669                                  uint32_t supported_device,
3670                                  u16 caps)
3671 {
3672         struct drm_device *dev = adev->ddev;
3673         struct drm_encoder *encoder;
3674         struct amdgpu_encoder *amdgpu_encoder;
3675
3676         /* see if we already added it */
3677         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3678                 amdgpu_encoder = to_amdgpu_encoder(encoder);
3679                 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3680                         amdgpu_encoder->devices |= supported_device;
3681                         return;
3682                 }
3683
3684         }
3685
3686         /* add a new one */
3687         amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3688         if (!amdgpu_encoder)
3689                 return;
3690
3691         encoder = &amdgpu_encoder->base;
3692         switch (adev->mode_info.num_crtc) {
3693         case 1:
3694                 encoder->possible_crtcs = 0x1;
3695                 break;
3696         case 2:
3697         default:
3698                 encoder->possible_crtcs = 0x3;
3699                 break;
3700         case 4:
3701                 encoder->possible_crtcs = 0xf;
3702                 break;
3703         case 6:
3704                 encoder->possible_crtcs = 0x3f;
3705                 break;
3706         }
3707
3708         amdgpu_encoder->enc_priv = NULL;
3709
3710         amdgpu_encoder->encoder_enum = encoder_enum;
3711         amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3712         amdgpu_encoder->devices = supported_device;
3713         amdgpu_encoder->rmx_type = RMX_OFF;
3714         amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3715         amdgpu_encoder->is_ext_encoder = false;
3716         amdgpu_encoder->caps = caps;
3717
3718         switch (amdgpu_encoder->encoder_id) {
3719         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3720         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3721                 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3722                                  DRM_MODE_ENCODER_DAC);
3723                 drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs);
3724                 break;
3725         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3726         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3727         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3728         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3729         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3730                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3731                         amdgpu_encoder->rmx_type = RMX_FULL;
3732                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3733                                          DRM_MODE_ENCODER_LVDS);
3734                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3735                 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3736                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3737                                          DRM_MODE_ENCODER_DAC);
3738                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3739                 } else {
3740                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3741                                          DRM_MODE_ENCODER_TMDS);
3742                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3743                 }
3744                 drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs);
3745                 break;
3746         case ENCODER_OBJECT_ID_SI170B:
3747         case ENCODER_OBJECT_ID_CH7303:
3748         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3749         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3750         case ENCODER_OBJECT_ID_TITFP513:
3751         case ENCODER_OBJECT_ID_VT1623:
3752         case ENCODER_OBJECT_ID_HDMI_SI1930:
3753         case ENCODER_OBJECT_ID_TRAVIS:
3754         case ENCODER_OBJECT_ID_NUTMEG:
3755                 /* these are handled by the primary encoders */
3756                 amdgpu_encoder->is_ext_encoder = true;
3757                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3758                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3759                                          DRM_MODE_ENCODER_LVDS);
3760                 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3761                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3762                                          DRM_MODE_ENCODER_DAC);
3763                 else
3764                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3765                                          DRM_MODE_ENCODER_TMDS);
3766                 drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs);
3767                 break;
3768         }
3769 }
3770
3771 static const struct amdgpu_display_funcs dce_v11_0_display_funcs = {
3772         .set_vga_render_state = &dce_v11_0_set_vga_render_state,
3773         .bandwidth_update = &dce_v11_0_bandwidth_update,
3774         .vblank_get_counter = &dce_v11_0_vblank_get_counter,
3775         .vblank_wait = &dce_v11_0_vblank_wait,
3776         .is_display_hung = &dce_v11_0_is_display_hung,
3777         .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3778         .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3779         .hpd_sense = &dce_v11_0_hpd_sense,
3780         .hpd_set_polarity = &dce_v11_0_hpd_set_polarity,
3781         .hpd_get_gpio_reg = &dce_v11_0_hpd_get_gpio_reg,
3782         .page_flip = &dce_v11_0_page_flip,
3783         .page_flip_get_scanoutpos = &dce_v11_0_crtc_get_scanoutpos,
3784         .add_encoder = &dce_v11_0_encoder_add,
3785         .add_connector = &amdgpu_connector_add,
3786         .stop_mc_access = &dce_v11_0_stop_mc_access,
3787         .resume_mc_access = &dce_v11_0_resume_mc_access,
3788 };
3789
3790 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev)
3791 {
3792         if (adev->mode_info.funcs == NULL)
3793                 adev->mode_info.funcs = &dce_v11_0_display_funcs;
3794 }
3795
3796 static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = {
3797         .set = dce_v11_0_set_crtc_irq_state,
3798         .process = dce_v11_0_crtc_irq,
3799 };
3800
3801 static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs = {
3802         .set = dce_v11_0_set_pageflip_irq_state,
3803         .process = dce_v11_0_pageflip_irq,
3804 };
3805
3806 static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = {
3807         .set = dce_v11_0_set_hpd_irq_state,
3808         .process = dce_v11_0_hpd_irq,
3809 };
3810
3811 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev)
3812 {
3813         adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
3814         adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs;
3815
3816         adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
3817         adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs;
3818
3819         adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3820         adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs;
3821 }