drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include "drmP.h"
  25 #include "amdgpu.h"
  26 #include "amdgpu_gfx.h"
  27 #include "vi.h"
  28 #include "vid.h"
  29 #include "amdgpu_ucode.h"
  30 #include "clearstate_vi.h"
  31
  32 #include "gmc/gmc_8_2_d.h"
  33 #include "gmc/gmc_8_2_sh_mask.h"
  34
  35 #include "oss/oss_3_0_d.h"
  36 #include "oss/oss_3_0_sh_mask.h"
  37
  38 #include "bif/bif_5_0_d.h"
  39 #include "bif/bif_5_0_sh_mask.h"
  40
  41 #include "gca/gfx_8_0_d.h"
  42 #include "gca/gfx_8_0_enum.h"
  43 #include "gca/gfx_8_0_sh_mask.h"
  44 #include "gca/gfx_8_0_enum.h"
  45
  46 #include "uvd/uvd_5_0_d.h"
  47 #include "uvd/uvd_5_0_sh_mask.h"
  48
  49 #include "dce/dce_10_0_d.h"
  50 #include "dce/dce_10_0_sh_mask.h"
  51
  52 #define GFX8_NUM_GFX_RINGS     1
  53 #define GFX8_NUM_COMPUTE_RINGS 8
  54
  55 #define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001
  56 #define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001
  57 #define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003
  58
  59 #define ARRAY_MODE(x)                                   ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
  60 #define PIPE_CONFIG(x)                                  ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
  61 #define TILE_SPLIT(x)                                   ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
  62 #define MICRO_TILE_MODE_NEW(x)                          ((x) << GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT)
  63 #define SAMPLE_SPLIT(x)                                 ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
  64 #define BANK_WIDTH(x)                                   ((x) << GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT)
  65 #define BANK_HEIGHT(x)                                  ((x) << GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT)
  66 #define MACRO_TILE_ASPECT(x)                            ((x) << GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT)
  67 #define NUM_BANKS(x)                                    ((x) << GB_MACROTILE_MODE0__NUM_BANKS__SHIFT)
  68
  69 MODULE_FIRMWARE("amdgpu/carrizo_ce.bin");
  70 MODULE_FIRMWARE("amdgpu/carrizo_pfp.bin");
  71 MODULE_FIRMWARE("amdgpu/carrizo_me.bin");
  72 MODULE_FIRMWARE("amdgpu/carrizo_mec.bin");
  73 MODULE_FIRMWARE("amdgpu/carrizo_mec2.bin");
  74 MODULE_FIRMWARE("amdgpu/carrizo_rlc.bin");
  75
  76 MODULE_FIRMWARE("amdgpu/stoney_ce.bin");
  77 MODULE_FIRMWARE("amdgpu/stoney_pfp.bin");
  78 MODULE_FIRMWARE("amdgpu/stoney_me.bin");
  79 MODULE_FIRMWARE("amdgpu/stoney_mec.bin");
  80 MODULE_FIRMWARE("amdgpu/stoney_rlc.bin");
  81
  82 MODULE_FIRMWARE("amdgpu/tonga_ce.bin");
  83 MODULE_FIRMWARE("amdgpu/tonga_pfp.bin");
  84 MODULE_FIRMWARE("amdgpu/tonga_me.bin");
  85 MODULE_FIRMWARE("amdgpu/tonga_mec.bin");
  86 MODULE_FIRMWARE("amdgpu/tonga_mec2.bin");
  87 MODULE_FIRMWARE("amdgpu/tonga_rlc.bin");
  88
  89 MODULE_FIRMWARE("amdgpu/topaz_ce.bin");
  90 MODULE_FIRMWARE("amdgpu/topaz_pfp.bin");
  91 MODULE_FIRMWARE("amdgpu/topaz_me.bin");
  92 MODULE_FIRMWARE("amdgpu/topaz_mec.bin");
  93 MODULE_FIRMWARE("amdgpu/topaz_mec2.bin");
  94 MODULE_FIRMWARE("amdgpu/topaz_rlc.bin");
  95
  96 MODULE_FIRMWARE("amdgpu/fiji_ce.bin");
  97 MODULE_FIRMWARE("amdgpu/fiji_pfp.bin");
  98 MODULE_FIRMWARE("amdgpu/fiji_me.bin");
  99 MODULE_FIRMWARE("amdgpu/fiji_mec.bin");
 100 MODULE_FIRMWARE("amdgpu/fiji_mec2.bin");
 101 MODULE_FIRMWARE("amdgpu/fiji_rlc.bin");
 102
 103 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
 104 {
 105         {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
 106         {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
 107         {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
 108         {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
 109         {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
 110         {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
 111         {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
 112         {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
 113         {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
 114         {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
 115         {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
 116         {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
 117         {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
 118         {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
 119         {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
 120         {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
 121 };
 122
 123 static const u32 golden_settings_tonga_a11[] =
 124 {
 125         mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208,
 126         mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
 127         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 128         mmGB_GPU_ID, 0x0000000f, 0x00000000,
 129         mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
 130         mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc,
 131         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 132         mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
 133         mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
 134         mmTCC_CTRL, 0x00100000, 0xf31fff7f,
 135         mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
 136         mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb,
 137         mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b,
 138         mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876,
 139         mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
 140 };
 141
 142 static const u32 tonga_golden_common_all[] =
 143 {
 144         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 145         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
 146         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
 147         mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
 148         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
 149         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
 150         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
 151         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
 152 };
 153
 154 static const u32 tonga_mgcg_cgcg_init[] =
 155 {
 156         mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
 157         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 158         mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 159         mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
 160         mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
 161         mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
 162         mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
 163         mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
 164         mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
 165         mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
 166         mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
 167         mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
 168         mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
 169         mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
 170         mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
 171         mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
 172         mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
 173         mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
 174         mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
 175         mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
 176         mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
 177         mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
 178         mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
 179         mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
 180         mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
 181         mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
 182         mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
 183         mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 184         mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 185         mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
 186         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 187         mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 188         mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 189         mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
 190         mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 191         mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 192         mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 193         mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 194         mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
 195         mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 196         mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 197         mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 198         mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 199         mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
 200         mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 201         mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 202         mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 203         mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 204         mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
 205         mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 206         mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 207         mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 208         mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 209         mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
 210         mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 211         mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 212         mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 213         mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 214         mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
 215         mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 216         mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 217         mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 218         mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 219         mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
 220         mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 221         mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 222         mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 223         mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 224         mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
 225         mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 226         mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 227         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
 228         mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
 229         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
 230         mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
 231 };
 232
 233 static const u32 fiji_golden_common_all[] =
 234 {
 235         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 236         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x3a00161a,
 237         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002e,
 238         mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
 239         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
 240         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
 241         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
 242         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF,
 243         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 244         mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x00000009,
 245 };
 246
 247 static const u32 golden_settings_fiji_a10[] =
 248 {
 249         mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
 250         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 251         mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
 252         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 253         mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
 254         mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
 255         mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
 256         mmTCC_CTRL, 0x00100000, 0xf31fff7f,
 257         mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
 258         mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000ff,
 259         mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
 260 };
 261
 262 static const u32 fiji_mgcg_cgcg_init[] =
 263 {
 264         mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
 265         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 266         mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 267         mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
 268         mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
 269         mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
 270         mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
 271         mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
 272         mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
 273         mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
 274         mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
 275         mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
 276         mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
 277         mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
 278         mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
 279         mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
 280         mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
 281         mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
 282         mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
 283         mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
 284         mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
 285         mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
 286         mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
 287         mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
 288         mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
 289         mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
 290         mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
 291         mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
 292         mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 293         mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 294         mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
 295         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 296         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
 297         mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
 298         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
 299         mmPCIE_INDEX, 0xffffffff, 0x0140001c,
 300         mmPCIE_DATA, 0x000f0000, 0x00000000,
 301         mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
 302         mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
 303         mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
 304 };
 305
 306 static const u32 golden_settings_iceland_a11[] =
 307 {
 308         mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
 309         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 310         mmDB_DEBUG3, 0xc0000000, 0xc0000000,
 311         mmGB_GPU_ID, 0x0000000f, 0x00000000,
 312         mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
 313         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 314         mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002,
 315         mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
 316         mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
 317         mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
 318         mmTCC_CTRL, 0x00100000, 0xf31fff7f,
 319         mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
 320         mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1,
 321         mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
 322         mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010,
 323 };
 324
 325 static const u32 iceland_golden_common_all[] =
 326 {
 327         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 328         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
 329         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
 330         mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
 331         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
 332         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
 333         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
 334         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
 335 };
 336
 337 static const u32 iceland_mgcg_cgcg_init[] =
 338 {
 339         mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
 340         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 341         mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 342         mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
 343         mmCGTT_CP_CLK_CTRL, 0xffffffff, 0xc0000100,
 344         mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0xc0000100,
 345         mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0xc0000100,
 346         mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
 347         mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
 348         mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
 349         mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
 350         mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
 351         mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
 352         mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
 353         mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
 354         mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
 355         mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
 356         mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
 357         mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
 358         mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
 359         mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
 360         mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
 361         mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0xff000100,
 362         mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
 363         mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
 364         mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
 365         mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
 366         mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 367         mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 368         mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
 369         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 370         mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 371         mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 372         mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
 373         mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 374         mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 375         mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 376         mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 377         mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
 378         mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 379         mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 380         mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 381         mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 382         mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
 383         mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 384         mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 385         mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 386         mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 387         mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
 388         mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 389         mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 390         mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 391         mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 392         mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
 393         mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 394         mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 395         mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 396         mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 397         mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
 398         mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 399         mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 400         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
 401         mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
 402         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
 403 };
 404
 405 static const u32 cz_golden_settings_a11[] =
 406 {
 407         mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
 408         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 409         mmGB_GPU_ID, 0x0000000f, 0x00000000,
 410         mmPA_SC_ENHANCE, 0xffffffff, 0x00000001,
 411         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 412         mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
 413         mmTA_CNTL_AUX, 0x000f000f, 0x00010000,
 414         mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
 415         mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3,
 416         mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302
 417 };
 418
 419 static const u32 cz_golden_common_all[] =
 420 {
 421         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 422         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
 423         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
 424         mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
 425         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
 426         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
 427         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
 428         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
 429 };
 430
 431 static const u32 cz_mgcg_cgcg_init[] =
 432 {
 433         mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
 434         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 435         mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 436         mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
 437         mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
 438         mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
 439         mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x00000100,
 440         mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
 441         mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
 442         mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
 443         mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
 444         mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
 445         mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
 446         mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
 447         mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
 448         mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
 449         mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
 450         mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
 451         mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
 452         mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
 453         mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
 454         mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
 455         mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
 456         mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
 457         mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
 458         mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
 459         mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
 460         mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 461         mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 462         mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
 463         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 464         mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 465         mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 466         mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
 467         mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 468         mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 469         mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 470         mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 471         mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
 472         mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 473         mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 474         mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 475         mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 476         mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
 477         mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 478         mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 479         mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 480         mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 481         mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
 482         mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 483         mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 484         mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 485         mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 486         mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
 487         mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 488         mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 489         mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 490         mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 491         mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
 492         mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 493         mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 494         mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 495         mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 496         mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
 497         mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 498         mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 499         mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 500         mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 501         mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
 502         mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 503         mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 504         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
 505         mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
 506         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
 507         mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
 508 };
 509
 510 static const u32 stoney_golden_settings_a11[] =
 511 {
 512         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 513         mmGB_GPU_ID, 0x0000000f, 0x00000000,
 514         mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
 515         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 516         mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
 517         mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
 518         mmTCC_CTRL, 0x00100000, 0xf31fff7f,
 519         mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
 520         mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f1,
 521         mmTCP_CHAN_STEER_LO, 0xffffffff, 0x10101010,
 522 };
 523
 524 static const u32 stoney_golden_common_all[] =
 525 {
 526         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 527         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000000,
 528         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
 529         mmGB_ADDR_CONFIG, 0xffffffff, 0x12010001,
 530         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
 531         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
 532         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
 533         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF,
 534 };
 535
 536 static const u32 stoney_mgcg_cgcg_init[] =
 537 {
 538         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 539         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
 540         mmCP_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
 541         mmRLC_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
 542         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
 543         mmATC_MISC_CG, 0xffffffff, 0x000c0200,
 544 };
 545
 546 static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev);
 547 static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev);
 548 static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev);
 549
 550 static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
 551 {
 552         switch (adev->asic_type) {
 553         case CHIP_TOPAZ:
 554                 amdgpu_program_register_sequence(adev,
 555                                                  iceland_mgcg_cgcg_init,
 556                                                  (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
 557                 amdgpu_program_register_sequence(adev,
 558                                                  golden_settings_iceland_a11,
 559                                                  (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
 560                 amdgpu_program_register_sequence(adev,
 561                                                  iceland_golden_common_all,
 562                                                  (const u32)ARRAY_SIZE(iceland_golden_common_all));
 563                 break;
 564         case CHIP_FIJI:
 565                 amdgpu_program_register_sequence(adev,
 566                                                  fiji_mgcg_cgcg_init,
 567                                                  (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
 568                 amdgpu_program_register_sequence(adev,
 569                                                  golden_settings_fiji_a10,
 570                                                  (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
 571                 amdgpu_program_register_sequence(adev,
 572                                                  fiji_golden_common_all,
 573                                                  (const u32)ARRAY_SIZE(fiji_golden_common_all));
 574                 break;
 575
 576         case CHIP_TONGA:
 577                 amdgpu_program_register_sequence(adev,
 578                                                  tonga_mgcg_cgcg_init,
 579                                                  (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
 580                 amdgpu_program_register_sequence(adev,
 581                                                  golden_settings_tonga_a11,
 582                                                  (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
 583                 amdgpu_program_register_sequence(adev,
 584                                                  tonga_golden_common_all,
 585                                                  (const u32)ARRAY_SIZE(tonga_golden_common_all));
 586                 break;
 587         case CHIP_CARRIZO:
 588                 amdgpu_program_register_sequence(adev,
 589                                                  cz_mgcg_cgcg_init,
 590                                                  (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
 591                 amdgpu_program_register_sequence(adev,
 592                                                  cz_golden_settings_a11,
 593                                                  (const u32)ARRAY_SIZE(cz_golden_settings_a11));
 594                 amdgpu_program_register_sequence(adev,
 595                                                  cz_golden_common_all,
 596                                                  (const u32)ARRAY_SIZE(cz_golden_common_all));
 597                 break;
 598         case CHIP_STONEY:
 599                 amdgpu_program_register_sequence(adev,
 600                                                  stoney_mgcg_cgcg_init,
 601                                                  (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
 602                 amdgpu_program_register_sequence(adev,
 603                                                  stoney_golden_settings_a11,
 604                                                  (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
 605                 amdgpu_program_register_sequence(adev,
 606                                                  stoney_golden_common_all,
 607                                                  (const u32)ARRAY_SIZE(stoney_golden_common_all));
 608                 break;
 609         default:
 610                 break;
 611         }
 612 }
 613
 614 static void gfx_v8_0_scratch_init(struct amdgpu_device *adev)
 615 {
 616         int i;
 617
 618         adev->gfx.scratch.num_reg = 7;
 619         adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
 620         for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
 621                 adev->gfx.scratch.free[i] = true;
 622                 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;
 623         }
 624 }
 625
 626 static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring)
 627 {
 628         struct amdgpu_device *adev = ring->adev;
 629         uint32_t scratch;
 630         uint32_t tmp = 0;
 631         unsigned i;
 632         int r;
 633
 634         r = amdgpu_gfx_scratch_get(adev, &scratch);
 635         if (r) {
 636                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
 637                 return r;
 638         }
 639         WREG32(scratch, 0xCAFEDEAD);
 640         r = amdgpu_ring_lock(ring, 3);
 641         if (r) {
 642                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
 643                           ring->idx, r);
 644                 amdgpu_gfx_scratch_free(adev, scratch);
 645                 return r;
 646         }
 647         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
 648         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
 649         amdgpu_ring_write(ring, 0xDEADBEEF);
 650         amdgpu_ring_unlock_commit(ring);
 651
 652         for (i = 0; i < adev->usec_timeout; i++) {
 653                 tmp = RREG32(scratch);
 654                 if (tmp == 0xDEADBEEF)
 655                         break;
 656                 DRM_UDELAY(1);
 657         }
 658         if (i < adev->usec_timeout) {
 659                 DRM_INFO("ring test on %d succeeded in %d usecs\n",
 660                          ring->idx, i);
 661         } else {
 662                 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
 663                           ring->idx, scratch, tmp);
 664                 r = -EINVAL;
 665         }
 666         amdgpu_gfx_scratch_free(adev, scratch);
 667         return r;
 668 }
 669
 670 static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring)
 671 {
 672         struct amdgpu_device *adev = ring->adev;
 673         struct amdgpu_ib ib;
 674         struct fence *f = NULL;
 675         uint32_t scratch;
 676         uint32_t tmp = 0;
 677         unsigned i;
 678         int r;
 679
 680         r = amdgpu_gfx_scratch_get(adev, &scratch);
 681         if (r) {
 682                 DRM_ERROR("amdgpu: failed to get scratch reg (%d).\n", r);
 683                 return r;
 684         }
 685         WREG32(scratch, 0xCAFEDEAD);
 686         memset(&ib, 0, sizeof(ib));
 687         r = amdgpu_ib_get(ring, NULL, 256, &ib);
 688         if (r) {
 689                 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
 690                 goto err1;
 691         }
 692         ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
 693         ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
 694         ib.ptr[2] = 0xDEADBEEF;
 695         ib.length_dw = 3;
 696
 697         r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, &ib, 1, NULL,
 698                                                  AMDGPU_FENCE_OWNER_UNDEFINED,
 699                                                  &f);
 700         if (r)
 701                 goto err2;
 702
 703         r = fence_wait(f, false);
 704         if (r) {
 705                 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
 706                 goto err2;
 707         }
 708         for (i = 0; i < adev->usec_timeout; i++) {
 709                 tmp = RREG32(scratch);
 710                 if (tmp == 0xDEADBEEF)
 711                         break;
 712                 DRM_UDELAY(1);
 713         }
 714         if (i < adev->usec_timeout) {
 715                 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
 716                          ring->idx, i);
 717                 goto err2;
 718         } else {
 719                 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
 720                           scratch, tmp);
 721                 r = -EINVAL;
 722         }
 723 err2:
 724         fence_put(f);
 725         amdgpu_ib_free(adev, &ib);
 726 err1:
 727         amdgpu_gfx_scratch_free(adev, scratch);
 728         return r;
 729 }
 730
 731 static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
 732 {
 733         const char *chip_name;
 734         char fw_name[30];
 735         int err;
 736         struct amdgpu_firmware_info *info = NULL;
 737         const struct common_firmware_header *header = NULL;
 738         const struct gfx_firmware_header_v1_0 *cp_hdr;
 739
 740         DRM_DEBUG("\n");
 741
 742         switch (adev->asic_type) {
 743         case CHIP_TOPAZ:
 744                 chip_name = "topaz";
 745                 break;
 746         case CHIP_TONGA:
 747                 chip_name = "tonga";
 748                 break;
 749         case CHIP_CARRIZO:
 750                 chip_name = "carrizo";
 751                 break;
 752         case CHIP_FIJI:
 753                 chip_name = "fiji";
 754                 break;
 755         case CHIP_STONEY:
 756                 chip_name = "stoney";
 757                 break;
 758         default:
 759                 BUG();
 760         }
 761
 762         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
 763         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
 764         if (err)
 765                 goto out;
 766         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
 767         if (err)
 768                 goto out;
 769         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
 770         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 771         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 772
 773         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
 774         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
 775         if (err)
 776                 goto out;
 777         err = amdgpu_ucode_validate(adev->gfx.me_fw);
 778         if (err)
 779                 goto out;
 780         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
 781         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 782         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 783
 784         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
 785         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
 786         if (err)
 787                 goto out;
 788         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
 789         if (err)
 790                 goto out;
 791         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
 792         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 793         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 794
 795         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
 796         err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
 797         if (err)
 798                 goto out;
 799         err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
 800         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
 801         adev->gfx.rlc_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 802         adev->gfx.rlc_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 803
 804         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
 805         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
 806         if (err)
 807                 goto out;
 808         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
 809         if (err)
 810                 goto out;
 811         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
 812         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 813         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 814
 815         if (adev->asic_type != CHIP_STONEY) {
 816                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
 817                 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
 818                 if (!err) {
 819                         err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
 820                         if (err)
 821                                 goto out;
 822                         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
 823                                 adev->gfx.mec2_fw->data;
 824                         adev->gfx.mec2_fw_version =
 825                                 le32_to_cpu(cp_hdr->header.ucode_version);
 826                         adev->gfx.mec2_feature_version =
 827                                 le32_to_cpu(cp_hdr->ucode_feature_version);
 828                 } else {
 829                         err = 0;
 830                         adev->gfx.mec2_fw = NULL;
 831                 }
 832         }
 833
 834         if (adev->firmware.smu_load) {
 835                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
 836                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
 837                 info->fw = adev->gfx.pfp_fw;
 838                 header = (const struct common_firmware_header *)info->fw->data;
 839                 adev->firmware.fw_size +=
 840                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 841
 842                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
 843                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
 844                 info->fw = adev->gfx.me_fw;
 845                 header = (const struct common_firmware_header *)info->fw->data;
 846                 adev->firmware.fw_size +=
 847                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 848
 849                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
 850                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
 851                 info->fw = adev->gfx.ce_fw;
 852                 header = (const struct common_firmware_header *)info->fw->data;
 853                 adev->firmware.fw_size +=
 854                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 855
 856                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
 857                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
 858                 info->fw = adev->gfx.rlc_fw;
 859                 header = (const struct common_firmware_header *)info->fw->data;
 860                 adev->firmware.fw_size +=
 861                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 862
 863                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
 864                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
 865                 info->fw = adev->gfx.mec_fw;
 866                 header = (const struct common_firmware_header *)info->fw->data;
 867                 adev->firmware.fw_size +=
 868                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 869
 870                 if (adev->gfx.mec2_fw) {
 871                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
 872                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 873                         info->fw = adev->gfx.mec2_fw;
 874                         header = (const struct common_firmware_header *)info->fw->data;
 875                         adev->firmware.fw_size +=
 876                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 877                 }
 878
 879         }
 880
 881 out:
 882         if (err) {
 883                 dev_err(adev->dev,
 884                         "gfx8: Failed to load firmware \"%s\"\n",
 885                         fw_name);
 886                 release_firmware(adev->gfx.pfp_fw);
 887                 adev->gfx.pfp_fw = NULL;
 888                 release_firmware(adev->gfx.me_fw);
 889                 adev->gfx.me_fw = NULL;
 890                 release_firmware(adev->gfx.ce_fw);
 891                 adev->gfx.ce_fw = NULL;
 892                 release_firmware(adev->gfx.rlc_fw);
 893                 adev->gfx.rlc_fw = NULL;
 894                 release_firmware(adev->gfx.mec_fw);
 895                 adev->gfx.mec_fw = NULL;
 896                 release_firmware(adev->gfx.mec2_fw);
 897                 adev->gfx.mec2_fw = NULL;
 898         }
 899         return err;
 900 }
 901
 902 static void gfx_v8_0_mec_fini(struct amdgpu_device *adev)
 903 {
 904         int r;
 905
 906         if (adev->gfx.mec.hpd_eop_obj) {
 907                 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
 908                 if (unlikely(r != 0))
 909                         dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
 910                 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
 911                 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
 912
 913                 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
 914                 adev->gfx.mec.hpd_eop_obj = NULL;
 915         }
 916 }
 917
 918 #define MEC_HPD_SIZE 2048
 919
 920 static int gfx_v8_0_mec_init(struct amdgpu_device *adev)
 921 {
 922         int r;
 923         u32 *hpd;
 924
 925         /*
 926          * we assign only 1 pipe because all other pipes will
 927          * be handled by KFD
 928          */
 929         adev->gfx.mec.num_mec = 1;
 930         adev->gfx.mec.num_pipe = 1;
 931         adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8;
 932
 933         if (adev->gfx.mec.hpd_eop_obj == NULL) {
 934                 r = amdgpu_bo_create(adev,
 935                                      adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2,
 936                                      PAGE_SIZE, true,
 937                                      AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
 938                                      &adev->gfx.mec.hpd_eop_obj);
 939                 if (r) {
 940                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
 941                         return r;
 942                 }
 943         }
 944
 945         r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
 946         if (unlikely(r != 0)) {
 947                 gfx_v8_0_mec_fini(adev);
 948                 return r;
 949         }
 950         r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
 951                           &adev->gfx.mec.hpd_eop_gpu_addr);
 952         if (r) {
 953                 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
 954                 gfx_v8_0_mec_fini(adev);
 955                 return r;
 956         }
 957         r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
 958         if (r) {
 959                 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
 960                 gfx_v8_0_mec_fini(adev);
 961                 return r;
 962         }
 963
 964         memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2);
 965
 966         amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
 967         amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
 968
 969         return 0;
 970 }
 971
 972 static void gfx_v8_0_gpu_early_init(struct amdgpu_device *adev)
 973 {
 974         u32 gb_addr_config;
 975         u32 mc_shared_chmap, mc_arb_ramcfg;
 976         u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
 977         u32 tmp;
 978
 979         switch (adev->asic_type) {
 980         case CHIP_TOPAZ:
 981                 adev->gfx.config.max_shader_engines = 1;
 982                 adev->gfx.config.max_tile_pipes = 2;
 983                 adev->gfx.config.max_cu_per_sh = 6;
 984                 adev->gfx.config.max_sh_per_se = 1;
 985                 adev->gfx.config.max_backends_per_se = 2;
 986                 adev->gfx.config.max_texture_channel_caches = 2;
 987                 adev->gfx.config.max_gprs = 256;
 988                 adev->gfx.config.max_gs_threads = 32;
 989                 adev->gfx.config.max_hw_contexts = 8;
 990
 991                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
 992                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
 993                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
 994                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
 995                 gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN;
 996                 break;
 997         case CHIP_FIJI:
 998                 adev->gfx.config.max_shader_engines = 4;
 999                 adev->gfx.config.max_tile_pipes = 16;
1000                 adev->gfx.config.max_cu_per_sh = 16;
1001                 adev->gfx.config.max_sh_per_se = 1;
1002                 adev->gfx.config.max_backends_per_se = 4;
1003                 adev->gfx.config.max_texture_channel_caches = 8;
1004                 adev->gfx.config.max_gprs = 256;
1005                 adev->gfx.config.max_gs_threads = 32;
1006                 adev->gfx.config.max_hw_contexts = 8;
1007
1008                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1009                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1010                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1011                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1012                 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1013                 break;
1014         case CHIP_TONGA:
1015                 adev->gfx.config.max_shader_engines = 4;
1016                 adev->gfx.config.max_tile_pipes = 8;
1017                 adev->gfx.config.max_cu_per_sh = 8;
1018                 adev->gfx.config.max_sh_per_se = 1;
1019                 adev->gfx.config.max_backends_per_se = 2;
1020                 adev->gfx.config.max_texture_channel_caches = 8;
1021                 adev->gfx.config.max_gprs = 256;
1022                 adev->gfx.config.max_gs_threads = 32;
1023                 adev->gfx.config.max_hw_contexts = 8;
1024
1025                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1026                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1027                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1028                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1029                 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1030                 break;
1031         case CHIP_CARRIZO:
1032                 adev->gfx.config.max_shader_engines = 1;
1033                 adev->gfx.config.max_tile_pipes = 2;
1034                 adev->gfx.config.max_sh_per_se = 1;
1035                 adev->gfx.config.max_backends_per_se = 2;
1036
1037                 switch (adev->pdev->revision) {
1038                 case 0xc4:
1039                 case 0x84:
1040                 case 0xc8:
1041                 case 0xcc:
1042                 case 0xe1:
1043                 case 0xe3:
1044                         /* B10 */
1045                         adev->gfx.config.max_cu_per_sh = 8;
1046                         break;
1047                 case 0xc5:
1048                 case 0x81:
1049                 case 0x85:
1050                 case 0xc9:
1051                 case 0xcd:
1052                 case 0xe2:
1053                 case 0xe4:
1054                         /* B8 */
1055                         adev->gfx.config.max_cu_per_sh = 6;
1056                         break;
1057                 case 0xc6:
1058                 case 0xca:
1059                 case 0xce:
1060                 case 0x88:
1061                         /* B6 */
1062                         adev->gfx.config.max_cu_per_sh = 6;
1063                         break;
1064                 case 0xc7:
1065                 case 0x87:
1066                 case 0xcb:
1067                 case 0xe5:
1068                 case 0x89:
1069                 default:
1070                         /* B4 */
1071                         adev->gfx.config.max_cu_per_sh = 4;
1072                         break;
1073                 }
1074
1075                 adev->gfx.config.max_texture_channel_caches = 2;
1076                 adev->gfx.config.max_gprs = 256;
1077                 adev->gfx.config.max_gs_threads = 32;
1078                 adev->gfx.config.max_hw_contexts = 8;
1079
1080                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1081                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1082                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1083                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1084                 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
1085                 break;
1086         case CHIP_STONEY:
1087                 adev->gfx.config.max_shader_engines = 1;
1088                 adev->gfx.config.max_tile_pipes = 2;
1089                 adev->gfx.config.max_sh_per_se = 1;
1090                 adev->gfx.config.max_backends_per_se = 1;
1091
1092                 switch (adev->pdev->revision) {
1093                 case 0xc0:
1094                 case 0xc1:
1095                 case 0xc2:
1096                 case 0xc4:
1097                 case 0xc8:
1098                 case 0xc9:
1099                         adev->gfx.config.max_cu_per_sh = 3;
1100                         break;
1101                 case 0xd0:
1102                 case 0xd1:
1103                 case 0xd2:
1104                 default:
1105                         adev->gfx.config.max_cu_per_sh = 2;
1106                         break;
1107                 }
1108
1109                 adev->gfx.config.max_texture_channel_caches = 2;
1110                 adev->gfx.config.max_gprs = 256;
1111                 adev->gfx.config.max_gs_threads = 16;
1112                 adev->gfx.config.max_hw_contexts = 8;
1113
1114                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1115                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1116                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1117                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1118                 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
1119                 break;
1120         default:
1121                 adev->gfx.config.max_shader_engines = 2;
1122                 adev->gfx.config.max_tile_pipes = 4;
1123                 adev->gfx.config.max_cu_per_sh = 2;
1124                 adev->gfx.config.max_sh_per_se = 1;
1125                 adev->gfx.config.max_backends_per_se = 2;
1126                 adev->gfx.config.max_texture_channel_caches = 4;
1127                 adev->gfx.config.max_gprs = 256;
1128                 adev->gfx.config.max_gs_threads = 32;
1129                 adev->gfx.config.max_hw_contexts = 8;
1130
1131                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1132                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1133                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1134                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1135                 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1136                 break;
1137         }
1138
1139         mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
1140         adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
1141         mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
1142
1143         adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
1144         adev->gfx.config.mem_max_burst_length_bytes = 256;
1145         if (adev->flags & AMD_IS_APU) {
1146                 /* Get memory bank mapping mode. */
1147                 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
1148                 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
1149                 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
1150
1151                 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
1152                 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
1153                 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
1154
1155                 /* Validate settings in case only one DIMM installed. */
1156                 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
1157                         dimm00_addr_map = 0;
1158                 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
1159                         dimm01_addr_map = 0;
1160                 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
1161                         dimm10_addr_map = 0;
1162                 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
1163                         dimm11_addr_map = 0;
1164
1165                 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
1166                 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
1167                 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
1168                         adev->gfx.config.mem_row_size_in_kb = 2;
1169                 else
1170                         adev->gfx.config.mem_row_size_in_kb = 1;
1171         } else {
1172                 tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS);
1173                 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1174                 if (adev->gfx.config.mem_row_size_in_kb > 4)
1175                         adev->gfx.config.mem_row_size_in_kb = 4;
1176         }
1177
1178         adev->gfx.config.shader_engine_tile_size = 32;
1179         adev->gfx.config.num_gpus = 1;
1180         adev->gfx.config.multi_gpu_tile_size = 64;
1181
1182         /* fix up row size */
1183         switch (adev->gfx.config.mem_row_size_in_kb) {
1184         case 1:
1185         default:
1186                 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0);
1187                 break;
1188         case 2:
1189                 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1);
1190                 break;
1191         case 4:
1192                 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2);
1193                 break;
1194         }
1195         adev->gfx.config.gb_addr_config = gb_addr_config;
1196 }
1197
1198 static int gfx_v8_0_sw_init(void *handle)
1199 {
1200         int i, r;
1201         struct amdgpu_ring *ring;
1202         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1203
1204         /* EOP Event */
1205         r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
1206         if (r)
1207                 return r;
1208
1209         /* Privileged reg */
1210         r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
1211         if (r)
1212                 return r;
1213
1214         /* Privileged inst */
1215         r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
1216         if (r)
1217                 return r;
1218
1219         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1220
1221         gfx_v8_0_scratch_init(adev);
1222
1223         r = gfx_v8_0_init_microcode(adev);
1224         if (r) {
1225                 DRM_ERROR("Failed to load gfx firmware!\n");
1226                 return r;
1227         }
1228
1229         r = gfx_v8_0_mec_init(adev);
1230         if (r) {
1231                 DRM_ERROR("Failed to init MEC BOs!\n");
1232                 return r;
1233         }
1234
1235         /* set up the gfx ring */
1236         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
1237                 ring = &adev->gfx.gfx_ring[i];
1238                 ring->ring_obj = NULL;
1239                 sprintf(ring->name, "gfx");
1240                 /* no gfx doorbells on iceland */
1241                 if (adev->asic_type != CHIP_TOPAZ) {
1242                         ring->use_doorbell = true;
1243                         ring->doorbell_index = AMDGPU_DOORBELL_GFX_RING0;
1244                 }
1245
1246                 r = amdgpu_ring_init(adev, ring, 1024 * 1024,
1247                                      PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
1248                                      &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
1249                                      AMDGPU_RING_TYPE_GFX);
1250                 if (r)
1251                         return r;
1252         }
1253
1254         /* set up the compute queues */
1255         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
1256                 unsigned irq_type;
1257
1258                 /* max 32 queues per MEC */
1259                 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
1260                         DRM_ERROR("Too many (%d) compute rings!\n", i);
1261                         break;
1262                 }
1263                 ring = &adev->gfx.compute_ring[i];
1264                 ring->ring_obj = NULL;
1265                 ring->use_doorbell = true;
1266                 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i;
1267                 ring->me = 1; /* first MEC */
1268                 ring->pipe = i / 8;
1269                 ring->queue = i % 8;
1270                 sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
1271                 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
1272                 /* type-2 packets are deprecated on MEC, use type-3 instead */
1273                 r = amdgpu_ring_init(adev, ring, 1024 * 1024,
1274                                      PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
1275                                      &adev->gfx.eop_irq, irq_type,
1276                                      AMDGPU_RING_TYPE_COMPUTE);
1277                 if (r)
1278                         return r;
1279         }
1280
1281         /* reserve GDS, GWS and OA resource for gfx */
1282         r = amdgpu_bo_create(adev, adev->gds.mem.gfx_partition_size,
1283                         PAGE_SIZE, true,
1284                         AMDGPU_GEM_DOMAIN_GDS, 0, NULL,
1285                         NULL, &adev->gds.gds_gfx_bo);
1286         if (r)
1287                 return r;
1288
1289         r = amdgpu_bo_create(adev, adev->gds.gws.gfx_partition_size,
1290                 PAGE_SIZE, true,
1291                 AMDGPU_GEM_DOMAIN_GWS, 0, NULL,
1292                 NULL, &adev->gds.gws_gfx_bo);
1293         if (r)
1294                 return r;
1295
1296         r = amdgpu_bo_create(adev, adev->gds.oa.gfx_partition_size,
1297                         PAGE_SIZE, true,
1298                         AMDGPU_GEM_DOMAIN_OA, 0, NULL,
1299                         NULL, &adev->gds.oa_gfx_bo);
1300         if (r)
1301                 return r;
1302
1303         adev->gfx.ce_ram_size = 0x8000;
1304
1305         gfx_v8_0_gpu_early_init(adev);
1306
1307         return 0;
1308 }
1309
1310 static int gfx_v8_0_sw_fini(void *handle)
1311 {
1312         int i;
1313         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1314
1315         amdgpu_bo_unref(&adev->gds.oa_gfx_bo);
1316         amdgpu_bo_unref(&adev->gds.gws_gfx_bo);
1317         amdgpu_bo_unref(&adev->gds.gds_gfx_bo);
1318
1319         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1320                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1321         for (i = 0; i < adev->gfx.num_compute_rings; i++)
1322                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1323
1324         gfx_v8_0_mec_fini(adev);
1325
1326         return 0;
1327 }
1328
1329 static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
1330 {
1331         const u32 num_tile_mode_states = 32;
1332         const u32 num_secondary_tile_mode_states = 16;
1333         u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
1334
1335         switch (adev->gfx.config.mem_row_size_in_kb) {
1336         case 1:
1337                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
1338                 break;
1339         case 2:
1340         default:
1341                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
1342                 break;
1343         case 4:
1344                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
1345                 break;
1346         }
1347
1348         switch (adev->asic_type) {
1349         case CHIP_TOPAZ:
1350                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1351                         switch (reg_offset) {
1352                         case 0:
1353                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1354                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1355                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1356                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1357                                 break;
1358                         case 1:
1359                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1360                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1361                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1362                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1363                                 break;
1364                         case 2:
1365                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1366                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1367                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1368                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1369                                 break;
1370                         case 3:
1371                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1372                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1373                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1374                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1375                                 break;
1376                         case 4:
1377                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1378                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1379                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1380                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1381                                 break;
1382                         case 5:
1383                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1384                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1385                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1386                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1387                                 break;
1388                         case 6:
1389                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1390                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1391                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1392                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1393                                 break;
1394                         case 8:
1395                                 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1396                                                 PIPE_CONFIG(ADDR_SURF_P2));
1397                                 break;
1398                         case 9:
1399                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1400                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1401                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1402                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1403                                 break;
1404                         case 10:
1405                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1406                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1407                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1408                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1409                                 break;
1410                         case 11:
1411                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1412                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1413                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1414                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1415                                 break;
1416                         case 13:
1417                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1418                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1419                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1420                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1421                                 break;
1422                         case 14:
1423                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1424                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1425                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1426                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1427                                 break;
1428                         case 15:
1429                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1430                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1431                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1432                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1433                                 break;
1434                         case 16:
1435                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1436                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1437                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1438                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1439                                 break;
1440                         case 18:
1441                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1442                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1443                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1444                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1445                                 break;
1446                         case 19:
1447                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1448                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1449                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1450                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1451                                 break;
1452                         case 20:
1453                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1454                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1455                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1456                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1457                                 break;
1458                         case 21:
1459                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1460                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1461                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1462                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1463                                 break;
1464                         case 22:
1465                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1466                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1467                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1468                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1469                                 break;
1470                         case 24:
1471                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1472                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1473                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1474                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1475                                 break;
1476                         case 25:
1477                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1478                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1479                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1480                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1481                                 break;
1482                         case 26:
1483                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1484                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1485                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1486                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1487                                 break;
1488                         case 27:
1489                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1490                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1491                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1492                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1493                                 break;
1494                         case 28:
1495                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1496                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1497                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1498                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1499                                 break;
1500                         case 29:
1501                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1502                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1503                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1504                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1505                                 break;
1506                         case 7:
1507                         case 12:
1508                         case 17:
1509                         case 23:
1510                                 /* unused idx */
1511                                 continue;
1512                         default:
1513                                 gb_tile_moden = 0;
1514                                 break;
1515                         };
1516                         adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
1517                         WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
1518                 }
1519                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
1520                         switch (reg_offset) {
1521                         case 0:
1522                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1523                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1524                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1525                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1526                                 break;
1527                         case 1:
1528                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1529                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1530                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1531                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1532                                 break;
1533                         case 2:
1534                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1535                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1536                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1537                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1538                                 break;
1539                         case 3:
1540                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1541                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1542                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1543                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1544                                 break;
1545                         case 4:
1546                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1547                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1548                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1549                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1550                                 break;
1551                         case 5:
1552                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1553                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1554                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1555                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1556                                 break;
1557                         case 6:
1558                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1559                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1560                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1561                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1562                                 break;
1563                         case 8:
1564                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1565                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1566                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1567                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1568                                 break;
1569                         case 9:
1570                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1571                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1572                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1573                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1574                                 break;
1575                         case 10:
1576                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1577                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1578                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1579                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1580                                 break;
1581                         case 11:
1582                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1583                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1584                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1585                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1586                                 break;
1587                         case 12:
1588                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1589                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1590                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1591                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1592                                 break;
1593                         case 13:
1594                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1595                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1596                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1597                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1598                                 break;
1599                         case 14:
1600                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1601                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1602                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1603                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1604                                 break;
1605                         case 7:
1606                                 /* unused idx */
1607                                 continue;
1608                         default:
1609                                 gb_tile_moden = 0;
1610                                 break;
1611                         };
1612                         adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
1613                         WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
1614                 }
1615         case CHIP_FIJI:
1616         case CHIP_TONGA:
1617                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1618                         switch (reg_offset) {
1619                         case 0:
1620                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1621                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1622                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1623                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1624                                 break;
1625                         case 1:
1626                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1627                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1628                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1629                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1630                                 break;
1631                         case 2:
1632                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1633                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1634                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1635                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1636                                 break;
1637                         case 3:
1638                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1639                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1640                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1641                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1642                                 break;
1643                         case 4:
1644                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1645                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1646                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1647                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1648                                 break;
1649                         case 5:
1650                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1651                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1652                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1653                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1654                                 break;
1655                         case 6:
1656                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1657                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1658                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1659                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1660                                 break;
1661                         case 7:
1662                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1663                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1664                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1665                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1666                                 break;
1667                         case 8:
1668                                 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1669                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
1670                                 break;
1671                         case 9:
1672                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1673                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1674                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1675                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1676                                 break;
1677                         case 10:
1678                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1679                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1680                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1681                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1682                                 break;
1683                         case 11:
1684                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1685                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1686                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1687                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1688                                 break;
1689                         case 12:
1690                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1691                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1692                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1693                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1694                                 break;
1695                         case 13:
1696                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1697                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1698                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1699                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1700                                 break;
1701                         case 14:
1702                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1703                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1704                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1705                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1706                                 break;
1707                         case 15:
1708                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1709                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1710                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1711                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1712                                 break;
1713                         case 16:
1714                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1715                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1716                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1717                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1718                                 break;
1719                         case 17:
1720                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1721                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1722                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1723                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1724                                 break;
1725                         case 18:
1726                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1727                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1728                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1729                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1730                                 break;
1731                         case 19:
1732                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1733                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1734                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1735                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1736                                 break;
1737                         case 20:
1738                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1739                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1740                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1741                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1742                                 break;
1743                         case 21:
1744                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1745                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1746                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1747                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1748                                 break;
1749                         case 22:
1750                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1751                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1752                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1753                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1754                                 break;
1755                         case 23:
1756                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1757                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1758                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1759                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1760                                 break;
1761                         case 24:
1762                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1763                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1764                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1765                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1766                                 break;
1767                         case 25:
1768                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1769                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1770                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1771                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1772                                 break;
1773                         case 26:
1774                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1775                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1776                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1777                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1778                                 break;
1779                         case 27:
1780                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1781                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1782                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1783                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1784                                 break;
1785                         case 28:
1786                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1787                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1788                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1789                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1790                                 break;
1791                         case 29:
1792                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1793                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1794                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1795                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1796                                 break;
1797                         case 30:
1798                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1799                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1800                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1801                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1802                                 break;
1803                         default:
1804                                 gb_tile_moden = 0;
1805                                 break;
1806                         };
1807                         adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
1808                         WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
1809                 }
1810                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
1811                         switch (reg_offset) {
1812                         case 0:
1813                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1814                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1815                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1816                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1817                                 break;
1818                         case 1:
1819                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1820                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1821                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1822                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1823                                 break;
1824                         case 2:
1825                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1826                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1827                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1828                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1829                                 break;
1830                         case 3:
1831                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1832                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1833                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1834                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1835                                 break;
1836                         case 4:
1837                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1838                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1839                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1840                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1841                                 break;
1842                         case 5:
1843                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1844                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1845                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1846                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1847                                 break;
1848                         case 6:
1849                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1850                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1851                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1852                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1853                                 break;
1854                         case 8:
1855                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1856                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1857                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1858                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1859                                 break;
1860                         case 9:
1861                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1862                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1863                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1864                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1865                                 break;
1866                         case 10:
1867                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1868                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1869                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1870                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1871                                 break;
1872                         case 11:
1873                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1874                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1875                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1876                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1877                                 break;
1878                         case 12:
1879                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1880                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1881                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1882                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1883                                 break;
1884                         case 13:
1885                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1886                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1887                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1888                                                 NUM_BANKS(ADDR_SURF_4_BANK));
1889                                 break;
1890                         case 14:
1891                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1892                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1893                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1894                                                 NUM_BANKS(ADDR_SURF_4_BANK));
1895                                 break;
1896                         case 7:
1897                                 /* unused idx */
1898                                 continue;
1899                         default:
1900                                 gb_tile_moden = 0;
1901                                 break;
1902                         };
1903                         adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
1904                         WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
1905                 }
1906                 break;
1907         case CHIP_STONEY:
1908                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1909                         switch (reg_offset) {
1910                         case 0:
1911                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1912                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1913                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1914                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1915                                 break;
1916                         case 1:
1917                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1918                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1919                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1920                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1921                                 break;
1922                         case 2:
1923                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1924                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1925                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1926                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1927                                 break;
1928                         case 3:
1929                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1930                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1931                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1932                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1933                                 break;
1934                         case 4:
1935                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1936                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1937                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1938                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1939                                 break;
1940                         case 5:
1941                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1942                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1943                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1944                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1945                                 break;
1946                         case 6:
1947                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1948                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1949                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1950                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1951                                 break;
1952                         case 8:
1953                                 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1954                                                 PIPE_CONFIG(ADDR_SURF_P2));
1955                                 break;
1956                         case 9:
1957                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1958                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1959                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1960                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1961                                 break;
1962                         case 10:
1963                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1964                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1965                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1966                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1967                                 break;
1968                         case 11:
1969                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1970                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1971                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1972                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1973                                 break;
1974                         case 13:
1975                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1976                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1977                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1978                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1979                                 break;
1980                         case 14:
1981                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1982                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1983                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1984                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1985                                 break;
1986                         case 15:
1987                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1988                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1989                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1990                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1991                                 break;
1992                         case 16:
1993                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1994                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1995                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1996                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1997                                 break;
1998                         case 18:
1999                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2000                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2001                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2002                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2003                                 break;
2004                         case 19:
2005                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2006                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2007                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2008                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2009                                 break;
2010                         case 20:
2011                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2012                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2013                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2014                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2015                                 break;
2016                         case 21:
2017                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2018                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2019                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2020                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2021                                 break;
2022                         case 22:
2023                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2024                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2025                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2026                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2027                                 break;
2028                         case 24:
2029                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2030                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2031                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2032                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2033                                 break;
2034                         case 25:
2035                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2036                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2037                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2038                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2039                                 break;
2040                         case 26:
2041                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2042                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2043                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2044                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2045                                 break;
2046                         case 27:
2047                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2048                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2049                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2050                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2051                                 break;
2052                         case 28:
2053                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2054                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2055                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2056                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2057                                 break;
2058                         case 29:
2059                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2060                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2061                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2062                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2063                                 break;
2064                         case 7:
2065                         case 12:
2066                         case 17:
2067                         case 23:
2068                                 /* unused idx */
2069                                 continue;
2070                         default:
2071                                 gb_tile_moden = 0;
2072                                 break;
2073                         };
2074                         adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
2075                         WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
2076                 }
2077                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
2078                         switch (reg_offset) {
2079                         case 0:
2080                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2081                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2082                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2083                                                 NUM_BANKS(ADDR_SURF_8_BANK));
2084                                 break;
2085                         case 1:
2086                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2087                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2088                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2089                                                 NUM_BANKS(ADDR_SURF_8_BANK));
2090                                 break;
2091                         case 2:
2092                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2093                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2094                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2095                                                 NUM_BANKS(ADDR_SURF_8_BANK));
2096                                 break;
2097                         case 3:
2098                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2099                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2100                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2101                                                 NUM_BANKS(ADDR_SURF_8_BANK));
2102                                 break;
2103                         case 4:
2104                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2105                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2106                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2107                                                 NUM_BANKS(ADDR_SURF_8_BANK));
2108                                 break;
2109                         case 5:
2110                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2111                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2112                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2113                                                 NUM_BANKS(ADDR_SURF_8_BANK));
2114                                 break;
2115                         case 6:
2116                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2117                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2118                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2119                                                 NUM_BANKS(ADDR_SURF_8_BANK));
2120                                 break;
2121                         case 8:
2122                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2123                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2124                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2125                                                 NUM_BANKS(ADDR_SURF_16_BANK));
2126                                 break;
2127                         case 9:
2128                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2129                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2130                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2131                                                 NUM_BANKS(ADDR_SURF_16_BANK));
2132                                 break;
2133                         case 10:
2134                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2135                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2136                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2137                                                 NUM_BANKS(ADDR_SURF_16_BANK));
2138                                 break;
2139                         case 11:
2140                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2141                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2142                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2143                                                 NUM_BANKS(ADDR_SURF_16_BANK));
2144                                 break;
2145                         case 12:
2146                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2147                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2148                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2149                                                 NUM_BANKS(ADDR_SURF_16_BANK));
2150                                 break;
2151                         case 13:
2152                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2153                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2154                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2155                                                 NUM_BANKS(ADDR_SURF_16_BANK));
2156                                 break;
2157                         case 14:
2158                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2159                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2160                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2161                                                 NUM_BANKS(ADDR_SURF_8_BANK));
2162                                 break;
2163                         case 7:
2164                                 /* unused idx */
2165                                 continue;
2166                         default:
2167                                 gb_tile_moden = 0;
2168                                 break;
2169                         };
2170                         adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
2171                         WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
2172                 }
2173                 break;
2174         case CHIP_CARRIZO:
2175         default:
2176                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
2177                         switch (reg_offset) {
2178                         case 0:
2179                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2180                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2181                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2182                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2183                                 break;
2184                         case 1:
2185                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2186                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2187                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2188                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2189                                 break;
2190                         case 2:
2191                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2192                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2193                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2194                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2195                                 break;
2196                         case 3:
2197                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2198                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2199                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2200                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2201                                 break;
2202                         case 4:
2203                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2204                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2205                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2206                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2207                                 break;
2208                         case 5:
2209                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2210                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2211                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2212                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2213                                 break;
2214                         case 6:
2215                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2216                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2217                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2218                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2219                                 break;
2220                         case 8:
2221                                 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2222                                                 PIPE_CONFIG(ADDR_SURF_P2));
2223                                 break;
2224                         case 9:
2225                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2226                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2227                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2228                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2229                                 break;
2230                         case 10:
2231                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2232                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2233                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2234                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2235                                 break;
2236                         case 11:
2237                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2238                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2239                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2240                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2241                                 break;
2242                         case 13:
2243                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2244                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2245                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2246                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2247                                 break;
2248                         case 14:
2249                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2250                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2251                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2252                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2253                                 break;
2254                         case 15:
2255                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2256                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2257                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2258                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2259                                 break;
2260                         case 16:
2261                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2262                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2263                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2264                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2265                                 break;
2266                         case 18:
2267                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2268                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2269                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2270                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2271                                 break;
2272                         case 19:
2273                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2274                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2275                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2276                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2277                                 break;
2278                         case 20:
2279                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2280                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2281                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2282                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2283                                 break;
2284                         case 21:
2285                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2286                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2287                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2288                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2289                                 break;
2290                         case 22:
2291                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2292                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2293                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2294                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2295                                 break;
2296                         case 24:
2297                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2298                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2299                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2300                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2301                                 break;
2302                         case 25:
2303                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2304                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2305                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2306                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2307                                 break;
2308                         case 26:
2309                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2310                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2311                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2312                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2313                                 break;
2314                         case 27:
2315                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2316                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2317                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2318                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2319                                 break;
2320                         case 28:
2321                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2322                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2323                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2324                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2325                                 break;
2326                         case 29:
2327                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2328                                                 PIPE_CONFIG(ADDR_SURF_P2) |
2329                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2330                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2331                                 break;
2332                         case 7:
2333                         case 12:
2334                         case 17:
2335                         case 23:
2336                                 /* unused idx */
2337                                 continue;
2338                         default:
2339                                 gb_tile_moden = 0;
2340                                 break;
2341                         };
2342                         adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
2343                         WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
2344                 }
2345                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
2346                         switch (reg_offset) {
2347                         case 0:
2348                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2349                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2350                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2351                                                 NUM_BANKS(ADDR_SURF_8_BANK));
2352                                 break;
2353                         case 1:
2354                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2355                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2356                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2357                                                 NUM_BANKS(ADDR_SURF_8_BANK));
2358                                 break;
2359                         case 2:
2360                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2361                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2362                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2363                                                 NUM_BANKS(ADDR_SURF_8_BANK));
2364                                 break;
2365                         case 3:
2366                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2367                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2368                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2369                                                 NUM_BANKS(ADDR_SURF_8_BANK));
2370                                 break;
2371                         case 4:
2372                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2373                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2374                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2375                                                 NUM_BANKS(ADDR_SURF_8_BANK));
2376                                 break;
2377                         case 5:
2378                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2379                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2380                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2381                                                 NUM_BANKS(ADDR_SURF_8_BANK));
2382                                 break;
2383                         case 6:
2384                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2385                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2386                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2387                                                 NUM_BANKS(ADDR_SURF_8_BANK));
2388                                 break;
2389                         case 8:
2390                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2391                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2392                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2393                                                 NUM_BANKS(ADDR_SURF_16_BANK));
2394                                 break;
2395                         case 9:
2396                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2397                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2398                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2399                                                 NUM_BANKS(ADDR_SURF_16_BANK));
2400                                 break;
2401                         case 10:
2402                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2403                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2404                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2405                                                 NUM_BANKS(ADDR_SURF_16_BANK));
2406                                 break;
2407                         case 11:
2408                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2409                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2410                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2411                                                 NUM_BANKS(ADDR_SURF_16_BANK));
2412                                 break;
2413                         case 12:
2414                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2415                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2416                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2417                                                 NUM_BANKS(ADDR_SURF_16_BANK));
2418                                 break;
2419                         case 13:
2420                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2421                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2422                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2423                                                 NUM_BANKS(ADDR_SURF_16_BANK));
2424                                 break;
2425                         case 14:
2426                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2427                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2428                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2429                                                 NUM_BANKS(ADDR_SURF_8_BANK));
2430                                 break;
2431                         case 7:
2432                                 /* unused idx */
2433                                 continue;
2434                         default:
2435                                 gb_tile_moden = 0;
2436                                 break;
2437                         };
2438                         adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
2439                         WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
2440                 }
2441         }
2442 }
2443
2444 static u32 gfx_v8_0_create_bitmask(u32 bit_width)
2445 {
2446         u32 i, mask = 0;
2447
2448         for (i = 0; i < bit_width; i++) {
2449                 mask <<= 1;
2450                 mask |= 1;
2451         }
2452         return mask;
2453 }
2454
2455 void gfx_v8_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num)
2456 {
2457         u32 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
2458
2459         if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) {
2460                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
2461                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
2462         } else if (se_num == 0xffffffff) {
2463                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
2464                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
2465         } else if (sh_num == 0xffffffff) {
2466                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
2467                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
2468         } else {
2469                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
2470                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
2471         }
2472         WREG32(mmGRBM_GFX_INDEX, data);
2473 }
2474
2475 static u32 gfx_v8_0_get_rb_disabled(struct amdgpu_device *adev,
2476                                     u32 max_rb_num_per_se,
2477                                     u32 sh_per_se)
2478 {
2479         u32 data, mask;
2480
2481         data = RREG32(mmCC_RB_BACKEND_DISABLE);
2482         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
2483
2484         data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
2485
2486         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
2487
2488         mask = gfx_v8_0_create_bitmask(max_rb_num_per_se / sh_per_se);
2489
2490         return data & mask;
2491 }
2492
2493 static void gfx_v8_0_setup_rb(struct amdgpu_device *adev,
2494                               u32 se_num, u32 sh_per_se,
2495                               u32 max_rb_num_per_se)
2496 {
2497         int i, j;
2498         u32 data, mask;
2499         u32 disabled_rbs = 0;
2500         u32 enabled_rbs = 0;
2501
2502         mutex_lock(&adev->grbm_idx_mutex);
2503         for (i = 0; i < se_num; i++) {
2504                 for (j = 0; j < sh_per_se; j++) {
2505                         gfx_v8_0_select_se_sh(adev, i, j);
2506                         data = gfx_v8_0_get_rb_disabled(adev,
2507                                               max_rb_num_per_se, sh_per_se);
2508                         disabled_rbs |= data << ((i * sh_per_se + j) *
2509                                                  RB_BITMAP_WIDTH_PER_SH);
2510                 }
2511         }
2512         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2513         mutex_unlock(&adev->grbm_idx_mutex);
2514
2515         mask = 1;
2516         for (i = 0; i < max_rb_num_per_se * se_num; i++) {
2517                 if (!(disabled_rbs & mask))
2518                         enabled_rbs |= mask;
2519                 mask <<= 1;
2520         }
2521
2522         adev->gfx.config.backend_enable_mask = enabled_rbs;
2523
2524         mutex_lock(&adev->grbm_idx_mutex);
2525         for (i = 0; i < se_num; i++) {
2526                 gfx_v8_0_select_se_sh(adev, i, 0xffffffff);
2527                 data = 0;
2528                 for (j = 0; j < sh_per_se; j++) {
2529                         switch (enabled_rbs & 3) {
2530                         case 0:
2531                                 if (j == 0)
2532                                         data |= (RASTER_CONFIG_RB_MAP_3 <<
2533                                                  PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT);
2534                                 else
2535                                         data |= (RASTER_CONFIG_RB_MAP_0 <<
2536                                                  PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT);
2537                                 break;
2538                         case 1:
2539                                 data |= (RASTER_CONFIG_RB_MAP_0 <<
2540                                          (i * sh_per_se + j) * 2);
2541                                 break;
2542                         case 2:
2543                                 data |= (RASTER_CONFIG_RB_MAP_3 <<
2544                                          (i * sh_per_se + j) * 2);
2545                                 break;
2546                         case 3:
2547                         default:
2548                                 data |= (RASTER_CONFIG_RB_MAP_2 <<
2549                                          (i * sh_per_se + j) * 2);
2550                                 break;
2551                         }
2552                         enabled_rbs >>= 2;
2553                 }
2554                 WREG32(mmPA_SC_RASTER_CONFIG, data);
2555         }
2556         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2557         mutex_unlock(&adev->grbm_idx_mutex);
2558 }
2559
2560 /**
2561  * gfx_v8_0_init_compute_vmid - gart enable
2562  *
2563  * @rdev: amdgpu_device pointer
2564  *
2565  * Initialize compute vmid sh_mem registers
2566  *
2567  */
2568 #define DEFAULT_SH_MEM_BASES    (0x6000)
2569 #define FIRST_COMPUTE_VMID      (8)
2570 #define LAST_COMPUTE_VMID       (16)
2571 static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev)
2572 {
2573         int i;
2574         uint32_t sh_mem_config;
2575         uint32_t sh_mem_bases;
2576
2577         /*
2578          * Configure apertures:
2579          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
2580          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
2581          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
2582          */
2583         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
2584
2585         sh_mem_config = SH_MEM_ADDRESS_MODE_HSA64 <<
2586                         SH_MEM_CONFIG__ADDRESS_MODE__SHIFT |
2587                         SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
2588                         SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT |
2589                         MTYPE_CC << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT |
2590                         SH_MEM_CONFIG__PRIVATE_ATC_MASK;
2591
2592         mutex_lock(&adev->srbm_mutex);
2593         for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
2594                 vi_srbm_select(adev, 0, 0, 0, i);
2595                 /* CP and shaders */
2596                 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
2597                 WREG32(mmSH_MEM_APE1_BASE, 1);
2598                 WREG32(mmSH_MEM_APE1_LIMIT, 0);
2599                 WREG32(mmSH_MEM_BASES, sh_mem_bases);
2600         }
2601         vi_srbm_select(adev, 0, 0, 0, 0);
2602         mutex_unlock(&adev->srbm_mutex);
2603 }
2604
2605 static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
2606 {
2607         u32 tmp;
2608         int i;
2609
2610         tmp = RREG32(mmGRBM_CNTL);
2611         tmp = REG_SET_FIELD(tmp, GRBM_CNTL, READ_TIMEOUT, 0xff);
2612         WREG32(mmGRBM_CNTL, tmp);
2613
2614         WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
2615         WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
2616         WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
2617         WREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET,
2618                adev->gfx.config.gb_addr_config & 0x70);
2619         WREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET,
2620                adev->gfx.config.gb_addr_config & 0x70);
2621         WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
2622         WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
2623         WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
2624
2625         gfx_v8_0_tiling_mode_table_init(adev);
2626
2627         gfx_v8_0_setup_rb(adev, adev->gfx.config.max_shader_engines,
2628                                  adev->gfx.config.max_sh_per_se,
2629                                  adev->gfx.config.max_backends_per_se);
2630
2631         /* XXX SH_MEM regs */
2632         /* where to put LDS, scratch, GPUVM in FSA64 space */
2633         mutex_lock(&adev->srbm_mutex);
2634         for (i = 0; i < 16; i++) {
2635                 vi_srbm_select(adev, 0, 0, 0, i);
2636                 /* CP and shaders */
2637                 if (i == 0) {
2638                         tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC);
2639                         tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
2640                         tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
2641                                             SH_MEM_ALIGNMENT_MODE_UNALIGNED);
2642                         WREG32(mmSH_MEM_CONFIG, tmp);
2643                 } else {
2644                         tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC);
2645                         tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_NC);
2646                         tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
2647                                             SH_MEM_ALIGNMENT_MODE_UNALIGNED);
2648                         WREG32(mmSH_MEM_CONFIG, tmp);
2649                 }
2650
2651                 WREG32(mmSH_MEM_APE1_BASE, 1);
2652                 WREG32(mmSH_MEM_APE1_LIMIT, 0);
2653                 WREG32(mmSH_MEM_BASES, 0);
2654         }
2655         vi_srbm_select(adev, 0, 0, 0, 0);
2656         mutex_unlock(&adev->srbm_mutex);
2657
2658         gfx_v8_0_init_compute_vmid(adev);
2659
2660         mutex_lock(&adev->grbm_idx_mutex);
2661         /*
2662          * making sure that the following register writes will be broadcasted
2663          * to all the shaders
2664          */
2665         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2666
2667         WREG32(mmPA_SC_FIFO_SIZE,
2668                    (adev->gfx.config.sc_prim_fifo_size_frontend <<
2669                         PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
2670                    (adev->gfx.config.sc_prim_fifo_size_backend <<
2671                         PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
2672                    (adev->gfx.config.sc_hiz_tile_fifo_size <<
2673                         PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
2674                    (adev->gfx.config.sc_earlyz_tile_fifo_size <<
2675                         PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
2676         mutex_unlock(&adev->grbm_idx_mutex);
2677
2678 }
2679
2680 static void gfx_v8_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
2681 {
2682         u32 i, j, k;
2683         u32 mask;
2684
2685         mutex_lock(&adev->grbm_idx_mutex);
2686         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
2687                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
2688                         gfx_v8_0_select_se_sh(adev, i, j);
2689                         for (k = 0; k < adev->usec_timeout; k++) {
2690                                 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
2691                                         break;
2692                                 udelay(1);
2693                         }
2694                 }
2695         }
2696         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2697         mutex_unlock(&adev->grbm_idx_mutex);
2698
2699         mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
2700                 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
2701                 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
2702                 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
2703         for (k = 0; k < adev->usec_timeout; k++) {
2704                 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
2705                         break;
2706                 udelay(1);
2707         }
2708 }
2709
2710 static void gfx_v8_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
2711                                                bool enable)
2712 {
2713         u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
2714
2715         if (enable) {
2716                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1);
2717                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1);
2718                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1);
2719                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1);
2720         } else {
2721                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 0);
2722                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 0);
2723                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 0);
2724                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 0);
2725         }
2726         WREG32(mmCP_INT_CNTL_RING0, tmp);
2727 }
2728
2729 void gfx_v8_0_rlc_stop(struct amdgpu_device *adev)
2730 {
2731         u32 tmp = RREG32(mmRLC_CNTL);
2732
2733         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
2734         WREG32(mmRLC_CNTL, tmp);
2735
2736         gfx_v8_0_enable_gui_idle_interrupt(adev, false);
2737
2738         gfx_v8_0_wait_for_rlc_serdes(adev);
2739 }
2740
2741 static void gfx_v8_0_rlc_reset(struct amdgpu_device *adev)
2742 {
2743         u32 tmp = RREG32(mmGRBM_SOFT_RESET);
2744
2745         tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2746         WREG32(mmGRBM_SOFT_RESET, tmp);
2747         udelay(50);
2748         tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2749         WREG32(mmGRBM_SOFT_RESET, tmp);
2750         udelay(50);
2751 }
2752
2753 static void gfx_v8_0_rlc_start(struct amdgpu_device *adev)
2754 {
2755         u32 tmp = RREG32(mmRLC_CNTL);
2756
2757         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 1);
2758         WREG32(mmRLC_CNTL, tmp);
2759
2760         /* carrizo do enable cp interrupt after cp inited */
2761         if (!(adev->flags & AMD_IS_APU))
2762                 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
2763
2764         udelay(50);
2765 }
2766
2767 static int gfx_v8_0_rlc_load_microcode(struct amdgpu_device *adev)
2768 {
2769         const struct rlc_firmware_header_v2_0 *hdr;
2770         const __le32 *fw_data;
2771         unsigned i, fw_size;
2772
2773         if (!adev->gfx.rlc_fw)
2774                 return -EINVAL;
2775
2776         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
2777         amdgpu_ucode_print_rlc_hdr(&hdr->header);
2778
2779         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2780                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2781         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2782
2783         WREG32(mmRLC_GPM_UCODE_ADDR, 0);
2784         for (i = 0; i < fw_size; i++)
2785                 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
2786         WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
2787
2788         return 0;
2789 }
2790
2791 static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
2792 {
2793         int r;
2794
2795         gfx_v8_0_rlc_stop(adev);
2796
2797         /* disable CG */
2798         WREG32(mmRLC_CGCG_CGLS_CTRL, 0);
2799
2800         /* disable PG */
2801         WREG32(mmRLC_PG_CNTL, 0);
2802
2803         gfx_v8_0_rlc_reset(adev);
2804
2805         if (!adev->firmware.smu_load) {
2806                 /* legacy rlc firmware loading */
2807                 r = gfx_v8_0_rlc_load_microcode(adev);
2808                 if (r)
2809                         return r;
2810         } else {
2811                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
2812                                                 AMDGPU_UCODE_ID_RLC_G);
2813                 if (r)
2814                         return -EINVAL;
2815         }
2816
2817         gfx_v8_0_rlc_start(adev);
2818
2819         return 0;
2820 }
2821
2822 static void gfx_v8_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2823 {
2824         int i;
2825         u32 tmp = RREG32(mmCP_ME_CNTL);
2826
2827         if (enable) {
2828                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0);
2829                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0);
2830                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0);
2831         } else {
2832                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
2833                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
2834                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
2835                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2836                         adev->gfx.gfx_ring[i].ready = false;
2837         }
2838         WREG32(mmCP_ME_CNTL, tmp);
2839         udelay(50);
2840 }
2841
2842 static int gfx_v8_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2843 {
2844         const struct gfx_firmware_header_v1_0 *pfp_hdr;
2845         const struct gfx_firmware_header_v1_0 *ce_hdr;
2846         const struct gfx_firmware_header_v1_0 *me_hdr;
2847         const __le32 *fw_data;
2848         unsigned i, fw_size;
2849
2850         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2851                 return -EINVAL;
2852
2853         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2854                 adev->gfx.pfp_fw->data;
2855         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
2856                 adev->gfx.ce_fw->data;
2857         me_hdr = (const struct gfx_firmware_header_v1_0 *)
2858                 adev->gfx.me_fw->data;
2859
2860         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2861         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2862         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2863
2864         gfx_v8_0_cp_gfx_enable(adev, false);
2865
2866         /* PFP */
2867         fw_data = (const __le32 *)
2868                 (adev->gfx.pfp_fw->data +
2869                  le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2870         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2871         WREG32(mmCP_PFP_UCODE_ADDR, 0);
2872         for (i = 0; i < fw_size; i++)
2873                 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2874         WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2875
2876         /* CE */
2877         fw_data = (const __le32 *)
2878                 (adev->gfx.ce_fw->data +
2879                  le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2880         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2881         WREG32(mmCP_CE_UCODE_ADDR, 0);
2882         for (i = 0; i < fw_size; i++)
2883                 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2884         WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2885
2886         /* ME */
2887         fw_data = (const __le32 *)
2888                 (adev->gfx.me_fw->data +
2889                  le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2890         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2891         WREG32(mmCP_ME_RAM_WADDR, 0);
2892         for (i = 0; i < fw_size; i++)
2893                 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2894         WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2895
2896         return 0;
2897 }
2898
2899 static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev)
2900 {
2901         u32 count = 0;
2902         const struct cs_section_def *sect = NULL;
2903         const struct cs_extent_def *ext = NULL;
2904
2905         /* begin clear state */
2906         count += 2;
2907         /* context control state */
2908         count += 3;
2909
2910         for (sect = vi_cs_data; sect->section != NULL; ++sect) {
2911                 for (ext = sect->section; ext->extent != NULL; ++ext) {
2912                         if (sect->id == SECT_CONTEXT)
2913                                 count += 2 + ext->reg_count;
2914                         else
2915                                 return 0;
2916                 }
2917         }
2918         /* pa_sc_raster_config/pa_sc_raster_config1 */
2919         count += 4;
2920         /* end clear state */
2921         count += 2;
2922         /* clear state */
2923         count += 2;
2924
2925         return count;
2926 }
2927
2928 static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev)
2929 {
2930         struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2931         const struct cs_section_def *sect = NULL;
2932         const struct cs_extent_def *ext = NULL;
2933         int r, i;
2934
2935         /* init the CP */
2936         WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2937         WREG32(mmCP_ENDIAN_SWAP, 0);
2938         WREG32(mmCP_DEVICE_ID, 1);
2939
2940         gfx_v8_0_cp_gfx_enable(adev, true);
2941
2942         r = amdgpu_ring_lock(ring, gfx_v8_0_get_csb_size(adev) + 4);
2943         if (r) {
2944                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2945                 return r;
2946         }
2947
2948         /* clear state buffer */
2949         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2950         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2951
2952         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2953         amdgpu_ring_write(ring, 0x80000000);
2954         amdgpu_ring_write(ring, 0x80000000);
2955
2956         for (sect = vi_cs_data; sect->section != NULL; ++sect) {
2957                 for (ext = sect->section; ext->extent != NULL; ++ext) {
2958                         if (sect->id == SECT_CONTEXT) {
2959                                 amdgpu_ring_write(ring,
2960                                        PACKET3(PACKET3_SET_CONTEXT_REG,
2961                                                ext->reg_count));
2962                                 amdgpu_ring_write(ring,
2963                                        ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2964                                 for (i = 0; i < ext->reg_count; i++)
2965                                         amdgpu_ring_write(ring, ext->extent[i]);
2966                         }
2967                 }
2968         }
2969
2970         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2971         amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2972         switch (adev->asic_type) {
2973         case CHIP_TONGA:
2974         case CHIP_FIJI:
2975                 amdgpu_ring_write(ring, 0x16000012);
2976                 amdgpu_ring_write(ring, 0x0000002A);
2977                 break;
2978         case CHIP_TOPAZ:
2979         case CHIP_CARRIZO:
2980                 amdgpu_ring_write(ring, 0x00000002);
2981                 amdgpu_ring_write(ring, 0x00000000);
2982                 break;
2983         case CHIP_STONEY:
2984                 amdgpu_ring_write(ring, 0x00000000);
2985                 amdgpu_ring_write(ring, 0x00000000);
2986                 break;
2987         default:
2988                 BUG();
2989         }
2990
2991         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2992         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2993
2994         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2995         amdgpu_ring_write(ring, 0);
2996
2997         /* init the CE partitions */
2998         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2999         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
3000         amdgpu_ring_write(ring, 0x8000);
3001         amdgpu_ring_write(ring, 0x8000);
3002
3003         amdgpu_ring_unlock_commit(ring);
3004
3005         return 0;
3006 }
3007
3008 static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
3009 {
3010         struct amdgpu_ring *ring;
3011         u32 tmp;
3012         u32 rb_bufsz;
3013         u64 rb_addr, rptr_addr;
3014         int r;
3015
3016         /* Set the write pointer delay */
3017         WREG32(mmCP_RB_WPTR_DELAY, 0);
3018
3019         /* set the RB to use vmid 0 */
3020         WREG32(mmCP_RB_VMID, 0);
3021
3022         /* Set ring buffer size */
3023         ring = &adev->gfx.gfx_ring[0];
3024         rb_bufsz = order_base_2(ring->ring_size / 8);
3025         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
3026         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
3027         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3);
3028         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1);
3029 #ifdef __BIG_ENDIAN
3030         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
3031 #endif
3032         WREG32(mmCP_RB0_CNTL, tmp);
3033
3034         /* Initialize the ring buffer's read and write pointers */
3035         WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
3036         ring->wptr = 0;
3037         WREG32(mmCP_RB0_WPTR, ring->wptr);
3038
3039         /* set the wb address wether it's enabled or not */
3040         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3041         WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
3042         WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
3043
3044         mdelay(1);
3045         WREG32(mmCP_RB0_CNTL, tmp);
3046
3047         rb_addr = ring->gpu_addr >> 8;
3048         WREG32(mmCP_RB0_BASE, rb_addr);
3049         WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
3050
3051         /* no gfx doorbells on iceland */
3052         if (adev->asic_type != CHIP_TOPAZ) {
3053                 tmp = RREG32(mmCP_RB_DOORBELL_CONTROL);
3054                 if (ring->use_doorbell) {
3055                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3056                                             DOORBELL_OFFSET, ring->doorbell_index);
3057                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3058                                             DOORBELL_EN, 1);
3059                 } else {
3060                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3061                                             DOORBELL_EN, 0);
3062                 }
3063                 WREG32(mmCP_RB_DOORBELL_CONTROL, tmp);
3064
3065                 if (adev->asic_type == CHIP_TONGA) {
3066                         tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
3067                                             DOORBELL_RANGE_LOWER,
3068                                             AMDGPU_DOORBELL_GFX_RING0);
3069                         WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
3070
3071                         WREG32(mmCP_RB_DOORBELL_RANGE_UPPER,
3072                                CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
3073                 }
3074
3075         }
3076
3077         /* start the ring */
3078         gfx_v8_0_cp_gfx_start(adev);
3079         ring->ready = true;
3080         r = amdgpu_ring_test_ring(ring);
3081         if (r) {
3082                 ring->ready = false;
3083                 return r;
3084         }
3085
3086         return 0;
3087 }
3088
3089 static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
3090 {
3091         int i;
3092
3093         if (enable) {
3094                 WREG32(mmCP_MEC_CNTL, 0);
3095         } else {
3096                 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
3097                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
3098                         adev->gfx.compute_ring[i].ready = false;
3099         }
3100         udelay(50);
3101 }
3102
3103 static int gfx_v8_0_cp_compute_start(struct amdgpu_device *adev)
3104 {
3105         gfx_v8_0_cp_compute_enable(adev, true);
3106
3107         return 0;
3108 }
3109
3110 static int gfx_v8_0_cp_compute_load_microcode(struct amdgpu_device *adev)
3111 {
3112         const struct gfx_firmware_header_v1_0 *mec_hdr;
3113         const __le32 *fw_data;
3114         unsigned i, fw_size;
3115
3116         if (!adev->gfx.mec_fw)
3117                 return -EINVAL;
3118
3119         gfx_v8_0_cp_compute_enable(adev, false);
3120
3121         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3122         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
3123
3124         fw_data = (const __le32 *)
3125                 (adev->gfx.mec_fw->data +
3126                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
3127         fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
3128
3129         /* MEC1 */
3130         WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
3131         for (i = 0; i < fw_size; i++)
3132                 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data+i));
3133         WREG32(mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
3134
3135         /* Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
3136         if (adev->gfx.mec2_fw) {
3137                 const struct gfx_firmware_header_v1_0 *mec2_hdr;
3138
3139                 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
3140                 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
3141
3142                 fw_data = (const __le32 *)
3143                         (adev->gfx.mec2_fw->data +
3144                          le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
3145                 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
3146
3147                 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
3148                 for (i = 0; i < fw_size; i++)
3149                         WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data+i));
3150                 WREG32(mmCP_MEC_ME2_UCODE_ADDR, adev->gfx.mec2_fw_version);
3151         }
3152
3153         return 0;
3154 }
3155
3156 struct vi_mqd {
3157         uint32_t header;  /* ordinal0 */
3158         uint32_t compute_dispatch_initiator;  /* ordinal1 */
3159         uint32_t compute_dim_x;  /* ordinal2 */
3160         uint32_t compute_dim_y;  /* ordinal3 */
3161         uint32_t compute_dim_z;  /* ordinal4 */
3162         uint32_t compute_start_x;  /* ordinal5 */
3163         uint32_t compute_start_y;  /* ordinal6 */
3164         uint32_t compute_start_z;  /* ordinal7 */
3165         uint32_t compute_num_thread_x;  /* ordinal8 */
3166         uint32_t compute_num_thread_y;  /* ordinal9 */
3167         uint32_t compute_num_thread_z;  /* ordinal10 */
3168         uint32_t compute_pipelinestat_enable;  /* ordinal11 */
3169         uint32_t compute_perfcount_enable;  /* ordinal12 */
3170         uint32_t compute_pgm_lo;  /* ordinal13 */
3171         uint32_t compute_pgm_hi;  /* ordinal14 */
3172         uint32_t compute_tba_lo;  /* ordinal15 */
3173         uint32_t compute_tba_hi;  /* ordinal16 */
3174         uint32_t compute_tma_lo;  /* ordinal17 */
3175         uint32_t compute_tma_hi;  /* ordinal18 */
3176         uint32_t compute_pgm_rsrc1;  /* ordinal19 */
3177         uint32_t compute_pgm_rsrc2;  /* ordinal20 */
3178         uint32_t compute_vmid;  /* ordinal21 */
3179         uint32_t compute_resource_limits;  /* ordinal22 */
3180         uint32_t compute_static_thread_mgmt_se0;  /* ordinal23 */
3181         uint32_t compute_static_thread_mgmt_se1;  /* ordinal24 */
3182         uint32_t compute_tmpring_size;  /* ordinal25 */
3183         uint32_t compute_static_thread_mgmt_se2;  /* ordinal26 */
3184         uint32_t compute_static_thread_mgmt_se3;  /* ordinal27 */
3185         uint32_t compute_restart_x;  /* ordinal28 */
3186         uint32_t compute_restart_y;  /* ordinal29 */
3187         uint32_t compute_restart_z;  /* ordinal30 */
3188         uint32_t compute_thread_trace_enable;  /* ordinal31 */
3189         uint32_t compute_misc_reserved;  /* ordinal32 */
3190         uint32_t compute_dispatch_id;  /* ordinal33 */
3191         uint32_t compute_threadgroup_id;  /* ordinal34 */
3192         uint32_t compute_relaunch;  /* ordinal35 */
3193         uint32_t compute_wave_restore_addr_lo;  /* ordinal36 */
3194         uint32_t compute_wave_restore_addr_hi;  /* ordinal37 */
3195         uint32_t compute_wave_restore_control;  /* ordinal38 */
3196         uint32_t reserved9;  /* ordinal39 */
3197         uint32_t reserved10;  /* ordinal40 */
3198         uint32_t reserved11;  /* ordinal41 */
3199         uint32_t reserved12;  /* ordinal42 */
3200         uint32_t reserved13;  /* ordinal43 */
3201         uint32_t reserved14;  /* ordinal44 */
3202         uint32_t reserved15;  /* ordinal45 */
3203         uint32_t reserved16;  /* ordinal46 */
3204         uint32_t reserved17;  /* ordinal47 */
3205         uint32_t reserved18;  /* ordinal48 */
3206         uint32_t reserved19;  /* ordinal49 */
3207         uint32_t reserved20;  /* ordinal50 */
3208         uint32_t reserved21;  /* ordinal51 */
3209         uint32_t reserved22;  /* ordinal52 */
3210         uint32_t reserved23;  /* ordinal53 */
3211         uint32_t reserved24;  /* ordinal54 */
3212         uint32_t reserved25;  /* ordinal55 */
3213         uint32_t reserved26;  /* ordinal56 */
3214         uint32_t reserved27;  /* ordinal57 */
3215         uint32_t reserved28;  /* ordinal58 */
3216         uint32_t reserved29;  /* ordinal59 */
3217         uint32_t reserved30;  /* ordinal60 */
3218         uint32_t reserved31;  /* ordinal61 */
3219         uint32_t reserved32;  /* ordinal62 */
3220         uint32_t reserved33;  /* ordinal63 */
3221         uint32_t reserved34;  /* ordinal64 */
3222         uint32_t compute_user_data_0;  /* ordinal65 */
3223         uint32_t compute_user_data_1;  /* ordinal66 */
3224         uint32_t compute_user_data_2;  /* ordinal67 */
3225         uint32_t compute_user_data_3;  /* ordinal68 */
3226         uint32_t compute_user_data_4;  /* ordinal69 */
3227         uint32_t compute_user_data_5;  /* ordinal70 */
3228         uint32_t compute_user_data_6;  /* ordinal71 */
3229         uint32_t compute_user_data_7;  /* ordinal72 */
3230         uint32_t compute_user_data_8;  /* ordinal73 */
3231         uint32_t compute_user_data_9;  /* ordinal74 */
3232         uint32_t compute_user_data_10;  /* ordinal75 */
3233         uint32_t compute_user_data_11;  /* ordinal76 */
3234         uint32_t compute_user_data_12;  /* ordinal77 */
3235         uint32_t compute_user_data_13;  /* ordinal78 */
3236         uint32_t compute_user_data_14;  /* ordinal79 */
3237         uint32_t compute_user_data_15;  /* ordinal80 */
3238         uint32_t cp_compute_csinvoc_count_lo;  /* ordinal81 */
3239         uint32_t cp_compute_csinvoc_count_hi;  /* ordinal82 */
3240         uint32_t reserved35;  /* ordinal83 */
3241         uint32_t reserved36;  /* ordinal84 */
3242         uint32_t reserved37;  /* ordinal85 */
3243         uint32_t cp_mqd_query_time_lo;  /* ordinal86 */
3244         uint32_t cp_mqd_query_time_hi;  /* ordinal87 */
3245         uint32_t cp_mqd_connect_start_time_lo;  /* ordinal88 */
3246         uint32_t cp_mqd_connect_start_time_hi;  /* ordinal89 */
3247         uint32_t cp_mqd_connect_end_time_lo;  /* ordinal90 */
3248         uint32_t cp_mqd_connect_end_time_hi;  /* ordinal91 */
3249         uint32_t cp_mqd_connect_end_wf_count;  /* ordinal92 */
3250         uint32_t cp_mqd_connect_end_pq_rptr;  /* ordinal93 */
3251         uint32_t cp_mqd_connect_end_pq_wptr;  /* ordinal94 */
3252         uint32_t cp_mqd_connect_end_ib_rptr;  /* ordinal95 */
3253         uint32_t reserved38;  /* ordinal96 */
3254         uint32_t reserved39;  /* ordinal97 */
3255         uint32_t cp_mqd_save_start_time_lo;  /* ordinal98 */
3256         uint32_t cp_mqd_save_start_time_hi;  /* ordinal99 */
3257         uint32_t cp_mqd_save_end_time_lo;  /* ordinal100 */
3258         uint32_t cp_mqd_save_end_time_hi;  /* ordinal101 */
3259         uint32_t cp_mqd_restore_start_time_lo;  /* ordinal102 */
3260         uint32_t cp_mqd_restore_start_time_hi;  /* ordinal103 */
3261         uint32_t cp_mqd_restore_end_time_lo;  /* ordinal104 */
3262         uint32_t cp_mqd_restore_end_time_hi;  /* ordinal105 */
3263         uint32_t reserved40;  /* ordinal106 */
3264         uint32_t reserved41;  /* ordinal107 */
3265         uint32_t gds_cs_ctxsw_cnt0;  /* ordinal108 */
3266         uint32_t gds_cs_ctxsw_cnt1;  /* ordinal109 */
3267         uint32_t gds_cs_ctxsw_cnt2;  /* ordinal110 */
3268         uint32_t gds_cs_ctxsw_cnt3;  /* ordinal111 */
3269         uint32_t reserved42;  /* ordinal112 */
3270         uint32_t reserved43;  /* ordinal113 */
3271         uint32_t cp_pq_exe_status_lo;  /* ordinal114 */
3272         uint32_t cp_pq_exe_status_hi;  /* ordinal115 */
3273         uint32_t cp_packet_id_lo;  /* ordinal116 */
3274         uint32_t cp_packet_id_hi;  /* ordinal117 */
3275         uint32_t cp_packet_exe_status_lo;  /* ordinal118 */
3276         uint32_t cp_packet_exe_status_hi;  /* ordinal119 */
3277         uint32_t gds_save_base_addr_lo;  /* ordinal120 */
3278         uint32_t gds_save_base_addr_hi;  /* ordinal121 */
3279         uint32_t gds_save_mask_lo;  /* ordinal122 */
3280         uint32_t gds_save_mask_hi;  /* ordinal123 */
3281         uint32_t ctx_save_base_addr_lo;  /* ordinal124 */
3282         uint32_t ctx_save_base_addr_hi;  /* ordinal125 */
3283         uint32_t reserved44;  /* ordinal126 */
3284         uint32_t reserved45;  /* ordinal127 */
3285         uint32_t cp_mqd_base_addr_lo;  /* ordinal128 */
3286         uint32_t cp_mqd_base_addr_hi;  /* ordinal129 */
3287         uint32_t cp_hqd_active;  /* ordinal130 */
3288         uint32_t cp_hqd_vmid;  /* ordinal131 */
3289         uint32_t cp_hqd_persistent_state;  /* ordinal132 */
3290         uint32_t cp_hqd_pipe_priority;  /* ordinal133 */
3291         uint32_t cp_hqd_queue_priority;  /* ordinal134 */
3292         uint32_t cp_hqd_quantum;  /* ordinal135 */
3293         uint32_t cp_hqd_pq_base_lo;  /* ordinal136 */
3294         uint32_t cp_hqd_pq_base_hi;  /* ordinal137 */
3295         uint32_t cp_hqd_pq_rptr;  /* ordinal138 */
3296         uint32_t cp_hqd_pq_rptr_report_addr_lo;  /* ordinal139 */
3297         uint32_t cp_hqd_pq_rptr_report_addr_hi;  /* ordinal140 */
3298         uint32_t cp_hqd_pq_wptr_poll_addr;  /* ordinal141 */
3299         uint32_t cp_hqd_pq_wptr_poll_addr_hi;  /* ordinal142 */
3300         uint32_t cp_hqd_pq_doorbell_control;  /* ordinal143 */
3301         uint32_t cp_hqd_pq_wptr;  /* ordinal144 */
3302         uint32_t cp_hqd_pq_control;  /* ordinal145 */
3303         uint32_t cp_hqd_ib_base_addr_lo;  /* ordinal146 */
3304         uint32_t cp_hqd_ib_base_addr_hi;  /* ordinal147 */
3305         uint32_t cp_hqd_ib_rptr;  /* ordinal148 */
3306         uint32_t cp_hqd_ib_control;  /* ordinal149 */
3307         uint32_t cp_hqd_iq_timer;  /* ordinal150 */
3308         uint32_t cp_hqd_iq_rptr;  /* ordinal151 */
3309         uint32_t cp_hqd_dequeue_request;  /* ordinal152 */
3310         uint32_t cp_hqd_dma_offload;  /* ordinal153 */
3311         uint32_t cp_hqd_sema_cmd;  /* ordinal154 */
3312         uint32_t cp_hqd_msg_type;  /* ordinal155 */
3313         uint32_t cp_hqd_atomic0_preop_lo;  /* ordinal156 */
3314         uint32_t cp_hqd_atomic0_preop_hi;  /* ordinal157 */
3315         uint32_t cp_hqd_atomic1_preop_lo;  /* ordinal158 */
3316         uint32_t cp_hqd_atomic1_preop_hi;  /* ordinal159 */
3317         uint32_t cp_hqd_hq_status0;  /* ordinal160 */
3318         uint32_t cp_hqd_hq_control0;  /* ordinal161 */
3319         uint32_t cp_mqd_control;  /* ordinal162 */
3320         uint32_t cp_hqd_hq_status1;  /* ordinal163 */
3321         uint32_t cp_hqd_hq_control1;  /* ordinal164 */
3322         uint32_t cp_hqd_eop_base_addr_lo;  /* ordinal165 */
3323         uint32_t cp_hqd_eop_base_addr_hi;  /* ordinal166 */
3324         uint32_t cp_hqd_eop_control;  /* ordinal167 */
3325         uint32_t cp_hqd_eop_rptr;  /* ordinal168 */
3326         uint32_t cp_hqd_eop_wptr;  /* ordinal169 */
3327         uint32_t cp_hqd_eop_done_events;  /* ordinal170 */
3328         uint32_t cp_hqd_ctx_save_base_addr_lo;  /* ordinal171 */
3329         uint32_t cp_hqd_ctx_save_base_addr_hi;  /* ordinal172 */
3330         uint32_t cp_hqd_ctx_save_control;  /* ordinal173 */
3331         uint32_t cp_hqd_cntl_stack_offset;  /* ordinal174 */
3332         uint32_t cp_hqd_cntl_stack_size;  /* ordinal175 */
3333         uint32_t cp_hqd_wg_state_offset;  /* ordinal176 */
3334         uint32_t cp_hqd_ctx_save_size;  /* ordinal177 */
3335         uint32_t cp_hqd_gds_resource_state;  /* ordinal178 */
3336         uint32_t cp_hqd_error;  /* ordinal179 */
3337         uint32_t cp_hqd_eop_wptr_mem;  /* ordinal180 */
3338         uint32_t cp_hqd_eop_dones;  /* ordinal181 */
3339         uint32_t reserved46;  /* ordinal182 */
3340         uint32_t reserved47;  /* ordinal183 */
3341         uint32_t reserved48;  /* ordinal184 */
3342         uint32_t reserved49;  /* ordinal185 */
3343         uint32_t reserved50;  /* ordinal186 */
3344         uint32_t reserved51;  /* ordinal187 */
3345         uint32_t reserved52;  /* ordinal188 */
3346         uint32_t reserved53;  /* ordinal189 */
3347         uint32_t reserved54;  /* ordinal190 */
3348         uint32_t reserved55;  /* ordinal191 */
3349         uint32_t iqtimer_pkt_header;  /* ordinal192 */
3350         uint32_t iqtimer_pkt_dw0;  /* ordinal193 */
3351         uint32_t iqtimer_pkt_dw1;  /* ordinal194 */
3352         uint32_t iqtimer_pkt_dw2;  /* ordinal195 */
3353         uint32_t iqtimer_pkt_dw3;  /* ordinal196 */
3354         uint32_t iqtimer_pkt_dw4;  /* ordinal197 */
3355         uint32_t iqtimer_pkt_dw5;  /* ordinal198 */
3356         uint32_t iqtimer_pkt_dw6;  /* ordinal199 */
3357         uint32_t iqtimer_pkt_dw7;  /* ordinal200 */
3358         uint32_t iqtimer_pkt_dw8;  /* ordinal201 */
3359         uint32_t iqtimer_pkt_dw9;  /* ordinal202 */
3360         uint32_t iqtimer_pkt_dw10;  /* ordinal203 */
3361         uint32_t iqtimer_pkt_dw11;  /* ordinal204 */
3362         uint32_t iqtimer_pkt_dw12;  /* ordinal205 */
3363         uint32_t iqtimer_pkt_dw13;  /* ordinal206 */
3364         uint32_t iqtimer_pkt_dw14;  /* ordinal207 */
3365         uint32_t iqtimer_pkt_dw15;  /* ordinal208 */
3366         uint32_t iqtimer_pkt_dw16;  /* ordinal209 */
3367         uint32_t iqtimer_pkt_dw17;  /* ordinal210 */
3368         uint32_t iqtimer_pkt_dw18;  /* ordinal211 */
3369         uint32_t iqtimer_pkt_dw19;  /* ordinal212 */
3370         uint32_t iqtimer_pkt_dw20;  /* ordinal213 */
3371         uint32_t iqtimer_pkt_dw21;  /* ordinal214 */
3372         uint32_t iqtimer_pkt_dw22;  /* ordinal215 */
3373         uint32_t iqtimer_pkt_dw23;  /* ordinal216 */
3374         uint32_t iqtimer_pkt_dw24;  /* ordinal217 */
3375         uint32_t iqtimer_pkt_dw25;  /* ordinal218 */
3376         uint32_t iqtimer_pkt_dw26;  /* ordinal219 */
3377         uint32_t iqtimer_pkt_dw27;  /* ordinal220 */
3378         uint32_t iqtimer_pkt_dw28;  /* ordinal221 */
3379         uint32_t iqtimer_pkt_dw29;  /* ordinal222 */
3380         uint32_t iqtimer_pkt_dw30;  /* ordinal223 */
3381         uint32_t iqtimer_pkt_dw31;  /* ordinal224 */
3382         uint32_t reserved56;  /* ordinal225 */
3383         uint32_t reserved57;  /* ordinal226 */
3384         uint32_t reserved58;  /* ordinal227 */
3385         uint32_t set_resources_header;  /* ordinal228 */
3386         uint32_t set_resources_dw1;  /* ordinal229 */
3387         uint32_t set_resources_dw2;  /* ordinal230 */
3388         uint32_t set_resources_dw3;  /* ordinal231 */
3389         uint32_t set_resources_dw4;  /* ordinal232 */
3390         uint32_t set_resources_dw5;  /* ordinal233 */
3391         uint32_t set_resources_dw6;  /* ordinal234 */
3392         uint32_t set_resources_dw7;  /* ordinal235 */
3393         uint32_t reserved59;  /* ordinal236 */
3394         uint32_t reserved60;  /* ordinal237 */
3395         uint32_t reserved61;  /* ordinal238 */
3396         uint32_t reserved62;  /* ordinal239 */
3397         uint32_t reserved63;  /* ordinal240 */
3398         uint32_t reserved64;  /* ordinal241 */
3399         uint32_t reserved65;  /* ordinal242 */
3400         uint32_t reserved66;  /* ordinal243 */
3401         uint32_t reserved67;  /* ordinal244 */
3402         uint32_t reserved68;  /* ordinal245 */
3403         uint32_t reserved69;  /* ordinal246 */
3404         uint32_t reserved70;  /* ordinal247 */
3405         uint32_t reserved71;  /* ordinal248 */
3406         uint32_t reserved72;  /* ordinal249 */
3407         uint32_t reserved73;  /* ordinal250 */
3408         uint32_t reserved74;  /* ordinal251 */
3409         uint32_t reserved75;  /* ordinal252 */
3410         uint32_t reserved76;  /* ordinal253 */
3411         uint32_t reserved77;  /* ordinal254 */
3412         uint32_t reserved78;  /* ordinal255 */
3413
3414         uint32_t reserved_t[256]; /* Reserve 256 dword buffer used by ucode */
3415 };
3416
3417 static void gfx_v8_0_cp_compute_fini(struct amdgpu_device *adev)
3418 {
3419         int i, r;
3420
3421         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3422                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
3423
3424                 if (ring->mqd_obj) {
3425                         r = amdgpu_bo_reserve(ring->mqd_obj, false);
3426                         if (unlikely(r != 0))
3427                                 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
3428
3429                         amdgpu_bo_unpin(ring->mqd_obj);
3430                         amdgpu_bo_unreserve(ring->mqd_obj);
3431
3432                         amdgpu_bo_unref(&ring->mqd_obj);
3433                         ring->mqd_obj = NULL;
3434                 }
3435         }
3436 }
3437
3438 static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
3439 {
3440         int r, i, j;
3441         u32 tmp;
3442         bool use_doorbell = true;
3443         u64 hqd_gpu_addr;
3444         u64 mqd_gpu_addr;
3445         u64 eop_gpu_addr;
3446         u64 wb_gpu_addr;
3447         u32 *buf;
3448         struct vi_mqd *mqd;
3449
3450         /* init the pipes */
3451         mutex_lock(&adev->srbm_mutex);
3452         for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {
3453                 int me = (i < 4) ? 1 : 2;
3454                 int pipe = (i < 4) ? i : (i - 4);
3455
3456                 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE);
3457                 eop_gpu_addr >>= 8;
3458
3459                 vi_srbm_select(adev, me, pipe, 0, 0);
3460
3461                 /* write the EOP addr */
3462                 WREG32(mmCP_HQD_EOP_BASE_ADDR, eop_gpu_addr);
3463                 WREG32(mmCP_HQD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr));
3464
3465                 /* set the VMID assigned */
3466                 WREG32(mmCP_HQD_VMID, 0);
3467
3468                 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3469                 tmp = RREG32(mmCP_HQD_EOP_CONTROL);
3470                 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
3471                                     (order_base_2(MEC_HPD_SIZE / 4) - 1));
3472                 WREG32(mmCP_HQD_EOP_CONTROL, tmp);
3473         }
3474         vi_srbm_select(adev, 0, 0, 0, 0);
3475         mutex_unlock(&adev->srbm_mutex);
3476
3477         /* init the queues.  Just two for now. */
3478         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3479                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
3480
3481                 if (ring->mqd_obj == NULL) {
3482                         r = amdgpu_bo_create(adev,
3483                                              sizeof(struct vi_mqd),
3484                                              PAGE_SIZE, true,
3485                                              AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
3486                                              NULL, &ring->mqd_obj);
3487                         if (r) {
3488                                 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
3489                                 return r;
3490                         }
3491                 }
3492
3493                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3494                 if (unlikely(r != 0)) {
3495                         gfx_v8_0_cp_compute_fini(adev);
3496                         return r;
3497                 }
3498                 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
3499                                   &mqd_gpu_addr);
3500                 if (r) {
3501                         dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
3502                         gfx_v8_0_cp_compute_fini(adev);
3503                         return r;
3504                 }
3505                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
3506                 if (r) {
3507                         dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
3508                         gfx_v8_0_cp_compute_fini(adev);
3509                         return r;
3510                 }
3511
3512                 /* init the mqd struct */
3513                 memset(buf, 0, sizeof(struct vi_mqd));
3514
3515                 mqd = (struct vi_mqd *)buf;
3516                 mqd->header = 0xC0310800;
3517                 mqd->compute_pipelinestat_enable = 0x00000001;
3518                 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
3519                 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
3520                 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
3521                 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
3522                 mqd->compute_misc_reserved = 0x00000003;
3523
3524                 mutex_lock(&adev->srbm_mutex);
3525                 vi_srbm_select(adev, ring->me,
3526                                ring->pipe,
3527                                ring->queue, 0);
3528
3529                 /* disable wptr polling */
3530                 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
3531                 tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3532                 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
3533
3534                 mqd->cp_hqd_eop_base_addr_lo =
3535                         RREG32(mmCP_HQD_EOP_BASE_ADDR);
3536                 mqd->cp_hqd_eop_base_addr_hi =
3537                         RREG32(mmCP_HQD_EOP_BASE_ADDR_HI);
3538
3539                 /* enable doorbell? */
3540                 tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
3541                 if (use_doorbell) {
3542                         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
3543                 } else {
3544                         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 0);
3545                 }
3546                 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, tmp);
3547                 mqd->cp_hqd_pq_doorbell_control = tmp;
3548
3549                 /* disable the queue if it's active */
3550                 mqd->cp_hqd_dequeue_request = 0;
3551                 mqd->cp_hqd_pq_rptr = 0;
3552                 mqd->cp_hqd_pq_wptr= 0;
3553                 if (RREG32(mmCP_HQD_ACTIVE) & 1) {
3554                         WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);
3555                         for (j = 0; j < adev->usec_timeout; j++) {
3556                                 if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
3557                                         break;
3558                                 udelay(1);
3559                         }
3560                         WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->cp_hqd_dequeue_request);
3561                         WREG32(mmCP_HQD_PQ_RPTR, mqd->cp_hqd_pq_rptr);
3562                         WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);
3563                 }
3564
3565                 /* set the pointer to the MQD */
3566                 mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc;
3567                 mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
3568                 WREG32(mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
3569                 WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
3570
3571                 /* set MQD vmid to 0 */
3572                 tmp = RREG32(mmCP_MQD_CONTROL);
3573                 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
3574                 WREG32(mmCP_MQD_CONTROL, tmp);
3575                 mqd->cp_mqd_control = tmp;
3576
3577                 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3578                 hqd_gpu_addr = ring->gpu_addr >> 8;
3579                 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
3580                 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3581                 WREG32(mmCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
3582                 WREG32(mmCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
3583
3584                 /* set up the HQD, this is similar to CP_RB0_CNTL */
3585                 tmp = RREG32(mmCP_HQD_PQ_CONTROL);
3586                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
3587                                     (order_base_2(ring->ring_size / 4) - 1));
3588                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
3589                                ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
3590 #ifdef __BIG_ENDIAN
3591                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
3592 #endif
3593                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
3594                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
3595                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3596                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
3597                 WREG32(mmCP_HQD_PQ_CONTROL, tmp);
3598                 mqd->cp_hqd_pq_control = tmp;
3599
3600                 /* set the wb address wether it's enabled or not */
3601                 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3602                 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3603                 mqd->cp_hqd_pq_rptr_report_addr_hi =
3604                         upper_32_bits(wb_gpu_addr) & 0xffff;
3605                 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR,
3606                        mqd->cp_hqd_pq_rptr_report_addr_lo);
3607                 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3608                        mqd->cp_hqd_pq_rptr_report_addr_hi);
3609
3610                 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3611                 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3612                 mqd->cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
3613                 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3614                 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->cp_hqd_pq_wptr_poll_addr);
3615                 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3616                        mqd->cp_hqd_pq_wptr_poll_addr_hi);
3617
3618                 /* enable the doorbell if requested */
3619                 if (use_doorbell) {
3620                         if ((adev->asic_type == CHIP_CARRIZO) ||
3621                             (adev->asic_type == CHIP_FIJI) ||
3622                             (adev->asic_type == CHIP_STONEY)) {
3623                                 WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER,
3624                                        AMDGPU_DOORBELL_KIQ << 2);
3625                                 WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER,
3626                                        AMDGPU_DOORBELL_MEC_RING7 << 2);
3627                         }
3628                         tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
3629                         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3630                                             DOORBELL_OFFSET, ring->doorbell_index);
3631                         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
3632                         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_SOURCE, 0);
3633                         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_HIT, 0);
3634                         mqd->cp_hqd_pq_doorbell_control = tmp;
3635
3636                 } else {
3637                         mqd->cp_hqd_pq_doorbell_control = 0;
3638                 }
3639                 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
3640                        mqd->cp_hqd_pq_doorbell_control);
3641
3642                 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3643                 ring->wptr = 0;
3644                 mqd->cp_hqd_pq_wptr = ring->wptr;
3645                 WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);
3646                 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
3647
3648                 /* set the vmid for the queue */
3649                 mqd->cp_hqd_vmid = 0;
3650                 WREG32(mmCP_HQD_VMID, mqd->cp_hqd_vmid);
3651
3652                 tmp = RREG32(mmCP_HQD_PERSISTENT_STATE);
3653                 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
3654                 WREG32(mmCP_HQD_PERSISTENT_STATE, tmp);
3655                 mqd->cp_hqd_persistent_state = tmp;
3656
3657                 /* activate the queue */
3658                 mqd->cp_hqd_active = 1;
3659                 WREG32(mmCP_HQD_ACTIVE, mqd->cp_hqd_active);
3660
3661                 vi_srbm_select(adev, 0, 0, 0, 0);
3662                 mutex_unlock(&adev->srbm_mutex);
3663
3664                 amdgpu_bo_kunmap(ring->mqd_obj);
3665                 amdgpu_bo_unreserve(ring->mqd_obj);
3666         }
3667
3668         if (use_doorbell) {
3669                 tmp = RREG32(mmCP_PQ_STATUS);
3670                 tmp = REG_SET_FIELD(tmp, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
3671                 WREG32(mmCP_PQ_STATUS, tmp);
3672         }
3673
3674         r = gfx_v8_0_cp_compute_start(adev);
3675         if (r)
3676                 return r;
3677
3678         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3679                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
3680
3681                 ring->ready = true;
3682                 r = amdgpu_ring_test_ring(ring);
3683                 if (r)
3684                         ring->ready = false;
3685         }
3686
3687         return 0;
3688 }
3689
3690 static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
3691 {
3692         int r;
3693
3694         if (!(adev->flags & AMD_IS_APU))
3695                 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
3696
3697         if (!adev->firmware.smu_load) {
3698                 /* legacy firmware loading */
3699                 r = gfx_v8_0_cp_gfx_load_microcode(adev);
3700                 if (r)
3701                         return r;
3702
3703                 r = gfx_v8_0_cp_compute_load_microcode(adev);
3704                 if (r)
3705                         return r;
3706         } else {
3707                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3708                                                 AMDGPU_UCODE_ID_CP_CE);
3709                 if (r)
3710                         return -EINVAL;
3711
3712                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3713                                                 AMDGPU_UCODE_ID_CP_PFP);
3714                 if (r)
3715                         return -EINVAL;
3716
3717                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3718                                                 AMDGPU_UCODE_ID_CP_ME);
3719                 if (r)
3720                         return -EINVAL;
3721
3722                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3723                                                 AMDGPU_UCODE_ID_CP_MEC1);
3724                 if (r)
3725                         return -EINVAL;
3726         }
3727
3728         r = gfx_v8_0_cp_gfx_resume(adev);
3729         if (r)
3730                 return r;
3731
3732         r = gfx_v8_0_cp_compute_resume(adev);
3733         if (r)
3734                 return r;
3735
3736         gfx_v8_0_enable_gui_idle_interrupt(adev, true);
3737
3738         return 0;
3739 }
3740
3741 static void gfx_v8_0_cp_enable(struct amdgpu_device *adev, bool enable)
3742 {
3743         gfx_v8_0_cp_gfx_enable(adev, enable);
3744         gfx_v8_0_cp_compute_enable(adev, enable);
3745 }
3746
3747 static int gfx_v8_0_hw_init(void *handle)
3748 {
3749         int r;
3750         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3751
3752         gfx_v8_0_init_golden_registers(adev);
3753
3754         gfx_v8_0_gpu_init(adev);
3755
3756         r = gfx_v8_0_rlc_resume(adev);
3757         if (r)
3758                 return r;
3759
3760         r = gfx_v8_0_cp_resume(adev);
3761         if (r)
3762                 return r;
3763
3764         return r;
3765 }
3766
3767 static int gfx_v8_0_hw_fini(void *handle)
3768 {
3769         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3770
3771         gfx_v8_0_cp_enable(adev, false);
3772         gfx_v8_0_rlc_stop(adev);
3773         gfx_v8_0_cp_compute_fini(adev);
3774
3775         return 0;
3776 }
3777
3778 static int gfx_v8_0_suspend(void *handle)
3779 {
3780         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3781
3782         return gfx_v8_0_hw_fini(adev);
3783 }
3784
3785 static int gfx_v8_0_resume(void *handle)
3786 {
3787         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3788
3789         return gfx_v8_0_hw_init(adev);
3790 }
3791
3792 static bool gfx_v8_0_is_idle(void *handle)
3793 {
3794         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3795
3796         if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE))
3797                 return false;
3798         else
3799                 return true;
3800 }
3801
3802 static int gfx_v8_0_wait_for_idle(void *handle)
3803 {
3804         unsigned i;
3805         u32 tmp;
3806         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3807
3808         for (i = 0; i < adev->usec_timeout; i++) {
3809                 /* read MC_STATUS */
3810                 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
3811
3812                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
3813                         return 0;
3814                 udelay(1);
3815         }
3816         return -ETIMEDOUT;
3817 }
3818
3819 static void gfx_v8_0_print_status(void *handle)
3820 {
3821         int i;
3822         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3823
3824         dev_info(adev->dev, "GFX 8.x registers\n");
3825         dev_info(adev->dev, "  GRBM_STATUS=0x%08X\n",
3826                  RREG32(mmGRBM_STATUS));
3827         dev_info(adev->dev, "  GRBM_STATUS2=0x%08X\n",
3828                  RREG32(mmGRBM_STATUS2));
3829         dev_info(adev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
3830                  RREG32(mmGRBM_STATUS_SE0));
3831         dev_info(adev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
3832                  RREG32(mmGRBM_STATUS_SE1));
3833         dev_info(adev->dev, "  GRBM_STATUS_SE2=0x%08X\n",
3834                  RREG32(mmGRBM_STATUS_SE2));
3835         dev_info(adev->dev, "  GRBM_STATUS_SE3=0x%08X\n",
3836                  RREG32(mmGRBM_STATUS_SE3));
3837         dev_info(adev->dev, "  CP_STAT = 0x%08x\n", RREG32(mmCP_STAT));
3838         dev_info(adev->dev, "  CP_STALLED_STAT1 = 0x%08x\n",
3839                  RREG32(mmCP_STALLED_STAT1));
3840         dev_info(adev->dev, "  CP_STALLED_STAT2 = 0x%08x\n",
3841                  RREG32(mmCP_STALLED_STAT2));
3842         dev_info(adev->dev, "  CP_STALLED_STAT3 = 0x%08x\n",
3843                  RREG32(mmCP_STALLED_STAT3));
3844         dev_info(adev->dev, "  CP_CPF_BUSY_STAT = 0x%08x\n",
3845                  RREG32(mmCP_CPF_BUSY_STAT));
3846         dev_info(adev->dev, "  CP_CPF_STALLED_STAT1 = 0x%08x\n",
3847                  RREG32(mmCP_CPF_STALLED_STAT1));
3848         dev_info(adev->dev, "  CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS));
3849         dev_info(adev->dev, "  CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT));
3850         dev_info(adev->dev, "  CP_CPC_STALLED_STAT1 = 0x%08x\n",
3851                  RREG32(mmCP_CPC_STALLED_STAT1));
3852         dev_info(adev->dev, "  CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS));
3853
3854         for (i = 0; i < 32; i++) {
3855                 dev_info(adev->dev, "  GB_TILE_MODE%d=0x%08X\n",
3856                          i, RREG32(mmGB_TILE_MODE0 + (i * 4)));
3857         }
3858         for (i = 0; i < 16; i++) {
3859                 dev_info(adev->dev, "  GB_MACROTILE_MODE%d=0x%08X\n",
3860                          i, RREG32(mmGB_MACROTILE_MODE0 + (i * 4)));
3861         }
3862         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3863                 dev_info(adev->dev, "  se: %d\n", i);
3864                 gfx_v8_0_select_se_sh(adev, i, 0xffffffff);
3865                 dev_info(adev->dev, "  PA_SC_RASTER_CONFIG=0x%08X\n",
3866                          RREG32(mmPA_SC_RASTER_CONFIG));
3867                 dev_info(adev->dev, "  PA_SC_RASTER_CONFIG_1=0x%08X\n",
3868                          RREG32(mmPA_SC_RASTER_CONFIG_1));
3869         }
3870         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3871
3872         dev_info(adev->dev, "  GB_ADDR_CONFIG=0x%08X\n",
3873                  RREG32(mmGB_ADDR_CONFIG));
3874         dev_info(adev->dev, "  HDP_ADDR_CONFIG=0x%08X\n",
3875                  RREG32(mmHDP_ADDR_CONFIG));
3876         dev_info(adev->dev, "  DMIF_ADDR_CALC=0x%08X\n",
3877                  RREG32(mmDMIF_ADDR_CALC));
3878         dev_info(adev->dev, "  SDMA0_TILING_CONFIG=0x%08X\n",
3879                  RREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET));
3880         dev_info(adev->dev, "  SDMA1_TILING_CONFIG=0x%08X\n",
3881                  RREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET));
3882         dev_info(adev->dev, "  UVD_UDEC_ADDR_CONFIG=0x%08X\n",
3883                  RREG32(mmUVD_UDEC_ADDR_CONFIG));
3884         dev_info(adev->dev, "  UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
3885                  RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
3886         dev_info(adev->dev, "  UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
3887                  RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
3888
3889         dev_info(adev->dev, "  CP_MEQ_THRESHOLDS=0x%08X\n",
3890                  RREG32(mmCP_MEQ_THRESHOLDS));
3891         dev_info(adev->dev, "  SX_DEBUG_1=0x%08X\n",
3892                  RREG32(mmSX_DEBUG_1));
3893         dev_info(adev->dev, "  TA_CNTL_AUX=0x%08X\n",
3894                  RREG32(mmTA_CNTL_AUX));
3895         dev_info(adev->dev, "  SPI_CONFIG_CNTL=0x%08X\n",
3896                  RREG32(mmSPI_CONFIG_CNTL));
3897         dev_info(adev->dev, "  SQ_CONFIG=0x%08X\n",
3898                  RREG32(mmSQ_CONFIG));
3899         dev_info(adev->dev, "  DB_DEBUG=0x%08X\n",
3900                  RREG32(mmDB_DEBUG));
3901         dev_info(adev->dev, "  DB_DEBUG2=0x%08X\n",
3902                  RREG32(mmDB_DEBUG2));
3903         dev_info(adev->dev, "  DB_DEBUG3=0x%08X\n",
3904                  RREG32(mmDB_DEBUG3));
3905         dev_info(adev->dev, "  CB_HW_CONTROL=0x%08X\n",
3906                  RREG32(mmCB_HW_CONTROL));
3907         dev_info(adev->dev, "  SPI_CONFIG_CNTL_1=0x%08X\n",
3908                  RREG32(mmSPI_CONFIG_CNTL_1));
3909         dev_info(adev->dev, "  PA_SC_FIFO_SIZE=0x%08X\n",
3910                  RREG32(mmPA_SC_FIFO_SIZE));
3911         dev_info(adev->dev, "  VGT_NUM_INSTANCES=0x%08X\n",
3912                  RREG32(mmVGT_NUM_INSTANCES));
3913         dev_info(adev->dev, "  CP_PERFMON_CNTL=0x%08X\n",
3914                  RREG32(mmCP_PERFMON_CNTL));
3915         dev_info(adev->dev, "  PA_SC_FORCE_EOV_MAX_CNTS=0x%08X\n",
3916                  RREG32(mmPA_SC_FORCE_EOV_MAX_CNTS));
3917         dev_info(adev->dev, "  VGT_CACHE_INVALIDATION=0x%08X\n",
3918                  RREG32(mmVGT_CACHE_INVALIDATION));
3919         dev_info(adev->dev, "  VGT_GS_VERTEX_REUSE=0x%08X\n",
3920                  RREG32(mmVGT_GS_VERTEX_REUSE));
3921         dev_info(adev->dev, "  PA_SC_LINE_STIPPLE_STATE=0x%08X\n",
3922                  RREG32(mmPA_SC_LINE_STIPPLE_STATE));
3923         dev_info(adev->dev, "  PA_CL_ENHANCE=0x%08X\n",
3924                  RREG32(mmPA_CL_ENHANCE));
3925         dev_info(adev->dev, "  PA_SC_ENHANCE=0x%08X\n",
3926                  RREG32(mmPA_SC_ENHANCE));
3927
3928         dev_info(adev->dev, "  CP_ME_CNTL=0x%08X\n",
3929                  RREG32(mmCP_ME_CNTL));
3930         dev_info(adev->dev, "  CP_MAX_CONTEXT=0x%08X\n",
3931                  RREG32(mmCP_MAX_CONTEXT));
3932         dev_info(adev->dev, "  CP_ENDIAN_SWAP=0x%08X\n",
3933                  RREG32(mmCP_ENDIAN_SWAP));
3934         dev_info(adev->dev, "  CP_DEVICE_ID=0x%08X\n",
3935                  RREG32(mmCP_DEVICE_ID));
3936
3937         dev_info(adev->dev, "  CP_SEM_WAIT_TIMER=0x%08X\n",
3938                  RREG32(mmCP_SEM_WAIT_TIMER));
3939
3940         dev_info(adev->dev, "  CP_RB_WPTR_DELAY=0x%08X\n",
3941                  RREG32(mmCP_RB_WPTR_DELAY));
3942         dev_info(adev->dev, "  CP_RB_VMID=0x%08X\n",
3943                  RREG32(mmCP_RB_VMID));
3944         dev_info(adev->dev, "  CP_RB0_CNTL=0x%08X\n",
3945                  RREG32(mmCP_RB0_CNTL));
3946         dev_info(adev->dev, "  CP_RB0_WPTR=0x%08X\n",
3947                  RREG32(mmCP_RB0_WPTR));
3948         dev_info(adev->dev, "  CP_RB0_RPTR_ADDR=0x%08X\n",
3949                  RREG32(mmCP_RB0_RPTR_ADDR));
3950         dev_info(adev->dev, "  CP_RB0_RPTR_ADDR_HI=0x%08X\n",
3951                  RREG32(mmCP_RB0_RPTR_ADDR_HI));
3952         dev_info(adev->dev, "  CP_RB0_CNTL=0x%08X\n",
3953                  RREG32(mmCP_RB0_CNTL));
3954         dev_info(adev->dev, "  CP_RB0_BASE=0x%08X\n",
3955                  RREG32(mmCP_RB0_BASE));
3956         dev_info(adev->dev, "  CP_RB0_BASE_HI=0x%08X\n",
3957                  RREG32(mmCP_RB0_BASE_HI));
3958         dev_info(adev->dev, "  CP_MEC_CNTL=0x%08X\n",
3959                  RREG32(mmCP_MEC_CNTL));
3960         dev_info(adev->dev, "  CP_CPF_DEBUG=0x%08X\n",
3961                  RREG32(mmCP_CPF_DEBUG));
3962
3963         dev_info(adev->dev, "  SCRATCH_ADDR=0x%08X\n",
3964                  RREG32(mmSCRATCH_ADDR));
3965         dev_info(adev->dev, "  SCRATCH_UMSK=0x%08X\n",
3966                  RREG32(mmSCRATCH_UMSK));
3967
3968         dev_info(adev->dev, "  CP_INT_CNTL_RING0=0x%08X\n",
3969                  RREG32(mmCP_INT_CNTL_RING0));
3970         dev_info(adev->dev, "  RLC_LB_CNTL=0x%08X\n",
3971                  RREG32(mmRLC_LB_CNTL));
3972         dev_info(adev->dev, "  RLC_CNTL=0x%08X\n",
3973                  RREG32(mmRLC_CNTL));
3974         dev_info(adev->dev, "  RLC_CGCG_CGLS_CTRL=0x%08X\n",
3975                  RREG32(mmRLC_CGCG_CGLS_CTRL));
3976         dev_info(adev->dev, "  RLC_LB_CNTR_INIT=0x%08X\n",
3977                  RREG32(mmRLC_LB_CNTR_INIT));
3978         dev_info(adev->dev, "  RLC_LB_CNTR_MAX=0x%08X\n",
3979                  RREG32(mmRLC_LB_CNTR_MAX));
3980         dev_info(adev->dev, "  RLC_LB_INIT_CU_MASK=0x%08X\n",
3981                  RREG32(mmRLC_LB_INIT_CU_MASK));
3982         dev_info(adev->dev, "  RLC_LB_PARAMS=0x%08X\n",
3983                  RREG32(mmRLC_LB_PARAMS));
3984         dev_info(adev->dev, "  RLC_LB_CNTL=0x%08X\n",
3985                  RREG32(mmRLC_LB_CNTL));
3986         dev_info(adev->dev, "  RLC_MC_CNTL=0x%08X\n",
3987                  RREG32(mmRLC_MC_CNTL));
3988         dev_info(adev->dev, "  RLC_UCODE_CNTL=0x%08X\n",
3989                  RREG32(mmRLC_UCODE_CNTL));
3990
3991         mutex_lock(&adev->srbm_mutex);
3992         for (i = 0; i < 16; i++) {
3993                 vi_srbm_select(adev, 0, 0, 0, i);
3994                 dev_info(adev->dev, "  VM %d:\n", i);
3995                 dev_info(adev->dev, "  SH_MEM_CONFIG=0x%08X\n",
3996                          RREG32(mmSH_MEM_CONFIG));
3997                 dev_info(adev->dev, "  SH_MEM_APE1_BASE=0x%08X\n",
3998                          RREG32(mmSH_MEM_APE1_BASE));
3999                 dev_info(adev->dev, "  SH_MEM_APE1_LIMIT=0x%08X\n",
4000                          RREG32(mmSH_MEM_APE1_LIMIT));
4001                 dev_info(adev->dev, "  SH_MEM_BASES=0x%08X\n",
4002                          RREG32(mmSH_MEM_BASES));
4003         }
4004         vi_srbm_select(adev, 0, 0, 0, 0);
4005         mutex_unlock(&adev->srbm_mutex);
4006 }
4007
4008 static int gfx_v8_0_soft_reset(void *handle)
4009 {
4010         u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
4011         u32 tmp;
4012         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4013
4014         /* GRBM_STATUS */
4015         tmp = RREG32(mmGRBM_STATUS);
4016         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
4017                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
4018                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
4019                    GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
4020                    GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
4021                    GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
4022                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4023                                                 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
4024                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4025                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
4026         }
4027
4028         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
4029                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4030                                                 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
4031                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
4032                                                 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
4033         }
4034
4035         /* GRBM_STATUS2 */
4036         tmp = RREG32(mmGRBM_STATUS2);
4037         if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
4038                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4039                                                 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
4040
4041         /* SRBM_STATUS */
4042         tmp = RREG32(mmSRBM_STATUS);
4043         if (REG_GET_FIELD(tmp, SRBM_STATUS, GRBM_RQ_PENDING))
4044                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
4045                                                 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
4046
4047         if (grbm_soft_reset || srbm_soft_reset) {
4048                 gfx_v8_0_print_status((void *)adev);
4049                 /* stop the rlc */
4050                 gfx_v8_0_rlc_stop(adev);
4051
4052                 /* Disable GFX parsing/prefetching */
4053                 gfx_v8_0_cp_gfx_enable(adev, false);
4054
4055                 /* Disable MEC parsing/prefetching */
4056                 /* XXX todo */
4057
4058                 if (grbm_soft_reset) {
4059                         tmp = RREG32(mmGRBM_SOFT_RESET);
4060                         tmp |= grbm_soft_reset;
4061                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
4062                         WREG32(mmGRBM_SOFT_RESET, tmp);
4063                         tmp = RREG32(mmGRBM_SOFT_RESET);
4064
4065                         udelay(50);
4066
4067                         tmp &= ~grbm_soft_reset;
4068                         WREG32(mmGRBM_SOFT_RESET, tmp);
4069                         tmp = RREG32(mmGRBM_SOFT_RESET);
4070                 }
4071
4072                 if (srbm_soft_reset) {
4073                         tmp = RREG32(mmSRBM_SOFT_RESET);
4074                         tmp |= srbm_soft_reset;
4075                         dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
4076                         WREG32(mmSRBM_SOFT_RESET, tmp);
4077                         tmp = RREG32(mmSRBM_SOFT_RESET);
4078
4079                         udelay(50);
4080
4081                         tmp &= ~srbm_soft_reset;
4082                         WREG32(mmSRBM_SOFT_RESET, tmp);
4083                         tmp = RREG32(mmSRBM_SOFT_RESET);
4084                 }
4085                 /* Wait a little for things to settle down */
4086                 udelay(50);
4087                 gfx_v8_0_print_status((void *)adev);
4088         }
4089         return 0;
4090 }
4091
4092 /**
4093  * gfx_v8_0_get_gpu_clock_counter - return GPU clock counter snapshot
4094  *
4095  * @adev: amdgpu_device pointer
4096  *
4097  * Fetches a GPU clock counter snapshot.
4098  * Returns the 64 bit clock counter snapshot.
4099  */
4100 uint64_t gfx_v8_0_get_gpu_clock_counter(struct amdgpu_device *adev)
4101 {
4102         uint64_t clock;
4103
4104         mutex_lock(&adev->gfx.gpu_clock_mutex);
4105         WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4106         clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
4107                 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4108         mutex_unlock(&adev->gfx.gpu_clock_mutex);
4109         return clock;
4110 }
4111
4112 static void gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
4113                                           uint32_t vmid,
4114                                           uint32_t gds_base, uint32_t gds_size,
4115                                           uint32_t gws_base, uint32_t gws_size,
4116                                           uint32_t oa_base, uint32_t oa_size)
4117 {
4118         gds_base = gds_base >> AMDGPU_GDS_SHIFT;
4119         gds_size = gds_size >> AMDGPU_GDS_SHIFT;
4120
4121         gws_base = gws_base >> AMDGPU_GWS_SHIFT;
4122         gws_size = gws_size >> AMDGPU_GWS_SHIFT;
4123
4124         oa_base = oa_base >> AMDGPU_OA_SHIFT;
4125         oa_size = oa_size >> AMDGPU_OA_SHIFT;
4126
4127         /* GDS Base */
4128         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4129         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4130                                 WRITE_DATA_DST_SEL(0)));
4131         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
4132         amdgpu_ring_write(ring, 0);
4133         amdgpu_ring_write(ring, gds_base);
4134
4135         /* GDS Size */
4136         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4137         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4138                                 WRITE_DATA_DST_SEL(0)));
4139         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
4140         amdgpu_ring_write(ring, 0);
4141         amdgpu_ring_write(ring, gds_size);
4142
4143         /* GWS */
4144         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4145         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4146                                 WRITE_DATA_DST_SEL(0)));
4147         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
4148         amdgpu_ring_write(ring, 0);
4149         amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
4150
4151         /* OA */
4152         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4153         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4154                                 WRITE_DATA_DST_SEL(0)));
4155         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
4156         amdgpu_ring_write(ring, 0);
4157         amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
4158 }
4159
4160 static int gfx_v8_0_early_init(void *handle)
4161 {
4162         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4163
4164         adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS;
4165         adev->gfx.num_compute_rings = GFX8_NUM_COMPUTE_RINGS;
4166         gfx_v8_0_set_ring_funcs(adev);
4167         gfx_v8_0_set_irq_funcs(adev);
4168         gfx_v8_0_set_gds_init(adev);
4169
4170         return 0;
4171 }
4172
4173 static int gfx_v8_0_set_powergating_state(void *handle,
4174                                           enum amd_powergating_state state)
4175 {
4176         return 0;
4177 }
4178
4179 static int gfx_v8_0_set_clockgating_state(void *handle,
4180                                           enum amd_clockgating_state state)
4181 {
4182         return 0;
4183 }
4184
4185 static u32 gfx_v8_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
4186 {
4187         u32 rptr;
4188
4189         rptr = ring->adev->wb.wb[ring->rptr_offs];
4190
4191         return rptr;
4192 }
4193
4194 static u32 gfx_v8_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
4195 {
4196         struct amdgpu_device *adev = ring->adev;
4197         u32 wptr;
4198
4199         if (ring->use_doorbell)
4200                 /* XXX check if swapping is necessary on BE */
4201                 wptr = ring->adev->wb.wb[ring->wptr_offs];
4202         else
4203                 wptr = RREG32(mmCP_RB0_WPTR);
4204
4205         return wptr;
4206 }
4207
4208 static void gfx_v8_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
4209 {
4210         struct amdgpu_device *adev = ring->adev;
4211
4212         if (ring->use_doorbell) {
4213                 /* XXX check if swapping is necessary on BE */
4214                 adev->wb.wb[ring->wptr_offs] = ring->wptr;
4215                 WDOORBELL32(ring->doorbell_index, ring->wptr);
4216         } else {
4217                 WREG32(mmCP_RB0_WPTR, ring->wptr);
4218                 (void)RREG32(mmCP_RB0_WPTR);
4219         }
4220 }
4221
4222 static void gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
4223 {
4224         u32 ref_and_mask, reg_mem_engine;
4225
4226         if (ring->type == AMDGPU_RING_TYPE_COMPUTE) {
4227                 switch (ring->me) {
4228                 case 1:
4229                         ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
4230                         break;
4231                 case 2:
4232                         ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
4233                         break;
4234                 default:
4235                         return;
4236                 }
4237                 reg_mem_engine = 0;
4238         } else {
4239                 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
4240                 reg_mem_engine = WAIT_REG_MEM_ENGINE(1); /* pfp */
4241         }
4242
4243         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
4244         amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
4245                                  WAIT_REG_MEM_FUNCTION(3) |  /* == */
4246                                  reg_mem_engine));
4247         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
4248         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
4249         amdgpu_ring_write(ring, ref_and_mask);
4250         amdgpu_ring_write(ring, ref_and_mask);
4251         amdgpu_ring_write(ring, 0x20); /* poll interval */
4252 }
4253
4254 static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
4255                                   struct amdgpu_ib *ib)
4256 {
4257         bool need_ctx_switch = ring->current_ctx != ib->ctx;
4258         u32 header, control = 0;
4259         u32 next_rptr = ring->wptr + 5;
4260
4261         /* drop the CE preamble IB for the same context */
4262         if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && !need_ctx_switch)
4263                 return;
4264
4265         if (need_ctx_switch)
4266                 next_rptr += 2;
4267
4268         next_rptr += 4;
4269         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4270         amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
4271         amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
4272         amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
4273         amdgpu_ring_write(ring, next_rptr);
4274
4275         /* insert SWITCH_BUFFER packet before first IB in the ring frame */
4276         if (need_ctx_switch) {
4277                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4278                 amdgpu_ring_write(ring, 0);
4279         }
4280
4281         if (ib->flags & AMDGPU_IB_FLAG_CE)
4282                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
4283         else
4284                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
4285
4286         control |= ib->length_dw |
4287                 (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0);
4288
4289         amdgpu_ring_write(ring, header);
4290         amdgpu_ring_write(ring,
4291 #ifdef __BIG_ENDIAN
4292                           (2 << 0) |
4293 #endif
4294                           (ib->gpu_addr & 0xFFFFFFFC));
4295         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
4296         amdgpu_ring_write(ring, control);
4297 }
4298
4299 static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
4300                                   struct amdgpu_ib *ib)
4301 {
4302         u32 header, control = 0;
4303         u32 next_rptr = ring->wptr + 5;
4304
4305         control |= INDIRECT_BUFFER_VALID;
4306
4307         next_rptr += 4;
4308         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4309         amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
4310         amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
4311         amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
4312         amdgpu_ring_write(ring, next_rptr);
4313
4314         header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
4315
4316         control |= ib->length_dw |
4317                            (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0);
4318
4319         amdgpu_ring_write(ring, header);
4320         amdgpu_ring_write(ring,
4321 #ifdef __BIG_ENDIAN
4322                                           (2 << 0) |
4323 #endif
4324                                           (ib->gpu_addr & 0xFFFFFFFC));
4325         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
4326         amdgpu_ring_write(ring, control);
4327 }
4328
4329 static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
4330                                          u64 seq, unsigned flags)
4331 {
4332         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
4333         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
4334
4335         /* EVENT_WRITE_EOP - flush caches, send int */
4336         amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
4337         amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
4338                                  EOP_TC_ACTION_EN |
4339                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
4340                                  EVENT_INDEX(5)));
4341         amdgpu_ring_write(ring, addr & 0xfffffffc);
4342         amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
4343                           DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
4344         amdgpu_ring_write(ring, lower_32_bits(seq));
4345         amdgpu_ring_write(ring, upper_32_bits(seq));
4346
4347 }
4348
4349 /**
4350  * gfx_v8_0_ring_emit_semaphore - emit a semaphore on the CP ring
4351  *
4352  * @ring: amdgpu ring buffer object
4353  * @semaphore: amdgpu semaphore object
4354  * @emit_wait: Is this a sempahore wait?
4355  *
4356  * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP
4357  * from running ahead of semaphore waits.
4358  */
4359 static bool gfx_v8_0_ring_emit_semaphore(struct amdgpu_ring *ring,
4360                                          struct amdgpu_semaphore *semaphore,
4361                                          bool emit_wait)
4362 {
4363         uint64_t addr = semaphore->gpu_addr;
4364         unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
4365
4366         if (ring->adev->asic_type == CHIP_TOPAZ ||
4367             ring->adev->asic_type == CHIP_TONGA ||
4368             ring->adev->asic_type == CHIP_FIJI)
4369                 /* we got a hw semaphore bug in VI TONGA, return false to switch back to sw fence wait */
4370                 return false;
4371         else {
4372                 amdgpu_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 2));
4373                 amdgpu_ring_write(ring, lower_32_bits(addr));
4374                 amdgpu_ring_write(ring, upper_32_bits(addr));
4375                 amdgpu_ring_write(ring, sel);
4376         }
4377
4378         if (emit_wait && (ring->type == AMDGPU_RING_TYPE_GFX)) {
4379                 /* Prevent the PFP from running ahead of the semaphore wait */
4380                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
4381                 amdgpu_ring_write(ring, 0x0);
4382         }
4383
4384         return true;
4385 }
4386
4387 static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
4388                                         unsigned vm_id, uint64_t pd_addr)
4389 {
4390         int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
4391         uint32_t seq = ring->fence_drv.sync_seq[ring->idx];
4392         uint64_t addr = ring->fence_drv.gpu_addr;
4393
4394         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
4395         amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
4396                  WAIT_REG_MEM_FUNCTION(3))); /* equal */
4397         amdgpu_ring_write(ring, addr & 0xfffffffc);
4398         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
4399         amdgpu_ring_write(ring, seq);
4400         amdgpu_ring_write(ring, 0xffffffff);
4401         amdgpu_ring_write(ring, 4); /* poll interval */
4402
4403         if (usepfp) {
4404                 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
4405                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4406                 amdgpu_ring_write(ring, 0);
4407                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4408                 amdgpu_ring_write(ring, 0);
4409         }
4410
4411         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4412         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
4413                                  WRITE_DATA_DST_SEL(0)) |
4414                                  WR_CONFIRM);
4415         if (vm_id < 8) {
4416                 amdgpu_ring_write(ring,
4417                                   (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
4418         } else {
4419                 amdgpu_ring_write(ring,
4420                                   (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
4421         }
4422         amdgpu_ring_write(ring, 0);
4423         amdgpu_ring_write(ring, pd_addr >> 12);
4424
4425         /* bits 0-15 are the VM contexts0-15 */
4426         /* invalidate the cache */
4427         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4428         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4429                                  WRITE_DATA_DST_SEL(0)));
4430         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
4431         amdgpu_ring_write(ring, 0);
4432         amdgpu_ring_write(ring, 1 << vm_id);
4433
4434         /* wait for the invalidate to complete */
4435         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
4436         amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
4437                                  WAIT_REG_MEM_FUNCTION(0) |  /* always */
4438                                  WAIT_REG_MEM_ENGINE(0))); /* me */
4439         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
4440         amdgpu_ring_write(ring, 0);
4441         amdgpu_ring_write(ring, 0); /* ref */
4442         amdgpu_ring_write(ring, 0); /* mask */
4443         amdgpu_ring_write(ring, 0x20); /* poll interval */
4444
4445         /* compute doesn't have PFP */
4446         if (usepfp) {
4447                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
4448                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
4449                 amdgpu_ring_write(ring, 0x0);
4450                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4451                 amdgpu_ring_write(ring, 0);
4452                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4453                 amdgpu_ring_write(ring, 0);
4454         }
4455 }
4456
4457 static u32 gfx_v8_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
4458 {
4459         return ring->adev->wb.wb[ring->rptr_offs];
4460 }
4461
4462 static u32 gfx_v8_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
4463 {
4464         return ring->adev->wb.wb[ring->wptr_offs];
4465 }
4466
4467 static void gfx_v8_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
4468 {
4469         struct amdgpu_device *adev = ring->adev;
4470
4471         /* XXX check if swapping is necessary on BE */
4472         adev->wb.wb[ring->wptr_offs] = ring->wptr;
4473         WDOORBELL32(ring->doorbell_index, ring->wptr);
4474 }
4475
4476 static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
4477                                              u64 addr, u64 seq,
4478                                              unsigned flags)
4479 {
4480         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
4481         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
4482
4483         /* RELEASE_MEM - flush caches, send int */
4484         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
4485         amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
4486                                  EOP_TC_ACTION_EN |
4487                                  EOP_TC_WB_ACTION_EN |
4488                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
4489                                  EVENT_INDEX(5)));
4490         amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
4491         amdgpu_ring_write(ring, addr & 0xfffffffc);
4492         amdgpu_ring_write(ring, upper_32_bits(addr));
4493         amdgpu_ring_write(ring, lower_32_bits(seq));
4494         amdgpu_ring_write(ring, upper_32_bits(seq));
4495 }
4496
4497 static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4498                                                  enum amdgpu_interrupt_state state)
4499 {
4500         u32 cp_int_cntl;
4501
4502         switch (state) {
4503         case AMDGPU_IRQ_STATE_DISABLE:
4504                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4505                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4506                                             TIME_STAMP_INT_ENABLE, 0);
4507                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4508                 break;
4509         case AMDGPU_IRQ_STATE_ENABLE:
4510                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4511                 cp_int_cntl =
4512                         REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4513                                       TIME_STAMP_INT_ENABLE, 1);
4514                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4515                 break;
4516         default:
4517                 break;
4518         }
4519 }
4520
4521 static void gfx_v8_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4522                                                      int me, int pipe,
4523                                                      enum amdgpu_interrupt_state state)
4524 {
4525         u32 mec_int_cntl, mec_int_cntl_reg;
4526
4527         /*
4528          * amdgpu controls only pipe 0 of MEC1. That's why this function only
4529          * handles the setting of interrupts for this specific pipe. All other
4530          * pipes' interrupts are set by amdkfd.
4531          */
4532
4533         if (me == 1) {
4534                 switch (pipe) {
4535                 case 0:
4536                         mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
4537                         break;
4538                 default:
4539                         DRM_DEBUG("invalid pipe %d\n", pipe);
4540                         return;
4541                 }
4542         } else {
4543                 DRM_DEBUG("invalid me %d\n", me);
4544                 return;
4545         }
4546
4547         switch (state) {
4548         case AMDGPU_IRQ_STATE_DISABLE:
4549                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4550                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4551                                              TIME_STAMP_INT_ENABLE, 0);
4552                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4553                 break;
4554         case AMDGPU_IRQ_STATE_ENABLE:
4555                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4556                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4557                                              TIME_STAMP_INT_ENABLE, 1);
4558                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4559                 break;
4560         default:
4561                 break;
4562         }
4563 }
4564
4565 static int gfx_v8_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4566                                              struct amdgpu_irq_src *source,
4567                                              unsigned type,
4568                                              enum amdgpu_interrupt_state state)
4569 {
4570         u32 cp_int_cntl;
4571
4572         switch (state) {
4573         case AMDGPU_IRQ_STATE_DISABLE:
4574                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4575                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4576                                             PRIV_REG_INT_ENABLE, 0);
4577                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4578                 break;
4579         case AMDGPU_IRQ_STATE_ENABLE:
4580                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4581                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4582                                             PRIV_REG_INT_ENABLE, 0);
4583                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4584                 break;
4585         default:
4586                 break;
4587         }
4588
4589         return 0;
4590 }
4591
4592 static int gfx_v8_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4593                                               struct amdgpu_irq_src *source,
4594                                               unsigned type,
4595                                               enum amdgpu_interrupt_state state)
4596 {
4597         u32 cp_int_cntl;
4598
4599         switch (state) {
4600         case AMDGPU_IRQ_STATE_DISABLE:
4601                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4602                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4603                                             PRIV_INSTR_INT_ENABLE, 0);
4604                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4605                 break;
4606         case AMDGPU_IRQ_STATE_ENABLE:
4607                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4608                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4609                                             PRIV_INSTR_INT_ENABLE, 1);
4610                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4611                 break;
4612         default:
4613                 break;
4614         }
4615
4616         return 0;
4617 }
4618
4619 static int gfx_v8_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4620                                             struct amdgpu_irq_src *src,
4621                                             unsigned type,
4622                                             enum amdgpu_interrupt_state state)
4623 {
4624         switch (type) {
4625         case AMDGPU_CP_IRQ_GFX_EOP:
4626                 gfx_v8_0_set_gfx_eop_interrupt_state(adev, state);
4627                 break;
4628         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4629                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4630                 break;
4631         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4632                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4633                 break;
4634         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4635                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4636                 break;
4637         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4638                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4639                 break;
4640         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4641                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4642                 break;
4643         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4644                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4645                 break;
4646         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4647                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4648                 break;
4649         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4650                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4651                 break;
4652         default:
4653                 break;
4654         }
4655         return 0;
4656 }
4657
4658 static int gfx_v8_0_eop_irq(struct amdgpu_device *adev,
4659                             struct amdgpu_irq_src *source,
4660                             struct amdgpu_iv_entry *entry)
4661 {
4662         int i;
4663         u8 me_id, pipe_id, queue_id;
4664         struct amdgpu_ring *ring;
4665
4666         DRM_DEBUG("IH: CP EOP\n");
4667         me_id = (entry->ring_id & 0x0c) >> 2;
4668         pipe_id = (entry->ring_id & 0x03) >> 0;
4669         queue_id = (entry->ring_id & 0x70) >> 4;
4670
4671         switch (me_id) {
4672         case 0:
4673                 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4674                 break;
4675         case 1:
4676         case 2:
4677                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4678                         ring = &adev->gfx.compute_ring[i];
4679                         /* Per-queue interrupt is supported for MEC starting from VI.
4680                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
4681                           */
4682                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
4683                                 amdgpu_fence_process(ring);
4684                 }
4685                 break;
4686         }
4687         return 0;
4688 }
4689
4690 static int gfx_v8_0_priv_reg_irq(struct amdgpu_device *adev,
4691                                  struct amdgpu_irq_src *source,
4692                                  struct amdgpu_iv_entry *entry)
4693 {
4694         DRM_ERROR("Illegal register access in command stream\n");
4695         schedule_work(&adev->reset_work);
4696         return 0;
4697 }
4698
4699 static int gfx_v8_0_priv_inst_irq(struct amdgpu_device *adev,
4700                                   struct amdgpu_irq_src *source,
4701                                   struct amdgpu_iv_entry *entry)
4702 {
4703         DRM_ERROR("Illegal instruction in command stream\n");
4704         schedule_work(&adev->reset_work);
4705         return 0;
4706 }
4707
4708 const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
4709         .early_init = gfx_v8_0_early_init,
4710         .late_init = NULL,
4711         .sw_init = gfx_v8_0_sw_init,
4712         .sw_fini = gfx_v8_0_sw_fini,
4713         .hw_init = gfx_v8_0_hw_init,
4714         .hw_fini = gfx_v8_0_hw_fini,
4715         .suspend = gfx_v8_0_suspend,
4716         .resume = gfx_v8_0_resume,
4717         .is_idle = gfx_v8_0_is_idle,
4718         .wait_for_idle = gfx_v8_0_wait_for_idle,
4719         .soft_reset = gfx_v8_0_soft_reset,
4720         .print_status = gfx_v8_0_print_status,
4721         .set_clockgating_state = gfx_v8_0_set_clockgating_state,
4722         .set_powergating_state = gfx_v8_0_set_powergating_state,
4723 };
4724
4725 static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
4726         .get_rptr = gfx_v8_0_ring_get_rptr_gfx,
4727         .get_wptr = gfx_v8_0_ring_get_wptr_gfx,
4728         .set_wptr = gfx_v8_0_ring_set_wptr_gfx,
4729         .parse_cs = NULL,
4730         .emit_ib = gfx_v8_0_ring_emit_ib_gfx,
4731         .emit_fence = gfx_v8_0_ring_emit_fence_gfx,
4732         .emit_semaphore = gfx_v8_0_ring_emit_semaphore,
4733         .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
4734         .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
4735         .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
4736         .test_ring = gfx_v8_0_ring_test_ring,
4737         .test_ib = gfx_v8_0_ring_test_ib,
4738         .insert_nop = amdgpu_ring_insert_nop,
4739 };
4740
4741 static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
4742         .get_rptr = gfx_v8_0_ring_get_rptr_compute,
4743         .get_wptr = gfx_v8_0_ring_get_wptr_compute,
4744         .set_wptr = gfx_v8_0_ring_set_wptr_compute,
4745         .parse_cs = NULL,
4746         .emit_ib = gfx_v8_0_ring_emit_ib_compute,
4747         .emit_fence = gfx_v8_0_ring_emit_fence_compute,
4748         .emit_semaphore = gfx_v8_0_ring_emit_semaphore,
4749         .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
4750         .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
4751         .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
4752         .test_ring = gfx_v8_0_ring_test_ring,
4753         .test_ib = gfx_v8_0_ring_test_ib,
4754         .insert_nop = amdgpu_ring_insert_nop,
4755 };
4756
4757 static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev)
4758 {
4759         int i;
4760
4761         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4762                 adev->gfx.gfx_ring[i].funcs = &gfx_v8_0_ring_funcs_gfx;
4763
4764         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4765                 adev->gfx.compute_ring[i].funcs = &gfx_v8_0_ring_funcs_compute;
4766 }
4767
4768 static const struct amdgpu_irq_src_funcs gfx_v8_0_eop_irq_funcs = {
4769         .set = gfx_v8_0_set_eop_interrupt_state,
4770         .process = gfx_v8_0_eop_irq,
4771 };
4772
4773 static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_reg_irq_funcs = {
4774         .set = gfx_v8_0_set_priv_reg_fault_state,
4775         .process = gfx_v8_0_priv_reg_irq,
4776 };
4777
4778 static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_inst_irq_funcs = {
4779         .set = gfx_v8_0_set_priv_inst_fault_state,
4780         .process = gfx_v8_0_priv_inst_irq,
4781 };
4782
4783 static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev)
4784 {
4785         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
4786         adev->gfx.eop_irq.funcs = &gfx_v8_0_eop_irq_funcs;
4787
4788         adev->gfx.priv_reg_irq.num_types = 1;
4789         adev->gfx.priv_reg_irq.funcs = &gfx_v8_0_priv_reg_irq_funcs;
4790
4791         adev->gfx.priv_inst_irq.num_types = 1;
4792         adev->gfx.priv_inst_irq.funcs = &gfx_v8_0_priv_inst_irq_funcs;
4793 }
4794
4795 static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev)
4796 {
4797         /* init asci gds info */
4798         adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
4799         adev->gds.gws.total_size = 64;
4800         adev->gds.oa.total_size = 16;
4801
4802         if (adev->gds.mem.total_size == 64 * 1024) {
4803                 adev->gds.mem.gfx_partition_size = 4096;
4804                 adev->gds.mem.cs_partition_size = 4096;
4805
4806                 adev->gds.gws.gfx_partition_size = 4;
4807                 adev->gds.gws.cs_partition_size = 4;
4808
4809                 adev->gds.oa.gfx_partition_size = 4;
4810                 adev->gds.oa.cs_partition_size = 1;
4811         } else {
4812                 adev->gds.mem.gfx_partition_size = 1024;
4813                 adev->gds.mem.cs_partition_size = 1024;
4814
4815                 adev->gds.gws.gfx_partition_size = 16;
4816                 adev->gds.gws.cs_partition_size = 16;
4817
4818                 adev->gds.oa.gfx_partition_size = 4;
4819                 adev->gds.oa.cs_partition_size = 4;
4820         }
4821 }
4822
4823 static u32 gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device *adev,
4824                 u32 se, u32 sh)
4825 {
4826         u32 mask = 0, tmp, tmp1;
4827         int i;
4828
4829         gfx_v8_0_select_se_sh(adev, se, sh);
4830         tmp = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
4831         tmp1 = RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
4832         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
4833
4834         tmp &= 0xffff0000;
4835
4836         tmp |= tmp1;
4837         tmp >>= 16;
4838
4839         for (i = 0; i < adev->gfx.config.max_cu_per_sh; i ++) {
4840                 mask <<= 1;
4841                 mask |= 1;
4842         }
4843
4844         return (~tmp) & mask;
4845 }
4846
4847 int gfx_v8_0_get_cu_info(struct amdgpu_device *adev,
4848                                                  struct amdgpu_cu_info *cu_info)
4849 {
4850         int i, j, k, counter, active_cu_number = 0;
4851         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
4852
4853         if (!adev || !cu_info)
4854                 return -EINVAL;
4855
4856         mutex_lock(&adev->grbm_idx_mutex);
4857         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4858                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4859                         mask = 1;
4860                         ao_bitmap = 0;
4861                         counter = 0;
4862                         bitmap = gfx_v8_0_get_cu_active_bitmap(adev, i, j);
4863                         cu_info->bitmap[i][j] = bitmap;
4864
4865                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
4866                                 if (bitmap & mask) {
4867                                         if (counter < 2)
4868                                                 ao_bitmap |= mask;
4869                                         counter ++;
4870                                 }
4871                                 mask <<= 1;
4872                         }
4873                         active_cu_number += counter;
4874                         ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
4875                 }
4876         }
4877
4878         cu_info->number = active_cu_number;
4879         cu_info->ao_cu_mask = ao_cu_mask;
4880         mutex_unlock(&adev->grbm_idx_mutex);
4881         return 0;
4882 }