drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include "drmP.h"
  25 #include "amdgpu.h"
  26 #include "gmc_v8_0.h"
  27 #include "amdgpu_ucode.h"
  28
  29 #include "gmc/gmc_8_1_d.h"
  30 #include "gmc/gmc_8_1_sh_mask.h"
  31
  32 #include "bif/bif_5_0_d.h"
  33 #include "bif/bif_5_0_sh_mask.h"
  34
  35 #include "oss/oss_3_0_d.h"
  36 #include "oss/oss_3_0_sh_mask.h"
  37
  38 #include "vid.h"
  39 #include "vi.h"
  40
  41
  42 static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev);
  43 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
  44 static int gmc_v8_0_wait_for_idle(void *handle);
  45
  46 MODULE_FIRMWARE("amdgpu/tonga_mc.bin");
  47 MODULE_FIRMWARE("amdgpu/polaris11_mc.bin");
  48 MODULE_FIRMWARE("amdgpu/polaris10_mc.bin");
  49
  50 static const u32 golden_settings_tonga_a11[] =
  51 {
  52         mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
  53         mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028,
  54         mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991,
  55         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  56         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  57         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  58         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  59 };
  60
  61 static const u32 tonga_mgcg_cgcg_init[] =
  62 {
  63         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  64 };
  65
  66 static const u32 golden_settings_fiji_a10[] =
  67 {
  68         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  69         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  70         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  71         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  72 };
  73
  74 static const u32 fiji_mgcg_cgcg_init[] =
  75 {
  76         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  77 };
  78
  79 static const u32 golden_settings_polaris11_a11[] =
  80 {
  81         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  82         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  83         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  84         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
  85 };
  86
  87 static const u32 golden_settings_polaris10_a11[] =
  88 {
  89         mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
  90         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  91         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  92         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  93         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
  94 };
  95
  96 static const u32 cz_mgcg_cgcg_init[] =
  97 {
  98         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  99 };
 100
 101 static const u32 stoney_mgcg_cgcg_init[] =
 102 {
 103         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
 104 };
 105
 106 static const u32 golden_settings_stoney_common[] =
 107 {
 108         mmMC_HUB_RDREQ_UVD, MC_HUB_RDREQ_UVD__PRESCALE_MASK, 0x00000004,
 109         mmMC_RD_GRP_OTH, MC_RD_GRP_OTH__UVD_MASK, 0x00600000
 110 };
 111
 112 static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
 113 {
 114         switch (adev->asic_type) {
 115         case CHIP_FIJI:
 116                 amdgpu_program_register_sequence(adev,
 117                                                  fiji_mgcg_cgcg_init,
 118                                                  (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
 119                 amdgpu_program_register_sequence(adev,
 120                                                  golden_settings_fiji_a10,
 121                                                  (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
 122                 break;
 123         case CHIP_TONGA:
 124                 amdgpu_program_register_sequence(adev,
 125                                                  tonga_mgcg_cgcg_init,
 126                                                  (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
 127                 amdgpu_program_register_sequence(adev,
 128                                                  golden_settings_tonga_a11,
 129                                                  (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
 130                 break;
 131         case CHIP_POLARIS11:
 132                 amdgpu_program_register_sequence(adev,
 133                                                  golden_settings_polaris11_a11,
 134                                                  (const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
 135                 break;
 136         case CHIP_POLARIS10:
 137                 amdgpu_program_register_sequence(adev,
 138                                                  golden_settings_polaris10_a11,
 139                                                  (const u32)ARRAY_SIZE(golden_settings_polaris10_a11));
 140                 break;
 141         case CHIP_CARRIZO:
 142                 amdgpu_program_register_sequence(adev,
 143                                                  cz_mgcg_cgcg_init,
 144                                                  (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
 145                 break;
 146         case CHIP_STONEY:
 147                 amdgpu_program_register_sequence(adev,
 148                                                  stoney_mgcg_cgcg_init,
 149                                                  (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
 150                 amdgpu_program_register_sequence(adev,
 151                                                  golden_settings_stoney_common,
 152                                                  (const u32)ARRAY_SIZE(golden_settings_stoney_common));
 153                 break;
 154         default:
 155                 break;
 156         }
 157 }
 158
 159 static void gmc_v8_0_mc_stop(struct amdgpu_device *adev,
 160                              struct amdgpu_mode_mc_save *save)
 161 {
 162         u32 blackout;
 163
 164         if (adev->mode_info.num_crtc)
 165                 amdgpu_display_stop_mc_access(adev, save);
 166
 167         gmc_v8_0_wait_for_idle(adev);
 168
 169         blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 170         if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
 171                 /* Block CPU access */
 172                 WREG32(mmBIF_FB_EN, 0);
 173                 /* blackout the MC */
 174                 blackout = REG_SET_FIELD(blackout,
 175                                          MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1);
 176                 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
 177         }
 178         /* wait for the MC to settle */
 179         udelay(100);
 180 }
 181
 182 static void gmc_v8_0_mc_resume(struct amdgpu_device *adev,
 183                                struct amdgpu_mode_mc_save *save)
 184 {
 185         u32 tmp;
 186
 187         /* unblackout the MC */
 188         tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 189         tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
 190         WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
 191         /* allow CPU access */
 192         tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
 193         tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
 194         WREG32(mmBIF_FB_EN, tmp);
 195
 196         if (adev->mode_info.num_crtc)
 197                 amdgpu_display_resume_mc_access(adev, save);
 198 }
 199
 200 /**
 201  * gmc_v8_0_init_microcode - load ucode images from disk
 202  *
 203  * @adev: amdgpu_device pointer
 204  *
 205  * Use the firmware interface to load the ucode images into
 206  * the driver (not loaded into hw).
 207  * Returns 0 on success, error on failure.
 208  */
 209 static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)
 210 {
 211         const char *chip_name;
 212         char fw_name[30];
 213         int err;
 214
 215         DRM_DEBUG("\n");
 216
 217         switch (adev->asic_type) {
 218         case CHIP_TONGA:
 219                 chip_name = "tonga";
 220                 break;
 221         case CHIP_POLARIS11:
 222                 chip_name = "polaris11";
 223                 break;
 224         case CHIP_POLARIS10:
 225                 chip_name = "polaris10";
 226                 break;
 227         case CHIP_FIJI:
 228         case CHIP_CARRIZO:
 229         case CHIP_STONEY:
 230                 return 0;
 231         default: BUG();
 232         }
 233
 234         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
 235         err = request_firmware(&adev->mc.fw, fw_name, adev->dev);
 236         if (err)
 237                 goto out;
 238         err = amdgpu_ucode_validate(adev->mc.fw);
 239
 240 out:
 241         if (err) {
 242                 printk(KERN_ERR
 243                        "mc: Failed to load firmware \"%s\"\n",
 244                        fw_name);
 245                 release_firmware(adev->mc.fw);
 246                 adev->mc.fw = NULL;
 247         }
 248         return err;
 249 }
 250
 251 /**
 252  * gmc_v8_0_mc_load_microcode - load MC ucode into the hw
 253  *
 254  * @adev: amdgpu_device pointer
 255  *
 256  * Load the GDDR MC ucode into the hw (CIK).
 257  * Returns 0 on success, error on failure.
 258  */
 259 static int gmc_v8_0_mc_load_microcode(struct amdgpu_device *adev)
 260 {
 261         const struct mc_firmware_header_v1_0 *hdr;
 262         const __le32 *fw_data = NULL;
 263         const __le32 *io_mc_regs = NULL;
 264         u32 running;
 265         int i, ucode_size, regs_size;
 266
 267         if (!adev->mc.fw)
 268                 return -EINVAL;
 269
 270         /* Skip MC ucode loading on SR-IOV capable boards.
 271          * vbios does this for us in asic_init in that case.
 272          * Skip MC ucode loading on VF, because hypervisor will do that
 273          * for this adaptor.
 274          */
 275         if (amdgpu_sriov_bios(adev))
 276                 return 0;
 277
 278         hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
 279         amdgpu_ucode_print_mc_hdr(&hdr->header);
 280
 281         adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 282         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 283         io_mc_regs = (const __le32 *)
 284                 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 285         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 286         fw_data = (const __le32 *)
 287                 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 288
 289         running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
 290
 291         if (running == 0) {
 292                 /* reset the engine and set to writable */
 293                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 294                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 295
 296                 /* load mc io regs */
 297                 for (i = 0; i < regs_size; i++) {
 298                         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
 299                         WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
 300                 }
 301                 /* load the MC ucode */
 302                 for (i = 0; i < ucode_size; i++)
 303                         WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
 304
 305                 /* put the engine back into the active state */
 306                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 307                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 308                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 309
 310                 /* wait for training to complete */
 311                 for (i = 0; i < adev->usec_timeout; i++) {
 312                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 313                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
 314                                 break;
 315                         udelay(1);
 316                 }
 317                 for (i = 0; i < adev->usec_timeout; i++) {
 318                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 319                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
 320                                 break;
 321                         udelay(1);
 322                 }
 323         }
 324
 325         return 0;
 326 }
 327
 328 static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev,
 329                                        struct amdgpu_mc *mc)
 330 {
 331         if (mc->mc_vram_size > 0xFFC0000000ULL) {
 332                 /* leave room for at least 1024M GTT */
 333                 dev_warn(adev->dev, "limiting VRAM\n");
 334                 mc->real_vram_size = 0xFFC0000000ULL;
 335                 mc->mc_vram_size = 0xFFC0000000ULL;
 336         }
 337         amdgpu_vram_location(adev, &adev->mc, 0);
 338         adev->mc.gtt_base_align = 0;
 339         amdgpu_gtt_location(adev, mc);
 340 }
 341
 342 /**
 343  * gmc_v8_0_mc_program - program the GPU memory controller
 344  *
 345  * @adev: amdgpu_device pointer
 346  *
 347  * Set the location of vram, gart, and AGP in the GPU's
 348  * physical address space (CIK).
 349  */
 350 static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
 351 {
 352         struct amdgpu_mode_mc_save save;
 353         u32 tmp;
 354         int i, j;
 355
 356         /* Initialize HDP */
 357         for (i = 0, j = 0; i < 32; i++, j += 0x6) {
 358                 WREG32((0xb05 + j), 0x00000000);
 359                 WREG32((0xb06 + j), 0x00000000);
 360                 WREG32((0xb07 + j), 0x00000000);
 361                 WREG32((0xb08 + j), 0x00000000);
 362                 WREG32((0xb09 + j), 0x00000000);
 363         }
 364         WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
 365
 366         if (adev->mode_info.num_crtc)
 367                 amdgpu_display_set_vga_render_state(adev, false);
 368
 369         gmc_v8_0_mc_stop(adev, &save);
 370         if (gmc_v8_0_wait_for_idle((void *)adev)) {
 371                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 372         }
 373         /* Update configuration */
 374         WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 375                adev->mc.vram_start >> 12);
 376         WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 377                adev->mc.vram_end >> 12);
 378         WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
 379                adev->vram_scratch.gpu_addr >> 12);
 380         tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16;
 381         tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF);
 382         WREG32(mmMC_VM_FB_LOCATION, tmp);
 383         /* XXX double check these! */
 384         WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));
 385         WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
 386         WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
 387         WREG32(mmMC_VM_AGP_BASE, 0);
 388         WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
 389         WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
 390         if (gmc_v8_0_wait_for_idle((void *)adev)) {
 391                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 392         }
 393         gmc_v8_0_mc_resume(adev, &save);
 394
 395         WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
 396
 397         tmp = RREG32(mmHDP_MISC_CNTL);
 398         tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
 399         WREG32(mmHDP_MISC_CNTL, tmp);
 400
 401         tmp = RREG32(mmHDP_HOST_PATH_CNTL);
 402         WREG32(mmHDP_HOST_PATH_CNTL, tmp);
 403 }
 404
 405 /**
 406  * gmc_v8_0_mc_init - initialize the memory controller driver params
 407  *
 408  * @adev: amdgpu_device pointer
 409  *
 410  * Look up the amount of vram, vram width, and decide how to place
 411  * vram and gart within the GPU's physical address space (CIK).
 412  * Returns 0 for success.
 413  */
 414 static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
 415 {
 416         u32 tmp;
 417         int chansize, numchan;
 418
 419         /* Get VRAM informations */
 420         tmp = RREG32(mmMC_ARB_RAMCFG);
 421         if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
 422                 chansize = 64;
 423         } else {
 424                 chansize = 32;
 425         }
 426         tmp = RREG32(mmMC_SHARED_CHMAP);
 427         switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 428         case 0:
 429         default:
 430                 numchan = 1;
 431                 break;
 432         case 1:
 433                 numchan = 2;
 434                 break;
 435         case 2:
 436                 numchan = 4;
 437                 break;
 438         case 3:
 439                 numchan = 8;
 440                 break;
 441         case 4:
 442                 numchan = 3;
 443                 break;
 444         case 5:
 445                 numchan = 6;
 446                 break;
 447         case 6:
 448                 numchan = 10;
 449                 break;
 450         case 7:
 451                 numchan = 12;
 452                 break;
 453         case 8:
 454                 numchan = 16;
 455                 break;
 456         }
 457         adev->mc.vram_width = numchan * chansize;
 458         /* Could aper size report 0 ? */
 459         adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
 460         adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
 461         /* size in MB on si */
 462         adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 463         adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 464         adev->mc.visible_vram_size = adev->mc.aper_size;
 465
 466         /* In case the PCI BAR is larger than the actual amount of vram */
 467         if (adev->mc.visible_vram_size > adev->mc.real_vram_size)
 468                 adev->mc.visible_vram_size = adev->mc.real_vram_size;
 469
 470         /* unless the user had overridden it, set the gart
 471          * size equal to the 1024 or vram, whichever is larger.
 472          */
 473         if (amdgpu_gart_size == -1)
 474                 adev->mc.gtt_size = amdgpu_ttm_get_gtt_mem_size(adev);
 475         else
 476                 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20;
 477
 478         gmc_v8_0_vram_gtt_location(adev, &adev->mc);
 479
 480         return 0;
 481 }
 482
 483 /*
 484  * GART
 485  * VMID 0 is the physical GPU addresses as used by the kernel.
 486  * VMIDs 1-15 are used for userspace clients and are handled
 487  * by the amdgpu vm/hsa code.
 488  */
 489
 490 /**
 491  * gmc_v8_0_gart_flush_gpu_tlb - gart tlb flush callback
 492  *
 493  * @adev: amdgpu_device pointer
 494  * @vmid: vm instance to flush
 495  *
 496  * Flush the TLB for the requested page table (CIK).
 497  */
 498 static void gmc_v8_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
 499                                         uint32_t vmid)
 500 {
 501         /* flush hdp cache */
 502         WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
 503
 504         /* bits 0-15 are the VM contexts0-15 */
 505         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 506 }
 507
 508 /**
 509  * gmc_v8_0_gart_set_pte_pde - update the page tables using MMIO
 510  *
 511  * @adev: amdgpu_device pointer
 512  * @cpu_pt_addr: cpu address of the page table
 513  * @gpu_page_idx: entry in the page table to update
 514  * @addr: dst addr to write into pte/pde
 515  * @flags: access flags
 516  *
 517  * Update the page tables using the CPU.
 518  */
 519 static int gmc_v8_0_gart_set_pte_pde(struct amdgpu_device *adev,
 520                                      void *cpu_pt_addr,
 521                                      uint32_t gpu_page_idx,
 522                                      uint64_t addr,
 523                                      uint32_t flags)
 524 {
 525         void __iomem *ptr = (void *)cpu_pt_addr;
 526         uint64_t value;
 527
 528         /*
 529          * PTE format on VI:
 530          * 63:40 reserved
 531          * 39:12 4k physical page base address
 532          * 11:7 fragment
 533          * 6 write
 534          * 5 read
 535          * 4 exe
 536          * 3 reserved
 537          * 2 snooped
 538          * 1 system
 539          * 0 valid
 540          *
 541          * PDE format on VI:
 542          * 63:59 block fragment size
 543          * 58:40 reserved
 544          * 39:1 physical base address of PTE
 545          * bits 5:1 must be 0.
 546          * 0 valid
 547          */
 548         value = addr & 0x000000FFFFFFF000ULL;
 549         value |= flags;
 550         writeq(value, ptr + (gpu_page_idx * 8));
 551
 552         return 0;
 553 }
 554
 555 /**
 556  * gmc_v8_0_set_fault_enable_default - update VM fault handling
 557  *
 558  * @adev: amdgpu_device pointer
 559  * @value: true redirects VM faults to the default page
 560  */
 561 static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev,
 562                                               bool value)
 563 {
 564         u32 tmp;
 565
 566         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 567         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 568                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 569         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 570                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 571         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 572                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 573         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 574                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 575         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 576                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 577         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 578                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 579         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 580                             EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 581         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 582 }
 583
 584 /**
 585  * gmc_v8_0_gart_enable - gart enable
 586  *
 587  * @adev: amdgpu_device pointer
 588  *
 589  * This sets up the TLBs, programs the page tables for VMID0,
 590  * sets up the hw for VMIDs 1-15 which are allocated on
 591  * demand, and sets up the global locations for the LDS, GDS,
 592  * and GPUVM for FSA64 clients (CIK).
 593  * Returns 0 for success, errors for failure.
 594  */
 595 static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
 596 {
 597         int r, i;
 598         u32 tmp;
 599
 600         if (adev->gart.robj == NULL) {
 601                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 602                 return -EINVAL;
 603         }
 604         r = amdgpu_gart_table_vram_pin(adev);
 605         if (r)
 606                 return r;
 607         /* Setup TLB control */
 608         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 609         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 610         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
 611         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 612         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
 613         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 614         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 615         /* Setup L2 cache */
 616         tmp = RREG32(mmVM_L2_CNTL);
 617         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 618         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
 619         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
 620         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
 621         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
 622         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 623         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
 624         WREG32(mmVM_L2_CNTL, tmp);
 625         tmp = RREG32(mmVM_L2_CNTL2);
 626         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 627         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 628         WREG32(mmVM_L2_CNTL2, tmp);
 629         tmp = RREG32(mmVM_L2_CNTL3);
 630         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
 631         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 4);
 632         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 4);
 633         WREG32(mmVM_L2_CNTL3, tmp);
 634         /* XXX: set to enable PTE/PDE in system memory */
 635         tmp = RREG32(mmVM_L2_CNTL4);
 636         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0);
 637         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0);
 638         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0);
 639         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0);
 640         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0);
 641         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0);
 642         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0);
 643         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0);
 644         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0);
 645         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0);
 646         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0);
 647         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0);
 648         WREG32(mmVM_L2_CNTL4, tmp);
 649         /* setup context0 */
 650         WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12);
 651         WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12);
 652         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
 653         WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 654                         (u32)(adev->dummy_page.addr >> 12));
 655         WREG32(mmVM_CONTEXT0_CNTL2, 0);
 656         tmp = RREG32(mmVM_CONTEXT0_CNTL);
 657         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 658         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 659         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 660         WREG32(mmVM_CONTEXT0_CNTL, tmp);
 661
 662         WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0);
 663         WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0);
 664         WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0);
 665
 666         /* empty context1-15 */
 667         /* FIXME start with 4G, once using 2 level pt switch to full
 668          * vm size space
 669          */
 670         /* set vm size, must be a multiple of 4 */
 671         WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
 672         WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
 673         for (i = 1; i < 16; i++) {
 674                 if (i < 8)
 675                         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
 676                                adev->gart.table_addr >> 12);
 677                 else
 678                         WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
 679                                adev->gart.table_addr >> 12);
 680         }
 681
 682         /* enable context1-15 */
 683         WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
 684                (u32)(adev->dummy_page.addr >> 12));
 685         WREG32(mmVM_CONTEXT1_CNTL2, 4);
 686         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 687         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 688         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
 689         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 690         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 691         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 692         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 693         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 694         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 695         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 696         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
 697                             amdgpu_vm_block_size - 9);
 698         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 699         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
 700                 gmc_v8_0_set_fault_enable_default(adev, false);
 701         else
 702                 gmc_v8_0_set_fault_enable_default(adev, true);
 703
 704         gmc_v8_0_gart_flush_gpu_tlb(adev, 0);
 705         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 706                  (unsigned)(adev->mc.gtt_size >> 20),
 707                  (unsigned long long)adev->gart.table_addr);
 708         adev->gart.ready = true;
 709         return 0;
 710 }
 711
 712 static int gmc_v8_0_gart_init(struct amdgpu_device *adev)
 713 {
 714         int r;
 715
 716         if (adev->gart.robj) {
 717                 WARN(1, "R600 PCIE GART already initialized\n");
 718                 return 0;
 719         }
 720         /* Initialize common gart structure */
 721         r = amdgpu_gart_init(adev);
 722         if (r)
 723                 return r;
 724         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 725         return amdgpu_gart_table_vram_alloc(adev);
 726 }
 727
 728 /**
 729  * gmc_v8_0_gart_disable - gart disable
 730  *
 731  * @adev: amdgpu_device pointer
 732  *
 733  * This disables all VM page table (CIK).
 734  */
 735 static void gmc_v8_0_gart_disable(struct amdgpu_device *adev)
 736 {
 737         u32 tmp;
 738
 739         /* Disable all tables */
 740         WREG32(mmVM_CONTEXT0_CNTL, 0);
 741         WREG32(mmVM_CONTEXT1_CNTL, 0);
 742         /* Setup TLB control */
 743         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 744         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 745         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
 746         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
 747         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 748         /* Setup L2 cache */
 749         tmp = RREG32(mmVM_L2_CNTL);
 750         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 751         WREG32(mmVM_L2_CNTL, tmp);
 752         WREG32(mmVM_L2_CNTL2, 0);
 753         amdgpu_gart_table_vram_unpin(adev);
 754 }
 755
 756 /**
 757  * gmc_v8_0_gart_fini - vm fini callback
 758  *
 759  * @adev: amdgpu_device pointer
 760  *
 761  * Tears down the driver GART/VM setup (CIK).
 762  */
 763 static void gmc_v8_0_gart_fini(struct amdgpu_device *adev)
 764 {
 765         amdgpu_gart_table_vram_free(adev);
 766         amdgpu_gart_fini(adev);
 767 }
 768
 769 /*
 770  * vm
 771  * VMID 0 is the physical GPU addresses as used by the kernel.
 772  * VMIDs 1-15 are used for userspace clients and are handled
 773  * by the amdgpu vm/hsa code.
 774  */
 775 /**
 776  * gmc_v8_0_vm_init - cik vm init callback
 777  *
 778  * @adev: amdgpu_device pointer
 779  *
 780  * Inits cik specific vm parameters (number of VMs, base of vram for
 781  * VMIDs 1-15) (CIK).
 782  * Returns 0 for success.
 783  */
 784 static int gmc_v8_0_vm_init(struct amdgpu_device *adev)
 785 {
 786         /*
 787          * number of VMs
 788          * VMID 0 is reserved for System
 789          * amdgpu graphics/compute will use VMIDs 1-7
 790          * amdkfd will use VMIDs 8-15
 791          */
 792         adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS;
 793         amdgpu_vm_manager_init(adev);
 794
 795         /* base offset of vram pages */
 796         if (adev->flags & AMD_IS_APU) {
 797                 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
 798                 tmp <<= 22;
 799                 adev->vm_manager.vram_base_offset = tmp;
 800         } else
 801                 adev->vm_manager.vram_base_offset = 0;
 802
 803         return 0;
 804 }
 805
 806 /**
 807  * gmc_v8_0_vm_fini - cik vm fini callback
 808  *
 809  * @adev: amdgpu_device pointer
 810  *
 811  * Tear down any asic specific VM setup (CIK).
 812  */
 813 static void gmc_v8_0_vm_fini(struct amdgpu_device *adev)
 814 {
 815 }
 816
 817 /**
 818  * gmc_v8_0_vm_decode_fault - print human readable fault info
 819  *
 820  * @adev: amdgpu_device pointer
 821  * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
 822  * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
 823  *
 824  * Print human readable fault information (CIK).
 825  */
 826 static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev,
 827                                      u32 status, u32 addr, u32 mc_client)
 828 {
 829         u32 mc_id;
 830         u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
 831         u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 832                                         PROTECTIONS);
 833         char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
 834                 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
 835
 836         mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 837                               MEMORY_CLIENT_ID);
 838
 839         printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
 840                protections, vmid, addr,
 841                REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 842                              MEMORY_CLIENT_RW) ?
 843                "write" : "read", block, mc_client, mc_id);
 844 }
 845
 846 static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type)
 847 {
 848         switch (mc_seq_vram_type) {
 849         case MC_SEQ_MISC0__MT__GDDR1:
 850                 return AMDGPU_VRAM_TYPE_GDDR1;
 851         case MC_SEQ_MISC0__MT__DDR2:
 852                 return AMDGPU_VRAM_TYPE_DDR2;
 853         case MC_SEQ_MISC0__MT__GDDR3:
 854                 return AMDGPU_VRAM_TYPE_GDDR3;
 855         case MC_SEQ_MISC0__MT__GDDR4:
 856                 return AMDGPU_VRAM_TYPE_GDDR4;
 857         case MC_SEQ_MISC0__MT__GDDR5:
 858                 return AMDGPU_VRAM_TYPE_GDDR5;
 859         case MC_SEQ_MISC0__MT__HBM:
 860                 return AMDGPU_VRAM_TYPE_HBM;
 861         case MC_SEQ_MISC0__MT__DDR3:
 862                 return AMDGPU_VRAM_TYPE_DDR3;
 863         default:
 864                 return AMDGPU_VRAM_TYPE_UNKNOWN;
 865         }
 866 }
 867
 868 static int gmc_v8_0_early_init(void *handle)
 869 {
 870         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 871
 872         gmc_v8_0_set_gart_funcs(adev);
 873         gmc_v8_0_set_irq_funcs(adev);
 874
 875         return 0;
 876 }
 877
 878 static int gmc_v8_0_late_init(void *handle)
 879 {
 880         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 881
 882         if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
 883                 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
 884         else
 885                 return 0;
 886 }
 887
 888 #define mmMC_SEQ_MISC0_FIJI 0xA71
 889
 890 static int gmc_v8_0_sw_init(void *handle)
 891 {
 892         int r;
 893         int dma_bits;
 894         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 895
 896         if (adev->flags & AMD_IS_APU) {
 897                 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 898         } else {
 899                 u32 tmp;
 900
 901                 if (adev->asic_type == CHIP_FIJI)
 902                         tmp = RREG32(mmMC_SEQ_MISC0_FIJI);
 903                 else
 904                         tmp = RREG32(mmMC_SEQ_MISC0);
 905                 tmp &= MC_SEQ_MISC0__MT__MASK;
 906                 adev->mc.vram_type = gmc_v8_0_convert_vram_type(tmp);
 907         }
 908
 909         r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault);
 910         if (r)
 911                 return r;
 912
 913         r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault);
 914         if (r)
 915                 return r;
 916
 917         /* Adjust VM size here.
 918          * Currently set to 4GB ((1 << 20) 4k pages).
 919          * Max GPUVM size for cayman and SI is 40 bits.
 920          */
 921         adev->vm_manager.max_pfn = amdgpu_vm_size << 18;
 922
 923         /* Set the internal MC address mask
 924          * This is the max address of the GPU's
 925          * internal address space.
 926          */
 927         adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
 928
 929         /* set DMA mask + need_dma32 flags.
 930          * PCIE - can handle 40-bits.
 931          * IGP - can handle 40-bits
 932          * PCI - dma32 for legacy pci gart, 40 bits on newer asics
 933          */
 934         adev->need_dma32 = false;
 935         dma_bits = adev->need_dma32 ? 32 : 40;
 936         r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 937         if (r) {
 938                 adev->need_dma32 = true;
 939                 dma_bits = 32;
 940                 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
 941         }
 942         r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
 943         if (r) {
 944                 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
 945                 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n");
 946         }
 947
 948         r = gmc_v8_0_init_microcode(adev);
 949         if (r) {
 950                 DRM_ERROR("Failed to load mc firmware!\n");
 951                 return r;
 952         }
 953
 954         r = amdgpu_ttm_global_init(adev);
 955         if (r) {
 956                 return r;
 957         }
 958
 959         r = gmc_v8_0_mc_init(adev);
 960         if (r)
 961                 return r;
 962
 963         /* Memory manager */
 964         r = amdgpu_bo_init(adev);
 965         if (r)
 966                 return r;
 967
 968         r = gmc_v8_0_gart_init(adev);
 969         if (r)
 970                 return r;
 971
 972         if (!adev->vm_manager.enabled) {
 973                 r = gmc_v8_0_vm_init(adev);
 974                 if (r) {
 975                         dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
 976                         return r;
 977                 }
 978                 adev->vm_manager.enabled = true;
 979         }
 980
 981         return r;
 982 }
 983
 984 static int gmc_v8_0_sw_fini(void *handle)
 985 {
 986         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 987
 988         if (adev->vm_manager.enabled) {
 989                 amdgpu_vm_manager_fini(adev);
 990                 gmc_v8_0_vm_fini(adev);
 991                 adev->vm_manager.enabled = false;
 992         }
 993         gmc_v8_0_gart_fini(adev);
 994         amdgpu_gem_force_release(adev);
 995         amdgpu_bo_fini(adev);
 996
 997         return 0;
 998 }
 999
1000 static int gmc_v8_0_hw_init(void *handle)
1001 {
1002         int r;
1003         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1004
1005         gmc_v8_0_init_golden_registers(adev);
1006
1007         gmc_v8_0_mc_program(adev);
1008
1009         if (adev->asic_type == CHIP_TONGA) {
1010                 r = gmc_v8_0_mc_load_microcode(adev);
1011                 if (r) {
1012                         DRM_ERROR("Failed to load MC firmware!\n");
1013                         return r;
1014                 }
1015         }
1016
1017         r = gmc_v8_0_gart_enable(adev);
1018         if (r)
1019                 return r;
1020
1021         return r;
1022 }
1023
1024 static int gmc_v8_0_hw_fini(void *handle)
1025 {
1026         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1027
1028         amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
1029         gmc_v8_0_gart_disable(adev);
1030
1031         return 0;
1032 }
1033
1034 static int gmc_v8_0_suspend(void *handle)
1035 {
1036         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1037
1038         if (adev->vm_manager.enabled) {
1039                 gmc_v8_0_vm_fini(adev);
1040                 adev->vm_manager.enabled = false;
1041         }
1042         gmc_v8_0_hw_fini(adev);
1043
1044         return 0;
1045 }
1046
1047 static int gmc_v8_0_resume(void *handle)
1048 {
1049         int r;
1050         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1051
1052         r = gmc_v8_0_hw_init(adev);
1053         if (r)
1054                 return r;
1055
1056         if (!adev->vm_manager.enabled) {
1057                 r = gmc_v8_0_vm_init(adev);
1058                 if (r) {
1059                         dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
1060                         return r;
1061                 }
1062                 adev->vm_manager.enabled = true;
1063         }
1064
1065         return r;
1066 }
1067
1068 static bool gmc_v8_0_is_idle(void *handle)
1069 {
1070         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1071         u32 tmp = RREG32(mmSRBM_STATUS);
1072
1073         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1074                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1075                 return false;
1076
1077         return true;
1078 }
1079
1080 static int gmc_v8_0_wait_for_idle(void *handle)
1081 {
1082         unsigned i;
1083         u32 tmp;
1084         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1085
1086         for (i = 0; i < adev->usec_timeout; i++) {
1087                 /* read MC_STATUS */
1088                 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1089                                                SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1090                                                SRBM_STATUS__MCC_BUSY_MASK |
1091                                                SRBM_STATUS__MCD_BUSY_MASK |
1092                                                SRBM_STATUS__VMC_BUSY_MASK |
1093                                                SRBM_STATUS__VMC1_BUSY_MASK);
1094                 if (!tmp)
1095                         return 0;
1096                 udelay(1);
1097         }
1098         return -ETIMEDOUT;
1099
1100 }
1101
1102 static int gmc_v8_0_check_soft_reset(void *handle)
1103 {
1104         u32 srbm_soft_reset = 0;
1105         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1106         u32 tmp = RREG32(mmSRBM_STATUS);
1107
1108         if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1109                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1110                                                 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1111
1112         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1113                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1114                 if (!(adev->flags & AMD_IS_APU))
1115                         srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1116                                                         SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1117         }
1118         if (srbm_soft_reset) {
1119                 adev->ip_block_status[AMD_IP_BLOCK_TYPE_GMC].hang = true;
1120                 adev->mc.srbm_soft_reset = srbm_soft_reset;
1121         } else {
1122                 adev->ip_block_status[AMD_IP_BLOCK_TYPE_GMC].hang = false;
1123                 adev->mc.srbm_soft_reset = 0;
1124         }
1125         return 0;
1126 }
1127
1128 static int gmc_v8_0_pre_soft_reset(void *handle)
1129 {
1130         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1131
1132         if (!adev->ip_block_status[AMD_IP_BLOCK_TYPE_GMC].hang)
1133                 return 0;
1134
1135         gmc_v8_0_mc_stop(adev, &adev->mc.save);
1136         if (gmc_v8_0_wait_for_idle(adev)) {
1137                 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1138         }
1139
1140         return 0;
1141 }
1142
1143 static int gmc_v8_0_soft_reset(void *handle)
1144 {
1145         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1146         u32 srbm_soft_reset;
1147
1148         if (!adev->ip_block_status[AMD_IP_BLOCK_TYPE_GMC].hang)
1149                 return 0;
1150         srbm_soft_reset = adev->mc.srbm_soft_reset;
1151
1152         if (srbm_soft_reset) {
1153                 u32 tmp;
1154
1155                 tmp = RREG32(mmSRBM_SOFT_RESET);
1156                 tmp |= srbm_soft_reset;
1157                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1158                 WREG32(mmSRBM_SOFT_RESET, tmp);
1159                 tmp = RREG32(mmSRBM_SOFT_RESET);
1160
1161                 udelay(50);
1162
1163                 tmp &= ~srbm_soft_reset;
1164                 WREG32(mmSRBM_SOFT_RESET, tmp);
1165                 tmp = RREG32(mmSRBM_SOFT_RESET);
1166
1167                 /* Wait a little for things to settle down */
1168                 udelay(50);
1169         }
1170
1171         return 0;
1172 }
1173
1174 static int gmc_v8_0_post_soft_reset(void *handle)
1175 {
1176         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1177
1178         if (!adev->ip_block_status[AMD_IP_BLOCK_TYPE_GMC].hang)
1179                 return 0;
1180
1181         gmc_v8_0_mc_resume(adev, &adev->mc.save);
1182         return 0;
1183 }
1184
1185 static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1186                                              struct amdgpu_irq_src *src,
1187                                              unsigned type,
1188                                              enum amdgpu_interrupt_state state)
1189 {
1190         u32 tmp;
1191         u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1192                     VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1193                     VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1194                     VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1195                     VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1196                     VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1197                     VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1198
1199         switch (state) {
1200         case AMDGPU_IRQ_STATE_DISABLE:
1201                 /* system context */
1202                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1203                 tmp &= ~bits;
1204                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1205                 /* VMs */
1206                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1207                 tmp &= ~bits;
1208                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1209                 break;
1210         case AMDGPU_IRQ_STATE_ENABLE:
1211                 /* system context */
1212                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1213                 tmp |= bits;
1214                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1215                 /* VMs */
1216                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1217                 tmp |= bits;
1218                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1219                 break;
1220         default:
1221                 break;
1222         }
1223
1224         return 0;
1225 }
1226
1227 static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,
1228                                       struct amdgpu_irq_src *source,
1229                                       struct amdgpu_iv_entry *entry)
1230 {
1231         u32 addr, status, mc_client;
1232
1233         addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1234         status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1235         mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1236         /* reset addr and status */
1237         WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1238
1239         if (!addr && !status)
1240                 return 0;
1241
1242         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1243                 gmc_v8_0_set_fault_enable_default(adev, false);
1244
1245         dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1246                 entry->src_id, entry->src_data);
1247         dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1248                 addr);
1249         dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1250                 status);
1251         gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client);
1252
1253         return 0;
1254 }
1255
1256 static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev,
1257                                                      bool enable)
1258 {
1259         uint32_t data;
1260
1261         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
1262                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1263                 data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1264                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1265
1266                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1267                 data |= MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1268                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1269
1270                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1271                 data |= MC_HUB_MISC_VM_CG__ENABLE_MASK;
1272                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1273
1274                 data = RREG32(mmMC_XPB_CLK_GAT);
1275                 data |= MC_XPB_CLK_GAT__ENABLE_MASK;
1276                 WREG32(mmMC_XPB_CLK_GAT, data);
1277
1278                 data = RREG32(mmATC_MISC_CG);
1279                 data |= ATC_MISC_CG__ENABLE_MASK;
1280                 WREG32(mmATC_MISC_CG, data);
1281
1282                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1283                 data |= MC_CITF_MISC_WR_CG__ENABLE_MASK;
1284                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1285
1286                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1287                 data |= MC_CITF_MISC_RD_CG__ENABLE_MASK;
1288                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1289
1290                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1291                 data |= MC_CITF_MISC_VM_CG__ENABLE_MASK;
1292                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1293
1294                 data = RREG32(mmVM_L2_CG);
1295                 data |= VM_L2_CG__ENABLE_MASK;
1296                 WREG32(mmVM_L2_CG, data);
1297         } else {
1298                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1299                 data &= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1300                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1301
1302                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1303                 data &= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1304                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1305
1306                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1307                 data &= ~MC_HUB_MISC_VM_CG__ENABLE_MASK;
1308                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1309
1310                 data = RREG32(mmMC_XPB_CLK_GAT);
1311                 data &= ~MC_XPB_CLK_GAT__ENABLE_MASK;
1312                 WREG32(mmMC_XPB_CLK_GAT, data);
1313
1314                 data = RREG32(mmATC_MISC_CG);
1315                 data &= ~ATC_MISC_CG__ENABLE_MASK;
1316                 WREG32(mmATC_MISC_CG, data);
1317
1318                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1319                 data &= ~MC_CITF_MISC_WR_CG__ENABLE_MASK;
1320                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1321
1322                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1323                 data &= ~MC_CITF_MISC_RD_CG__ENABLE_MASK;
1324                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1325
1326                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1327                 data &= ~MC_CITF_MISC_VM_CG__ENABLE_MASK;
1328                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1329
1330                 data = RREG32(mmVM_L2_CG);
1331                 data &= ~VM_L2_CG__ENABLE_MASK;
1332                 WREG32(mmVM_L2_CG, data);
1333         }
1334 }
1335
1336 static void fiji_update_mc_light_sleep(struct amdgpu_device *adev,
1337                                        bool enable)
1338 {
1339         uint32_t data;
1340
1341         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) {
1342                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1343                 data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1344                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1345
1346                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1347                 data |= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1348                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1349
1350                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1351                 data |= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1352                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1353
1354                 data = RREG32(mmMC_XPB_CLK_GAT);
1355                 data |= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1356                 WREG32(mmMC_XPB_CLK_GAT, data);
1357
1358                 data = RREG32(mmATC_MISC_CG);
1359                 data |= ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1360                 WREG32(mmATC_MISC_CG, data);
1361
1362                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1363                 data |= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1364                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1365
1366                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1367                 data |= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1368                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1369
1370                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1371                 data |= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1372                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1373
1374                 data = RREG32(mmVM_L2_CG);
1375                 data |= VM_L2_CG__MEM_LS_ENABLE_MASK;
1376                 WREG32(mmVM_L2_CG, data);
1377         } else {
1378                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1379                 data &= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1380                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1381
1382                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1383                 data &= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1384                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1385
1386                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1387                 data &= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1388                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1389
1390                 data = RREG32(mmMC_XPB_CLK_GAT);
1391                 data &= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1392                 WREG32(mmMC_XPB_CLK_GAT, data);
1393
1394                 data = RREG32(mmATC_MISC_CG);
1395                 data &= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1396                 WREG32(mmATC_MISC_CG, data);
1397
1398                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1399                 data &= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1400                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1401
1402                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1403                 data &= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1404                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1405
1406                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1407                 data &= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1408                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1409
1410                 data = RREG32(mmVM_L2_CG);
1411                 data &= ~VM_L2_CG__MEM_LS_ENABLE_MASK;
1412                 WREG32(mmVM_L2_CG, data);
1413         }
1414 }
1415
1416 static int gmc_v8_0_set_clockgating_state(void *handle,
1417                                           enum amd_clockgating_state state)
1418 {
1419         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1420
1421         switch (adev->asic_type) {
1422         case CHIP_FIJI:
1423                 fiji_update_mc_medium_grain_clock_gating(adev,
1424                                 state == AMD_CG_STATE_GATE ? true : false);
1425                 fiji_update_mc_light_sleep(adev,
1426                                 state == AMD_CG_STATE_GATE ? true : false);
1427                 break;
1428         default:
1429                 break;
1430         }
1431         return 0;
1432 }
1433
1434 static int gmc_v8_0_set_powergating_state(void *handle,
1435                                           enum amd_powergating_state state)
1436 {
1437         return 0;
1438 }
1439
1440 const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
1441         .name = "gmc_v8_0",
1442         .early_init = gmc_v8_0_early_init,
1443         .late_init = gmc_v8_0_late_init,
1444         .sw_init = gmc_v8_0_sw_init,
1445         .sw_fini = gmc_v8_0_sw_fini,
1446         .hw_init = gmc_v8_0_hw_init,
1447         .hw_fini = gmc_v8_0_hw_fini,
1448         .suspend = gmc_v8_0_suspend,
1449         .resume = gmc_v8_0_resume,
1450         .is_idle = gmc_v8_0_is_idle,
1451         .wait_for_idle = gmc_v8_0_wait_for_idle,
1452         .check_soft_reset = gmc_v8_0_check_soft_reset,
1453         .pre_soft_reset = gmc_v8_0_pre_soft_reset,
1454         .soft_reset = gmc_v8_0_soft_reset,
1455         .post_soft_reset = gmc_v8_0_post_soft_reset,
1456         .set_clockgating_state = gmc_v8_0_set_clockgating_state,
1457         .set_powergating_state = gmc_v8_0_set_powergating_state,
1458 };
1459
1460 static const struct amdgpu_gart_funcs gmc_v8_0_gart_funcs = {
1461         .flush_gpu_tlb = gmc_v8_0_gart_flush_gpu_tlb,
1462         .set_pte_pde = gmc_v8_0_gart_set_pte_pde,
1463 };
1464
1465 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = {
1466         .set = gmc_v8_0_vm_fault_interrupt_state,
1467         .process = gmc_v8_0_process_interrupt,
1468 };
1469
1470 static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev)
1471 {
1472         if (adev->gart.gart_funcs == NULL)
1473                 adev->gart.gart_funcs = &gmc_v8_0_gart_funcs;
1474 }
1475
1476 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev)
1477 {
1478         adev->mc.vm_fault.num_types = 1;
1479         adev->mc.vm_fault.funcs = &gmc_v8_0_irq_funcs;
1480 }