2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
27 #include "amdgpu_ucode.h"
29 #include "gmc/gmc_8_1_d.h"
30 #include "gmc/gmc_8_1_sh_mask.h"
32 #include "bif/bif_5_0_d.h"
33 #include "bif/bif_5_0_sh_mask.h"
35 #include "oss/oss_3_0_d.h"
36 #include "oss/oss_3_0_sh_mask.h"
42 static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev);
43 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
45 MODULE_FIRMWARE("amdgpu/topaz_mc.bin");
46 MODULE_FIRMWARE("amdgpu/tonga_mc.bin");
47 MODULE_FIRMWARE("amdgpu/fiji_mc.bin");
49 static const u32 golden_settings_tonga_a11[] =
51 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
52 mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028,
53 mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991,
54 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
55 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
56 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
57 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
60 static const u32 tonga_mgcg_cgcg_init[] =
62 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
65 static const u32 golden_settings_fiji_a10[] =
67 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
68 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
69 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
70 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
73 static const u32 fiji_mgcg_cgcg_init[] =
75 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
78 static const u32 golden_settings_iceland_a11[] =
80 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
81 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
82 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
83 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
86 static const u32 iceland_mgcg_cgcg_init[] =
88 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
91 static const u32 cz_mgcg_cgcg_init[] =
93 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
96 static const u32 stoney_mgcg_cgcg_init[] =
98 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
102 static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
104 switch (adev->asic_type) {
106 amdgpu_program_register_sequence(adev,
107 iceland_mgcg_cgcg_init,
108 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
109 amdgpu_program_register_sequence(adev,
110 golden_settings_iceland_a11,
111 (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
114 amdgpu_program_register_sequence(adev,
116 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
117 amdgpu_program_register_sequence(adev,
118 golden_settings_fiji_a10,
119 (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
122 amdgpu_program_register_sequence(adev,
123 tonga_mgcg_cgcg_init,
124 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
125 amdgpu_program_register_sequence(adev,
126 golden_settings_tonga_a11,
127 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
130 amdgpu_program_register_sequence(adev,
132 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
135 amdgpu_program_register_sequence(adev,
136 stoney_mgcg_cgcg_init,
137 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
145 * gmc8_mc_wait_for_idle - wait for MC idle callback.
147 * @adev: amdgpu_device pointer
149 * Wait for the MC (memory controller) to be idle.
151 * Returns 0 if the MC is idle, -1 if not.
153 int gmc_v8_0_mc_wait_for_idle(struct amdgpu_device *adev)
158 for (i = 0; i < adev->usec_timeout; i++) {
160 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__VMC_BUSY_MASK |
161 SRBM_STATUS__MCB_BUSY_MASK |
162 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
163 SRBM_STATUS__MCC_BUSY_MASK |
164 SRBM_STATUS__MCD_BUSY_MASK |
165 SRBM_STATUS__VMC1_BUSY_MASK);
173 void gmc_v8_0_mc_stop(struct amdgpu_device *adev,
174 struct amdgpu_mode_mc_save *save)
178 if (adev->mode_info.num_crtc)
179 amdgpu_display_stop_mc_access(adev, save);
181 amdgpu_asic_wait_for_mc_idle(adev);
183 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
184 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
185 /* Block CPU access */
186 WREG32(mmBIF_FB_EN, 0);
187 /* blackout the MC */
188 blackout = REG_SET_FIELD(blackout,
189 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1);
190 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
192 /* wait for the MC to settle */
196 void gmc_v8_0_mc_resume(struct amdgpu_device *adev,
197 struct amdgpu_mode_mc_save *save)
201 /* unblackout the MC */
202 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
203 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
204 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
205 /* allow CPU access */
206 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
207 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
208 WREG32(mmBIF_FB_EN, tmp);
210 if (adev->mode_info.num_crtc)
211 amdgpu_display_resume_mc_access(adev, save);
215 * gmc_v8_0_init_microcode - load ucode images from disk
217 * @adev: amdgpu_device pointer
219 * Use the firmware interface to load the ucode images into
220 * the driver (not loaded into hw).
221 * Returns 0 on success, error on failure.
223 static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)
225 const char *chip_name;
231 switch (adev->asic_type) {
247 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
248 err = request_firmware(&adev->mc.fw, fw_name, adev->dev);
251 err = amdgpu_ucode_validate(adev->mc.fw);
256 "mc: Failed to load firmware \"%s\"\n",
258 release_firmware(adev->mc.fw);
265 * gmc_v8_0_mc_load_microcode - load MC ucode into the hw
267 * @adev: amdgpu_device pointer
269 * Load the GDDR MC ucode into the hw (CIK).
270 * Returns 0 on success, error on failure.
272 static int gmc_v8_0_mc_load_microcode(struct amdgpu_device *adev)
274 const struct mc_firmware_header_v1_0 *hdr;
275 const __le32 *fw_data = NULL;
276 const __le32 *io_mc_regs = NULL;
277 u32 running, blackout = 0;
278 int i, ucode_size, regs_size;
283 hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
284 amdgpu_ucode_print_mc_hdr(&hdr->header);
286 adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
287 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
288 io_mc_regs = (const __le32 *)
289 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
290 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
291 fw_data = (const __le32 *)
292 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
294 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
298 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
299 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
302 /* reset the engine and set to writable */
303 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
304 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
306 /* load mc io regs */
307 for (i = 0; i < regs_size; i++) {
308 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
309 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
311 /* load the MC ucode */
312 for (i = 0; i < ucode_size; i++)
313 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
315 /* put the engine back into the active state */
316 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
317 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
318 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
320 /* wait for training to complete */
321 for (i = 0; i < adev->usec_timeout; i++) {
322 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
323 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
327 for (i = 0; i < adev->usec_timeout; i++) {
328 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
329 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
335 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
341 static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev,
342 struct amdgpu_mc *mc)
344 if (mc->mc_vram_size > 0xFFC0000000ULL) {
345 /* leave room for at least 1024M GTT */
346 dev_warn(adev->dev, "limiting VRAM\n");
347 mc->real_vram_size = 0xFFC0000000ULL;
348 mc->mc_vram_size = 0xFFC0000000ULL;
350 amdgpu_vram_location(adev, &adev->mc, 0);
351 adev->mc.gtt_base_align = 0;
352 amdgpu_gtt_location(adev, mc);
356 * gmc_v8_0_mc_program - program the GPU memory controller
358 * @adev: amdgpu_device pointer
360 * Set the location of vram, gart, and AGP in the GPU's
361 * physical address space (CIK).
363 static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
365 struct amdgpu_mode_mc_save save;
370 for (i = 0, j = 0; i < 32; i++, j += 0x6) {
371 WREG32((0xb05 + j), 0x00000000);
372 WREG32((0xb06 + j), 0x00000000);
373 WREG32((0xb07 + j), 0x00000000);
374 WREG32((0xb08 + j), 0x00000000);
375 WREG32((0xb09 + j), 0x00000000);
377 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
379 if (adev->mode_info.num_crtc)
380 amdgpu_display_set_vga_render_state(adev, false);
382 gmc_v8_0_mc_stop(adev, &save);
383 if (amdgpu_asic_wait_for_mc_idle(adev)) {
384 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
386 /* Update configuration */
387 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
388 adev->mc.vram_start >> 12);
389 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
390 adev->mc.vram_end >> 12);
391 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
392 adev->vram_scratch.gpu_addr >> 12);
393 tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16;
394 tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF);
395 WREG32(mmMC_VM_FB_LOCATION, tmp);
396 /* XXX double check these! */
397 WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));
398 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
399 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
400 WREG32(mmMC_VM_AGP_BASE, 0);
401 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
402 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
403 if (amdgpu_asic_wait_for_mc_idle(adev)) {
404 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
406 gmc_v8_0_mc_resume(adev, &save);
408 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
410 tmp = RREG32(mmHDP_MISC_CNTL);
411 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
412 WREG32(mmHDP_MISC_CNTL, tmp);
414 tmp = RREG32(mmHDP_HOST_PATH_CNTL);
415 WREG32(mmHDP_HOST_PATH_CNTL, tmp);
419 * gmc_v8_0_mc_init - initialize the memory controller driver params
421 * @adev: amdgpu_device pointer
423 * Look up the amount of vram, vram width, and decide how to place
424 * vram and gart within the GPU's physical address space (CIK).
425 * Returns 0 for success.
427 static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
430 int chansize, numchan;
432 /* Get VRAM informations */
433 tmp = RREG32(mmMC_ARB_RAMCFG);
434 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
439 tmp = RREG32(mmMC_SHARED_CHMAP);
440 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
470 adev->mc.vram_width = numchan * chansize;
471 /* Could aper size report 0 ? */
472 adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
473 adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
474 /* size in MB on si */
475 adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
476 adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
477 adev->mc.visible_vram_size = adev->mc.aper_size;
479 /* In case the PCI BAR is larger than the actual amount of vram */
480 if (adev->mc.visible_vram_size > adev->mc.real_vram_size)
481 adev->mc.visible_vram_size = adev->mc.real_vram_size;
483 /* unless the user had overridden it, set the gart
484 * size equal to the 1024 or vram, whichever is larger.
486 if (amdgpu_gart_size == -1)
487 adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size);
489 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20;
491 gmc_v8_0_vram_gtt_location(adev, &adev->mc);
498 * VMID 0 is the physical GPU addresses as used by the kernel.
499 * VMIDs 1-15 are used for userspace clients and are handled
500 * by the amdgpu vm/hsa code.
504 * gmc_v8_0_gart_flush_gpu_tlb - gart tlb flush callback
506 * @adev: amdgpu_device pointer
507 * @vmid: vm instance to flush
509 * Flush the TLB for the requested page table (CIK).
511 static void gmc_v8_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
514 /* flush hdp cache */
515 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
517 /* bits 0-15 are the VM contexts0-15 */
518 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
522 * gmc_v8_0_gart_set_pte_pde - update the page tables using MMIO
524 * @adev: amdgpu_device pointer
525 * @cpu_pt_addr: cpu address of the page table
526 * @gpu_page_idx: entry in the page table to update
527 * @addr: dst addr to write into pte/pde
528 * @flags: access flags
530 * Update the page tables using the CPU.
532 static int gmc_v8_0_gart_set_pte_pde(struct amdgpu_device *adev,
534 uint32_t gpu_page_idx,
538 void __iomem *ptr = (void *)cpu_pt_addr;
544 * 39:12 4k physical page base address
555 * 63:59 block fragment size
557 * 39:1 physical base address of PTE
558 * bits 5:1 must be 0.
561 value = addr & 0x000000FFFFFFF000ULL;
563 writeq(value, ptr + (gpu_page_idx * 8));
569 * gmc_v8_0_set_fault_enable_default - update VM fault handling
571 * @adev: amdgpu_device pointer
572 * @value: true redirects VM faults to the default page
574 static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev,
579 tmp = RREG32(mmVM_CONTEXT1_CNTL);
580 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
581 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
582 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
583 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
584 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
585 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
586 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
587 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
588 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
589 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
590 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
591 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
592 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
593 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
594 WREG32(mmVM_CONTEXT1_CNTL, tmp);
598 * gmc_v8_0_gart_enable - gart enable
600 * @adev: amdgpu_device pointer
602 * This sets up the TLBs, programs the page tables for VMID0,
603 * sets up the hw for VMIDs 1-15 which are allocated on
604 * demand, and sets up the global locations for the LDS, GDS,
605 * and GPUVM for FSA64 clients (CIK).
606 * Returns 0 for success, errors for failure.
608 static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
613 if (adev->gart.robj == NULL) {
614 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
617 r = amdgpu_gart_table_vram_pin(adev);
620 /* Setup TLB control */
621 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
622 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
623 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
624 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
625 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
626 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
627 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
629 tmp = RREG32(mmVM_L2_CNTL);
630 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
631 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
632 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
633 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
634 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
635 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
636 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
637 WREG32(mmVM_L2_CNTL, tmp);
638 tmp = RREG32(mmVM_L2_CNTL2);
639 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
640 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
641 WREG32(mmVM_L2_CNTL2, tmp);
642 tmp = RREG32(mmVM_L2_CNTL3);
643 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
644 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 4);
645 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 4);
646 WREG32(mmVM_L2_CNTL3, tmp);
647 /* XXX: set to enable PTE/PDE in system memory */
648 tmp = RREG32(mmVM_L2_CNTL4);
649 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0);
650 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0);
651 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0);
652 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0);
653 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0);
654 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0);
655 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0);
656 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0);
657 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0);
658 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0);
659 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0);
660 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0);
661 WREG32(mmVM_L2_CNTL4, tmp);
663 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12);
664 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12);
665 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
666 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
667 (u32)(adev->dummy_page.addr >> 12));
668 WREG32(mmVM_CONTEXT0_CNTL2, 0);
669 tmp = RREG32(mmVM_CONTEXT0_CNTL);
670 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
671 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
672 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
673 WREG32(mmVM_CONTEXT0_CNTL, tmp);
675 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0);
676 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0);
677 WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0);
679 /* empty context1-15 */
680 /* FIXME start with 4G, once using 2 level pt switch to full
683 /* set vm size, must be a multiple of 4 */
684 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
685 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
686 for (i = 1; i < 16; i++) {
688 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
689 adev->gart.table_addr >> 12);
691 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
692 adev->gart.table_addr >> 12);
695 /* enable context1-15 */
696 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
697 (u32)(adev->dummy_page.addr >> 12));
698 WREG32(mmVM_CONTEXT1_CNTL2, 4);
699 tmp = RREG32(mmVM_CONTEXT1_CNTL);
700 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
701 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
702 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
703 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
704 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
705 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
706 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
707 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
708 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
709 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
710 amdgpu_vm_block_size - 9);
711 WREG32(mmVM_CONTEXT1_CNTL, tmp);
712 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
713 gmc_v8_0_set_fault_enable_default(adev, false);
715 gmc_v8_0_set_fault_enable_default(adev, true);
717 gmc_v8_0_gart_flush_gpu_tlb(adev, 0);
718 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
719 (unsigned)(adev->mc.gtt_size >> 20),
720 (unsigned long long)adev->gart.table_addr);
721 adev->gart.ready = true;
725 static int gmc_v8_0_gart_init(struct amdgpu_device *adev)
729 if (adev->gart.robj) {
730 WARN(1, "R600 PCIE GART already initialized\n");
733 /* Initialize common gart structure */
734 r = amdgpu_gart_init(adev);
737 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
738 return amdgpu_gart_table_vram_alloc(adev);
742 * gmc_v8_0_gart_disable - gart disable
744 * @adev: amdgpu_device pointer
746 * This disables all VM page table (CIK).
748 static void gmc_v8_0_gart_disable(struct amdgpu_device *adev)
752 /* Disable all tables */
753 WREG32(mmVM_CONTEXT0_CNTL, 0);
754 WREG32(mmVM_CONTEXT1_CNTL, 0);
755 /* Setup TLB control */
756 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
757 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
758 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
759 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
760 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
762 tmp = RREG32(mmVM_L2_CNTL);
763 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
764 WREG32(mmVM_L2_CNTL, tmp);
765 WREG32(mmVM_L2_CNTL2, 0);
766 amdgpu_gart_table_vram_unpin(adev);
770 * gmc_v8_0_gart_fini - vm fini callback
772 * @adev: amdgpu_device pointer
774 * Tears down the driver GART/VM setup (CIK).
776 static void gmc_v8_0_gart_fini(struct amdgpu_device *adev)
778 amdgpu_gart_table_vram_free(adev);
779 amdgpu_gart_fini(adev);
784 * VMID 0 is the physical GPU addresses as used by the kernel.
785 * VMIDs 1-15 are used for userspace clients and are handled
786 * by the amdgpu vm/hsa code.
789 * gmc_v8_0_vm_init - cik vm init callback
791 * @adev: amdgpu_device pointer
793 * Inits cik specific vm parameters (number of VMs, base of vram for
795 * Returns 0 for success.
797 static int gmc_v8_0_vm_init(struct amdgpu_device *adev)
801 * VMID 0 is reserved for System
802 * amdgpu graphics/compute will use VMIDs 1-7
803 * amdkfd will use VMIDs 8-15
805 adev->vm_manager.nvm = AMDGPU_NUM_OF_VMIDS;
807 /* base offset of vram pages */
808 if (adev->flags & AMD_IS_APU) {
809 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
811 adev->vm_manager.vram_base_offset = tmp;
813 adev->vm_manager.vram_base_offset = 0;
819 * gmc_v8_0_vm_fini - cik vm fini callback
821 * @adev: amdgpu_device pointer
823 * Tear down any asic specific VM setup (CIK).
825 static void gmc_v8_0_vm_fini(struct amdgpu_device *adev)
830 * gmc_v8_0_vm_decode_fault - print human readable fault info
832 * @adev: amdgpu_device pointer
833 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
834 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
836 * Print human readable fault information (CIK).
838 static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev,
839 u32 status, u32 addr, u32 mc_client)
842 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
843 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
845 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
846 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
848 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
851 printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
852 protections, vmid, addr,
853 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
855 "write" : "read", block, mc_client, mc_id);
858 static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type)
860 switch (mc_seq_vram_type) {
861 case MC_SEQ_MISC0__MT__GDDR1:
862 return AMDGPU_VRAM_TYPE_GDDR1;
863 case MC_SEQ_MISC0__MT__DDR2:
864 return AMDGPU_VRAM_TYPE_DDR2;
865 case MC_SEQ_MISC0__MT__GDDR3:
866 return AMDGPU_VRAM_TYPE_GDDR3;
867 case MC_SEQ_MISC0__MT__GDDR4:
868 return AMDGPU_VRAM_TYPE_GDDR4;
869 case MC_SEQ_MISC0__MT__GDDR5:
870 return AMDGPU_VRAM_TYPE_GDDR5;
871 case MC_SEQ_MISC0__MT__HBM:
872 return AMDGPU_VRAM_TYPE_HBM;
873 case MC_SEQ_MISC0__MT__DDR3:
874 return AMDGPU_VRAM_TYPE_DDR3;
876 return AMDGPU_VRAM_TYPE_UNKNOWN;
880 static int gmc_v8_0_early_init(void *handle)
882 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
884 gmc_v8_0_set_gart_funcs(adev);
885 gmc_v8_0_set_irq_funcs(adev);
887 if (adev->flags & AMD_IS_APU) {
888 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
890 u32 tmp = RREG32(mmMC_SEQ_MISC0);
891 tmp &= MC_SEQ_MISC0__MT__MASK;
892 adev->mc.vram_type = gmc_v8_0_convert_vram_type(tmp);
898 static int gmc_v8_0_late_init(void *handle)
900 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
902 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
905 static int gmc_v8_0_sw_init(void *handle)
909 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
911 r = amdgpu_gem_init(adev);
915 r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault);
919 r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault);
923 /* Adjust VM size here.
924 * Currently set to 4GB ((1 << 20) 4k pages).
925 * Max GPUVM size for cayman and SI is 40 bits.
927 adev->vm_manager.max_pfn = amdgpu_vm_size << 18;
929 /* Set the internal MC address mask
930 * This is the max address of the GPU's
931 * internal address space.
933 adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
935 /* set DMA mask + need_dma32 flags.
936 * PCIE - can handle 40-bits.
937 * IGP - can handle 40-bits
938 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
940 adev->need_dma32 = false;
941 dma_bits = adev->need_dma32 ? 32 : 40;
942 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
944 adev->need_dma32 = true;
946 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
948 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
950 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
951 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n");
954 r = gmc_v8_0_init_microcode(adev);
956 DRM_ERROR("Failed to load mc firmware!\n");
960 r = gmc_v8_0_mc_init(adev);
965 r = amdgpu_bo_init(adev);
969 r = gmc_v8_0_gart_init(adev);
973 if (!adev->vm_manager.enabled) {
974 r = gmc_v8_0_vm_init(adev);
976 dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
979 adev->vm_manager.enabled = true;
985 static int gmc_v8_0_sw_fini(void *handle)
987 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
989 if (adev->vm_manager.enabled) {
990 amdgpu_vm_manager_fini(adev);
991 gmc_v8_0_vm_fini(adev);
992 adev->vm_manager.enabled = false;
994 gmc_v8_0_gart_fini(adev);
995 amdgpu_gem_fini(adev);
996 amdgpu_bo_fini(adev);
1001 static int gmc_v8_0_hw_init(void *handle)
1004 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1006 gmc_v8_0_init_golden_registers(adev);
1008 gmc_v8_0_mc_program(adev);
1010 if (!(adev->flags & AMD_IS_APU)) {
1011 r = gmc_v8_0_mc_load_microcode(adev);
1013 DRM_ERROR("Failed to load MC firmware!\n");
1018 r = gmc_v8_0_gart_enable(adev);
1025 static int gmc_v8_0_hw_fini(void *handle)
1027 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1029 amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
1030 gmc_v8_0_gart_disable(adev);
1035 static int gmc_v8_0_suspend(void *handle)
1037 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1039 if (adev->vm_manager.enabled) {
1040 gmc_v8_0_vm_fini(adev);
1041 adev->vm_manager.enabled = false;
1043 gmc_v8_0_hw_fini(adev);
1048 static int gmc_v8_0_resume(void *handle)
1051 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1053 r = gmc_v8_0_hw_init(adev);
1057 if (!adev->vm_manager.enabled) {
1058 r = gmc_v8_0_vm_init(adev);
1060 dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
1063 adev->vm_manager.enabled = true;
1069 static bool gmc_v8_0_is_idle(void *handle)
1071 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1072 u32 tmp = RREG32(mmSRBM_STATUS);
1074 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1075 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1081 static int gmc_v8_0_wait_for_idle(void *handle)
1085 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1087 for (i = 0; i < adev->usec_timeout; i++) {
1088 /* read MC_STATUS */
1089 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1090 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1091 SRBM_STATUS__MCC_BUSY_MASK |
1092 SRBM_STATUS__MCD_BUSY_MASK |
1093 SRBM_STATUS__VMC_BUSY_MASK |
1094 SRBM_STATUS__VMC1_BUSY_MASK);
1103 static void gmc_v8_0_print_status(void *handle)
1106 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1108 dev_info(adev->dev, "GMC 8.x registers\n");
1109 dev_info(adev->dev, " SRBM_STATUS=0x%08X\n",
1110 RREG32(mmSRBM_STATUS));
1111 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
1112 RREG32(mmSRBM_STATUS2));
1114 dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1115 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR));
1116 dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1117 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS));
1118 dev_info(adev->dev, " MC_VM_MX_L1_TLB_CNTL=0x%08X\n",
1119 RREG32(mmMC_VM_MX_L1_TLB_CNTL));
1120 dev_info(adev->dev, " VM_L2_CNTL=0x%08X\n",
1121 RREG32(mmVM_L2_CNTL));
1122 dev_info(adev->dev, " VM_L2_CNTL2=0x%08X\n",
1123 RREG32(mmVM_L2_CNTL2));
1124 dev_info(adev->dev, " VM_L2_CNTL3=0x%08X\n",
1125 RREG32(mmVM_L2_CNTL3));
1126 dev_info(adev->dev, " VM_L2_CNTL4=0x%08X\n",
1127 RREG32(mmVM_L2_CNTL4));
1128 dev_info(adev->dev, " VM_CONTEXT0_PAGE_TABLE_START_ADDR=0x%08X\n",
1129 RREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR));
1130 dev_info(adev->dev, " VM_CONTEXT0_PAGE_TABLE_END_ADDR=0x%08X\n",
1131 RREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR));
1132 dev_info(adev->dev, " VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n",
1133 RREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR));
1134 dev_info(adev->dev, " VM_CONTEXT0_CNTL2=0x%08X\n",
1135 RREG32(mmVM_CONTEXT0_CNTL2));
1136 dev_info(adev->dev, " VM_CONTEXT0_CNTL=0x%08X\n",
1137 RREG32(mmVM_CONTEXT0_CNTL));
1138 dev_info(adev->dev, " VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR=0x%08X\n",
1139 RREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR));
1140 dev_info(adev->dev, " VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR=0x%08X\n",
1141 RREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR));
1142 dev_info(adev->dev, " mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET=0x%08X\n",
1143 RREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET));
1144 dev_info(adev->dev, " VM_CONTEXT1_PAGE_TABLE_START_ADDR=0x%08X\n",
1145 RREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR));
1146 dev_info(adev->dev, " VM_CONTEXT1_PAGE_TABLE_END_ADDR=0x%08X\n",
1147 RREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR));
1148 dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n",
1149 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR));
1150 dev_info(adev->dev, " VM_CONTEXT1_CNTL2=0x%08X\n",
1151 RREG32(mmVM_CONTEXT1_CNTL2));
1152 dev_info(adev->dev, " VM_CONTEXT1_CNTL=0x%08X\n",
1153 RREG32(mmVM_CONTEXT1_CNTL));
1154 for (i = 0; i < 16; i++) {
1156 dev_info(adev->dev, " VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n",
1157 i, RREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i));
1159 dev_info(adev->dev, " VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n",
1160 i, RREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8));
1162 dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_LOW_ADDR=0x%08X\n",
1163 RREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR));
1164 dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_HIGH_ADDR=0x%08X\n",
1165 RREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR));
1166 dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR=0x%08X\n",
1167 RREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR));
1168 dev_info(adev->dev, " MC_VM_FB_LOCATION=0x%08X\n",
1169 RREG32(mmMC_VM_FB_LOCATION));
1170 dev_info(adev->dev, " MC_VM_AGP_BASE=0x%08X\n",
1171 RREG32(mmMC_VM_AGP_BASE));
1172 dev_info(adev->dev, " MC_VM_AGP_TOP=0x%08X\n",
1173 RREG32(mmMC_VM_AGP_TOP));
1174 dev_info(adev->dev, " MC_VM_AGP_BOT=0x%08X\n",
1175 RREG32(mmMC_VM_AGP_BOT));
1177 dev_info(adev->dev, " HDP_REG_COHERENCY_FLUSH_CNTL=0x%08X\n",
1178 RREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL));
1179 dev_info(adev->dev, " HDP_NONSURFACE_BASE=0x%08X\n",
1180 RREG32(mmHDP_NONSURFACE_BASE));
1181 dev_info(adev->dev, " HDP_NONSURFACE_INFO=0x%08X\n",
1182 RREG32(mmHDP_NONSURFACE_INFO));
1183 dev_info(adev->dev, " HDP_NONSURFACE_SIZE=0x%08X\n",
1184 RREG32(mmHDP_NONSURFACE_SIZE));
1185 dev_info(adev->dev, " HDP_MISC_CNTL=0x%08X\n",
1186 RREG32(mmHDP_MISC_CNTL));
1187 dev_info(adev->dev, " HDP_HOST_PATH_CNTL=0x%08X\n",
1188 RREG32(mmHDP_HOST_PATH_CNTL));
1190 for (i = 0, j = 0; i < 32; i++, j += 0x6) {
1191 dev_info(adev->dev, " %d:\n", i);
1192 dev_info(adev->dev, " 0x%04X=0x%08X\n",
1193 0xb05 + j, RREG32(0xb05 + j));
1194 dev_info(adev->dev, " 0x%04X=0x%08X\n",
1195 0xb06 + j, RREG32(0xb06 + j));
1196 dev_info(adev->dev, " 0x%04X=0x%08X\n",
1197 0xb07 + j, RREG32(0xb07 + j));
1198 dev_info(adev->dev, " 0x%04X=0x%08X\n",
1199 0xb08 + j, RREG32(0xb08 + j));
1200 dev_info(adev->dev, " 0x%04X=0x%08X\n",
1201 0xb09 + j, RREG32(0xb09 + j));
1204 dev_info(adev->dev, " BIF_FB_EN=0x%08X\n",
1205 RREG32(mmBIF_FB_EN));
1208 static int gmc_v8_0_soft_reset(void *handle)
1210 struct amdgpu_mode_mc_save save;
1211 u32 srbm_soft_reset = 0;
1212 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1213 u32 tmp = RREG32(mmSRBM_STATUS);
1215 if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1216 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1217 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1219 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1220 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1221 if (!(adev->flags & AMD_IS_APU))
1222 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1223 SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1226 if (srbm_soft_reset) {
1227 gmc_v8_0_print_status((void *)adev);
1229 gmc_v8_0_mc_stop(adev, &save);
1230 if (gmc_v8_0_wait_for_idle(adev)) {
1231 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1235 tmp = RREG32(mmSRBM_SOFT_RESET);
1236 tmp |= srbm_soft_reset;
1237 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1238 WREG32(mmSRBM_SOFT_RESET, tmp);
1239 tmp = RREG32(mmSRBM_SOFT_RESET);
1243 tmp &= ~srbm_soft_reset;
1244 WREG32(mmSRBM_SOFT_RESET, tmp);
1245 tmp = RREG32(mmSRBM_SOFT_RESET);
1247 /* Wait a little for things to settle down */
1250 gmc_v8_0_mc_resume(adev, &save);
1253 gmc_v8_0_print_status((void *)adev);
1259 static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1260 struct amdgpu_irq_src *src,
1262 enum amdgpu_interrupt_state state)
1265 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1266 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1267 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1268 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1269 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1270 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1271 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1274 case AMDGPU_IRQ_STATE_DISABLE:
1275 /* system context */
1276 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1278 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1280 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1282 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1284 case AMDGPU_IRQ_STATE_ENABLE:
1285 /* system context */
1286 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1288 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1290 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1292 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1301 static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,
1302 struct amdgpu_irq_src *source,
1303 struct amdgpu_iv_entry *entry)
1305 u32 addr, status, mc_client;
1307 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1308 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1309 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1310 /* reset addr and status */
1311 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1313 if (!addr && !status)
1316 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1317 gmc_v8_0_set_fault_enable_default(adev, false);
1319 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1320 entry->src_id, entry->src_data);
1321 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1323 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1325 gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client);
1330 static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev,
1336 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1337 data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1338 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1340 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1341 data |= MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1342 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1344 data = RREG32(mmMC_HUB_MISC_VM_CG);
1345 data |= MC_HUB_MISC_VM_CG__ENABLE_MASK;
1346 WREG32(mmMC_HUB_MISC_VM_CG, data);
1348 data = RREG32(mmMC_XPB_CLK_GAT);
1349 data |= MC_XPB_CLK_GAT__ENABLE_MASK;
1350 WREG32(mmMC_XPB_CLK_GAT, data);
1352 data = RREG32(mmATC_MISC_CG);
1353 data |= ATC_MISC_CG__ENABLE_MASK;
1354 WREG32(mmATC_MISC_CG, data);
1356 data = RREG32(mmMC_CITF_MISC_WR_CG);
1357 data |= MC_CITF_MISC_WR_CG__ENABLE_MASK;
1358 WREG32(mmMC_CITF_MISC_WR_CG, data);
1360 data = RREG32(mmMC_CITF_MISC_RD_CG);
1361 data |= MC_CITF_MISC_RD_CG__ENABLE_MASK;
1362 WREG32(mmMC_CITF_MISC_RD_CG, data);
1364 data = RREG32(mmMC_CITF_MISC_VM_CG);
1365 data |= MC_CITF_MISC_VM_CG__ENABLE_MASK;
1366 WREG32(mmMC_CITF_MISC_VM_CG, data);
1368 data = RREG32(mmVM_L2_CG);
1369 data |= VM_L2_CG__ENABLE_MASK;
1370 WREG32(mmVM_L2_CG, data);
1372 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1373 data &= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1374 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1376 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1377 data &= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1378 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1380 data = RREG32(mmMC_HUB_MISC_VM_CG);
1381 data &= ~MC_HUB_MISC_VM_CG__ENABLE_MASK;
1382 WREG32(mmMC_HUB_MISC_VM_CG, data);
1384 data = RREG32(mmMC_XPB_CLK_GAT);
1385 data &= ~MC_XPB_CLK_GAT__ENABLE_MASK;
1386 WREG32(mmMC_XPB_CLK_GAT, data);
1388 data = RREG32(mmATC_MISC_CG);
1389 data &= ~ATC_MISC_CG__ENABLE_MASK;
1390 WREG32(mmATC_MISC_CG, data);
1392 data = RREG32(mmMC_CITF_MISC_WR_CG);
1393 data &= ~MC_CITF_MISC_WR_CG__ENABLE_MASK;
1394 WREG32(mmMC_CITF_MISC_WR_CG, data);
1396 data = RREG32(mmMC_CITF_MISC_RD_CG);
1397 data &= ~MC_CITF_MISC_RD_CG__ENABLE_MASK;
1398 WREG32(mmMC_CITF_MISC_RD_CG, data);
1400 data = RREG32(mmMC_CITF_MISC_VM_CG);
1401 data &= ~MC_CITF_MISC_VM_CG__ENABLE_MASK;
1402 WREG32(mmMC_CITF_MISC_VM_CG, data);
1404 data = RREG32(mmVM_L2_CG);
1405 data &= ~VM_L2_CG__ENABLE_MASK;
1406 WREG32(mmVM_L2_CG, data);
1410 static void fiji_update_mc_light_sleep(struct amdgpu_device *adev,
1416 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1417 data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1418 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1420 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1421 data |= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1422 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1424 data = RREG32(mmMC_HUB_MISC_VM_CG);
1425 data |= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1426 WREG32(mmMC_HUB_MISC_VM_CG, data);
1428 data = RREG32(mmMC_XPB_CLK_GAT);
1429 data |= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1430 WREG32(mmMC_XPB_CLK_GAT, data);
1432 data = RREG32(mmATC_MISC_CG);
1433 data |= ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1434 WREG32(mmATC_MISC_CG, data);
1436 data = RREG32(mmMC_CITF_MISC_WR_CG);
1437 data |= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1438 WREG32(mmMC_CITF_MISC_WR_CG, data);
1440 data = RREG32(mmMC_CITF_MISC_RD_CG);
1441 data |= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1442 WREG32(mmMC_CITF_MISC_RD_CG, data);
1444 data = RREG32(mmMC_CITF_MISC_VM_CG);
1445 data |= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1446 WREG32(mmMC_CITF_MISC_VM_CG, data);
1448 data = RREG32(mmVM_L2_CG);
1449 data |= VM_L2_CG__MEM_LS_ENABLE_MASK;
1450 WREG32(mmVM_L2_CG, data);
1452 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1453 data &= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1454 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1456 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1457 data &= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1458 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1460 data = RREG32(mmMC_HUB_MISC_VM_CG);
1461 data &= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1462 WREG32(mmMC_HUB_MISC_VM_CG, data);
1464 data = RREG32(mmMC_XPB_CLK_GAT);
1465 data &= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1466 WREG32(mmMC_XPB_CLK_GAT, data);
1468 data = RREG32(mmATC_MISC_CG);
1469 data &= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1470 WREG32(mmATC_MISC_CG, data);
1472 data = RREG32(mmMC_CITF_MISC_WR_CG);
1473 data &= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1474 WREG32(mmMC_CITF_MISC_WR_CG, data);
1476 data = RREG32(mmMC_CITF_MISC_RD_CG);
1477 data &= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1478 WREG32(mmMC_CITF_MISC_RD_CG, data);
1480 data = RREG32(mmMC_CITF_MISC_VM_CG);
1481 data &= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1482 WREG32(mmMC_CITF_MISC_VM_CG, data);
1484 data = RREG32(mmVM_L2_CG);
1485 data &= ~VM_L2_CG__MEM_LS_ENABLE_MASK;
1486 WREG32(mmVM_L2_CG, data);
1490 static int gmc_v8_0_set_clockgating_state(void *handle,
1491 enum amd_clockgating_state state)
1493 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1495 switch (adev->asic_type) {
1497 fiji_update_mc_medium_grain_clock_gating(adev,
1498 state == AMD_CG_STATE_GATE ? true : false);
1499 fiji_update_mc_light_sleep(adev,
1500 state == AMD_CG_STATE_GATE ? true : false);
1508 static int gmc_v8_0_set_powergating_state(void *handle,
1509 enum amd_powergating_state state)
1514 const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
1515 .early_init = gmc_v8_0_early_init,
1516 .late_init = gmc_v8_0_late_init,
1517 .sw_init = gmc_v8_0_sw_init,
1518 .sw_fini = gmc_v8_0_sw_fini,
1519 .hw_init = gmc_v8_0_hw_init,
1520 .hw_fini = gmc_v8_0_hw_fini,
1521 .suspend = gmc_v8_0_suspend,
1522 .resume = gmc_v8_0_resume,
1523 .is_idle = gmc_v8_0_is_idle,
1524 .wait_for_idle = gmc_v8_0_wait_for_idle,
1525 .soft_reset = gmc_v8_0_soft_reset,
1526 .print_status = gmc_v8_0_print_status,
1527 .set_clockgating_state = gmc_v8_0_set_clockgating_state,
1528 .set_powergating_state = gmc_v8_0_set_powergating_state,
1531 static const struct amdgpu_gart_funcs gmc_v8_0_gart_funcs = {
1532 .flush_gpu_tlb = gmc_v8_0_gart_flush_gpu_tlb,
1533 .set_pte_pde = gmc_v8_0_gart_set_pte_pde,
1536 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = {
1537 .set = gmc_v8_0_vm_fault_interrupt_state,
1538 .process = gmc_v8_0_process_interrupt,
1541 static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev)
1543 if (adev->gart.gart_funcs == NULL)
1544 adev->gart.gart_funcs = &gmc_v8_0_gart_funcs;
1547 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev)
1549 adev->mc.vm_fault.num_types = 1;
1550 adev->mc.vm_fault.funcs = &gmc_v8_0_irq_funcs;