drivers/gpu/drm/amd/amdgpu/si_dpm.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "drmP.h"
  25 #include "amdgpu.h"
  26 #include "amdgpu_pm.h"
  27 #include "amdgpu_dpm.h"
  28 #include "amdgpu_atombios.h"
  29 #include "si/sid.h"
  30 #include "r600_dpm.h"
  31 #include "si_dpm.h"
  32 #include "atom.h"
  33 #include "../include/pptable.h"
  34 #include <linux/math64.h>
  35 #include <linux/seq_file.h>
  36 #include <linux/firmware.h>
  37
  38 #define MC_CG_ARB_FREQ_F0           0x0a
  39 #define MC_CG_ARB_FREQ_F1           0x0b
  40 #define MC_CG_ARB_FREQ_F2           0x0c
  41 #define MC_CG_ARB_FREQ_F3           0x0d
  42
  43 #define SMC_RAM_END                 0x20000
  44
  45 #define SCLK_MIN_DEEPSLEEP_FREQ     1350
  46
  47
  48 /* sizeof(ATOM_PPLIB_EXTENDEDHEADER) */
  49 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2 12
  50 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3 14
  51 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4 16
  52 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5 18
  53 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6 20
  54 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7 22
  55
  56 #define BIOS_SCRATCH_4                                    0x5cd
  57
  58 MODULE_FIRMWARE("radeon/tahiti_smc.bin");
  59 MODULE_FIRMWARE("radeon/tahiti_k_smc.bin");
  60 MODULE_FIRMWARE("radeon/pitcairn_smc.bin");
  61 MODULE_FIRMWARE("radeon/pitcairn_k_smc.bin");
  62 MODULE_FIRMWARE("radeon/verde_smc.bin");
  63 MODULE_FIRMWARE("radeon/verde_k_smc.bin");
  64 MODULE_FIRMWARE("radeon/oland_smc.bin");
  65 MODULE_FIRMWARE("radeon/oland_k_smc.bin");
  66 MODULE_FIRMWARE("radeon/hainan_smc.bin");
  67 MODULE_FIRMWARE("radeon/hainan_k_smc.bin");
  68
  69 union power_info {
  70         struct _ATOM_POWERPLAY_INFO info;
  71         struct _ATOM_POWERPLAY_INFO_V2 info_2;
  72         struct _ATOM_POWERPLAY_INFO_V3 info_3;
  73         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
  74         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
  75         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
  76         struct _ATOM_PPLIB_POWERPLAYTABLE4 pplib4;
  77         struct _ATOM_PPLIB_POWERPLAYTABLE5 pplib5;
  78 };
  79
  80 union fan_info {
  81         struct _ATOM_PPLIB_FANTABLE fan;
  82         struct _ATOM_PPLIB_FANTABLE2 fan2;
  83         struct _ATOM_PPLIB_FANTABLE3 fan3;
  84 };
  85
  86 union pplib_clock_info {
  87         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
  88         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
  89         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
  90         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
  91         struct _ATOM_PPLIB_SI_CLOCK_INFO si;
  92 };
  93
  94 static const u32 r600_utc[R600_PM_NUMBER_OF_TC] =
  95 {
  96         R600_UTC_DFLT_00,
  97         R600_UTC_DFLT_01,
  98         R600_UTC_DFLT_02,
  99         R600_UTC_DFLT_03,
 100         R600_UTC_DFLT_04,
 101         R600_UTC_DFLT_05,
 102         R600_UTC_DFLT_06,
 103         R600_UTC_DFLT_07,
 104         R600_UTC_DFLT_08,
 105         R600_UTC_DFLT_09,
 106         R600_UTC_DFLT_10,
 107         R600_UTC_DFLT_11,
 108         R600_UTC_DFLT_12,
 109         R600_UTC_DFLT_13,
 110         R600_UTC_DFLT_14,
 111 };
 112
 113 static const u32 r600_dtc[R600_PM_NUMBER_OF_TC] =
 114 {
 115         R600_DTC_DFLT_00,
 116         R600_DTC_DFLT_01,
 117         R600_DTC_DFLT_02,
 118         R600_DTC_DFLT_03,
 119         R600_DTC_DFLT_04,
 120         R600_DTC_DFLT_05,
 121         R600_DTC_DFLT_06,
 122         R600_DTC_DFLT_07,
 123         R600_DTC_DFLT_08,
 124         R600_DTC_DFLT_09,
 125         R600_DTC_DFLT_10,
 126         R600_DTC_DFLT_11,
 127         R600_DTC_DFLT_12,
 128         R600_DTC_DFLT_13,
 129         R600_DTC_DFLT_14,
 130 };
 131
 132 static const struct si_cac_config_reg cac_weights_tahiti[] =
 133 {
 134         { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
 135         { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 136         { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
 137         { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
 138         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 139         { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 140         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 141         { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 142         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 143         { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
 144         { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 145         { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
 146         { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
 147         { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
 148         { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
 149         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 150         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 151         { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
 152         { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 153         { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
 154         { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
 155         { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
 156         { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 157         { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 158         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 159         { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 160         { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 161         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 162         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 163         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 164         { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
 165         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 166         { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 167         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 168         { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 169         { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 170         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 171         { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
 172         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 173         { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
 174         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 175         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 176         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 177         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 178         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 179         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 180         { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 181         { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 182         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 183         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 184         { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 185         { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 186         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 187         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 188         { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 189         { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 190         { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 191         { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 192         { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 193         { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
 194         { 0xFFFFFFFF }
 195 };
 196
 197 static const struct si_cac_config_reg lcac_tahiti[] =
 198 {
 199         { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 200         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 201         { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 202         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 203         { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 204         { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 205         { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 206         { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 207         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 208         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 209         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 210         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 211         { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 212         { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 213         { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 214         { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 215         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 216         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 217         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 218         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 219         { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 220         { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 221         { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 222         { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 223         { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 224         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 225         { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 226         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 227         { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 228         { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 229         { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 230         { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 231         { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 232         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 233         { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 234         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 235         { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 236         { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 237         { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 238         { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 239         { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 240         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 241         { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 242         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 243         { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 244         { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 245         { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 246         { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 247         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 248         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 249         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 250         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 251         { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 252         { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 253         { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 254         { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 255         { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 256         { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 257         { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 258         { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 259         { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 260         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 261         { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 262         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 263         { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 264         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 265         { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 266         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 267         { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 268         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 269         { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 270         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 271         { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
 272         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 273         { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 274         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 275         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 276         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 277         { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 278         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 279         { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 280         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 281         { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 282         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 283         { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 284         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 285         { 0xFFFFFFFF }
 286
 287 };
 288
 289 static const struct si_cac_config_reg cac_override_tahiti[] =
 290 {
 291         { 0xFFFFFFFF }
 292 };
 293
 294 static const struct si_powertune_data powertune_data_tahiti =
 295 {
 296         ((1 << 16) | 27027),
 297         6,
 298         0,
 299         4,
 300         95,
 301         {
 302                 0UL,
 303                 0UL,
 304                 4521550UL,
 305                 309631529UL,
 306                 -1270850L,
 307                 4513710L,
 308                 40
 309         },
 310         595000000UL,
 311         12,
 312         {
 313                 0,
 314                 0,
 315                 0,
 316                 0,
 317                 0,
 318                 0,
 319                 0,
 320                 0
 321         },
 322         true
 323 };
 324
 325 static const struct si_dte_data dte_data_tahiti =
 326 {
 327         { 1159409, 0, 0, 0, 0 },
 328         { 777, 0, 0, 0, 0 },
 329         2,
 330         54000,
 331         127000,
 332         25,
 333         2,
 334         10,
 335         13,
 336         { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
 337         { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
 338         { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
 339         85,
 340         false
 341 };
 342
 343 #if 0
 344 static const struct si_dte_data dte_data_tahiti_le =
 345 {
 346         { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 },
 347         { 0x7D, 0x7D, 0x4E4, 0xB00, 0 },
 348         0x5,
 349         0xAFC8,
 350         0x64,
 351         0x32,
 352         1,
 353         0,
 354         0x10,
 355         { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 },
 356         { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 },
 357         { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 },
 358         85,
 359         true
 360 };
 361 #endif
 362
 363 static const struct si_dte_data dte_data_tahiti_pro =
 364 {
 365         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 366         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 367         5,
 368         45000,
 369         100,
 370         0xA,
 371         1,
 372         0,
 373         0x10,
 374         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 375         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 376         { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 377         90,
 378         true
 379 };
 380
 381 static const struct si_dte_data dte_data_new_zealand =
 382 {
 383         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
 384         { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
 385         0x5,
 386         0xAFC8,
 387         0x69,
 388         0x32,
 389         1,
 390         0,
 391         0x10,
 392         { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
 393         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 394         { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
 395         85,
 396         true
 397 };
 398
 399 static const struct si_dte_data dte_data_aruba_pro =
 400 {
 401         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 402         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 403         5,
 404         45000,
 405         100,
 406         0xA,
 407         1,
 408         0,
 409         0x10,
 410         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 411         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 412         { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 413         90,
 414         true
 415 };
 416
 417 static const struct si_dte_data dte_data_malta =
 418 {
 419         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 420         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 421         5,
 422         45000,
 423         100,
 424         0xA,
 425         1,
 426         0,
 427         0x10,
 428         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 429         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 430         { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 431         90,
 432         true
 433 };
 434
 435 static const struct si_cac_config_reg cac_weights_pitcairn[] =
 436 {
 437         { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
 438         { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 439         { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 440         { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
 441         { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
 442         { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 443         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 444         { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
 445         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 446         { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
 447         { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
 448         { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
 449         { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
 450         { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
 451         { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 452         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 453         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 454         { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
 455         { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
 456         { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
 457         { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
 458         { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
 459         { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
 460         { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 461         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 462         { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
 463         { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
 464         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 465         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 466         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 467         { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
 468         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 469         { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
 470         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 471         { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
 472         { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
 473         { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
 474         { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 475         { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
 476         { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 477         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 478         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 479         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 480         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 481         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 482         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 483         { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 484         { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 485         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 486         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 487         { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 488         { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 489         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 490         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 491         { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 492         { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 493         { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 494         { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 495         { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 496         { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
 497         { 0xFFFFFFFF }
 498 };
 499
 500 static const struct si_cac_config_reg lcac_pitcairn[] =
 501 {
 502         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 503         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 504         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 505         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 506         { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 507         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 508         { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 509         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 510         { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 511         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 512         { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 513         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 514         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 515         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 516         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 517         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 518         { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 519         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 520         { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 521         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 522         { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 523         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 524         { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 525         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 526         { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 527         { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 528         { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 529         { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 530         { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 531         { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 532         { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 533         { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 534         { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 535         { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 536         { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 537         { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 538         { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 539         { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 540         { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 541         { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 542         { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 543         { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 544         { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 545         { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 546         { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 547         { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 548         { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 549         { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 550         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 551         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 552         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 553         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 554         { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 555         { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 556         { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 557         { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 558         { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 559         { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 560         { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 561         { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 562         { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 563         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 564         { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 565         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 566         { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 567         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 568         { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 569         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 570         { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 571         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 572         { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 573         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 574         { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 575         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 576         { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 577         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 578         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 579         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 580         { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 581         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 582         { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 583         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 584         { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 585         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 586         { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 587         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 588         { 0xFFFFFFFF }
 589 };
 590
 591 static const struct si_cac_config_reg cac_override_pitcairn[] =
 592 {
 593     { 0xFFFFFFFF }
 594 };
 595
 596 static const struct si_powertune_data powertune_data_pitcairn =
 597 {
 598         ((1 << 16) | 27027),
 599         5,
 600         0,
 601         6,
 602         100,
 603         {
 604                 51600000UL,
 605                 1800000UL,
 606                 7194395UL,
 607                 309631529UL,
 608                 -1270850L,
 609                 4513710L,
 610                 100
 611         },
 612         117830498UL,
 613         12,
 614         {
 615                 0,
 616                 0,
 617                 0,
 618                 0,
 619                 0,
 620                 0,
 621                 0,
 622                 0
 623         },
 624         true
 625 };
 626
 627 static const struct si_dte_data dte_data_pitcairn =
 628 {
 629         { 0, 0, 0, 0, 0 },
 630         { 0, 0, 0, 0, 0 },
 631         0,
 632         0,
 633         0,
 634         0,
 635         0,
 636         0,
 637         0,
 638         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 639         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 640         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 641         0,
 642         false
 643 };
 644
 645 static const struct si_dte_data dte_data_curacao_xt =
 646 {
 647         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 648         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 649         5,
 650         45000,
 651         100,
 652         0xA,
 653         1,
 654         0,
 655         0x10,
 656         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 657         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 658         { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 659         90,
 660         true
 661 };
 662
 663 static const struct si_dte_data dte_data_curacao_pro =
 664 {
 665         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 666         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 667         5,
 668         45000,
 669         100,
 670         0xA,
 671         1,
 672         0,
 673         0x10,
 674         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 675         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 676         { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 677         90,
 678         true
 679 };
 680
 681 static const struct si_dte_data dte_data_neptune_xt =
 682 {
 683         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 684         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 685         5,
 686         45000,
 687         100,
 688         0xA,
 689         1,
 690         0,
 691         0x10,
 692         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 693         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 694         { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 695         90,
 696         true
 697 };
 698
 699 static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
 700 {
 701         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 702         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 703         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 704         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 705         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 706         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 707         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 708         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 709         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 710         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 711         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 712         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 713         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 714         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 715         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 716         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 717         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 718         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 719         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 720         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 721         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 722         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 723         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 724         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 725         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 726         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 727         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 728         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 729         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 730         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 731         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 732         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 733         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 734         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 735         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 736         { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
 737         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 738         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 739         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 740         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 741         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 742         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 743         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 744         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 745         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 746         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 747         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 748         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 749         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 750         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 751         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 752         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 753         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 754         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 755         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 756         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 757         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 758         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 759         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 760         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 761         { 0xFFFFFFFF }
 762 };
 763
 764 static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
 765 {
 766         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 767         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 768         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 769         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 770         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 771         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 772         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 773         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 774         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 775         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 776         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 777         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 778         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 779         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 780         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 781         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 782         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 783         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 784         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 785         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 786         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 787         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 788         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 789         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 790         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 791         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 792         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 793         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 794         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 795         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 796         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 797         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 798         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 799         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 800         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 801         { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
 802         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 803         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 804         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 805         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 806         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 807         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 808         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 809         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 810         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 811         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 812         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 813         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 814         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 815         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 816         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 817         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 818         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 819         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 820         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 821         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 822         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 823         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 824         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 825         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 826         { 0xFFFFFFFF }
 827 };
 828
 829 static const struct si_cac_config_reg cac_weights_heathrow[] =
 830 {
 831         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 832         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 833         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 834         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 835         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 836         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 837         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 838         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 839         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 840         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 841         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 842         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 843         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 844         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 845         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 846         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 847         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 848         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 849         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 850         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 851         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 852         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 853         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 854         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 855         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 856         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 857         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 858         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 859         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 860         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 861         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 862         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 863         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 864         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 865         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 866         { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
 867         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 868         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 869         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 870         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 871         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 872         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 873         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 874         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 875         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 876         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 877         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 878         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 879         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 880         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 881         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 882         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 883         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 884         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 885         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 886         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 887         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 888         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 889         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 890         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 891         { 0xFFFFFFFF }
 892 };
 893
 894 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
 895 {
 896         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 897         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 898         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 899         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 900         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 901         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 902         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 903         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 904         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 905         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 906         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 907         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 908         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 909         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 910         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 911         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 912         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 913         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 914         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 915         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 916         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 917         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 918         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 919         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 920         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 921         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 922         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 923         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 924         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 925         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 926         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 927         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 928         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 929         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 930         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 931         { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
 932         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 933         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 934         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 935         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 936         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 937         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 938         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 939         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 940         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 941         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 942         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 943         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 944         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 945         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 946         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 947         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 948         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 949         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 950         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 951         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 952         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 953         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 954         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 955         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 956         { 0xFFFFFFFF }
 957 };
 958
 959 static const struct si_cac_config_reg cac_weights_cape_verde[] =
 960 {
 961         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 962         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 963         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 964         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 965         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 966         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 967         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 968         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 969         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 970         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 971         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 972         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 973         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 974         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 975         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 976         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 977         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 978         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 979         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 980         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 981         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 982         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 983         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 984         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 985         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 986         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 987         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 988         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 989         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 990         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 991         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 992         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 993         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 994         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 995         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 996         { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
 997         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 998         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 999         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1000         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1001         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1002         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1003         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1004         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1005         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1006         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1007         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1008         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1009         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1010         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1011         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1012         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1013         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1014         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1015         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1016         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1017         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1018         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1019         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1020         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1021         { 0xFFFFFFFF }
1022 };
1023
1024 static const struct si_cac_config_reg lcac_cape_verde[] =
1025 {
1026         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1027         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1028         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1029         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1030         { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1031         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1032         { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1033         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1034         { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1035         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1036         { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1037         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1038         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1039         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1040         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1041         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1042         { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1043         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1044         { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1045         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1046         { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1047         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1048         { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1049         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1050         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1051         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1052         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1053         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1054         { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1055         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1056         { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1057         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1058         { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1059         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1060         { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1061         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1062         { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1063         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1064         { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1065         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1066         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1067         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1068         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1069         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1070         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1071         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1072         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1073         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1074         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1075         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1076         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1077         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1078         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1079         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1080         { 0xFFFFFFFF }
1081 };
1082
1083 static const struct si_cac_config_reg cac_override_cape_verde[] =
1084 {
1085     { 0xFFFFFFFF }
1086 };
1087
1088 static const struct si_powertune_data powertune_data_cape_verde =
1089 {
1090         ((1 << 16) | 0x6993),
1091         5,
1092         0,
1093         7,
1094         105,
1095         {
1096                 0UL,
1097                 0UL,
1098                 7194395UL,
1099                 309631529UL,
1100                 -1270850L,
1101                 4513710L,
1102                 100
1103         },
1104         117830498UL,
1105         12,
1106         {
1107                 0,
1108                 0,
1109                 0,
1110                 0,
1111                 0,
1112                 0,
1113                 0,
1114                 0
1115         },
1116         true
1117 };
1118
1119 static const struct si_dte_data dte_data_cape_verde =
1120 {
1121         { 0, 0, 0, 0, 0 },
1122         { 0, 0, 0, 0, 0 },
1123         0,
1124         0,
1125         0,
1126         0,
1127         0,
1128         0,
1129         0,
1130         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1131         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1132         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1133         0,
1134         false
1135 };
1136
1137 static const struct si_dte_data dte_data_venus_xtx =
1138 {
1139         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1140         { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1141         5,
1142         55000,
1143         0x69,
1144         0xA,
1145         1,
1146         0,
1147         0x3,
1148         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1149         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1150         { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1151         90,
1152         true
1153 };
1154
1155 static const struct si_dte_data dte_data_venus_xt =
1156 {
1157         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1158         { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1159         5,
1160         55000,
1161         0x69,
1162         0xA,
1163         1,
1164         0,
1165         0x3,
1166         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1167         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1168         { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1169         90,
1170         true
1171 };
1172
1173 static const struct si_dte_data dte_data_venus_pro =
1174 {
1175         {  0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1176         { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1177         5,
1178         55000,
1179         0x69,
1180         0xA,
1181         1,
1182         0,
1183         0x3,
1184         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1185         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1186         { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1187         90,
1188         true
1189 };
1190
1191 static const struct si_cac_config_reg cac_weights_oland[] =
1192 {
1193         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1194         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1195         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1196         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1197         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1198         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1199         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1200         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1201         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1202         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1203         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1204         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1205         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1206         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1207         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1208         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1209         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1210         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1211         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1212         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1213         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1214         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1215         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1216         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1217         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1218         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1219         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1220         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1221         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1222         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1223         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1224         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1225         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1226         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1227         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1228         { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1229         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1230         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1231         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1232         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1233         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1234         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1235         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1236         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1237         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1238         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1239         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1240         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1241         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1242         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1243         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1244         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1245         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1246         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1247         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1248         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1249         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1250         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1251         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1252         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1253         { 0xFFFFFFFF }
1254 };
1255
1256 static const struct si_cac_config_reg cac_weights_mars_pro[] =
1257 {
1258         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1259         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1260         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1261         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1262         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1263         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1264         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1265         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1266         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1267         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1268         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1269         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1270         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1271         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1272         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1273         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1274         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1275         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1276         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1277         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1278         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1279         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1280         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1281         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1282         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1283         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1284         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1285         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1286         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1287         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1288         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1289         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1290         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1291         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1292         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1293         { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1294         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1295         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1296         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1297         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1298         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1299         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1300         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1301         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1302         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1303         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1304         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1305         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1306         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1307         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1308         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1309         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1310         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1311         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1312         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1313         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1314         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1315         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1316         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1317         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1318         { 0xFFFFFFFF }
1319 };
1320
1321 static const struct si_cac_config_reg cac_weights_mars_xt[] =
1322 {
1323         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1324         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1325         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1326         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1327         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1328         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1329         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1330         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1331         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1332         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1333         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1334         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1335         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1336         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1337         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1338         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1339         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1340         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1341         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1342         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1343         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1344         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1345         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1346         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1347         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1348         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1349         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1350         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1351         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1352         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1353         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1354         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1355         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1356         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1357         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1358         { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1359         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1360         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1361         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1362         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1363         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1364         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1365         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1366         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1367         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1368         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1369         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1370         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1371         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1372         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1373         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1374         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1375         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1376         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1377         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1378         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1379         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1380         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1381         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1382         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1383         { 0xFFFFFFFF }
1384 };
1385
1386 static const struct si_cac_config_reg cac_weights_oland_pro[] =
1387 {
1388         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1389         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1390         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1391         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1392         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1393         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1394         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1395         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1396         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1397         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1398         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1399         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1400         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1401         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1402         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1403         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1404         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1405         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1406         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1407         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1408         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1409         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1410         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1411         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1412         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1413         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1414         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1415         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1416         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1417         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1418         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1419         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1420         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1421         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1422         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1423         { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1424         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1425         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1426         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1427         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1428         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1429         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1430         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1431         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1432         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1433         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1434         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1435         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1436         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1437         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1438         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1439         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1440         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1441         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1442         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1443         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1444         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1445         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1446         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1447         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1448         { 0xFFFFFFFF }
1449 };
1450
1451 static const struct si_cac_config_reg cac_weights_oland_xt[] =
1452 {
1453         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1454         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1455         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1456         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1457         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1458         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1459         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1460         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1461         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1462         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1463         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1464         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1465         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1466         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1467         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1468         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1469         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1470         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1471         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1472         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1473         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1474         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1475         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1476         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1477         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1478         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1479         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1480         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1481         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1482         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1483         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1484         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1485         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1486         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1487         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1488         { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1489         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1490         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1491         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1492         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1493         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1494         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1495         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1496         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1497         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1498         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1499         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1500         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1501         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1502         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1503         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1504         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1505         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1506         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1507         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1508         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1509         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1510         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1511         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1512         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1513         { 0xFFFFFFFF }
1514 };
1515
1516 static const struct si_cac_config_reg lcac_oland[] =
1517 {
1518         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1519         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1520         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1521         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1522         { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1523         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1524         { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1525         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1526         { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1527         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1528         { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1529         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1530         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1531         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1532         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1533         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1534         { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1535         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1536         { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1537         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1538         { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1539         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1540         { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1541         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1542         { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1543         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1544         { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1545         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1546         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1547         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1548         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1549         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1550         { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1551         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1552         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1553         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1554         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1555         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1556         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1557         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1558         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1559         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1560         { 0xFFFFFFFF }
1561 };
1562
1563 static const struct si_cac_config_reg lcac_mars_pro[] =
1564 {
1565         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1566         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1567         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1568         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1569         { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1570         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1571         { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1572         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1573         { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1574         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1575         { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1576         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1577         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1578         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1579         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1580         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1581         { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1582         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1583         { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1584         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1585         { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1586         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1587         { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1588         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1589         { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1590         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1591         { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1592         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1593         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1594         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1595         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1596         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1597         { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1598         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1599         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1600         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1601         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1602         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1603         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1604         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1605         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1606         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1607         { 0xFFFFFFFF }
1608 };
1609
1610 static const struct si_cac_config_reg cac_override_oland[] =
1611 {
1612         { 0xFFFFFFFF }
1613 };
1614
1615 static const struct si_powertune_data powertune_data_oland =
1616 {
1617         ((1 << 16) | 0x6993),
1618         5,
1619         0,
1620         7,
1621         105,
1622         {
1623                 0UL,
1624                 0UL,
1625                 7194395UL,
1626                 309631529UL,
1627                 -1270850L,
1628                 4513710L,
1629                 100
1630         },
1631         117830498UL,
1632         12,
1633         {
1634                 0,
1635                 0,
1636                 0,
1637                 0,
1638                 0,
1639                 0,
1640                 0,
1641                 0
1642         },
1643         true
1644 };
1645
1646 static const struct si_powertune_data powertune_data_mars_pro =
1647 {
1648         ((1 << 16) | 0x6993),
1649         5,
1650         0,
1651         7,
1652         105,
1653         {
1654                 0UL,
1655                 0UL,
1656                 7194395UL,
1657                 309631529UL,
1658                 -1270850L,
1659                 4513710L,
1660                 100
1661         },
1662         117830498UL,
1663         12,
1664         {
1665                 0,
1666                 0,
1667                 0,
1668                 0,
1669                 0,
1670                 0,
1671                 0,
1672                 0
1673         },
1674         true
1675 };
1676
1677 static const struct si_dte_data dte_data_oland =
1678 {
1679         { 0, 0, 0, 0, 0 },
1680         { 0, 0, 0, 0, 0 },
1681         0,
1682         0,
1683         0,
1684         0,
1685         0,
1686         0,
1687         0,
1688         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1689         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1690         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1691         0,
1692         false
1693 };
1694
1695 static const struct si_dte_data dte_data_mars_pro =
1696 {
1697         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1698         { 0x0, 0x0, 0x0, 0x0, 0x0 },
1699         5,
1700         55000,
1701         105,
1702         0xA,
1703         1,
1704         0,
1705         0x10,
1706         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1707         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1708         { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1709         90,
1710         true
1711 };
1712
1713 static const struct si_dte_data dte_data_sun_xt =
1714 {
1715         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1716         { 0x0, 0x0, 0x0, 0x0, 0x0 },
1717         5,
1718         55000,
1719         105,
1720         0xA,
1721         1,
1722         0,
1723         0x10,
1724         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1725         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1726         { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1727         90,
1728         true
1729 };
1730
1731
1732 static const struct si_cac_config_reg cac_weights_hainan[] =
1733 {
1734         { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1735         { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1736         { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1737         { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1738         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1739         { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1740         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1741         { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1742         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1743         { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1744         { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1745         { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1746         { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1747         { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1748         { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1749         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1750         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1751         { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1752         { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1753         { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1754         { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1755         { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1756         { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1757         { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1758         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1759         { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1760         { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1761         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1762         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1763         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1764         { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1765         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1766         { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1767         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1768         { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1769         { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1770         { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1771         { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1772         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1773         { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1774         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1775         { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1776         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1777         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1778         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1779         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1780         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1781         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1782         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1783         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1784         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1785         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1786         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1787         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1788         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1789         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1790         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1791         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1792         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1793         { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1794         { 0xFFFFFFFF }
1795 };
1796
1797 static const struct si_powertune_data powertune_data_hainan =
1798 {
1799         ((1 << 16) | 0x6993),
1800         5,
1801         0,
1802         9,
1803         105,
1804         {
1805                 0UL,
1806                 0UL,
1807                 7194395UL,
1808                 309631529UL,
1809                 -1270850L,
1810                 4513710L,
1811                 100
1812         },
1813         117830498UL,
1814         12,
1815         {
1816                 0,
1817                 0,
1818                 0,
1819                 0,
1820                 0,
1821                 0,
1822                 0,
1823                 0
1824         },
1825         true
1826 };
1827
1828 static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev);
1829 static struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev);
1830 static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev);
1831 static struct  si_ps *si_get_ps(struct amdgpu_ps *rps);
1832
1833 static int si_populate_voltage_value(struct amdgpu_device *adev,
1834                                      const struct atom_voltage_table *table,
1835                                      u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1836 static int si_get_std_voltage_value(struct amdgpu_device *adev,
1837                                     SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1838                                     u16 *std_voltage);
1839 static int si_write_smc_soft_register(struct amdgpu_device *adev,
1840                                       u16 reg_offset, u32 value);
1841 static int si_convert_power_level_to_smc(struct amdgpu_device *adev,
1842                                          struct rv7xx_pl *pl,
1843                                          SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1844 static int si_calculate_sclk_params(struct amdgpu_device *adev,
1845                                     u32 engine_clock,
1846                                     SISLANDS_SMC_SCLK_VALUE *sclk);
1847
1848 static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev);
1849 static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev);
1850 static void si_dpm_set_dpm_funcs(struct amdgpu_device *adev);
1851 static void si_dpm_set_irq_funcs(struct amdgpu_device *adev);
1852
1853 static struct si_power_info *si_get_pi(struct amdgpu_device *adev)
1854 {
1855         struct si_power_info *pi = adev->pm.dpm.priv;
1856         return pi;
1857 }
1858
1859 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1860                                                      u16 v, s32 t, u32 ileakage, u32 *leakage)
1861 {
1862         s64 kt, kv, leakage_w, i_leakage, vddc;
1863         s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1864         s64 tmp;
1865
1866         i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1867         vddc = div64_s64(drm_int2fixp(v), 1000);
1868         temperature = div64_s64(drm_int2fixp(t), 1000);
1869
1870         t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1871         t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1872         av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1873         bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1874         t_ref = drm_int2fixp(coeff->t_ref);
1875
1876         tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1877         kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1878         kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1879         kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1880
1881         leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1882
1883         *leakage = drm_fixp2int(leakage_w * 1000);
1884 }
1885
1886 static void si_calculate_leakage_for_v_and_t(struct amdgpu_device *adev,
1887                                              const struct ni_leakage_coeffients *coeff,
1888                                              u16 v,
1889                                              s32 t,
1890                                              u32 i_leakage,
1891                                              u32 *leakage)
1892 {
1893         si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1894 }
1895
1896 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1897                                                const u32 fixed_kt, u16 v,
1898                                                u32 ileakage, u32 *leakage)
1899 {
1900         s64 kt, kv, leakage_w, i_leakage, vddc;
1901
1902         i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1903         vddc = div64_s64(drm_int2fixp(v), 1000);
1904
1905         kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1906         kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1907                           drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1908
1909         leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1910
1911         *leakage = drm_fixp2int(leakage_w * 1000);
1912 }
1913
1914 static void si_calculate_leakage_for_v(struct amdgpu_device *adev,
1915                                        const struct ni_leakage_coeffients *coeff,
1916                                        const u32 fixed_kt,
1917                                        u16 v,
1918                                        u32 i_leakage,
1919                                        u32 *leakage)
1920 {
1921         si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1922 }
1923
1924
1925 static void si_update_dte_from_pl2(struct amdgpu_device *adev,
1926                                    struct si_dte_data *dte_data)
1927 {
1928         u32 p_limit1 = adev->pm.dpm.tdp_limit;
1929         u32 p_limit2 = adev->pm.dpm.near_tdp_limit;
1930         u32 k = dte_data->k;
1931         u32 t_max = dte_data->max_t;
1932         u32 t_split[5] = { 10, 15, 20, 25, 30 };
1933         u32 t_0 = dte_data->t0;
1934         u32 i;
1935
1936         if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1937                 dte_data->tdep_count = 3;
1938
1939                 for (i = 0; i < k; i++) {
1940                         dte_data->r[i] =
1941                                 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1942                                 (p_limit2  * (u32)100);
1943                 }
1944
1945                 dte_data->tdep_r[1] = dte_data->r[4] * 2;
1946
1947                 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1948                         dte_data->tdep_r[i] = dte_data->r[4];
1949                 }
1950         } else {
1951                 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1952         }
1953 }
1954
1955 static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev)
1956 {
1957         struct rv7xx_power_info *pi = adev->pm.dpm.priv;
1958
1959         return pi;
1960 }
1961
1962 static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev)
1963 {
1964         struct ni_power_info *pi = adev->pm.dpm.priv;
1965
1966         return pi;
1967 }
1968
1969 static struct si_ps *si_get_ps(struct amdgpu_ps *aps)
1970 {
1971         struct  si_ps *ps = aps->ps_priv;
1972
1973         return ps;
1974 }
1975
1976 static void si_initialize_powertune_defaults(struct amdgpu_device *adev)
1977 {
1978         struct ni_power_info *ni_pi = ni_get_pi(adev);
1979         struct si_power_info *si_pi = si_get_pi(adev);
1980         bool update_dte_from_pl2 = false;
1981
1982         if (adev->asic_type == CHIP_TAHITI) {
1983                 si_pi->cac_weights = cac_weights_tahiti;
1984                 si_pi->lcac_config = lcac_tahiti;
1985                 si_pi->cac_override = cac_override_tahiti;
1986                 si_pi->powertune_data = &powertune_data_tahiti;
1987                 si_pi->dte_data = dte_data_tahiti;
1988
1989                 switch (adev->pdev->device) {
1990                 case 0x6798:
1991                         si_pi->dte_data.enable_dte_by_default = true;
1992                         break;
1993                 case 0x6799:
1994                         si_pi->dte_data = dte_data_new_zealand;
1995                         break;
1996                 case 0x6790:
1997                 case 0x6791:
1998                 case 0x6792:
1999                 case 0x679E:
2000                         si_pi->dte_data = dte_data_aruba_pro;
2001                         update_dte_from_pl2 = true;
2002                         break;
2003                 case 0x679B:
2004                         si_pi->dte_data = dte_data_malta;
2005                         update_dte_from_pl2 = true;
2006                         break;
2007                 case 0x679A:
2008                         si_pi->dte_data = dte_data_tahiti_pro;
2009                         update_dte_from_pl2 = true;
2010                         break;
2011                 default:
2012                         if (si_pi->dte_data.enable_dte_by_default == true)
2013                                 DRM_ERROR("DTE is not enabled!\n");
2014                         break;
2015                 }
2016         } else if (adev->asic_type == CHIP_PITCAIRN) {
2017                 si_pi->cac_weights = cac_weights_pitcairn;
2018                 si_pi->lcac_config = lcac_pitcairn;
2019                 si_pi->cac_override = cac_override_pitcairn;
2020                 si_pi->powertune_data = &powertune_data_pitcairn;
2021
2022                 switch (adev->pdev->device) {
2023                 case 0x6810:
2024                 case 0x6818:
2025                         si_pi->dte_data = dte_data_curacao_xt;
2026                         update_dte_from_pl2 = true;
2027                         break;
2028                 case 0x6819:
2029                 case 0x6811:
2030                         si_pi->dte_data = dte_data_curacao_pro;
2031                         update_dte_from_pl2 = true;
2032                         break;
2033                 case 0x6800:
2034                 case 0x6806:
2035                         si_pi->dte_data = dte_data_neptune_xt;
2036                         update_dte_from_pl2 = true;
2037                         break;
2038                 default:
2039                         si_pi->dte_data = dte_data_pitcairn;
2040                         break;
2041                 }
2042         } else if (adev->asic_type == CHIP_VERDE) {
2043                 si_pi->lcac_config = lcac_cape_verde;
2044                 si_pi->cac_override = cac_override_cape_verde;
2045                 si_pi->powertune_data = &powertune_data_cape_verde;
2046
2047                 switch (adev->pdev->device) {
2048                 case 0x683B:
2049                 case 0x683F:
2050                 case 0x6829:
2051                 case 0x6835:
2052                         si_pi->cac_weights = cac_weights_cape_verde_pro;
2053                         si_pi->dte_data = dte_data_cape_verde;
2054                         break;
2055                 case 0x682C:
2056                         si_pi->cac_weights = cac_weights_cape_verde_pro;
2057                         si_pi->dte_data = dte_data_sun_xt;
2058                         break;
2059                 case 0x6825:
2060                 case 0x6827:
2061                         si_pi->cac_weights = cac_weights_heathrow;
2062                         si_pi->dte_data = dte_data_cape_verde;
2063                         break;
2064                 case 0x6824:
2065                 case 0x682D:
2066                         si_pi->cac_weights = cac_weights_chelsea_xt;
2067                         si_pi->dte_data = dte_data_cape_verde;
2068                         break;
2069                 case 0x682F:
2070                         si_pi->cac_weights = cac_weights_chelsea_pro;
2071                         si_pi->dte_data = dte_data_cape_verde;
2072                         break;
2073                 case 0x6820:
2074                         si_pi->cac_weights = cac_weights_heathrow;
2075                         si_pi->dte_data = dte_data_venus_xtx;
2076                         break;
2077                 case 0x6821:
2078                         si_pi->cac_weights = cac_weights_heathrow;
2079                         si_pi->dte_data = dte_data_venus_xt;
2080                         break;
2081                 case 0x6823:
2082                 case 0x682B:
2083                 case 0x6822:
2084                 case 0x682A:
2085                         si_pi->cac_weights = cac_weights_chelsea_pro;
2086                         si_pi->dte_data = dte_data_venus_pro;
2087                         break;
2088                 default:
2089                         si_pi->cac_weights = cac_weights_cape_verde;
2090                         si_pi->dte_data = dte_data_cape_verde;
2091                         break;
2092                 }
2093         } else if (adev->asic_type == CHIP_OLAND) {
2094                 si_pi->lcac_config = lcac_mars_pro;
2095                 si_pi->cac_override = cac_override_oland;
2096                 si_pi->powertune_data = &powertune_data_mars_pro;
2097                 si_pi->dte_data = dte_data_mars_pro;
2098
2099                 switch (adev->pdev->device) {
2100                 case 0x6601:
2101                 case 0x6621:
2102                 case 0x6603:
2103                 case 0x6605:
2104                         si_pi->cac_weights = cac_weights_mars_pro;
2105                         update_dte_from_pl2 = true;
2106                         break;
2107                 case 0x6600:
2108                 case 0x6606:
2109                 case 0x6620:
2110                 case 0x6604:
2111                         si_pi->cac_weights = cac_weights_mars_xt;
2112                         update_dte_from_pl2 = true;
2113                         break;
2114                 case 0x6611:
2115                 case 0x6613:
2116                 case 0x6608:
2117                         si_pi->cac_weights = cac_weights_oland_pro;
2118                         update_dte_from_pl2 = true;
2119                         break;
2120                 case 0x6610:
2121                         si_pi->cac_weights = cac_weights_oland_xt;
2122                         update_dte_from_pl2 = true;
2123                         break;
2124                 default:
2125                         si_pi->cac_weights = cac_weights_oland;
2126                         si_pi->lcac_config = lcac_oland;
2127                         si_pi->cac_override = cac_override_oland;
2128                         si_pi->powertune_data = &powertune_data_oland;
2129                         si_pi->dte_data = dte_data_oland;
2130                         break;
2131                 }
2132         } else if (adev->asic_type == CHIP_HAINAN) {
2133                 si_pi->cac_weights = cac_weights_hainan;
2134                 si_pi->lcac_config = lcac_oland;
2135                 si_pi->cac_override = cac_override_oland;
2136                 si_pi->powertune_data = &powertune_data_hainan;
2137                 si_pi->dte_data = dte_data_sun_xt;
2138                 update_dte_from_pl2 = true;
2139         } else {
2140                 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2141                 return;
2142         }
2143
2144         ni_pi->enable_power_containment = false;
2145         ni_pi->enable_cac = false;
2146         ni_pi->enable_sq_ramping = false;
2147         si_pi->enable_dte = false;
2148
2149         if (si_pi->powertune_data->enable_powertune_by_default) {
2150                 ni_pi->enable_power_containment = true;
2151                 ni_pi->enable_cac = true;
2152                 if (si_pi->dte_data.enable_dte_by_default) {
2153                         si_pi->enable_dte = true;
2154                         if (update_dte_from_pl2)
2155                                 si_update_dte_from_pl2(adev, &si_pi->dte_data);
2156
2157                 }
2158                 ni_pi->enable_sq_ramping = true;
2159         }
2160
2161         ni_pi->driver_calculate_cac_leakage = true;
2162         ni_pi->cac_configuration_required = true;
2163
2164         if (ni_pi->cac_configuration_required) {
2165                 ni_pi->support_cac_long_term_average = true;
2166                 si_pi->dyn_powertune_data.l2_lta_window_size =
2167                         si_pi->powertune_data->l2_lta_window_size_default;
2168                 si_pi->dyn_powertune_data.lts_truncate =
2169                         si_pi->powertune_data->lts_truncate_default;
2170         } else {
2171                 ni_pi->support_cac_long_term_average = false;
2172                 si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2173                 si_pi->dyn_powertune_data.lts_truncate = 0;
2174         }
2175
2176         si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2177 }
2178
2179 static u32 si_get_smc_power_scaling_factor(struct amdgpu_device *adev)
2180 {
2181         return 1;
2182 }
2183
2184 static u32 si_calculate_cac_wintime(struct amdgpu_device *adev)
2185 {
2186         u32 xclk;
2187         u32 wintime;
2188         u32 cac_window;
2189         u32 cac_window_size;
2190
2191         xclk = amdgpu_asic_get_xclk(adev);
2192
2193         if (xclk == 0)
2194                 return 0;
2195
2196         cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
2197         cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2198
2199         wintime = (cac_window_size * 100) / xclk;
2200
2201         return wintime;
2202 }
2203
2204 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2205 {
2206         return power_in_watts;
2207 }
2208
2209 static int si_calculate_adjusted_tdp_limits(struct amdgpu_device *adev,
2210                                             bool adjust_polarity,
2211                                             u32 tdp_adjustment,
2212                                             u32 *tdp_limit,
2213                                             u32 *near_tdp_limit)
2214 {
2215         u32 adjustment_delta, max_tdp_limit;
2216
2217         if (tdp_adjustment > (u32)adev->pm.dpm.tdp_od_limit)
2218                 return -EINVAL;
2219
2220         max_tdp_limit = ((100 + 100) * adev->pm.dpm.tdp_limit) / 100;
2221
2222         if (adjust_polarity) {
2223                 *tdp_limit = ((100 + tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100;
2224                 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - adev->pm.dpm.tdp_limit);
2225         } else {
2226                 *tdp_limit = ((100 - tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100;
2227                 adjustment_delta  = adev->pm.dpm.tdp_limit - *tdp_limit;
2228                 if (adjustment_delta < adev->pm.dpm.near_tdp_limit_adjusted)
2229                         *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2230                 else
2231                         *near_tdp_limit = 0;
2232         }
2233
2234         if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2235                 return -EINVAL;
2236         if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2237                 return -EINVAL;
2238
2239         return 0;
2240 }
2241
2242 static int si_populate_smc_tdp_limits(struct amdgpu_device *adev,
2243                                       struct amdgpu_ps *amdgpu_state)
2244 {
2245         struct ni_power_info *ni_pi = ni_get_pi(adev);
2246         struct si_power_info *si_pi = si_get_pi(adev);
2247
2248         if (ni_pi->enable_power_containment) {
2249                 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2250                 PP_SIslands_PAPMParameters *papm_parm;
2251                 struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table;
2252                 u32 scaling_factor = si_get_smc_power_scaling_factor(adev);
2253                 u32 tdp_limit;
2254                 u32 near_tdp_limit;
2255                 int ret;
2256
2257                 if (scaling_factor == 0)
2258                         return -EINVAL;
2259
2260                 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2261
2262                 ret = si_calculate_adjusted_tdp_limits(adev,
2263                                                        false, /* ??? */
2264                                                        adev->pm.dpm.tdp_adjustment,
2265                                                        &tdp_limit,
2266                                                        &near_tdp_limit);
2267                 if (ret)
2268                         return ret;
2269
2270                 smc_table->dpm2Params.TDPLimit =
2271                         cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2272                 smc_table->dpm2Params.NearTDPLimit =
2273                         cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2274                 smc_table->dpm2Params.SafePowerLimit =
2275                         cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2276
2277                 ret = amdgpu_si_copy_bytes_to_smc(adev,
2278                                                   (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2279                                                    offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2280                                                   (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2281                                                   sizeof(u32) * 3,
2282                                                   si_pi->sram_end);
2283                 if (ret)
2284                         return ret;
2285
2286                 if (si_pi->enable_ppm) {
2287                         papm_parm = &si_pi->papm_parm;
2288                         memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2289                         papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2290                         papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2291                         papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2292                         papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2293                         papm_parm->PlatformPowerLimit = 0xffffffff;
2294                         papm_parm->NearTDPLimitPAPM = 0xffffffff;
2295
2296                         ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->papm_cfg_table_start,
2297                                                           (u8 *)papm_parm,
2298                                                           sizeof(PP_SIslands_PAPMParameters),
2299                                                           si_pi->sram_end);
2300                         if (ret)
2301                                 return ret;
2302                 }
2303         }
2304         return 0;
2305 }
2306
2307 static int si_populate_smc_tdp_limits_2(struct amdgpu_device *adev,
2308                                         struct amdgpu_ps *amdgpu_state)
2309 {
2310         struct ni_power_info *ni_pi = ni_get_pi(adev);
2311         struct si_power_info *si_pi = si_get_pi(adev);
2312
2313         if (ni_pi->enable_power_containment) {
2314                 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2315                 u32 scaling_factor = si_get_smc_power_scaling_factor(adev);
2316                 int ret;
2317
2318                 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2319
2320                 smc_table->dpm2Params.NearTDPLimit =
2321                         cpu_to_be32(si_scale_power_for_smc(adev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2322                 smc_table->dpm2Params.SafePowerLimit =
2323                         cpu_to_be32(si_scale_power_for_smc((adev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2324
2325                 ret = amdgpu_si_copy_bytes_to_smc(adev,
2326                                                   (si_pi->state_table_start +
2327                                                    offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2328                                                    offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2329                                                   (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2330                                                   sizeof(u32) * 2,
2331                                                   si_pi->sram_end);
2332                 if (ret)
2333                         return ret;
2334         }
2335
2336         return 0;
2337 }
2338
2339 static u16 si_calculate_power_efficiency_ratio(struct amdgpu_device *adev,
2340                                                const u16 prev_std_vddc,
2341                                                const u16 curr_std_vddc)
2342 {
2343         u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2344         u64 prev_vddc = (u64)prev_std_vddc;
2345         u64 curr_vddc = (u64)curr_std_vddc;
2346         u64 pwr_efficiency_ratio, n, d;
2347
2348         if ((prev_vddc == 0) || (curr_vddc == 0))
2349                 return 0;
2350
2351         n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2352         d = prev_vddc * prev_vddc;
2353         pwr_efficiency_ratio = div64_u64(n, d);
2354
2355         if (pwr_efficiency_ratio > (u64)0xFFFF)
2356                 return 0;
2357
2358         return (u16)pwr_efficiency_ratio;
2359 }
2360
2361 static bool si_should_disable_uvd_powertune(struct amdgpu_device *adev,
2362                                             struct amdgpu_ps *amdgpu_state)
2363 {
2364         struct si_power_info *si_pi = si_get_pi(adev);
2365
2366         if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2367             amdgpu_state->vclk && amdgpu_state->dclk)
2368                 return true;
2369
2370         return false;
2371 }
2372
2373 struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev)
2374 {
2375         struct evergreen_power_info *pi = adev->pm.dpm.priv;
2376
2377         return pi;
2378 }
2379
2380 static int si_populate_power_containment_values(struct amdgpu_device *adev,
2381                                                 struct amdgpu_ps *amdgpu_state,
2382                                                 SISLANDS_SMC_SWSTATE *smc_state)
2383 {
2384         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
2385         struct ni_power_info *ni_pi = ni_get_pi(adev);
2386         struct  si_ps *state = si_get_ps(amdgpu_state);
2387         SISLANDS_SMC_VOLTAGE_VALUE vddc;
2388         u32 prev_sclk;
2389         u32 max_sclk;
2390         u32 min_sclk;
2391         u16 prev_std_vddc;
2392         u16 curr_std_vddc;
2393         int i;
2394         u16 pwr_efficiency_ratio;
2395         u8 max_ps_percent;
2396         bool disable_uvd_power_tune;
2397         int ret;
2398
2399         if (ni_pi->enable_power_containment == false)
2400                 return 0;
2401
2402         if (state->performance_level_count == 0)
2403                 return -EINVAL;
2404
2405         if (smc_state->levelCount != state->performance_level_count)
2406                 return -EINVAL;
2407
2408         disable_uvd_power_tune = si_should_disable_uvd_powertune(adev, amdgpu_state);
2409
2410         smc_state->levels[0].dpm2.MaxPS = 0;
2411         smc_state->levels[0].dpm2.NearTDPDec = 0;
2412         smc_state->levels[0].dpm2.AboveSafeInc = 0;
2413         smc_state->levels[0].dpm2.BelowSafeInc = 0;
2414         smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2415
2416         for (i = 1; i < state->performance_level_count; i++) {
2417                 prev_sclk = state->performance_levels[i-1].sclk;
2418                 max_sclk  = state->performance_levels[i].sclk;
2419                 if (i == 1)
2420                         max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2421                 else
2422                         max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2423
2424                 if (prev_sclk > max_sclk)
2425                         return -EINVAL;
2426
2427                 if ((max_ps_percent == 0) ||
2428                     (prev_sclk == max_sclk) ||
2429                     disable_uvd_power_tune)
2430                         min_sclk = max_sclk;
2431                 else if (i == 1)
2432                         min_sclk = prev_sclk;
2433                 else
2434                         min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2435
2436                 if (min_sclk < state->performance_levels[0].sclk)
2437                         min_sclk = state->performance_levels[0].sclk;
2438
2439                 if (min_sclk == 0)
2440                         return -EINVAL;
2441
2442                 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
2443                                                 state->performance_levels[i-1].vddc, &vddc);
2444                 if (ret)
2445                         return ret;
2446
2447                 ret = si_get_std_voltage_value(adev, &vddc, &prev_std_vddc);
2448                 if (ret)
2449                         return ret;
2450
2451                 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
2452                                                 state->performance_levels[i].vddc, &vddc);
2453                 if (ret)
2454                         return ret;
2455
2456                 ret = si_get_std_voltage_value(adev, &vddc, &curr_std_vddc);
2457                 if (ret)
2458                         return ret;
2459
2460                 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(adev,
2461                                                                            prev_std_vddc, curr_std_vddc);
2462
2463                 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2464                 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2465                 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2466                 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2467                 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2468         }
2469
2470         return 0;
2471 }
2472
2473 static int si_populate_sq_ramping_values(struct amdgpu_device *adev,
2474                                          struct amdgpu_ps *amdgpu_state,
2475                                          SISLANDS_SMC_SWSTATE *smc_state)
2476 {
2477         struct ni_power_info *ni_pi = ni_get_pi(adev);
2478         struct  si_ps *state = si_get_ps(amdgpu_state);
2479         u32 sq_power_throttle, sq_power_throttle2;
2480         bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2481         int i;
2482
2483         if (state->performance_level_count == 0)
2484                 return -EINVAL;
2485
2486         if (smc_state->levelCount != state->performance_level_count)
2487                 return -EINVAL;
2488
2489         if (adev->pm.dpm.sq_ramping_threshold == 0)
2490                 return -EINVAL;
2491
2492         if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2493                 enable_sq_ramping = false;
2494
2495         if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2496                 enable_sq_ramping = false;
2497
2498         if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2499                 enable_sq_ramping = false;
2500
2501         if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2502                 enable_sq_ramping = false;
2503
2504         if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2505                 enable_sq_ramping = false;
2506
2507         for (i = 0; i < state->performance_level_count; i++) {
2508                 sq_power_throttle = 0;
2509                 sq_power_throttle2 = 0;
2510
2511                 if ((state->performance_levels[i].sclk >= adev->pm.dpm.sq_ramping_threshold) &&
2512                     enable_sq_ramping) {
2513                         sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2514                         sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2515                         sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2516                         sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2517                         sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2518                 } else {
2519                         sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2520                         sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2521                 }
2522
2523                 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2524                 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2525         }
2526
2527         return 0;
2528 }
2529
2530 static int si_enable_power_containment(struct amdgpu_device *adev,
2531                                        struct amdgpu_ps *amdgpu_new_state,
2532                                        bool enable)
2533 {
2534         struct ni_power_info *ni_pi = ni_get_pi(adev);
2535         PPSMC_Result smc_result;
2536         int ret = 0;
2537
2538         if (ni_pi->enable_power_containment) {
2539                 if (enable) {
2540                         if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
2541                                 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingActive);
2542                                 if (smc_result != PPSMC_Result_OK) {
2543                                         ret = -EINVAL;
2544                                         ni_pi->pc_enabled = false;
2545                                 } else {
2546                                         ni_pi->pc_enabled = true;
2547                                 }
2548                         }
2549                 } else {
2550                         smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingInactive);
2551                         if (smc_result != PPSMC_Result_OK)
2552                                 ret = -EINVAL;
2553                         ni_pi->pc_enabled = false;
2554                 }
2555         }
2556
2557         return ret;
2558 }
2559
2560 static int si_initialize_smc_dte_tables(struct amdgpu_device *adev)
2561 {
2562         struct si_power_info *si_pi = si_get_pi(adev);
2563         int ret = 0;
2564         struct si_dte_data *dte_data = &si_pi->dte_data;
2565         Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2566         u32 table_size;
2567         u8 tdep_count;
2568         u32 i;
2569
2570         if (dte_data == NULL)
2571                 si_pi->enable_dte = false;
2572
2573         if (si_pi->enable_dte == false)
2574                 return 0;
2575
2576         if (dte_data->k <= 0)
2577                 return -EINVAL;
2578
2579         dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2580         if (dte_tables == NULL) {
2581                 si_pi->enable_dte = false;
2582                 return -ENOMEM;
2583         }
2584
2585         table_size = dte_data->k;
2586
2587         if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2588                 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2589
2590         tdep_count = dte_data->tdep_count;
2591         if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2592                 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2593
2594         dte_tables->K = cpu_to_be32(table_size);
2595         dte_tables->T0 = cpu_to_be32(dte_data->t0);
2596         dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2597         dte_tables->WindowSize = dte_data->window_size;
2598         dte_tables->temp_select = dte_data->temp_select;
2599         dte_tables->DTE_mode = dte_data->dte_mode;
2600         dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2601
2602         if (tdep_count > 0)
2603                 table_size--;
2604
2605         for (i = 0; i < table_size; i++) {
2606                 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2607                 dte_tables->R[i]   = cpu_to_be32(dte_data->r[i]);
2608         }
2609
2610         dte_tables->Tdep_count = tdep_count;
2611
2612         for (i = 0; i < (u32)tdep_count; i++) {
2613                 dte_tables->T_limits[i] = dte_data->t_limits[i];
2614                 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2615                 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2616         }
2617
2618         ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->dte_table_start,
2619                                           (u8 *)dte_tables,
2620                                           sizeof(Smc_SIslands_DTE_Configuration),
2621                                           si_pi->sram_end);
2622         kfree(dte_tables);
2623
2624         return ret;
2625 }
2626
2627 static int si_get_cac_std_voltage_max_min(struct amdgpu_device *adev,
2628                                           u16 *max, u16 *min)
2629 {
2630         struct si_power_info *si_pi = si_get_pi(adev);
2631         struct amdgpu_cac_leakage_table *table =
2632                 &adev->pm.dpm.dyn_state.cac_leakage_table;
2633         u32 i;
2634         u32 v0_loadline;
2635
2636         if (table == NULL)
2637                 return -EINVAL;
2638
2639         *max = 0;
2640         *min = 0xFFFF;
2641
2642         for (i = 0; i < table->count; i++) {
2643                 if (table->entries[i].vddc > *max)
2644                         *max = table->entries[i].vddc;
2645                 if (table->entries[i].vddc < *min)
2646                         *min = table->entries[i].vddc;
2647         }
2648
2649         if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2650                 return -EINVAL;
2651
2652         v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2653
2654         if (v0_loadline > 0xFFFFUL)
2655                 return -EINVAL;
2656
2657         *min = (u16)v0_loadline;
2658
2659         if ((*min > *max) || (*max == 0) || (*min == 0))
2660                 return -EINVAL;
2661
2662         return 0;
2663 }
2664
2665 static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2666 {
2667         return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2668                 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2669 }
2670
2671 static int si_init_dte_leakage_table(struct amdgpu_device *adev,
2672                                      PP_SIslands_CacConfig *cac_tables,
2673                                      u16 vddc_max, u16 vddc_min, u16 vddc_step,
2674                                      u16 t0, u16 t_step)
2675 {
2676         struct si_power_info *si_pi = si_get_pi(adev);
2677         u32 leakage;
2678         unsigned int i, j;
2679         s32 t;
2680         u32 smc_leakage;
2681         u32 scaling_factor;
2682         u16 voltage;
2683
2684         scaling_factor = si_get_smc_power_scaling_factor(adev);
2685
2686         for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2687                 t = (1000 * (i * t_step + t0));
2688
2689                 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2690                         voltage = vddc_max - (vddc_step * j);
2691
2692                         si_calculate_leakage_for_v_and_t(adev,
2693                                                          &si_pi->powertune_data->leakage_coefficients,
2694                                                          voltage,
2695                                                          t,
2696                                                          si_pi->dyn_powertune_data.cac_leakage,
2697                                                          &leakage);
2698
2699                         smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2700
2701                         if (smc_leakage > 0xFFFF)
2702                                 smc_leakage = 0xFFFF;
2703
2704                         cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2705                                 cpu_to_be16((u16)smc_leakage);
2706                 }
2707         }
2708         return 0;
2709 }
2710
2711 static int si_init_simplified_leakage_table(struct amdgpu_device *adev,
2712                                             PP_SIslands_CacConfig *cac_tables,
2713                                             u16 vddc_max, u16 vddc_min, u16 vddc_step)
2714 {
2715         struct si_power_info *si_pi = si_get_pi(adev);
2716         u32 leakage;
2717         unsigned int i, j;
2718         u32 smc_leakage;
2719         u32 scaling_factor;
2720         u16 voltage;
2721
2722         scaling_factor = si_get_smc_power_scaling_factor(adev);
2723
2724         for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2725                 voltage = vddc_max - (vddc_step * j);
2726
2727                 si_calculate_leakage_for_v(adev,
2728                                            &si_pi->powertune_data->leakage_coefficients,
2729                                            si_pi->powertune_data->fixed_kt,
2730                                            voltage,
2731                                            si_pi->dyn_powertune_data.cac_leakage,
2732                                            &leakage);
2733
2734                 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2735
2736                 if (smc_leakage > 0xFFFF)
2737                         smc_leakage = 0xFFFF;
2738
2739                 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2740                         cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2741                                 cpu_to_be16((u16)smc_leakage);
2742         }
2743         return 0;
2744 }
2745
2746 static int si_initialize_smc_cac_tables(struct amdgpu_device *adev)
2747 {
2748         struct ni_power_info *ni_pi = ni_get_pi(adev);
2749         struct si_power_info *si_pi = si_get_pi(adev);
2750         PP_SIslands_CacConfig *cac_tables = NULL;
2751         u16 vddc_max, vddc_min, vddc_step;
2752         u16 t0, t_step;
2753         u32 load_line_slope, reg;
2754         int ret = 0;
2755         u32 ticks_per_us = amdgpu_asic_get_xclk(adev) / 100;
2756
2757         if (ni_pi->enable_cac == false)
2758                 return 0;
2759
2760         cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2761         if (!cac_tables)
2762                 return -ENOMEM;
2763
2764         reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
2765         reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
2766         WREG32(CG_CAC_CTRL, reg);
2767
2768         si_pi->dyn_powertune_data.cac_leakage = adev->pm.dpm.cac_leakage;
2769         si_pi->dyn_powertune_data.dc_pwr_value =
2770                 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2771         si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(adev);
2772         si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2773
2774         si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2775
2776         ret = si_get_cac_std_voltage_max_min(adev, &vddc_max, &vddc_min);
2777         if (ret)
2778                 goto done_free;
2779
2780         vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2781         vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2782         t_step = 4;
2783         t0 = 60;
2784
2785         if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2786                 ret = si_init_dte_leakage_table(adev, cac_tables,
2787                                                 vddc_max, vddc_min, vddc_step,
2788                                                 t0, t_step);
2789         else
2790                 ret = si_init_simplified_leakage_table(adev, cac_tables,
2791                                                        vddc_max, vddc_min, vddc_step);
2792         if (ret)
2793                 goto done_free;
2794
2795         load_line_slope = ((u32)adev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2796
2797         cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2798         cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2799         cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2800         cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2801         cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2802         cac_tables->R_LL = cpu_to_be32(load_line_slope);
2803         cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2804         cac_tables->calculation_repeats = cpu_to_be32(2);
2805         cac_tables->dc_cac = cpu_to_be32(0);
2806         cac_tables->log2_PG_LKG_SCALE = 12;
2807         cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2808         cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2809         cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2810
2811         ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->cac_table_start,
2812                                           (u8 *)cac_tables,
2813                                           sizeof(PP_SIslands_CacConfig),
2814                                           si_pi->sram_end);
2815
2816         if (ret)
2817                 goto done_free;
2818
2819         ret = si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2820
2821 done_free:
2822         if (ret) {
2823                 ni_pi->enable_cac = false;
2824                 ni_pi->enable_power_containment = false;
2825         }
2826
2827         kfree(cac_tables);
2828
2829         return ret;
2830 }
2831
2832 static int si_program_cac_config_registers(struct amdgpu_device *adev,
2833                                            const struct si_cac_config_reg *cac_config_regs)
2834 {
2835         const struct si_cac_config_reg *config_regs = cac_config_regs;
2836         u32 data = 0, offset;
2837
2838         if (!config_regs)
2839                 return -EINVAL;
2840
2841         while (config_regs->offset != 0xFFFFFFFF) {
2842                 switch (config_regs->type) {
2843                 case SISLANDS_CACCONFIG_CGIND:
2844                         offset = SMC_CG_IND_START + config_regs->offset;
2845                         if (offset < SMC_CG_IND_END)
2846                                 data = RREG32_SMC(offset);
2847                         break;
2848                 default:
2849                         data = RREG32(config_regs->offset);
2850                         break;
2851                 }
2852
2853                 data &= ~config_regs->mask;
2854                 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2855
2856                 switch (config_regs->type) {
2857                 case SISLANDS_CACCONFIG_CGIND:
2858                         offset = SMC_CG_IND_START + config_regs->offset;
2859                         if (offset < SMC_CG_IND_END)
2860                                 WREG32_SMC(offset, data);
2861                         break;
2862                 default:
2863                         WREG32(config_regs->offset, data);
2864                         break;
2865                 }
2866                 config_regs++;
2867         }
2868         return 0;
2869 }
2870
2871 static int si_initialize_hardware_cac_manager(struct amdgpu_device *adev)
2872 {
2873         struct ni_power_info *ni_pi = ni_get_pi(adev);
2874         struct si_power_info *si_pi = si_get_pi(adev);
2875         int ret;
2876
2877         if ((ni_pi->enable_cac == false) ||
2878             (ni_pi->cac_configuration_required == false))
2879                 return 0;
2880
2881         ret = si_program_cac_config_registers(adev, si_pi->lcac_config);
2882         if (ret)
2883                 return ret;
2884         ret = si_program_cac_config_registers(adev, si_pi->cac_override);
2885         if (ret)
2886                 return ret;
2887         ret = si_program_cac_config_registers(adev, si_pi->cac_weights);
2888         if (ret)
2889                 return ret;
2890
2891         return 0;
2892 }
2893
2894 static int si_enable_smc_cac(struct amdgpu_device *adev,
2895                              struct amdgpu_ps *amdgpu_new_state,
2896                              bool enable)
2897 {
2898         struct ni_power_info *ni_pi = ni_get_pi(adev);
2899         struct si_power_info *si_pi = si_get_pi(adev);
2900         PPSMC_Result smc_result;
2901         int ret = 0;
2902
2903         if (ni_pi->enable_cac) {
2904                 if (enable) {
2905                         if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
2906                                 if (ni_pi->support_cac_long_term_average) {
2907                                         smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgEnable);
2908                                         if (smc_result != PPSMC_Result_OK)
2909                                                 ni_pi->support_cac_long_term_average = false;
2910                                 }
2911
2912                                 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableCac);
2913                                 if (smc_result != PPSMC_Result_OK) {
2914                                         ret = -EINVAL;
2915                                         ni_pi->cac_enabled = false;
2916                                 } else {
2917                                         ni_pi->cac_enabled = true;
2918                                 }
2919
2920                                 if (si_pi->enable_dte) {
2921                                         smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE);
2922                                         if (smc_result != PPSMC_Result_OK)
2923                                                 ret = -EINVAL;
2924                                 }
2925                         }
2926                 } else if (ni_pi->cac_enabled) {
2927                         if (si_pi->enable_dte)
2928                                 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE);
2929
2930                         smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableCac);
2931
2932                         ni_pi->cac_enabled = false;
2933
2934                         if (ni_pi->support_cac_long_term_average)
2935                                 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgDisable);
2936                 }
2937         }
2938         return ret;
2939 }
2940
2941 static int si_init_smc_spll_table(struct amdgpu_device *adev)
2942 {
2943         struct ni_power_info *ni_pi = ni_get_pi(adev);
2944         struct si_power_info *si_pi = si_get_pi(adev);
2945         SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2946         SISLANDS_SMC_SCLK_VALUE sclk_params;
2947         u32 fb_div, p_div;
2948         u32 clk_s, clk_v;
2949         u32 sclk = 0;
2950         int ret = 0;
2951         u32 tmp;
2952         int i;
2953
2954         if (si_pi->spll_table_start == 0)
2955                 return -EINVAL;
2956
2957         spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2958         if (spll_table == NULL)
2959                 return -ENOMEM;
2960
2961         for (i = 0; i < 256; i++) {
2962                 ret = si_calculate_sclk_params(adev, sclk, &sclk_params);
2963                 if (ret)
2964                         break;
2965                 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2966                 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2967                 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2968                 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2969
2970                 fb_div &= ~0x00001FFF;
2971                 fb_div >>= 1;
2972                 clk_v >>= 6;
2973
2974                 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2975                         ret = -EINVAL;
2976                 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2977                         ret = -EINVAL;
2978                 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2979                         ret = -EINVAL;
2980                 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2981                         ret = -EINVAL;
2982
2983                 if (ret)
2984                         break;
2985
2986                 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2987                         ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2988                 spll_table->freq[i] = cpu_to_be32(tmp);
2989
2990                 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2991                         ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2992                 spll_table->ss[i] = cpu_to_be32(tmp);
2993
2994                 sclk += 512;
2995         }
2996
2997
2998         if (!ret)
2999                 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->spll_table_start,
3000                                                   (u8 *)spll_table,
3001                                                   sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
3002                                                   si_pi->sram_end);
3003
3004         if (ret)
3005                 ni_pi->enable_power_containment = false;
3006
3007         kfree(spll_table);
3008
3009         return ret;
3010 }
3011
3012 struct si_dpm_quirk {
3013         u32 chip_vendor;
3014         u32 chip_device;
3015         u32 subsys_vendor;
3016         u32 subsys_device;
3017         u32 max_sclk;
3018         u32 max_mclk;
3019 };
3020
3021 /* cards with dpm stability problems */
3022 static struct si_dpm_quirk si_dpm_quirk_list[] = {
3023         /* PITCAIRN - https://bugs.freedesktop.org/show_bug.cgi?id=76490 */
3024         { PCI_VENDOR_ID_ATI, 0x6810, 0x1462, 0x3036, 0, 120000 },
3025         { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0xe271, 0, 120000 },
3026         { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0x2015, 0, 120000 },
3027         { PCI_VENDOR_ID_ATI, 0x6810, 0x174b, 0xe271, 85000, 90000 },
3028         { PCI_VENDOR_ID_ATI, 0x6811, 0x1462, 0x2015, 0, 120000 },
3029         { PCI_VENDOR_ID_ATI, 0x6811, 0x1043, 0x2015, 0, 120000 },
3030         { PCI_VENDOR_ID_ATI, 0x6811, 0x148c, 0x2015, 0, 120000 },
3031         { PCI_VENDOR_ID_ATI, 0x6810, 0x1682, 0x9275, 0, 120000 },
3032         { 0, 0, 0, 0 },
3033 };
3034
3035 static u16 si_get_lower_of_leakage_and_vce_voltage(struct amdgpu_device *adev,
3036                                                    u16 vce_voltage)
3037 {
3038         u16 highest_leakage = 0;
3039         struct si_power_info *si_pi = si_get_pi(adev);
3040         int i;
3041
3042         for (i = 0; i < si_pi->leakage_voltage.count; i++){
3043                 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage)
3044                         highest_leakage = si_pi->leakage_voltage.entries[i].voltage;
3045         }
3046
3047         if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage))
3048                 return highest_leakage;
3049
3050         return vce_voltage;
3051 }
3052
3053 static int si_get_vce_clock_voltage(struct amdgpu_device *adev,
3054                                     u32 evclk, u32 ecclk, u16 *voltage)
3055 {
3056         u32 i;
3057         int ret = -EINVAL;
3058         struct amdgpu_vce_clock_voltage_dependency_table *table =
3059                 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
3060
3061         if (((evclk == 0) && (ecclk == 0)) ||
3062             (table && (table->count == 0))) {
3063                 *voltage = 0;
3064                 return 0;
3065         }
3066
3067         for (i = 0; i < table->count; i++) {
3068                 if ((evclk <= table->entries[i].evclk) &&
3069                     (ecclk <= table->entries[i].ecclk)) {
3070                         *voltage = table->entries[i].v;
3071                         ret = 0;
3072                         break;
3073                 }
3074         }
3075
3076         /* if no match return the highest voltage */
3077         if (ret)
3078                 *voltage = table->entries[table->count - 1].v;
3079
3080         *voltage = si_get_lower_of_leakage_and_vce_voltage(adev, *voltage);
3081
3082         return ret;
3083 }
3084
3085 static bool si_dpm_vblank_too_short(struct amdgpu_device *adev)
3086 {
3087
3088         u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
3089         /* we never hit the non-gddr5 limit so disable it */
3090         u32 switch_limit = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 0;
3091
3092         if (vblank_time < switch_limit)
3093                 return true;
3094         else
3095                 return false;
3096
3097 }
3098
3099 static int ni_copy_and_switch_arb_sets(struct amdgpu_device *adev,
3100                                 u32 arb_freq_src, u32 arb_freq_dest)
3101 {
3102         u32 mc_arb_dram_timing;
3103         u32 mc_arb_dram_timing2;
3104         u32 burst_time;
3105         u32 mc_cg_config;
3106
3107         switch (arb_freq_src) {
3108         case MC_CG_ARB_FREQ_F0:
3109                 mc_arb_dram_timing  = RREG32(MC_ARB_DRAM_TIMING);
3110                 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
3111                 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE0_MASK) >> STATE0_SHIFT;
3112                 break;
3113         case MC_CG_ARB_FREQ_F1:
3114                 mc_arb_dram_timing  = RREG32(MC_ARB_DRAM_TIMING_1);
3115                 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_1);
3116                 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE1_MASK) >> STATE1_SHIFT;
3117                 break;
3118         case MC_CG_ARB_FREQ_F2:
3119                 mc_arb_dram_timing  = RREG32(MC_ARB_DRAM_TIMING_2);
3120                 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_2);
3121                 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE2_MASK) >> STATE2_SHIFT;
3122                 break;
3123         case MC_CG_ARB_FREQ_F3:
3124                 mc_arb_dram_timing  = RREG32(MC_ARB_DRAM_TIMING_3);
3125                 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_3);
3126                 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE3_MASK) >> STATE3_SHIFT;
3127                 break;
3128         default:
3129                 return -EINVAL;
3130         }
3131
3132         switch (arb_freq_dest) {
3133         case MC_CG_ARB_FREQ_F0:
3134                 WREG32(MC_ARB_DRAM_TIMING, mc_arb_dram_timing);
3135                 WREG32(MC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
3136                 WREG32_P(MC_ARB_BURST_TIME, STATE0(burst_time), ~STATE0_MASK);
3137                 break;
3138         case MC_CG_ARB_FREQ_F1:
3139                 WREG32(MC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
3140                 WREG32(MC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
3141                 WREG32_P(MC_ARB_BURST_TIME, STATE1(burst_time), ~STATE1_MASK);
3142                 break;
3143         case MC_CG_ARB_FREQ_F2:
3144                 WREG32(MC_ARB_DRAM_TIMING_2, mc_arb_dram_timing);
3145                 WREG32(MC_ARB_DRAM_TIMING2_2, mc_arb_dram_timing2);
3146                 WREG32_P(MC_ARB_BURST_TIME, STATE2(burst_time), ~STATE2_MASK);
3147                 break;
3148         case MC_CG_ARB_FREQ_F3:
3149                 WREG32(MC_ARB_DRAM_TIMING_3, mc_arb_dram_timing);
3150                 WREG32(MC_ARB_DRAM_TIMING2_3, mc_arb_dram_timing2);
3151                 WREG32_P(MC_ARB_BURST_TIME, STATE3(burst_time), ~STATE3_MASK);
3152                 break;
3153         default:
3154                 return -EINVAL;
3155         }
3156
3157         mc_cg_config = RREG32(MC_CG_CONFIG) | 0x0000000F;
3158         WREG32(MC_CG_CONFIG, mc_cg_config);
3159         WREG32_P(MC_ARB_CG, CG_ARB_REQ(arb_freq_dest), ~CG_ARB_REQ_MASK);
3160
3161         return 0;
3162 }
3163
3164 static void ni_update_current_ps(struct amdgpu_device *adev,
3165                           struct amdgpu_ps *rps)
3166 {
3167         struct si_ps *new_ps = si_get_ps(rps);
3168         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3169         struct ni_power_info *ni_pi = ni_get_pi(adev);
3170
3171         eg_pi->current_rps = *rps;
3172         ni_pi->current_ps = *new_ps;
3173         eg_pi->current_rps.ps_priv = &ni_pi->current_ps;
3174 }
3175
3176 static void ni_update_requested_ps(struct amdgpu_device *adev,
3177                             struct amdgpu_ps *rps)
3178 {
3179         struct si_ps *new_ps = si_get_ps(rps);
3180         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3181         struct ni_power_info *ni_pi = ni_get_pi(adev);
3182
3183         eg_pi->requested_rps = *rps;
3184         ni_pi->requested_ps = *new_ps;
3185         eg_pi->requested_rps.ps_priv = &ni_pi->requested_ps;
3186 }
3187
3188 static void ni_set_uvd_clock_before_set_eng_clock(struct amdgpu_device *adev,
3189                                            struct amdgpu_ps *new_ps,
3190                                            struct amdgpu_ps *old_ps)
3191 {
3192         struct si_ps *new_state = si_get_ps(new_ps);
3193         struct si_ps *current_state = si_get_ps(old_ps);
3194
3195         if ((new_ps->vclk == old_ps->vclk) &&
3196             (new_ps->dclk == old_ps->dclk))
3197                 return;
3198
3199         if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >=
3200             current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3201                 return;
3202
3203         amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
3204 }
3205
3206 static void ni_set_uvd_clock_after_set_eng_clock(struct amdgpu_device *adev,
3207                                           struct amdgpu_ps *new_ps,
3208                                           struct amdgpu_ps *old_ps)
3209 {
3210         struct si_ps *new_state = si_get_ps(new_ps);
3211         struct si_ps *current_state = si_get_ps(old_ps);
3212
3213         if ((new_ps->vclk == old_ps->vclk) &&
3214             (new_ps->dclk == old_ps->dclk))
3215                 return;
3216
3217         if (new_state->performance_levels[new_state->performance_level_count - 1].sclk <
3218             current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3219                 return;
3220
3221         amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
3222 }
3223
3224 static u16 btc_find_voltage(struct atom_voltage_table *table, u16 voltage)
3225 {
3226         unsigned int i;
3227
3228         for (i = 0; i < table->count; i++)
3229                 if (voltage <= table->entries[i].value)
3230                         return table->entries[i].value;
3231
3232         return table->entries[table->count - 1].value;
3233 }
3234
3235 static u32 btc_find_valid_clock(struct amdgpu_clock_array *clocks,
3236                                 u32 max_clock, u32 requested_clock)
3237 {
3238         unsigned int i;
3239
3240         if ((clocks == NULL) || (clocks->count == 0))
3241                 return (requested_clock < max_clock) ? requested_clock : max_clock;
3242
3243         for (i = 0; i < clocks->count; i++) {
3244                 if (clocks->values[i] >= requested_clock)
3245                         return (clocks->values[i] < max_clock) ? clocks->values[i] : max_clock;
3246         }
3247
3248         return (clocks->values[clocks->count - 1] < max_clock) ?
3249                 clocks->values[clocks->count - 1] : max_clock;
3250 }
3251
3252 static u32 btc_get_valid_mclk(struct amdgpu_device *adev,
3253                               u32 max_mclk, u32 requested_mclk)
3254 {
3255         return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_mclk_values,
3256                                     max_mclk, requested_mclk);
3257 }
3258
3259 static u32 btc_get_valid_sclk(struct amdgpu_device *adev,
3260                               u32 max_sclk, u32 requested_sclk)
3261 {
3262         return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_sclk_values,
3263                                     max_sclk, requested_sclk);
3264 }
3265
3266 static void btc_get_max_clock_from_voltage_dependency_table(struct amdgpu_clock_voltage_dependency_table *table,
3267                                                             u32 *max_clock)
3268 {
3269         u32 i, clock = 0;
3270
3271         if ((table == NULL) || (table->count == 0)) {
3272                 *max_clock = clock;
3273                 return;
3274         }
3275
3276         for (i = 0; i < table->count; i++) {
3277                 if (clock < table->entries[i].clk)
3278                         clock = table->entries[i].clk;
3279         }
3280         *max_clock = clock;
3281 }
3282
3283 static void btc_apply_voltage_dependency_rules(struct amdgpu_clock_voltage_dependency_table *table,
3284                                                u32 clock, u16 max_voltage, u16 *voltage)
3285 {
3286         u32 i;
3287
3288         if ((table == NULL) || (table->count == 0))
3289                 return;
3290
3291         for (i= 0; i < table->count; i++) {
3292                 if (clock <= table->entries[i].clk) {
3293                         if (*voltage < table->entries[i].v)
3294                                 *voltage = (u16)((table->entries[i].v < max_voltage) ?
3295                                            table->entries[i].v : max_voltage);
3296                         return;
3297                 }
3298         }
3299
3300         *voltage = (*voltage > max_voltage) ? *voltage : max_voltage;
3301 }
3302
3303 static void btc_adjust_clock_combinations(struct amdgpu_device *adev,
3304                                           const struct amdgpu_clock_and_voltage_limits *max_limits,
3305                                           struct rv7xx_pl *pl)
3306 {
3307
3308         if ((pl->mclk == 0) || (pl->sclk == 0))
3309                 return;
3310
3311         if (pl->mclk == pl->sclk)
3312                 return;
3313
3314         if (pl->mclk > pl->sclk) {
3315                 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > adev->pm.dpm.dyn_state.mclk_sclk_ratio)
3316                         pl->sclk = btc_get_valid_sclk(adev,
3317                                                       max_limits->sclk,
3318                                                       (pl->mclk +
3319                                                       (adev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) /
3320                                                       adev->pm.dpm.dyn_state.mclk_sclk_ratio);
3321         } else {
3322                 if ((pl->sclk - pl->mclk) > adev->pm.dpm.dyn_state.sclk_mclk_delta)
3323                         pl->mclk = btc_get_valid_mclk(adev,
3324                                                       max_limits->mclk,
3325                                                       pl->sclk -
3326                                                       adev->pm.dpm.dyn_state.sclk_mclk_delta);
3327         }
3328 }
3329
3330 static void btc_apply_voltage_delta_rules(struct amdgpu_device *adev,
3331                                           u16 max_vddc, u16 max_vddci,
3332                                           u16 *vddc, u16 *vddci)
3333 {
3334         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3335         u16 new_voltage;
3336
3337         if ((0 == *vddc) || (0 == *vddci))
3338                 return;
3339
3340         if (*vddc > *vddci) {
3341                 if ((*vddc - *vddci) > adev->pm.dpm.dyn_state.vddc_vddci_delta) {
3342                         new_voltage = btc_find_voltage(&eg_pi->vddci_voltage_table,
3343                                                        (*vddc - adev->pm.dpm.dyn_state.vddc_vddci_delta));
3344                         *vddci = (new_voltage < max_vddci) ? new_voltage : max_vddci;
3345                 }
3346         } else {
3347                 if ((*vddci - *vddc) > adev->pm.dpm.dyn_state.vddc_vddci_delta) {
3348                         new_voltage = btc_find_voltage(&eg_pi->vddc_voltage_table,
3349                                                        (*vddci - adev->pm.dpm.dyn_state.vddc_vddci_delta));
3350                         *vddc = (new_voltage < max_vddc) ? new_voltage : max_vddc;
3351                 }
3352         }
3353 }
3354
3355 static enum amdgpu_pcie_gen r600_get_pcie_gen_support(struct amdgpu_device *adev,
3356                                                u32 sys_mask,
3357                                                enum amdgpu_pcie_gen asic_gen,
3358                                                enum amdgpu_pcie_gen default_gen)
3359 {
3360         switch (asic_gen) {
3361         case AMDGPU_PCIE_GEN1:
3362                 return AMDGPU_PCIE_GEN1;
3363         case AMDGPU_PCIE_GEN2:
3364                 return AMDGPU_PCIE_GEN2;
3365         case AMDGPU_PCIE_GEN3:
3366                 return AMDGPU_PCIE_GEN3;
3367         default:
3368                 if ((sys_mask & DRM_PCIE_SPEED_80) && (default_gen == AMDGPU_PCIE_GEN3))
3369                         return AMDGPU_PCIE_GEN3;
3370                 else if ((sys_mask & DRM_PCIE_SPEED_50) && (default_gen == AMDGPU_PCIE_GEN2))
3371                         return AMDGPU_PCIE_GEN2;
3372                 else
3373                         return AMDGPU_PCIE_GEN1;
3374         }
3375         return AMDGPU_PCIE_GEN1;
3376 }
3377
3378 static void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
3379                             u32 *p, u32 *u)
3380 {
3381         u32 b_c = 0;
3382         u32 i_c;
3383         u32 tmp;
3384
3385         i_c = (i * r_c) / 100;
3386         tmp = i_c >> p_b;
3387
3388         while (tmp) {
3389                 b_c++;
3390                 tmp >>= 1;
3391         }
3392
3393         *u = (b_c + 1) / 2;
3394         *p = i_c / (1 << (2 * (*u)));
3395 }
3396
3397 static int r600_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th)
3398 {
3399         u32 k, a, ah, al;
3400         u32 t1;
3401
3402         if ((fl == 0) || (fh == 0) || (fl > fh))
3403                 return -EINVAL;
3404
3405         k = (100 * fh) / fl;
3406         t1 = (t * (k - 100));
3407         a = (1000 * (100 * h + t1)) / (10000 + (t1 / 100));
3408         a = (a + 5) / 10;
3409         ah = ((a * t) + 5000) / 10000;
3410         al = a - ah;
3411
3412         *th = t - ah;
3413         *tl = t + al;
3414
3415         return 0;
3416 }
3417
3418 static bool r600_is_uvd_state(u32 class, u32 class2)
3419 {
3420         if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
3421                 return true;
3422         if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
3423                 return true;
3424         if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
3425                 return true;
3426         if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
3427                 return true;
3428         if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
3429                 return true;
3430         return false;
3431 }
3432
3433 static u8 rv770_get_memory_module_index(struct amdgpu_device *adev)
3434 {
3435         return (u8) ((RREG32(BIOS_SCRATCH_4) >> 16) & 0xff);
3436 }
3437
3438 static void rv770_get_max_vddc(struct amdgpu_device *adev)
3439 {
3440         struct rv7xx_power_info *pi = rv770_get_pi(adev);
3441         u16 vddc;
3442
3443         if (amdgpu_atombios_get_max_vddc(adev, 0, 0, &vddc))
3444                 pi->max_vddc = 0;
3445         else
3446                 pi->max_vddc = vddc;
3447 }
3448
3449 static void rv770_get_engine_memory_ss(struct amdgpu_device *adev)
3450 {
3451         struct rv7xx_power_info *pi = rv770_get_pi(adev);
3452         struct amdgpu_atom_ss ss;
3453
3454         pi->sclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss,
3455                                                        ASIC_INTERNAL_ENGINE_SS, 0);
3456         pi->mclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss,
3457                                                        ASIC_INTERNAL_MEMORY_SS, 0);
3458
3459         if (pi->sclk_ss || pi->mclk_ss)
3460                 pi->dynamic_ss = true;
3461         else
3462                 pi->dynamic_ss = false;
3463 }
3464
3465
3466 static void si_apply_state_adjust_rules(struct amdgpu_device *adev,
3467                                         struct amdgpu_ps *rps)
3468 {
3469         struct  si_ps *ps = si_get_ps(rps);
3470         struct amdgpu_clock_and_voltage_limits *max_limits;
3471         bool disable_mclk_switching = false;
3472         bool disable_sclk_switching = false;
3473         u32 mclk, sclk;
3474         u16 vddc, vddci, min_vce_voltage = 0;
3475         u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
3476         u32 max_sclk = 0, max_mclk = 0;
3477         int i;
3478         struct si_dpm_quirk *p = si_dpm_quirk_list;
3479
3480         /* Apply dpm quirks */
3481         while (p && p->chip_device != 0) {
3482                 if (adev->pdev->vendor == p->chip_vendor &&
3483                     adev->pdev->device == p->chip_device &&
3484                     adev->pdev->subsystem_vendor == p->subsys_vendor &&
3485                     adev->pdev->subsystem_device == p->subsys_device) {
3486                         max_sclk = p->max_sclk;
3487                         max_mclk = p->max_mclk;
3488                         break;
3489                 }
3490                 ++p;
3491         }
3492         /* limit mclk on all R7 370 parts for stability */
3493         if (adev->pdev->device == 0x6811 &&
3494             adev->pdev->revision == 0x81)
3495                 max_mclk = 120000;
3496         /* limit sclk/mclk on Jet parts for stability */
3497         if (adev->pdev->device == 0x6665 &&
3498             adev->pdev->revision == 0xc3) {
3499                 max_sclk = 75000;
3500                 max_mclk = 80000;
3501         }
3502         /* Limit clocks for some HD8600 parts */
3503         if (adev->pdev->device == 0x6660 &&
3504             adev->pdev->revision == 0x83) {
3505                 max_sclk = 75000;
3506                 max_mclk = 80000;
3507         }
3508
3509         if (rps->vce_active) {
3510                 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
3511                 rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk;
3512                 si_get_vce_clock_voltage(adev, rps->evclk, rps->ecclk,
3513                                          &min_vce_voltage);
3514         } else {
3515                 rps->evclk = 0;
3516                 rps->ecclk = 0;
3517         }
3518
3519         if ((adev->pm.dpm.new_active_crtc_count > 1) ||
3520             si_dpm_vblank_too_short(adev))
3521                 disable_mclk_switching = true;
3522
3523         if (rps->vclk || rps->dclk) {
3524                 disable_mclk_switching = true;
3525                 disable_sclk_switching = true;
3526         }
3527
3528         if (adev->pm.dpm.ac_power)
3529                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3530         else
3531                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3532
3533         for (i = ps->performance_level_count - 2; i >= 0; i--) {
3534                 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
3535                         ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
3536         }
3537         if (adev->pm.dpm.ac_power == false) {
3538                 for (i = 0; i < ps->performance_level_count; i++) {
3539                         if (ps->performance_levels[i].mclk > max_limits->mclk)
3540                                 ps->performance_levels[i].mclk = max_limits->mclk;
3541                         if (ps->performance_levels[i].sclk > max_limits->sclk)
3542                                 ps->performance_levels[i].sclk = max_limits->sclk;
3543                         if (ps->performance_levels[i].vddc > max_limits->vddc)
3544                                 ps->performance_levels[i].vddc = max_limits->vddc;
3545                         if (ps->performance_levels[i].vddci > max_limits->vddci)
3546                                 ps->performance_levels[i].vddci = max_limits->vddci;
3547                 }
3548         }
3549
3550         /* limit clocks to max supported clocks based on voltage dependency tables */
3551         btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3552                                                         &max_sclk_vddc);
3553         btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3554                                                         &max_mclk_vddci);
3555         btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3556                                                         &max_mclk_vddc);
3557
3558         for (i = 0; i < ps->performance_level_count; i++) {
3559                 if (max_sclk_vddc) {
3560                         if (ps->performance_levels[i].sclk > max_sclk_vddc)
3561                                 ps->performance_levels[i].sclk = max_sclk_vddc;
3562                 }
3563                 if (max_mclk_vddci) {
3564                         if (ps->performance_levels[i].mclk > max_mclk_vddci)
3565                                 ps->performance_levels[i].mclk = max_mclk_vddci;
3566                 }
3567                 if (max_mclk_vddc) {
3568                         if (ps->performance_levels[i].mclk > max_mclk_vddc)
3569                                 ps->performance_levels[i].mclk = max_mclk_vddc;
3570                 }
3571                 if (max_mclk) {
3572                         if (ps->performance_levels[i].mclk > max_mclk)
3573                                 ps->performance_levels[i].mclk = max_mclk;
3574                 }
3575                 if (max_sclk) {
3576                         if (ps->performance_levels[i].sclk > max_sclk)
3577                                 ps->performance_levels[i].sclk = max_sclk;
3578                 }
3579         }
3580
3581         /* XXX validate the min clocks required for display */
3582
3583         if (disable_mclk_switching) {
3584                 mclk  = ps->performance_levels[ps->performance_level_count - 1].mclk;
3585                 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
3586         } else {
3587                 mclk = ps->performance_levels[0].mclk;
3588                 vddci = ps->performance_levels[0].vddci;
3589         }
3590
3591         if (disable_sclk_switching) {
3592                 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;
3593                 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
3594         } else {
3595                 sclk = ps->performance_levels[0].sclk;
3596                 vddc = ps->performance_levels[0].vddc;
3597         }
3598
3599         if (rps->vce_active) {
3600                 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk)
3601                         sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk;
3602                 if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk)
3603                         mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk;
3604         }
3605
3606         /* adjusted low state */
3607         ps->performance_levels[0].sclk = sclk;
3608         ps->performance_levels[0].mclk = mclk;
3609         ps->performance_levels[0].vddc = vddc;
3610         ps->performance_levels[0].vddci = vddci;
3611
3612         if (disable_sclk_switching) {
3613                 sclk = ps->performance_levels[0].sclk;
3614                 for (i = 1; i < ps->performance_level_count; i++) {
3615                         if (sclk < ps->performance_levels[i].sclk)
3616                                 sclk = ps->performance_levels[i].sclk;
3617                 }
3618                 for (i = 0; i < ps->performance_level_count; i++) {
3619                         ps->performance_levels[i].sclk = sclk;
3620                         ps->performance_levels[i].vddc = vddc;
3621                 }
3622         } else {
3623                 for (i = 1; i < ps->performance_level_count; i++) {
3624                         if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
3625                                 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
3626                         if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
3627                                 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
3628                 }
3629         }
3630
3631         if (disable_mclk_switching) {
3632                 mclk = ps->performance_levels[0].mclk;
3633                 for (i = 1; i < ps->performance_level_count; i++) {
3634                         if (mclk < ps->performance_levels[i].mclk)
3635                                 mclk = ps->performance_levels[i].mclk;
3636                 }
3637                 for (i = 0; i < ps->performance_level_count; i++) {
3638                         ps->performance_levels[i].mclk = mclk;
3639                         ps->performance_levels[i].vddci = vddci;
3640                 }
3641         } else {
3642                 for (i = 1; i < ps->performance_level_count; i++) {
3643                         if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
3644                                 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
3645                         if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
3646                                 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
3647                 }
3648         }
3649
3650         for (i = 0; i < ps->performance_level_count; i++)
3651                 btc_adjust_clock_combinations(adev, max_limits,
3652                                               &ps->performance_levels[i]);
3653
3654         for (i = 0; i < ps->performance_level_count; i++) {
3655                 if (ps->performance_levels[i].vddc < min_vce_voltage)
3656                         ps->performance_levels[i].vddc = min_vce_voltage;
3657                 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3658                                                    ps->performance_levels[i].sclk,
3659                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3660                 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3661                                                    ps->performance_levels[i].mclk,
3662                                                    max_limits->vddci, &ps->performance_levels[i].vddci);
3663                 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3664                                                    ps->performance_levels[i].mclk,
3665                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3666                 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3667                                                    adev->clock.current_dispclk,
3668                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3669         }
3670
3671         for (i = 0; i < ps->performance_level_count; i++) {
3672                 btc_apply_voltage_delta_rules(adev,
3673                                               max_limits->vddc, max_limits->vddci,
3674                                               &ps->performance_levels[i].vddc,
3675                                               &ps->performance_levels[i].vddci);
3676         }
3677
3678         ps->dc_compatible = true;
3679         for (i = 0; i < ps->performance_level_count; i++) {
3680                 if (ps->performance_levels[i].vddc > adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3681                         ps->dc_compatible = false;
3682         }
3683 }
3684
3685 #if 0
3686 static int si_read_smc_soft_register(struct amdgpu_device *adev,
3687                                      u16 reg_offset, u32 *value)
3688 {
3689         struct si_power_info *si_pi = si_get_pi(adev);
3690
3691         return amdgpu_si_read_smc_sram_dword(adev,
3692                                              si_pi->soft_regs_start + reg_offset, value,
3693                                              si_pi->sram_end);
3694 }
3695 #endif
3696
3697 static int si_write_smc_soft_register(struct amdgpu_device *adev,
3698                                       u16 reg_offset, u32 value)
3699 {
3700         struct si_power_info *si_pi = si_get_pi(adev);
3701
3702         return amdgpu_si_write_smc_sram_dword(adev,
3703                                               si_pi->soft_regs_start + reg_offset,
3704                                               value, si_pi->sram_end);
3705 }
3706
3707 static bool si_is_special_1gb_platform(struct amdgpu_device *adev)
3708 {
3709         bool ret = false;
3710         u32 tmp, width, row, column, bank, density;
3711         bool is_memory_gddr5, is_special;
3712
3713         tmp = RREG32(MC_SEQ_MISC0);
3714         is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3715         is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3716                 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3717
3718         WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3719         width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3720
3721         tmp = RREG32(MC_ARB_RAMCFG);
3722         row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
3723         column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
3724         bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3725
3726         density = (1 << (row + column - 20 + bank)) * width;
3727
3728         if ((adev->pdev->device == 0x6819) &&
3729             is_memory_gddr5 && is_special && (density == 0x400))
3730                 ret = true;
3731
3732         return ret;
3733 }
3734
3735 static void si_get_leakage_vddc(struct amdgpu_device *adev)
3736 {
3737         struct si_power_info *si_pi = si_get_pi(adev);
3738         u16 vddc, count = 0;
3739         int i, ret;
3740
3741         for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3742                 ret = amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(adev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3743
3744                 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3745                         si_pi->leakage_voltage.entries[count].voltage = vddc;
3746                         si_pi->leakage_voltage.entries[count].leakage_index =
3747                                 SISLANDS_LEAKAGE_INDEX0 + i;
3748                         count++;
3749                 }
3750         }
3751         si_pi->leakage_voltage.count = count;
3752 }
3753
3754 static int si_get_leakage_voltage_from_leakage_index(struct amdgpu_device *adev,
3755                                                      u32 index, u16 *leakage_voltage)
3756 {
3757         struct si_power_info *si_pi = si_get_pi(adev);
3758         int i;
3759
3760         if (leakage_voltage == NULL)
3761                 return -EINVAL;
3762
3763         if ((index & 0xff00) != 0xff00)
3764                 return -EINVAL;
3765
3766         if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3767                 return -EINVAL;
3768
3769         if (index < SISLANDS_LEAKAGE_INDEX0)
3770                 return -EINVAL;
3771
3772         for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3773                 if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3774                         *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3775                         return 0;
3776                 }
3777         }
3778         return -EAGAIN;
3779 }
3780
3781 static void si_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources)
3782 {
3783         struct rv7xx_power_info *pi = rv770_get_pi(adev);
3784         bool want_thermal_protection;
3785         enum amdgpu_dpm_event_src dpm_event_src;
3786
3787         switch (sources) {
3788         case 0:
3789         default:
3790                 want_thermal_protection = false;
3791                 break;
3792         case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL):
3793                 want_thermal_protection = true;
3794                 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGITAL;
3795                 break;
3796         case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3797                 want_thermal_protection = true;
3798                 dpm_event_src = AMDGPU_DPM_EVENT_SRC_EXTERNAL;
3799                 break;
3800         case ((1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3801               (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3802                 want_thermal_protection = true;
3803                 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3804                 break;
3805         }
3806
3807         if (want_thermal_protection) {
3808                 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
3809                 if (pi->thermal_protection)
3810                         WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3811         } else {
3812                 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3813         }
3814 }
3815
3816 static void si_enable_auto_throttle_source(struct amdgpu_device *adev,
3817                                            enum amdgpu_dpm_auto_throttle_src source,
3818                                            bool enable)
3819 {
3820         struct rv7xx_power_info *pi = rv770_get_pi(adev);
3821
3822         if (enable) {
3823                 if (!(pi->active_auto_throttle_sources & (1 << source))) {
3824                         pi->active_auto_throttle_sources |= 1 << source;
3825                         si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
3826                 }
3827         } else {
3828                 if (pi->active_auto_throttle_sources & (1 << source)) {
3829                         pi->active_auto_throttle_sources &= ~(1 << source);
3830                         si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
3831                 }
3832         }
3833 }
3834
3835 static void si_start_dpm(struct amdgpu_device *adev)
3836 {
3837         WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
3838 }
3839
3840 static void si_stop_dpm(struct amdgpu_device *adev)
3841 {
3842         WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3843 }
3844
3845 static void si_enable_sclk_control(struct amdgpu_device *adev, bool enable)
3846 {
3847         if (enable)
3848                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3849         else
3850                 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3851
3852 }
3853
3854 #if 0
3855 static int si_notify_hardware_of_thermal_state(struct amdgpu_device *adev,
3856                                                u32 thermal_level)
3857 {
3858         PPSMC_Result ret;
3859
3860         if (thermal_level == 0) {
3861                 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
3862                 if (ret == PPSMC_Result_OK)
3863                         return 0;
3864                 else
3865                         return -EINVAL;
3866         }
3867         return 0;
3868 }
3869
3870 static void si_notify_hardware_vpu_recovery_event(struct amdgpu_device *adev)
3871 {
3872         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3873 }
3874 #endif
3875
3876 #if 0
3877 static int si_notify_hw_of_powersource(struct amdgpu_device *adev, bool ac_power)
3878 {
3879         if (ac_power)
3880                 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3881                         0 : -EINVAL;
3882
3883         return 0;
3884 }
3885 #endif
3886
3887 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
3888                                                       PPSMC_Msg msg, u32 parameter)
3889 {
3890         WREG32(SMC_SCRATCH0, parameter);
3891         return amdgpu_si_send_msg_to_smc(adev, msg);
3892 }
3893
3894 static int si_restrict_performance_levels_before_switch(struct amdgpu_device *adev)
3895 {
3896         if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3897                 return -EINVAL;
3898
3899         return (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3900                 0 : -EINVAL;
3901 }
3902
3903 static int si_dpm_force_performance_level(struct amdgpu_device *adev,
3904                                    enum amdgpu_dpm_forced_level level)
3905 {
3906         struct amdgpu_ps *rps = adev->pm.dpm.current_ps;
3907         struct  si_ps *ps = si_get_ps(rps);
3908         u32 levels = ps->performance_level_count;
3909
3910         if (level == AMDGPU_DPM_FORCED_LEVEL_HIGH) {
3911                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3912                         return -EINVAL;
3913
3914                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3915                         return -EINVAL;
3916         } else if (level == AMDGPU_DPM_FORCED_LEVEL_LOW) {
3917                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3918                         return -EINVAL;
3919
3920                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3921                         return -EINVAL;
3922         } else if (level == AMDGPU_DPM_FORCED_LEVEL_AUTO) {
3923                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3924                         return -EINVAL;
3925
3926                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3927                         return -EINVAL;
3928         }
3929
3930         adev->pm.dpm.forced_level = level;
3931
3932         return 0;
3933 }
3934
3935 #if 0
3936 static int si_set_boot_state(struct amdgpu_device *adev)
3937 {
3938         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3939                 0 : -EINVAL;
3940 }
3941 #endif
3942
3943 static int si_set_sw_state(struct amdgpu_device *adev)
3944 {
3945         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3946                 0 : -EINVAL;
3947 }
3948
3949 static int si_halt_smc(struct amdgpu_device *adev)
3950 {
3951         if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3952                 return -EINVAL;
3953
3954         return (amdgpu_si_wait_for_smc_inactive(adev) == PPSMC_Result_OK) ?
3955                 0 : -EINVAL;
3956 }
3957
3958 static int si_resume_smc(struct amdgpu_device *adev)
3959 {
3960         if (amdgpu_si_send_msg_to_smc(adev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3961                 return -EINVAL;
3962
3963         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3964                 0 : -EINVAL;
3965 }
3966
3967 static void si_dpm_start_smc(struct amdgpu_device *adev)
3968 {
3969         amdgpu_si_program_jump_on_start(adev);
3970         amdgpu_si_start_smc(adev);
3971         amdgpu_si_smc_clock(adev, true);
3972 }
3973
3974 static void si_dpm_stop_smc(struct amdgpu_device *adev)
3975 {
3976         amdgpu_si_reset_smc(adev);
3977         amdgpu_si_smc_clock(adev, false);
3978 }
3979
3980 static int si_process_firmware_header(struct amdgpu_device *adev)
3981 {
3982         struct si_power_info *si_pi = si_get_pi(adev);
3983         u32 tmp;
3984         int ret;
3985
3986         ret = amdgpu_si_read_smc_sram_dword(adev,
3987                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3988                                             SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
3989                                             &tmp, si_pi->sram_end);
3990         if (ret)
3991                 return ret;
3992
3993         si_pi->state_table_start = tmp;
3994
3995         ret = amdgpu_si_read_smc_sram_dword(adev,
3996                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3997                                             SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
3998                                             &tmp, si_pi->sram_end);
3999         if (ret)
4000                 return ret;
4001
4002         si_pi->soft_regs_start = tmp;
4003
4004         ret = amdgpu_si_read_smc_sram_dword(adev,
4005                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4006                                             SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
4007                                             &tmp, si_pi->sram_end);
4008         if (ret)
4009                 return ret;
4010
4011         si_pi->mc_reg_table_start = tmp;
4012
4013         ret = amdgpu_si_read_smc_sram_dword(adev,
4014                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4015                                             SISLANDS_SMC_FIRMWARE_HEADER_fanTable,
4016                                             &tmp, si_pi->sram_end);
4017         if (ret)
4018                 return ret;
4019
4020         si_pi->fan_table_start = tmp;
4021
4022         ret = amdgpu_si_read_smc_sram_dword(adev,
4023                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4024                                             SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
4025                                             &tmp, si_pi->sram_end);
4026         if (ret)
4027                 return ret;
4028
4029         si_pi->arb_table_start = tmp;
4030
4031         ret = amdgpu_si_read_smc_sram_dword(adev,
4032                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4033                                             SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
4034                                             &tmp, si_pi->sram_end);
4035         if (ret)
4036                 return ret;
4037
4038         si_pi->cac_table_start = tmp;
4039
4040         ret = amdgpu_si_read_smc_sram_dword(adev,
4041                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4042                                             SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
4043                                             &tmp, si_pi->sram_end);
4044         if (ret)
4045                 return ret;
4046
4047         si_pi->dte_table_start = tmp;
4048
4049         ret = amdgpu_si_read_smc_sram_dword(adev,
4050                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4051                                             SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
4052                                             &tmp, si_pi->sram_end);
4053         if (ret)
4054                 return ret;
4055
4056         si_pi->spll_table_start = tmp;
4057
4058         ret = amdgpu_si_read_smc_sram_dword(adev,
4059                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4060                                             SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
4061                                             &tmp, si_pi->sram_end);
4062         if (ret)
4063                 return ret;
4064
4065         si_pi->papm_cfg_table_start = tmp;
4066
4067         return ret;
4068 }
4069
4070 static void si_read_clock_registers(struct amdgpu_device *adev)
4071 {
4072         struct si_power_info *si_pi = si_get_pi(adev);
4073
4074         si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
4075         si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
4076         si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
4077         si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
4078         si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
4079         si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
4080         si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
4081         si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
4082         si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
4083         si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
4084         si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
4085         si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
4086         si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
4087         si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
4088         si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
4089 }
4090
4091 static void si_enable_thermal_protection(struct amdgpu_device *adev,
4092                                           bool enable)
4093 {
4094         if (enable)
4095                 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
4096         else
4097                 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
4098 }
4099
4100 static void si_enable_acpi_power_management(struct amdgpu_device *adev)
4101 {
4102         WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
4103 }
4104
4105 #if 0
4106 static int si_enter_ulp_state(struct amdgpu_device *adev)
4107 {
4108         WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
4109
4110         udelay(25000);
4111
4112         return 0;
4113 }
4114
4115 static int si_exit_ulp_state(struct amdgpu_device *adev)
4116 {
4117         int i;
4118
4119         WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
4120
4121         udelay(7000);
4122
4123         for (i = 0; i < adev->usec_timeout; i++) {
4124                 if (RREG32(SMC_RESP_0) == 1)
4125                         break;
4126                 udelay(1000);
4127         }
4128
4129         return 0;
4130 }
4131 #endif
4132
4133 static int si_notify_smc_display_change(struct amdgpu_device *adev,
4134                                      bool has_display)
4135 {
4136         PPSMC_Msg msg = has_display ?
4137                 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
4138
4139         return (amdgpu_si_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ?
4140                 0 : -EINVAL;
4141 }
4142
4143 static void si_program_response_times(struct amdgpu_device *adev)
4144 {
4145         u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;
4146         u32 vddc_dly, acpi_dly, vbi_dly;
4147         u32 reference_clock;
4148
4149         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
4150
4151         voltage_response_time = (u32)adev->pm.dpm.voltage_response_time;
4152         backbias_response_time = (u32)adev->pm.dpm.backbias_response_time;
4153
4154         if (voltage_response_time == 0)
4155                 voltage_response_time = 1000;
4156
4157         acpi_delay_time = 15000;
4158         vbi_time_out = 100000;
4159
4160         reference_clock = amdgpu_asic_get_xclk(adev);
4161
4162         vddc_dly = (voltage_response_time  * reference_clock) / 100;
4163         acpi_dly = (acpi_delay_time * reference_clock) / 100;
4164         vbi_dly  = (vbi_time_out * reference_clock) / 100;
4165
4166         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_vreg,  vddc_dly);
4167         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_acpi,  acpi_dly);
4168         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
4169         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
4170 }
4171
4172 static void si_program_ds_registers(struct amdgpu_device *adev)
4173 {
4174         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4175         u32 tmp;
4176
4177         /* DEEP_SLEEP_CLK_SEL field should be 0x10 on tahiti A0 */
4178         if (adev->asic_type == CHIP_TAHITI && adev->rev_id == 0x0)
4179                 tmp = 0x10;
4180         else
4181                 tmp = 0x1;
4182
4183         if (eg_pi->sclk_deep_sleep) {
4184                 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
4185                 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
4186                          ~AUTOSCALE_ON_SS_CLEAR);
4187         }
4188 }
4189
4190 static void si_program_display_gap(struct amdgpu_device *adev)
4191 {
4192         u32 tmp, pipe;
4193         int i;
4194
4195         tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
4196         if (adev->pm.dpm.new_active_crtc_count > 0)
4197                 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
4198         else
4199                 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
4200
4201         if (adev->pm.dpm.new_active_crtc_count > 1)
4202                 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
4203         else
4204                 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
4205
4206         WREG32(CG_DISPLAY_GAP_CNTL, tmp);
4207
4208         tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
4209         pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
4210
4211         if ((adev->pm.dpm.new_active_crtc_count > 0) &&
4212             (!(adev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
4213                 /* find the first active crtc */
4214                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
4215                         if (adev->pm.dpm.new_active_crtcs & (1 << i))
4216                                 break;
4217                 }
4218                 if (i == adev->mode_info.num_crtc)
4219                         pipe = 0;
4220                 else
4221                         pipe = i;
4222
4223                 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
4224                 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
4225                 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
4226         }
4227
4228         /* Setting this to false forces the performance state to low if the crtcs are disabled.
4229          * This can be a problem on PowerXpress systems or if you want to use the card
4230          * for offscreen rendering or compute if there are no crtcs enabled.
4231          */
4232         si_notify_smc_display_change(adev, adev->pm.dpm.new_active_crtc_count > 0);
4233 }
4234
4235 static void si_enable_spread_spectrum(struct amdgpu_device *adev, bool enable)
4236 {
4237         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4238
4239         if (enable) {
4240                 if (pi->sclk_ss)
4241                         WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
4242         } else {
4243                 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
4244                 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
4245         }
4246 }
4247
4248 static void si_setup_bsp(struct amdgpu_device *adev)
4249 {
4250         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4251         u32 xclk = amdgpu_asic_get_xclk(adev);
4252
4253         r600_calculate_u_and_p(pi->asi,
4254                                xclk,
4255                                16,
4256                                &pi->bsp,
4257                                &pi->bsu);
4258
4259         r600_calculate_u_and_p(pi->pasi,
4260                                xclk,
4261                                16,
4262                                &pi->pbsp,
4263                                &pi->pbsu);
4264
4265
4266         pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
4267         pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
4268
4269         WREG32(CG_BSP, pi->dsp);
4270 }
4271
4272 static void si_program_git(struct amdgpu_device *adev)
4273 {
4274         WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
4275 }
4276
4277 static void si_program_tp(struct amdgpu_device *adev)
4278 {
4279         int i;
4280         enum r600_td td = R600_TD_DFLT;
4281
4282         for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
4283                 WREG32(CG_FFCT_0 + i, (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
4284
4285         if (td == R600_TD_AUTO)
4286                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
4287         else
4288                 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
4289
4290         if (td == R600_TD_UP)
4291                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
4292
4293         if (td == R600_TD_DOWN)
4294                 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
4295 }
4296
4297 static void si_program_tpp(struct amdgpu_device *adev)
4298 {
4299         WREG32(CG_TPC, R600_TPC_DFLT);
4300 }
4301
4302 static void si_program_sstp(struct amdgpu_device *adev)
4303 {
4304         WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
4305 }
4306
4307 static void si_enable_display_gap(struct amdgpu_device *adev)
4308 {
4309         u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
4310
4311         tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
4312         tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
4313                 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
4314
4315         tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
4316         tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
4317                 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
4318         WREG32(CG_DISPLAY_GAP_CNTL, tmp);
4319 }
4320
4321 static void si_program_vc(struct amdgpu_device *adev)
4322 {
4323         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4324
4325         WREG32(CG_FTV, pi->vrc);
4326 }
4327
4328 static void si_clear_vc(struct amdgpu_device *adev)
4329 {
4330         WREG32(CG_FTV, 0);
4331 }
4332
4333 static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
4334 {
4335         u8 mc_para_index;
4336
4337         if (memory_clock < 10000)
4338                 mc_para_index = 0;
4339         else if (memory_clock >= 80000)
4340                 mc_para_index = 0x0f;
4341         else
4342                 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
4343         return mc_para_index;
4344 }
4345
4346 static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
4347 {
4348         u8 mc_para_index;
4349
4350         if (strobe_mode) {
4351                 if (memory_clock < 12500)
4352                         mc_para_index = 0x00;
4353                 else if (memory_clock > 47500)
4354                         mc_para_index = 0x0f;
4355                 else
4356                         mc_para_index = (u8)((memory_clock - 10000) / 2500);
4357         } else {
4358                 if (memory_clock < 65000)
4359                         mc_para_index = 0x00;
4360                 else if (memory_clock > 135000)
4361                         mc_para_index = 0x0f;
4362                 else
4363                         mc_para_index = (u8)((memory_clock - 60000) / 5000);
4364         }
4365         return mc_para_index;
4366 }
4367
4368 static u8 si_get_strobe_mode_settings(struct amdgpu_device *adev, u32 mclk)
4369 {
4370         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4371         bool strobe_mode = false;
4372         u8 result = 0;
4373
4374         if (mclk <= pi->mclk_strobe_mode_threshold)
4375                 strobe_mode = true;
4376
4377         if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
4378                 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
4379         else
4380                 result = si_get_ddr3_mclk_frequency_ratio(mclk);
4381
4382         if (strobe_mode)
4383                 result |= SISLANDS_SMC_STROBE_ENABLE;
4384
4385         return result;
4386 }
4387
4388 static int si_upload_firmware(struct amdgpu_device *adev)
4389 {
4390         struct si_power_info *si_pi = si_get_pi(adev);
4391
4392         amdgpu_si_reset_smc(adev);
4393         amdgpu_si_smc_clock(adev, false);
4394
4395         return amdgpu_si_load_smc_ucode(adev, si_pi->sram_end);
4396 }
4397
4398 static bool si_validate_phase_shedding_tables(struct amdgpu_device *adev,
4399                                               const struct atom_voltage_table *table,
4400                                               const struct amdgpu_phase_shedding_limits_table *limits)
4401 {
4402         u32 data, num_bits, num_levels;
4403
4404         if ((table == NULL) || (limits == NULL))
4405                 return false;
4406
4407         data = table->mask_low;
4408
4409         num_bits = hweight32(data);
4410
4411         if (num_bits == 0)
4412                 return false;
4413
4414         num_levels = (1 << num_bits);
4415
4416         if (table->count != num_levels)
4417                 return false;
4418
4419         if (limits->count != (num_levels - 1))
4420                 return false;
4421
4422         return true;
4423 }
4424
4425 static void si_trim_voltage_table_to_fit_state_table(struct amdgpu_device *adev,
4426                                               u32 max_voltage_steps,
4427                                               struct atom_voltage_table *voltage_table)
4428 {
4429         unsigned int i, diff;
4430
4431         if (voltage_table->count <= max_voltage_steps)
4432                 return;
4433
4434         diff = voltage_table->count - max_voltage_steps;
4435
4436         for (i= 0; i < max_voltage_steps; i++)
4437                 voltage_table->entries[i] = voltage_table->entries[i + diff];
4438
4439         voltage_table->count = max_voltage_steps;
4440 }
4441
4442 static int si_get_svi2_voltage_table(struct amdgpu_device *adev,
4443                                      struct amdgpu_clock_voltage_dependency_table *voltage_dependency_table,
4444                                      struct atom_voltage_table *voltage_table)
4445 {
4446         u32 i;
4447
4448         if (voltage_dependency_table == NULL)
4449                 return -EINVAL;
4450
4451         voltage_table->mask_low = 0;
4452         voltage_table->phase_delay = 0;
4453
4454         voltage_table->count = voltage_dependency_table->count;
4455         for (i = 0; i < voltage_table->count; i++) {
4456                 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
4457                 voltage_table->entries[i].smio_low = 0;
4458         }
4459
4460         return 0;
4461 }
4462
4463 static int si_construct_voltage_tables(struct amdgpu_device *adev)
4464 {
4465         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4466         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4467         struct si_power_info *si_pi = si_get_pi(adev);
4468         int ret;
4469
4470         if (pi->voltage_control) {
4471                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
4472                                                     VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
4473                 if (ret)
4474                         return ret;
4475
4476                 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4477                         si_trim_voltage_table_to_fit_state_table(adev,
4478                                                                  SISLANDS_MAX_NO_VREG_STEPS,
4479                                                                  &eg_pi->vddc_voltage_table);
4480         } else if (si_pi->voltage_control_svi2) {
4481                 ret = si_get_svi2_voltage_table(adev,
4482                                                 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
4483                                                 &eg_pi->vddc_voltage_table);
4484                 if (ret)
4485                         return ret;
4486         } else {
4487                 return -EINVAL;
4488         }
4489
4490         if (eg_pi->vddci_control) {
4491                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDCI,
4492                                                     VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
4493                 if (ret)
4494                         return ret;
4495
4496                 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4497                         si_trim_voltage_table_to_fit_state_table(adev,
4498                                                                  SISLANDS_MAX_NO_VREG_STEPS,
4499                                                                  &eg_pi->vddci_voltage_table);
4500         }
4501         if (si_pi->vddci_control_svi2) {
4502                 ret = si_get_svi2_voltage_table(adev,
4503                                                 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
4504                                                 &eg_pi->vddci_voltage_table);
4505                 if (ret)
4506                         return ret;
4507         }
4508
4509         if (pi->mvdd_control) {
4510                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_MVDDC,
4511                                                     VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
4512
4513                 if (ret) {
4514                         pi->mvdd_control = false;
4515                         return ret;
4516                 }
4517
4518                 if (si_pi->mvdd_voltage_table.count == 0) {
4519                         pi->mvdd_control = false;
4520                         return -EINVAL;
4521                 }
4522
4523                 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4524                         si_trim_voltage_table_to_fit_state_table(adev,
4525                                                                  SISLANDS_MAX_NO_VREG_STEPS,
4526                                                                  &si_pi->mvdd_voltage_table);
4527         }
4528
4529         if (si_pi->vddc_phase_shed_control) {
4530                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
4531                                                     VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
4532                 if (ret)
4533                         si_pi->vddc_phase_shed_control = false;
4534
4535                 if ((si_pi->vddc_phase_shed_table.count == 0) ||
4536                     (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
4537                         si_pi->vddc_phase_shed_control = false;
4538         }
4539
4540         return 0;
4541 }
4542
4543 static void si_populate_smc_voltage_table(struct amdgpu_device *adev,
4544                                           const struct atom_voltage_table *voltage_table,
4545                                           SISLANDS_SMC_STATETABLE *table)
4546 {
4547         unsigned int i;
4548
4549         for (i = 0; i < voltage_table->count; i++)
4550                 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
4551 }
4552
4553 static int si_populate_smc_voltage_tables(struct amdgpu_device *adev,
4554                                           SISLANDS_SMC_STATETABLE *table)
4555 {
4556         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4557         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4558         struct si_power_info *si_pi = si_get_pi(adev);
4559         u8 i;
4560
4561         if (si_pi->voltage_control_svi2) {
4562                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc,
4563                         si_pi->svc_gpio_id);
4564                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd,
4565                         si_pi->svd_gpio_id);
4566                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type,
4567                                            2);
4568         } else {
4569                 if (eg_pi->vddc_voltage_table.count) {
4570                         si_populate_smc_voltage_table(adev, &eg_pi->vddc_voltage_table, table);
4571                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
4572                                 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
4573
4574                         for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
4575                                 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
4576                                         table->maxVDDCIndexInPPTable = i;
4577                                         break;
4578                                 }
4579                         }
4580                 }
4581
4582                 if (eg_pi->vddci_voltage_table.count) {
4583                         si_populate_smc_voltage_table(adev, &eg_pi->vddci_voltage_table, table);
4584
4585                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
4586                                 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
4587                 }
4588
4589
4590                 if (si_pi->mvdd_voltage_table.count) {
4591                         si_populate_smc_voltage_table(adev, &si_pi->mvdd_voltage_table, table);
4592
4593                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
4594                                 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
4595                 }
4596
4597                 if (si_pi->vddc_phase_shed_control) {
4598                         if (si_validate_phase_shedding_tables(adev, &si_pi->vddc_phase_shed_table,
4599                                                               &adev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
4600                                 si_populate_smc_voltage_table(adev, &si_pi->vddc_phase_shed_table, table);
4601
4602                                 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] =
4603                                         cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
4604
4605                                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
4606                                                            (u32)si_pi->vddc_phase_shed_table.phase_delay);
4607                         } else {
4608                                 si_pi->vddc_phase_shed_control = false;
4609                         }
4610                 }
4611         }
4612
4613         return 0;
4614 }
4615
4616 static int si_populate_voltage_value(struct amdgpu_device *adev,
4617                                      const struct atom_voltage_table *table,
4618                                      u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4619 {
4620         unsigned int i;
4621
4622         for (i = 0; i < table->count; i++) {
4623                 if (value <= table->entries[i].value) {
4624                         voltage->index = (u8)i;
4625                         voltage->value = cpu_to_be16(table->entries[i].value);
4626                         break;
4627                 }
4628         }
4629
4630         if (i >= table->count)
4631                 return -EINVAL;
4632
4633         return 0;
4634 }
4635
4636 static int si_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk,
4637                                   SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4638 {
4639         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4640         struct si_power_info *si_pi = si_get_pi(adev);
4641
4642         if (pi->mvdd_control) {
4643                 if (mclk <= pi->mvdd_split_frequency)
4644                         voltage->index = 0;
4645                 else
4646                         voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
4647
4648                 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
4649         }
4650         return 0;
4651 }
4652
4653 static int si_get_std_voltage_value(struct amdgpu_device *adev,
4654                                     SISLANDS_SMC_VOLTAGE_VALUE *voltage,
4655                                     u16 *std_voltage)
4656 {
4657         u16 v_index;
4658         bool voltage_found = false;
4659         *std_voltage = be16_to_cpu(voltage->value);
4660
4661         if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) {
4662                 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
4663                         if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
4664                                 return -EINVAL;
4665
4666                         for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4667                                 if (be16_to_cpu(voltage->value) ==
4668                                     (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4669                                         voltage_found = true;
4670                                         if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4671                                                 *std_voltage =
4672                                                         adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4673                                         else
4674                                                 *std_voltage =
4675                                                         adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4676                                         break;
4677                                 }
4678                         }
4679
4680                         if (!voltage_found) {
4681                                 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4682                                         if (be16_to_cpu(voltage->value) <=
4683                                             (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4684                                                 voltage_found = true;
4685                                                 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4686                                                         *std_voltage =
4687                                                                 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4688                                                 else
4689                                                         *std_voltage =
4690                                                                 adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4691                                                 break;
4692                                         }
4693                                 }
4694                         }
4695                 } else {
4696                         if ((u32)voltage->index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4697                                 *std_voltage = adev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4698                 }
4699         }
4700
4701         return 0;
4702 }
4703
4704 static int si_populate_std_voltage_value(struct amdgpu_device *adev,
4705                                          u16 value, u8 index,
4706                                          SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4707 {
4708         voltage->index = index;
4709         voltage->value = cpu_to_be16(value);
4710
4711         return 0;
4712 }
4713
4714 static int si_populate_phase_shedding_value(struct amdgpu_device *adev,
4715                                             const struct amdgpu_phase_shedding_limits_table *limits,
4716                                             u16 voltage, u32 sclk, u32 mclk,
4717                                             SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
4718 {
4719         unsigned int i;
4720
4721         for (i = 0; i < limits->count; i++) {
4722                 if ((voltage <= limits->entries[i].voltage) &&
4723                     (sclk <= limits->entries[i].sclk) &&
4724                     (mclk <= limits->entries[i].mclk))
4725                         break;
4726         }
4727
4728         smc_voltage->phase_settings = (u8)i;
4729
4730         return 0;
4731 }
4732
4733 static int si_init_arb_table_index(struct amdgpu_device *adev)
4734 {
4735         struct si_power_info *si_pi = si_get_pi(adev);
4736         u32 tmp;
4737         int ret;
4738
4739         ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start,
4740                                             &tmp, si_pi->sram_end);
4741         if (ret)
4742                 return ret;
4743
4744         tmp &= 0x00FFFFFF;
4745         tmp |= MC_CG_ARB_FREQ_F1 << 24;
4746
4747         return amdgpu_si_write_smc_sram_dword(adev, si_pi->arb_table_start,
4748                                               tmp, si_pi->sram_end);
4749 }
4750
4751 static int si_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev)
4752 {
4753         return ni_copy_and_switch_arb_sets(adev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4754 }
4755
4756 static int si_reset_to_default(struct amdgpu_device *adev)
4757 {
4758         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4759                 0 : -EINVAL;
4760 }
4761
4762 static int si_force_switch_to_arb_f0(struct amdgpu_device *adev)
4763 {
4764         struct si_power_info *si_pi = si_get_pi(adev);
4765         u32 tmp;
4766         int ret;
4767
4768         ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start,
4769                                             &tmp, si_pi->sram_end);
4770         if (ret)
4771                 return ret;
4772
4773         tmp = (tmp >> 24) & 0xff;
4774
4775         if (tmp == MC_CG_ARB_FREQ_F0)
4776                 return 0;
4777
4778         return ni_copy_and_switch_arb_sets(adev, tmp, MC_CG_ARB_FREQ_F0);
4779 }
4780
4781 static u32 si_calculate_memory_refresh_rate(struct amdgpu_device *adev,
4782                                             u32 engine_clock)
4783 {
4784         u32 dram_rows;
4785         u32 dram_refresh_rate;
4786         u32 mc_arb_rfsh_rate;
4787         u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4788
4789         if (tmp >= 4)
4790                 dram_rows = 16384;
4791         else
4792                 dram_rows = 1 << (tmp + 10);
4793
4794         dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4795         mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4796
4797         return mc_arb_rfsh_rate;
4798 }
4799
4800 static int si_populate_memory_timing_parameters(struct amdgpu_device *adev,
4801                                                 struct rv7xx_pl *pl,
4802                                                 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4803 {
4804         u32 dram_timing;
4805         u32 dram_timing2;
4806         u32 burst_time;
4807
4808         arb_regs->mc_arb_rfsh_rate =
4809                 (u8)si_calculate_memory_refresh_rate(adev, pl->sclk);
4810
4811         amdgpu_atombios_set_engine_dram_timings(adev,
4812                                             pl->sclk,
4813                                             pl->mclk);
4814
4815         dram_timing  = RREG32(MC_ARB_DRAM_TIMING);
4816         dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4817         burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4818
4819         arb_regs->mc_arb_dram_timing  = cpu_to_be32(dram_timing);
4820         arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4821         arb_regs->mc_arb_burst_time = (u8)burst_time;
4822
4823         return 0;
4824 }
4825
4826 static int si_do_program_memory_timing_parameters(struct amdgpu_device *adev,
4827                                                   struct amdgpu_ps *amdgpu_state,
4828                                                   unsigned int first_arb_set)
4829 {
4830         struct si_power_info *si_pi = si_get_pi(adev);
4831         struct  si_ps *state = si_get_ps(amdgpu_state);
4832         SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4833         int i, ret = 0;
4834
4835         for (i = 0; i < state->performance_level_count; i++) {
4836                 ret = si_populate_memory_timing_parameters(adev, &state->performance_levels[i], &arb_regs);
4837                 if (ret)
4838                         break;
4839                 ret = amdgpu_si_copy_bytes_to_smc(adev,
4840                                                   si_pi->arb_table_start +
4841                                                   offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4842                                                   sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4843                                                   (u8 *)&arb_regs,
4844                                                   sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4845                                                   si_pi->sram_end);
4846                 if (ret)
4847                         break;
4848         }
4849
4850         return ret;
4851 }
4852
4853 static int si_program_memory_timing_parameters(struct amdgpu_device *adev,
4854                                                struct amdgpu_ps *amdgpu_new_state)
4855 {
4856         return si_do_program_memory_timing_parameters(adev, amdgpu_new_state,
4857                                                       SISLANDS_DRIVER_STATE_ARB_INDEX);
4858 }
4859
4860 static int si_populate_initial_mvdd_value(struct amdgpu_device *adev,
4861                                           struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4862 {
4863         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4864         struct si_power_info *si_pi = si_get_pi(adev);
4865
4866         if (pi->mvdd_control)
4867                 return si_populate_voltage_value(adev, &si_pi->mvdd_voltage_table,
4868                                                  si_pi->mvdd_bootup_value, voltage);
4869
4870         return 0;
4871 }
4872
4873 static int si_populate_smc_initial_state(struct amdgpu_device *adev,
4874                                          struct amdgpu_ps *amdgpu_initial_state,
4875                                          SISLANDS_SMC_STATETABLE *table)
4876 {
4877         struct  si_ps *initial_state = si_get_ps(amdgpu_initial_state);
4878         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4879         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4880         struct si_power_info *si_pi = si_get_pi(adev);
4881         u32 reg;
4882         int ret;
4883
4884         table->initialState.levels[0].mclk.vDLL_CNTL =
4885                 cpu_to_be32(si_pi->clock_registers.dll_cntl);
4886         table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4887                 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4888         table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4889                 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4890         table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4891                 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4892         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
4893                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4894         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4895                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4896         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4897                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4898         table->initialState.levels[0].mclk.vMPLL_SS =
4899                 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4900         table->initialState.levels[0].mclk.vMPLL_SS2 =
4901                 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4902
4903         table->initialState.levels[0].mclk.mclk_value =
4904                 cpu_to_be32(initial_state->performance_levels[0].mclk);
4905
4906         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4907                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4908         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4909                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4910         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4911                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4912         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4913                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4914         table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
4915                 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4916         table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2  =
4917                 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4918
4919         table->initialState.levels[0].sclk.sclk_value =
4920                 cpu_to_be32(initial_state->performance_levels[0].sclk);
4921
4922         table->initialState.levels[0].arbRefreshState =
4923                 SISLANDS_INITIAL_STATE_ARB_INDEX;
4924
4925         table->initialState.levels[0].ACIndex = 0;
4926
4927         ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
4928                                         initial_state->performance_levels[0].vddc,
4929                                         &table->initialState.levels[0].vddc);
4930
4931         if (!ret) {
4932                 u16 std_vddc;
4933
4934                 ret = si_get_std_voltage_value(adev,
4935                                                &table->initialState.levels[0].vddc,
4936                                                &std_vddc);
4937                 if (!ret)
4938                         si_populate_std_voltage_value(adev, std_vddc,
4939                                                       table->initialState.levels[0].vddc.index,
4940                                                       &table->initialState.levels[0].std_vddc);
4941         }
4942
4943         if (eg_pi->vddci_control)
4944                 si_populate_voltage_value(adev,
4945                                           &eg_pi->vddci_voltage_table,
4946                                           initial_state->performance_levels[0].vddci,
4947                                           &table->initialState.levels[0].vddci);
4948
4949         if (si_pi->vddc_phase_shed_control)
4950                 si_populate_phase_shedding_value(adev,
4951                                                  &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
4952                                                  initial_state->performance_levels[0].vddc,
4953                                                  initial_state->performance_levels[0].sclk,
4954                                                  initial_state->performance_levels[0].mclk,
4955                                                  &table->initialState.levels[0].vddc);
4956
4957         si_populate_initial_mvdd_value(adev, &table->initialState.levels[0].mvdd);
4958
4959         reg = CG_R(0xffff) | CG_L(0);
4960         table->initialState.levels[0].aT = cpu_to_be32(reg);
4961         table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
4962         table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
4963
4964         if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
4965                 table->initialState.levels[0].strobeMode =
4966                         si_get_strobe_mode_settings(adev,
4967                                                     initial_state->performance_levels[0].mclk);
4968
4969                 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4970                         table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4971                 else
4972                         table->initialState.levels[0].mcFlags =  0;
4973         }
4974
4975         table->initialState.levelCount = 1;
4976
4977         table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4978
4979         table->initialState.levels[0].dpm2.MaxPS = 0;
4980         table->initialState.levels[0].dpm2.NearTDPDec = 0;
4981         table->initialState.levels[0].dpm2.AboveSafeInc = 0;
4982         table->initialState.levels[0].dpm2.BelowSafeInc = 0;
4983         table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4984
4985         reg = MIN_POWER_MASK | MAX_POWER_MASK;
4986         table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4987
4988         reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4989         table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4990
4991         return 0;
4992 }
4993
4994 static int si_populate_smc_acpi_state(struct amdgpu_device *adev,
4995                                       SISLANDS_SMC_STATETABLE *table)
4996 {
4997         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4998         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4999         struct si_power_info *si_pi = si_get_pi(adev);
5000         u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
5001         u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
5002         u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
5003         u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
5004         u32 dll_cntl = si_pi->clock_registers.dll_cntl;
5005         u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
5006         u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
5007         u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
5008         u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
5009         u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
5010         u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
5011         u32 reg;
5012         int ret;
5013
5014         table->ACPIState = table->initialState;
5015
5016         table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
5017
5018         if (pi->acpi_vddc) {
5019                 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
5020                                                 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
5021                 if (!ret) {
5022                         u16 std_vddc;
5023
5024                         ret = si_get_std_voltage_value(adev,
5025                                                        &table->ACPIState.levels[0].vddc, &std_vddc);
5026                         if (!ret)
5027                                 si_populate_std_voltage_value(adev, std_vddc,
5028                                                               table->ACPIState.levels[0].vddc.index,
5029                                                               &table->ACPIState.levels[0].std_vddc);
5030                 }
5031                 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
5032
5033                 if (si_pi->vddc_phase_shed_control) {
5034                         si_populate_phase_shedding_value(adev,
5035                                                          &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5036                                                          pi->acpi_vddc,
5037                                                          0,
5038                                                          0,
5039                                                          &table->ACPIState.levels[0].vddc);
5040                 }
5041         } else {
5042                 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
5043                                                 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
5044                 if (!ret) {
5045                         u16 std_vddc;
5046
5047                         ret = si_get_std_voltage_value(adev,
5048                                                        &table->ACPIState.levels[0].vddc, &std_vddc);
5049
5050                         if (!ret)
5051                                 si_populate_std_voltage_value(adev, std_vddc,
5052                                                               table->ACPIState.levels[0].vddc.index,
5053                                                               &table->ACPIState.levels[0].std_vddc);
5054                 }
5055                 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(adev,
5056                                                                                     si_pi->sys_pcie_mask,
5057                                                                                     si_pi->boot_pcie_gen,
5058                                                                                     AMDGPU_PCIE_GEN1);
5059
5060                 if (si_pi->vddc_phase_shed_control)
5061                         si_populate_phase_shedding_value(adev,
5062                                                          &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5063                                                          pi->min_vddc_in_table,
5064                                                          0,
5065                                                          0,
5066                                                          &table->ACPIState.levels[0].vddc);
5067         }
5068
5069         if (pi->acpi_vddc) {
5070                 if (eg_pi->acpi_vddci)
5071                         si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table,
5072                                                   eg_pi->acpi_vddci,
5073                                                   &table->ACPIState.levels[0].vddci);
5074         }
5075
5076         mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
5077         mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
5078
5079         dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
5080
5081         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
5082         spll_func_cntl_2 |= SCLK_MUX_SEL(4);
5083
5084         table->ACPIState.levels[0].mclk.vDLL_CNTL =
5085                 cpu_to_be32(dll_cntl);
5086         table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
5087                 cpu_to_be32(mclk_pwrmgt_cntl);
5088         table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
5089                 cpu_to_be32(mpll_ad_func_cntl);
5090         table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
5091                 cpu_to_be32(mpll_dq_func_cntl);
5092         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
5093                 cpu_to_be32(mpll_func_cntl);
5094         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
5095                 cpu_to_be32(mpll_func_cntl_1);
5096         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
5097                 cpu_to_be32(mpll_func_cntl_2);
5098         table->ACPIState.levels[0].mclk.vMPLL_SS =
5099                 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
5100         table->ACPIState.levels[0].mclk.vMPLL_SS2 =
5101                 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
5102
5103         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
5104                 cpu_to_be32(spll_func_cntl);
5105         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
5106                 cpu_to_be32(spll_func_cntl_2);
5107         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
5108                 cpu_to_be32(spll_func_cntl_3);
5109         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
5110                 cpu_to_be32(spll_func_cntl_4);
5111
5112         table->ACPIState.levels[0].mclk.mclk_value = 0;
5113         table->ACPIState.levels[0].sclk.sclk_value = 0;
5114
5115         si_populate_mvdd_value(adev, 0, &table->ACPIState.levels[0].mvdd);
5116
5117         if (eg_pi->dynamic_ac_timing)
5118                 table->ACPIState.levels[0].ACIndex = 0;
5119
5120         table->ACPIState.levels[0].dpm2.MaxPS = 0;
5121         table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
5122         table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
5123         table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
5124         table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
5125
5126         reg = MIN_POWER_MASK | MAX_POWER_MASK;
5127         table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
5128
5129         reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
5130         table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
5131
5132         return 0;
5133 }
5134
5135 static int si_populate_ulv_state(struct amdgpu_device *adev,
5136                                  SISLANDS_SMC_SWSTATE *state)
5137 {
5138         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5139         struct si_power_info *si_pi = si_get_pi(adev);
5140         struct si_ulv_param *ulv = &si_pi->ulv;
5141         u32 sclk_in_sr = 1350; /* ??? */
5142         int ret;
5143
5144         ret = si_convert_power_level_to_smc(adev, &ulv->pl,
5145                                             &state->levels[0]);
5146         if (!ret) {
5147                 if (eg_pi->sclk_deep_sleep) {
5148                         if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5149                                 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5150                         else
5151                                 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5152                 }
5153                 if (ulv->one_pcie_lane_in_ulv)
5154                         state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
5155                 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
5156                 state->levels[0].ACIndex = 1;
5157                 state->levels[0].std_vddc = state->levels[0].vddc;
5158                 state->levelCount = 1;
5159
5160                 state->flags |= PPSMC_SWSTATE_FLAG_DC;
5161         }
5162
5163         return ret;
5164 }
5165
5166 static int si_program_ulv_memory_timing_parameters(struct amdgpu_device *adev)
5167 {
5168         struct si_power_info *si_pi = si_get_pi(adev);
5169         struct si_ulv_param *ulv = &si_pi->ulv;
5170         SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
5171         int ret;
5172
5173         ret = si_populate_memory_timing_parameters(adev, &ulv->pl,
5174                                                    &arb_regs);
5175         if (ret)
5176                 return ret;
5177
5178         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
5179                                    ulv->volt_change_delay);
5180
5181         ret = amdgpu_si_copy_bytes_to_smc(adev,
5182                                           si_pi->arb_table_start +
5183                                           offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
5184                                           sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
5185                                           (u8 *)&arb_regs,
5186                                           sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
5187                                           si_pi->sram_end);
5188
5189         return ret;
5190 }
5191
5192 static void si_get_mvdd_configuration(struct amdgpu_device *adev)
5193 {
5194         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5195
5196         pi->mvdd_split_frequency = 30000;
5197 }
5198
5199 static int si_init_smc_table(struct amdgpu_device *adev)
5200 {
5201         struct si_power_info *si_pi = si_get_pi(adev);
5202         struct amdgpu_ps *amdgpu_boot_state = adev->pm.dpm.boot_ps;
5203         const struct si_ulv_param *ulv = &si_pi->ulv;
5204         SISLANDS_SMC_STATETABLE  *table = &si_pi->smc_statetable;
5205         int ret;
5206         u32 lane_width;
5207         u32 vr_hot_gpio;
5208
5209         si_populate_smc_voltage_tables(adev, table);
5210
5211         switch (adev->pm.int_thermal_type) {
5212         case THERMAL_TYPE_SI:
5213         case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
5214                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
5215                 break;
5216         case THERMAL_TYPE_NONE:
5217                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
5218                 break;
5219         default:
5220                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
5221                 break;
5222         }
5223
5224         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
5225                 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
5226
5227         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
5228                 if ((adev->pdev->device != 0x6818) && (adev->pdev->device != 0x6819))
5229                         table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
5230         }
5231
5232         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
5233                 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
5234
5235         if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
5236                 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
5237
5238         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
5239                 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
5240
5241         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
5242                 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
5243                 vr_hot_gpio = adev->pm.dpm.backbias_response_time;
5244                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
5245                                            vr_hot_gpio);
5246         }
5247
5248         ret = si_populate_smc_initial_state(adev, amdgpu_boot_state, table);
5249         if (ret)
5250                 return ret;
5251
5252         ret = si_populate_smc_acpi_state(adev, table);
5253         if (ret)
5254                 return ret;
5255
5256         table->driverState = table->initialState;
5257
5258         ret = si_do_program_memory_timing_parameters(adev, amdgpu_boot_state,
5259                                                      SISLANDS_INITIAL_STATE_ARB_INDEX);
5260         if (ret)
5261                 return ret;
5262
5263         if (ulv->supported && ulv->pl.vddc) {
5264                 ret = si_populate_ulv_state(adev, &table->ULVState);
5265                 if (ret)
5266                         return ret;
5267
5268                 ret = si_program_ulv_memory_timing_parameters(adev);
5269                 if (ret)
5270                         return ret;
5271
5272                 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
5273                 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
5274
5275                 lane_width = amdgpu_get_pcie_lanes(adev);
5276                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5277         } else {
5278                 table->ULVState = table->initialState;
5279         }
5280
5281         return amdgpu_si_copy_bytes_to_smc(adev, si_pi->state_table_start,
5282                                            (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
5283                                            si_pi->sram_end);
5284 }
5285
5286 static int si_calculate_sclk_params(struct amdgpu_device *adev,
5287                                     u32 engine_clock,
5288                                     SISLANDS_SMC_SCLK_VALUE *sclk)
5289 {
5290         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5291         struct si_power_info *si_pi = si_get_pi(adev);
5292         struct atom_clock_dividers dividers;
5293         u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
5294         u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
5295         u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
5296         u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
5297         u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
5298         u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
5299         u64 tmp;
5300         u32 reference_clock = adev->clock.spll.reference_freq;
5301         u32 reference_divider;
5302         u32 fbdiv;
5303         int ret;
5304
5305         ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
5306                                              engine_clock, false, &dividers);
5307         if (ret)
5308                 return ret;
5309
5310         reference_divider = 1 + dividers.ref_div;
5311
5312         tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
5313         do_div(tmp, reference_clock);
5314         fbdiv = (u32) tmp;
5315
5316         spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
5317         spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
5318         spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
5319
5320         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
5321         spll_func_cntl_2 |= SCLK_MUX_SEL(2);
5322
5323         spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
5324         spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
5325         spll_func_cntl_3 |= SPLL_DITHEN;
5326
5327         if (pi->sclk_ss) {
5328                 struct amdgpu_atom_ss ss;
5329                 u32 vco_freq = engine_clock * dividers.post_div;
5330
5331                 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
5332                                                      ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
5333                         u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
5334                         u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
5335
5336                         cg_spll_spread_spectrum &= ~CLK_S_MASK;
5337                         cg_spll_spread_spectrum |= CLK_S(clk_s);
5338                         cg_spll_spread_spectrum |= SSEN;
5339
5340                         cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
5341                         cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
5342                 }
5343         }
5344
5345         sclk->sclk_value = engine_clock;
5346         sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
5347         sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
5348         sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
5349         sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
5350         sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
5351         sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
5352
5353         return 0;
5354 }
5355
5356 static int si_populate_sclk_value(struct amdgpu_device *adev,
5357                                   u32 engine_clock,
5358                                   SISLANDS_SMC_SCLK_VALUE *sclk)
5359 {
5360         SISLANDS_SMC_SCLK_VALUE sclk_tmp;
5361         int ret;
5362
5363         ret = si_calculate_sclk_params(adev, engine_clock, &sclk_tmp);
5364         if (!ret) {
5365                 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
5366                 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
5367                 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
5368                 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
5369                 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
5370                 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
5371                 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
5372         }
5373
5374         return ret;
5375 }
5376
5377 static int si_populate_mclk_value(struct amdgpu_device *adev,
5378                                   u32 engine_clock,
5379                                   u32 memory_clock,
5380                                   SISLANDS_SMC_MCLK_VALUE *mclk,
5381                                   bool strobe_mode,
5382                                   bool dll_state_on)
5383 {
5384         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5385         struct si_power_info *si_pi = si_get_pi(adev);
5386         u32  dll_cntl = si_pi->clock_registers.dll_cntl;
5387         u32  mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
5388         u32  mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
5389         u32  mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
5390         u32  mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
5391         u32  mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
5392         u32  mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
5393         u32  mpll_ss1 = si_pi->clock_registers.mpll_ss1;
5394         u32  mpll_ss2 = si_pi->clock_registers.mpll_ss2;
5395         struct atom_mpll_param mpll_param;
5396         int ret;
5397
5398         ret = amdgpu_atombios_get_memory_pll_dividers(adev, memory_clock, strobe_mode, &mpll_param);
5399         if (ret)
5400                 return ret;
5401
5402         mpll_func_cntl &= ~BWCTRL_MASK;
5403         mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
5404
5405         mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
5406         mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
5407                 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
5408
5409         mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
5410         mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
5411
5412         if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
5413                 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
5414                 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
5415                         YCLK_POST_DIV(mpll_param.post_div);
5416         }
5417
5418         if (pi->mclk_ss) {
5419                 struct amdgpu_atom_ss ss;
5420                 u32 freq_nom;
5421                 u32 tmp;
5422                 u32 reference_clock = adev->clock.mpll.reference_freq;
5423
5424                 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
5425                         freq_nom = memory_clock * 4;
5426                 else
5427                         freq_nom = memory_clock * 2;
5428
5429                 tmp = freq_nom / reference_clock;
5430                 tmp = tmp * tmp;
5431                 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
5432                                                      ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
5433                         u32 clks = reference_clock * 5 / ss.rate;
5434                         u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
5435
5436                         mpll_ss1 &= ~CLKV_MASK;
5437                         mpll_ss1 |= CLKV(clkv);
5438
5439                         mpll_ss2 &= ~CLKS_MASK;
5440                         mpll_ss2 |= CLKS(clks);
5441                 }
5442         }
5443
5444         mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
5445         mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
5446
5447         if (dll_state_on)
5448                 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
5449         else
5450                 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
5451
5452         mclk->mclk_value = cpu_to_be32(memory_clock);
5453         mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
5454         mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
5455         mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
5456         mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
5457         mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
5458         mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
5459         mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
5460         mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
5461         mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
5462
5463         return 0;
5464 }
5465
5466 static void si_populate_smc_sp(struct amdgpu_device *adev,
5467                                struct amdgpu_ps *amdgpu_state,
5468                                SISLANDS_SMC_SWSTATE *smc_state)
5469 {
5470         struct  si_ps *ps = si_get_ps(amdgpu_state);
5471         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5472         int i;
5473
5474         for (i = 0; i < ps->performance_level_count - 1; i++)
5475                 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
5476
5477         smc_state->levels[ps->performance_level_count - 1].bSP =
5478                 cpu_to_be32(pi->psp);
5479 }
5480
5481 static int si_convert_power_level_to_smc(struct amdgpu_device *adev,
5482                                          struct rv7xx_pl *pl,
5483                                          SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
5484 {
5485         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5486         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5487         struct si_power_info *si_pi = si_get_pi(adev);
5488         int ret;
5489         bool dll_state_on;
5490         u16 std_vddc;
5491         bool gmc_pg = false;
5492
5493         if (eg_pi->pcie_performance_request &&
5494             (si_pi->force_pcie_gen != AMDGPU_PCIE_GEN_INVALID))
5495                 level->gen2PCIE = (u8)si_pi->force_pcie_gen;
5496         else
5497                 level->gen2PCIE = (u8)pl->pcie_gen;
5498
5499         ret = si_populate_sclk_value(adev, pl->sclk, &level->sclk);
5500         if (ret)
5501                 return ret;
5502
5503         level->mcFlags =  0;
5504
5505         if (pi->mclk_stutter_mode_threshold &&
5506             (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
5507             !eg_pi->uvd_enabled &&
5508             (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
5509             (adev->pm.dpm.new_active_crtc_count <= 2)) {
5510                 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
5511
5512                 if (gmc_pg)
5513                         level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
5514         }
5515
5516         if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
5517                 if (pl->mclk > pi->mclk_edc_enable_threshold)
5518                         level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
5519
5520                 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
5521                         level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
5522
5523                 level->strobeMode = si_get_strobe_mode_settings(adev, pl->mclk);
5524
5525                 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
5526                         if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
5527                             ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
5528                                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5529                         else
5530                                 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
5531                 } else {
5532                         dll_state_on = false;
5533                 }
5534         } else {
5535                 level->strobeMode = si_get_strobe_mode_settings(adev,
5536                                                                 pl->mclk);
5537
5538                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5539         }
5540
5541         ret = si_populate_mclk_value(adev,
5542                                      pl->sclk,
5543                                      pl->mclk,
5544                                      &level->mclk,
5545                                      (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
5546         if (ret)
5547                 return ret;
5548
5549         ret = si_populate_voltage_value(adev,
5550                                         &eg_pi->vddc_voltage_table,
5551                                         pl->vddc, &level->vddc);
5552         if (ret)
5553                 return ret;
5554
5555
5556         ret = si_get_std_voltage_value(adev, &level->vddc, &std_vddc);
5557         if (ret)
5558                 return ret;
5559
5560         ret = si_populate_std_voltage_value(adev, std_vddc,
5561                                             level->vddc.index, &level->std_vddc);
5562         if (ret)
5563                 return ret;
5564
5565         if (eg_pi->vddci_control) {
5566                 ret = si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table,
5567                                                 pl->vddci, &level->vddci);
5568                 if (ret)
5569                         return ret;
5570         }
5571
5572         if (si_pi->vddc_phase_shed_control) {
5573                 ret = si_populate_phase_shedding_value(adev,
5574                                                        &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5575                                                        pl->vddc,
5576                                                        pl->sclk,
5577                                                        pl->mclk,
5578                                                        &level->vddc);
5579                 if (ret)
5580                         return ret;
5581         }
5582
5583         level->MaxPoweredUpCU = si_pi->max_cu;
5584
5585         ret = si_populate_mvdd_value(adev, pl->mclk, &level->mvdd);
5586
5587         return ret;
5588 }
5589
5590 static int si_populate_smc_t(struct amdgpu_device *adev,
5591                              struct amdgpu_ps *amdgpu_state,
5592                              SISLANDS_SMC_SWSTATE *smc_state)
5593 {
5594         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5595         struct  si_ps *state = si_get_ps(amdgpu_state);
5596         u32 a_t;
5597         u32 t_l, t_h;
5598         u32 high_bsp;
5599         int i, ret;
5600
5601         if (state->performance_level_count >= 9)
5602                 return -EINVAL;
5603
5604         if (state->performance_level_count < 2) {
5605                 a_t = CG_R(0xffff) | CG_L(0);
5606                 smc_state->levels[0].aT = cpu_to_be32(a_t);
5607                 return 0;
5608         }
5609
5610         smc_state->levels[0].aT = cpu_to_be32(0);
5611
5612         for (i = 0; i <= state->performance_level_count - 2; i++) {
5613                 ret = r600_calculate_at(
5614                         (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
5615                         100 * R600_AH_DFLT,
5616                         state->performance_levels[i + 1].sclk,
5617                         state->performance_levels[i].sclk,
5618                         &t_l,
5619                         &t_h);
5620
5621                 if (ret) {
5622                         t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
5623                         t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
5624                 }
5625
5626                 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
5627                 a_t |= CG_R(t_l * pi->bsp / 20000);
5628                 smc_state->levels[i].aT = cpu_to_be32(a_t);
5629
5630                 high_bsp = (i == state->performance_level_count - 2) ?
5631                         pi->pbsp : pi->bsp;
5632                 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
5633                 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
5634         }
5635
5636         return 0;
5637 }
5638
5639 static int si_disable_ulv(struct amdgpu_device *adev)
5640 {
5641         struct si_power_info *si_pi = si_get_pi(adev);
5642         struct si_ulv_param *ulv = &si_pi->ulv;
5643
5644         if (ulv->supported)
5645                 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
5646                         0 : -EINVAL;
5647
5648         return 0;
5649 }
5650
5651 static bool si_is_state_ulv_compatible(struct amdgpu_device *adev,
5652                                        struct amdgpu_ps *amdgpu_state)
5653 {
5654         const struct si_power_info *si_pi = si_get_pi(adev);
5655         const struct si_ulv_param *ulv = &si_pi->ulv;
5656         const struct  si_ps *state = si_get_ps(amdgpu_state);
5657         int i;
5658
5659         if (state->performance_levels[0].mclk != ulv->pl.mclk)
5660                 return false;
5661
5662         /* XXX validate against display requirements! */
5663
5664         for (i = 0; i < adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
5665                 if (adev->clock.current_dispclk <=
5666                     adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
5667                         if (ulv->pl.vddc <
5668                             adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
5669                                 return false;
5670                 }
5671         }
5672
5673         if ((amdgpu_state->vclk != 0) || (amdgpu_state->dclk != 0))
5674                 return false;
5675
5676         return true;
5677 }
5678
5679 static int si_set_power_state_conditionally_enable_ulv(struct amdgpu_device *adev,
5680                                                        struct amdgpu_ps *amdgpu_new_state)
5681 {
5682         const struct si_power_info *si_pi = si_get_pi(adev);
5683         const struct si_ulv_param *ulv = &si_pi->ulv;
5684
5685         if (ulv->supported) {
5686                 if (si_is_state_ulv_compatible(adev, amdgpu_new_state))
5687                         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
5688                                 0 : -EINVAL;
5689         }
5690         return 0;
5691 }
5692
5693 static int si_convert_power_state_to_smc(struct amdgpu_device *adev,
5694                                          struct amdgpu_ps *amdgpu_state,
5695                                          SISLANDS_SMC_SWSTATE *smc_state)
5696 {
5697         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5698         struct ni_power_info *ni_pi = ni_get_pi(adev);
5699         struct si_power_info *si_pi = si_get_pi(adev);
5700         struct  si_ps *state = si_get_ps(amdgpu_state);
5701         int i, ret;
5702         u32 threshold;
5703         u32 sclk_in_sr = 1350; /* ??? */
5704
5705         if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
5706                 return -EINVAL;
5707
5708         threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
5709
5710         if (amdgpu_state->vclk && amdgpu_state->dclk) {
5711                 eg_pi->uvd_enabled = true;
5712                 if (eg_pi->smu_uvd_hs)
5713                         smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
5714         } else {
5715                 eg_pi->uvd_enabled = false;
5716         }
5717
5718         if (state->dc_compatible)
5719                 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
5720
5721         smc_state->levelCount = 0;
5722         for (i = 0; i < state->performance_level_count; i++) {
5723                 if (eg_pi->sclk_deep_sleep) {
5724                         if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
5725                                 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5726                                         smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5727                                 else
5728                                         smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5729                         }
5730                 }
5731
5732                 ret = si_convert_power_level_to_smc(adev, &state->performance_levels[i],
5733                                                     &smc_state->levels[i]);
5734                 smc_state->levels[i].arbRefreshState =
5735                         (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
5736
5737                 if (ret)
5738                         return ret;
5739
5740                 if (ni_pi->enable_power_containment)
5741                         smc_state->levels[i].displayWatermark =
5742                                 (state->performance_levels[i].sclk < threshold) ?
5743                                 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5744                 else
5745                         smc_state->levels[i].displayWatermark = (i < 2) ?
5746                                 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5747
5748                 if (eg_pi->dynamic_ac_timing)
5749                         smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5750                 else
5751                         smc_state->levels[i].ACIndex = 0;
5752
5753                 smc_state->levelCount++;
5754         }
5755
5756         si_write_smc_soft_register(adev,
5757                                    SI_SMC_SOFT_REGISTER_watermark_threshold,
5758                                    threshold / 512);
5759
5760         si_populate_smc_sp(adev, amdgpu_state, smc_state);
5761
5762         ret = si_populate_power_containment_values(adev, amdgpu_state, smc_state);
5763         if (ret)
5764                 ni_pi->enable_power_containment = false;
5765
5766         ret = si_populate_sq_ramping_values(adev, amdgpu_state, smc_state);
5767         if (ret)
5768                 ni_pi->enable_sq_ramping = false;
5769
5770         return si_populate_smc_t(adev, amdgpu_state, smc_state);
5771 }
5772
5773 static int si_upload_sw_state(struct amdgpu_device *adev,
5774                               struct amdgpu_ps *amdgpu_new_state)
5775 {
5776         struct si_power_info *si_pi = si_get_pi(adev);
5777         struct  si_ps *new_state = si_get_ps(amdgpu_new_state);
5778         int ret;
5779         u32 address = si_pi->state_table_start +
5780                 offsetof(SISLANDS_SMC_STATETABLE, driverState);
5781         u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +
5782                 ((new_state->performance_level_count - 1) *
5783                  sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL));
5784         SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5785
5786         memset(smc_state, 0, state_size);
5787
5788         ret = si_convert_power_state_to_smc(adev, amdgpu_new_state, smc_state);
5789         if (ret)
5790                 return ret;
5791
5792         return amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
5793                                            state_size, si_pi->sram_end);
5794 }
5795
5796 static int si_upload_ulv_state(struct amdgpu_device *adev)
5797 {
5798         struct si_power_info *si_pi = si_get_pi(adev);
5799         struct si_ulv_param *ulv = &si_pi->ulv;
5800         int ret = 0;
5801
5802         if (ulv->supported && ulv->pl.vddc) {
5803                 u32 address = si_pi->state_table_start +
5804                         offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5805                 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;
5806                 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);
5807
5808                 memset(smc_state, 0, state_size);
5809
5810                 ret = si_populate_ulv_state(adev, smc_state);
5811                 if (!ret)
5812                         ret = amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
5813                                                           state_size, si_pi->sram_end);
5814         }
5815
5816         return ret;
5817 }
5818
5819 static int si_upload_smc_data(struct amdgpu_device *adev)
5820 {
5821         struct amdgpu_crtc *amdgpu_crtc = NULL;
5822         int i;
5823
5824         if (adev->pm.dpm.new_active_crtc_count == 0)
5825                 return 0;
5826
5827         for (i = 0; i < adev->mode_info.num_crtc; i++) {
5828                 if (adev->pm.dpm.new_active_crtcs & (1 << i)) {
5829                         amdgpu_crtc = adev->mode_info.crtcs[i];
5830                         break;
5831                 }
5832         }
5833
5834         if (amdgpu_crtc == NULL)
5835                 return 0;
5836
5837         if (amdgpu_crtc->line_time <= 0)
5838                 return 0;
5839
5840         if (si_write_smc_soft_register(adev,
5841                                        SI_SMC_SOFT_REGISTER_crtc_index,
5842                                        amdgpu_crtc->crtc_id) != PPSMC_Result_OK)
5843                 return 0;
5844
5845         if (si_write_smc_soft_register(adev,
5846                                        SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5847                                        amdgpu_crtc->wm_high / amdgpu_crtc->line_time) != PPSMC_Result_OK)
5848                 return 0;
5849
5850         if (si_write_smc_soft_register(adev,
5851                                        SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5852                                        amdgpu_crtc->wm_low / amdgpu_crtc->line_time) != PPSMC_Result_OK)
5853                 return 0;
5854
5855         return 0;
5856 }
5857
5858 static int si_set_mc_special_registers(struct amdgpu_device *adev,
5859                                        struct si_mc_reg_table *table)
5860 {
5861         u8 i, j, k;
5862         u32 temp_reg;
5863
5864         for (i = 0, j = table->last; i < table->last; i++) {
5865                 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5866                         return -EINVAL;
5867                 switch (table->mc_reg_address[i].s1) {
5868                 case MC_SEQ_MISC1:
5869                         temp_reg = RREG32(MC_PMG_CMD_EMRS);
5870                         table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS;
5871                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP;
5872                         for (k = 0; k < table->num_entries; k++)
5873                                 table->mc_reg_table_entry[k].mc_data[j] =
5874                                         ((temp_reg & 0xffff0000)) |
5875                                         ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5876                         j++;
5877                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5878                                 return -EINVAL;
5879
5880                         temp_reg = RREG32(MC_PMG_CMD_MRS);
5881                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS;
5882                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP;
5883                         for (k = 0; k < table->num_entries; k++) {
5884                                 table->mc_reg_table_entry[k].mc_data[j] =
5885                                         (temp_reg & 0xffff0000) |
5886                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5887                                 if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5)
5888                                         table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5889                         }
5890                         j++;
5891                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5892                                 return -EINVAL;
5893
5894                         if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) {
5895                                 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD;
5896                                 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD;
5897                                 for (k = 0; k < table->num_entries; k++)
5898                                         table->mc_reg_table_entry[k].mc_data[j] =
5899                                                 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5900                                 j++;
5901                                 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5902                                         return -EINVAL;
5903                         }
5904                         break;
5905                 case MC_SEQ_RESERVE_M:
5906                         temp_reg = RREG32(MC_PMG_CMD_MRS1);
5907                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1;
5908                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP;
5909                         for(k = 0; k < table->num_entries; k++)
5910                                 table->mc_reg_table_entry[k].mc_data[j] =
5911                                         (temp_reg & 0xffff0000) |
5912                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5913                         j++;
5914                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5915                                 return -EINVAL;
5916                         break;
5917                 default:
5918                         break;
5919                 }
5920         }
5921
5922         table->last = j;
5923
5924         return 0;
5925 }
5926
5927 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5928 {
5929         bool result = true;
5930         switch (in_reg) {
5931         case  MC_SEQ_RAS_TIMING:
5932                 *out_reg = MC_SEQ_RAS_TIMING_LP;
5933                 break;
5934         case MC_SEQ_CAS_TIMING:
5935                 *out_reg = MC_SEQ_CAS_TIMING_LP;
5936                 break;
5937         case MC_SEQ_MISC_TIMING:
5938                 *out_reg = MC_SEQ_MISC_TIMING_LP;
5939                 break;
5940         case MC_SEQ_MISC_TIMING2:
5941                 *out_reg = MC_SEQ_MISC_TIMING2_LP;
5942                 break;
5943         case MC_SEQ_RD_CTL_D0:
5944                 *out_reg = MC_SEQ_RD_CTL_D0_LP;
5945                 break;
5946         case MC_SEQ_RD_CTL_D1:
5947                 *out_reg = MC_SEQ_RD_CTL_D1_LP;
5948                 break;
5949         case MC_SEQ_WR_CTL_D0:
5950                 *out_reg = MC_SEQ_WR_CTL_D0_LP;
5951                 break;
5952         case MC_SEQ_WR_CTL_D1:
5953                 *out_reg = MC_SEQ_WR_CTL_D1_LP;
5954                 break;
5955         case MC_PMG_CMD_EMRS:
5956                 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP;
5957                 break;
5958         case MC_PMG_CMD_MRS:
5959                 *out_reg = MC_SEQ_PMG_CMD_MRS_LP;
5960                 break;
5961         case MC_PMG_CMD_MRS1:
5962                 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP;
5963                 break;
5964         case MC_SEQ_PMG_TIMING:
5965                 *out_reg = MC_SEQ_PMG_TIMING_LP;
5966                 break;
5967         case MC_PMG_CMD_MRS2:
5968                 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP;
5969                 break;
5970         case MC_SEQ_WR_CTL_2:
5971                 *out_reg = MC_SEQ_WR_CTL_2_LP;
5972                 break;
5973         default:
5974                 result = false;
5975                 break;
5976         }
5977
5978         return result;
5979 }
5980
5981 static void si_set_valid_flag(struct si_mc_reg_table *table)
5982 {
5983         u8 i, j;
5984
5985         for (i = 0; i < table->last; i++) {
5986                 for (j = 1; j < table->num_entries; j++) {
5987                         if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
5988                                 table->valid_flag |= 1 << i;
5989                                 break;
5990                         }
5991                 }
5992         }
5993 }
5994
5995 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
5996 {
5997         u32 i;
5998         u16 address;
5999
6000         for (i = 0; i < table->last; i++)
6001                 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
6002                         address : table->mc_reg_address[i].s1;
6003
6004 }
6005
6006 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
6007                                       struct si_mc_reg_table *si_table)
6008 {
6009         u8 i, j;
6010
6011         if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
6012                 return -EINVAL;
6013         if (table->num_entries > MAX_AC_TIMING_ENTRIES)
6014                 return -EINVAL;
6015
6016         for (i = 0; i < table->last; i++)
6017                 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
6018         si_table->last = table->last;
6019
6020         for (i = 0; i < table->num_entries; i++) {
6021                 si_table->mc_reg_table_entry[i].mclk_max =
6022                         table->mc_reg_table_entry[i].mclk_max;
6023                 for (j = 0; j < table->last; j++) {
6024                         si_table->mc_reg_table_entry[i].mc_data[j] =
6025                                 table->mc_reg_table_entry[i].mc_data[j];
6026                 }
6027         }
6028         si_table->num_entries = table->num_entries;
6029
6030         return 0;
6031 }
6032
6033 static int si_initialize_mc_reg_table(struct amdgpu_device *adev)
6034 {
6035         struct si_power_info *si_pi = si_get_pi(adev);
6036         struct atom_mc_reg_table *table;
6037         struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
6038         u8 module_index = rv770_get_memory_module_index(adev);
6039         int ret;
6040
6041         table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
6042         if (!table)
6043                 return -ENOMEM;
6044
6045         WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
6046         WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
6047         WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
6048         WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
6049         WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
6050         WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
6051         WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
6052         WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
6053         WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
6054         WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
6055         WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
6056         WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
6057         WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
6058         WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
6059
6060         ret = amdgpu_atombios_init_mc_reg_table(adev, module_index, table);
6061         if (ret)
6062                 goto init_mc_done;
6063
6064         ret = si_copy_vbios_mc_reg_table(table, si_table);
6065         if (ret)
6066                 goto init_mc_done;
6067
6068         si_set_s0_mc_reg_index(si_table);
6069
6070         ret = si_set_mc_special_registers(adev, si_table);
6071         if (ret)
6072                 goto init_mc_done;
6073
6074         si_set_valid_flag(si_table);
6075
6076 init_mc_done:
6077         kfree(table);
6078
6079         return ret;
6080
6081 }
6082
6083 static void si_populate_mc_reg_addresses(struct amdgpu_device *adev,
6084                                          SMC_SIslands_MCRegisters *mc_reg_table)
6085 {
6086         struct si_power_info *si_pi = si_get_pi(adev);
6087         u32 i, j;
6088
6089         for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
6090                 if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
6091                         if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
6092                                 break;
6093                         mc_reg_table->address[i].s0 =
6094                                 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
6095                         mc_reg_table->address[i].s1 =
6096                                 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
6097                         i++;
6098                 }
6099         }
6100         mc_reg_table->last = (u8)i;
6101 }
6102
6103 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
6104                                     SMC_SIslands_MCRegisterSet *data,
6105                                     u32 num_entries, u32 valid_flag)
6106 {
6107         u32 i, j;
6108
6109         for(i = 0, j = 0; j < num_entries; j++) {
6110                 if (valid_flag & (1 << j)) {
6111                         data->value[i] = cpu_to_be32(entry->mc_data[j]);
6112                         i++;
6113                 }
6114         }
6115 }
6116
6117 static void si_convert_mc_reg_table_entry_to_smc(struct amdgpu_device *adev,
6118                                                  struct rv7xx_pl *pl,
6119                                                  SMC_SIslands_MCRegisterSet *mc_reg_table_data)
6120 {
6121         struct si_power_info *si_pi = si_get_pi(adev);
6122         u32 i = 0;
6123
6124         for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
6125                 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
6126                         break;
6127         }
6128
6129         if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
6130                 --i;
6131
6132         si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
6133                                 mc_reg_table_data, si_pi->mc_reg_table.last,
6134                                 si_pi->mc_reg_table.valid_flag);
6135 }
6136
6137 static void si_convert_mc_reg_table_to_smc(struct amdgpu_device *adev,
6138                                            struct amdgpu_ps *amdgpu_state,
6139                                            SMC_SIslands_MCRegisters *mc_reg_table)
6140 {
6141         struct si_ps *state = si_get_ps(amdgpu_state);
6142         int i;
6143
6144         for (i = 0; i < state->performance_level_count; i++) {
6145                 si_convert_mc_reg_table_entry_to_smc(adev,
6146                                                      &state->performance_levels[i],
6147                                                      &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
6148         }
6149 }
6150
6151 static int si_populate_mc_reg_table(struct amdgpu_device *adev,
6152                                     struct amdgpu_ps *amdgpu_boot_state)
6153 {
6154         struct  si_ps *boot_state = si_get_ps(amdgpu_boot_state);
6155         struct si_power_info *si_pi = si_get_pi(adev);
6156         struct si_ulv_param *ulv = &si_pi->ulv;
6157         SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
6158
6159         memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
6160
6161         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_seq_index, 1);
6162
6163         si_populate_mc_reg_addresses(adev, smc_mc_reg_table);
6164
6165         si_convert_mc_reg_table_entry_to_smc(adev, &boot_state->performance_levels[0],
6166                                              &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
6167
6168         si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
6169                                 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
6170                                 si_pi->mc_reg_table.last,
6171                                 si_pi->mc_reg_table.valid_flag);
6172
6173         if (ulv->supported && ulv->pl.vddc != 0)
6174                 si_convert_mc_reg_table_entry_to_smc(adev, &ulv->pl,
6175                                                      &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
6176         else
6177                 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
6178                                         &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
6179                                         si_pi->mc_reg_table.last,
6180                                         si_pi->mc_reg_table.valid_flag);
6181
6182         si_convert_mc_reg_table_to_smc(adev, amdgpu_boot_state, smc_mc_reg_table);
6183
6184         return amdgpu_si_copy_bytes_to_smc(adev, si_pi->mc_reg_table_start,
6185                                            (u8 *)smc_mc_reg_table,
6186                                            sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
6187 }
6188
6189 static int si_upload_mc_reg_table(struct amdgpu_device *adev,
6190                                   struct amdgpu_ps *amdgpu_new_state)
6191 {
6192         struct si_ps *new_state = si_get_ps(amdgpu_new_state);
6193         struct si_power_info *si_pi = si_get_pi(adev);
6194         u32 address = si_pi->mc_reg_table_start +
6195                 offsetof(SMC_SIslands_MCRegisters,
6196                          data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
6197         SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
6198
6199         memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
6200
6201         si_convert_mc_reg_table_to_smc(adev, amdgpu_new_state, smc_mc_reg_table);
6202
6203         return amdgpu_si_copy_bytes_to_smc(adev, address,
6204                                            (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
6205                                            sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
6206                                            si_pi->sram_end);
6207 }
6208
6209 static void si_enable_voltage_control(struct amdgpu_device *adev, bool enable)
6210 {
6211         if (enable)
6212                 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
6213         else
6214                 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
6215 }
6216
6217 static enum amdgpu_pcie_gen si_get_maximum_link_speed(struct amdgpu_device *adev,
6218                                                       struct amdgpu_ps *amdgpu_state)
6219 {
6220         struct si_ps *state = si_get_ps(amdgpu_state);
6221         int i;
6222         u16 pcie_speed, max_speed = 0;
6223
6224         for (i = 0; i < state->performance_level_count; i++) {
6225                 pcie_speed = state->performance_levels[i].pcie_gen;
6226                 if (max_speed < pcie_speed)
6227                         max_speed = pcie_speed;
6228         }
6229         return max_speed;
6230 }
6231
6232 static u16 si_get_current_pcie_speed(struct amdgpu_device *adev)
6233 {
6234         u32 speed_cntl;
6235
6236         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
6237         speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
6238
6239         return (u16)speed_cntl;
6240 }
6241
6242 static void si_request_link_speed_change_before_state_change(struct amdgpu_device *adev,
6243                                                              struct amdgpu_ps *amdgpu_new_state,
6244                                                              struct amdgpu_ps *amdgpu_current_state)
6245 {
6246         struct si_power_info *si_pi = si_get_pi(adev);
6247         enum amdgpu_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state);
6248         enum amdgpu_pcie_gen current_link_speed;
6249
6250         if (si_pi->force_pcie_gen == AMDGPU_PCIE_GEN_INVALID)
6251                 current_link_speed = si_get_maximum_link_speed(adev, amdgpu_current_state);
6252         else
6253                 current_link_speed = si_pi->force_pcie_gen;
6254
6255         si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
6256         si_pi->pspp_notify_required = false;
6257         if (target_link_speed > current_link_speed) {
6258                 switch (target_link_speed) {
6259 #if defined(CONFIG_ACPI)
6260                 case AMDGPU_PCIE_GEN3:
6261                         if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
6262                                 break;
6263                         si_pi->force_pcie_gen = AMDGPU_PCIE_GEN2;
6264                         if (current_link_speed == AMDGPU_PCIE_GEN2)
6265                                 break;
6266                 case AMDGPU_PCIE_GEN2:
6267                         if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
6268                                 break;
6269 #endif
6270                 default:
6271                         si_pi->force_pcie_gen = si_get_current_pcie_speed(adev);
6272                         break;
6273                 }
6274         } else {
6275                 if (target_link_speed < current_link_speed)
6276                         si_pi->pspp_notify_required = true;
6277         }
6278 }
6279
6280 static void si_notify_link_speed_change_after_state_change(struct amdgpu_device *adev,
6281                                                            struct amdgpu_ps *amdgpu_new_state,
6282                                                            struct amdgpu_ps *amdgpu_current_state)
6283 {
6284         struct si_power_info *si_pi = si_get_pi(adev);
6285         enum amdgpu_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state);
6286         u8 request;
6287
6288         if (si_pi->pspp_notify_required) {
6289                 if (target_link_speed == AMDGPU_PCIE_GEN3)
6290                         request = PCIE_PERF_REQ_PECI_GEN3;
6291                 else if (target_link_speed == AMDGPU_PCIE_GEN2)
6292                         request = PCIE_PERF_REQ_PECI_GEN2;
6293                 else
6294                         request = PCIE_PERF_REQ_PECI_GEN1;
6295
6296                 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
6297                     (si_get_current_pcie_speed(adev) > 0))
6298                         return;
6299
6300 #if defined(CONFIG_ACPI)
6301                 amdgpu_acpi_pcie_performance_request(adev, request, false);
6302 #endif
6303         }
6304 }
6305
6306 #if 0
6307 static int si_ds_request(struct amdgpu_device *adev,
6308                          bool ds_status_on, u32 count_write)
6309 {
6310         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6311
6312         if (eg_pi->sclk_deep_sleep) {
6313                 if (ds_status_on)
6314                         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
6315                                 PPSMC_Result_OK) ?
6316                                 0 : -EINVAL;
6317                 else
6318                         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
6319                                 PPSMC_Result_OK) ? 0 : -EINVAL;
6320         }
6321         return 0;
6322 }
6323 #endif
6324
6325 static void si_set_max_cu_value(struct amdgpu_device *adev)
6326 {
6327         struct si_power_info *si_pi = si_get_pi(adev);
6328
6329         if (adev->asic_type == CHIP_VERDE) {
6330                 switch (adev->pdev->device) {
6331                 case 0x6820:
6332                 case 0x6825:
6333                 case 0x6821:
6334                 case 0x6823:
6335                 case 0x6827:
6336                         si_pi->max_cu = 10;
6337                         break;
6338                 case 0x682D:
6339                 case 0x6824:
6340                 case 0x682F:
6341                 case 0x6826:
6342                         si_pi->max_cu = 8;
6343                         break;
6344                 case 0x6828:
6345                 case 0x6830:
6346                 case 0x6831:
6347                 case 0x6838:
6348                 case 0x6839:
6349                 case 0x683D:
6350                         si_pi->max_cu = 10;
6351                         break;
6352                 case 0x683B:
6353                 case 0x683F:
6354                 case 0x6829:
6355                         si_pi->max_cu = 8;
6356                         break;
6357                 default:
6358                         si_pi->max_cu = 0;
6359                         break;
6360                 }
6361         } else {
6362                 si_pi->max_cu = 0;
6363         }
6364 }
6365
6366 static int si_patch_single_dependency_table_based_on_leakage(struct amdgpu_device *adev,
6367                                                              struct amdgpu_clock_voltage_dependency_table *table)
6368 {
6369         u32 i;
6370         int j;
6371         u16 leakage_voltage;
6372
6373         if (table) {
6374                 for (i = 0; i < table->count; i++) {
6375                         switch (si_get_leakage_voltage_from_leakage_index(adev,
6376                                                                           table->entries[i].v,
6377                                                                           &leakage_voltage)) {
6378                         case 0:
6379                                 table->entries[i].v = leakage_voltage;
6380                                 break;
6381                         case -EAGAIN:
6382                                 return -EINVAL;
6383                         case -EINVAL:
6384                         default:
6385                                 break;
6386                         }
6387                 }
6388
6389                 for (j = (table->count - 2); j >= 0; j--) {
6390                         table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
6391                                 table->entries[j].v : table->entries[j + 1].v;
6392                 }
6393         }
6394         return 0;
6395 }
6396
6397 static int si_patch_dependency_tables_based_on_leakage(struct amdgpu_device *adev)
6398 {
6399         int ret = 0;
6400
6401         ret = si_patch_single_dependency_table_based_on_leakage(adev,
6402                                                                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
6403         if (ret)
6404                 DRM_ERROR("Could not patch vddc_on_sclk leakage table\n");
6405         ret = si_patch_single_dependency_table_based_on_leakage(adev,
6406                                                                 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
6407         if (ret)
6408                 DRM_ERROR("Could not patch vddc_on_mclk leakage table\n");
6409         ret = si_patch_single_dependency_table_based_on_leakage(adev,
6410                                                                 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
6411         if (ret)
6412                 DRM_ERROR("Could not patch vddci_on_mclk leakage table\n");
6413         return ret;
6414 }
6415
6416 static void si_set_pcie_lane_width_in_smc(struct amdgpu_device *adev,
6417                                           struct amdgpu_ps *amdgpu_new_state,
6418                                           struct amdgpu_ps *amdgpu_current_state)
6419 {
6420         u32 lane_width;
6421         u32 new_lane_width =
6422                 (amdgpu_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
6423         u32 current_lane_width =
6424                 (amdgpu_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
6425
6426         if (new_lane_width != current_lane_width) {
6427                 amdgpu_set_pcie_lanes(adev, new_lane_width);
6428                 lane_width = amdgpu_get_pcie_lanes(adev);
6429                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
6430         }
6431 }
6432
6433 static void si_dpm_setup_asic(struct amdgpu_device *adev)
6434 {
6435         si_read_clock_registers(adev);
6436         si_enable_acpi_power_management(adev);
6437 }
6438
6439 static int si_thermal_enable_alert(struct amdgpu_device *adev,
6440                                    bool enable)
6441 {
6442         u32 thermal_int = RREG32(CG_THERMAL_INT);
6443
6444         if (enable) {
6445                 PPSMC_Result result;
6446
6447                 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
6448                 WREG32(CG_THERMAL_INT, thermal_int);
6449                 result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
6450                 if (result != PPSMC_Result_OK) {
6451                         DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
6452                         return -EINVAL;
6453                 }
6454         } else {
6455                 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
6456                 WREG32(CG_THERMAL_INT, thermal_int);
6457         }
6458
6459         return 0;
6460 }
6461
6462 static int si_thermal_set_temperature_range(struct amdgpu_device *adev,
6463                                             int min_temp, int max_temp)
6464 {
6465         int low_temp = 0 * 1000;
6466         int high_temp = 255 * 1000;
6467
6468         if (low_temp < min_temp)
6469                 low_temp = min_temp;
6470         if (high_temp > max_temp)
6471                 high_temp = max_temp;
6472         if (high_temp < low_temp) {
6473                 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
6474                 return -EINVAL;
6475         }
6476
6477         WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
6478         WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
6479         WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
6480
6481         adev->pm.dpm.thermal.min_temp = low_temp;
6482         adev->pm.dpm.thermal.max_temp = high_temp;
6483
6484         return 0;
6485 }
6486
6487 static void si_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode)
6488 {
6489         struct si_power_info *si_pi = si_get_pi(adev);
6490         u32 tmp;
6491
6492         if (si_pi->fan_ctrl_is_in_default_mode) {
6493                 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
6494                 si_pi->fan_ctrl_default_mode = tmp;
6495                 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
6496                 si_pi->t_min = tmp;
6497                 si_pi->fan_ctrl_is_in_default_mode = false;
6498         }
6499
6500         tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6501         tmp |= TMIN(0);
6502         WREG32(CG_FDO_CTRL2, tmp);
6503
6504         tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6505         tmp |= FDO_PWM_MODE(mode);
6506         WREG32(CG_FDO_CTRL2, tmp);
6507 }
6508
6509 static int si_thermal_setup_fan_table(struct amdgpu_device *adev)
6510 {
6511         struct si_power_info *si_pi = si_get_pi(adev);
6512         PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE };
6513         u32 duty100;
6514         u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
6515         u16 fdo_min, slope1, slope2;
6516         u32 reference_clock, tmp;
6517         int ret;
6518         u64 tmp64;
6519
6520         if (!si_pi->fan_table_start) {
6521                 adev->pm.dpm.fan.ucode_fan_control = false;
6522                 return 0;
6523         }
6524
6525         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6526
6527         if (duty100 == 0) {
6528                 adev->pm.dpm.fan.ucode_fan_control = false;
6529                 return 0;
6530         }
6531
6532         tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100;
6533         do_div(tmp64, 10000);
6534         fdo_min = (u16)tmp64;
6535
6536         t_diff1 = adev->pm.dpm.fan.t_med - adev->pm.dpm.fan.t_min;
6537         t_diff2 = adev->pm.dpm.fan.t_high - adev->pm.dpm.fan.t_med;
6538
6539         pwm_diff1 = adev->pm.dpm.fan.pwm_med - adev->pm.dpm.fan.pwm_min;
6540         pwm_diff2 = adev->pm.dpm.fan.pwm_high - adev->pm.dpm.fan.pwm_med;
6541
6542         slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
6543         slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
6544
6545         fan_table.temp_min = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100);
6546         fan_table.temp_med = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100);
6547         fan_table.temp_max = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100);
6548         fan_table.slope1 = cpu_to_be16(slope1);
6549         fan_table.slope2 = cpu_to_be16(slope2);
6550         fan_table.fdo_min = cpu_to_be16(fdo_min);
6551         fan_table.hys_down = cpu_to_be16(adev->pm.dpm.fan.t_hyst);
6552         fan_table.hys_up = cpu_to_be16(1);
6553         fan_table.hys_slope = cpu_to_be16(1);
6554         fan_table.temp_resp_lim = cpu_to_be16(5);
6555         reference_clock = amdgpu_asic_get_xclk(adev);
6556
6557         fan_table.refresh_period = cpu_to_be32((adev->pm.dpm.fan.cycle_delay *
6558                                                 reference_clock) / 1600);
6559         fan_table.fdo_max = cpu_to_be16((u16)duty100);
6560
6561         tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
6562         fan_table.temp_src = (uint8_t)tmp;
6563
6564         ret = amdgpu_si_copy_bytes_to_smc(adev,
6565                                           si_pi->fan_table_start,
6566                                           (u8 *)(&fan_table),
6567                                           sizeof(fan_table),
6568                                           si_pi->sram_end);
6569
6570         if (ret) {
6571                 DRM_ERROR("Failed to load fan table to the SMC.");
6572                 adev->pm.dpm.fan.ucode_fan_control = false;
6573         }
6574
6575         return ret;
6576 }
6577
6578 static int si_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev)
6579 {
6580         struct si_power_info *si_pi = si_get_pi(adev);
6581         PPSMC_Result ret;
6582
6583         ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StartFanControl);
6584         if (ret == PPSMC_Result_OK) {
6585                 si_pi->fan_is_controlled_by_smc = true;
6586                 return 0;
6587         } else {
6588                 return -EINVAL;
6589         }
6590 }
6591
6592 static int si_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev)
6593 {
6594         struct si_power_info *si_pi = si_get_pi(adev);
6595         PPSMC_Result ret;
6596
6597         ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StopFanControl);
6598
6599         if (ret == PPSMC_Result_OK) {
6600                 si_pi->fan_is_controlled_by_smc = false;
6601                 return 0;
6602         } else {
6603                 return -EINVAL;
6604         }
6605 }
6606
6607 static int si_dpm_get_fan_speed_percent(struct amdgpu_device *adev,
6608                                       u32 *speed)
6609 {
6610         u32 duty, duty100;
6611         u64 tmp64;
6612
6613         if (adev->pm.no_fan)
6614                 return -ENOENT;
6615
6616         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6617         duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;
6618
6619         if (duty100 == 0)
6620                 return -EINVAL;
6621
6622         tmp64 = (u64)duty * 100;
6623         do_div(tmp64, duty100);
6624         *speed = (u32)tmp64;
6625
6626         if (*speed > 100)
6627                 *speed = 100;
6628
6629         return 0;
6630 }
6631
6632 static int si_dpm_set_fan_speed_percent(struct amdgpu_device *adev,
6633                                       u32 speed)
6634 {
6635         struct si_power_info *si_pi = si_get_pi(adev);
6636         u32 tmp;
6637         u32 duty, duty100;
6638         u64 tmp64;
6639
6640         if (adev->pm.no_fan)
6641                 return -ENOENT;
6642
6643         if (si_pi->fan_is_controlled_by_smc)
6644                 return -EINVAL;
6645
6646         if (speed > 100)
6647                 return -EINVAL;
6648
6649         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6650
6651         if (duty100 == 0)
6652                 return -EINVAL;
6653
6654         tmp64 = (u64)speed * duty100;
6655         do_div(tmp64, 100);
6656         duty = (u32)tmp64;
6657
6658         tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
6659         tmp |= FDO_STATIC_DUTY(duty);
6660         WREG32(CG_FDO_CTRL0, tmp);
6661
6662         return 0;
6663 }
6664
6665 static void si_dpm_set_fan_control_mode(struct amdgpu_device *adev, u32 mode)
6666 {
6667         if (mode) {
6668                 /* stop auto-manage */
6669                 if (adev->pm.dpm.fan.ucode_fan_control)
6670                         si_fan_ctrl_stop_smc_fan_control(adev);
6671                 si_fan_ctrl_set_static_mode(adev, mode);
6672         } else {
6673                 /* restart auto-manage */
6674                 if (adev->pm.dpm.fan.ucode_fan_control)
6675                         si_thermal_start_smc_fan_control(adev);
6676                 else
6677                         si_fan_ctrl_set_default_mode(adev);
6678         }
6679 }
6680
6681 static u32 si_dpm_get_fan_control_mode(struct amdgpu_device *adev)
6682 {
6683         struct si_power_info *si_pi = si_get_pi(adev);
6684         u32 tmp;
6685
6686         if (si_pi->fan_is_controlled_by_smc)
6687                 return 0;
6688
6689         tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
6690         return (tmp >> FDO_PWM_MODE_SHIFT);
6691 }
6692
6693 #if 0
6694 static int si_fan_ctrl_get_fan_speed_rpm(struct amdgpu_device *adev,
6695                                          u32 *speed)
6696 {
6697         u32 tach_period;
6698         u32 xclk = amdgpu_asic_get_xclk(adev);
6699
6700         if (adev->pm.no_fan)
6701                 return -ENOENT;
6702
6703         if (adev->pm.fan_pulses_per_revolution == 0)
6704                 return -ENOENT;
6705
6706         tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
6707         if (tach_period == 0)
6708                 return -ENOENT;
6709
6710         *speed = 60 * xclk * 10000 / tach_period;
6711
6712         return 0;
6713 }
6714
6715 static int si_fan_ctrl_set_fan_speed_rpm(struct amdgpu_device *adev,
6716                                          u32 speed)
6717 {
6718         u32 tach_period, tmp;
6719         u32 xclk = amdgpu_asic_get_xclk(adev);
6720
6721         if (adev->pm.no_fan)
6722                 return -ENOENT;
6723
6724         if (adev->pm.fan_pulses_per_revolution == 0)
6725                 return -ENOENT;
6726
6727         if ((speed < adev->pm.fan_min_rpm) ||
6728             (speed > adev->pm.fan_max_rpm))
6729                 return -EINVAL;
6730
6731         if (adev->pm.dpm.fan.ucode_fan_control)
6732                 si_fan_ctrl_stop_smc_fan_control(adev);
6733
6734         tach_period = 60 * xclk * 10000 / (8 * speed);
6735         tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
6736         tmp |= TARGET_PERIOD(tach_period);
6737         WREG32(CG_TACH_CTRL, tmp);
6738
6739         si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC_RPM);
6740
6741         return 0;
6742 }
6743 #endif
6744
6745 static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev)
6746 {
6747         struct si_power_info *si_pi = si_get_pi(adev);
6748         u32 tmp;
6749
6750         if (!si_pi->fan_ctrl_is_in_default_mode) {
6751                 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6752                 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode);
6753                 WREG32(CG_FDO_CTRL2, tmp);
6754
6755                 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6756                 tmp |= TMIN(si_pi->t_min);
6757                 WREG32(CG_FDO_CTRL2, tmp);
6758                 si_pi->fan_ctrl_is_in_default_mode = true;
6759         }
6760 }
6761
6762 static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev)
6763 {
6764         if (adev->pm.dpm.fan.ucode_fan_control) {
6765                 si_fan_ctrl_start_smc_fan_control(adev);
6766                 si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC);
6767         }
6768 }
6769
6770 static void si_thermal_initialize(struct amdgpu_device *adev)
6771 {
6772         u32 tmp;
6773
6774         if (adev->pm.fan_pulses_per_revolution) {
6775                 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
6776                 tmp |= EDGE_PER_REV(adev->pm.fan_pulses_per_revolution -1);
6777                 WREG32(CG_TACH_CTRL, tmp);
6778         }
6779
6780         tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
6781         tmp |= TACH_PWM_RESP_RATE(0x28);
6782         WREG32(CG_FDO_CTRL2, tmp);
6783 }
6784
6785 static int si_thermal_start_thermal_controller(struct amdgpu_device *adev)
6786 {
6787         int ret;
6788
6789         si_thermal_initialize(adev);
6790         ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6791         if (ret)
6792                 return ret;
6793         ret = si_thermal_enable_alert(adev, true);
6794         if (ret)
6795                 return ret;
6796         if (adev->pm.dpm.fan.ucode_fan_control) {
6797                 ret = si_halt_smc(adev);
6798                 if (ret)
6799                         return ret;
6800                 ret = si_thermal_setup_fan_table(adev);
6801                 if (ret)
6802                         return ret;
6803                 ret = si_resume_smc(adev);
6804                 if (ret)
6805                         return ret;
6806                 si_thermal_start_smc_fan_control(adev);
6807         }
6808
6809         return 0;
6810 }
6811
6812 static void si_thermal_stop_thermal_controller(struct amdgpu_device *adev)
6813 {
6814         if (!adev->pm.no_fan) {
6815                 si_fan_ctrl_set_default_mode(adev);
6816                 si_fan_ctrl_stop_smc_fan_control(adev);
6817         }
6818 }
6819
6820 static int si_dpm_enable(struct amdgpu_device *adev)
6821 {
6822         struct rv7xx_power_info *pi = rv770_get_pi(adev);
6823         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6824         struct si_power_info *si_pi = si_get_pi(adev);
6825         struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
6826         int ret;
6827
6828         if (amdgpu_si_is_smc_running(adev))
6829                 return -EINVAL;
6830         if (pi->voltage_control || si_pi->voltage_control_svi2)
6831                 si_enable_voltage_control(adev, true);
6832         if (pi->mvdd_control)
6833                 si_get_mvdd_configuration(adev);
6834         if (pi->voltage_control || si_pi->voltage_control_svi2) {
6835                 ret = si_construct_voltage_tables(adev);
6836                 if (ret) {
6837                         DRM_ERROR("si_construct_voltage_tables failed\n");
6838                         return ret;
6839                 }
6840         }
6841         if (eg_pi->dynamic_ac_timing) {
6842                 ret = si_initialize_mc_reg_table(adev);
6843                 if (ret)
6844                         eg_pi->dynamic_ac_timing = false;
6845         }
6846         if (pi->dynamic_ss)
6847                 si_enable_spread_spectrum(adev, true);
6848         if (pi->thermal_protection)
6849                 si_enable_thermal_protection(adev, true);
6850         si_setup_bsp(adev);
6851         si_program_git(adev);
6852         si_program_tp(adev);
6853         si_program_tpp(adev);
6854         si_program_sstp(adev);
6855         si_enable_display_gap(adev);
6856         si_program_vc(adev);
6857         ret = si_upload_firmware(adev);
6858         if (ret) {
6859                 DRM_ERROR("si_upload_firmware failed\n");
6860                 return ret;
6861         }
6862         ret = si_process_firmware_header(adev);
6863         if (ret) {
6864                 DRM_ERROR("si_process_firmware_header failed\n");
6865                 return ret;
6866         }
6867         ret = si_initial_switch_from_arb_f0_to_f1(adev);
6868         if (ret) {
6869                 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
6870                 return ret;
6871         }
6872         ret = si_init_smc_table(adev);
6873         if (ret) {
6874                 DRM_ERROR("si_init_smc_table failed\n");
6875                 return ret;
6876         }
6877         ret = si_init_smc_spll_table(adev);
6878         if (ret) {
6879                 DRM_ERROR("si_init_smc_spll_table failed\n");
6880                 return ret;
6881         }
6882         ret = si_init_arb_table_index(adev);
6883         if (ret) {
6884                 DRM_ERROR("si_init_arb_table_index failed\n");
6885                 return ret;
6886         }
6887         if (eg_pi->dynamic_ac_timing) {
6888                 ret = si_populate_mc_reg_table(adev, boot_ps);
6889                 if (ret) {
6890                         DRM_ERROR("si_populate_mc_reg_table failed\n");
6891                         return ret;
6892                 }
6893         }
6894         ret = si_initialize_smc_cac_tables(adev);
6895         if (ret) {
6896                 DRM_ERROR("si_initialize_smc_cac_tables failed\n");
6897                 return ret;
6898         }
6899         ret = si_initialize_hardware_cac_manager(adev);
6900         if (ret) {
6901                 DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
6902                 return ret;
6903         }
6904         ret = si_initialize_smc_dte_tables(adev);
6905         if (ret) {
6906                 DRM_ERROR("si_initialize_smc_dte_tables failed\n");
6907                 return ret;
6908         }
6909         ret = si_populate_smc_tdp_limits(adev, boot_ps);
6910         if (ret) {
6911                 DRM_ERROR("si_populate_smc_tdp_limits failed\n");
6912                 return ret;
6913         }
6914         ret = si_populate_smc_tdp_limits_2(adev, boot_ps);
6915         if (ret) {
6916                 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
6917                 return ret;
6918         }
6919         si_program_response_times(adev);
6920         si_program_ds_registers(adev);
6921         si_dpm_start_smc(adev);
6922         ret = si_notify_smc_display_change(adev, false);
6923         if (ret) {
6924                 DRM_ERROR("si_notify_smc_display_change failed\n");
6925                 return ret;
6926         }
6927         si_enable_sclk_control(adev, true);
6928         si_start_dpm(adev);
6929
6930         si_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
6931         si_thermal_start_thermal_controller(adev);
6932         ni_update_current_ps(adev, boot_ps);
6933
6934         return 0;
6935 }
6936
6937 static int si_set_temperature_range(struct amdgpu_device *adev)
6938 {
6939         int ret;
6940
6941         ret = si_thermal_enable_alert(adev, false);
6942         if (ret)
6943                 return ret;
6944         ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6945         if (ret)
6946                 return ret;
6947         ret = si_thermal_enable_alert(adev, true);
6948         if (ret)
6949                 return ret;
6950
6951         return ret;
6952 }
6953
6954 static void si_dpm_disable(struct amdgpu_device *adev)
6955 {
6956         struct rv7xx_power_info *pi = rv770_get_pi(adev);
6957         struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
6958
6959         if (!amdgpu_si_is_smc_running(adev))
6960                 return;
6961         si_thermal_stop_thermal_controller(adev);
6962         si_disable_ulv(adev);
6963         si_clear_vc(adev);
6964         if (pi->thermal_protection)
6965                 si_enable_thermal_protection(adev, false);
6966         si_enable_power_containment(adev, boot_ps, false);
6967         si_enable_smc_cac(adev, boot_ps, false);
6968         si_enable_spread_spectrum(adev, false);
6969         si_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
6970         si_stop_dpm(adev);
6971         si_reset_to_default(adev);
6972         si_dpm_stop_smc(adev);
6973         si_force_switch_to_arb_f0(adev);
6974
6975         ni_update_current_ps(adev, boot_ps);
6976 }
6977
6978 static int si_dpm_pre_set_power_state(struct amdgpu_device *adev)
6979 {
6980         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6981         struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
6982         struct amdgpu_ps *new_ps = &requested_ps;
6983
6984         ni_update_requested_ps(adev, new_ps);
6985         si_apply_state_adjust_rules(adev, &eg_pi->requested_rps);
6986
6987         return 0;
6988 }
6989
6990 static int si_power_control_set_level(struct amdgpu_device *adev)
6991 {
6992         struct amdgpu_ps *new_ps = adev->pm.dpm.requested_ps;
6993         int ret;
6994
6995         ret = si_restrict_performance_levels_before_switch(adev);
6996         if (ret)
6997                 return ret;
6998         ret = si_halt_smc(adev);
6999         if (ret)
7000                 return ret;
7001         ret = si_populate_smc_tdp_limits(adev, new_ps);
7002         if (ret)
7003                 return ret;
7004         ret = si_populate_smc_tdp_limits_2(adev, new_ps);
7005         if (ret)
7006                 return ret;
7007         ret = si_resume_smc(adev);
7008         if (ret)
7009                 return ret;
7010         ret = si_set_sw_state(adev);
7011         if (ret)
7012                 return ret;
7013         return 0;
7014 }
7015
7016 static int si_dpm_set_power_state(struct amdgpu_device *adev)
7017 {
7018         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7019         struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
7020         struct amdgpu_ps *old_ps = &eg_pi->current_rps;
7021         int ret;
7022
7023         ret = si_disable_ulv(adev);
7024         if (ret) {
7025                 DRM_ERROR("si_disable_ulv failed\n");
7026                 return ret;
7027         }
7028         ret = si_restrict_performance_levels_before_switch(adev);
7029         if (ret) {
7030                 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
7031                 return ret;
7032         }
7033         if (eg_pi->pcie_performance_request)
7034                 si_request_link_speed_change_before_state_change(adev, new_ps, old_ps);
7035         ni_set_uvd_clock_before_set_eng_clock(adev, new_ps, old_ps);
7036         ret = si_enable_power_containment(adev, new_ps, false);
7037         if (ret) {
7038                 DRM_ERROR("si_enable_power_containment failed\n");
7039                 return ret;
7040         }
7041         ret = si_enable_smc_cac(adev, new_ps, false);
7042         if (ret) {
7043                 DRM_ERROR("si_enable_smc_cac failed\n");
7044                 return ret;
7045         }
7046         ret = si_halt_smc(adev);
7047         if (ret) {
7048                 DRM_ERROR("si_halt_smc failed\n");
7049                 return ret;
7050         }
7051         ret = si_upload_sw_state(adev, new_ps);
7052         if (ret) {
7053                 DRM_ERROR("si_upload_sw_state failed\n");
7054                 return ret;
7055         }
7056         ret = si_upload_smc_data(adev);
7057         if (ret) {
7058                 DRM_ERROR("si_upload_smc_data failed\n");
7059                 return ret;
7060         }
7061         ret = si_upload_ulv_state(adev);
7062         if (ret) {
7063                 DRM_ERROR("si_upload_ulv_state failed\n");
7064                 return ret;
7065         }
7066         if (eg_pi->dynamic_ac_timing) {
7067                 ret = si_upload_mc_reg_table(adev, new_ps);
7068                 if (ret) {
7069                         DRM_ERROR("si_upload_mc_reg_table failed\n");
7070                         return ret;
7071                 }
7072         }
7073         ret = si_program_memory_timing_parameters(adev, new_ps);
7074         if (ret) {
7075                 DRM_ERROR("si_program_memory_timing_parameters failed\n");
7076                 return ret;
7077         }
7078         si_set_pcie_lane_width_in_smc(adev, new_ps, old_ps);
7079
7080         ret = si_resume_smc(adev);
7081         if (ret) {
7082                 DRM_ERROR("si_resume_smc failed\n");
7083                 return ret;
7084         }
7085         ret = si_set_sw_state(adev);
7086         if (ret) {
7087                 DRM_ERROR("si_set_sw_state failed\n");
7088                 return ret;
7089         }
7090         ni_set_uvd_clock_after_set_eng_clock(adev, new_ps, old_ps);
7091         if (eg_pi->pcie_performance_request)
7092                 si_notify_link_speed_change_after_state_change(adev, new_ps, old_ps);
7093         ret = si_set_power_state_conditionally_enable_ulv(adev, new_ps);
7094         if (ret) {
7095                 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
7096                 return ret;
7097         }
7098         ret = si_enable_smc_cac(adev, new_ps, true);
7099         if (ret) {
7100                 DRM_ERROR("si_enable_smc_cac failed\n");
7101                 return ret;
7102         }
7103         ret = si_enable_power_containment(adev, new_ps, true);
7104         if (ret) {
7105                 DRM_ERROR("si_enable_power_containment failed\n");
7106                 return ret;
7107         }
7108
7109         ret = si_power_control_set_level(adev);
7110         if (ret) {
7111                 DRM_ERROR("si_power_control_set_level failed\n");
7112                 return ret;
7113         }
7114
7115         return 0;
7116 }
7117
7118 static void si_dpm_post_set_power_state(struct amdgpu_device *adev)
7119 {
7120         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7121         struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
7122
7123         ni_update_current_ps(adev, new_ps);
7124 }
7125
7126 #if 0
7127 void si_dpm_reset_asic(struct amdgpu_device *adev)
7128 {
7129         si_restrict_performance_levels_before_switch(adev);
7130         si_disable_ulv(adev);
7131         si_set_boot_state(adev);
7132 }
7133 #endif
7134
7135 static void si_dpm_display_configuration_changed(struct amdgpu_device *adev)
7136 {
7137         si_program_display_gap(adev);
7138 }
7139
7140
7141 static void si_parse_pplib_non_clock_info(struct amdgpu_device *adev,
7142                                           struct amdgpu_ps *rps,
7143                                           struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
7144                                           u8 table_rev)
7145 {
7146         rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
7147         rps->class = le16_to_cpu(non_clock_info->usClassification);
7148         rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
7149
7150         if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
7151                 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
7152                 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
7153         } else if (r600_is_uvd_state(rps->class, rps->class2)) {
7154                 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
7155                 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
7156         } else {
7157                 rps->vclk = 0;
7158                 rps->dclk = 0;
7159         }
7160
7161         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
7162                 adev->pm.dpm.boot_ps = rps;
7163         if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
7164                 adev->pm.dpm.uvd_ps = rps;
7165 }
7166
7167 static void si_parse_pplib_clock_info(struct amdgpu_device *adev,
7168                                       struct amdgpu_ps *rps, int index,
7169                                       union pplib_clock_info *clock_info)
7170 {
7171         struct rv7xx_power_info *pi = rv770_get_pi(adev);
7172         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7173         struct si_power_info *si_pi = si_get_pi(adev);
7174         struct  si_ps *ps = si_get_ps(rps);
7175         u16 leakage_voltage;
7176         struct rv7xx_pl *pl = &ps->performance_levels[index];
7177         int ret;
7178
7179         ps->performance_level_count = index + 1;
7180
7181         pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
7182         pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
7183         pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
7184         pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
7185
7186         pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
7187         pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
7188         pl->flags = le32_to_cpu(clock_info->si.ulFlags);
7189         pl->pcie_gen = r600_get_pcie_gen_support(adev,
7190                                                  si_pi->sys_pcie_mask,
7191                                                  si_pi->boot_pcie_gen,
7192                                                  clock_info->si.ucPCIEGen);
7193
7194         /* patch up vddc if necessary */
7195         ret = si_get_leakage_voltage_from_leakage_index(adev, pl->vddc,
7196                                                         &leakage_voltage);
7197         if (ret == 0)
7198                 pl->vddc = leakage_voltage;
7199
7200         if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
7201                 pi->acpi_vddc = pl->vddc;
7202                 eg_pi->acpi_vddci = pl->vddci;
7203                 si_pi->acpi_pcie_gen = pl->pcie_gen;
7204         }
7205
7206         if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
7207             index == 0) {
7208                 /* XXX disable for A0 tahiti */
7209                 si_pi->ulv.supported = false;
7210                 si_pi->ulv.pl = *pl;
7211                 si_pi->ulv.one_pcie_lane_in_ulv = false;
7212                 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
7213                 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
7214                 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
7215         }
7216
7217         if (pi->min_vddc_in_table > pl->vddc)
7218                 pi->min_vddc_in_table = pl->vddc;
7219
7220         if (pi->max_vddc_in_table < pl->vddc)
7221                 pi->max_vddc_in_table = pl->vddc;
7222
7223         /* patch up boot state */
7224         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
7225                 u16 vddc, vddci, mvdd;
7226                 amdgpu_atombios_get_default_voltages(adev, &vddc, &vddci, &mvdd);
7227                 pl->mclk = adev->clock.default_mclk;
7228                 pl->sclk = adev->clock.default_sclk;
7229                 pl->vddc = vddc;
7230                 pl->vddci = vddci;
7231                 si_pi->mvdd_bootup_value = mvdd;
7232         }
7233
7234         if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
7235             ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
7236                 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
7237                 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
7238                 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
7239                 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
7240         }
7241 }
7242
7243 union pplib_power_state {
7244         struct _ATOM_PPLIB_STATE v1;
7245         struct _ATOM_PPLIB_STATE_V2 v2;
7246 };
7247
7248 static int si_parse_power_table(struct amdgpu_device *adev)
7249 {
7250         struct amdgpu_mode_info *mode_info = &adev->mode_info;
7251         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
7252         union pplib_power_state *power_state;
7253         int i, j, k, non_clock_array_index, clock_array_index;
7254         union pplib_clock_info *clock_info;
7255         struct _StateArray *state_array;
7256         struct _ClockInfoArray *clock_info_array;
7257         struct _NonClockInfoArray *non_clock_info_array;
7258         union power_info *power_info;
7259         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
7260         u16 data_offset;
7261         u8 frev, crev;
7262         u8 *power_state_offset;
7263         struct  si_ps *ps;
7264
7265         if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
7266                                    &frev, &crev, &data_offset))
7267                 return -EINVAL;
7268         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
7269
7270         amdgpu_add_thermal_controller(adev);
7271
7272         state_array = (struct _StateArray *)
7273                 (mode_info->atom_context->bios + data_offset +
7274                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
7275         clock_info_array = (struct _ClockInfoArray *)
7276                 (mode_info->atom_context->bios + data_offset +
7277                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
7278         non_clock_info_array = (struct _NonClockInfoArray *)
7279                 (mode_info->atom_context->bios + data_offset +
7280                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
7281
7282         adev->pm.dpm.ps = kzalloc(sizeof(struct amdgpu_ps) *
7283                                   state_array->ucNumEntries, GFP_KERNEL);
7284         if (!adev->pm.dpm.ps)
7285                 return -ENOMEM;
7286         power_state_offset = (u8 *)state_array->states;
7287         for (i = 0; i < state_array->ucNumEntries; i++) {
7288                 u8 *idx;
7289                 power_state = (union pplib_power_state *)power_state_offset;
7290                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
7291                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
7292                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
7293                 ps = kzalloc(sizeof(struct  si_ps), GFP_KERNEL);
7294                 if (ps == NULL) {
7295                         kfree(adev->pm.dpm.ps);
7296                         return -ENOMEM;
7297                 }
7298                 adev->pm.dpm.ps[i].ps_priv = ps;
7299                 si_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],
7300                                               non_clock_info,
7301                                               non_clock_info_array->ucEntrySize);
7302                 k = 0;
7303                 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
7304                 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
7305                         clock_array_index = idx[j];
7306                         if (clock_array_index >= clock_info_array->ucNumEntries)
7307                                 continue;
7308                         if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
7309                                 break;
7310                         clock_info = (union pplib_clock_info *)
7311                                 ((u8 *)&clock_info_array->clockInfo[0] +
7312                                  (clock_array_index * clock_info_array->ucEntrySize));
7313                         si_parse_pplib_clock_info(adev,
7314                                                   &adev->pm.dpm.ps[i], k,
7315                                                   clock_info);
7316                         k++;
7317                 }
7318                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
7319         }
7320         adev->pm.dpm.num_ps = state_array->ucNumEntries;
7321
7322         /* fill in the vce power states */
7323         for (i = 0; i < AMDGPU_MAX_VCE_LEVELS; i++) {
7324                 u32 sclk, mclk;
7325                 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
7326                 clock_info = (union pplib_clock_info *)
7327                         &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
7328                 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
7329                 sclk |= clock_info->si.ucEngineClockHigh << 16;
7330                 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
7331                 mclk |= clock_info->si.ucMemoryClockHigh << 16;
7332                 adev->pm.dpm.vce_states[i].sclk = sclk;
7333                 adev->pm.dpm.vce_states[i].mclk = mclk;
7334         }
7335
7336         return 0;
7337 }
7338
7339 static int si_dpm_init(struct amdgpu_device *adev)
7340 {
7341         struct rv7xx_power_info *pi;
7342         struct evergreen_power_info *eg_pi;
7343         struct ni_power_info *ni_pi;
7344         struct si_power_info *si_pi;
7345         struct atom_clock_dividers dividers;
7346         int ret;
7347         u32 mask;
7348
7349         si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
7350         if (si_pi == NULL)
7351                 return -ENOMEM;
7352         adev->pm.dpm.priv = si_pi;
7353         ni_pi = &si_pi->ni;
7354         eg_pi = &ni_pi->eg;
7355         pi = &eg_pi->rv7xx;
7356
7357         ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
7358         if (ret)
7359                 si_pi->sys_pcie_mask = 0;
7360         else
7361                 si_pi->sys_pcie_mask = mask;
7362         si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
7363         si_pi->boot_pcie_gen = si_get_current_pcie_speed(adev);
7364
7365         si_set_max_cu_value(adev);
7366
7367         rv770_get_max_vddc(adev);
7368         si_get_leakage_vddc(adev);
7369         si_patch_dependency_tables_based_on_leakage(adev);
7370
7371         pi->acpi_vddc = 0;
7372         eg_pi->acpi_vddci = 0;
7373         pi->min_vddc_in_table = 0;
7374         pi->max_vddc_in_table = 0;
7375
7376         ret = amdgpu_get_platform_caps(adev);
7377         if (ret)
7378                 return ret;
7379
7380         ret = amdgpu_parse_extended_power_table(adev);
7381         if (ret)
7382                 return ret;
7383
7384         ret = si_parse_power_table(adev);
7385         if (ret)
7386                 return ret;
7387
7388         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
7389                 kzalloc(4 * sizeof(struct amdgpu_clock_voltage_dependency_entry), GFP_KERNEL);
7390         if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
7391                 amdgpu_free_extended_power_table(adev);
7392                 return -ENOMEM;
7393         }
7394         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
7395         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
7396         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
7397         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
7398         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
7399         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
7400         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
7401         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
7402         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
7403
7404         if (adev->pm.dpm.voltage_response_time == 0)
7405                 adev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
7406         if (adev->pm.dpm.backbias_response_time == 0)
7407                 adev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
7408
7409         ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
7410                                              0, false, &dividers);
7411         if (ret)
7412                 pi->ref_div = dividers.ref_div + 1;
7413         else
7414                 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
7415
7416         eg_pi->smu_uvd_hs = false;
7417
7418         pi->mclk_strobe_mode_threshold = 40000;
7419         if (si_is_special_1gb_platform(adev))
7420                 pi->mclk_stutter_mode_threshold = 0;
7421         else
7422                 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
7423         pi->mclk_edc_enable_threshold = 40000;
7424         eg_pi->mclk_edc_wr_enable_threshold = 40000;
7425
7426         ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
7427
7428         pi->voltage_control =
7429                 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7430                                             VOLTAGE_OBJ_GPIO_LUT);
7431         if (!pi->voltage_control) {
7432                 si_pi->voltage_control_svi2 =
7433                         amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7434                                                     VOLTAGE_OBJ_SVID2);
7435                 if (si_pi->voltage_control_svi2)
7436                         amdgpu_atombios_get_svi2_info(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7437                                                   &si_pi->svd_gpio_id, &si_pi->svc_gpio_id);
7438         }
7439
7440         pi->mvdd_control =
7441                 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_MVDDC,
7442                                             VOLTAGE_OBJ_GPIO_LUT);
7443
7444         eg_pi->vddci_control =
7445                 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7446                                             VOLTAGE_OBJ_GPIO_LUT);
7447         if (!eg_pi->vddci_control)
7448                 si_pi->vddci_control_svi2 =
7449                         amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7450                                                     VOLTAGE_OBJ_SVID2);
7451
7452         si_pi->vddc_phase_shed_control =
7453                 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7454                                             VOLTAGE_OBJ_PHASE_LUT);
7455
7456         rv770_get_engine_memory_ss(adev);
7457
7458         pi->asi = RV770_ASI_DFLT;
7459         pi->pasi = CYPRESS_HASI_DFLT;
7460         pi->vrc = SISLANDS_VRC_DFLT;
7461
7462         pi->gfx_clock_gating = true;
7463
7464         eg_pi->sclk_deep_sleep = true;
7465         si_pi->sclk_deep_sleep_above_low = false;
7466
7467         if (adev->pm.int_thermal_type != THERMAL_TYPE_NONE)
7468                 pi->thermal_protection = true;
7469         else
7470                 pi->thermal_protection = false;
7471
7472         eg_pi->dynamic_ac_timing = true;
7473
7474         eg_pi->light_sleep = true;
7475 #if defined(CONFIG_ACPI)
7476         eg_pi->pcie_performance_request =
7477                 amdgpu_acpi_is_pcie_performance_request_supported(adev);
7478 #else
7479         eg_pi->pcie_performance_request = false;
7480 #endif
7481
7482         si_pi->sram_end = SMC_RAM_END;
7483
7484         adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
7485         adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
7486         adev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
7487         adev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
7488         adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
7489         adev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
7490         adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
7491
7492         si_initialize_powertune_defaults(adev);
7493
7494         /* make sure dc limits are valid */
7495         if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
7496             (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
7497                 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
7498                         adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
7499
7500         si_pi->fan_ctrl_is_in_default_mode = true;
7501
7502         return 0;
7503 }
7504
7505 static void si_dpm_fini(struct amdgpu_device *adev)
7506 {
7507         int i;
7508
7509         if (adev->pm.dpm.ps)
7510                 for (i = 0; i < adev->pm.dpm.num_ps; i++)
7511                         kfree(adev->pm.dpm.ps[i].ps_priv);
7512         kfree(adev->pm.dpm.ps);
7513         kfree(adev->pm.dpm.priv);
7514         kfree(adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
7515         amdgpu_free_extended_power_table(adev);
7516 }
7517
7518 static void si_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
7519                                                     struct seq_file *m)
7520 {
7521         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7522         struct amdgpu_ps *rps = &eg_pi->current_rps;
7523         struct  si_ps *ps = si_get_ps(rps);
7524         struct rv7xx_pl *pl;
7525         u32 current_index =
7526                 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7527                 CURRENT_STATE_INDEX_SHIFT;
7528
7529         if (current_index >= ps->performance_level_count) {
7530                 seq_printf(m, "invalid dpm profile %d\n", current_index);
7531         } else {
7532                 pl = &ps->performance_levels[current_index];
7533                 seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7534                 seq_printf(m, "power level %d    sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7535                            current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7536         }
7537 }
7538
7539 static int si_dpm_set_interrupt_state(struct amdgpu_device *adev,
7540                                       struct amdgpu_irq_src *source,
7541                                       unsigned type,
7542                                       enum amdgpu_interrupt_state state)
7543 {
7544         u32 cg_thermal_int;
7545
7546         switch (type) {
7547         case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH:
7548                 switch (state) {
7549                 case AMDGPU_IRQ_STATE_DISABLE:
7550                         cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7551                         cg_thermal_int |= THERM_INT_MASK_HIGH;
7552                         WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7553                         break;
7554                 case AMDGPU_IRQ_STATE_ENABLE:
7555                         cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7556                         cg_thermal_int &= ~THERM_INT_MASK_HIGH;
7557                         WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7558                         break;
7559                 default:
7560                         break;
7561                 }
7562                 break;
7563
7564         case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW:
7565                 switch (state) {
7566                 case AMDGPU_IRQ_STATE_DISABLE:
7567                         cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7568                         cg_thermal_int |= THERM_INT_MASK_LOW;
7569                         WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7570                         break;
7571                 case AMDGPU_IRQ_STATE_ENABLE:
7572                         cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7573                         cg_thermal_int &= ~THERM_INT_MASK_LOW;
7574                         WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7575                         break;
7576                 default:
7577                         break;
7578                 }
7579                 break;
7580
7581         default:
7582                 break;
7583         }
7584         return 0;
7585 }
7586
7587 static int si_dpm_process_interrupt(struct amdgpu_device *adev,
7588                                     struct amdgpu_irq_src *source,
7589                                     struct amdgpu_iv_entry *entry)
7590 {
7591         bool queue_thermal = false;
7592
7593         if (entry == NULL)
7594                 return -EINVAL;
7595
7596         switch (entry->src_id) {
7597         case 230: /* thermal low to high */
7598                 DRM_DEBUG("IH: thermal low to high\n");
7599                 adev->pm.dpm.thermal.high_to_low = false;
7600                 queue_thermal = true;
7601                 break;
7602         case 231: /* thermal high to low */
7603                 DRM_DEBUG("IH: thermal high to low\n");
7604                 adev->pm.dpm.thermal.high_to_low = true;
7605                 queue_thermal = true;
7606                 break;
7607         default:
7608                 break;
7609         }
7610
7611         if (queue_thermal)
7612                 schedule_work(&adev->pm.dpm.thermal.work);
7613
7614         return 0;
7615 }
7616
7617 static int si_dpm_late_init(void *handle)
7618 {
7619         int ret;
7620         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7621
7622         if (!amdgpu_dpm)
7623                 return 0;
7624
7625         /* init the sysfs and debugfs files late */
7626         ret = amdgpu_pm_sysfs_init(adev);
7627         if (ret)
7628                 return ret;
7629
7630         ret = si_set_temperature_range(adev);
7631         if (ret)
7632                 return ret;
7633 #if 0 //TODO ?
7634         si_dpm_powergate_uvd(adev, true);
7635 #endif
7636         return 0;
7637 }
7638
7639 /**
7640  * si_dpm_init_microcode - load ucode images from disk
7641  *
7642  * @adev: amdgpu_device pointer
7643  *
7644  * Use the firmware interface to load the ucode images into
7645  * the driver (not loaded into hw).
7646  * Returns 0 on success, error on failure.
7647  */
7648 static int si_dpm_init_microcode(struct amdgpu_device *adev)
7649 {
7650         const char *chip_name;
7651         char fw_name[30];
7652         int err;
7653
7654         DRM_DEBUG("\n");
7655         switch (adev->asic_type) {
7656         case CHIP_TAHITI:
7657                 chip_name = "tahiti";
7658                 break;
7659         case CHIP_PITCAIRN:
7660                 if ((adev->pdev->revision == 0x81) ||
7661                     (adev->pdev->device == 0x6810) ||
7662                     (adev->pdev->device == 0x6811) ||
7663                     (adev->pdev->device == 0x6816) ||
7664                     (adev->pdev->device == 0x6817) ||
7665                     (adev->pdev->device == 0x6806))
7666                         chip_name = "pitcairn_k";
7667                 else
7668                         chip_name = "pitcairn";
7669                 break;
7670         case CHIP_VERDE:
7671                 if ((adev->pdev->revision == 0x81) ||
7672                     (adev->pdev->revision == 0x83) ||
7673                     (adev->pdev->revision == 0x87) ||
7674                     (adev->pdev->device == 0x6820) ||
7675                     (adev->pdev->device == 0x6821) ||
7676                     (adev->pdev->device == 0x6822) ||
7677                     (adev->pdev->device == 0x6823) ||
7678                     (adev->pdev->device == 0x682A) ||
7679                     (adev->pdev->device == 0x682B))
7680                         chip_name = "verde_k";
7681                 else
7682                         chip_name = "verde";
7683                 break;
7684         case CHIP_OLAND:
7685                 if ((adev->pdev->revision == 0xC7) ||
7686                     (adev->pdev->revision == 0x80) ||
7687                     (adev->pdev->revision == 0x81) ||
7688                     (adev->pdev->revision == 0x83) ||
7689                     (adev->pdev->device == 0x6604) ||
7690                     (adev->pdev->device == 0x6605))
7691                         chip_name = "oland_k";
7692                 else
7693                         chip_name = "oland";
7694                 break;
7695         case CHIP_HAINAN:
7696                 if ((adev->pdev->revision == 0x81) ||
7697                     (adev->pdev->revision == 0x83) ||
7698                     (adev->pdev->revision == 0xC3) ||
7699                     (adev->pdev->device == 0x6664) ||
7700                     (adev->pdev->device == 0x6665) ||
7701                     (adev->pdev->device == 0x6667))
7702                         chip_name = "hainan_k";
7703                 else
7704                         chip_name = "hainan";
7705                 break;
7706         default: BUG();
7707         }
7708
7709         snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
7710         err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
7711         if (err)
7712                 goto out;
7713         err = amdgpu_ucode_validate(adev->pm.fw);
7714
7715 out:
7716         if (err) {
7717                 DRM_ERROR("si_smc: Failed to load firmware. err = %d\"%s\"\n",
7718                           err, fw_name);
7719                 release_firmware(adev->pm.fw);
7720                 adev->pm.fw = NULL;
7721         }
7722         return err;
7723
7724 }
7725
7726 static int si_dpm_sw_init(void *handle)
7727 {
7728         int ret;
7729         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7730
7731         ret = amdgpu_irq_add_id(adev, 230, &adev->pm.dpm.thermal.irq);
7732         if (ret)
7733                 return ret;
7734
7735         ret = amdgpu_irq_add_id(adev, 231, &adev->pm.dpm.thermal.irq);
7736         if (ret)
7737                 return ret;
7738
7739         /* default to balanced state */
7740         adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
7741         adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
7742         adev->pm.dpm.forced_level = AMDGPU_DPM_FORCED_LEVEL_AUTO;
7743         adev->pm.default_sclk = adev->clock.default_sclk;
7744         adev->pm.default_mclk = adev->clock.default_mclk;
7745         adev->pm.current_sclk = adev->clock.default_sclk;
7746         adev->pm.current_mclk = adev->clock.default_mclk;
7747         adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
7748
7749         if (amdgpu_dpm == 0)
7750                 return 0;
7751
7752         ret = si_dpm_init_microcode(adev);
7753         if (ret)
7754                 return ret;
7755
7756         INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler);
7757         mutex_lock(&adev->pm.mutex);
7758         ret = si_dpm_init(adev);
7759         if (ret)
7760                 goto dpm_failed;
7761         adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
7762         if (amdgpu_dpm == 1)
7763                 amdgpu_pm_print_power_states(adev);
7764         mutex_unlock(&adev->pm.mutex);
7765         DRM_INFO("amdgpu: dpm initialized\n");
7766
7767         return 0;
7768
7769 dpm_failed:
7770         si_dpm_fini(adev);
7771         mutex_unlock(&adev->pm.mutex);
7772         DRM_ERROR("amdgpu: dpm initialization failed\n");
7773         return ret;
7774 }
7775
7776 static int si_dpm_sw_fini(void *handle)
7777 {
7778         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7779
7780         mutex_lock(&adev->pm.mutex);
7781         amdgpu_pm_sysfs_fini(adev);
7782         si_dpm_fini(adev);
7783         mutex_unlock(&adev->pm.mutex);
7784
7785         return 0;
7786 }
7787
7788 static int si_dpm_hw_init(void *handle)
7789 {
7790         int ret;
7791
7792         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7793
7794         if (!amdgpu_dpm)
7795                 return 0;
7796
7797         mutex_lock(&adev->pm.mutex);
7798         si_dpm_setup_asic(adev);
7799         ret = si_dpm_enable(adev);
7800         if (ret)
7801                 adev->pm.dpm_enabled = false;
7802         else
7803                 adev->pm.dpm_enabled = true;
7804         mutex_unlock(&adev->pm.mutex);
7805
7806         return ret;
7807 }
7808
7809 static int si_dpm_hw_fini(void *handle)
7810 {
7811         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7812
7813         if (adev->pm.dpm_enabled) {
7814                 mutex_lock(&adev->pm.mutex);
7815                 si_dpm_disable(adev);
7816                 mutex_unlock(&adev->pm.mutex);
7817         }
7818
7819         return 0;
7820 }
7821
7822 static int si_dpm_suspend(void *handle)
7823 {
7824         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7825
7826         if (adev->pm.dpm_enabled) {
7827                 mutex_lock(&adev->pm.mutex);
7828                 /* disable dpm */
7829                 si_dpm_disable(adev);
7830                 /* reset the power state */
7831                 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
7832                 mutex_unlock(&adev->pm.mutex);
7833         }
7834         return 0;
7835 }
7836
7837 static int si_dpm_resume(void *handle)
7838 {
7839         int ret;
7840         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7841
7842         if (adev->pm.dpm_enabled) {
7843                 /* asic init will reset to the boot state */
7844                 mutex_lock(&adev->pm.mutex);
7845                 si_dpm_setup_asic(adev);
7846                 ret = si_dpm_enable(adev);
7847                 if (ret)
7848                         adev->pm.dpm_enabled = false;
7849                 else
7850                         adev->pm.dpm_enabled = true;
7851                 mutex_unlock(&adev->pm.mutex);
7852                 if (adev->pm.dpm_enabled)
7853                         amdgpu_pm_compute_clocks(adev);
7854         }
7855         return 0;
7856 }
7857
7858 static bool si_dpm_is_idle(void *handle)
7859 {
7860         /* XXX */
7861         return true;
7862 }
7863
7864 static int si_dpm_wait_for_idle(void *handle)
7865 {
7866         /* XXX */
7867         return 0;
7868 }
7869
7870 static int si_dpm_soft_reset(void *handle)
7871 {
7872         return 0;
7873 }
7874
7875 static int si_dpm_set_clockgating_state(void *handle,
7876                                         enum amd_clockgating_state state)
7877 {
7878         return 0;
7879 }
7880
7881 static int si_dpm_set_powergating_state(void *handle,
7882                                         enum amd_powergating_state state)
7883 {
7884         return 0;
7885 }
7886
7887 /* get temperature in millidegrees */
7888 static int si_dpm_get_temp(struct amdgpu_device *adev)
7889 {
7890         u32 temp;
7891         int actual_temp = 0;
7892
7893         temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
7894                 CTF_TEMP_SHIFT;
7895
7896         if (temp & 0x200)
7897                 actual_temp = 255;
7898         else
7899                 actual_temp = temp & 0x1ff;
7900
7901         actual_temp = (actual_temp * 1000);
7902
7903         return actual_temp;
7904 }
7905
7906 static u32 si_dpm_get_sclk(struct amdgpu_device *adev, bool low)
7907 {
7908         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7909         struct  si_ps *requested_state = si_get_ps(&eg_pi->requested_rps);
7910
7911         if (low)
7912                 return requested_state->performance_levels[0].sclk;
7913         else
7914                 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
7915 }
7916
7917 static u32 si_dpm_get_mclk(struct amdgpu_device *adev, bool low)
7918 {
7919         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7920         struct  si_ps *requested_state = si_get_ps(&eg_pi->requested_rps);
7921
7922         if (low)
7923                 return requested_state->performance_levels[0].mclk;
7924         else
7925                 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
7926 }
7927
7928 static void si_dpm_print_power_state(struct amdgpu_device *adev,
7929                                      struct amdgpu_ps *rps)
7930 {
7931         struct  si_ps *ps = si_get_ps(rps);
7932         struct rv7xx_pl *pl;
7933         int i;
7934
7935         amdgpu_dpm_print_class_info(rps->class, rps->class2);
7936         amdgpu_dpm_print_cap_info(rps->caps);
7937         DRM_INFO("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7938         for (i = 0; i < ps->performance_level_count; i++) {
7939                 pl = &ps->performance_levels[i];
7940                 if (adev->asic_type >= CHIP_TAHITI)
7941                         DRM_INFO("\t\tpower level %d    sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7942                                  i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7943                 else
7944                         DRM_INFO("\t\tpower level %d    sclk: %u mclk: %u vddc: %u vddci: %u\n",
7945                                  i, pl->sclk, pl->mclk, pl->vddc, pl->vddci);
7946         }
7947         amdgpu_dpm_print_ps_status(adev, rps);
7948 }
7949
7950 static int si_dpm_early_init(void *handle)
7951 {
7952
7953         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7954
7955         si_dpm_set_dpm_funcs(adev);
7956         si_dpm_set_irq_funcs(adev);
7957         return 0;
7958 }
7959
7960
7961 const struct amd_ip_funcs si_dpm_ip_funcs = {
7962         .name = "si_dpm",
7963         .early_init = si_dpm_early_init,
7964         .late_init = si_dpm_late_init,
7965         .sw_init = si_dpm_sw_init,
7966         .sw_fini = si_dpm_sw_fini,
7967         .hw_init = si_dpm_hw_init,
7968         .hw_fini = si_dpm_hw_fini,
7969         .suspend = si_dpm_suspend,
7970         .resume = si_dpm_resume,
7971         .is_idle = si_dpm_is_idle,
7972         .wait_for_idle = si_dpm_wait_for_idle,
7973         .soft_reset = si_dpm_soft_reset,
7974         .set_clockgating_state = si_dpm_set_clockgating_state,
7975         .set_powergating_state = si_dpm_set_powergating_state,
7976 };
7977
7978 static const struct amdgpu_dpm_funcs si_dpm_funcs = {
7979         .get_temperature = &si_dpm_get_temp,
7980         .pre_set_power_state = &si_dpm_pre_set_power_state,
7981         .set_power_state = &si_dpm_set_power_state,
7982         .post_set_power_state = &si_dpm_post_set_power_state,
7983         .display_configuration_changed = &si_dpm_display_configuration_changed,
7984         .get_sclk = &si_dpm_get_sclk,
7985         .get_mclk = &si_dpm_get_mclk,
7986         .print_power_state = &si_dpm_print_power_state,
7987         .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
7988         .force_performance_level = &si_dpm_force_performance_level,
7989         .vblank_too_short = &si_dpm_vblank_too_short,
7990         .set_fan_control_mode = &si_dpm_set_fan_control_mode,
7991         .get_fan_control_mode = &si_dpm_get_fan_control_mode,
7992         .set_fan_speed_percent = &si_dpm_set_fan_speed_percent,
7993         .get_fan_speed_percent = &si_dpm_get_fan_speed_percent,
7994 };
7995
7996 static void si_dpm_set_dpm_funcs(struct amdgpu_device *adev)
7997 {
7998         if (adev->pm.funcs == NULL)
7999                 adev->pm.funcs = &si_dpm_funcs;
8000 }
8001
8002 static const struct amdgpu_irq_src_funcs si_dpm_irq_funcs = {
8003         .set = si_dpm_set_interrupt_state,
8004         .process = si_dpm_process_interrupt,
8005 };
8006
8007 static void si_dpm_set_irq_funcs(struct amdgpu_device *adev)
8008 {
8009         adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST;
8010         adev->pm.dpm.thermal.irq.funcs = &si_dpm_irq_funcs;
8011 }
8012