2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
28 #include "amdgpu_atombios.h"
29 #include "amdgpu_ih.h"
30 #include "amdgpu_uvd.h"
31 #include "amdgpu_vce.h"
32 #include "amdgpu_ucode.h"
36 #include "gmc/gmc_8_1_d.h"
37 #include "gmc/gmc_8_1_sh_mask.h"
39 #include "oss/oss_3_0_d.h"
40 #include "oss/oss_3_0_sh_mask.h"
42 #include "bif/bif_5_0_d.h"
43 #include "bif/bif_5_0_sh_mask.h"
45 #include "gca/gfx_8_0_d.h"
46 #include "gca/gfx_8_0_sh_mask.h"
48 #include "smu/smu_7_1_1_d.h"
49 #include "smu/smu_7_1_1_sh_mask.h"
51 #include "uvd/uvd_5_0_d.h"
52 #include "uvd/uvd_5_0_sh_mask.h"
54 #include "vce/vce_3_0_d.h"
55 #include "vce/vce_3_0_sh_mask.h"
57 #include "dce/dce_10_0_d.h"
58 #include "dce/dce_10_0_sh_mask.h"
66 #include "sdma_v2_4.h"
67 #include "sdma_v3_0.h"
68 #include "dce_v10_0.h"
69 #include "dce_v11_0.h"
70 #include "iceland_ih.h"
76 #include "amdgpu_powerplay.h"
77 #if defined(CONFIG_DRM_AMD_ACP)
78 #include "amdgpu_acp.h"
81 MODULE_FIRMWARE("amdgpu/polaris10_smc.bin");
82 MODULE_FIRMWARE("amdgpu/polaris10_smc_sk.bin");
83 MODULE_FIRMWARE("amdgpu/polaris11_smc.bin");
84 MODULE_FIRMWARE("amdgpu/polaris11_smc_sk.bin");
87 * Indirect registers accessor
89 static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg)
94 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
95 WREG32(mmPCIE_INDEX, reg);
96 (void)RREG32(mmPCIE_INDEX);
97 r = RREG32(mmPCIE_DATA);
98 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
102 static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
106 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
107 WREG32(mmPCIE_INDEX, reg);
108 (void)RREG32(mmPCIE_INDEX);
109 WREG32(mmPCIE_DATA, v);
110 (void)RREG32(mmPCIE_DATA);
111 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
114 static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg)
119 spin_lock_irqsave(&adev->smc_idx_lock, flags);
120 WREG32(mmSMC_IND_INDEX_0, (reg));
121 r = RREG32(mmSMC_IND_DATA_0);
122 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
126 static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
130 spin_lock_irqsave(&adev->smc_idx_lock, flags);
131 WREG32(mmSMC_IND_INDEX_0, (reg));
132 WREG32(mmSMC_IND_DATA_0, (v));
133 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
137 #define mmMP0PUB_IND_INDEX 0x180
138 #define mmMP0PUB_IND_DATA 0x181
140 static u32 cz_smc_rreg(struct amdgpu_device *adev, u32 reg)
145 spin_lock_irqsave(&adev->smc_idx_lock, flags);
146 WREG32(mmMP0PUB_IND_INDEX, (reg));
147 r = RREG32(mmMP0PUB_IND_DATA);
148 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
152 static void cz_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
156 spin_lock_irqsave(&adev->smc_idx_lock, flags);
157 WREG32(mmMP0PUB_IND_INDEX, (reg));
158 WREG32(mmMP0PUB_IND_DATA, (v));
159 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
162 static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
167 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
168 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
169 r = RREG32(mmUVD_CTX_DATA);
170 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
174 static void vi_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
178 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
179 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
180 WREG32(mmUVD_CTX_DATA, (v));
181 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
184 static u32 vi_didt_rreg(struct amdgpu_device *adev, u32 reg)
189 spin_lock_irqsave(&adev->didt_idx_lock, flags);
190 WREG32(mmDIDT_IND_INDEX, (reg));
191 r = RREG32(mmDIDT_IND_DATA);
192 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
196 static void vi_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
200 spin_lock_irqsave(&adev->didt_idx_lock, flags);
201 WREG32(mmDIDT_IND_INDEX, (reg));
202 WREG32(mmDIDT_IND_DATA, (v));
203 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
206 static u32 vi_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
211 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
212 WREG32(mmGC_CAC_IND_INDEX, (reg));
213 r = RREG32(mmGC_CAC_IND_DATA);
214 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
218 static void vi_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
222 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
223 WREG32(mmGC_CAC_IND_INDEX, (reg));
224 WREG32(mmGC_CAC_IND_DATA, (v));
225 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
229 static const u32 tonga_mgcg_cgcg_init[] =
231 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
232 mmPCIE_INDEX, 0xffffffff, 0x0140001c,
233 mmPCIE_DATA, 0x000f0000, 0x00000000,
234 mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
235 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
236 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
237 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
240 static const u32 fiji_mgcg_cgcg_init[] =
242 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
243 mmPCIE_INDEX, 0xffffffff, 0x0140001c,
244 mmPCIE_DATA, 0x000f0000, 0x00000000,
245 mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
246 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
247 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
248 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
251 static const u32 iceland_mgcg_cgcg_init[] =
253 mmPCIE_INDEX, 0xffffffff, ixPCIE_CNTL2,
254 mmPCIE_DATA, 0x000f0000, 0x00000000,
255 mmSMC_IND_INDEX_4, 0xffffffff, ixCGTT_ROM_CLK_CTRL0,
256 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
257 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
260 static const u32 cz_mgcg_cgcg_init[] =
262 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
263 mmPCIE_INDEX, 0xffffffff, 0x0140001c,
264 mmPCIE_DATA, 0x000f0000, 0x00000000,
265 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
266 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
269 static const u32 stoney_mgcg_cgcg_init[] =
271 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00000100,
272 mmHDP_XDP_CGTT_BLK_CTRL, 0xffffffff, 0x00000104,
273 mmHDP_HOST_PATH_CNTL, 0xffffffff, 0x0f000027,
276 static void vi_init_golden_registers(struct amdgpu_device *adev)
278 /* Some of the registers might be dependent on GRBM_GFX_INDEX */
279 mutex_lock(&adev->grbm_idx_mutex);
281 switch (adev->asic_type) {
283 amdgpu_program_register_sequence(adev,
284 iceland_mgcg_cgcg_init,
285 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
288 amdgpu_program_register_sequence(adev,
290 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
293 amdgpu_program_register_sequence(adev,
294 tonga_mgcg_cgcg_init,
295 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
298 amdgpu_program_register_sequence(adev,
300 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
303 amdgpu_program_register_sequence(adev,
304 stoney_mgcg_cgcg_init,
305 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
312 mutex_unlock(&adev->grbm_idx_mutex);
316 * vi_get_xclk - get the xclk
318 * @adev: amdgpu_device pointer
320 * Returns the reference clock used by the gfx engine
323 static u32 vi_get_xclk(struct amdgpu_device *adev)
325 u32 reference_clock = adev->clock.spll.reference_freq;
328 if (adev->flags & AMD_IS_APU)
329 return reference_clock;
331 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2);
332 if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK))
335 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL);
336 if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL, XTALIN_DIVIDE))
337 return reference_clock / 4;
339 return reference_clock;
343 * vi_srbm_select - select specific register instances
345 * @adev: amdgpu_device pointer
346 * @me: selected ME (micro engine)
351 * Switches the currently active registers instances. Some
352 * registers are instanced per VMID, others are instanced per
353 * me/pipe/queue combination.
355 void vi_srbm_select(struct amdgpu_device *adev,
356 u32 me, u32 pipe, u32 queue, u32 vmid)
358 u32 srbm_gfx_cntl = 0;
359 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, PIPEID, pipe);
360 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, MEID, me);
361 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vmid);
362 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, QUEUEID, queue);
363 WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl);
366 static void vi_vga_set_state(struct amdgpu_device *adev, bool state)
371 static bool vi_read_disabled_bios(struct amdgpu_device *adev)
374 u32 d1vga_control = 0;
375 u32 d2vga_control = 0;
376 u32 vga_render_control = 0;
380 bus_cntl = RREG32(mmBUS_CNTL);
381 if (adev->mode_info.num_crtc) {
382 d1vga_control = RREG32(mmD1VGA_CONTROL);
383 d2vga_control = RREG32(mmD2VGA_CONTROL);
384 vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
386 rom_cntl = RREG32_SMC(ixROM_CNTL);
389 WREG32(mmBUS_CNTL, (bus_cntl & ~BUS_CNTL__BIOS_ROM_DIS_MASK));
390 if (adev->mode_info.num_crtc) {
391 /* Disable VGA mode */
392 WREG32(mmD1VGA_CONTROL,
393 (d1vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK |
394 D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK)));
395 WREG32(mmD2VGA_CONTROL,
396 (d2vga_control & ~(D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK |
397 D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK)));
398 WREG32(mmVGA_RENDER_CONTROL,
399 (vga_render_control & ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK));
401 WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK);
403 r = amdgpu_read_bios(adev);
406 WREG32(mmBUS_CNTL, bus_cntl);
407 if (adev->mode_info.num_crtc) {
408 WREG32(mmD1VGA_CONTROL, d1vga_control);
409 WREG32(mmD2VGA_CONTROL, d2vga_control);
410 WREG32(mmVGA_RENDER_CONTROL, vga_render_control);
412 WREG32_SMC(ixROM_CNTL, rom_cntl);
416 static bool vi_read_bios_from_rom(struct amdgpu_device *adev,
417 u8 *bios, u32 length_bytes)
425 if (length_bytes == 0)
427 /* APU vbios image is part of sbios image */
428 if (adev->flags & AMD_IS_APU)
431 dw_ptr = (u32 *)bios;
432 length_dw = ALIGN(length_bytes, 4) / 4;
433 /* take the smc lock since we are using the smc index */
434 spin_lock_irqsave(&adev->smc_idx_lock, flags);
435 /* set rom index to 0 */
436 WREG32(mmSMC_IND_INDEX_0, ixROM_INDEX);
437 WREG32(mmSMC_IND_DATA_0, 0);
438 /* set index to data for continous read */
439 WREG32(mmSMC_IND_INDEX_0, ixROM_DATA);
440 for (i = 0; i < length_dw; i++)
441 dw_ptr[i] = RREG32(mmSMC_IND_DATA_0);
442 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
447 static u32 vi_get_virtual_caps(struct amdgpu_device *adev)
450 u32 reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER);
452 if (REG_GET_FIELD(reg, BIF_IOV_FUNC_IDENTIFIER, IOV_ENABLE))
453 caps |= AMDGPU_VIRT_CAPS_SRIOV_EN;
455 if (REG_GET_FIELD(reg, BIF_IOV_FUNC_IDENTIFIER, FUNC_IDENTIFIER))
456 caps |= AMDGPU_VIRT_CAPS_IS_VF;
461 static const struct amdgpu_allowed_register_entry tonga_allowed_read_registers[] = {
462 {mmGB_MACROTILE_MODE7, true},
465 static const struct amdgpu_allowed_register_entry cz_allowed_read_registers[] = {
466 {mmGB_TILE_MODE7, true},
467 {mmGB_TILE_MODE12, true},
468 {mmGB_TILE_MODE17, true},
469 {mmGB_TILE_MODE23, true},
470 {mmGB_MACROTILE_MODE7, true},
473 static const struct amdgpu_allowed_register_entry vi_allowed_read_registers[] = {
474 {mmGRBM_STATUS, false},
475 {mmGRBM_STATUS2, false},
476 {mmGRBM_STATUS_SE0, false},
477 {mmGRBM_STATUS_SE1, false},
478 {mmGRBM_STATUS_SE2, false},
479 {mmGRBM_STATUS_SE3, false},
480 {mmSRBM_STATUS, false},
481 {mmSRBM_STATUS2, false},
482 {mmSRBM_STATUS3, false},
483 {mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET, false},
484 {mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET, false},
486 {mmCP_STALLED_STAT1, false},
487 {mmCP_STALLED_STAT2, false},
488 {mmCP_STALLED_STAT3, false},
489 {mmCP_CPF_BUSY_STAT, false},
490 {mmCP_CPF_STALLED_STAT1, false},
491 {mmCP_CPF_STATUS, false},
492 {mmCP_CPC_BUSY_STAT, false},
493 {mmCP_CPC_STALLED_STAT1, false},
494 {mmCP_CPC_STATUS, false},
495 {mmGB_ADDR_CONFIG, false},
496 {mmMC_ARB_RAMCFG, false},
497 {mmGB_TILE_MODE0, false},
498 {mmGB_TILE_MODE1, false},
499 {mmGB_TILE_MODE2, false},
500 {mmGB_TILE_MODE3, false},
501 {mmGB_TILE_MODE4, false},
502 {mmGB_TILE_MODE5, false},
503 {mmGB_TILE_MODE6, false},
504 {mmGB_TILE_MODE7, false},
505 {mmGB_TILE_MODE8, false},
506 {mmGB_TILE_MODE9, false},
507 {mmGB_TILE_MODE10, false},
508 {mmGB_TILE_MODE11, false},
509 {mmGB_TILE_MODE12, false},
510 {mmGB_TILE_MODE13, false},
511 {mmGB_TILE_MODE14, false},
512 {mmGB_TILE_MODE15, false},
513 {mmGB_TILE_MODE16, false},
514 {mmGB_TILE_MODE17, false},
515 {mmGB_TILE_MODE18, false},
516 {mmGB_TILE_MODE19, false},
517 {mmGB_TILE_MODE20, false},
518 {mmGB_TILE_MODE21, false},
519 {mmGB_TILE_MODE22, false},
520 {mmGB_TILE_MODE23, false},
521 {mmGB_TILE_MODE24, false},
522 {mmGB_TILE_MODE25, false},
523 {mmGB_TILE_MODE26, false},
524 {mmGB_TILE_MODE27, false},
525 {mmGB_TILE_MODE28, false},
526 {mmGB_TILE_MODE29, false},
527 {mmGB_TILE_MODE30, false},
528 {mmGB_TILE_MODE31, false},
529 {mmGB_MACROTILE_MODE0, false},
530 {mmGB_MACROTILE_MODE1, false},
531 {mmGB_MACROTILE_MODE2, false},
532 {mmGB_MACROTILE_MODE3, false},
533 {mmGB_MACROTILE_MODE4, false},
534 {mmGB_MACROTILE_MODE5, false},
535 {mmGB_MACROTILE_MODE6, false},
536 {mmGB_MACROTILE_MODE7, false},
537 {mmGB_MACROTILE_MODE8, false},
538 {mmGB_MACROTILE_MODE9, false},
539 {mmGB_MACROTILE_MODE10, false},
540 {mmGB_MACROTILE_MODE11, false},
541 {mmGB_MACROTILE_MODE12, false},
542 {mmGB_MACROTILE_MODE13, false},
543 {mmGB_MACROTILE_MODE14, false},
544 {mmGB_MACROTILE_MODE15, false},
545 {mmCC_RB_BACKEND_DISABLE, false, true},
546 {mmGC_USER_RB_BACKEND_DISABLE, false, true},
547 {mmGB_BACKEND_MAP, false, false},
548 {mmPA_SC_RASTER_CONFIG, false, true},
549 {mmPA_SC_RASTER_CONFIG_1, false, true},
552 static uint32_t vi_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
553 u32 sh_num, u32 reg_offset)
557 mutex_lock(&adev->grbm_idx_mutex);
558 if (se_num != 0xffffffff || sh_num != 0xffffffff)
559 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
561 val = RREG32(reg_offset);
563 if (se_num != 0xffffffff || sh_num != 0xffffffff)
564 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
565 mutex_unlock(&adev->grbm_idx_mutex);
569 static int vi_read_register(struct amdgpu_device *adev, u32 se_num,
570 u32 sh_num, u32 reg_offset, u32 *value)
572 const struct amdgpu_allowed_register_entry *asic_register_table = NULL;
573 const struct amdgpu_allowed_register_entry *asic_register_entry;
577 switch (adev->asic_type) {
579 asic_register_table = tonga_allowed_read_registers;
580 size = ARRAY_SIZE(tonga_allowed_read_registers);
588 asic_register_table = cz_allowed_read_registers;
589 size = ARRAY_SIZE(cz_allowed_read_registers);
595 if (asic_register_table) {
596 for (i = 0; i < size; i++) {
597 asic_register_entry = asic_register_table + i;
598 if (reg_offset != asic_register_entry->reg_offset)
600 if (!asic_register_entry->untouched)
601 *value = asic_register_entry->grbm_indexed ?
602 vi_read_indexed_register(adev, se_num,
603 sh_num, reg_offset) :
609 for (i = 0; i < ARRAY_SIZE(vi_allowed_read_registers); i++) {
610 if (reg_offset != vi_allowed_read_registers[i].reg_offset)
613 if (!vi_allowed_read_registers[i].untouched)
614 *value = vi_allowed_read_registers[i].grbm_indexed ?
615 vi_read_indexed_register(adev, se_num,
616 sh_num, reg_offset) :
623 static int vi_gpu_pci_config_reset(struct amdgpu_device *adev)
627 dev_info(adev->dev, "GPU pci config reset\n");
630 pci_clear_master(adev->pdev);
632 amdgpu_pci_config_reset(adev);
636 /* wait for asic to come out of reset */
637 for (i = 0; i < adev->usec_timeout; i++) {
638 if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) {
640 pci_set_master(adev->pdev);
648 static void vi_set_bios_scratch_engine_hung(struct amdgpu_device *adev, bool hung)
650 u32 tmp = RREG32(mmBIOS_SCRATCH_3);
653 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
655 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
657 WREG32(mmBIOS_SCRATCH_3, tmp);
661 * vi_asic_reset - soft reset GPU
663 * @adev: amdgpu_device pointer
665 * Look up which blocks are hung and attempt
667 * Returns 0 for success.
669 static int vi_asic_reset(struct amdgpu_device *adev)
673 vi_set_bios_scratch_engine_hung(adev, true);
675 r = vi_gpu_pci_config_reset(adev);
677 vi_set_bios_scratch_engine_hung(adev, false);
682 static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
683 u32 cntl_reg, u32 status_reg)
686 struct atom_clock_dividers dividers;
689 r = amdgpu_atombios_get_clock_dividers(adev,
690 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
691 clock, false, ÷rs);
695 tmp = RREG32_SMC(cntl_reg);
696 tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK |
697 CG_DCLK_CNTL__DCLK_DIVIDER_MASK);
698 tmp |= dividers.post_divider;
699 WREG32_SMC(cntl_reg, tmp);
701 for (i = 0; i < 100; i++) {
702 if (RREG32_SMC(status_reg) & CG_DCLK_STATUS__DCLK_STATUS_MASK)
712 static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
716 r = vi_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
720 r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
725 static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
732 static void vi_pcie_gen3_enable(struct amdgpu_device *adev)
734 if (pci_is_root_bus(adev->pdev->bus))
737 if (amdgpu_pcie_gen2 == 0)
740 if (adev->flags & AMD_IS_APU)
743 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
744 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
750 static void vi_program_aspm(struct amdgpu_device *adev)
753 if (amdgpu_aspm == 0)
759 static void vi_enable_doorbell_aperture(struct amdgpu_device *adev,
764 /* not necessary on CZ */
765 if (adev->flags & AMD_IS_APU)
768 tmp = RREG32(mmBIF_DOORBELL_APER_EN);
770 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 1);
772 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 0);
774 WREG32(mmBIF_DOORBELL_APER_EN, tmp);
777 /* topaz has no DCE, UVD, VCE */
778 static const struct amdgpu_ip_block_version topaz_ip_blocks[] =
782 .type = AMD_IP_BLOCK_TYPE_COMMON,
786 .funcs = &vi_common_ip_funcs,
789 .type = AMD_IP_BLOCK_TYPE_GMC,
793 .funcs = &gmc_v7_0_ip_funcs,
796 .type = AMD_IP_BLOCK_TYPE_IH,
800 .funcs = &iceland_ih_ip_funcs,
803 .type = AMD_IP_BLOCK_TYPE_SMC,
807 .funcs = &amdgpu_pp_ip_funcs,
810 .type = AMD_IP_BLOCK_TYPE_GFX,
814 .funcs = &gfx_v8_0_ip_funcs,
817 .type = AMD_IP_BLOCK_TYPE_SDMA,
821 .funcs = &sdma_v2_4_ip_funcs,
825 static const struct amdgpu_ip_block_version tonga_ip_blocks[] =
829 .type = AMD_IP_BLOCK_TYPE_COMMON,
833 .funcs = &vi_common_ip_funcs,
836 .type = AMD_IP_BLOCK_TYPE_GMC,
840 .funcs = &gmc_v8_0_ip_funcs,
843 .type = AMD_IP_BLOCK_TYPE_IH,
847 .funcs = &tonga_ih_ip_funcs,
850 .type = AMD_IP_BLOCK_TYPE_SMC,
854 .funcs = &amdgpu_pp_ip_funcs,
857 .type = AMD_IP_BLOCK_TYPE_DCE,
861 .funcs = &dce_v10_0_ip_funcs,
864 .type = AMD_IP_BLOCK_TYPE_GFX,
868 .funcs = &gfx_v8_0_ip_funcs,
871 .type = AMD_IP_BLOCK_TYPE_SDMA,
875 .funcs = &sdma_v3_0_ip_funcs,
878 .type = AMD_IP_BLOCK_TYPE_UVD,
882 .funcs = &uvd_v5_0_ip_funcs,
885 .type = AMD_IP_BLOCK_TYPE_VCE,
889 .funcs = &vce_v3_0_ip_funcs,
893 static const struct amdgpu_ip_block_version fiji_ip_blocks[] =
897 .type = AMD_IP_BLOCK_TYPE_COMMON,
901 .funcs = &vi_common_ip_funcs,
904 .type = AMD_IP_BLOCK_TYPE_GMC,
908 .funcs = &gmc_v8_0_ip_funcs,
911 .type = AMD_IP_BLOCK_TYPE_IH,
915 .funcs = &tonga_ih_ip_funcs,
918 .type = AMD_IP_BLOCK_TYPE_SMC,
922 .funcs = &amdgpu_pp_ip_funcs,
925 .type = AMD_IP_BLOCK_TYPE_DCE,
929 .funcs = &dce_v10_0_ip_funcs,
932 .type = AMD_IP_BLOCK_TYPE_GFX,
936 .funcs = &gfx_v8_0_ip_funcs,
939 .type = AMD_IP_BLOCK_TYPE_SDMA,
943 .funcs = &sdma_v3_0_ip_funcs,
946 .type = AMD_IP_BLOCK_TYPE_UVD,
950 .funcs = &uvd_v6_0_ip_funcs,
953 .type = AMD_IP_BLOCK_TYPE_VCE,
957 .funcs = &vce_v3_0_ip_funcs,
961 static const struct amdgpu_ip_block_version polaris11_ip_blocks[] =
965 .type = AMD_IP_BLOCK_TYPE_COMMON,
969 .funcs = &vi_common_ip_funcs,
972 .type = AMD_IP_BLOCK_TYPE_GMC,
976 .funcs = &gmc_v8_0_ip_funcs,
979 .type = AMD_IP_BLOCK_TYPE_IH,
983 .funcs = &tonga_ih_ip_funcs,
986 .type = AMD_IP_BLOCK_TYPE_SMC,
990 .funcs = &amdgpu_pp_ip_funcs,
993 .type = AMD_IP_BLOCK_TYPE_DCE,
997 .funcs = &dce_v11_0_ip_funcs,
1000 .type = AMD_IP_BLOCK_TYPE_GFX,
1004 .funcs = &gfx_v8_0_ip_funcs,
1007 .type = AMD_IP_BLOCK_TYPE_SDMA,
1011 .funcs = &sdma_v3_0_ip_funcs,
1014 .type = AMD_IP_BLOCK_TYPE_UVD,
1018 .funcs = &uvd_v6_0_ip_funcs,
1021 .type = AMD_IP_BLOCK_TYPE_VCE,
1025 .funcs = &vce_v3_0_ip_funcs,
1029 static const struct amdgpu_ip_block_version cz_ip_blocks[] =
1031 /* ORDER MATTERS! */
1033 .type = AMD_IP_BLOCK_TYPE_COMMON,
1037 .funcs = &vi_common_ip_funcs,
1040 .type = AMD_IP_BLOCK_TYPE_GMC,
1044 .funcs = &gmc_v8_0_ip_funcs,
1047 .type = AMD_IP_BLOCK_TYPE_IH,
1051 .funcs = &cz_ih_ip_funcs,
1054 .type = AMD_IP_BLOCK_TYPE_SMC,
1058 .funcs = &amdgpu_pp_ip_funcs
1061 .type = AMD_IP_BLOCK_TYPE_DCE,
1065 .funcs = &dce_v11_0_ip_funcs,
1068 .type = AMD_IP_BLOCK_TYPE_GFX,
1072 .funcs = &gfx_v8_0_ip_funcs,
1075 .type = AMD_IP_BLOCK_TYPE_SDMA,
1079 .funcs = &sdma_v3_0_ip_funcs,
1082 .type = AMD_IP_BLOCK_TYPE_UVD,
1086 .funcs = &uvd_v6_0_ip_funcs,
1089 .type = AMD_IP_BLOCK_TYPE_VCE,
1093 .funcs = &vce_v3_0_ip_funcs,
1095 #if defined(CONFIG_DRM_AMD_ACP)
1097 .type = AMD_IP_BLOCK_TYPE_ACP,
1101 .funcs = &acp_ip_funcs,
1106 int vi_set_ip_blocks(struct amdgpu_device *adev)
1108 switch (adev->asic_type) {
1110 adev->ip_blocks = topaz_ip_blocks;
1111 adev->num_ip_blocks = ARRAY_SIZE(topaz_ip_blocks);
1114 adev->ip_blocks = fiji_ip_blocks;
1115 adev->num_ip_blocks = ARRAY_SIZE(fiji_ip_blocks);
1118 adev->ip_blocks = tonga_ip_blocks;
1119 adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks);
1121 case CHIP_POLARIS11:
1122 case CHIP_POLARIS10:
1123 adev->ip_blocks = polaris11_ip_blocks;
1124 adev->num_ip_blocks = ARRAY_SIZE(polaris11_ip_blocks);
1128 adev->ip_blocks = cz_ip_blocks;
1129 adev->num_ip_blocks = ARRAY_SIZE(cz_ip_blocks);
1132 /* FIXME: not supported yet */
1139 #define ATI_REV_ID_FUSE_MACRO__ADDRESS 0xC0014044
1140 #define ATI_REV_ID_FUSE_MACRO__SHIFT 9
1141 #define ATI_REV_ID_FUSE_MACRO__MASK 0x00001E00
1143 static uint32_t vi_get_rev_id(struct amdgpu_device *adev)
1145 if (adev->flags & AMD_IS_APU)
1146 return (RREG32_SMC(ATI_REV_ID_FUSE_MACRO__ADDRESS) & ATI_REV_ID_FUSE_MACRO__MASK)
1147 >> ATI_REV_ID_FUSE_MACRO__SHIFT;
1149 return (RREG32(mmPCIE_EFUSE4) & PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK)
1150 >> PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT;
1153 static const struct amdgpu_asic_funcs vi_asic_funcs =
1155 .read_disabled_bios = &vi_read_disabled_bios,
1156 .read_bios_from_rom = &vi_read_bios_from_rom,
1157 .read_register = &vi_read_register,
1158 .reset = &vi_asic_reset,
1159 .set_vga_state = &vi_vga_set_state,
1160 .get_xclk = &vi_get_xclk,
1161 .set_uvd_clocks = &vi_set_uvd_clocks,
1162 .set_vce_clocks = &vi_set_vce_clocks,
1163 .get_virtual_caps = &vi_get_virtual_caps,
1166 static int vi_common_early_init(void *handle)
1168 bool smc_enabled = false;
1169 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1171 if (adev->flags & AMD_IS_APU) {
1172 adev->smc_rreg = &cz_smc_rreg;
1173 adev->smc_wreg = &cz_smc_wreg;
1175 adev->smc_rreg = &vi_smc_rreg;
1176 adev->smc_wreg = &vi_smc_wreg;
1178 adev->pcie_rreg = &vi_pcie_rreg;
1179 adev->pcie_wreg = &vi_pcie_wreg;
1180 adev->uvd_ctx_rreg = &vi_uvd_ctx_rreg;
1181 adev->uvd_ctx_wreg = &vi_uvd_ctx_wreg;
1182 adev->didt_rreg = &vi_didt_rreg;
1183 adev->didt_wreg = &vi_didt_wreg;
1184 adev->gc_cac_rreg = &vi_gc_cac_rreg;
1185 adev->gc_cac_wreg = &vi_gc_cac_wreg;
1187 adev->asic_funcs = &vi_asic_funcs;
1189 if (amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC) &&
1190 (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_SMC)))
1193 adev->rev_id = vi_get_rev_id(adev);
1194 adev->external_rev_id = 0xFF;
1195 switch (adev->asic_type) {
1199 adev->external_rev_id = 0x1;
1202 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1203 AMD_CG_SUPPORT_GFX_MGLS |
1204 AMD_CG_SUPPORT_GFX_RLC_LS |
1205 AMD_CG_SUPPORT_GFX_CP_LS |
1206 AMD_CG_SUPPORT_GFX_CGTS |
1207 AMD_CG_SUPPORT_GFX_CGTS_LS |
1208 AMD_CG_SUPPORT_GFX_CGCG |
1209 AMD_CG_SUPPORT_GFX_CGLS |
1210 AMD_CG_SUPPORT_SDMA_MGCG |
1211 AMD_CG_SUPPORT_SDMA_LS |
1212 AMD_CG_SUPPORT_BIF_LS |
1213 AMD_CG_SUPPORT_HDP_MGCG |
1214 AMD_CG_SUPPORT_HDP_LS |
1215 AMD_CG_SUPPORT_ROM_MGCG |
1216 AMD_CG_SUPPORT_MC_MGCG |
1217 AMD_CG_SUPPORT_MC_LS;
1219 adev->external_rev_id = adev->rev_id + 0x3c;
1222 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG;
1224 adev->external_rev_id = adev->rev_id + 0x14;
1226 case CHIP_POLARIS11:
1229 adev->external_rev_id = adev->rev_id + 0x5A;
1231 case CHIP_POLARIS10:
1234 adev->external_rev_id = adev->rev_id + 0x50;
1237 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
1238 AMD_CG_SUPPORT_GFX_MGCG |
1239 AMD_CG_SUPPORT_GFX_MGLS |
1240 AMD_CG_SUPPORT_GFX_RLC_LS |
1241 AMD_CG_SUPPORT_GFX_CP_LS |
1242 AMD_CG_SUPPORT_GFX_CGTS |
1243 AMD_CG_SUPPORT_GFX_MGLS |
1244 AMD_CG_SUPPORT_GFX_CGTS_LS |
1245 AMD_CG_SUPPORT_GFX_CGCG |
1246 AMD_CG_SUPPORT_GFX_CGLS |
1247 AMD_CG_SUPPORT_BIF_LS |
1248 AMD_CG_SUPPORT_HDP_MGCG |
1249 AMD_CG_SUPPORT_HDP_LS |
1250 AMD_CG_SUPPORT_SDMA_MGCG |
1251 AMD_CG_SUPPORT_SDMA_LS;
1253 adev->external_rev_id = adev->rev_id + 0x1;
1256 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
1257 AMD_CG_SUPPORT_GFX_MGCG |
1258 AMD_CG_SUPPORT_GFX_MGLS |
1259 AMD_CG_SUPPORT_GFX_RLC_LS |
1260 AMD_CG_SUPPORT_GFX_CP_LS |
1261 AMD_CG_SUPPORT_GFX_CGTS |
1262 AMD_CG_SUPPORT_GFX_MGLS |
1263 AMD_CG_SUPPORT_GFX_CGTS_LS |
1264 AMD_CG_SUPPORT_GFX_CGCG |
1265 AMD_CG_SUPPORT_GFX_CGLS |
1266 AMD_CG_SUPPORT_BIF_LS |
1267 AMD_CG_SUPPORT_HDP_MGCG |
1268 AMD_CG_SUPPORT_HDP_LS |
1269 AMD_CG_SUPPORT_SDMA_MGCG |
1270 AMD_CG_SUPPORT_SDMA_LS;
1271 adev->external_rev_id = adev->rev_id + 0x1;
1274 /* FIXME: not supported yet */
1278 if (amdgpu_smc_load_fw && smc_enabled)
1279 adev->firmware.smu_load = true;
1281 amdgpu_get_pcie_info(adev);
1286 static int vi_common_sw_init(void *handle)
1291 static int vi_common_sw_fini(void *handle)
1296 static int vi_common_hw_init(void *handle)
1298 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1300 /* move the golden regs per IP block */
1301 vi_init_golden_registers(adev);
1302 /* enable pcie gen2/3 link */
1303 vi_pcie_gen3_enable(adev);
1305 vi_program_aspm(adev);
1306 /* enable the doorbell aperture */
1307 vi_enable_doorbell_aperture(adev, true);
1312 static int vi_common_hw_fini(void *handle)
1314 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1316 /* enable the doorbell aperture */
1317 vi_enable_doorbell_aperture(adev, false);
1322 static int vi_common_suspend(void *handle)
1324 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1326 return vi_common_hw_fini(adev);
1329 static int vi_common_resume(void *handle)
1331 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1333 return vi_common_hw_init(adev);
1336 static bool vi_common_is_idle(void *handle)
1341 static int vi_common_wait_for_idle(void *handle)
1346 static int vi_common_soft_reset(void *handle)
1351 static void vi_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev,
1354 uint32_t temp, data;
1356 temp = data = RREG32_PCIE(ixPCIE_CNTL2);
1358 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
1359 data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
1360 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
1361 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK;
1363 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
1364 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
1365 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
1368 WREG32_PCIE(ixPCIE_CNTL2, data);
1371 static void vi_update_hdp_medium_grain_clock_gating(struct amdgpu_device *adev,
1374 uint32_t temp, data;
1376 temp = data = RREG32(mmHDP_HOST_PATH_CNTL);
1378 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
1379 data &= ~HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK;
1381 data |= HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK;
1384 WREG32(mmHDP_HOST_PATH_CNTL, data);
1387 static void vi_update_hdp_light_sleep(struct amdgpu_device *adev,
1390 uint32_t temp, data;
1392 temp = data = RREG32(mmHDP_MEM_POWER_LS);
1394 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1395 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1397 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1400 WREG32(mmHDP_MEM_POWER_LS, data);
1403 static void vi_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
1406 uint32_t temp, data;
1408 temp = data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0);
1410 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
1411 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1412 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
1414 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1415 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
1418 WREG32_SMC(ixCGTT_ROM_CLK_CTRL0, data);
1421 static int vi_common_set_clockgating_state(void *handle,
1422 enum amd_clockgating_state state)
1424 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1426 switch (adev->asic_type) {
1428 vi_update_bif_medium_grain_light_sleep(adev,
1429 state == AMD_CG_STATE_GATE ? true : false);
1430 vi_update_hdp_medium_grain_clock_gating(adev,
1431 state == AMD_CG_STATE_GATE ? true : false);
1432 vi_update_hdp_light_sleep(adev,
1433 state == AMD_CG_STATE_GATE ? true : false);
1434 vi_update_rom_medium_grain_clock_gating(adev,
1435 state == AMD_CG_STATE_GATE ? true : false);
1439 vi_update_bif_medium_grain_light_sleep(adev,
1440 state == AMD_CG_STATE_GATE ? true : false);
1441 vi_update_hdp_medium_grain_clock_gating(adev,
1442 state == AMD_CG_STATE_GATE ? true : false);
1443 vi_update_hdp_light_sleep(adev,
1444 state == AMD_CG_STATE_GATE ? true : false);
1452 static int vi_common_set_powergating_state(void *handle,
1453 enum amd_powergating_state state)
1458 const struct amd_ip_funcs vi_common_ip_funcs = {
1459 .name = "vi_common",
1460 .early_init = vi_common_early_init,
1462 .sw_init = vi_common_sw_init,
1463 .sw_fini = vi_common_sw_fini,
1464 .hw_init = vi_common_hw_init,
1465 .hw_fini = vi_common_hw_fini,
1466 .suspend = vi_common_suspend,
1467 .resume = vi_common_resume,
1468 .is_idle = vi_common_is_idle,
1469 .wait_for_idle = vi_common_wait_for_idle,
1470 .soft_reset = vi_common_soft_reset,
1471 .set_clockgating_state = vi_common_set_clockgating_state,
1472 .set_powergating_state = vi_common_set_powergating_state,