2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
28 #include "amdgpu_atombios.h"
29 #include "amdgpu_ih.h"
30 #include "amdgpu_uvd.h"
31 #include "amdgpu_vce.h"
32 #include "amdgpu_ucode.h"
36 #include "gmc/gmc_8_1_d.h"
37 #include "gmc/gmc_8_1_sh_mask.h"
39 #include "oss/oss_3_0_d.h"
40 #include "oss/oss_3_0_sh_mask.h"
42 #include "bif/bif_5_0_d.h"
43 #include "bif/bif_5_0_sh_mask.h"
45 #include "gca/gfx_8_0_d.h"
46 #include "gca/gfx_8_0_sh_mask.h"
48 #include "smu/smu_7_1_1_d.h"
49 #include "smu/smu_7_1_1_sh_mask.h"
51 #include "uvd/uvd_5_0_d.h"
52 #include "uvd/uvd_5_0_sh_mask.h"
54 #include "vce/vce_3_0_d.h"
55 #include "vce/vce_3_0_sh_mask.h"
57 #include "dce/dce_10_0_d.h"
58 #include "dce/dce_10_0_sh_mask.h"
66 #include "sdma_v2_4.h"
67 #include "sdma_v3_0.h"
68 #include "dce_v10_0.h"
69 #include "dce_v11_0.h"
70 #include "iceland_ih.h"
76 #include "amdgpu_powerplay.h"
77 #if defined(CONFIG_DRM_AMD_ACP)
78 #include "amdgpu_acp.h"
80 #include "dce_virtual.h"
82 MODULE_FIRMWARE("amdgpu/polaris10_smc.bin");
83 MODULE_FIRMWARE("amdgpu/polaris10_smc_sk.bin");
84 MODULE_FIRMWARE("amdgpu/polaris11_smc.bin");
85 MODULE_FIRMWARE("amdgpu/polaris11_smc_sk.bin");
88 * Indirect registers accessor
90 static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg)
95 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
96 WREG32(mmPCIE_INDEX, reg);
97 (void)RREG32(mmPCIE_INDEX);
98 r = RREG32(mmPCIE_DATA);
99 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
103 static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
107 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
108 WREG32(mmPCIE_INDEX, reg);
109 (void)RREG32(mmPCIE_INDEX);
110 WREG32(mmPCIE_DATA, v);
111 (void)RREG32(mmPCIE_DATA);
112 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
115 static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg)
120 spin_lock_irqsave(&adev->smc_idx_lock, flags);
121 WREG32(mmSMC_IND_INDEX_0, (reg));
122 r = RREG32(mmSMC_IND_DATA_0);
123 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
127 static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
131 spin_lock_irqsave(&adev->smc_idx_lock, flags);
132 WREG32(mmSMC_IND_INDEX_0, (reg));
133 WREG32(mmSMC_IND_DATA_0, (v));
134 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
138 #define mmMP0PUB_IND_INDEX 0x180
139 #define mmMP0PUB_IND_DATA 0x181
141 static u32 cz_smc_rreg(struct amdgpu_device *adev, u32 reg)
146 spin_lock_irqsave(&adev->smc_idx_lock, flags);
147 WREG32(mmMP0PUB_IND_INDEX, (reg));
148 r = RREG32(mmMP0PUB_IND_DATA);
149 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
153 static void cz_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
157 spin_lock_irqsave(&adev->smc_idx_lock, flags);
158 WREG32(mmMP0PUB_IND_INDEX, (reg));
159 WREG32(mmMP0PUB_IND_DATA, (v));
160 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
163 static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
168 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
169 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
170 r = RREG32(mmUVD_CTX_DATA);
171 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
175 static void vi_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
179 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
180 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
181 WREG32(mmUVD_CTX_DATA, (v));
182 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
185 static u32 vi_didt_rreg(struct amdgpu_device *adev, u32 reg)
190 spin_lock_irqsave(&adev->didt_idx_lock, flags);
191 WREG32(mmDIDT_IND_INDEX, (reg));
192 r = RREG32(mmDIDT_IND_DATA);
193 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
197 static void vi_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
201 spin_lock_irqsave(&adev->didt_idx_lock, flags);
202 WREG32(mmDIDT_IND_INDEX, (reg));
203 WREG32(mmDIDT_IND_DATA, (v));
204 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
207 static u32 vi_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
212 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
213 WREG32(mmGC_CAC_IND_INDEX, (reg));
214 r = RREG32(mmGC_CAC_IND_DATA);
215 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
219 static void vi_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
223 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
224 WREG32(mmGC_CAC_IND_INDEX, (reg));
225 WREG32(mmGC_CAC_IND_DATA, (v));
226 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
230 static const u32 tonga_mgcg_cgcg_init[] =
232 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
233 mmPCIE_INDEX, 0xffffffff, 0x0140001c,
234 mmPCIE_DATA, 0x000f0000, 0x00000000,
235 mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
236 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
237 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
238 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
241 static const u32 fiji_mgcg_cgcg_init[] =
243 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
244 mmPCIE_INDEX, 0xffffffff, 0x0140001c,
245 mmPCIE_DATA, 0x000f0000, 0x00000000,
246 mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
247 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
248 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
249 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
252 static const u32 iceland_mgcg_cgcg_init[] =
254 mmPCIE_INDEX, 0xffffffff, ixPCIE_CNTL2,
255 mmPCIE_DATA, 0x000f0000, 0x00000000,
256 mmSMC_IND_INDEX_4, 0xffffffff, ixCGTT_ROM_CLK_CTRL0,
257 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
258 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
261 static const u32 cz_mgcg_cgcg_init[] =
263 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
264 mmPCIE_INDEX, 0xffffffff, 0x0140001c,
265 mmPCIE_DATA, 0x000f0000, 0x00000000,
266 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
267 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
270 static const u32 stoney_mgcg_cgcg_init[] =
272 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00000100,
273 mmHDP_XDP_CGTT_BLK_CTRL, 0xffffffff, 0x00000104,
274 mmHDP_HOST_PATH_CNTL, 0xffffffff, 0x0f000027,
277 static void vi_init_golden_registers(struct amdgpu_device *adev)
279 /* Some of the registers might be dependent on GRBM_GFX_INDEX */
280 mutex_lock(&adev->grbm_idx_mutex);
282 switch (adev->asic_type) {
284 amdgpu_program_register_sequence(adev,
285 iceland_mgcg_cgcg_init,
286 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
289 amdgpu_program_register_sequence(adev,
291 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
294 amdgpu_program_register_sequence(adev,
295 tonga_mgcg_cgcg_init,
296 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
299 amdgpu_program_register_sequence(adev,
301 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
304 amdgpu_program_register_sequence(adev,
305 stoney_mgcg_cgcg_init,
306 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
313 mutex_unlock(&adev->grbm_idx_mutex);
317 * vi_get_xclk - get the xclk
319 * @adev: amdgpu_device pointer
321 * Returns the reference clock used by the gfx engine
324 static u32 vi_get_xclk(struct amdgpu_device *adev)
326 u32 reference_clock = adev->clock.spll.reference_freq;
329 if (adev->flags & AMD_IS_APU)
330 return reference_clock;
332 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2);
333 if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK))
336 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL);
337 if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL, XTALIN_DIVIDE))
338 return reference_clock / 4;
340 return reference_clock;
344 * vi_srbm_select - select specific register instances
346 * @adev: amdgpu_device pointer
347 * @me: selected ME (micro engine)
352 * Switches the currently active registers instances. Some
353 * registers are instanced per VMID, others are instanced per
354 * me/pipe/queue combination.
356 void vi_srbm_select(struct amdgpu_device *adev,
357 u32 me, u32 pipe, u32 queue, u32 vmid)
359 u32 srbm_gfx_cntl = 0;
360 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, PIPEID, pipe);
361 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, MEID, me);
362 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vmid);
363 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, QUEUEID, queue);
364 WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl);
367 static void vi_vga_set_state(struct amdgpu_device *adev, bool state)
372 static bool vi_read_disabled_bios(struct amdgpu_device *adev)
375 u32 d1vga_control = 0;
376 u32 d2vga_control = 0;
377 u32 vga_render_control = 0;
381 bus_cntl = RREG32(mmBUS_CNTL);
382 if (adev->mode_info.num_crtc) {
383 d1vga_control = RREG32(mmD1VGA_CONTROL);
384 d2vga_control = RREG32(mmD2VGA_CONTROL);
385 vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
387 rom_cntl = RREG32_SMC(ixROM_CNTL);
390 WREG32(mmBUS_CNTL, (bus_cntl & ~BUS_CNTL__BIOS_ROM_DIS_MASK));
391 if (adev->mode_info.num_crtc) {
392 /* Disable VGA mode */
393 WREG32(mmD1VGA_CONTROL,
394 (d1vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK |
395 D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK)));
396 WREG32(mmD2VGA_CONTROL,
397 (d2vga_control & ~(D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK |
398 D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK)));
399 WREG32(mmVGA_RENDER_CONTROL,
400 (vga_render_control & ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK));
402 WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK);
404 r = amdgpu_read_bios(adev);
407 WREG32(mmBUS_CNTL, bus_cntl);
408 if (adev->mode_info.num_crtc) {
409 WREG32(mmD1VGA_CONTROL, d1vga_control);
410 WREG32(mmD2VGA_CONTROL, d2vga_control);
411 WREG32(mmVGA_RENDER_CONTROL, vga_render_control);
413 WREG32_SMC(ixROM_CNTL, rom_cntl);
417 static bool vi_read_bios_from_rom(struct amdgpu_device *adev,
418 u8 *bios, u32 length_bytes)
426 if (length_bytes == 0)
428 /* APU vbios image is part of sbios image */
429 if (adev->flags & AMD_IS_APU)
432 dw_ptr = (u32 *)bios;
433 length_dw = ALIGN(length_bytes, 4) / 4;
434 /* take the smc lock since we are using the smc index */
435 spin_lock_irqsave(&adev->smc_idx_lock, flags);
436 /* set rom index to 0 */
437 WREG32(mmSMC_IND_INDEX_0, ixROM_INDEX);
438 WREG32(mmSMC_IND_DATA_0, 0);
439 /* set index to data for continous read */
440 WREG32(mmSMC_IND_INDEX_0, ixROM_DATA);
441 for (i = 0; i < length_dw; i++)
442 dw_ptr[i] = RREG32(mmSMC_IND_DATA_0);
443 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
448 static u32 vi_get_virtual_caps(struct amdgpu_device *adev)
451 u32 reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER);
453 if (REG_GET_FIELD(reg, BIF_IOV_FUNC_IDENTIFIER, IOV_ENABLE))
454 caps |= AMDGPU_VIRT_CAPS_SRIOV_EN;
456 if (REG_GET_FIELD(reg, BIF_IOV_FUNC_IDENTIFIER, FUNC_IDENTIFIER))
457 caps |= AMDGPU_VIRT_CAPS_IS_VF;
462 static const struct amdgpu_allowed_register_entry tonga_allowed_read_registers[] = {
463 {mmGB_MACROTILE_MODE7, true},
466 static const struct amdgpu_allowed_register_entry cz_allowed_read_registers[] = {
467 {mmGB_TILE_MODE7, true},
468 {mmGB_TILE_MODE12, true},
469 {mmGB_TILE_MODE17, true},
470 {mmGB_TILE_MODE23, true},
471 {mmGB_MACROTILE_MODE7, true},
474 static const struct amdgpu_allowed_register_entry vi_allowed_read_registers[] = {
475 {mmGRBM_STATUS, false},
476 {mmGRBM_STATUS2, false},
477 {mmGRBM_STATUS_SE0, false},
478 {mmGRBM_STATUS_SE1, false},
479 {mmGRBM_STATUS_SE2, false},
480 {mmGRBM_STATUS_SE3, false},
481 {mmSRBM_STATUS, false},
482 {mmSRBM_STATUS2, false},
483 {mmSRBM_STATUS3, false},
484 {mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET, false},
485 {mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET, false},
487 {mmCP_STALLED_STAT1, false},
488 {mmCP_STALLED_STAT2, false},
489 {mmCP_STALLED_STAT3, false},
490 {mmCP_CPF_BUSY_STAT, false},
491 {mmCP_CPF_STALLED_STAT1, false},
492 {mmCP_CPF_STATUS, false},
493 {mmCP_CPC_BUSY_STAT, false},
494 {mmCP_CPC_STALLED_STAT1, false},
495 {mmCP_CPC_STATUS, false},
496 {mmGB_ADDR_CONFIG, false},
497 {mmMC_ARB_RAMCFG, false},
498 {mmGB_TILE_MODE0, false},
499 {mmGB_TILE_MODE1, false},
500 {mmGB_TILE_MODE2, false},
501 {mmGB_TILE_MODE3, false},
502 {mmGB_TILE_MODE4, false},
503 {mmGB_TILE_MODE5, false},
504 {mmGB_TILE_MODE6, false},
505 {mmGB_TILE_MODE7, false},
506 {mmGB_TILE_MODE8, false},
507 {mmGB_TILE_MODE9, false},
508 {mmGB_TILE_MODE10, false},
509 {mmGB_TILE_MODE11, false},
510 {mmGB_TILE_MODE12, false},
511 {mmGB_TILE_MODE13, false},
512 {mmGB_TILE_MODE14, false},
513 {mmGB_TILE_MODE15, false},
514 {mmGB_TILE_MODE16, false},
515 {mmGB_TILE_MODE17, false},
516 {mmGB_TILE_MODE18, false},
517 {mmGB_TILE_MODE19, false},
518 {mmGB_TILE_MODE20, false},
519 {mmGB_TILE_MODE21, false},
520 {mmGB_TILE_MODE22, false},
521 {mmGB_TILE_MODE23, false},
522 {mmGB_TILE_MODE24, false},
523 {mmGB_TILE_MODE25, false},
524 {mmGB_TILE_MODE26, false},
525 {mmGB_TILE_MODE27, false},
526 {mmGB_TILE_MODE28, false},
527 {mmGB_TILE_MODE29, false},
528 {mmGB_TILE_MODE30, false},
529 {mmGB_TILE_MODE31, false},
530 {mmGB_MACROTILE_MODE0, false},
531 {mmGB_MACROTILE_MODE1, false},
532 {mmGB_MACROTILE_MODE2, false},
533 {mmGB_MACROTILE_MODE3, false},
534 {mmGB_MACROTILE_MODE4, false},
535 {mmGB_MACROTILE_MODE5, false},
536 {mmGB_MACROTILE_MODE6, false},
537 {mmGB_MACROTILE_MODE7, false},
538 {mmGB_MACROTILE_MODE8, false},
539 {mmGB_MACROTILE_MODE9, false},
540 {mmGB_MACROTILE_MODE10, false},
541 {mmGB_MACROTILE_MODE11, false},
542 {mmGB_MACROTILE_MODE12, false},
543 {mmGB_MACROTILE_MODE13, false},
544 {mmGB_MACROTILE_MODE14, false},
545 {mmGB_MACROTILE_MODE15, false},
546 {mmCC_RB_BACKEND_DISABLE, false, true},
547 {mmGC_USER_RB_BACKEND_DISABLE, false, true},
548 {mmGB_BACKEND_MAP, false, false},
549 {mmPA_SC_RASTER_CONFIG, false, true},
550 {mmPA_SC_RASTER_CONFIG_1, false, true},
553 static uint32_t vi_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
554 u32 sh_num, u32 reg_offset)
558 mutex_lock(&adev->grbm_idx_mutex);
559 if (se_num != 0xffffffff || sh_num != 0xffffffff)
560 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
562 val = RREG32(reg_offset);
564 if (se_num != 0xffffffff || sh_num != 0xffffffff)
565 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
566 mutex_unlock(&adev->grbm_idx_mutex);
570 static int vi_read_register(struct amdgpu_device *adev, u32 se_num,
571 u32 sh_num, u32 reg_offset, u32 *value)
573 const struct amdgpu_allowed_register_entry *asic_register_table = NULL;
574 const struct amdgpu_allowed_register_entry *asic_register_entry;
578 switch (adev->asic_type) {
580 asic_register_table = tonga_allowed_read_registers;
581 size = ARRAY_SIZE(tonga_allowed_read_registers);
589 asic_register_table = cz_allowed_read_registers;
590 size = ARRAY_SIZE(cz_allowed_read_registers);
596 if (asic_register_table) {
597 for (i = 0; i < size; i++) {
598 asic_register_entry = asic_register_table + i;
599 if (reg_offset != asic_register_entry->reg_offset)
601 if (!asic_register_entry->untouched)
602 *value = asic_register_entry->grbm_indexed ?
603 vi_read_indexed_register(adev, se_num,
604 sh_num, reg_offset) :
610 for (i = 0; i < ARRAY_SIZE(vi_allowed_read_registers); i++) {
611 if (reg_offset != vi_allowed_read_registers[i].reg_offset)
614 if (!vi_allowed_read_registers[i].untouched)
615 *value = vi_allowed_read_registers[i].grbm_indexed ?
616 vi_read_indexed_register(adev, se_num,
617 sh_num, reg_offset) :
624 static int vi_gpu_pci_config_reset(struct amdgpu_device *adev)
628 dev_info(adev->dev, "GPU pci config reset\n");
631 pci_clear_master(adev->pdev);
633 amdgpu_pci_config_reset(adev);
637 /* wait for asic to come out of reset */
638 for (i = 0; i < adev->usec_timeout; i++) {
639 if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) {
641 pci_set_master(adev->pdev);
649 static void vi_set_bios_scratch_engine_hung(struct amdgpu_device *adev, bool hung)
651 u32 tmp = RREG32(mmBIOS_SCRATCH_3);
654 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
656 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
658 WREG32(mmBIOS_SCRATCH_3, tmp);
662 * vi_asic_reset - soft reset GPU
664 * @adev: amdgpu_device pointer
666 * Look up which blocks are hung and attempt
668 * Returns 0 for success.
670 static int vi_asic_reset(struct amdgpu_device *adev)
674 vi_set_bios_scratch_engine_hung(adev, true);
676 r = vi_gpu_pci_config_reset(adev);
678 vi_set_bios_scratch_engine_hung(adev, false);
683 static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
684 u32 cntl_reg, u32 status_reg)
687 struct atom_clock_dividers dividers;
690 r = amdgpu_atombios_get_clock_dividers(adev,
691 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
692 clock, false, ÷rs);
696 tmp = RREG32_SMC(cntl_reg);
697 tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK |
698 CG_DCLK_CNTL__DCLK_DIVIDER_MASK);
699 tmp |= dividers.post_divider;
700 WREG32_SMC(cntl_reg, tmp);
702 for (i = 0; i < 100; i++) {
703 if (RREG32_SMC(status_reg) & CG_DCLK_STATUS__DCLK_STATUS_MASK)
713 static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
717 r = vi_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
721 r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
726 static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
733 static void vi_pcie_gen3_enable(struct amdgpu_device *adev)
735 if (pci_is_root_bus(adev->pdev->bus))
738 if (amdgpu_pcie_gen2 == 0)
741 if (adev->flags & AMD_IS_APU)
744 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
745 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
751 static void vi_program_aspm(struct amdgpu_device *adev)
754 if (amdgpu_aspm == 0)
760 static void vi_enable_doorbell_aperture(struct amdgpu_device *adev,
765 /* not necessary on CZ */
766 if (adev->flags & AMD_IS_APU)
769 tmp = RREG32(mmBIF_DOORBELL_APER_EN);
771 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 1);
773 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 0);
775 WREG32(mmBIF_DOORBELL_APER_EN, tmp);
778 /* topaz has no DCE, UVD, VCE */
779 static const struct amdgpu_ip_block_version topaz_ip_blocks[] =
783 .type = AMD_IP_BLOCK_TYPE_COMMON,
787 .funcs = &vi_common_ip_funcs,
790 .type = AMD_IP_BLOCK_TYPE_GMC,
794 .funcs = &gmc_v7_0_ip_funcs,
797 .type = AMD_IP_BLOCK_TYPE_IH,
801 .funcs = &iceland_ih_ip_funcs,
804 .type = AMD_IP_BLOCK_TYPE_SMC,
808 .funcs = &amdgpu_pp_ip_funcs,
811 .type = AMD_IP_BLOCK_TYPE_GFX,
815 .funcs = &gfx_v8_0_ip_funcs,
818 .type = AMD_IP_BLOCK_TYPE_SDMA,
822 .funcs = &sdma_v2_4_ip_funcs,
826 static const struct amdgpu_ip_block_version tonga_ip_blocks[] =
830 .type = AMD_IP_BLOCK_TYPE_COMMON,
834 .funcs = &vi_common_ip_funcs,
837 .type = AMD_IP_BLOCK_TYPE_GMC,
841 .funcs = &gmc_v8_0_ip_funcs,
844 .type = AMD_IP_BLOCK_TYPE_IH,
848 .funcs = &tonga_ih_ip_funcs,
851 .type = AMD_IP_BLOCK_TYPE_SMC,
855 .funcs = &amdgpu_pp_ip_funcs,
858 .type = AMD_IP_BLOCK_TYPE_DCE,
862 .funcs = &dce_v10_0_ip_funcs,
865 .type = AMD_IP_BLOCK_TYPE_GFX,
869 .funcs = &gfx_v8_0_ip_funcs,
872 .type = AMD_IP_BLOCK_TYPE_SDMA,
876 .funcs = &sdma_v3_0_ip_funcs,
879 .type = AMD_IP_BLOCK_TYPE_UVD,
883 .funcs = &uvd_v5_0_ip_funcs,
886 .type = AMD_IP_BLOCK_TYPE_VCE,
890 .funcs = &vce_v3_0_ip_funcs,
894 static const struct amdgpu_ip_block_version tonga_ip_blocks_vd[] =
898 .type = AMD_IP_BLOCK_TYPE_COMMON,
902 .funcs = &vi_common_ip_funcs,
905 .type = AMD_IP_BLOCK_TYPE_GMC,
909 .funcs = &gmc_v8_0_ip_funcs,
912 .type = AMD_IP_BLOCK_TYPE_IH,
916 .funcs = &tonga_ih_ip_funcs,
919 .type = AMD_IP_BLOCK_TYPE_SMC,
923 .funcs = &amdgpu_pp_ip_funcs,
926 .type = AMD_IP_BLOCK_TYPE_DCE,
930 .funcs = &dce_virtual_ip_funcs,
933 .type = AMD_IP_BLOCK_TYPE_GFX,
937 .funcs = &gfx_v8_0_ip_funcs,
940 .type = AMD_IP_BLOCK_TYPE_SDMA,
944 .funcs = &sdma_v3_0_ip_funcs,
947 .type = AMD_IP_BLOCK_TYPE_UVD,
951 .funcs = &uvd_v5_0_ip_funcs,
954 .type = AMD_IP_BLOCK_TYPE_VCE,
958 .funcs = &vce_v3_0_ip_funcs,
962 static const struct amdgpu_ip_block_version fiji_ip_blocks[] =
966 .type = AMD_IP_BLOCK_TYPE_COMMON,
970 .funcs = &vi_common_ip_funcs,
973 .type = AMD_IP_BLOCK_TYPE_GMC,
977 .funcs = &gmc_v8_0_ip_funcs,
980 .type = AMD_IP_BLOCK_TYPE_IH,
984 .funcs = &tonga_ih_ip_funcs,
987 .type = AMD_IP_BLOCK_TYPE_SMC,
991 .funcs = &amdgpu_pp_ip_funcs,
994 .type = AMD_IP_BLOCK_TYPE_DCE,
998 .funcs = &dce_v10_0_ip_funcs,
1001 .type = AMD_IP_BLOCK_TYPE_GFX,
1005 .funcs = &gfx_v8_0_ip_funcs,
1008 .type = AMD_IP_BLOCK_TYPE_SDMA,
1012 .funcs = &sdma_v3_0_ip_funcs,
1015 .type = AMD_IP_BLOCK_TYPE_UVD,
1019 .funcs = &uvd_v6_0_ip_funcs,
1022 .type = AMD_IP_BLOCK_TYPE_VCE,
1026 .funcs = &vce_v3_0_ip_funcs,
1030 static const struct amdgpu_ip_block_version fiji_ip_blocks_vd[] =
1032 /* ORDER MATTERS! */
1034 .type = AMD_IP_BLOCK_TYPE_COMMON,
1038 .funcs = &vi_common_ip_funcs,
1041 .type = AMD_IP_BLOCK_TYPE_GMC,
1045 .funcs = &gmc_v8_0_ip_funcs,
1048 .type = AMD_IP_BLOCK_TYPE_IH,
1052 .funcs = &tonga_ih_ip_funcs,
1055 .type = AMD_IP_BLOCK_TYPE_SMC,
1059 .funcs = &amdgpu_pp_ip_funcs,
1062 .type = AMD_IP_BLOCK_TYPE_DCE,
1066 .funcs = &dce_virtual_ip_funcs,
1069 .type = AMD_IP_BLOCK_TYPE_GFX,
1073 .funcs = &gfx_v8_0_ip_funcs,
1076 .type = AMD_IP_BLOCK_TYPE_SDMA,
1080 .funcs = &sdma_v3_0_ip_funcs,
1083 .type = AMD_IP_BLOCK_TYPE_UVD,
1087 .funcs = &uvd_v6_0_ip_funcs,
1090 .type = AMD_IP_BLOCK_TYPE_VCE,
1094 .funcs = &vce_v3_0_ip_funcs,
1098 static const struct amdgpu_ip_block_version polaris11_ip_blocks[] =
1100 /* ORDER MATTERS! */
1102 .type = AMD_IP_BLOCK_TYPE_COMMON,
1106 .funcs = &vi_common_ip_funcs,
1109 .type = AMD_IP_BLOCK_TYPE_GMC,
1113 .funcs = &gmc_v8_0_ip_funcs,
1116 .type = AMD_IP_BLOCK_TYPE_IH,
1120 .funcs = &tonga_ih_ip_funcs,
1123 .type = AMD_IP_BLOCK_TYPE_SMC,
1127 .funcs = &amdgpu_pp_ip_funcs,
1130 .type = AMD_IP_BLOCK_TYPE_DCE,
1134 .funcs = &dce_v11_0_ip_funcs,
1137 .type = AMD_IP_BLOCK_TYPE_GFX,
1141 .funcs = &gfx_v8_0_ip_funcs,
1144 .type = AMD_IP_BLOCK_TYPE_SDMA,
1148 .funcs = &sdma_v3_0_ip_funcs,
1151 .type = AMD_IP_BLOCK_TYPE_UVD,
1155 .funcs = &uvd_v6_0_ip_funcs,
1158 .type = AMD_IP_BLOCK_TYPE_VCE,
1162 .funcs = &vce_v3_0_ip_funcs,
1166 static const struct amdgpu_ip_block_version polaris11_ip_blocks_vd[] =
1168 /* ORDER MATTERS! */
1170 .type = AMD_IP_BLOCK_TYPE_COMMON,
1174 .funcs = &vi_common_ip_funcs,
1177 .type = AMD_IP_BLOCK_TYPE_GMC,
1181 .funcs = &gmc_v8_0_ip_funcs,
1184 .type = AMD_IP_BLOCK_TYPE_IH,
1188 .funcs = &tonga_ih_ip_funcs,
1191 .type = AMD_IP_BLOCK_TYPE_SMC,
1195 .funcs = &amdgpu_pp_ip_funcs,
1198 .type = AMD_IP_BLOCK_TYPE_DCE,
1202 .funcs = &dce_virtual_ip_funcs,
1205 .type = AMD_IP_BLOCK_TYPE_GFX,
1209 .funcs = &gfx_v8_0_ip_funcs,
1212 .type = AMD_IP_BLOCK_TYPE_SDMA,
1216 .funcs = &sdma_v3_0_ip_funcs,
1219 .type = AMD_IP_BLOCK_TYPE_UVD,
1223 .funcs = &uvd_v6_0_ip_funcs,
1226 .type = AMD_IP_BLOCK_TYPE_VCE,
1230 .funcs = &vce_v3_0_ip_funcs,
1234 static const struct amdgpu_ip_block_version cz_ip_blocks[] =
1236 /* ORDER MATTERS! */
1238 .type = AMD_IP_BLOCK_TYPE_COMMON,
1242 .funcs = &vi_common_ip_funcs,
1245 .type = AMD_IP_BLOCK_TYPE_GMC,
1249 .funcs = &gmc_v8_0_ip_funcs,
1252 .type = AMD_IP_BLOCK_TYPE_IH,
1256 .funcs = &cz_ih_ip_funcs,
1259 .type = AMD_IP_BLOCK_TYPE_SMC,
1263 .funcs = &amdgpu_pp_ip_funcs
1266 .type = AMD_IP_BLOCK_TYPE_DCE,
1270 .funcs = &dce_v11_0_ip_funcs,
1273 .type = AMD_IP_BLOCK_TYPE_GFX,
1277 .funcs = &gfx_v8_0_ip_funcs,
1280 .type = AMD_IP_BLOCK_TYPE_SDMA,
1284 .funcs = &sdma_v3_0_ip_funcs,
1287 .type = AMD_IP_BLOCK_TYPE_UVD,
1291 .funcs = &uvd_v6_0_ip_funcs,
1294 .type = AMD_IP_BLOCK_TYPE_VCE,
1298 .funcs = &vce_v3_0_ip_funcs,
1300 #if defined(CONFIG_DRM_AMD_ACP)
1302 .type = AMD_IP_BLOCK_TYPE_ACP,
1306 .funcs = &acp_ip_funcs,
1311 static const struct amdgpu_ip_block_version cz_ip_blocks_vd[] =
1313 /* ORDER MATTERS! */
1315 .type = AMD_IP_BLOCK_TYPE_COMMON,
1319 .funcs = &vi_common_ip_funcs,
1322 .type = AMD_IP_BLOCK_TYPE_GMC,
1326 .funcs = &gmc_v8_0_ip_funcs,
1329 .type = AMD_IP_BLOCK_TYPE_IH,
1333 .funcs = &cz_ih_ip_funcs,
1336 .type = AMD_IP_BLOCK_TYPE_SMC,
1340 .funcs = &amdgpu_pp_ip_funcs
1343 .type = AMD_IP_BLOCK_TYPE_DCE,
1347 .funcs = &dce_virtual_ip_funcs,
1350 .type = AMD_IP_BLOCK_TYPE_GFX,
1354 .funcs = &gfx_v8_0_ip_funcs,
1357 .type = AMD_IP_BLOCK_TYPE_SDMA,
1361 .funcs = &sdma_v3_0_ip_funcs,
1364 .type = AMD_IP_BLOCK_TYPE_UVD,
1368 .funcs = &uvd_v6_0_ip_funcs,
1371 .type = AMD_IP_BLOCK_TYPE_VCE,
1375 .funcs = &vce_v3_0_ip_funcs,
1377 #if defined(CONFIG_DRM_AMD_ACP)
1379 .type = AMD_IP_BLOCK_TYPE_ACP,
1383 .funcs = &acp_ip_funcs,
1388 int vi_set_ip_blocks(struct amdgpu_device *adev)
1390 if (amdgpu_virtual_display) {
1391 switch (adev->asic_type) {
1393 adev->ip_blocks = topaz_ip_blocks;
1394 adev->num_ip_blocks = ARRAY_SIZE(topaz_ip_blocks);
1397 adev->ip_blocks = fiji_ip_blocks_vd;
1398 adev->num_ip_blocks = ARRAY_SIZE(fiji_ip_blocks_vd);
1401 adev->ip_blocks = tonga_ip_blocks_vd;
1402 adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks_vd);
1404 case CHIP_POLARIS11:
1405 case CHIP_POLARIS10:
1406 adev->ip_blocks = polaris11_ip_blocks_vd;
1407 adev->num_ip_blocks = ARRAY_SIZE(polaris11_ip_blocks_vd);
1412 adev->ip_blocks = cz_ip_blocks_vd;
1413 adev->num_ip_blocks = ARRAY_SIZE(cz_ip_blocks_vd);
1416 /* FIXME: not supported yet */
1420 switch (adev->asic_type) {
1422 adev->ip_blocks = topaz_ip_blocks;
1423 adev->num_ip_blocks = ARRAY_SIZE(topaz_ip_blocks);
1426 adev->ip_blocks = fiji_ip_blocks;
1427 adev->num_ip_blocks = ARRAY_SIZE(fiji_ip_blocks);
1430 adev->ip_blocks = tonga_ip_blocks;
1431 adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks);
1433 case CHIP_POLARIS11:
1434 case CHIP_POLARIS10:
1435 adev->ip_blocks = polaris11_ip_blocks;
1436 adev->num_ip_blocks = ARRAY_SIZE(polaris11_ip_blocks);
1440 adev->ip_blocks = cz_ip_blocks;
1441 adev->num_ip_blocks = ARRAY_SIZE(cz_ip_blocks);
1444 /* FIXME: not supported yet */
1452 #define ATI_REV_ID_FUSE_MACRO__ADDRESS 0xC0014044
1453 #define ATI_REV_ID_FUSE_MACRO__SHIFT 9
1454 #define ATI_REV_ID_FUSE_MACRO__MASK 0x00001E00
1456 static uint32_t vi_get_rev_id(struct amdgpu_device *adev)
1458 if (adev->flags & AMD_IS_APU)
1459 return (RREG32_SMC(ATI_REV_ID_FUSE_MACRO__ADDRESS) & ATI_REV_ID_FUSE_MACRO__MASK)
1460 >> ATI_REV_ID_FUSE_MACRO__SHIFT;
1462 return (RREG32(mmPCIE_EFUSE4) & PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK)
1463 >> PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT;
1466 static const struct amdgpu_asic_funcs vi_asic_funcs =
1468 .read_disabled_bios = &vi_read_disabled_bios,
1469 .read_bios_from_rom = &vi_read_bios_from_rom,
1470 .read_register = &vi_read_register,
1471 .reset = &vi_asic_reset,
1472 .set_vga_state = &vi_vga_set_state,
1473 .get_xclk = &vi_get_xclk,
1474 .set_uvd_clocks = &vi_set_uvd_clocks,
1475 .set_vce_clocks = &vi_set_vce_clocks,
1476 .get_virtual_caps = &vi_get_virtual_caps,
1479 static int vi_common_early_init(void *handle)
1481 bool smc_enabled = false;
1482 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1484 if (adev->flags & AMD_IS_APU) {
1485 adev->smc_rreg = &cz_smc_rreg;
1486 adev->smc_wreg = &cz_smc_wreg;
1488 adev->smc_rreg = &vi_smc_rreg;
1489 adev->smc_wreg = &vi_smc_wreg;
1491 adev->pcie_rreg = &vi_pcie_rreg;
1492 adev->pcie_wreg = &vi_pcie_wreg;
1493 adev->uvd_ctx_rreg = &vi_uvd_ctx_rreg;
1494 adev->uvd_ctx_wreg = &vi_uvd_ctx_wreg;
1495 adev->didt_rreg = &vi_didt_rreg;
1496 adev->didt_wreg = &vi_didt_wreg;
1497 adev->gc_cac_rreg = &vi_gc_cac_rreg;
1498 adev->gc_cac_wreg = &vi_gc_cac_wreg;
1500 adev->asic_funcs = &vi_asic_funcs;
1502 if (amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC) &&
1503 (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_SMC)))
1506 adev->rev_id = vi_get_rev_id(adev);
1507 adev->external_rev_id = 0xFF;
1508 switch (adev->asic_type) {
1512 adev->external_rev_id = 0x1;
1515 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1516 AMD_CG_SUPPORT_GFX_MGLS |
1517 AMD_CG_SUPPORT_GFX_RLC_LS |
1518 AMD_CG_SUPPORT_GFX_CP_LS |
1519 AMD_CG_SUPPORT_GFX_CGTS |
1520 AMD_CG_SUPPORT_GFX_CGTS_LS |
1521 AMD_CG_SUPPORT_GFX_CGCG |
1522 AMD_CG_SUPPORT_GFX_CGLS |
1523 AMD_CG_SUPPORT_SDMA_MGCG |
1524 AMD_CG_SUPPORT_SDMA_LS |
1525 AMD_CG_SUPPORT_BIF_LS |
1526 AMD_CG_SUPPORT_HDP_MGCG |
1527 AMD_CG_SUPPORT_HDP_LS |
1528 AMD_CG_SUPPORT_ROM_MGCG |
1529 AMD_CG_SUPPORT_MC_MGCG |
1530 AMD_CG_SUPPORT_MC_LS;
1532 adev->external_rev_id = adev->rev_id + 0x3c;
1535 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG;
1537 adev->external_rev_id = adev->rev_id + 0x14;
1539 case CHIP_POLARIS11:
1542 adev->external_rev_id = adev->rev_id + 0x5A;
1544 case CHIP_POLARIS10:
1547 adev->external_rev_id = adev->rev_id + 0x50;
1550 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
1551 AMD_CG_SUPPORT_GFX_MGCG |
1552 AMD_CG_SUPPORT_GFX_MGLS |
1553 AMD_CG_SUPPORT_GFX_RLC_LS |
1554 AMD_CG_SUPPORT_GFX_CP_LS |
1555 AMD_CG_SUPPORT_GFX_CGTS |
1556 AMD_CG_SUPPORT_GFX_MGLS |
1557 AMD_CG_SUPPORT_GFX_CGTS_LS |
1558 AMD_CG_SUPPORT_GFX_CGCG |
1559 AMD_CG_SUPPORT_GFX_CGLS |
1560 AMD_CG_SUPPORT_BIF_LS |
1561 AMD_CG_SUPPORT_HDP_MGCG |
1562 AMD_CG_SUPPORT_HDP_LS |
1563 AMD_CG_SUPPORT_SDMA_MGCG |
1564 AMD_CG_SUPPORT_SDMA_LS |
1565 AMD_CG_SUPPORT_VCE_MGCG;
1566 /* rev0 hardware requires workarounds to support PG */
1568 if (adev->rev_id != 0x00) {
1569 adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
1570 AMD_PG_SUPPORT_GFX_SMG |
1571 AMD_PG_SUPPORT_GFX_PIPELINE |
1572 AMD_PG_SUPPORT_UVD |
1575 adev->external_rev_id = adev->rev_id + 0x1;
1578 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
1579 AMD_CG_SUPPORT_GFX_MGCG |
1580 AMD_CG_SUPPORT_GFX_MGLS |
1581 AMD_CG_SUPPORT_GFX_RLC_LS |
1582 AMD_CG_SUPPORT_GFX_CP_LS |
1583 AMD_CG_SUPPORT_GFX_CGTS |
1584 AMD_CG_SUPPORT_GFX_MGLS |
1585 AMD_CG_SUPPORT_GFX_CGTS_LS |
1586 AMD_CG_SUPPORT_GFX_CGCG |
1587 AMD_CG_SUPPORT_GFX_CGLS |
1588 AMD_CG_SUPPORT_BIF_LS |
1589 AMD_CG_SUPPORT_HDP_MGCG |
1590 AMD_CG_SUPPORT_HDP_LS |
1591 AMD_CG_SUPPORT_SDMA_MGCG |
1592 AMD_CG_SUPPORT_SDMA_LS |
1593 AMD_CG_SUPPORT_VCE_MGCG;
1594 adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
1595 AMD_PG_SUPPORT_GFX_SMG |
1596 AMD_PG_SUPPORT_GFX_PIPELINE |
1597 AMD_PG_SUPPORT_UVD |
1599 adev->external_rev_id = adev->rev_id + 0x1;
1602 /* FIXME: not supported yet */
1606 if (amdgpu_smc_load_fw && smc_enabled)
1607 adev->firmware.smu_load = true;
1609 amdgpu_get_pcie_info(adev);
1614 static int vi_common_sw_init(void *handle)
1619 static int vi_common_sw_fini(void *handle)
1624 static int vi_common_hw_init(void *handle)
1626 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1628 /* move the golden regs per IP block */
1629 vi_init_golden_registers(adev);
1630 /* enable pcie gen2/3 link */
1631 vi_pcie_gen3_enable(adev);
1633 vi_program_aspm(adev);
1634 /* enable the doorbell aperture */
1635 vi_enable_doorbell_aperture(adev, true);
1640 static int vi_common_hw_fini(void *handle)
1642 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1644 /* enable the doorbell aperture */
1645 vi_enable_doorbell_aperture(adev, false);
1650 static int vi_common_suspend(void *handle)
1652 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1654 return vi_common_hw_fini(adev);
1657 static int vi_common_resume(void *handle)
1659 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1661 return vi_common_hw_init(adev);
1664 static bool vi_common_is_idle(void *handle)
1669 static int vi_common_wait_for_idle(void *handle)
1674 static int vi_common_soft_reset(void *handle)
1679 static void vi_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev,
1682 uint32_t temp, data;
1684 temp = data = RREG32_PCIE(ixPCIE_CNTL2);
1686 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
1687 data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
1688 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
1689 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK;
1691 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
1692 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
1693 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
1696 WREG32_PCIE(ixPCIE_CNTL2, data);
1699 static void vi_update_hdp_medium_grain_clock_gating(struct amdgpu_device *adev,
1702 uint32_t temp, data;
1704 temp = data = RREG32(mmHDP_HOST_PATH_CNTL);
1706 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
1707 data &= ~HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK;
1709 data |= HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK;
1712 WREG32(mmHDP_HOST_PATH_CNTL, data);
1715 static void vi_update_hdp_light_sleep(struct amdgpu_device *adev,
1718 uint32_t temp, data;
1720 temp = data = RREG32(mmHDP_MEM_POWER_LS);
1722 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1723 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1725 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1728 WREG32(mmHDP_MEM_POWER_LS, data);
1731 static void vi_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
1734 uint32_t temp, data;
1736 temp = data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0);
1738 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
1739 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1740 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
1742 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1743 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
1746 WREG32_SMC(ixCGTT_ROM_CLK_CTRL0, data);
1749 static int vi_common_set_clockgating_state(void *handle,
1750 enum amd_clockgating_state state)
1752 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1754 switch (adev->asic_type) {
1756 vi_update_bif_medium_grain_light_sleep(adev,
1757 state == AMD_CG_STATE_GATE ? true : false);
1758 vi_update_hdp_medium_grain_clock_gating(adev,
1759 state == AMD_CG_STATE_GATE ? true : false);
1760 vi_update_hdp_light_sleep(adev,
1761 state == AMD_CG_STATE_GATE ? true : false);
1762 vi_update_rom_medium_grain_clock_gating(adev,
1763 state == AMD_CG_STATE_GATE ? true : false);
1767 vi_update_bif_medium_grain_light_sleep(adev,
1768 state == AMD_CG_STATE_GATE ? true : false);
1769 vi_update_hdp_medium_grain_clock_gating(adev,
1770 state == AMD_CG_STATE_GATE ? true : false);
1771 vi_update_hdp_light_sleep(adev,
1772 state == AMD_CG_STATE_GATE ? true : false);
1780 static int vi_common_set_powergating_state(void *handle,
1781 enum amd_powergating_state state)
1786 const struct amd_ip_funcs vi_common_ip_funcs = {
1787 .name = "vi_common",
1788 .early_init = vi_common_early_init,
1790 .sw_init = vi_common_sw_init,
1791 .sw_fini = vi_common_sw_fini,
1792 .hw_init = vi_common_hw_init,
1793 .hw_fini = vi_common_hw_fini,
1794 .suspend = vi_common_suspend,
1795 .resume = vi_common_resume,
1796 .is_idle = vi_common_is_idle,
1797 .wait_for_idle = vi_common_wait_for_idle,
1798 .soft_reset = vi_common_soft_reset,
1799 .set_clockgating_state = vi_common_set_clockgating_state,
1800 .set_powergating_state = vi_common_set_powergating_state,