drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/types.h>
  24 #include <linux/kernel.h>
  25 #include <linux/slab.h>
  26 #include "atom-types.h"
  27 #include "atombios.h"
  28 #include "processpptables.h"
  29 #include "pp_debug.h"
  30 #include "cgs_common.h"
  31 #include "smu/smu_8_0_d.h"
  32 #include "smu8_fusion.h"
  33 #include "smu/smu_8_0_sh_mask.h"
  34 #include "smumgr.h"
  35 #include "hwmgr.h"
  36 #include "hardwaremanager.h"
  37 #include "cz_ppsmc.h"
  38 #include "cz_hwmgr.h"
  39 #include "power_state.h"
  40 #include "cz_clockpowergating.h"
  41 #include "pp_debug.h"
  42
  43 #define ixSMUSVI_NB_CURRENTVID 0xD8230044
  44 #define CURRENT_NB_VID_MASK 0xff000000
  45 #define CURRENT_NB_VID__SHIFT 24
  46 #define ixSMUSVI_GFX_CURRENTVID  0xD8230048
  47 #define CURRENT_GFX_VID_MASK 0xff000000
  48 #define CURRENT_GFX_VID__SHIFT 24
  49
  50 static const unsigned long PhwCz_Magic = (unsigned long) PHM_Cz_Magic;
  51
  52 static struct cz_power_state *cast_PhwCzPowerState(struct pp_hw_power_state *hw_ps)
  53 {
  54         if (PhwCz_Magic != hw_ps->magic)
  55                 return NULL;
  56
  57         return (struct cz_power_state *)hw_ps;
  58 }
  59
  60 static const struct cz_power_state *cast_const_PhwCzPowerState(
  61                                 const struct pp_hw_power_state *hw_ps)
  62 {
  63         if (PhwCz_Magic != hw_ps->magic)
  64                 return NULL;
  65
  66         return (struct cz_power_state *)hw_ps;
  67 }
  68
  69 uint32_t cz_get_eclk_level(struct pp_hwmgr *hwmgr,
  70                                         uint32_t clock, uint32_t msg)
  71 {
  72         int i = 0;
  73         struct phm_vce_clock_voltage_dependency_table *ptable =
  74                 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
  75
  76         switch (msg) {
  77         case PPSMC_MSG_SetEclkSoftMin:
  78         case PPSMC_MSG_SetEclkHardMin:
  79                 for (i = 0; i < (int)ptable->count; i++) {
  80                         if (clock <= ptable->entries[i].ecclk)
  81                                 break;
  82                 }
  83                 break;
  84
  85         case PPSMC_MSG_SetEclkSoftMax:
  86         case PPSMC_MSG_SetEclkHardMax:
  87                 for (i = ptable->count - 1; i >= 0; i--) {
  88                         if (clock >= ptable->entries[i].ecclk)
  89                                 break;
  90                 }
  91                 break;
  92
  93         default:
  94                 break;
  95         }
  96
  97         return i;
  98 }
  99
 100 static uint32_t cz_get_sclk_level(struct pp_hwmgr *hwmgr,
 101                                 uint32_t clock, uint32_t msg)
 102 {
 103         int i = 0;
 104         struct phm_clock_voltage_dependency_table *table =
 105                                 hwmgr->dyn_state.vddc_dependency_on_sclk;
 106
 107         switch (msg) {
 108         case PPSMC_MSG_SetSclkSoftMin:
 109         case PPSMC_MSG_SetSclkHardMin:
 110                 for (i = 0; i < (int)table->count; i++) {
 111                         if (clock <= table->entries[i].clk)
 112                                 break;
 113                 }
 114                 break;
 115
 116         case PPSMC_MSG_SetSclkSoftMax:
 117         case PPSMC_MSG_SetSclkHardMax:
 118                 for (i = table->count - 1; i >= 0; i--) {
 119                         if (clock >= table->entries[i].clk)
 120                                 break;
 121                 }
 122                 break;
 123
 124         default:
 125                 break;
 126         }
 127         return i;
 128 }
 129
 130 static uint32_t cz_get_uvd_level(struct pp_hwmgr *hwmgr,
 131                                         uint32_t clock, uint32_t msg)
 132 {
 133         int i = 0;
 134         struct phm_uvd_clock_voltage_dependency_table *ptable =
 135                 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
 136
 137         switch (msg) {
 138         case PPSMC_MSG_SetUvdSoftMin:
 139         case PPSMC_MSG_SetUvdHardMin:
 140                 for (i = 0; i < (int)ptable->count; i++) {
 141                         if (clock <= ptable->entries[i].vclk)
 142                                 break;
 143                 }
 144                 break;
 145
 146         case PPSMC_MSG_SetUvdSoftMax:
 147         case PPSMC_MSG_SetUvdHardMax:
 148                 for (i = ptable->count - 1; i >= 0; i--) {
 149                         if (clock >= ptable->entries[i].vclk)
 150                                 break;
 151                 }
 152                 break;
 153
 154         default:
 155                 break;
 156         }
 157
 158         return i;
 159 }
 160
 161 static uint32_t cz_get_max_sclk_level(struct pp_hwmgr *hwmgr)
 162 {
 163         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 164
 165         if (cz_hwmgr->max_sclk_level == 0) {
 166                 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxSclkLevel);
 167                 cz_hwmgr->max_sclk_level = smum_get_argument(hwmgr->smumgr) + 1;
 168         }
 169
 170         return cz_hwmgr->max_sclk_level;
 171 }
 172
 173 static int cz_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
 174 {
 175         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 176         uint32_t i;
 177         struct cgs_system_info sys_info = {0};
 178         int result;
 179
 180         cz_hwmgr->gfx_ramp_step = 256*25/100;
 181
 182         cz_hwmgr->gfx_ramp_delay = 1; /* by default, we delay 1us */
 183
 184         for (i = 0; i < CZ_MAX_HARDWARE_POWERLEVELS; i++)
 185                 cz_hwmgr->activity_target[i] = CZ_AT_DFLT;
 186
 187         cz_hwmgr->mgcg_cgtt_local0 = 0x00000000;
 188         cz_hwmgr->mgcg_cgtt_local1 = 0x00000000;
 189
 190         cz_hwmgr->clock_slow_down_freq = 25000;
 191
 192         cz_hwmgr->skip_clock_slow_down = 1;
 193
 194         cz_hwmgr->enable_nb_ps_policy = 1; /* disable until UNB is ready, Enabled */
 195
 196         cz_hwmgr->voltage_drop_in_dce_power_gating = 0; /* disable until fully verified */
 197
 198         cz_hwmgr->voting_rights_clients = 0x00C00033;
 199
 200         cz_hwmgr->static_screen_threshold = 8;
 201
 202         cz_hwmgr->ddi_power_gating_disabled = 0;
 203
 204         cz_hwmgr->bapm_enabled = 1;
 205
 206         cz_hwmgr->voltage_drop_threshold = 0;
 207
 208         cz_hwmgr->gfx_power_gating_threshold = 500;
 209
 210         cz_hwmgr->vce_slow_sclk_threshold = 20000;
 211
 212         cz_hwmgr->dce_slow_sclk_threshold = 30000;
 213
 214         cz_hwmgr->disable_driver_thermal_policy = 1;
 215
 216         cz_hwmgr->disable_nb_ps3_in_battery = 0;
 217
 218         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 219                                                         PHM_PlatformCaps_ABM);
 220
 221         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 222                                     PHM_PlatformCaps_NonABMSupportInPPLib);
 223
 224         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 225                                            PHM_PlatformCaps_SclkDeepSleep);
 226
 227         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 228                                         PHM_PlatformCaps_DynamicM3Arbiter);
 229
 230         cz_hwmgr->override_dynamic_mgpg = 1;
 231
 232         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 233                                   PHM_PlatformCaps_DynamicPatchPowerState);
 234
 235         cz_hwmgr->thermal_auto_throttling_treshold = 0;
 236
 237         cz_hwmgr->tdr_clock = 0;
 238
 239         cz_hwmgr->disable_gfx_power_gating_in_uvd = 0;
 240
 241         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 242                                         PHM_PlatformCaps_DynamicUVDState);
 243
 244         cz_hwmgr->cc6_settings.cpu_cc6_disable = false;
 245         cz_hwmgr->cc6_settings.cpu_pstate_disable = false;
 246         cz_hwmgr->cc6_settings.nb_pstate_switch_disable = false;
 247         cz_hwmgr->cc6_settings.cpu_pstate_separation_time = 0;
 248
 249         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 250                                    PHM_PlatformCaps_DisableVoltageIsland);
 251
 252         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 253                       PHM_PlatformCaps_UVDPowerGating);
 254         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 255                       PHM_PlatformCaps_VCEPowerGating);
 256         sys_info.size = sizeof(struct cgs_system_info);
 257         sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS;
 258         result = cgs_query_system_info(hwmgr->device, &sys_info);
 259         if (!result) {
 260                 if (sys_info.value & AMD_PG_SUPPORT_UVD)
 261                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 262                                       PHM_PlatformCaps_UVDPowerGating);
 263                 if (sys_info.value & AMD_PG_SUPPORT_VCE)
 264                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 265                                       PHM_PlatformCaps_VCEPowerGating);
 266         }
 267
 268         return 0;
 269 }
 270
 271 static uint32_t cz_convert_8Bit_index_to_voltage(
 272                         struct pp_hwmgr *hwmgr, uint16_t voltage)
 273 {
 274         return 6200 - (voltage * 25);
 275 }
 276
 277 static int cz_construct_max_power_limits_table(struct pp_hwmgr *hwmgr,
 278                         struct phm_clock_and_voltage_limits *table)
 279 {
 280         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)hwmgr->backend;
 281         struct cz_sys_info *sys_info = &cz_hwmgr->sys_info;
 282         struct phm_clock_voltage_dependency_table *dep_table =
 283                                 hwmgr->dyn_state.vddc_dependency_on_sclk;
 284
 285         if (dep_table->count > 0) {
 286                 table->sclk = dep_table->entries[dep_table->count-1].clk;
 287                 table->vddc = cz_convert_8Bit_index_to_voltage(hwmgr,
 288                    (uint16_t)dep_table->entries[dep_table->count-1].v);
 289         }
 290         table->mclk = sys_info->nbp_memory_clock[0];
 291         return 0;
 292 }
 293
 294 static int cz_init_dynamic_state_adjustment_rule_settings(
 295                         struct pp_hwmgr *hwmgr,
 296                         ATOM_CLK_VOLT_CAPABILITY *disp_voltage_table)
 297 {
 298         uint32_t table_size =
 299                 sizeof(struct phm_clock_voltage_dependency_table) +
 300                 (7 * sizeof(struct phm_clock_voltage_dependency_record));
 301
 302         struct phm_clock_voltage_dependency_table *table_clk_vlt =
 303                                         kzalloc(table_size, GFP_KERNEL);
 304
 305         if (NULL == table_clk_vlt) {
 306                 printk(KERN_ERR "[ powerplay ] Can not allocate memory!\n");
 307                 return -ENOMEM;
 308         }
 309
 310         table_clk_vlt->count = 8;
 311         table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_0;
 312         table_clk_vlt->entries[0].v = 0;
 313         table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_1;
 314         table_clk_vlt->entries[1].v = 1;
 315         table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_2;
 316         table_clk_vlt->entries[2].v = 2;
 317         table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_3;
 318         table_clk_vlt->entries[3].v = 3;
 319         table_clk_vlt->entries[4].clk = PP_DAL_POWERLEVEL_4;
 320         table_clk_vlt->entries[4].v = 4;
 321         table_clk_vlt->entries[5].clk = PP_DAL_POWERLEVEL_5;
 322         table_clk_vlt->entries[5].v = 5;
 323         table_clk_vlt->entries[6].clk = PP_DAL_POWERLEVEL_6;
 324         table_clk_vlt->entries[6].v = 6;
 325         table_clk_vlt->entries[7].clk = PP_DAL_POWERLEVEL_7;
 326         table_clk_vlt->entries[7].v = 7;
 327         hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
 328
 329         return 0;
 330 }
 331
 332 static int cz_get_system_info_data(struct pp_hwmgr *hwmgr)
 333 {
 334         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)hwmgr->backend;
 335         ATOM_INTEGRATED_SYSTEM_INFO_V1_9 *info = NULL;
 336         uint32_t i;
 337         int result = 0;
 338         uint8_t frev, crev;
 339         uint16_t size;
 340
 341         info = (ATOM_INTEGRATED_SYSTEM_INFO_V1_9 *) cgs_atom_get_data_table(
 342                         hwmgr->device,
 343                         GetIndexIntoMasterTable(DATA, IntegratedSystemInfo),
 344                         &size, &frev, &crev);
 345
 346         if (crev != 9) {
 347                 printk(KERN_ERR "[ powerplay ] Unsupported IGP table: %d %d\n", frev, crev);
 348                 return -EINVAL;
 349         }
 350
 351         if (info == NULL) {
 352                 printk(KERN_ERR "[ powerplay ] Could not retrieve the Integrated System Info Table!\n");
 353                 return -EINVAL;
 354         }
 355
 356         cz_hwmgr->sys_info.bootup_uma_clock =
 357                                    le32_to_cpu(info->ulBootUpUMAClock);
 358
 359         cz_hwmgr->sys_info.bootup_engine_clock =
 360                                 le32_to_cpu(info->ulBootUpEngineClock);
 361
 362         cz_hwmgr->sys_info.dentist_vco_freq =
 363                                    le32_to_cpu(info->ulDentistVCOFreq);
 364
 365         cz_hwmgr->sys_info.system_config =
 366                                      le32_to_cpu(info->ulSystemConfig);
 367
 368         cz_hwmgr->sys_info.bootup_nb_voltage_index =
 369                                   le16_to_cpu(info->usBootUpNBVoltage);
 370
 371         cz_hwmgr->sys_info.htc_hyst_lmt =
 372                         (info->ucHtcHystLmt == 0) ? 5 : info->ucHtcHystLmt;
 373
 374         cz_hwmgr->sys_info.htc_tmp_lmt =
 375                         (info->ucHtcTmpLmt == 0) ? 203 : info->ucHtcTmpLmt;
 376
 377         if (cz_hwmgr->sys_info.htc_tmp_lmt <=
 378                         cz_hwmgr->sys_info.htc_hyst_lmt) {
 379                 printk(KERN_ERR "[ powerplay ] The htcTmpLmt should be larger than htcHystLmt.\n");
 380                 return -EINVAL;
 381         }
 382
 383         cz_hwmgr->sys_info.nb_dpm_enable =
 384                                 cz_hwmgr->enable_nb_ps_policy &&
 385                                 (le32_to_cpu(info->ulSystemConfig) >> 3 & 0x1);
 386
 387         for (i = 0; i < CZ_NUM_NBPSTATES; i++) {
 388                 if (i < CZ_NUM_NBPMEMORYCLOCK) {
 389                         cz_hwmgr->sys_info.nbp_memory_clock[i] =
 390                           le32_to_cpu(info->ulNbpStateMemclkFreq[i]);
 391                 }
 392                 cz_hwmgr->sys_info.nbp_n_clock[i] =
 393                             le32_to_cpu(info->ulNbpStateNClkFreq[i]);
 394         }
 395
 396         for (i = 0; i < MAX_DISPLAY_CLOCK_LEVEL; i++) {
 397                 cz_hwmgr->sys_info.display_clock[i] =
 398                                         le32_to_cpu(info->sDispClkVoltageMapping[i].ulMaximumSupportedCLK);
 399         }
 400
 401         /* Here use 4 levels, make sure not exceed */
 402         for (i = 0; i < CZ_NUM_NBPSTATES; i++) {
 403                 cz_hwmgr->sys_info.nbp_voltage_index[i] =
 404                              le16_to_cpu(info->usNBPStateVoltage[i]);
 405         }
 406
 407         if (!cz_hwmgr->sys_info.nb_dpm_enable) {
 408                 for (i = 1; i < CZ_NUM_NBPSTATES; i++) {
 409                         if (i < CZ_NUM_NBPMEMORYCLOCK) {
 410                                 cz_hwmgr->sys_info.nbp_memory_clock[i] =
 411                                     cz_hwmgr->sys_info.nbp_memory_clock[0];
 412                         }
 413                         cz_hwmgr->sys_info.nbp_n_clock[i] =
 414                                     cz_hwmgr->sys_info.nbp_n_clock[0];
 415                         cz_hwmgr->sys_info.nbp_voltage_index[i] =
 416                                     cz_hwmgr->sys_info.nbp_voltage_index[0];
 417                 }
 418         }
 419
 420         if (le32_to_cpu(info->ulGPUCapInfo) &
 421                 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS) {
 422                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 423                                     PHM_PlatformCaps_EnableDFSBypass);
 424         }
 425
 426         cz_hwmgr->sys_info.uma_channel_number = info->ucUMAChannelNumber;
 427
 428         cz_construct_max_power_limits_table (hwmgr,
 429                                     &hwmgr->dyn_state.max_clock_voltage_on_ac);
 430
 431         cz_init_dynamic_state_adjustment_rule_settings(hwmgr,
 432                                     &info->sDISPCLK_Voltage[0]);
 433
 434         return result;
 435 }
 436
 437 static int cz_construct_boot_state(struct pp_hwmgr *hwmgr)
 438 {
 439         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 440
 441         cz_hwmgr->boot_power_level.engineClock =
 442                                 cz_hwmgr->sys_info.bootup_engine_clock;
 443
 444         cz_hwmgr->boot_power_level.vddcIndex =
 445                         (uint8_t)cz_hwmgr->sys_info.bootup_nb_voltage_index;
 446
 447         cz_hwmgr->boot_power_level.dsDividerIndex = 0;
 448
 449         cz_hwmgr->boot_power_level.ssDividerIndex = 0;
 450
 451         cz_hwmgr->boot_power_level.allowGnbSlow = 1;
 452
 453         cz_hwmgr->boot_power_level.forceNBPstate = 0;
 454
 455         cz_hwmgr->boot_power_level.hysteresis_up = 0;
 456
 457         cz_hwmgr->boot_power_level.numSIMDToPowerDown = 0;
 458
 459         cz_hwmgr->boot_power_level.display_wm = 0;
 460
 461         cz_hwmgr->boot_power_level.vce_wm = 0;
 462
 463         return 0;
 464 }
 465
 466 static int cz_tf_reset_active_process_mask(struct pp_hwmgr *hwmgr, void *input,
 467                                         void *output, void *storage, int result)
 468 {
 469         return 0;
 470 }
 471
 472 static int cz_tf_upload_pptable_to_smu(struct pp_hwmgr *hwmgr, void *input,
 473                                        void *output, void *storage, int result)
 474 {
 475         struct SMU8_Fusion_ClkTable *clock_table;
 476         int ret;
 477         uint32_t i;
 478         void *table = NULL;
 479         pp_atomctrl_clock_dividers_kong dividers;
 480
 481         struct phm_clock_voltage_dependency_table *vddc_table =
 482                 hwmgr->dyn_state.vddc_dependency_on_sclk;
 483         struct phm_clock_voltage_dependency_table *vdd_gfx_table =
 484                 hwmgr->dyn_state.vdd_gfx_dependency_on_sclk;
 485         struct phm_acp_clock_voltage_dependency_table *acp_table =
 486                 hwmgr->dyn_state.acp_clock_voltage_dependency_table;
 487         struct phm_uvd_clock_voltage_dependency_table *uvd_table =
 488                 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
 489         struct phm_vce_clock_voltage_dependency_table *vce_table =
 490                 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
 491
 492         if (!hwmgr->need_pp_table_upload)
 493                 return 0;
 494
 495         ret = smum_download_powerplay_table(hwmgr->smumgr, &table);
 496
 497         PP_ASSERT_WITH_CODE((0 == ret && NULL != table),
 498                             "Fail to get clock table from SMU!", return -EINVAL;);
 499
 500         clock_table = (struct SMU8_Fusion_ClkTable *)table;
 501
 502         /* patch clock table */
 503         PP_ASSERT_WITH_CODE((vddc_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
 504                             "Dependency table entry exceeds max limit!", return -EINVAL;);
 505         PP_ASSERT_WITH_CODE((vdd_gfx_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
 506                             "Dependency table entry exceeds max limit!", return -EINVAL;);
 507         PP_ASSERT_WITH_CODE((acp_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
 508                             "Dependency table entry exceeds max limit!", return -EINVAL;);
 509         PP_ASSERT_WITH_CODE((uvd_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
 510                             "Dependency table entry exceeds max limit!", return -EINVAL;);
 511         PP_ASSERT_WITH_CODE((vce_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
 512                             "Dependency table entry exceeds max limit!", return -EINVAL;);
 513
 514         for (i = 0; i < CZ_MAX_HARDWARE_POWERLEVELS; i++) {
 515
 516                 /* vddc_sclk */
 517                 clock_table->SclkBreakdownTable.ClkLevel[i].GnbVid =
 518                         (i < vddc_table->count) ? (uint8_t)vddc_table->entries[i].v : 0;
 519                 clock_table->SclkBreakdownTable.ClkLevel[i].Frequency =
 520                         (i < vddc_table->count) ? vddc_table->entries[i].clk : 0;
 521
 522                 atomctrl_get_engine_pll_dividers_kong(hwmgr,
 523                                                       clock_table->SclkBreakdownTable.ClkLevel[i].Frequency,
 524                                                       &dividers);
 525
 526                 clock_table->SclkBreakdownTable.ClkLevel[i].DfsDid =
 527                         (uint8_t)dividers.pll_post_divider;
 528
 529                 /* vddgfx_sclk */
 530                 clock_table->SclkBreakdownTable.ClkLevel[i].GfxVid =
 531                         (i < vdd_gfx_table->count) ? (uint8_t)vdd_gfx_table->entries[i].v : 0;
 532
 533                 /* acp breakdown */
 534                 clock_table->AclkBreakdownTable.ClkLevel[i].GfxVid =
 535                         (i < acp_table->count) ? (uint8_t)acp_table->entries[i].v : 0;
 536                 clock_table->AclkBreakdownTable.ClkLevel[i].Frequency =
 537                         (i < acp_table->count) ? acp_table->entries[i].acpclk : 0;
 538
 539                 atomctrl_get_engine_pll_dividers_kong(hwmgr,
 540                                                       clock_table->AclkBreakdownTable.ClkLevel[i].Frequency,
 541                                                       &dividers);
 542
 543                 clock_table->AclkBreakdownTable.ClkLevel[i].DfsDid =
 544                         (uint8_t)dividers.pll_post_divider;
 545
 546
 547                 /* uvd breakdown */
 548                 clock_table->VclkBreakdownTable.ClkLevel[i].GfxVid =
 549                         (i < uvd_table->count) ? (uint8_t)uvd_table->entries[i].v : 0;
 550                 clock_table->VclkBreakdownTable.ClkLevel[i].Frequency =
 551                         (i < uvd_table->count) ? uvd_table->entries[i].vclk : 0;
 552
 553                 atomctrl_get_engine_pll_dividers_kong(hwmgr,
 554                                                       clock_table->VclkBreakdownTable.ClkLevel[i].Frequency,
 555                                                       &dividers);
 556
 557                 clock_table->VclkBreakdownTable.ClkLevel[i].DfsDid =
 558                         (uint8_t)dividers.pll_post_divider;
 559
 560                 clock_table->DclkBreakdownTable.ClkLevel[i].GfxVid =
 561                         (i < uvd_table->count) ? (uint8_t)uvd_table->entries[i].v : 0;
 562                 clock_table->DclkBreakdownTable.ClkLevel[i].Frequency =
 563                         (i < uvd_table->count) ? uvd_table->entries[i].dclk : 0;
 564
 565                 atomctrl_get_engine_pll_dividers_kong(hwmgr,
 566                                                       clock_table->DclkBreakdownTable.ClkLevel[i].Frequency,
 567                                                       &dividers);
 568
 569                 clock_table->DclkBreakdownTable.ClkLevel[i].DfsDid =
 570                         (uint8_t)dividers.pll_post_divider;
 571
 572                 /* vce breakdown */
 573                 clock_table->EclkBreakdownTable.ClkLevel[i].GfxVid =
 574                         (i < vce_table->count) ? (uint8_t)vce_table->entries[i].v : 0;
 575                 clock_table->EclkBreakdownTable.ClkLevel[i].Frequency =
 576                         (i < vce_table->count) ? vce_table->entries[i].ecclk : 0;
 577
 578
 579                 atomctrl_get_engine_pll_dividers_kong(hwmgr,
 580                                                       clock_table->EclkBreakdownTable.ClkLevel[i].Frequency,
 581                                                       &dividers);
 582
 583                 clock_table->EclkBreakdownTable.ClkLevel[i].DfsDid =
 584                         (uint8_t)dividers.pll_post_divider;
 585
 586         }
 587         ret = smum_upload_powerplay_table(hwmgr->smumgr);
 588
 589         return ret;
 590 }
 591
 592 static int cz_tf_init_sclk_limit(struct pp_hwmgr *hwmgr, void *input,
 593                                  void *output, void *storage, int result)
 594 {
 595         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 596         struct phm_clock_voltage_dependency_table *table =
 597                                         hwmgr->dyn_state.vddc_dependency_on_sclk;
 598         unsigned long clock = 0, level;
 599
 600         if (NULL == table || table->count <= 0)
 601                 return -EINVAL;
 602
 603         cz_hwmgr->sclk_dpm.soft_min_clk = table->entries[0].clk;
 604         cz_hwmgr->sclk_dpm.hard_min_clk = table->entries[0].clk;
 605
 606         level = cz_get_max_sclk_level(hwmgr) - 1;
 607
 608         if (level < table->count)
 609                 clock = table->entries[level].clk;
 610         else
 611                 clock = table->entries[table->count - 1].clk;
 612
 613         cz_hwmgr->sclk_dpm.soft_max_clk = clock;
 614         cz_hwmgr->sclk_dpm.hard_max_clk = clock;
 615
 616         return 0;
 617 }
 618
 619 static int cz_tf_init_uvd_limit(struct pp_hwmgr *hwmgr, void *input,
 620                                 void *output, void *storage, int result)
 621 {
 622         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 623         struct phm_uvd_clock_voltage_dependency_table *table =
 624                                 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
 625         unsigned long clock = 0, level;
 626
 627         if (NULL == table || table->count <= 0)
 628                 return -EINVAL;
 629
 630         cz_hwmgr->uvd_dpm.soft_min_clk = 0;
 631         cz_hwmgr->uvd_dpm.hard_min_clk = 0;
 632
 633         smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxUvdLevel);
 634         level = smum_get_argument(hwmgr->smumgr);
 635
 636         if (level < table->count)
 637                 clock = table->entries[level].vclk;
 638         else
 639                 clock = table->entries[table->count - 1].vclk;
 640
 641         cz_hwmgr->uvd_dpm.soft_max_clk = clock;
 642         cz_hwmgr->uvd_dpm.hard_max_clk = clock;
 643
 644         return 0;
 645 }
 646
 647 static int cz_tf_init_vce_limit(struct pp_hwmgr *hwmgr, void *input,
 648                                 void *output, void *storage, int result)
 649 {
 650         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 651         struct phm_vce_clock_voltage_dependency_table *table =
 652                                 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
 653         unsigned long clock = 0, level;
 654
 655         if (NULL == table || table->count <= 0)
 656                 return -EINVAL;
 657
 658         cz_hwmgr->vce_dpm.soft_min_clk = 0;
 659         cz_hwmgr->vce_dpm.hard_min_clk = 0;
 660
 661         smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxEclkLevel);
 662         level = smum_get_argument(hwmgr->smumgr);
 663
 664         if (level < table->count)
 665                 clock = table->entries[level].ecclk;
 666         else
 667                 clock = table->entries[table->count - 1].ecclk;
 668
 669         cz_hwmgr->vce_dpm.soft_max_clk = clock;
 670         cz_hwmgr->vce_dpm.hard_max_clk = clock;
 671
 672         return 0;
 673 }
 674
 675 static int cz_tf_init_acp_limit(struct pp_hwmgr *hwmgr, void *input,
 676                                 void *output, void *storage, int result)
 677 {
 678         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 679         struct phm_acp_clock_voltage_dependency_table *table =
 680                                 hwmgr->dyn_state.acp_clock_voltage_dependency_table;
 681         unsigned long clock = 0, level;
 682
 683         if (NULL == table || table->count <= 0)
 684                 return -EINVAL;
 685
 686         cz_hwmgr->acp_dpm.soft_min_clk = 0;
 687         cz_hwmgr->acp_dpm.hard_min_clk = 0;
 688
 689         smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxAclkLevel);
 690         level = smum_get_argument(hwmgr->smumgr);
 691
 692         if (level < table->count)
 693                 clock = table->entries[level].acpclk;
 694         else
 695                 clock = table->entries[table->count - 1].acpclk;
 696
 697         cz_hwmgr->acp_dpm.soft_max_clk = clock;
 698         cz_hwmgr->acp_dpm.hard_max_clk = clock;
 699         return 0;
 700 }
 701
 702 static int cz_tf_init_power_gate_state(struct pp_hwmgr *hwmgr, void *input,
 703                                 void *output, void *storage, int result)
 704 {
 705         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 706
 707         cz_hwmgr->uvd_power_gated = false;
 708         cz_hwmgr->vce_power_gated = false;
 709         cz_hwmgr->samu_power_gated = false;
 710         cz_hwmgr->acp_power_gated = false;
 711         cz_hwmgr->pgacpinit = true;
 712
 713         return 0;
 714 }
 715
 716 static int cz_tf_init_sclk_threshold(struct pp_hwmgr *hwmgr, void *input,
 717                                 void *output, void *storage, int result)
 718 {
 719         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 720
 721         cz_hwmgr->low_sclk_interrupt_threshold = 0;
 722
 723         return 0;
 724 }
 725 static int cz_tf_update_sclk_limit(struct pp_hwmgr *hwmgr,
 726                                         void *input, void *output,
 727                                         void *storage, int result)
 728 {
 729         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 730         struct phm_clock_voltage_dependency_table *table =
 731                                         hwmgr->dyn_state.vddc_dependency_on_sclk;
 732
 733         unsigned long clock = 0;
 734         unsigned long level;
 735         unsigned long stable_pstate_sclk;
 736         unsigned long percentage;
 737
 738         cz_hwmgr->sclk_dpm.soft_min_clk = table->entries[0].clk;
 739         level = cz_get_max_sclk_level(hwmgr) - 1;
 740
 741         if (level < table->count)
 742                 cz_hwmgr->sclk_dpm.soft_max_clk  = table->entries[level].clk;
 743         else
 744                 cz_hwmgr->sclk_dpm.soft_max_clk  = table->entries[table->count - 1].clk;
 745
 746         clock = hwmgr->display_config.min_core_set_clock;
 747 ;
 748         if (clock == 0)
 749                 printk(KERN_INFO "[ powerplay ] min_core_set_clock not set\n");
 750
 751         if (cz_hwmgr->sclk_dpm.hard_min_clk != clock) {
 752                 cz_hwmgr->sclk_dpm.hard_min_clk = clock;
 753
 754                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 755                                                 PPSMC_MSG_SetSclkHardMin,
 756                                                  cz_get_sclk_level(hwmgr,
 757                                         cz_hwmgr->sclk_dpm.hard_min_clk,
 758                                              PPSMC_MSG_SetSclkHardMin));
 759         }
 760
 761         clock = cz_hwmgr->sclk_dpm.soft_min_clk;
 762
 763         /* update minimum clocks for Stable P-State feature */
 764         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 765                                      PHM_PlatformCaps_StablePState)) {
 766                 percentage = 75;
 767                 /*Sclk - calculate sclk value based on percentage and find FLOOR sclk from VddcDependencyOnSCLK table  */
 768                 stable_pstate_sclk = (hwmgr->dyn_state.max_clock_voltage_on_ac.mclk *
 769                                         percentage) / 100;
 770
 771                 if (clock < stable_pstate_sclk)
 772                         clock = stable_pstate_sclk;
 773         } else {
 774                 if (clock < hwmgr->gfx_arbiter.sclk)
 775                         clock = hwmgr->gfx_arbiter.sclk;
 776         }
 777
 778         if (cz_hwmgr->sclk_dpm.soft_min_clk != clock) {
 779                 cz_hwmgr->sclk_dpm.soft_min_clk = clock;
 780                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 781                                                 PPSMC_MSG_SetSclkSoftMin,
 782                                                 cz_get_sclk_level(hwmgr,
 783                                         cz_hwmgr->sclk_dpm.soft_min_clk,
 784                                              PPSMC_MSG_SetSclkSoftMin));
 785         }
 786
 787         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 788                                     PHM_PlatformCaps_StablePState) &&
 789                          cz_hwmgr->sclk_dpm.soft_max_clk != clock) {
 790                 cz_hwmgr->sclk_dpm.soft_max_clk = clock;
 791                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 792                                                 PPSMC_MSG_SetSclkSoftMax,
 793                                                 cz_get_sclk_level(hwmgr,
 794                                         cz_hwmgr->sclk_dpm.soft_max_clk,
 795                                         PPSMC_MSG_SetSclkSoftMax));
 796         }
 797
 798         return 0;
 799 }
 800
 801 static int cz_tf_set_deep_sleep_sclk_threshold(struct pp_hwmgr *hwmgr,
 802                                         void *input, void *output,
 803                                         void *storage, int result)
 804 {
 805         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 806                                 PHM_PlatformCaps_SclkDeepSleep)) {
 807                 uint32_t clks = hwmgr->display_config.min_core_set_clock_in_sr;
 808                 if (clks == 0)
 809                         clks = CZ_MIN_DEEP_SLEEP_SCLK;
 810
 811                 PP_DBG_LOG("Setting Deep Sleep Clock: %d\n", clks);
 812
 813                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 814                                 PPSMC_MSG_SetMinDeepSleepSclk,
 815                                 clks);
 816         }
 817
 818         return 0;
 819 }
 820
 821 static int cz_tf_set_watermark_threshold(struct pp_hwmgr *hwmgr,
 822                                         void *input, void *output,
 823                                         void *storage, int result)
 824 {
 825         struct cz_hwmgr *cz_hwmgr =
 826                                   (struct cz_hwmgr *)(hwmgr->backend);
 827
 828         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 829                                         PPSMC_MSG_SetWatermarkFrequency,
 830                                       cz_hwmgr->sclk_dpm.soft_max_clk);
 831
 832         return 0;
 833 }
 834
 835 static int cz_tf_set_enabled_levels(struct pp_hwmgr *hwmgr,
 836                                         void *input, void *output,
 837                                         void *storage, int result)
 838 {
 839         return 0;
 840 }
 841
 842
 843 static int cz_tf_enable_nb_dpm(struct pp_hwmgr *hwmgr,
 844                                         void *input, void *output,
 845                                         void *storage, int result)
 846 {
 847         int ret = 0;
 848
 849         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 850         unsigned long dpm_features = 0;
 851
 852         if (!cz_hwmgr->is_nb_dpm_enabled) {
 853                 PP_DBG_LOG("enabling ALL SMU features.\n");
 854                 dpm_features |= NB_DPM_MASK;
 855                 ret = smum_send_msg_to_smc_with_parameter(
 856                                                              hwmgr->smumgr,
 857                                          PPSMC_MSG_EnableAllSmuFeatures,
 858                                                              dpm_features);
 859                 if (ret == 0)
 860                         cz_hwmgr->is_nb_dpm_enabled = true;
 861         }
 862
 863         return ret;
 864 }
 865
 866 static int cz_nbdpm_pstate_enable_disable(struct pp_hwmgr *hwmgr, bool enable, bool lock)
 867 {
 868         struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
 869
 870         if (hw_data->is_nb_dpm_enabled) {
 871                 if (enable) {
 872                         PP_DBG_LOG("enable Low Memory PState.\n");
 873
 874                         return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 875                                                 PPSMC_MSG_EnableLowMemoryPstate,
 876                                                 (lock ? 1 : 0));
 877                 } else {
 878                         PP_DBG_LOG("disable Low Memory PState.\n");
 879
 880                         return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 881                                                 PPSMC_MSG_DisableLowMemoryPstate,
 882                                                 (lock ? 1 : 0));
 883                 }
 884         }
 885
 886         return 0;
 887 }
 888
 889 static int cz_tf_update_low_mem_pstate(struct pp_hwmgr *hwmgr,
 890                                         void *input, void *output,
 891                                         void *storage, int result)
 892 {
 893         bool disable_switch;
 894         bool enable_low_mem_state;
 895         struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
 896         const struct phm_set_power_state_input *states = (struct phm_set_power_state_input *)input;
 897         const struct cz_power_state *pnew_state = cast_const_PhwCzPowerState(states->pnew_state);
 898
 899         if (hw_data->sys_info.nb_dpm_enable) {
 900                 disable_switch = hw_data->cc6_settings.nb_pstate_switch_disable ? true : false;
 901                 enable_low_mem_state = hw_data->cc6_settings.nb_pstate_switch_disable ? false : true;
 902
 903                 if (pnew_state->action == FORCE_HIGH)
 904                         cz_nbdpm_pstate_enable_disable(hwmgr, false, disable_switch);
 905                 else if (pnew_state->action == CANCEL_FORCE_HIGH)
 906                         cz_nbdpm_pstate_enable_disable(hwmgr, true, disable_switch);
 907                 else
 908                         cz_nbdpm_pstate_enable_disable(hwmgr, enable_low_mem_state, disable_switch);
 909         }
 910         return 0;
 911 }
 912
 913 static struct phm_master_table_item cz_set_power_state_list[] = {
 914         {NULL, cz_tf_update_sclk_limit},
 915         {NULL, cz_tf_set_deep_sleep_sclk_threshold},
 916         {NULL, cz_tf_set_watermark_threshold},
 917         {NULL, cz_tf_set_enabled_levels},
 918         {NULL, cz_tf_enable_nb_dpm},
 919         {NULL, cz_tf_update_low_mem_pstate},
 920         {NULL, NULL}
 921 };
 922
 923 static struct phm_master_table_header cz_set_power_state_master = {
 924         0,
 925         PHM_MasterTableFlag_None,
 926         cz_set_power_state_list
 927 };
 928
 929 static struct phm_master_table_item cz_setup_asic_list[] = {
 930         {NULL, cz_tf_reset_active_process_mask},
 931         {NULL, cz_tf_upload_pptable_to_smu},
 932         {NULL, cz_tf_init_sclk_limit},
 933         {NULL, cz_tf_init_uvd_limit},
 934         {NULL, cz_tf_init_vce_limit},
 935         {NULL, cz_tf_init_acp_limit},
 936         {NULL, cz_tf_init_power_gate_state},
 937         {NULL, cz_tf_init_sclk_threshold},
 938         {NULL, NULL}
 939 };
 940
 941 static struct phm_master_table_header cz_setup_asic_master = {
 942         0,
 943         PHM_MasterTableFlag_None,
 944         cz_setup_asic_list
 945 };
 946
 947 static int cz_tf_power_up_display_clock_sys_pll(struct pp_hwmgr *hwmgr,
 948                                         void *input, void *output,
 949                                         void *storage, int result)
 950 {
 951         struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
 952         hw_data->disp_clk_bypass_pending = false;
 953         hw_data->disp_clk_bypass = false;
 954
 955         return 0;
 956 }
 957
 958 static int cz_tf_clear_nb_dpm_flag(struct pp_hwmgr *hwmgr,
 959                                         void *input, void *output,
 960                                         void *storage, int result)
 961 {
 962         struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
 963         hw_data->is_nb_dpm_enabled = false;
 964
 965         return 0;
 966 }
 967
 968 static int cz_tf_reset_cc6_data(struct pp_hwmgr *hwmgr,
 969                                         void *input, void *output,
 970                                         void *storage, int result)
 971 {
 972         struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
 973
 974         hw_data->cc6_settings.cc6_setting_changed = false;
 975         hw_data->cc6_settings.cpu_pstate_separation_time = 0;
 976         hw_data->cc6_settings.cpu_cc6_disable = false;
 977         hw_data->cc6_settings.cpu_pstate_disable = false;
 978
 979         return 0;
 980 }
 981
 982 static struct phm_master_table_item cz_power_down_asic_list[] = {
 983         {NULL, cz_tf_power_up_display_clock_sys_pll},
 984         {NULL, cz_tf_clear_nb_dpm_flag},
 985         {NULL, cz_tf_reset_cc6_data},
 986         {NULL, NULL}
 987 };
 988
 989 static struct phm_master_table_header cz_power_down_asic_master = {
 990         0,
 991         PHM_MasterTableFlag_None,
 992         cz_power_down_asic_list
 993 };
 994
 995 static int cz_tf_program_voting_clients(struct pp_hwmgr *hwmgr, void *input,
 996                                 void *output, void *storage, int result)
 997 {
 998         PHMCZ_WRITE_SMC_REGISTER(hwmgr->device, CG_FREQ_TRAN_VOTING_0,
 999                                 PPCZ_VOTINGRIGHTSCLIENTS_DFLT0);
1000         return 0;
1001 }
1002
1003 static int cz_tf_start_dpm(struct pp_hwmgr *hwmgr, void *input, void *output,
1004                            void *storage, int result)
1005 {
1006         int res = 0xff;
1007         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1008         unsigned long dpm_features = 0;
1009
1010         cz_hwmgr->dpm_flags |= DPMFlags_SCLK_Enabled;
1011         dpm_features |= SCLK_DPM_MASK;
1012
1013         res = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1014                                 PPSMC_MSG_EnableAllSmuFeatures,
1015                                 dpm_features);
1016
1017         return res;
1018 }
1019
1020 static int cz_tf_program_bootup_state(struct pp_hwmgr *hwmgr, void *input,
1021                                 void *output, void *storage, int result)
1022 {
1023         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1024
1025         cz_hwmgr->sclk_dpm.soft_min_clk = cz_hwmgr->sys_info.bootup_engine_clock;
1026         cz_hwmgr->sclk_dpm.soft_max_clk = cz_hwmgr->sys_info.bootup_engine_clock;
1027
1028         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1029                                 PPSMC_MSG_SetSclkSoftMin,
1030                                 cz_get_sclk_level(hwmgr,
1031                                 cz_hwmgr->sclk_dpm.soft_min_clk,
1032                                 PPSMC_MSG_SetSclkSoftMin));
1033
1034         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1035                                 PPSMC_MSG_SetSclkSoftMax,
1036                                 cz_get_sclk_level(hwmgr,
1037                                 cz_hwmgr->sclk_dpm.soft_max_clk,
1038                                 PPSMC_MSG_SetSclkSoftMax));
1039
1040         return 0;
1041 }
1042
1043 int cz_tf_reset_acp_boot_level(struct pp_hwmgr *hwmgr, void *input,
1044                                 void *output, void *storage, int result)
1045 {
1046         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1047
1048         cz_hwmgr->acp_boot_level = 0xff;
1049         return 0;
1050 }
1051
1052 static bool cz_dpm_check_smu_features(struct pp_hwmgr *hwmgr,
1053                                 unsigned long check_feature)
1054 {
1055         int result;
1056         unsigned long features;
1057
1058         result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_GetFeatureStatus, 0);
1059         if (result == 0) {
1060                 features = smum_get_argument(hwmgr->smumgr);
1061                 if (features & check_feature)
1062                         return true;
1063         }
1064
1065         return result;
1066 }
1067
1068 static int cz_tf_check_for_dpm_disabled(struct pp_hwmgr *hwmgr, void *input,
1069                                 void *output, void *storage, int result)
1070 {
1071         if (cz_dpm_check_smu_features(hwmgr, SMU_EnabledFeatureScoreboard_SclkDpmOn))
1072                 return PP_Result_TableImmediateExit;
1073         return 0;
1074 }
1075
1076 static int cz_tf_enable_didt(struct pp_hwmgr *hwmgr, void *input,
1077                                 void *output, void *storage, int result)
1078 {
1079         /* TO DO */
1080         return 0;
1081 }
1082
1083 static int cz_tf_check_for_dpm_enabled(struct pp_hwmgr *hwmgr,
1084                                                 void *input, void *output,
1085                                                 void *storage, int result)
1086 {
1087         if (!cz_dpm_check_smu_features(hwmgr,
1088                              SMU_EnabledFeatureScoreboard_SclkDpmOn))
1089                 return PP_Result_TableImmediateExit;
1090         return 0;
1091 }
1092
1093 static struct phm_master_table_item cz_disable_dpm_list[] = {
1094         { NULL, cz_tf_check_for_dpm_enabled},
1095         {NULL, NULL},
1096 };
1097
1098
1099 static struct phm_master_table_header cz_disable_dpm_master = {
1100         0,
1101         PHM_MasterTableFlag_None,
1102         cz_disable_dpm_list
1103 };
1104
1105 static struct phm_master_table_item cz_enable_dpm_list[] = {
1106         { NULL, cz_tf_check_for_dpm_disabled },
1107         { NULL, cz_tf_program_voting_clients },
1108         { NULL, cz_tf_start_dpm},
1109         { NULL, cz_tf_program_bootup_state},
1110         { NULL, cz_tf_enable_didt },
1111         { NULL, cz_tf_reset_acp_boot_level },
1112         {NULL, NULL},
1113 };
1114
1115 static struct phm_master_table_header cz_enable_dpm_master = {
1116         0,
1117         PHM_MasterTableFlag_None,
1118         cz_enable_dpm_list
1119 };
1120
1121 static int cz_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
1122                                 struct pp_power_state  *prequest_ps,
1123                         const struct pp_power_state *pcurrent_ps)
1124 {
1125         struct cz_power_state *cz_ps =
1126                                 cast_PhwCzPowerState(&prequest_ps->hardware);
1127
1128         const struct cz_power_state *cz_current_ps =
1129                                 cast_const_PhwCzPowerState(&pcurrent_ps->hardware);
1130
1131         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1132         struct PP_Clocks clocks = {0, 0, 0, 0};
1133         bool force_high;
1134         uint32_t  num_of_active_displays = 0;
1135         struct cgs_display_info info = {0};
1136
1137         cz_ps->evclk = hwmgr->vce_arbiter.evclk;
1138         cz_ps->ecclk = hwmgr->vce_arbiter.ecclk;
1139
1140         cz_ps->need_dfs_bypass = true;
1141
1142         cz_hwmgr->video_start = (hwmgr->uvd_arbiter.vclk != 0 || hwmgr->uvd_arbiter.dclk != 0 ||
1143                                 hwmgr->vce_arbiter.evclk != 0 || hwmgr->vce_arbiter.ecclk != 0);
1144
1145         cz_hwmgr->battery_state = (PP_StateUILabel_Battery == prequest_ps->classification.ui_label);
1146
1147         clocks.memoryClock = hwmgr->display_config.min_mem_set_clock != 0 ?
1148                                 hwmgr->display_config.min_mem_set_clock :
1149                                 cz_hwmgr->sys_info.nbp_memory_clock[1];
1150
1151         cgs_get_active_displays_info(hwmgr->device, &info);
1152         num_of_active_displays = info.display_count;
1153
1154         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
1155                 clocks.memoryClock = hwmgr->dyn_state.max_clock_voltage_on_ac.mclk;
1156
1157         if (clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
1158                 clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
1159
1160         force_high = (clocks.memoryClock > cz_hwmgr->sys_info.nbp_memory_clock[CZ_NUM_NBPMEMORYCLOCK - 1])
1161                         || (num_of_active_displays >= 3);
1162
1163         cz_ps->action = cz_current_ps->action;
1164
1165         if ((force_high == false) && (cz_ps->action == FORCE_HIGH))
1166                 cz_ps->action = CANCEL_FORCE_HIGH;
1167         else if ((force_high == true) && (cz_ps->action != FORCE_HIGH))
1168                 cz_ps->action = FORCE_HIGH;
1169         else
1170                 cz_ps->action = DO_NOTHING;
1171
1172         return 0;
1173 }
1174
1175 static int cz_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
1176 {
1177         int result = 0;
1178
1179         result = cz_initialize_dpm_defaults(hwmgr);
1180         if (result != 0) {
1181                 printk(KERN_ERR "[ powerplay ] cz_initialize_dpm_defaults failed\n");
1182                 return result;
1183         }
1184
1185         result = cz_get_system_info_data(hwmgr);
1186         if (result != 0) {
1187                 printk(KERN_ERR "[ powerplay ] cz_get_system_info_data failed\n");
1188                 return result;
1189         }
1190
1191         cz_construct_boot_state(hwmgr);
1192
1193         result = phm_construct_table(hwmgr, &cz_setup_asic_master,
1194                                 &(hwmgr->setup_asic));
1195         if (result != 0) {
1196                 printk(KERN_ERR "[ powerplay ] Fail to construct setup ASIC\n");
1197                 return result;
1198         }
1199
1200         result = phm_construct_table(hwmgr, &cz_power_down_asic_master,
1201                                 &(hwmgr->power_down_asic));
1202         if (result != 0) {
1203                 printk(KERN_ERR "[ powerplay ] Fail to construct power down ASIC\n");
1204                 return result;
1205         }
1206
1207         result = phm_construct_table(hwmgr, &cz_disable_dpm_master,
1208                                 &(hwmgr->disable_dynamic_state_management));
1209         if (result != 0) {
1210                 printk(KERN_ERR "[ powerplay ] Fail to disable_dynamic_state\n");
1211                 return result;
1212         }
1213         result = phm_construct_table(hwmgr, &cz_enable_dpm_master,
1214                                 &(hwmgr->enable_dynamic_state_management));
1215         if (result != 0) {
1216                 printk(KERN_ERR "[ powerplay ] Fail to enable_dynamic_state\n");
1217                 return result;
1218         }
1219         result = phm_construct_table(hwmgr, &cz_set_power_state_master,
1220                                 &(hwmgr->set_power_state));
1221         if (result != 0) {
1222                 printk(KERN_ERR "[ powerplay ] Fail to construct set_power_state\n");
1223                 return result;
1224         }
1225         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =  CZ_MAX_HARDWARE_POWERLEVELS;
1226
1227         result = phm_construct_table(hwmgr, &cz_phm_enable_clock_power_gatings_master, &(hwmgr->enable_clock_power_gatings));
1228         if (result != 0) {
1229                 printk(KERN_ERR "[ powerplay ] Fail to construct enable_clock_power_gatings\n");
1230                 return result;
1231         }
1232         return result;
1233 }
1234
1235 static int cz_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
1236 {
1237         if (hwmgr != NULL || hwmgr->backend != NULL) {
1238                 kfree(hwmgr->backend);
1239                 kfree(hwmgr);
1240         }
1241         return 0;
1242 }
1243
1244 int cz_phm_force_dpm_highest(struct pp_hwmgr *hwmgr)
1245 {
1246         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1247
1248         if (cz_hwmgr->sclk_dpm.soft_min_clk !=
1249                                 cz_hwmgr->sclk_dpm.soft_max_clk)
1250                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1251                                                 PPSMC_MSG_SetSclkSoftMin,
1252                                                 cz_get_sclk_level(hwmgr,
1253                                                 cz_hwmgr->sclk_dpm.soft_max_clk,
1254                                                 PPSMC_MSG_SetSclkSoftMin));
1255         return 0;
1256 }
1257
1258 int cz_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
1259 {
1260         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1261         struct phm_clock_voltage_dependency_table *table =
1262                                 hwmgr->dyn_state.vddc_dependency_on_sclk;
1263         unsigned long clock = 0, level;
1264
1265         if (NULL == table || table->count <= 0)
1266                 return -EINVAL;
1267
1268         cz_hwmgr->sclk_dpm.soft_min_clk = table->entries[0].clk;
1269         cz_hwmgr->sclk_dpm.hard_min_clk = table->entries[0].clk;
1270
1271         level = cz_get_max_sclk_level(hwmgr) - 1;
1272
1273         if (level < table->count)
1274                 clock = table->entries[level].clk;
1275         else
1276                 clock = table->entries[table->count - 1].clk;
1277
1278         cz_hwmgr->sclk_dpm.soft_max_clk = clock;
1279         cz_hwmgr->sclk_dpm.hard_max_clk = clock;
1280
1281         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1282                                 PPSMC_MSG_SetSclkSoftMin,
1283                                 cz_get_sclk_level(hwmgr,
1284                                 cz_hwmgr->sclk_dpm.soft_min_clk,
1285                                 PPSMC_MSG_SetSclkSoftMin));
1286
1287         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1288                                 PPSMC_MSG_SetSclkSoftMax,
1289                                 cz_get_sclk_level(hwmgr,
1290                                 cz_hwmgr->sclk_dpm.soft_max_clk,
1291                                 PPSMC_MSG_SetSclkSoftMax));
1292
1293         return 0;
1294 }
1295
1296 int cz_phm_force_dpm_lowest(struct pp_hwmgr *hwmgr)
1297 {
1298         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1299
1300         if (cz_hwmgr->sclk_dpm.soft_min_clk !=
1301                                 cz_hwmgr->sclk_dpm.soft_max_clk) {
1302                 cz_hwmgr->sclk_dpm.soft_max_clk =
1303                         cz_hwmgr->sclk_dpm.soft_min_clk;
1304
1305                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1306                                 PPSMC_MSG_SetSclkSoftMax,
1307                                 cz_get_sclk_level(hwmgr,
1308                                 cz_hwmgr->sclk_dpm.soft_max_clk,
1309                                 PPSMC_MSG_SetSclkSoftMax));
1310         }
1311
1312         return 0;
1313 }
1314
1315 static int cz_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
1316                                 enum amd_dpm_forced_level level)
1317 {
1318         int ret = 0;
1319
1320         switch (level) {
1321         case AMD_DPM_FORCED_LEVEL_HIGH:
1322                 ret = cz_phm_force_dpm_highest(hwmgr);
1323                 if (ret)
1324                         return ret;
1325                 break;
1326         case AMD_DPM_FORCED_LEVEL_LOW:
1327                 ret = cz_phm_force_dpm_lowest(hwmgr);
1328                 if (ret)
1329                         return ret;
1330                 break;
1331         case AMD_DPM_FORCED_LEVEL_AUTO:
1332                 ret = cz_phm_unforce_dpm_levels(hwmgr);
1333                 if (ret)
1334                         return ret;
1335                 break;
1336         default:
1337                 break;
1338         }
1339
1340         hwmgr->dpm_level = level;
1341
1342         return ret;
1343 }
1344
1345 int cz_dpm_powerdown_uvd(struct pp_hwmgr *hwmgr)
1346 {
1347         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1348                                          PHM_PlatformCaps_UVDPowerGating))
1349                 return smum_send_msg_to_smc(hwmgr->smumgr,
1350                                                      PPSMC_MSG_UVDPowerOFF);
1351         return 0;
1352 }
1353
1354 int cz_dpm_powerup_uvd(struct pp_hwmgr *hwmgr)
1355 {
1356         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1357                                          PHM_PlatformCaps_UVDPowerGating)) {
1358                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1359                                   PHM_PlatformCaps_UVDDynamicPowerGating)) {
1360                         return smum_send_msg_to_smc_with_parameter(
1361                                                                 hwmgr->smumgr,
1362                                                    PPSMC_MSG_UVDPowerON, 1);
1363                 } else {
1364                         return smum_send_msg_to_smc_with_parameter(
1365                                                                 hwmgr->smumgr,
1366                                                    PPSMC_MSG_UVDPowerON, 0);
1367                 }
1368         }
1369
1370         return 0;
1371 }
1372
1373 int cz_dpm_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
1374 {
1375         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1376         struct phm_uvd_clock_voltage_dependency_table *ptable =
1377                 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
1378
1379         if (!bgate) {
1380                 /* Stable Pstate is enabled and we need to set the UVD DPM to highest level */
1381                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1382                                          PHM_PlatformCaps_StablePState)) {
1383                         cz_hwmgr->uvd_dpm.hard_min_clk =
1384                                    ptable->entries[ptable->count - 1].vclk;
1385
1386                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1387                                                      PPSMC_MSG_SetUvdHardMin,
1388                                                       cz_get_uvd_level(hwmgr,
1389                                              cz_hwmgr->uvd_dpm.hard_min_clk,
1390                                                    PPSMC_MSG_SetUvdHardMin));
1391
1392                         cz_enable_disable_uvd_dpm(hwmgr, true);
1393                 } else
1394                         cz_enable_disable_uvd_dpm(hwmgr, true);
1395         } else
1396                 cz_enable_disable_uvd_dpm(hwmgr, false);
1397
1398         return 0;
1399 }
1400
1401 int  cz_dpm_update_vce_dpm(struct pp_hwmgr *hwmgr)
1402 {
1403         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1404         struct phm_vce_clock_voltage_dependency_table *ptable =
1405                 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
1406
1407         /* Stable Pstate is enabled and we need to set the VCE DPM to highest level */
1408         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1409                                          PHM_PlatformCaps_StablePState)) {
1410                 cz_hwmgr->vce_dpm.hard_min_clk =
1411                                   ptable->entries[ptable->count - 1].ecclk;
1412
1413                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1414                                         PPSMC_MSG_SetEclkHardMin,
1415                                         cz_get_eclk_level(hwmgr,
1416                                              cz_hwmgr->vce_dpm.hard_min_clk,
1417                                                 PPSMC_MSG_SetEclkHardMin));
1418         } else {
1419                 /*EPR# 419220 -HW limitation to to */
1420                 cz_hwmgr->vce_dpm.hard_min_clk = hwmgr->vce_arbiter.ecclk;
1421                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1422                                             PPSMC_MSG_SetEclkHardMin,
1423                                             cz_get_eclk_level(hwmgr,
1424                                      cz_hwmgr->vce_dpm.hard_min_clk,
1425                                           PPSMC_MSG_SetEclkHardMin));
1426
1427         }
1428         return 0;
1429 }
1430
1431 int cz_dpm_powerdown_vce(struct pp_hwmgr *hwmgr)
1432 {
1433         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1434                                          PHM_PlatformCaps_VCEPowerGating))
1435                 return smum_send_msg_to_smc(hwmgr->smumgr,
1436                                                      PPSMC_MSG_VCEPowerOFF);
1437         return 0;
1438 }
1439
1440 int cz_dpm_powerup_vce(struct pp_hwmgr *hwmgr)
1441 {
1442         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1443                                          PHM_PlatformCaps_VCEPowerGating))
1444                 return smum_send_msg_to_smc(hwmgr->smumgr,
1445                                                      PPSMC_MSG_VCEPowerON);
1446         return 0;
1447 }
1448
1449 static int cz_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
1450 {
1451         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1452
1453         return cz_hwmgr->sys_info.bootup_uma_clock;
1454 }
1455
1456 static int cz_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
1457 {
1458         struct pp_power_state  *ps;
1459         struct cz_power_state  *cz_ps;
1460
1461         if (hwmgr == NULL)
1462                 return -EINVAL;
1463
1464         ps = hwmgr->request_ps;
1465
1466         if (ps == NULL)
1467                 return -EINVAL;
1468
1469         cz_ps = cast_PhwCzPowerState(&ps->hardware);
1470
1471         if (low)
1472                 return cz_ps->levels[0].engineClock;
1473         else
1474                 return cz_ps->levels[cz_ps->level-1].engineClock;
1475 }
1476
1477 static int cz_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
1478                                         struct pp_hw_power_state *hw_ps)
1479 {
1480         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1481         struct cz_power_state *cz_ps = cast_PhwCzPowerState(hw_ps);
1482
1483         cz_ps->level = 1;
1484         cz_ps->nbps_flags = 0;
1485         cz_ps->bapm_flags = 0;
1486         cz_ps->levels[0] = cz_hwmgr->boot_power_level;
1487
1488         return 0;
1489 }
1490
1491 static int cz_dpm_get_pp_table_entry_callback(
1492                                                      struct pp_hwmgr *hwmgr,
1493                                            struct pp_hw_power_state *hw_ps,
1494                                                           unsigned int index,
1495                                                      const void *clock_info)
1496 {
1497         struct cz_power_state *cz_ps = cast_PhwCzPowerState(hw_ps);
1498
1499         const ATOM_PPLIB_CZ_CLOCK_INFO *cz_clock_info = clock_info;
1500
1501         struct phm_clock_voltage_dependency_table *table =
1502                                     hwmgr->dyn_state.vddc_dependency_on_sclk;
1503         uint8_t clock_info_index = cz_clock_info->index;
1504
1505         if (clock_info_index > (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1))
1506                 clock_info_index = (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1);
1507
1508         cz_ps->levels[index].engineClock = table->entries[clock_info_index].clk;
1509         cz_ps->levels[index].vddcIndex = (uint8_t)table->entries[clock_info_index].v;
1510
1511         cz_ps->level = index + 1;
1512
1513         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
1514                 cz_ps->levels[index].dsDividerIndex = 5;
1515                 cz_ps->levels[index].ssDividerIndex = 5;
1516         }
1517
1518         return 0;
1519 }
1520
1521 static int cz_dpm_get_num_of_pp_table_entries(struct pp_hwmgr *hwmgr)
1522 {
1523         int result;
1524         unsigned long ret = 0;
1525
1526         result = pp_tables_get_num_of_entries(hwmgr, &ret);
1527
1528         return result ? 0 : ret;
1529 }
1530
1531 static int cz_dpm_get_pp_table_entry(struct pp_hwmgr *hwmgr,
1532                     unsigned long entry, struct pp_power_state *ps)
1533 {
1534         int result;
1535         struct cz_power_state *cz_ps;
1536
1537         ps->hardware.magic = PhwCz_Magic;
1538
1539         cz_ps = cast_PhwCzPowerState(&(ps->hardware));
1540
1541         result = pp_tables_get_entry(hwmgr, entry, ps,
1542                         cz_dpm_get_pp_table_entry_callback);
1543
1544         cz_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK;
1545         cz_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK;
1546
1547         return result;
1548 }
1549
1550 int cz_get_power_state_size(struct pp_hwmgr *hwmgr)
1551 {
1552         return sizeof(struct cz_power_state);
1553 }
1554
1555 static void
1556 cz_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
1557 {
1558         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1559
1560         struct phm_clock_voltage_dependency_table *table =
1561                                 hwmgr->dyn_state.vddc_dependency_on_sclk;
1562
1563         struct phm_vce_clock_voltage_dependency_table *vce_table =
1564                 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
1565
1566         struct phm_uvd_clock_voltage_dependency_table *uvd_table =
1567                 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
1568
1569         uint32_t sclk_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX),
1570                                         TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX);
1571         uint32_t uvd_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
1572                                         TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_UVD_INDEX);
1573         uint32_t vce_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
1574                                         TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_VCE_INDEX);
1575
1576         uint32_t sclk, vclk, dclk, ecclk, tmp, activity_percent;
1577         uint16_t vddnb, vddgfx;
1578         int result;
1579
1580         if (sclk_index >= NUM_SCLK_LEVELS) {
1581                 seq_printf(m, "\n invalid sclk dpm profile %d\n", sclk_index);
1582         } else {
1583                 sclk = table->entries[sclk_index].clk;
1584                 seq_printf(m, "\n index: %u sclk: %u MHz\n", sclk_index, sclk/100);
1585         }
1586
1587         tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_NB_CURRENTVID) &
1588                 CURRENT_NB_VID_MASK) >> CURRENT_NB_VID__SHIFT;
1589         vddnb = cz_convert_8Bit_index_to_voltage(hwmgr, tmp);
1590         tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_GFX_CURRENTVID) &
1591                 CURRENT_GFX_VID_MASK) >> CURRENT_GFX_VID__SHIFT;
1592         vddgfx = cz_convert_8Bit_index_to_voltage(hwmgr, (u16)tmp);
1593         seq_printf(m, "\n vddnb: %u vddgfx: %u\n", vddnb, vddgfx);
1594
1595         seq_printf(m, "\n uvd    %sabled\n", cz_hwmgr->uvd_power_gated ? "dis" : "en");
1596         if (!cz_hwmgr->uvd_power_gated) {
1597                 if (uvd_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
1598                         seq_printf(m, "\n invalid uvd dpm level %d\n", uvd_index);
1599                 } else {
1600                         vclk = uvd_table->entries[uvd_index].vclk;
1601                         dclk = uvd_table->entries[uvd_index].dclk;
1602                         seq_printf(m, "\n index: %u uvd vclk: %u MHz dclk: %u MHz\n", uvd_index, vclk/100, dclk/100);
1603                 }
1604         }
1605
1606         seq_printf(m, "\n vce    %sabled\n", cz_hwmgr->vce_power_gated ? "dis" : "en");
1607         if (!cz_hwmgr->vce_power_gated) {
1608                 if (vce_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
1609                         seq_printf(m, "\n invalid vce dpm level %d\n", vce_index);
1610                 } else {
1611                         ecclk = vce_table->entries[vce_index].ecclk;
1612                         seq_printf(m, "\n index: %u vce ecclk: %u MHz\n", vce_index, ecclk/100);
1613                 }
1614         }
1615
1616         result = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetAverageGraphicsActivity);
1617         if (0 == result) {
1618                 activity_percent = cgs_read_register(hwmgr->device, mmSMU_MP1_SRBM2P_ARG_0);
1619                 activity_percent = activity_percent > 100 ? 100 : activity_percent;
1620         } else {
1621                 activity_percent = 50;
1622         }
1623
1624         seq_printf(m, "\n [GPU load]: %u %%\n\n", activity_percent);
1625 }
1626
1627 static void cz_hw_print_display_cfg(
1628         const struct cc6_settings *cc6_settings)
1629 {
1630         PP_DBG_LOG("New Display Configuration:\n");
1631
1632         PP_DBG_LOG("   cpu_cc6_disable: %d\n",
1633                         cc6_settings->cpu_cc6_disable);
1634         PP_DBG_LOG("   cpu_pstate_disable: %d\n",
1635                         cc6_settings->cpu_pstate_disable);
1636         PP_DBG_LOG("   nb_pstate_switch_disable: %d\n",
1637                         cc6_settings->nb_pstate_switch_disable);
1638         PP_DBG_LOG("   cpu_pstate_separation_time: %d\n\n",
1639                         cc6_settings->cpu_pstate_separation_time);
1640 }
1641
1642  static int cz_set_cpu_power_state(struct pp_hwmgr *hwmgr)
1643 {
1644         struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
1645         uint32_t data = 0;
1646
1647         if (hw_data->cc6_settings.cc6_setting_changed == true) {
1648
1649                 hw_data->cc6_settings.cc6_setting_changed = false;
1650
1651                 cz_hw_print_display_cfg(&hw_data->cc6_settings);
1652
1653                 data |= (hw_data->cc6_settings.cpu_pstate_separation_time
1654                         & PWRMGT_SEPARATION_TIME_MASK)
1655                         << PWRMGT_SEPARATION_TIME_SHIFT;
1656
1657                 data |= (hw_data->cc6_settings.cpu_cc6_disable ? 0x1 : 0x0)
1658                         << PWRMGT_DISABLE_CPU_CSTATES_SHIFT;
1659
1660                 data |= (hw_data->cc6_settings.cpu_pstate_disable ? 0x1 : 0x0)
1661                         << PWRMGT_DISABLE_CPU_PSTATES_SHIFT;
1662
1663                 PP_DBG_LOG("SetDisplaySizePowerParams data: 0x%X\n",
1664                         data);
1665
1666                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1667                                                 PPSMC_MSG_SetDisplaySizePowerParams,
1668                                                 data);
1669         }
1670
1671         return 0;
1672 }
1673
1674
1675 static int cz_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time,
1676                         bool cc6_disable, bool pstate_disable, bool pstate_switch_disable)
1677 {
1678         struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
1679
1680         if (separation_time !=
1681                 hw_data->cc6_settings.cpu_pstate_separation_time
1682                 || cc6_disable !=
1683                 hw_data->cc6_settings.cpu_cc6_disable
1684                 || pstate_disable !=
1685                 hw_data->cc6_settings.cpu_pstate_disable
1686                 || pstate_switch_disable !=
1687                 hw_data->cc6_settings.nb_pstate_switch_disable) {
1688
1689                 hw_data->cc6_settings.cc6_setting_changed = true;
1690
1691                 hw_data->cc6_settings.cpu_pstate_separation_time =
1692                         separation_time;
1693                 hw_data->cc6_settings.cpu_cc6_disable =
1694                         cc6_disable;
1695                 hw_data->cc6_settings.cpu_pstate_disable =
1696                         pstate_disable;
1697                 hw_data->cc6_settings.nb_pstate_switch_disable =
1698                         pstate_switch_disable;
1699
1700         }
1701
1702         return 0;
1703 }
1704
1705 static int cz_get_dal_power_level(struct pp_hwmgr *hwmgr,
1706                 struct amd_pp_simple_clock_info *info)
1707 {
1708         uint32_t i;
1709         const struct phm_clock_voltage_dependency_table *table =
1710                         hwmgr->dyn_state.vddc_dep_on_dal_pwrl;
1711         const struct phm_clock_and_voltage_limits *limits =
1712                         &hwmgr->dyn_state.max_clock_voltage_on_ac;
1713
1714         info->engine_max_clock = limits->sclk;
1715         info->memory_max_clock = limits->mclk;
1716
1717         for (i = table->count - 1; i > 0; i--) {
1718                 if (limits->vddc >= table->entries[i].v) {
1719                         info->level = table->entries[i].clk;
1720                         return 0;
1721                 }
1722         }
1723         return -EINVAL;
1724 }
1725
1726 static int cz_force_clock_level(struct pp_hwmgr *hwmgr,
1727                 enum pp_clock_type type, int level)
1728 {
1729         if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1730                 return -EINVAL;
1731
1732         switch (type) {
1733         case PP_SCLK:
1734                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1735                                 PPSMC_MSG_SetSclkSoftMin,
1736                                 (1 << level));
1737                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1738                                 PPSMC_MSG_SetSclkSoftMax,
1739                                 (1 << level));
1740                 break;
1741         default:
1742                 break;
1743         }
1744
1745         return 0;
1746 }
1747
1748 static int cz_print_clock_levels(struct pp_hwmgr *hwmgr,
1749                 enum pp_clock_type type, char *buf)
1750 {
1751         struct phm_clock_voltage_dependency_table *sclk_table =
1752                         hwmgr->dyn_state.vddc_dependency_on_sclk;
1753         int i, now, size = 0;
1754
1755         switch (type) {
1756         case PP_SCLK:
1757                 now = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device,
1758                                 CGS_IND_REG__SMC,
1759                                 ixTARGET_AND_CURRENT_PROFILE_INDEX),
1760                                 TARGET_AND_CURRENT_PROFILE_INDEX,
1761                                 CURR_SCLK_INDEX);
1762
1763                 for (i = 0; i < sclk_table->count; i++)
1764                         size += sprintf(buf + size, "%d: %uMhz %s\n",
1765                                         i, sclk_table->entries[i].clk / 100,
1766                                         (i == now) ? "*" : "");
1767                 break;
1768         default:
1769                 break;
1770         }
1771         return size;
1772 }
1773
1774 static int cz_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
1775                                 PHM_PerformanceLevelDesignation designation, uint32_t index,
1776                                 PHM_PerformanceLevel *level)
1777 {
1778         const struct cz_power_state *ps;
1779         struct cz_hwmgr *data;
1780         uint32_t level_index;
1781         uint32_t i;
1782
1783         if (level == NULL || hwmgr == NULL || state == NULL)
1784                 return -EINVAL;
1785
1786         data = (struct cz_hwmgr *)(hwmgr->backend);
1787         ps = cast_const_PhwCzPowerState(state);
1788
1789         level_index = index > ps->level - 1 ? ps->level - 1 : index;
1790
1791         level->coreClock  = ps->levels[level_index].engineClock;
1792
1793         if (designation == PHM_PerformanceLevelDesignation_PowerContainment) {
1794                 for (i = 1; i < ps->level; i++) {
1795                         if (ps->levels[i].engineClock > data->dce_slow_sclk_threshold) {
1796                                 level->coreClock = ps->levels[i].engineClock;
1797                                 break;
1798                         }
1799                 }
1800         }
1801
1802         if (level_index == 0)
1803                 level->memory_clock = data->sys_info.nbp_memory_clock[CZ_NUM_NBPMEMORYCLOCK - 1];
1804         else
1805                 level->memory_clock = data->sys_info.nbp_memory_clock[0];
1806
1807         level->vddc = (cz_convert_8Bit_index_to_voltage(hwmgr, ps->levels[level_index].vddcIndex) + 2) / 4;
1808         level->nonLocalMemoryFreq = 0;
1809         level->nonLocalMemoryWidth = 0;
1810
1811         return 0;
1812 }
1813
1814 static int cz_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr,
1815         const struct pp_hw_power_state *state, struct pp_clock_info *clock_info)
1816 {
1817         const struct cz_power_state *ps = cast_const_PhwCzPowerState(state);
1818
1819         clock_info->min_eng_clk = ps->levels[0].engineClock / (1 << (ps->levels[0].ssDividerIndex));
1820         clock_info->max_eng_clk = ps->levels[ps->level - 1].engineClock / (1 << (ps->levels[ps->level - 1].ssDividerIndex));
1821
1822         return 0;
1823 }
1824
1825 static int cz_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type,
1826                                                 struct amd_pp_clocks *clocks)
1827 {
1828         struct cz_hwmgr *data = (struct cz_hwmgr *)(hwmgr->backend);
1829         int i;
1830         struct phm_clock_voltage_dependency_table *table;
1831
1832         clocks->count = cz_get_max_sclk_level(hwmgr);
1833         switch (type) {
1834         case amd_pp_disp_clock:
1835                 for (i = 0; i < clocks->count; i++)
1836                         clocks->clock[i] = data->sys_info.display_clock[i];
1837                 break;
1838         case amd_pp_sys_clock:
1839                 table = hwmgr->dyn_state.vddc_dependency_on_sclk;
1840                 for (i = 0; i < clocks->count; i++)
1841                         clocks->clock[i] = table->entries[i].clk;
1842                 break;
1843         case amd_pp_mem_clock:
1844                 clocks->count = CZ_NUM_NBPMEMORYCLOCK;
1845                 for (i = 0; i < clocks->count; i++)
1846                         clocks->clock[i] = data->sys_info.nbp_memory_clock[clocks->count - 1 - i];
1847                 break;
1848         default:
1849                 return -1;
1850         }
1851
1852         return 0;
1853 }
1854
1855 static int cz_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks)
1856 {
1857         struct phm_clock_voltage_dependency_table *table =
1858                                         hwmgr->dyn_state.vddc_dependency_on_sclk;
1859         unsigned long level;
1860         const struct phm_clock_and_voltage_limits *limits =
1861                         &hwmgr->dyn_state.max_clock_voltage_on_ac;
1862
1863         if ((NULL == table) || (table->count <= 0) || (clocks == NULL))
1864                 return -EINVAL;
1865
1866         level = cz_get_max_sclk_level(hwmgr) - 1;
1867
1868         if (level < table->count)
1869                 clocks->engine_max_clock = table->entries[level].clk;
1870         else
1871                 clocks->engine_max_clock = table->entries[table->count - 1].clk;
1872
1873         clocks->memory_max_clock = limits->mclk;
1874
1875         return 0;
1876 }
1877
1878 static const struct pp_hwmgr_func cz_hwmgr_funcs = {
1879         .backend_init = cz_hwmgr_backend_init,
1880         .backend_fini = cz_hwmgr_backend_fini,
1881         .asic_setup = NULL,
1882         .apply_state_adjust_rules = cz_apply_state_adjust_rules,
1883         .force_dpm_level = cz_dpm_force_dpm_level,
1884         .get_power_state_size = cz_get_power_state_size,
1885         .powerdown_uvd = cz_dpm_powerdown_uvd,
1886         .powergate_uvd = cz_dpm_powergate_uvd,
1887         .powergate_vce = cz_dpm_powergate_vce,
1888         .get_mclk = cz_dpm_get_mclk,
1889         .get_sclk = cz_dpm_get_sclk,
1890         .patch_boot_state = cz_dpm_patch_boot_state,
1891         .get_pp_table_entry = cz_dpm_get_pp_table_entry,
1892         .get_num_of_pp_table_entries = cz_dpm_get_num_of_pp_table_entries,
1893         .print_current_perforce_level = cz_print_current_perforce_level,
1894         .set_cpu_power_state = cz_set_cpu_power_state,
1895         .store_cc6_data = cz_store_cc6_data,
1896         .force_clock_level = cz_force_clock_level,
1897         .print_clock_levels = cz_print_clock_levels,
1898         .get_dal_power_level = cz_get_dal_power_level,
1899         .get_performance_level = cz_get_performance_level,
1900         .get_current_shallow_sleep_clocks = cz_get_current_shallow_sleep_clocks,
1901         .get_clock_by_type = cz_get_clock_by_type,
1902         .get_max_high_clocks = cz_get_max_high_clocks,
1903 };
1904
1905 int cz_hwmgr_init(struct pp_hwmgr *hwmgr)
1906 {
1907         struct cz_hwmgr *cz_hwmgr;
1908         int ret = 0;
1909
1910         cz_hwmgr = kzalloc(sizeof(struct cz_hwmgr), GFP_KERNEL);
1911         if (cz_hwmgr == NULL)
1912                 return -ENOMEM;
1913
1914         hwmgr->backend = cz_hwmgr;
1915         hwmgr->hwmgr_func = &cz_hwmgr_funcs;
1916         hwmgr->pptable_func = &pptable_funcs;
1917         return ret;
1918 }