drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/types.h>
  24 #include <linux/kernel.h>
  25 #include <linux/slab.h>
  26 #include "atom-types.h"
  27 #include "atombios.h"
  28 #include "processpptables.h"
  29 #include "pp_debug.h"
  30 #include "cgs_common.h"
  31 #include "smu/smu_8_0_d.h"
  32 #include "smu8_fusion.h"
  33 #include "smu/smu_8_0_sh_mask.h"
  34 #include "smumgr.h"
  35 #include "hwmgr.h"
  36 #include "hardwaremanager.h"
  37 #include "cz_ppsmc.h"
  38 #include "cz_hwmgr.h"
  39 #include "power_state.h"
  40 #include "cz_clockpowergating.h"
  41 #include "pp_debug.h"
  42
  43 #define ixSMUSVI_NB_CURRENTVID 0xD8230044
  44 #define CURRENT_NB_VID_MASK 0xff000000
  45 #define CURRENT_NB_VID__SHIFT 24
  46 #define ixSMUSVI_GFX_CURRENTVID  0xD8230048
  47 #define CURRENT_GFX_VID_MASK 0xff000000
  48 #define CURRENT_GFX_VID__SHIFT 24
  49
  50 static const unsigned long PhwCz_Magic = (unsigned long) PHM_Cz_Magic;
  51
  52 static struct cz_power_state *cast_PhwCzPowerState(struct pp_hw_power_state *hw_ps)
  53 {
  54         if (PhwCz_Magic != hw_ps->magic)
  55                 return NULL;
  56
  57         return (struct cz_power_state *)hw_ps;
  58 }
  59
  60 static const struct cz_power_state *cast_const_PhwCzPowerState(
  61                                 const struct pp_hw_power_state *hw_ps)
  62 {
  63         if (PhwCz_Magic != hw_ps->magic)
  64                 return NULL;
  65
  66         return (struct cz_power_state *)hw_ps;
  67 }
  68
  69 uint32_t cz_get_eclk_level(struct pp_hwmgr *hwmgr,
  70                                         uint32_t clock, uint32_t msg)
  71 {
  72         int i = 0;
  73         struct phm_vce_clock_voltage_dependency_table *ptable =
  74                 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
  75
  76         switch (msg) {
  77         case PPSMC_MSG_SetEclkSoftMin:
  78         case PPSMC_MSG_SetEclkHardMin:
  79                 for (i = 0; i < (int)ptable->count; i++) {
  80                         if (clock <= ptable->entries[i].ecclk)
  81                                 break;
  82                 }
  83                 break;
  84
  85         case PPSMC_MSG_SetEclkSoftMax:
  86         case PPSMC_MSG_SetEclkHardMax:
  87                 for (i = ptable->count - 1; i >= 0; i--) {
  88                         if (clock >= ptable->entries[i].ecclk)
  89                                 break;
  90                 }
  91                 break;
  92
  93         default:
  94                 break;
  95         }
  96
  97         return i;
  98 }
  99
 100 static uint32_t cz_get_sclk_level(struct pp_hwmgr *hwmgr,
 101                                 uint32_t clock, uint32_t msg)
 102 {
 103         int i = 0;
 104         struct phm_clock_voltage_dependency_table *table =
 105                                 hwmgr->dyn_state.vddc_dependency_on_sclk;
 106
 107         switch (msg) {
 108         case PPSMC_MSG_SetSclkSoftMin:
 109         case PPSMC_MSG_SetSclkHardMin:
 110                 for (i = 0; i < (int)table->count; i++) {
 111                         if (clock <= table->entries[i].clk)
 112                                 break;
 113                 }
 114                 break;
 115
 116         case PPSMC_MSG_SetSclkSoftMax:
 117         case PPSMC_MSG_SetSclkHardMax:
 118                 for (i = table->count - 1; i >= 0; i--) {
 119                         if (clock >= table->entries[i].clk)
 120                                 break;
 121                 }
 122                 break;
 123
 124         default:
 125                 break;
 126         }
 127         return i;
 128 }
 129
 130 static uint32_t cz_get_uvd_level(struct pp_hwmgr *hwmgr,
 131                                         uint32_t clock, uint32_t msg)
 132 {
 133         int i = 0;
 134         struct phm_uvd_clock_voltage_dependency_table *ptable =
 135                 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
 136
 137         switch (msg) {
 138         case PPSMC_MSG_SetUvdSoftMin:
 139         case PPSMC_MSG_SetUvdHardMin:
 140                 for (i = 0; i < (int)ptable->count; i++) {
 141                         if (clock <= ptable->entries[i].vclk)
 142                                 break;
 143                 }
 144                 break;
 145
 146         case PPSMC_MSG_SetUvdSoftMax:
 147         case PPSMC_MSG_SetUvdHardMax:
 148                 for (i = ptable->count - 1; i >= 0; i--) {
 149                         if (clock >= ptable->entries[i].vclk)
 150                                 break;
 151                 }
 152                 break;
 153
 154         default:
 155                 break;
 156         }
 157
 158         return i;
 159 }
 160
 161 static uint32_t cz_get_max_sclk_level(struct pp_hwmgr *hwmgr)
 162 {
 163         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 164
 165         if (cz_hwmgr->max_sclk_level == 0) {
 166                 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxSclkLevel);
 167                 cz_hwmgr->max_sclk_level = smum_get_argument(hwmgr->smumgr) + 1;
 168         }
 169
 170         return cz_hwmgr->max_sclk_level;
 171 }
 172
 173 static int cz_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
 174 {
 175         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 176         uint32_t i;
 177         struct cgs_system_info sys_info = {0};
 178         int result;
 179
 180         cz_hwmgr->gfx_ramp_step = 256*25/100;
 181
 182         cz_hwmgr->gfx_ramp_delay = 1; /* by default, we delay 1us */
 183
 184         for (i = 0; i < CZ_MAX_HARDWARE_POWERLEVELS; i++)
 185                 cz_hwmgr->activity_target[i] = CZ_AT_DFLT;
 186
 187         cz_hwmgr->mgcg_cgtt_local0 = 0x00000000;
 188         cz_hwmgr->mgcg_cgtt_local1 = 0x00000000;
 189
 190         cz_hwmgr->clock_slow_down_freq = 25000;
 191
 192         cz_hwmgr->skip_clock_slow_down = 1;
 193
 194         cz_hwmgr->enable_nb_ps_policy = 1; /* disable until UNB is ready, Enabled */
 195
 196         cz_hwmgr->voltage_drop_in_dce_power_gating = 0; /* disable until fully verified */
 197
 198         cz_hwmgr->voting_rights_clients = 0x00C00033;
 199
 200         cz_hwmgr->static_screen_threshold = 8;
 201
 202         cz_hwmgr->ddi_power_gating_disabled = 0;
 203
 204         cz_hwmgr->bapm_enabled = 1;
 205
 206         cz_hwmgr->voltage_drop_threshold = 0;
 207
 208         cz_hwmgr->gfx_power_gating_threshold = 500;
 209
 210         cz_hwmgr->vce_slow_sclk_threshold = 20000;
 211
 212         cz_hwmgr->dce_slow_sclk_threshold = 30000;
 213
 214         cz_hwmgr->disable_driver_thermal_policy = 1;
 215
 216         cz_hwmgr->disable_nb_ps3_in_battery = 0;
 217
 218         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 219                                                         PHM_PlatformCaps_ABM);
 220
 221         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 222                                     PHM_PlatformCaps_NonABMSupportInPPLib);
 223
 224         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 225                                            PHM_PlatformCaps_SclkDeepSleep);
 226
 227         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 228                                         PHM_PlatformCaps_DynamicM3Arbiter);
 229
 230         cz_hwmgr->override_dynamic_mgpg = 1;
 231
 232         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 233                                   PHM_PlatformCaps_DynamicPatchPowerState);
 234
 235         cz_hwmgr->thermal_auto_throttling_treshold = 0;
 236
 237         cz_hwmgr->tdr_clock = 0;
 238
 239         cz_hwmgr->disable_gfx_power_gating_in_uvd = 0;
 240
 241         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 242                                         PHM_PlatformCaps_DynamicUVDState);
 243
 244         cz_hwmgr->cc6_settings.cpu_cc6_disable = false;
 245         cz_hwmgr->cc6_settings.cpu_pstate_disable = false;
 246         cz_hwmgr->cc6_settings.nb_pstate_switch_disable = false;
 247         cz_hwmgr->cc6_settings.cpu_pstate_separation_time = 0;
 248
 249         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 250                                    PHM_PlatformCaps_DisableVoltageIsland);
 251
 252         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 253                       PHM_PlatformCaps_UVDPowerGating);
 254         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 255                       PHM_PlatformCaps_VCEPowerGating);
 256         sys_info.size = sizeof(struct cgs_system_info);
 257         sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS;
 258         result = cgs_query_system_info(hwmgr->device, &sys_info);
 259         if (!result) {
 260                 if (sys_info.value & AMD_PG_SUPPORT_UVD)
 261                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 262                                       PHM_PlatformCaps_UVDPowerGating);
 263                 if (sys_info.value & AMD_PG_SUPPORT_VCE)
 264                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 265                                       PHM_PlatformCaps_VCEPowerGating);
 266         }
 267
 268         return 0;
 269 }
 270
 271 static uint32_t cz_convert_8Bit_index_to_voltage(
 272                         struct pp_hwmgr *hwmgr, uint16_t voltage)
 273 {
 274         return 6200 - (voltage * 25);
 275 }
 276
 277 static int cz_construct_max_power_limits_table(struct pp_hwmgr *hwmgr,
 278                         struct phm_clock_and_voltage_limits *table)
 279 {
 280         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)hwmgr->backend;
 281         struct cz_sys_info *sys_info = &cz_hwmgr->sys_info;
 282         struct phm_clock_voltage_dependency_table *dep_table =
 283                                 hwmgr->dyn_state.vddc_dependency_on_sclk;
 284
 285         if (dep_table->count > 0) {
 286                 table->sclk = dep_table->entries[dep_table->count-1].clk;
 287                 table->vddc = cz_convert_8Bit_index_to_voltage(hwmgr,
 288                    (uint16_t)dep_table->entries[dep_table->count-1].v);
 289         }
 290         table->mclk = sys_info->nbp_memory_clock[0];
 291         return 0;
 292 }
 293
 294 static int cz_init_dynamic_state_adjustment_rule_settings(
 295                         struct pp_hwmgr *hwmgr,
 296                         ATOM_CLK_VOLT_CAPABILITY *disp_voltage_table)
 297 {
 298         uint32_t table_size =
 299                 sizeof(struct phm_clock_voltage_dependency_table) +
 300                 (7 * sizeof(struct phm_clock_voltage_dependency_record));
 301
 302         struct phm_clock_voltage_dependency_table *table_clk_vlt =
 303                                         kzalloc(table_size, GFP_KERNEL);
 304
 305         if (NULL == table_clk_vlt) {
 306                 printk(KERN_ERR "[ powerplay ] Can not allocate memory!\n");
 307                 return -ENOMEM;
 308         }
 309
 310         table_clk_vlt->count = 8;
 311         table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_0;
 312         table_clk_vlt->entries[0].v = 0;
 313         table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_1;
 314         table_clk_vlt->entries[1].v = 1;
 315         table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_2;
 316         table_clk_vlt->entries[2].v = 2;
 317         table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_3;
 318         table_clk_vlt->entries[3].v = 3;
 319         table_clk_vlt->entries[4].clk = PP_DAL_POWERLEVEL_4;
 320         table_clk_vlt->entries[4].v = 4;
 321         table_clk_vlt->entries[5].clk = PP_DAL_POWERLEVEL_5;
 322         table_clk_vlt->entries[5].v = 5;
 323         table_clk_vlt->entries[6].clk = PP_DAL_POWERLEVEL_6;
 324         table_clk_vlt->entries[6].v = 6;
 325         table_clk_vlt->entries[7].clk = PP_DAL_POWERLEVEL_7;
 326         table_clk_vlt->entries[7].v = 7;
 327         hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
 328
 329         return 0;
 330 }
 331
 332 static int cz_get_system_info_data(struct pp_hwmgr *hwmgr)
 333 {
 334         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)hwmgr->backend;
 335         ATOM_INTEGRATED_SYSTEM_INFO_V1_9 *info = NULL;
 336         uint32_t i;
 337         int result = 0;
 338         uint8_t frev, crev;
 339         uint16_t size;
 340
 341         info = (ATOM_INTEGRATED_SYSTEM_INFO_V1_9 *) cgs_atom_get_data_table(
 342                         hwmgr->device,
 343                         GetIndexIntoMasterTable(DATA, IntegratedSystemInfo),
 344                         &size, &frev, &crev);
 345
 346         if (crev != 9) {
 347                 printk(KERN_ERR "[ powerplay ] Unsupported IGP table: %d %d\n", frev, crev);
 348                 return -EINVAL;
 349         }
 350
 351         if (info == NULL) {
 352                 printk(KERN_ERR "[ powerplay ] Could not retrieve the Integrated System Info Table!\n");
 353                 return -EINVAL;
 354         }
 355
 356         cz_hwmgr->sys_info.bootup_uma_clock =
 357                                    le32_to_cpu(info->ulBootUpUMAClock);
 358
 359         cz_hwmgr->sys_info.bootup_engine_clock =
 360                                 le32_to_cpu(info->ulBootUpEngineClock);
 361
 362         cz_hwmgr->sys_info.dentist_vco_freq =
 363                                    le32_to_cpu(info->ulDentistVCOFreq);
 364
 365         cz_hwmgr->sys_info.system_config =
 366                                      le32_to_cpu(info->ulSystemConfig);
 367
 368         cz_hwmgr->sys_info.bootup_nb_voltage_index =
 369                                   le16_to_cpu(info->usBootUpNBVoltage);
 370
 371         cz_hwmgr->sys_info.htc_hyst_lmt =
 372                         (info->ucHtcHystLmt == 0) ? 5 : info->ucHtcHystLmt;
 373
 374         cz_hwmgr->sys_info.htc_tmp_lmt =
 375                         (info->ucHtcTmpLmt == 0) ? 203 : info->ucHtcTmpLmt;
 376
 377         if (cz_hwmgr->sys_info.htc_tmp_lmt <=
 378                         cz_hwmgr->sys_info.htc_hyst_lmt) {
 379                 printk(KERN_ERR "[ powerplay ] The htcTmpLmt should be larger than htcHystLmt.\n");
 380                 return -EINVAL;
 381         }
 382
 383         cz_hwmgr->sys_info.nb_dpm_enable =
 384                                 cz_hwmgr->enable_nb_ps_policy &&
 385                                 (le32_to_cpu(info->ulSystemConfig) >> 3 & 0x1);
 386
 387         for (i = 0; i < CZ_NUM_NBPSTATES; i++) {
 388                 if (i < CZ_NUM_NBPMEMORYCLOCK) {
 389                         cz_hwmgr->sys_info.nbp_memory_clock[i] =
 390                           le32_to_cpu(info->ulNbpStateMemclkFreq[i]);
 391                 }
 392                 cz_hwmgr->sys_info.nbp_n_clock[i] =
 393                             le32_to_cpu(info->ulNbpStateNClkFreq[i]);
 394         }
 395
 396         for (i = 0; i < MAX_DISPLAY_CLOCK_LEVEL; i++) {
 397                 cz_hwmgr->sys_info.display_clock[i] =
 398                                         le32_to_cpu(info->sDispClkVoltageMapping[i].ulMaximumSupportedCLK);
 399         }
 400
 401         /* Here use 4 levels, make sure not exceed */
 402         for (i = 0; i < CZ_NUM_NBPSTATES; i++) {
 403                 cz_hwmgr->sys_info.nbp_voltage_index[i] =
 404                              le16_to_cpu(info->usNBPStateVoltage[i]);
 405         }
 406
 407         if (!cz_hwmgr->sys_info.nb_dpm_enable) {
 408                 for (i = 1; i < CZ_NUM_NBPSTATES; i++) {
 409                         if (i < CZ_NUM_NBPMEMORYCLOCK) {
 410                                 cz_hwmgr->sys_info.nbp_memory_clock[i] =
 411                                     cz_hwmgr->sys_info.nbp_memory_clock[0];
 412                         }
 413                         cz_hwmgr->sys_info.nbp_n_clock[i] =
 414                                     cz_hwmgr->sys_info.nbp_n_clock[0];
 415                         cz_hwmgr->sys_info.nbp_voltage_index[i] =
 416                                     cz_hwmgr->sys_info.nbp_voltage_index[0];
 417                 }
 418         }
 419
 420         if (le32_to_cpu(info->ulGPUCapInfo) &
 421                 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS) {
 422                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 423                                     PHM_PlatformCaps_EnableDFSBypass);
 424         }
 425
 426         cz_hwmgr->sys_info.uma_channel_number = info->ucUMAChannelNumber;
 427
 428         cz_construct_max_power_limits_table (hwmgr,
 429                                     &hwmgr->dyn_state.max_clock_voltage_on_ac);
 430
 431         cz_init_dynamic_state_adjustment_rule_settings(hwmgr,
 432                                     &info->sDISPCLK_Voltage[0]);
 433
 434         return result;
 435 }
 436
 437 static int cz_construct_boot_state(struct pp_hwmgr *hwmgr)
 438 {
 439         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 440
 441         cz_hwmgr->boot_power_level.engineClock =
 442                                 cz_hwmgr->sys_info.bootup_engine_clock;
 443
 444         cz_hwmgr->boot_power_level.vddcIndex =
 445                         (uint8_t)cz_hwmgr->sys_info.bootup_nb_voltage_index;
 446
 447         cz_hwmgr->boot_power_level.dsDividerIndex = 0;
 448
 449         cz_hwmgr->boot_power_level.ssDividerIndex = 0;
 450
 451         cz_hwmgr->boot_power_level.allowGnbSlow = 1;
 452
 453         cz_hwmgr->boot_power_level.forceNBPstate = 0;
 454
 455         cz_hwmgr->boot_power_level.hysteresis_up = 0;
 456
 457         cz_hwmgr->boot_power_level.numSIMDToPowerDown = 0;
 458
 459         cz_hwmgr->boot_power_level.display_wm = 0;
 460
 461         cz_hwmgr->boot_power_level.vce_wm = 0;
 462
 463         return 0;
 464 }
 465
 466 static int cz_tf_reset_active_process_mask(struct pp_hwmgr *hwmgr, void *input,
 467                                         void *output, void *storage, int result)
 468 {
 469         return 0;
 470 }
 471
 472 static int cz_tf_upload_pptable_to_smu(struct pp_hwmgr *hwmgr, void *input,
 473                                        void *output, void *storage, int result)
 474 {
 475         struct SMU8_Fusion_ClkTable *clock_table;
 476         int ret;
 477         uint32_t i;
 478         void *table = NULL;
 479         pp_atomctrl_clock_dividers_kong dividers;
 480
 481         struct phm_clock_voltage_dependency_table *vddc_table =
 482                 hwmgr->dyn_state.vddc_dependency_on_sclk;
 483         struct phm_clock_voltage_dependency_table *vdd_gfx_table =
 484                 hwmgr->dyn_state.vdd_gfx_dependency_on_sclk;
 485         struct phm_acp_clock_voltage_dependency_table *acp_table =
 486                 hwmgr->dyn_state.acp_clock_voltage_dependency_table;
 487         struct phm_uvd_clock_voltage_dependency_table *uvd_table =
 488                 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
 489         struct phm_vce_clock_voltage_dependency_table *vce_table =
 490                 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
 491
 492         if (!hwmgr->need_pp_table_upload)
 493                 return 0;
 494
 495         ret = smum_download_powerplay_table(hwmgr->smumgr, &table);
 496
 497         PP_ASSERT_WITH_CODE((0 == ret && NULL != table),
 498                             "Fail to get clock table from SMU!", return -EINVAL;);
 499
 500         clock_table = (struct SMU8_Fusion_ClkTable *)table;
 501
 502         /* patch clock table */
 503         PP_ASSERT_WITH_CODE((vddc_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
 504                             "Dependency table entry exceeds max limit!", return -EINVAL;);
 505         PP_ASSERT_WITH_CODE((vdd_gfx_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
 506                             "Dependency table entry exceeds max limit!", return -EINVAL;);
 507         PP_ASSERT_WITH_CODE((acp_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
 508                             "Dependency table entry exceeds max limit!", return -EINVAL;);
 509         PP_ASSERT_WITH_CODE((uvd_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
 510                             "Dependency table entry exceeds max limit!", return -EINVAL;);
 511         PP_ASSERT_WITH_CODE((vce_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
 512                             "Dependency table entry exceeds max limit!", return -EINVAL;);
 513
 514         for (i = 0; i < CZ_MAX_HARDWARE_POWERLEVELS; i++) {
 515
 516                 /* vddc_sclk */
 517                 clock_table->SclkBreakdownTable.ClkLevel[i].GnbVid =
 518                         (i < vddc_table->count) ? (uint8_t)vddc_table->entries[i].v : 0;
 519                 clock_table->SclkBreakdownTable.ClkLevel[i].Frequency =
 520                         (i < vddc_table->count) ? vddc_table->entries[i].clk : 0;
 521
 522                 atomctrl_get_engine_pll_dividers_kong(hwmgr,
 523                                                       clock_table->SclkBreakdownTable.ClkLevel[i].Frequency,
 524                                                       &dividers);
 525
 526                 clock_table->SclkBreakdownTable.ClkLevel[i].DfsDid =
 527                         (uint8_t)dividers.pll_post_divider;
 528
 529                 /* vddgfx_sclk */
 530                 clock_table->SclkBreakdownTable.ClkLevel[i].GfxVid =
 531                         (i < vdd_gfx_table->count) ? (uint8_t)vdd_gfx_table->entries[i].v : 0;
 532
 533                 /* acp breakdown */
 534                 clock_table->AclkBreakdownTable.ClkLevel[i].GfxVid =
 535                         (i < acp_table->count) ? (uint8_t)acp_table->entries[i].v : 0;
 536                 clock_table->AclkBreakdownTable.ClkLevel[i].Frequency =
 537                         (i < acp_table->count) ? acp_table->entries[i].acpclk : 0;
 538
 539                 atomctrl_get_engine_pll_dividers_kong(hwmgr,
 540                                                       clock_table->AclkBreakdownTable.ClkLevel[i].Frequency,
 541                                                       &dividers);
 542
 543                 clock_table->AclkBreakdownTable.ClkLevel[i].DfsDid =
 544                         (uint8_t)dividers.pll_post_divider;
 545
 546
 547                 /* uvd breakdown */
 548                 clock_table->VclkBreakdownTable.ClkLevel[i].GfxVid =
 549                         (i < uvd_table->count) ? (uint8_t)uvd_table->entries[i].v : 0;
 550                 clock_table->VclkBreakdownTable.ClkLevel[i].Frequency =
 551                         (i < uvd_table->count) ? uvd_table->entries[i].vclk : 0;
 552
 553                 atomctrl_get_engine_pll_dividers_kong(hwmgr,
 554                                                       clock_table->VclkBreakdownTable.ClkLevel[i].Frequency,
 555                                                       &dividers);
 556
 557                 clock_table->VclkBreakdownTable.ClkLevel[i].DfsDid =
 558                         (uint8_t)dividers.pll_post_divider;
 559
 560                 clock_table->DclkBreakdownTable.ClkLevel[i].GfxVid =
 561                         (i < uvd_table->count) ? (uint8_t)uvd_table->entries[i].v : 0;
 562                 clock_table->DclkBreakdownTable.ClkLevel[i].Frequency =
 563                         (i < uvd_table->count) ? uvd_table->entries[i].dclk : 0;
 564
 565                 atomctrl_get_engine_pll_dividers_kong(hwmgr,
 566                                                       clock_table->DclkBreakdownTable.ClkLevel[i].Frequency,
 567                                                       &dividers);
 568
 569                 clock_table->DclkBreakdownTable.ClkLevel[i].DfsDid =
 570                         (uint8_t)dividers.pll_post_divider;
 571
 572                 /* vce breakdown */
 573                 clock_table->EclkBreakdownTable.ClkLevel[i].GfxVid =
 574                         (i < vce_table->count) ? (uint8_t)vce_table->entries[i].v : 0;
 575                 clock_table->EclkBreakdownTable.ClkLevel[i].Frequency =
 576                         (i < vce_table->count) ? vce_table->entries[i].ecclk : 0;
 577
 578
 579                 atomctrl_get_engine_pll_dividers_kong(hwmgr,
 580                                                       clock_table->EclkBreakdownTable.ClkLevel[i].Frequency,
 581                                                       &dividers);
 582
 583                 clock_table->EclkBreakdownTable.ClkLevel[i].DfsDid =
 584                         (uint8_t)dividers.pll_post_divider;
 585
 586         }
 587         ret = smum_upload_powerplay_table(hwmgr->smumgr);
 588
 589         return ret;
 590 }
 591
 592 static int cz_tf_init_sclk_limit(struct pp_hwmgr *hwmgr, void *input,
 593                                  void *output, void *storage, int result)
 594 {
 595         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 596         struct phm_clock_voltage_dependency_table *table =
 597                                         hwmgr->dyn_state.vddc_dependency_on_sclk;
 598         unsigned long clock = 0, level;
 599
 600         if (NULL == table || table->count <= 0)
 601                 return -EINVAL;
 602
 603         cz_hwmgr->sclk_dpm.soft_min_clk = table->entries[0].clk;
 604         cz_hwmgr->sclk_dpm.hard_min_clk = table->entries[0].clk;
 605
 606         level = cz_get_max_sclk_level(hwmgr) - 1;
 607
 608         if (level < table->count)
 609                 clock = table->entries[level].clk;
 610         else
 611                 clock = table->entries[table->count - 1].clk;
 612
 613         cz_hwmgr->sclk_dpm.soft_max_clk = clock;
 614         cz_hwmgr->sclk_dpm.hard_max_clk = clock;
 615
 616         return 0;
 617 }
 618
 619 static int cz_tf_init_uvd_limit(struct pp_hwmgr *hwmgr, void *input,
 620                                 void *output, void *storage, int result)
 621 {
 622         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 623         struct phm_uvd_clock_voltage_dependency_table *table =
 624                                 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
 625         unsigned long clock = 0, level;
 626
 627         if (NULL == table || table->count <= 0)
 628                 return -EINVAL;
 629
 630         cz_hwmgr->uvd_dpm.soft_min_clk = 0;
 631         cz_hwmgr->uvd_dpm.hard_min_clk = 0;
 632
 633         smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxUvdLevel);
 634         level = smum_get_argument(hwmgr->smumgr);
 635
 636         if (level < table->count)
 637                 clock = table->entries[level].vclk;
 638         else
 639                 clock = table->entries[table->count - 1].vclk;
 640
 641         cz_hwmgr->uvd_dpm.soft_max_clk = clock;
 642         cz_hwmgr->uvd_dpm.hard_max_clk = clock;
 643
 644         return 0;
 645 }
 646
 647 static int cz_tf_init_vce_limit(struct pp_hwmgr *hwmgr, void *input,
 648                                 void *output, void *storage, int result)
 649 {
 650         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 651         struct phm_vce_clock_voltage_dependency_table *table =
 652                                 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
 653         unsigned long clock = 0, level;
 654
 655         if (NULL == table || table->count <= 0)
 656                 return -EINVAL;
 657
 658         cz_hwmgr->vce_dpm.soft_min_clk = 0;
 659         cz_hwmgr->vce_dpm.hard_min_clk = 0;
 660
 661         smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxEclkLevel);
 662         level = smum_get_argument(hwmgr->smumgr);
 663
 664         if (level < table->count)
 665                 clock = table->entries[level].ecclk;
 666         else
 667                 clock = table->entries[table->count - 1].ecclk;
 668
 669         cz_hwmgr->vce_dpm.soft_max_clk = clock;
 670         cz_hwmgr->vce_dpm.hard_max_clk = clock;
 671
 672         return 0;
 673 }
 674
 675 static int cz_tf_init_acp_limit(struct pp_hwmgr *hwmgr, void *input,
 676                                 void *output, void *storage, int result)
 677 {
 678         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 679         struct phm_acp_clock_voltage_dependency_table *table =
 680                                 hwmgr->dyn_state.acp_clock_voltage_dependency_table;
 681         unsigned long clock = 0, level;
 682
 683         if (NULL == table || table->count <= 0)
 684                 return -EINVAL;
 685
 686         cz_hwmgr->acp_dpm.soft_min_clk = 0;
 687         cz_hwmgr->acp_dpm.hard_min_clk = 0;
 688
 689         smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxAclkLevel);
 690         level = smum_get_argument(hwmgr->smumgr);
 691
 692         if (level < table->count)
 693                 clock = table->entries[level].acpclk;
 694         else
 695                 clock = table->entries[table->count - 1].acpclk;
 696
 697         cz_hwmgr->acp_dpm.soft_max_clk = clock;
 698         cz_hwmgr->acp_dpm.hard_max_clk = clock;
 699         return 0;
 700 }
 701
 702 static int cz_tf_init_power_gate_state(struct pp_hwmgr *hwmgr, void *input,
 703                                 void *output, void *storage, int result)
 704 {
 705         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 706
 707         cz_hwmgr->uvd_power_gated = false;
 708         cz_hwmgr->vce_power_gated = false;
 709         cz_hwmgr->samu_power_gated = false;
 710         cz_hwmgr->acp_power_gated = false;
 711         cz_hwmgr->pgacpinit = true;
 712
 713         return 0;
 714 }
 715
 716 static int cz_tf_init_sclk_threshold(struct pp_hwmgr *hwmgr, void *input,
 717                                 void *output, void *storage, int result)
 718 {
 719         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 720
 721         cz_hwmgr->low_sclk_interrupt_threshold = 0;
 722
 723         return 0;
 724 }
 725 static int cz_tf_update_sclk_limit(struct pp_hwmgr *hwmgr,
 726                                         void *input, void *output,
 727                                         void *storage, int result)
 728 {
 729         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 730         struct phm_clock_voltage_dependency_table *table =
 731                                         hwmgr->dyn_state.vddc_dependency_on_sclk;
 732
 733         unsigned long clock = 0;
 734         unsigned long level;
 735         unsigned long stable_pstate_sclk;
 736         unsigned long percentage;
 737
 738         cz_hwmgr->sclk_dpm.soft_min_clk = table->entries[0].clk;
 739         level = cz_get_max_sclk_level(hwmgr) - 1;
 740
 741         if (level < table->count)
 742                 cz_hwmgr->sclk_dpm.soft_max_clk  = table->entries[level].clk;
 743         else
 744                 cz_hwmgr->sclk_dpm.soft_max_clk  = table->entries[table->count - 1].clk;
 745
 746         clock = hwmgr->display_config.min_core_set_clock;
 747         if (clock == 0)
 748                 printk(KERN_ERR "[ powerplay ] min_core_set_clock not set\n");
 749
 750         if (cz_hwmgr->sclk_dpm.hard_min_clk != clock) {
 751                 cz_hwmgr->sclk_dpm.hard_min_clk = clock;
 752
 753                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 754                                                 PPSMC_MSG_SetSclkHardMin,
 755                                                  cz_get_sclk_level(hwmgr,
 756                                         cz_hwmgr->sclk_dpm.hard_min_clk,
 757                                              PPSMC_MSG_SetSclkHardMin));
 758         }
 759
 760         clock = cz_hwmgr->sclk_dpm.soft_min_clk;
 761
 762         /* update minimum clocks for Stable P-State feature */
 763         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 764                                      PHM_PlatformCaps_StablePState)) {
 765                 percentage = 75;
 766                 /*Sclk - calculate sclk value based on percentage and find FLOOR sclk from VddcDependencyOnSCLK table  */
 767                 stable_pstate_sclk = (hwmgr->dyn_state.max_clock_voltage_on_ac.mclk *
 768                                         percentage) / 100;
 769
 770                 if (clock < stable_pstate_sclk)
 771                         clock = stable_pstate_sclk;
 772         } else {
 773                 if (clock < hwmgr->gfx_arbiter.sclk)
 774                         clock = hwmgr->gfx_arbiter.sclk;
 775         }
 776
 777         if (cz_hwmgr->sclk_dpm.soft_min_clk != clock) {
 778                 cz_hwmgr->sclk_dpm.soft_min_clk = clock;
 779                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 780                                                 PPSMC_MSG_SetSclkSoftMin,
 781                                                 cz_get_sclk_level(hwmgr,
 782                                         cz_hwmgr->sclk_dpm.soft_min_clk,
 783                                              PPSMC_MSG_SetSclkSoftMin));
 784         }
 785
 786         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 787                                     PHM_PlatformCaps_StablePState) &&
 788                          cz_hwmgr->sclk_dpm.soft_max_clk != clock) {
 789                 cz_hwmgr->sclk_dpm.soft_max_clk = clock;
 790                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 791                                                 PPSMC_MSG_SetSclkSoftMax,
 792                                                 cz_get_sclk_level(hwmgr,
 793                                         cz_hwmgr->sclk_dpm.soft_max_clk,
 794                                         PPSMC_MSG_SetSclkSoftMax));
 795         }
 796
 797         return 0;
 798 }
 799
 800 static int cz_tf_set_deep_sleep_sclk_threshold(struct pp_hwmgr *hwmgr,
 801                                         void *input, void *output,
 802                                         void *storage, int result)
 803 {
 804         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 805                                 PHM_PlatformCaps_SclkDeepSleep)) {
 806                 uint32_t clks = hwmgr->display_config.min_core_set_clock_in_sr;
 807                 if (clks == 0)
 808                         clks = CZ_MIN_DEEP_SLEEP_SCLK;
 809
 810                 PP_DBG_LOG("Setting Deep Sleep Clock: %d\n", clks);
 811
 812                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 813                                 PPSMC_MSG_SetMinDeepSleepSclk,
 814                                 clks);
 815         }
 816
 817         return 0;
 818 }
 819
 820 static int cz_tf_set_watermark_threshold(struct pp_hwmgr *hwmgr,
 821                                         void *input, void *output,
 822                                         void *storage, int result)
 823 {
 824         struct cz_hwmgr *cz_hwmgr =
 825                                   (struct cz_hwmgr *)(hwmgr->backend);
 826
 827         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 828                                         PPSMC_MSG_SetWatermarkFrequency,
 829                                       cz_hwmgr->sclk_dpm.soft_max_clk);
 830
 831         return 0;
 832 }
 833
 834 static int cz_tf_set_enabled_levels(struct pp_hwmgr *hwmgr,
 835                                         void *input, void *output,
 836                                         void *storage, int result)
 837 {
 838         return 0;
 839 }
 840
 841
 842 static int cz_tf_enable_nb_dpm(struct pp_hwmgr *hwmgr,
 843                                         void *input, void *output,
 844                                         void *storage, int result)
 845 {
 846         int ret = 0;
 847
 848         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 849         unsigned long dpm_features = 0;
 850
 851         if (!cz_hwmgr->is_nb_dpm_enabled) {
 852                 PP_DBG_LOG("enabling ALL SMU features.\n");
 853                 dpm_features |= NB_DPM_MASK;
 854                 ret = smum_send_msg_to_smc_with_parameter(
 855                                                              hwmgr->smumgr,
 856                                          PPSMC_MSG_EnableAllSmuFeatures,
 857                                                              dpm_features);
 858                 if (ret == 0)
 859                         cz_hwmgr->is_nb_dpm_enabled = true;
 860         }
 861
 862         return ret;
 863 }
 864
 865 static int cz_nbdpm_pstate_enable_disable(struct pp_hwmgr *hwmgr, bool enable, bool lock)
 866 {
 867         struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
 868
 869         if (hw_data->is_nb_dpm_enabled) {
 870                 if (enable) {
 871                         PP_DBG_LOG("enable Low Memory PState.\n");
 872
 873                         return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 874                                                 PPSMC_MSG_EnableLowMemoryPstate,
 875                                                 (lock ? 1 : 0));
 876                 } else {
 877                         PP_DBG_LOG("disable Low Memory PState.\n");
 878
 879                         return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 880                                                 PPSMC_MSG_DisableLowMemoryPstate,
 881                                                 (lock ? 1 : 0));
 882                 }
 883         }
 884
 885         return 0;
 886 }
 887
 888 static int cz_tf_update_low_mem_pstate(struct pp_hwmgr *hwmgr,
 889                                         void *input, void *output,
 890                                         void *storage, int result)
 891 {
 892         bool disable_switch;
 893         bool enable_low_mem_state;
 894         struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
 895         const struct phm_set_power_state_input *states = (struct phm_set_power_state_input *)input;
 896         const struct cz_power_state *pnew_state = cast_const_PhwCzPowerState(states->pnew_state);
 897
 898         if (hw_data->sys_info.nb_dpm_enable) {
 899                 disable_switch = hw_data->cc6_settings.nb_pstate_switch_disable ? true : false;
 900                 enable_low_mem_state = hw_data->cc6_settings.nb_pstate_switch_disable ? false : true;
 901
 902                 if (pnew_state->action == FORCE_HIGH)
 903                         cz_nbdpm_pstate_enable_disable(hwmgr, false, disable_switch);
 904                 else if (pnew_state->action == CANCEL_FORCE_HIGH)
 905                         cz_nbdpm_pstate_enable_disable(hwmgr, true, disable_switch);
 906                 else
 907                         cz_nbdpm_pstate_enable_disable(hwmgr, enable_low_mem_state, disable_switch);
 908         }
 909         return 0;
 910 }
 911
 912 static struct phm_master_table_item cz_set_power_state_list[] = {
 913         {NULL, cz_tf_update_sclk_limit},
 914         {NULL, cz_tf_set_deep_sleep_sclk_threshold},
 915         {NULL, cz_tf_set_watermark_threshold},
 916         {NULL, cz_tf_set_enabled_levels},
 917         {NULL, cz_tf_enable_nb_dpm},
 918         {NULL, cz_tf_update_low_mem_pstate},
 919         {NULL, NULL}
 920 };
 921
 922 static struct phm_master_table_header cz_set_power_state_master = {
 923         0,
 924         PHM_MasterTableFlag_None,
 925         cz_set_power_state_list
 926 };
 927
 928 static struct phm_master_table_item cz_setup_asic_list[] = {
 929         {NULL, cz_tf_reset_active_process_mask},
 930         {NULL, cz_tf_upload_pptable_to_smu},
 931         {NULL, cz_tf_init_sclk_limit},
 932         {NULL, cz_tf_init_uvd_limit},
 933         {NULL, cz_tf_init_vce_limit},
 934         {NULL, cz_tf_init_acp_limit},
 935         {NULL, cz_tf_init_power_gate_state},
 936         {NULL, cz_tf_init_sclk_threshold},
 937         {NULL, NULL}
 938 };
 939
 940 static struct phm_master_table_header cz_setup_asic_master = {
 941         0,
 942         PHM_MasterTableFlag_None,
 943         cz_setup_asic_list
 944 };
 945
 946 static int cz_tf_power_up_display_clock_sys_pll(struct pp_hwmgr *hwmgr,
 947                                         void *input, void *output,
 948                                         void *storage, int result)
 949 {
 950         struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
 951         hw_data->disp_clk_bypass_pending = false;
 952         hw_data->disp_clk_bypass = false;
 953
 954         return 0;
 955 }
 956
 957 static int cz_tf_clear_nb_dpm_flag(struct pp_hwmgr *hwmgr,
 958                                         void *input, void *output,
 959                                         void *storage, int result)
 960 {
 961         struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
 962         hw_data->is_nb_dpm_enabled = false;
 963
 964         return 0;
 965 }
 966
 967 static int cz_tf_reset_cc6_data(struct pp_hwmgr *hwmgr,
 968                                         void *input, void *output,
 969                                         void *storage, int result)
 970 {
 971         struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
 972
 973         hw_data->cc6_settings.cc6_setting_changed = false;
 974         hw_data->cc6_settings.cpu_pstate_separation_time = 0;
 975         hw_data->cc6_settings.cpu_cc6_disable = false;
 976         hw_data->cc6_settings.cpu_pstate_disable = false;
 977
 978         return 0;
 979 }
 980
 981 static struct phm_master_table_item cz_power_down_asic_list[] = {
 982         {NULL, cz_tf_power_up_display_clock_sys_pll},
 983         {NULL, cz_tf_clear_nb_dpm_flag},
 984         {NULL, cz_tf_reset_cc6_data},
 985         {NULL, NULL}
 986 };
 987
 988 static struct phm_master_table_header cz_power_down_asic_master = {
 989         0,
 990         PHM_MasterTableFlag_None,
 991         cz_power_down_asic_list
 992 };
 993
 994 static int cz_tf_program_voting_clients(struct pp_hwmgr *hwmgr, void *input,
 995                                 void *output, void *storage, int result)
 996 {
 997         PHMCZ_WRITE_SMC_REGISTER(hwmgr->device, CG_FREQ_TRAN_VOTING_0,
 998                                 PPCZ_VOTINGRIGHTSCLIENTS_DFLT0);
 999         return 0;
1000 }
1001
1002 static int cz_tf_start_dpm(struct pp_hwmgr *hwmgr, void *input, void *output,
1003                            void *storage, int result)
1004 {
1005         int res = 0xff;
1006         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1007         unsigned long dpm_features = 0;
1008
1009         cz_hwmgr->dpm_flags |= DPMFlags_SCLK_Enabled;
1010         dpm_features |= SCLK_DPM_MASK;
1011
1012         res = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1013                                 PPSMC_MSG_EnableAllSmuFeatures,
1014                                 dpm_features);
1015
1016         return res;
1017 }
1018
1019 static int cz_tf_program_bootup_state(struct pp_hwmgr *hwmgr, void *input,
1020                                 void *output, void *storage, int result)
1021 {
1022         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1023
1024         cz_hwmgr->sclk_dpm.soft_min_clk = cz_hwmgr->sys_info.bootup_engine_clock;
1025         cz_hwmgr->sclk_dpm.soft_max_clk = cz_hwmgr->sys_info.bootup_engine_clock;
1026
1027         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1028                                 PPSMC_MSG_SetSclkSoftMin,
1029                                 cz_get_sclk_level(hwmgr,
1030                                 cz_hwmgr->sclk_dpm.soft_min_clk,
1031                                 PPSMC_MSG_SetSclkSoftMin));
1032
1033         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1034                                 PPSMC_MSG_SetSclkSoftMax,
1035                                 cz_get_sclk_level(hwmgr,
1036                                 cz_hwmgr->sclk_dpm.soft_max_clk,
1037                                 PPSMC_MSG_SetSclkSoftMax));
1038
1039         return 0;
1040 }
1041
1042 int cz_tf_reset_acp_boot_level(struct pp_hwmgr *hwmgr, void *input,
1043                                 void *output, void *storage, int result)
1044 {
1045         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1046
1047         cz_hwmgr->acp_boot_level = 0xff;
1048         return 0;
1049 }
1050
1051 static bool cz_dpm_check_smu_features(struct pp_hwmgr *hwmgr,
1052                                 unsigned long check_feature)
1053 {
1054         int result;
1055         unsigned long features;
1056
1057         result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_GetFeatureStatus, 0);
1058         if (result == 0) {
1059                 features = smum_get_argument(hwmgr->smumgr);
1060                 if (features & check_feature)
1061                         return true;
1062         }
1063
1064         return result;
1065 }
1066
1067 static int cz_tf_check_for_dpm_disabled(struct pp_hwmgr *hwmgr, void *input,
1068                                 void *output, void *storage, int result)
1069 {
1070         if (cz_dpm_check_smu_features(hwmgr, SMU_EnabledFeatureScoreboard_SclkDpmOn))
1071                 return PP_Result_TableImmediateExit;
1072         return 0;
1073 }
1074
1075 static int cz_tf_enable_didt(struct pp_hwmgr *hwmgr, void *input,
1076                                 void *output, void *storage, int result)
1077 {
1078         /* TO DO */
1079         return 0;
1080 }
1081
1082 static int cz_tf_check_for_dpm_enabled(struct pp_hwmgr *hwmgr,
1083                                                 void *input, void *output,
1084                                                 void *storage, int result)
1085 {
1086         if (!cz_dpm_check_smu_features(hwmgr,
1087                              SMU_EnabledFeatureScoreboard_SclkDpmOn))
1088                 return PP_Result_TableImmediateExit;
1089         return 0;
1090 }
1091
1092 static struct phm_master_table_item cz_disable_dpm_list[] = {
1093         { NULL, cz_tf_check_for_dpm_enabled},
1094         {NULL, NULL},
1095 };
1096
1097
1098 static struct phm_master_table_header cz_disable_dpm_master = {
1099         0,
1100         PHM_MasterTableFlag_None,
1101         cz_disable_dpm_list
1102 };
1103
1104 static struct phm_master_table_item cz_enable_dpm_list[] = {
1105         { NULL, cz_tf_check_for_dpm_disabled },
1106         { NULL, cz_tf_program_voting_clients },
1107         { NULL, cz_tf_start_dpm},
1108         { NULL, cz_tf_program_bootup_state},
1109         { NULL, cz_tf_enable_didt },
1110         { NULL, cz_tf_reset_acp_boot_level },
1111         {NULL, NULL},
1112 };
1113
1114 static struct phm_master_table_header cz_enable_dpm_master = {
1115         0,
1116         PHM_MasterTableFlag_None,
1117         cz_enable_dpm_list
1118 };
1119
1120 static int cz_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
1121                                 struct pp_power_state  *prequest_ps,
1122                         const struct pp_power_state *pcurrent_ps)
1123 {
1124         struct cz_power_state *cz_ps =
1125                                 cast_PhwCzPowerState(&prequest_ps->hardware);
1126
1127         const struct cz_power_state *cz_current_ps =
1128                                 cast_const_PhwCzPowerState(&pcurrent_ps->hardware);
1129
1130         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1131         struct PP_Clocks clocks = {0, 0, 0, 0};
1132         bool force_high;
1133         uint32_t  num_of_active_displays = 0;
1134         struct cgs_display_info info = {0};
1135
1136         cz_ps->evclk = hwmgr->vce_arbiter.evclk;
1137         cz_ps->ecclk = hwmgr->vce_arbiter.ecclk;
1138
1139         cz_ps->need_dfs_bypass = true;
1140
1141         cz_hwmgr->video_start = (hwmgr->uvd_arbiter.vclk != 0 || hwmgr->uvd_arbiter.dclk != 0 ||
1142                                 hwmgr->vce_arbiter.evclk != 0 || hwmgr->vce_arbiter.ecclk != 0);
1143
1144         cz_hwmgr->battery_state = (PP_StateUILabel_Battery == prequest_ps->classification.ui_label);
1145
1146         clocks.memoryClock = hwmgr->display_config.min_mem_set_clock != 0 ?
1147                                 hwmgr->display_config.min_mem_set_clock :
1148                                 cz_hwmgr->sys_info.nbp_memory_clock[1];
1149
1150         cgs_get_active_displays_info(hwmgr->device, &info);
1151         num_of_active_displays = info.display_count;
1152
1153         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
1154                 clocks.memoryClock = hwmgr->dyn_state.max_clock_voltage_on_ac.mclk;
1155
1156         if (clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
1157                 clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
1158
1159         force_high = (clocks.memoryClock > cz_hwmgr->sys_info.nbp_memory_clock[CZ_NUM_NBPMEMORYCLOCK - 1])
1160                         || (num_of_active_displays >= 3);
1161
1162         cz_ps->action = cz_current_ps->action;
1163
1164         if ((force_high == false) && (cz_ps->action == FORCE_HIGH))
1165                 cz_ps->action = CANCEL_FORCE_HIGH;
1166         else if ((force_high == true) && (cz_ps->action != FORCE_HIGH))
1167                 cz_ps->action = FORCE_HIGH;
1168         else
1169                 cz_ps->action = DO_NOTHING;
1170
1171         return 0;
1172 }
1173
1174 static int cz_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
1175 {
1176         int result = 0;
1177
1178         result = cz_initialize_dpm_defaults(hwmgr);
1179         if (result != 0) {
1180                 printk(KERN_ERR "[ powerplay ] cz_initialize_dpm_defaults failed\n");
1181                 return result;
1182         }
1183
1184         result = cz_get_system_info_data(hwmgr);
1185         if (result != 0) {
1186                 printk(KERN_ERR "[ powerplay ] cz_get_system_info_data failed\n");
1187                 return result;
1188         }
1189
1190         cz_construct_boot_state(hwmgr);
1191
1192         result = phm_construct_table(hwmgr, &cz_setup_asic_master,
1193                                 &(hwmgr->setup_asic));
1194         if (result != 0) {
1195                 printk(KERN_ERR "[ powerplay ] Fail to construct setup ASIC\n");
1196                 return result;
1197         }
1198
1199         result = phm_construct_table(hwmgr, &cz_power_down_asic_master,
1200                                 &(hwmgr->power_down_asic));
1201         if (result != 0) {
1202                 printk(KERN_ERR "[ powerplay ] Fail to construct power down ASIC\n");
1203                 return result;
1204         }
1205
1206         result = phm_construct_table(hwmgr, &cz_disable_dpm_master,
1207                                 &(hwmgr->disable_dynamic_state_management));
1208         if (result != 0) {
1209                 printk(KERN_ERR "[ powerplay ] Fail to disable_dynamic_state\n");
1210                 return result;
1211         }
1212         result = phm_construct_table(hwmgr, &cz_enable_dpm_master,
1213                                 &(hwmgr->enable_dynamic_state_management));
1214         if (result != 0) {
1215                 printk(KERN_ERR "[ powerplay ] Fail to enable_dynamic_state\n");
1216                 return result;
1217         }
1218         result = phm_construct_table(hwmgr, &cz_set_power_state_master,
1219                                 &(hwmgr->set_power_state));
1220         if (result != 0) {
1221                 printk(KERN_ERR "[ powerplay ] Fail to construct set_power_state\n");
1222                 return result;
1223         }
1224         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =  CZ_MAX_HARDWARE_POWERLEVELS;
1225
1226         result = phm_construct_table(hwmgr, &cz_phm_enable_clock_power_gatings_master, &(hwmgr->enable_clock_power_gatings));
1227         if (result != 0) {
1228                 printk(KERN_ERR "[ powerplay ] Fail to construct enable_clock_power_gatings\n");
1229                 return result;
1230         }
1231         return result;
1232 }
1233
1234 static int cz_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
1235 {
1236         if (hwmgr != NULL || hwmgr->backend != NULL) {
1237                 kfree(hwmgr->backend);
1238                 kfree(hwmgr);
1239         }
1240         return 0;
1241 }
1242
1243 int cz_phm_force_dpm_highest(struct pp_hwmgr *hwmgr)
1244 {
1245         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1246
1247         if (cz_hwmgr->sclk_dpm.soft_min_clk !=
1248                                 cz_hwmgr->sclk_dpm.soft_max_clk)
1249                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1250                                                 PPSMC_MSG_SetSclkSoftMin,
1251                                                 cz_get_sclk_level(hwmgr,
1252                                                 cz_hwmgr->sclk_dpm.soft_max_clk,
1253                                                 PPSMC_MSG_SetSclkSoftMin));
1254         return 0;
1255 }
1256
1257 int cz_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
1258 {
1259         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1260         struct phm_clock_voltage_dependency_table *table =
1261                                 hwmgr->dyn_state.vddc_dependency_on_sclk;
1262         unsigned long clock = 0, level;
1263
1264         if (NULL == table || table->count <= 0)
1265                 return -EINVAL;
1266
1267         cz_hwmgr->sclk_dpm.soft_min_clk = table->entries[0].clk;
1268         cz_hwmgr->sclk_dpm.hard_min_clk = table->entries[0].clk;
1269
1270         level = cz_get_max_sclk_level(hwmgr) - 1;
1271
1272         if (level < table->count)
1273                 clock = table->entries[level].clk;
1274         else
1275                 clock = table->entries[table->count - 1].clk;
1276
1277         cz_hwmgr->sclk_dpm.soft_max_clk = clock;
1278         cz_hwmgr->sclk_dpm.hard_max_clk = clock;
1279
1280         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1281                                 PPSMC_MSG_SetSclkSoftMin,
1282                                 cz_get_sclk_level(hwmgr,
1283                                 cz_hwmgr->sclk_dpm.soft_min_clk,
1284                                 PPSMC_MSG_SetSclkSoftMin));
1285
1286         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1287                                 PPSMC_MSG_SetSclkSoftMax,
1288                                 cz_get_sclk_level(hwmgr,
1289                                 cz_hwmgr->sclk_dpm.soft_max_clk,
1290                                 PPSMC_MSG_SetSclkSoftMax));
1291
1292         return 0;
1293 }
1294
1295 int cz_phm_force_dpm_lowest(struct pp_hwmgr *hwmgr)
1296 {
1297         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1298
1299         if (cz_hwmgr->sclk_dpm.soft_min_clk !=
1300                                 cz_hwmgr->sclk_dpm.soft_max_clk) {
1301                 cz_hwmgr->sclk_dpm.soft_max_clk =
1302                         cz_hwmgr->sclk_dpm.soft_min_clk;
1303
1304                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1305                                 PPSMC_MSG_SetSclkSoftMax,
1306                                 cz_get_sclk_level(hwmgr,
1307                                 cz_hwmgr->sclk_dpm.soft_max_clk,
1308                                 PPSMC_MSG_SetSclkSoftMax));
1309         }
1310
1311         return 0;
1312 }
1313
1314 static int cz_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
1315                                 enum amd_dpm_forced_level level)
1316 {
1317         int ret = 0;
1318
1319         switch (level) {
1320         case AMD_DPM_FORCED_LEVEL_HIGH:
1321                 ret = cz_phm_force_dpm_highest(hwmgr);
1322                 if (ret)
1323                         return ret;
1324                 break;
1325         case AMD_DPM_FORCED_LEVEL_LOW:
1326                 ret = cz_phm_force_dpm_lowest(hwmgr);
1327                 if (ret)
1328                         return ret;
1329                 break;
1330         case AMD_DPM_FORCED_LEVEL_AUTO:
1331                 ret = cz_phm_unforce_dpm_levels(hwmgr);
1332                 if (ret)
1333                         return ret;
1334                 break;
1335         default:
1336                 break;
1337         }
1338
1339         hwmgr->dpm_level = level;
1340
1341         return ret;
1342 }
1343
1344 int cz_dpm_powerdown_uvd(struct pp_hwmgr *hwmgr)
1345 {
1346         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1347                                          PHM_PlatformCaps_UVDPowerGating))
1348                 return smum_send_msg_to_smc(hwmgr->smumgr,
1349                                                      PPSMC_MSG_UVDPowerOFF);
1350         return 0;
1351 }
1352
1353 int cz_dpm_powerup_uvd(struct pp_hwmgr *hwmgr)
1354 {
1355         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1356                                          PHM_PlatformCaps_UVDPowerGating)) {
1357                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1358                                   PHM_PlatformCaps_UVDDynamicPowerGating)) {
1359                         return smum_send_msg_to_smc_with_parameter(
1360                                                                 hwmgr->smumgr,
1361                                                    PPSMC_MSG_UVDPowerON, 1);
1362                 } else {
1363                         return smum_send_msg_to_smc_with_parameter(
1364                                                                 hwmgr->smumgr,
1365                                                    PPSMC_MSG_UVDPowerON, 0);
1366                 }
1367         }
1368
1369         return 0;
1370 }
1371
1372 int cz_dpm_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
1373 {
1374         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1375         struct phm_uvd_clock_voltage_dependency_table *ptable =
1376                 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
1377
1378         if (!bgate) {
1379                 /* Stable Pstate is enabled and we need to set the UVD DPM to highest level */
1380                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1381                                          PHM_PlatformCaps_StablePState)) {
1382                         cz_hwmgr->uvd_dpm.hard_min_clk =
1383                                    ptable->entries[ptable->count - 1].vclk;
1384
1385                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1386                                                      PPSMC_MSG_SetUvdHardMin,
1387                                                       cz_get_uvd_level(hwmgr,
1388                                              cz_hwmgr->uvd_dpm.hard_min_clk,
1389                                                    PPSMC_MSG_SetUvdHardMin));
1390
1391                         cz_enable_disable_uvd_dpm(hwmgr, true);
1392                 } else
1393                         cz_enable_disable_uvd_dpm(hwmgr, true);
1394         } else
1395                 cz_enable_disable_uvd_dpm(hwmgr, false);
1396
1397         return 0;
1398 }
1399
1400 int  cz_dpm_update_vce_dpm(struct pp_hwmgr *hwmgr)
1401 {
1402         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1403         struct phm_vce_clock_voltage_dependency_table *ptable =
1404                 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
1405
1406         /* Stable Pstate is enabled and we need to set the VCE DPM to highest level */
1407         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1408                                          PHM_PlatformCaps_StablePState)) {
1409                 cz_hwmgr->vce_dpm.hard_min_clk =
1410                                   ptable->entries[ptable->count - 1].ecclk;
1411
1412                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1413                                         PPSMC_MSG_SetEclkHardMin,
1414                                         cz_get_eclk_level(hwmgr,
1415                                              cz_hwmgr->vce_dpm.hard_min_clk,
1416                                                 PPSMC_MSG_SetEclkHardMin));
1417         } else {
1418                 /*EPR# 419220 -HW limitation to to */
1419                 cz_hwmgr->vce_dpm.hard_min_clk = hwmgr->vce_arbiter.ecclk;
1420                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1421                                             PPSMC_MSG_SetEclkHardMin,
1422                                             cz_get_eclk_level(hwmgr,
1423                                      cz_hwmgr->vce_dpm.hard_min_clk,
1424                                           PPSMC_MSG_SetEclkHardMin));
1425
1426         }
1427         return 0;
1428 }
1429
1430 int cz_dpm_powerdown_vce(struct pp_hwmgr *hwmgr)
1431 {
1432         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1433                                          PHM_PlatformCaps_VCEPowerGating))
1434                 return smum_send_msg_to_smc(hwmgr->smumgr,
1435                                                      PPSMC_MSG_VCEPowerOFF);
1436         return 0;
1437 }
1438
1439 int cz_dpm_powerup_vce(struct pp_hwmgr *hwmgr)
1440 {
1441         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1442                                          PHM_PlatformCaps_VCEPowerGating))
1443                 return smum_send_msg_to_smc(hwmgr->smumgr,
1444                                                      PPSMC_MSG_VCEPowerON);
1445         return 0;
1446 }
1447
1448 static int cz_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
1449 {
1450         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1451
1452         return cz_hwmgr->sys_info.bootup_uma_clock;
1453 }
1454
1455 static int cz_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
1456 {
1457         struct pp_power_state  *ps;
1458         struct cz_power_state  *cz_ps;
1459
1460         if (hwmgr == NULL)
1461                 return -EINVAL;
1462
1463         ps = hwmgr->request_ps;
1464
1465         if (ps == NULL)
1466                 return -EINVAL;
1467
1468         cz_ps = cast_PhwCzPowerState(&ps->hardware);
1469
1470         if (low)
1471                 return cz_ps->levels[0].engineClock;
1472         else
1473                 return cz_ps->levels[cz_ps->level-1].engineClock;
1474 }
1475
1476 static int cz_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
1477                                         struct pp_hw_power_state *hw_ps)
1478 {
1479         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1480         struct cz_power_state *cz_ps = cast_PhwCzPowerState(hw_ps);
1481
1482         cz_ps->level = 1;
1483         cz_ps->nbps_flags = 0;
1484         cz_ps->bapm_flags = 0;
1485         cz_ps->levels[0] = cz_hwmgr->boot_power_level;
1486
1487         return 0;
1488 }
1489
1490 static int cz_dpm_get_pp_table_entry_callback(
1491                                                      struct pp_hwmgr *hwmgr,
1492                                            struct pp_hw_power_state *hw_ps,
1493                                                           unsigned int index,
1494                                                      const void *clock_info)
1495 {
1496         struct cz_power_state *cz_ps = cast_PhwCzPowerState(hw_ps);
1497
1498         const ATOM_PPLIB_CZ_CLOCK_INFO *cz_clock_info = clock_info;
1499
1500         struct phm_clock_voltage_dependency_table *table =
1501                                     hwmgr->dyn_state.vddc_dependency_on_sclk;
1502         uint8_t clock_info_index = cz_clock_info->index;
1503
1504         if (clock_info_index > (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1))
1505                 clock_info_index = (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1);
1506
1507         cz_ps->levels[index].engineClock = table->entries[clock_info_index].clk;
1508         cz_ps->levels[index].vddcIndex = (uint8_t)table->entries[clock_info_index].v;
1509
1510         cz_ps->level = index + 1;
1511
1512         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
1513                 cz_ps->levels[index].dsDividerIndex = 5;
1514                 cz_ps->levels[index].ssDividerIndex = 5;
1515         }
1516
1517         return 0;
1518 }
1519
1520 static int cz_dpm_get_num_of_pp_table_entries(struct pp_hwmgr *hwmgr)
1521 {
1522         int result;
1523         unsigned long ret = 0;
1524
1525         result = pp_tables_get_num_of_entries(hwmgr, &ret);
1526
1527         return result ? 0 : ret;
1528 }
1529
1530 static int cz_dpm_get_pp_table_entry(struct pp_hwmgr *hwmgr,
1531                     unsigned long entry, struct pp_power_state *ps)
1532 {
1533         int result;
1534         struct cz_power_state *cz_ps;
1535
1536         ps->hardware.magic = PhwCz_Magic;
1537
1538         cz_ps = cast_PhwCzPowerState(&(ps->hardware));
1539
1540         result = pp_tables_get_entry(hwmgr, entry, ps,
1541                         cz_dpm_get_pp_table_entry_callback);
1542
1543         cz_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK;
1544         cz_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK;
1545
1546         return result;
1547 }
1548
1549 int cz_get_power_state_size(struct pp_hwmgr *hwmgr)
1550 {
1551         return sizeof(struct cz_power_state);
1552 }
1553
1554 static void
1555 cz_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
1556 {
1557         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1558
1559         struct phm_clock_voltage_dependency_table *table =
1560                                 hwmgr->dyn_state.vddc_dependency_on_sclk;
1561
1562         struct phm_vce_clock_voltage_dependency_table *vce_table =
1563                 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
1564
1565         struct phm_uvd_clock_voltage_dependency_table *uvd_table =
1566                 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
1567
1568         uint32_t sclk_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX),
1569                                         TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX);
1570         uint32_t uvd_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
1571                                         TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_UVD_INDEX);
1572         uint32_t vce_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
1573                                         TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_VCE_INDEX);
1574
1575         uint32_t sclk, vclk, dclk, ecclk, tmp, activity_percent;
1576         uint16_t vddnb, vddgfx;
1577         int result;
1578
1579         if (sclk_index >= NUM_SCLK_LEVELS) {
1580                 seq_printf(m, "\n invalid sclk dpm profile %d\n", sclk_index);
1581         } else {
1582                 sclk = table->entries[sclk_index].clk;
1583                 seq_printf(m, "\n index: %u sclk: %u MHz\n", sclk_index, sclk/100);
1584         }
1585
1586         tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_NB_CURRENTVID) &
1587                 CURRENT_NB_VID_MASK) >> CURRENT_NB_VID__SHIFT;
1588         vddnb = cz_convert_8Bit_index_to_voltage(hwmgr, tmp);
1589         tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_GFX_CURRENTVID) &
1590                 CURRENT_GFX_VID_MASK) >> CURRENT_GFX_VID__SHIFT;
1591         vddgfx = cz_convert_8Bit_index_to_voltage(hwmgr, (u16)tmp);
1592         seq_printf(m, "\n vddnb: %u vddgfx: %u\n", vddnb, vddgfx);
1593
1594         seq_printf(m, "\n uvd    %sabled\n", cz_hwmgr->uvd_power_gated ? "dis" : "en");
1595         if (!cz_hwmgr->uvd_power_gated) {
1596                 if (uvd_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
1597                         seq_printf(m, "\n invalid uvd dpm level %d\n", uvd_index);
1598                 } else {
1599                         vclk = uvd_table->entries[uvd_index].vclk;
1600                         dclk = uvd_table->entries[uvd_index].dclk;
1601                         seq_printf(m, "\n index: %u uvd vclk: %u MHz dclk: %u MHz\n", uvd_index, vclk/100, dclk/100);
1602                 }
1603         }
1604
1605         seq_printf(m, "\n vce    %sabled\n", cz_hwmgr->vce_power_gated ? "dis" : "en");
1606         if (!cz_hwmgr->vce_power_gated) {
1607                 if (vce_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
1608                         seq_printf(m, "\n invalid vce dpm level %d\n", vce_index);
1609                 } else {
1610                         ecclk = vce_table->entries[vce_index].ecclk;
1611                         seq_printf(m, "\n index: %u vce ecclk: %u MHz\n", vce_index, ecclk/100);
1612                 }
1613         }
1614
1615         result = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetAverageGraphicsActivity);
1616         if (0 == result) {
1617                 activity_percent = cgs_read_register(hwmgr->device, mmSMU_MP1_SRBM2P_ARG_0);
1618                 activity_percent = activity_percent > 100 ? 100 : activity_percent;
1619         } else {
1620                 activity_percent = 50;
1621         }
1622
1623         seq_printf(m, "\n [GPU load]: %u %%\n\n", activity_percent);
1624 }
1625
1626 static void cz_hw_print_display_cfg(
1627         const struct cc6_settings *cc6_settings)
1628 {
1629         PP_DBG_LOG("New Display Configuration:\n");
1630
1631         PP_DBG_LOG("   cpu_cc6_disable: %d\n",
1632                         cc6_settings->cpu_cc6_disable);
1633         PP_DBG_LOG("   cpu_pstate_disable: %d\n",
1634                         cc6_settings->cpu_pstate_disable);
1635         PP_DBG_LOG("   nb_pstate_switch_disable: %d\n",
1636                         cc6_settings->nb_pstate_switch_disable);
1637         PP_DBG_LOG("   cpu_pstate_separation_time: %d\n\n",
1638                         cc6_settings->cpu_pstate_separation_time);
1639 }
1640
1641  static int cz_set_cpu_power_state(struct pp_hwmgr *hwmgr)
1642 {
1643         struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
1644         uint32_t data = 0;
1645
1646         if (hw_data->cc6_settings.cc6_setting_changed == true) {
1647
1648                 hw_data->cc6_settings.cc6_setting_changed = false;
1649
1650                 cz_hw_print_display_cfg(&hw_data->cc6_settings);
1651
1652                 data |= (hw_data->cc6_settings.cpu_pstate_separation_time
1653                         & PWRMGT_SEPARATION_TIME_MASK)
1654                         << PWRMGT_SEPARATION_TIME_SHIFT;
1655
1656                 data |= (hw_data->cc6_settings.cpu_cc6_disable ? 0x1 : 0x0)
1657                         << PWRMGT_DISABLE_CPU_CSTATES_SHIFT;
1658
1659                 data |= (hw_data->cc6_settings.cpu_pstate_disable ? 0x1 : 0x0)
1660                         << PWRMGT_DISABLE_CPU_PSTATES_SHIFT;
1661
1662                 PP_DBG_LOG("SetDisplaySizePowerParams data: 0x%X\n",
1663                         data);
1664
1665                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1666                                                 PPSMC_MSG_SetDisplaySizePowerParams,
1667                                                 data);
1668         }
1669
1670         return 0;
1671 }
1672
1673
1674 static int cz_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time,
1675                         bool cc6_disable, bool pstate_disable, bool pstate_switch_disable)
1676 {
1677         struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
1678
1679         if (separation_time !=
1680                 hw_data->cc6_settings.cpu_pstate_separation_time
1681                 || cc6_disable !=
1682                 hw_data->cc6_settings.cpu_cc6_disable
1683                 || pstate_disable !=
1684                 hw_data->cc6_settings.cpu_pstate_disable
1685                 || pstate_switch_disable !=
1686                 hw_data->cc6_settings.nb_pstate_switch_disable) {
1687
1688                 hw_data->cc6_settings.cc6_setting_changed = true;
1689
1690                 hw_data->cc6_settings.cpu_pstate_separation_time =
1691                         separation_time;
1692                 hw_data->cc6_settings.cpu_cc6_disable =
1693                         cc6_disable;
1694                 hw_data->cc6_settings.cpu_pstate_disable =
1695                         pstate_disable;
1696                 hw_data->cc6_settings.nb_pstate_switch_disable =
1697                         pstate_switch_disable;
1698
1699         }
1700
1701         return 0;
1702 }
1703
1704 static int cz_get_dal_power_level(struct pp_hwmgr *hwmgr,
1705                 struct amd_pp_simple_clock_info *info)
1706 {
1707         uint32_t i;
1708         const struct phm_clock_voltage_dependency_table *table =
1709                         hwmgr->dyn_state.vddc_dep_on_dal_pwrl;
1710         const struct phm_clock_and_voltage_limits *limits =
1711                         &hwmgr->dyn_state.max_clock_voltage_on_ac;
1712
1713         info->engine_max_clock = limits->sclk;
1714         info->memory_max_clock = limits->mclk;
1715
1716         for (i = table->count - 1; i > 0; i--) {
1717                 if (limits->vddc >= table->entries[i].v) {
1718                         info->level = table->entries[i].clk;
1719                         return 0;
1720                 }
1721         }
1722         return -EINVAL;
1723 }
1724
1725 static int cz_force_clock_level(struct pp_hwmgr *hwmgr,
1726                 enum pp_clock_type type, int level)
1727 {
1728         if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1729                 return -EINVAL;
1730
1731         switch (type) {
1732         case PP_SCLK:
1733                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1734                                 PPSMC_MSG_SetSclkSoftMin,
1735                                 (1 << level));
1736                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1737                                 PPSMC_MSG_SetSclkSoftMax,
1738                                 (1 << level));
1739                 break;
1740         default:
1741                 break;
1742         }
1743
1744         return 0;
1745 }
1746
1747 static int cz_print_clock_levels(struct pp_hwmgr *hwmgr,
1748                 enum pp_clock_type type, char *buf)
1749 {
1750         struct phm_clock_voltage_dependency_table *sclk_table =
1751                         hwmgr->dyn_state.vddc_dependency_on_sclk;
1752         int i, now, size = 0;
1753
1754         switch (type) {
1755         case PP_SCLK:
1756                 now = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device,
1757                                 CGS_IND_REG__SMC,
1758                                 ixTARGET_AND_CURRENT_PROFILE_INDEX),
1759                                 TARGET_AND_CURRENT_PROFILE_INDEX,
1760                                 CURR_SCLK_INDEX);
1761
1762                 for (i = 0; i < sclk_table->count; i++)
1763                         size += sprintf(buf + size, "%d: %uMhz %s\n",
1764                                         i, sclk_table->entries[i].clk / 100,
1765                                         (i == now) ? "*" : "");
1766                 break;
1767         default:
1768                 break;
1769         }
1770         return size;
1771 }
1772
1773 static int cz_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
1774                                 PHM_PerformanceLevelDesignation designation, uint32_t index,
1775                                 PHM_PerformanceLevel *level)
1776 {
1777         const struct cz_power_state *ps;
1778         struct cz_hwmgr *data;
1779         uint32_t level_index;
1780         uint32_t i;
1781
1782         if (level == NULL || hwmgr == NULL || state == NULL)
1783                 return -EINVAL;
1784
1785         data = (struct cz_hwmgr *)(hwmgr->backend);
1786         ps = cast_const_PhwCzPowerState(state);
1787
1788         level_index = index > ps->level - 1 ? ps->level - 1 : index;
1789
1790         level->coreClock  = ps->levels[level_index].engineClock;
1791
1792         if (designation == PHM_PerformanceLevelDesignation_PowerContainment) {
1793                 for (i = 1; i < ps->level; i++) {
1794                         if (ps->levels[i].engineClock > data->dce_slow_sclk_threshold) {
1795                                 level->coreClock = ps->levels[i].engineClock;
1796                                 break;
1797                         }
1798                 }
1799         }
1800
1801         if (level_index == 0)
1802                 level->memory_clock = data->sys_info.nbp_memory_clock[CZ_NUM_NBPMEMORYCLOCK - 1];
1803         else
1804                 level->memory_clock = data->sys_info.nbp_memory_clock[0];
1805
1806         level->vddc = (cz_convert_8Bit_index_to_voltage(hwmgr, ps->levels[level_index].vddcIndex) + 2) / 4;
1807         level->nonLocalMemoryFreq = 0;
1808         level->nonLocalMemoryWidth = 0;
1809
1810         return 0;
1811 }
1812
1813 static int cz_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr,
1814         const struct pp_hw_power_state *state, struct pp_clock_info *clock_info)
1815 {
1816         const struct cz_power_state *ps = cast_const_PhwCzPowerState(state);
1817
1818         clock_info->min_eng_clk = ps->levels[0].engineClock / (1 << (ps->levels[0].ssDividerIndex));
1819         clock_info->max_eng_clk = ps->levels[ps->level - 1].engineClock / (1 << (ps->levels[ps->level - 1].ssDividerIndex));
1820
1821         return 0;
1822 }
1823
1824 static int cz_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type,
1825                                                 struct amd_pp_clocks *clocks)
1826 {
1827         struct cz_hwmgr *data = (struct cz_hwmgr *)(hwmgr->backend);
1828         int i;
1829         struct phm_clock_voltage_dependency_table *table;
1830
1831         clocks->count = cz_get_max_sclk_level(hwmgr);
1832         switch (type) {
1833         case amd_pp_disp_clock:
1834                 for (i = 0; i < clocks->count; i++)
1835                         clocks->clock[i] = data->sys_info.display_clock[i];
1836                 break;
1837         case amd_pp_sys_clock:
1838                 table = hwmgr->dyn_state.vddc_dependency_on_sclk;
1839                 for (i = 0; i < clocks->count; i++)
1840                         clocks->clock[i] = table->entries[i].clk;
1841                 break;
1842         case amd_pp_mem_clock:
1843                 clocks->count = CZ_NUM_NBPMEMORYCLOCK;
1844                 for (i = 0; i < clocks->count; i++)
1845                         clocks->clock[i] = data->sys_info.nbp_memory_clock[clocks->count - 1 - i];
1846                 break;
1847         default:
1848                 return -1;
1849         }
1850
1851         return 0;
1852 }
1853
1854 static int cz_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks)
1855 {
1856         struct phm_clock_voltage_dependency_table *table =
1857                                         hwmgr->dyn_state.vddc_dependency_on_sclk;
1858         unsigned long level;
1859         const struct phm_clock_and_voltage_limits *limits =
1860                         &hwmgr->dyn_state.max_clock_voltage_on_ac;
1861
1862         if ((NULL == table) || (table->count <= 0) || (clocks == NULL))
1863                 return -EINVAL;
1864
1865         level = cz_get_max_sclk_level(hwmgr) - 1;
1866
1867         if (level < table->count)
1868                 clocks->engine_max_clock = table->entries[level].clk;
1869         else
1870                 clocks->engine_max_clock = table->entries[table->count - 1].clk;
1871
1872         clocks->memory_max_clock = limits->mclk;
1873
1874         return 0;
1875 }
1876
1877 static const struct pp_hwmgr_func cz_hwmgr_funcs = {
1878         .backend_init = cz_hwmgr_backend_init,
1879         .backend_fini = cz_hwmgr_backend_fini,
1880         .asic_setup = NULL,
1881         .apply_state_adjust_rules = cz_apply_state_adjust_rules,
1882         .force_dpm_level = cz_dpm_force_dpm_level,
1883         .get_power_state_size = cz_get_power_state_size,
1884         .powerdown_uvd = cz_dpm_powerdown_uvd,
1885         .powergate_uvd = cz_dpm_powergate_uvd,
1886         .powergate_vce = cz_dpm_powergate_vce,
1887         .get_mclk = cz_dpm_get_mclk,
1888         .get_sclk = cz_dpm_get_sclk,
1889         .patch_boot_state = cz_dpm_patch_boot_state,
1890         .get_pp_table_entry = cz_dpm_get_pp_table_entry,
1891         .get_num_of_pp_table_entries = cz_dpm_get_num_of_pp_table_entries,
1892         .print_current_perforce_level = cz_print_current_perforce_level,
1893         .set_cpu_power_state = cz_set_cpu_power_state,
1894         .store_cc6_data = cz_store_cc6_data,
1895         .force_clock_level = cz_force_clock_level,
1896         .print_clock_levels = cz_print_clock_levels,
1897         .get_dal_power_level = cz_get_dal_power_level,
1898         .get_performance_level = cz_get_performance_level,
1899         .get_current_shallow_sleep_clocks = cz_get_current_shallow_sleep_clocks,
1900         .get_clock_by_type = cz_get_clock_by_type,
1901         .get_max_high_clocks = cz_get_max_high_clocks,
1902 };
1903
1904 int cz_hwmgr_init(struct pp_hwmgr *hwmgr)
1905 {
1906         struct cz_hwmgr *cz_hwmgr;
1907         int ret = 0;
1908
1909         cz_hwmgr = kzalloc(sizeof(struct cz_hwmgr), GFP_KERNEL);
1910         if (cz_hwmgr == NULL)
1911                 return -ENOMEM;
1912
1913         hwmgr->backend = cz_hwmgr;
1914         hwmgr->hwmgr_func = &cz_hwmgr_funcs;
1915         hwmgr->pptable_func = &pptable_funcs;
1916         return ret;
1917 }