drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/types.h>
  24 #include <linux/kernel.h>
  25 #include <linux/slab.h>
  26 #include "atom-types.h"
  27 #include "atombios.h"
  28 #include "processpptables.h"
  29 #include "pp_debug.h"
  30 #include "cgs_common.h"
  31 #include "smu/smu_8_0_d.h"
  32 #include "smu8_fusion.h"
  33 #include "smu/smu_8_0_sh_mask.h"
  34 #include "smumgr.h"
  35 #include "hwmgr.h"
  36 #include "hardwaremanager.h"
  37 #include "cz_ppsmc.h"
  38 #include "cz_hwmgr.h"
  39 #include "power_state.h"
  40 #include "cz_clockpowergating.h"
  41 #include "pp_debug.h"
  42
  43 #define ixSMUSVI_NB_CURRENTVID 0xD8230044
  44 #define CURRENT_NB_VID_MASK 0xff000000
  45 #define CURRENT_NB_VID__SHIFT 24
  46 #define ixSMUSVI_GFX_CURRENTVID  0xD8230048
  47 #define CURRENT_GFX_VID_MASK 0xff000000
  48 #define CURRENT_GFX_VID__SHIFT 24
  49
  50 static const unsigned long PhwCz_Magic = (unsigned long) PHM_Cz_Magic;
  51
  52 static struct cz_power_state *cast_PhwCzPowerState(struct pp_hw_power_state *hw_ps)
  53 {
  54         if (PhwCz_Magic != hw_ps->magic)
  55                 return NULL;
  56
  57         return (struct cz_power_state *)hw_ps;
  58 }
  59
  60 static const struct cz_power_state *cast_const_PhwCzPowerState(
  61                                 const struct pp_hw_power_state *hw_ps)
  62 {
  63         if (PhwCz_Magic != hw_ps->magic)
  64                 return NULL;
  65
  66         return (struct cz_power_state *)hw_ps;
  67 }
  68
  69 uint32_t cz_get_eclk_level(struct pp_hwmgr *hwmgr,
  70                                         uint32_t clock, uint32_t msg)
  71 {
  72         int i = 0;
  73         struct phm_vce_clock_voltage_dependency_table *ptable =
  74                 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
  75
  76         switch (msg) {
  77         case PPSMC_MSG_SetEclkSoftMin:
  78         case PPSMC_MSG_SetEclkHardMin:
  79                 for (i = 0; i < (int)ptable->count; i++) {
  80                         if (clock <= ptable->entries[i].ecclk)
  81                                 break;
  82                 }
  83                 break;
  84
  85         case PPSMC_MSG_SetEclkSoftMax:
  86         case PPSMC_MSG_SetEclkHardMax:
  87                 for (i = ptable->count - 1; i >= 0; i--) {
  88                         if (clock >= ptable->entries[i].ecclk)
  89                                 break;
  90                 }
  91                 break;
  92
  93         default:
  94                 break;
  95         }
  96
  97         return i;
  98 }
  99
 100 static uint32_t cz_get_sclk_level(struct pp_hwmgr *hwmgr,
 101                                 uint32_t clock, uint32_t msg)
 102 {
 103         int i = 0;
 104         struct phm_clock_voltage_dependency_table *table =
 105                                 hwmgr->dyn_state.vddc_dependency_on_sclk;
 106
 107         switch (msg) {
 108         case PPSMC_MSG_SetSclkSoftMin:
 109         case PPSMC_MSG_SetSclkHardMin:
 110                 for (i = 0; i < (int)table->count; i++) {
 111                         if (clock <= table->entries[i].clk)
 112                                 break;
 113                 }
 114                 break;
 115
 116         case PPSMC_MSG_SetSclkSoftMax:
 117         case PPSMC_MSG_SetSclkHardMax:
 118                 for (i = table->count - 1; i >= 0; i--) {
 119                         if (clock >= table->entries[i].clk)
 120                                 break;
 121                 }
 122                 break;
 123
 124         default:
 125                 break;
 126         }
 127         return i;
 128 }
 129
 130 static uint32_t cz_get_uvd_level(struct pp_hwmgr *hwmgr,
 131                                         uint32_t clock, uint32_t msg)
 132 {
 133         int i = 0;
 134         struct phm_uvd_clock_voltage_dependency_table *ptable =
 135                 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
 136
 137         switch (msg) {
 138         case PPSMC_MSG_SetUvdSoftMin:
 139         case PPSMC_MSG_SetUvdHardMin:
 140                 for (i = 0; i < (int)ptable->count; i++) {
 141                         if (clock <= ptable->entries[i].vclk)
 142                                 break;
 143                 }
 144                 break;
 145
 146         case PPSMC_MSG_SetUvdSoftMax:
 147         case PPSMC_MSG_SetUvdHardMax:
 148                 for (i = ptable->count - 1; i >= 0; i--) {
 149                         if (clock >= ptable->entries[i].vclk)
 150                                 break;
 151                 }
 152                 break;
 153
 154         default:
 155                 break;
 156         }
 157
 158         return i;
 159 }
 160
 161 static uint32_t cz_get_max_sclk_level(struct pp_hwmgr *hwmgr)
 162 {
 163         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 164
 165         if (cz_hwmgr->max_sclk_level == 0) {
 166                 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxSclkLevel);
 167                 cz_hwmgr->max_sclk_level = smum_get_argument(hwmgr->smumgr) + 1;
 168         }
 169
 170         return cz_hwmgr->max_sclk_level;
 171 }
 172
 173 static int cz_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
 174 {
 175         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 176         uint32_t i;
 177         struct cgs_system_info sys_info = {0};
 178         int result;
 179
 180         cz_hwmgr->gfx_ramp_step = 256*25/100;
 181
 182         cz_hwmgr->gfx_ramp_delay = 1; /* by default, we delay 1us */
 183
 184         for (i = 0; i < CZ_MAX_HARDWARE_POWERLEVELS; i++)
 185                 cz_hwmgr->activity_target[i] = CZ_AT_DFLT;
 186
 187         cz_hwmgr->mgcg_cgtt_local0 = 0x00000000;
 188         cz_hwmgr->mgcg_cgtt_local1 = 0x00000000;
 189
 190         cz_hwmgr->clock_slow_down_freq = 25000;
 191
 192         cz_hwmgr->skip_clock_slow_down = 1;
 193
 194         cz_hwmgr->enable_nb_ps_policy = 1; /* disable until UNB is ready, Enabled */
 195
 196         cz_hwmgr->voltage_drop_in_dce_power_gating = 0; /* disable until fully verified */
 197
 198         cz_hwmgr->voting_rights_clients = 0x00C00033;
 199
 200         cz_hwmgr->static_screen_threshold = 8;
 201
 202         cz_hwmgr->ddi_power_gating_disabled = 0;
 203
 204         cz_hwmgr->bapm_enabled = 1;
 205
 206         cz_hwmgr->voltage_drop_threshold = 0;
 207
 208         cz_hwmgr->gfx_power_gating_threshold = 500;
 209
 210         cz_hwmgr->vce_slow_sclk_threshold = 20000;
 211
 212         cz_hwmgr->dce_slow_sclk_threshold = 30000;
 213
 214         cz_hwmgr->disable_driver_thermal_policy = 1;
 215
 216         cz_hwmgr->disable_nb_ps3_in_battery = 0;
 217
 218         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 219                                                         PHM_PlatformCaps_ABM);
 220
 221         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 222                                     PHM_PlatformCaps_NonABMSupportInPPLib);
 223
 224         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 225                                            PHM_PlatformCaps_SclkDeepSleep);
 226
 227         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 228                                         PHM_PlatformCaps_DynamicM3Arbiter);
 229
 230         cz_hwmgr->override_dynamic_mgpg = 1;
 231
 232         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 233                                   PHM_PlatformCaps_DynamicPatchPowerState);
 234
 235         cz_hwmgr->thermal_auto_throttling_treshold = 0;
 236
 237         cz_hwmgr->tdr_clock = 0;
 238
 239         cz_hwmgr->disable_gfx_power_gating_in_uvd = 0;
 240
 241         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 242                                         PHM_PlatformCaps_DynamicUVDState);
 243
 244         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 245                         PHM_PlatformCaps_UVDDPM);
 246         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 247                         PHM_PlatformCaps_VCEDPM);
 248
 249         cz_hwmgr->cc6_settings.cpu_cc6_disable = false;
 250         cz_hwmgr->cc6_settings.cpu_pstate_disable = false;
 251         cz_hwmgr->cc6_settings.nb_pstate_switch_disable = false;
 252         cz_hwmgr->cc6_settings.cpu_pstate_separation_time = 0;
 253
 254         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 255                                    PHM_PlatformCaps_DisableVoltageIsland);
 256
 257         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 258                       PHM_PlatformCaps_UVDPowerGating);
 259         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 260                       PHM_PlatformCaps_VCEPowerGating);
 261         sys_info.size = sizeof(struct cgs_system_info);
 262         sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS;
 263         result = cgs_query_system_info(hwmgr->device, &sys_info);
 264         if (!result) {
 265                 if (sys_info.value & AMD_PG_SUPPORT_UVD)
 266                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 267                                       PHM_PlatformCaps_UVDPowerGating);
 268                 if (sys_info.value & AMD_PG_SUPPORT_VCE)
 269                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 270                                       PHM_PlatformCaps_VCEPowerGating);
 271         }
 272
 273         return 0;
 274 }
 275
 276 static uint32_t cz_convert_8Bit_index_to_voltage(
 277                         struct pp_hwmgr *hwmgr, uint16_t voltage)
 278 {
 279         return 6200 - (voltage * 25);
 280 }
 281
 282 static int cz_construct_max_power_limits_table(struct pp_hwmgr *hwmgr,
 283                         struct phm_clock_and_voltage_limits *table)
 284 {
 285         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)hwmgr->backend;
 286         struct cz_sys_info *sys_info = &cz_hwmgr->sys_info;
 287         struct phm_clock_voltage_dependency_table *dep_table =
 288                                 hwmgr->dyn_state.vddc_dependency_on_sclk;
 289
 290         if (dep_table->count > 0) {
 291                 table->sclk = dep_table->entries[dep_table->count-1].clk;
 292                 table->vddc = cz_convert_8Bit_index_to_voltage(hwmgr,
 293                    (uint16_t)dep_table->entries[dep_table->count-1].v);
 294         }
 295         table->mclk = sys_info->nbp_memory_clock[0];
 296         return 0;
 297 }
 298
 299 static int cz_init_dynamic_state_adjustment_rule_settings(
 300                         struct pp_hwmgr *hwmgr,
 301                         ATOM_CLK_VOLT_CAPABILITY *disp_voltage_table)
 302 {
 303         uint32_t table_size =
 304                 sizeof(struct phm_clock_voltage_dependency_table) +
 305                 (7 * sizeof(struct phm_clock_voltage_dependency_record));
 306
 307         struct phm_clock_voltage_dependency_table *table_clk_vlt =
 308                                         kzalloc(table_size, GFP_KERNEL);
 309
 310         if (NULL == table_clk_vlt) {
 311                 printk(KERN_ERR "[ powerplay ] Can not allocate memory!\n");
 312                 return -ENOMEM;
 313         }
 314
 315         table_clk_vlt->count = 8;
 316         table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_0;
 317         table_clk_vlt->entries[0].v = 0;
 318         table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_1;
 319         table_clk_vlt->entries[1].v = 1;
 320         table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_2;
 321         table_clk_vlt->entries[2].v = 2;
 322         table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_3;
 323         table_clk_vlt->entries[3].v = 3;
 324         table_clk_vlt->entries[4].clk = PP_DAL_POWERLEVEL_4;
 325         table_clk_vlt->entries[4].v = 4;
 326         table_clk_vlt->entries[5].clk = PP_DAL_POWERLEVEL_5;
 327         table_clk_vlt->entries[5].v = 5;
 328         table_clk_vlt->entries[6].clk = PP_DAL_POWERLEVEL_6;
 329         table_clk_vlt->entries[6].v = 6;
 330         table_clk_vlt->entries[7].clk = PP_DAL_POWERLEVEL_7;
 331         table_clk_vlt->entries[7].v = 7;
 332         hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
 333
 334         return 0;
 335 }
 336
 337 static int cz_get_system_info_data(struct pp_hwmgr *hwmgr)
 338 {
 339         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)hwmgr->backend;
 340         ATOM_INTEGRATED_SYSTEM_INFO_V1_9 *info = NULL;
 341         uint32_t i;
 342         int result = 0;
 343         uint8_t frev, crev;
 344         uint16_t size;
 345
 346         info = (ATOM_INTEGRATED_SYSTEM_INFO_V1_9 *) cgs_atom_get_data_table(
 347                         hwmgr->device,
 348                         GetIndexIntoMasterTable(DATA, IntegratedSystemInfo),
 349                         &size, &frev, &crev);
 350
 351         if (crev != 9) {
 352                 printk(KERN_ERR "[ powerplay ] Unsupported IGP table: %d %d\n", frev, crev);
 353                 return -EINVAL;
 354         }
 355
 356         if (info == NULL) {
 357                 printk(KERN_ERR "[ powerplay ] Could not retrieve the Integrated System Info Table!\n");
 358                 return -EINVAL;
 359         }
 360
 361         cz_hwmgr->sys_info.bootup_uma_clock =
 362                                    le32_to_cpu(info->ulBootUpUMAClock);
 363
 364         cz_hwmgr->sys_info.bootup_engine_clock =
 365                                 le32_to_cpu(info->ulBootUpEngineClock);
 366
 367         cz_hwmgr->sys_info.dentist_vco_freq =
 368                                    le32_to_cpu(info->ulDentistVCOFreq);
 369
 370         cz_hwmgr->sys_info.system_config =
 371                                      le32_to_cpu(info->ulSystemConfig);
 372
 373         cz_hwmgr->sys_info.bootup_nb_voltage_index =
 374                                   le16_to_cpu(info->usBootUpNBVoltage);
 375
 376         cz_hwmgr->sys_info.htc_hyst_lmt =
 377                         (info->ucHtcHystLmt == 0) ? 5 : info->ucHtcHystLmt;
 378
 379         cz_hwmgr->sys_info.htc_tmp_lmt =
 380                         (info->ucHtcTmpLmt == 0) ? 203 : info->ucHtcTmpLmt;
 381
 382         if (cz_hwmgr->sys_info.htc_tmp_lmt <=
 383                         cz_hwmgr->sys_info.htc_hyst_lmt) {
 384                 printk(KERN_ERR "[ powerplay ] The htcTmpLmt should be larger than htcHystLmt.\n");
 385                 return -EINVAL;
 386         }
 387
 388         cz_hwmgr->sys_info.nb_dpm_enable =
 389                                 cz_hwmgr->enable_nb_ps_policy &&
 390                                 (le32_to_cpu(info->ulSystemConfig) >> 3 & 0x1);
 391
 392         for (i = 0; i < CZ_NUM_NBPSTATES; i++) {
 393                 if (i < CZ_NUM_NBPMEMORYCLOCK) {
 394                         cz_hwmgr->sys_info.nbp_memory_clock[i] =
 395                           le32_to_cpu(info->ulNbpStateMemclkFreq[i]);
 396                 }
 397                 cz_hwmgr->sys_info.nbp_n_clock[i] =
 398                             le32_to_cpu(info->ulNbpStateNClkFreq[i]);
 399         }
 400
 401         for (i = 0; i < MAX_DISPLAY_CLOCK_LEVEL; i++) {
 402                 cz_hwmgr->sys_info.display_clock[i] =
 403                                         le32_to_cpu(info->sDispClkVoltageMapping[i].ulMaximumSupportedCLK);
 404         }
 405
 406         /* Here use 4 levels, make sure not exceed */
 407         for (i = 0; i < CZ_NUM_NBPSTATES; i++) {
 408                 cz_hwmgr->sys_info.nbp_voltage_index[i] =
 409                              le16_to_cpu(info->usNBPStateVoltage[i]);
 410         }
 411
 412         if (!cz_hwmgr->sys_info.nb_dpm_enable) {
 413                 for (i = 1; i < CZ_NUM_NBPSTATES; i++) {
 414                         if (i < CZ_NUM_NBPMEMORYCLOCK) {
 415                                 cz_hwmgr->sys_info.nbp_memory_clock[i] =
 416                                     cz_hwmgr->sys_info.nbp_memory_clock[0];
 417                         }
 418                         cz_hwmgr->sys_info.nbp_n_clock[i] =
 419                                     cz_hwmgr->sys_info.nbp_n_clock[0];
 420                         cz_hwmgr->sys_info.nbp_voltage_index[i] =
 421                                     cz_hwmgr->sys_info.nbp_voltage_index[0];
 422                 }
 423         }
 424
 425         if (le32_to_cpu(info->ulGPUCapInfo) &
 426                 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS) {
 427                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 428                                     PHM_PlatformCaps_EnableDFSBypass);
 429         }
 430
 431         cz_hwmgr->sys_info.uma_channel_number = info->ucUMAChannelNumber;
 432
 433         cz_construct_max_power_limits_table (hwmgr,
 434                                     &hwmgr->dyn_state.max_clock_voltage_on_ac);
 435
 436         cz_init_dynamic_state_adjustment_rule_settings(hwmgr,
 437                                     &info->sDISPCLK_Voltage[0]);
 438
 439         return result;
 440 }
 441
 442 static int cz_construct_boot_state(struct pp_hwmgr *hwmgr)
 443 {
 444         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 445
 446         cz_hwmgr->boot_power_level.engineClock =
 447                                 cz_hwmgr->sys_info.bootup_engine_clock;
 448
 449         cz_hwmgr->boot_power_level.vddcIndex =
 450                         (uint8_t)cz_hwmgr->sys_info.bootup_nb_voltage_index;
 451
 452         cz_hwmgr->boot_power_level.dsDividerIndex = 0;
 453
 454         cz_hwmgr->boot_power_level.ssDividerIndex = 0;
 455
 456         cz_hwmgr->boot_power_level.allowGnbSlow = 1;
 457
 458         cz_hwmgr->boot_power_level.forceNBPstate = 0;
 459
 460         cz_hwmgr->boot_power_level.hysteresis_up = 0;
 461
 462         cz_hwmgr->boot_power_level.numSIMDToPowerDown = 0;
 463
 464         cz_hwmgr->boot_power_level.display_wm = 0;
 465
 466         cz_hwmgr->boot_power_level.vce_wm = 0;
 467
 468         return 0;
 469 }
 470
 471 static int cz_tf_reset_active_process_mask(struct pp_hwmgr *hwmgr, void *input,
 472                                         void *output, void *storage, int result)
 473 {
 474         return 0;
 475 }
 476
 477 static int cz_tf_upload_pptable_to_smu(struct pp_hwmgr *hwmgr, void *input,
 478                                        void *output, void *storage, int result)
 479 {
 480         struct SMU8_Fusion_ClkTable *clock_table;
 481         int ret;
 482         uint32_t i;
 483         void *table = NULL;
 484         pp_atomctrl_clock_dividers_kong dividers;
 485
 486         struct phm_clock_voltage_dependency_table *vddc_table =
 487                 hwmgr->dyn_state.vddc_dependency_on_sclk;
 488         struct phm_clock_voltage_dependency_table *vdd_gfx_table =
 489                 hwmgr->dyn_state.vdd_gfx_dependency_on_sclk;
 490         struct phm_acp_clock_voltage_dependency_table *acp_table =
 491                 hwmgr->dyn_state.acp_clock_voltage_dependency_table;
 492         struct phm_uvd_clock_voltage_dependency_table *uvd_table =
 493                 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
 494         struct phm_vce_clock_voltage_dependency_table *vce_table =
 495                 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
 496
 497         if (!hwmgr->need_pp_table_upload)
 498                 return 0;
 499
 500         ret = smum_download_powerplay_table(hwmgr->smumgr, &table);
 501
 502         PP_ASSERT_WITH_CODE((0 == ret && NULL != table),
 503                             "Fail to get clock table from SMU!", return -EINVAL;);
 504
 505         clock_table = (struct SMU8_Fusion_ClkTable *)table;
 506
 507         /* patch clock table */
 508         PP_ASSERT_WITH_CODE((vddc_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
 509                             "Dependency table entry exceeds max limit!", return -EINVAL;);
 510         PP_ASSERT_WITH_CODE((vdd_gfx_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
 511                             "Dependency table entry exceeds max limit!", return -EINVAL;);
 512         PP_ASSERT_WITH_CODE((acp_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
 513                             "Dependency table entry exceeds max limit!", return -EINVAL;);
 514         PP_ASSERT_WITH_CODE((uvd_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
 515                             "Dependency table entry exceeds max limit!", return -EINVAL;);
 516         PP_ASSERT_WITH_CODE((vce_table->count <= CZ_MAX_HARDWARE_POWERLEVELS),
 517                             "Dependency table entry exceeds max limit!", return -EINVAL;);
 518
 519         for (i = 0; i < CZ_MAX_HARDWARE_POWERLEVELS; i++) {
 520
 521                 /* vddc_sclk */
 522                 clock_table->SclkBreakdownTable.ClkLevel[i].GnbVid =
 523                         (i < vddc_table->count) ? (uint8_t)vddc_table->entries[i].v : 0;
 524                 clock_table->SclkBreakdownTable.ClkLevel[i].Frequency =
 525                         (i < vddc_table->count) ? vddc_table->entries[i].clk : 0;
 526
 527                 atomctrl_get_engine_pll_dividers_kong(hwmgr,
 528                                                       clock_table->SclkBreakdownTable.ClkLevel[i].Frequency,
 529                                                       &dividers);
 530
 531                 clock_table->SclkBreakdownTable.ClkLevel[i].DfsDid =
 532                         (uint8_t)dividers.pll_post_divider;
 533
 534                 /* vddgfx_sclk */
 535                 clock_table->SclkBreakdownTable.ClkLevel[i].GfxVid =
 536                         (i < vdd_gfx_table->count) ? (uint8_t)vdd_gfx_table->entries[i].v : 0;
 537
 538                 /* acp breakdown */
 539                 clock_table->AclkBreakdownTable.ClkLevel[i].GfxVid =
 540                         (i < acp_table->count) ? (uint8_t)acp_table->entries[i].v : 0;
 541                 clock_table->AclkBreakdownTable.ClkLevel[i].Frequency =
 542                         (i < acp_table->count) ? acp_table->entries[i].acpclk : 0;
 543
 544                 atomctrl_get_engine_pll_dividers_kong(hwmgr,
 545                                                       clock_table->AclkBreakdownTable.ClkLevel[i].Frequency,
 546                                                       &dividers);
 547
 548                 clock_table->AclkBreakdownTable.ClkLevel[i].DfsDid =
 549                         (uint8_t)dividers.pll_post_divider;
 550
 551
 552                 /* uvd breakdown */
 553                 clock_table->VclkBreakdownTable.ClkLevel[i].GfxVid =
 554                         (i < uvd_table->count) ? (uint8_t)uvd_table->entries[i].v : 0;
 555                 clock_table->VclkBreakdownTable.ClkLevel[i].Frequency =
 556                         (i < uvd_table->count) ? uvd_table->entries[i].vclk : 0;
 557
 558                 atomctrl_get_engine_pll_dividers_kong(hwmgr,
 559                                                       clock_table->VclkBreakdownTable.ClkLevel[i].Frequency,
 560                                                       &dividers);
 561
 562                 clock_table->VclkBreakdownTable.ClkLevel[i].DfsDid =
 563                         (uint8_t)dividers.pll_post_divider;
 564
 565                 clock_table->DclkBreakdownTable.ClkLevel[i].GfxVid =
 566                         (i < uvd_table->count) ? (uint8_t)uvd_table->entries[i].v : 0;
 567                 clock_table->DclkBreakdownTable.ClkLevel[i].Frequency =
 568                         (i < uvd_table->count) ? uvd_table->entries[i].dclk : 0;
 569
 570                 atomctrl_get_engine_pll_dividers_kong(hwmgr,
 571                                                       clock_table->DclkBreakdownTable.ClkLevel[i].Frequency,
 572                                                       &dividers);
 573
 574                 clock_table->DclkBreakdownTable.ClkLevel[i].DfsDid =
 575                         (uint8_t)dividers.pll_post_divider;
 576
 577                 /* vce breakdown */
 578                 clock_table->EclkBreakdownTable.ClkLevel[i].GfxVid =
 579                         (i < vce_table->count) ? (uint8_t)vce_table->entries[i].v : 0;
 580                 clock_table->EclkBreakdownTable.ClkLevel[i].Frequency =
 581                         (i < vce_table->count) ? vce_table->entries[i].ecclk : 0;
 582
 583
 584                 atomctrl_get_engine_pll_dividers_kong(hwmgr,
 585                                                       clock_table->EclkBreakdownTable.ClkLevel[i].Frequency,
 586                                                       &dividers);
 587
 588                 clock_table->EclkBreakdownTable.ClkLevel[i].DfsDid =
 589                         (uint8_t)dividers.pll_post_divider;
 590
 591         }
 592         ret = smum_upload_powerplay_table(hwmgr->smumgr);
 593
 594         return ret;
 595 }
 596
 597 static int cz_tf_init_sclk_limit(struct pp_hwmgr *hwmgr, void *input,
 598                                  void *output, void *storage, int result)
 599 {
 600         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 601         struct phm_clock_voltage_dependency_table *table =
 602                                         hwmgr->dyn_state.vddc_dependency_on_sclk;
 603         unsigned long clock = 0, level;
 604
 605         if (NULL == table || table->count <= 0)
 606                 return -EINVAL;
 607
 608         cz_hwmgr->sclk_dpm.soft_min_clk = table->entries[0].clk;
 609         cz_hwmgr->sclk_dpm.hard_min_clk = table->entries[0].clk;
 610
 611         level = cz_get_max_sclk_level(hwmgr) - 1;
 612
 613         if (level < table->count)
 614                 clock = table->entries[level].clk;
 615         else
 616                 clock = table->entries[table->count - 1].clk;
 617
 618         cz_hwmgr->sclk_dpm.soft_max_clk = clock;
 619         cz_hwmgr->sclk_dpm.hard_max_clk = clock;
 620
 621         return 0;
 622 }
 623
 624 static int cz_tf_init_uvd_limit(struct pp_hwmgr *hwmgr, void *input,
 625                                 void *output, void *storage, int result)
 626 {
 627         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 628         struct phm_uvd_clock_voltage_dependency_table *table =
 629                                 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
 630         unsigned long clock = 0, level;
 631
 632         if (NULL == table || table->count <= 0)
 633                 return -EINVAL;
 634
 635         cz_hwmgr->uvd_dpm.soft_min_clk = 0;
 636         cz_hwmgr->uvd_dpm.hard_min_clk = 0;
 637
 638         smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxUvdLevel);
 639         level = smum_get_argument(hwmgr->smumgr);
 640
 641         if (level < table->count)
 642                 clock = table->entries[level].vclk;
 643         else
 644                 clock = table->entries[table->count - 1].vclk;
 645
 646         cz_hwmgr->uvd_dpm.soft_max_clk = clock;
 647         cz_hwmgr->uvd_dpm.hard_max_clk = clock;
 648
 649         return 0;
 650 }
 651
 652 static int cz_tf_init_vce_limit(struct pp_hwmgr *hwmgr, void *input,
 653                                 void *output, void *storage, int result)
 654 {
 655         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 656         struct phm_vce_clock_voltage_dependency_table *table =
 657                                 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
 658         unsigned long clock = 0, level;
 659
 660         if (NULL == table || table->count <= 0)
 661                 return -EINVAL;
 662
 663         cz_hwmgr->vce_dpm.soft_min_clk = 0;
 664         cz_hwmgr->vce_dpm.hard_min_clk = 0;
 665
 666         smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxEclkLevel);
 667         level = smum_get_argument(hwmgr->smumgr);
 668
 669         if (level < table->count)
 670                 clock = table->entries[level].ecclk;
 671         else
 672                 clock = table->entries[table->count - 1].ecclk;
 673
 674         cz_hwmgr->vce_dpm.soft_max_clk = clock;
 675         cz_hwmgr->vce_dpm.hard_max_clk = clock;
 676
 677         return 0;
 678 }
 679
 680 static int cz_tf_init_acp_limit(struct pp_hwmgr *hwmgr, void *input,
 681                                 void *output, void *storage, int result)
 682 {
 683         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 684         struct phm_acp_clock_voltage_dependency_table *table =
 685                                 hwmgr->dyn_state.acp_clock_voltage_dependency_table;
 686         unsigned long clock = 0, level;
 687
 688         if (NULL == table || table->count <= 0)
 689                 return -EINVAL;
 690
 691         cz_hwmgr->acp_dpm.soft_min_clk = 0;
 692         cz_hwmgr->acp_dpm.hard_min_clk = 0;
 693
 694         smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxAclkLevel);
 695         level = smum_get_argument(hwmgr->smumgr);
 696
 697         if (level < table->count)
 698                 clock = table->entries[level].acpclk;
 699         else
 700                 clock = table->entries[table->count - 1].acpclk;
 701
 702         cz_hwmgr->acp_dpm.soft_max_clk = clock;
 703         cz_hwmgr->acp_dpm.hard_max_clk = clock;
 704         return 0;
 705 }
 706
 707 static int cz_tf_init_power_gate_state(struct pp_hwmgr *hwmgr, void *input,
 708                                 void *output, void *storage, int result)
 709 {
 710         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 711
 712         cz_hwmgr->uvd_power_gated = false;
 713         cz_hwmgr->vce_power_gated = false;
 714         cz_hwmgr->samu_power_gated = false;
 715         cz_hwmgr->acp_power_gated = false;
 716         cz_hwmgr->pgacpinit = true;
 717
 718         return 0;
 719 }
 720
 721 static int cz_tf_init_sclk_threshold(struct pp_hwmgr *hwmgr, void *input,
 722                                 void *output, void *storage, int result)
 723 {
 724         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 725
 726         cz_hwmgr->low_sclk_interrupt_threshold = 0;
 727
 728         return 0;
 729 }
 730 static int cz_tf_update_sclk_limit(struct pp_hwmgr *hwmgr,
 731                                         void *input, void *output,
 732                                         void *storage, int result)
 733 {
 734         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 735         struct phm_clock_voltage_dependency_table *table =
 736                                         hwmgr->dyn_state.vddc_dependency_on_sclk;
 737
 738         unsigned long clock = 0;
 739         unsigned long level;
 740         unsigned long stable_pstate_sclk;
 741         unsigned long percentage;
 742
 743         cz_hwmgr->sclk_dpm.soft_min_clk = table->entries[0].clk;
 744         level = cz_get_max_sclk_level(hwmgr) - 1;
 745
 746         if (level < table->count)
 747                 cz_hwmgr->sclk_dpm.soft_max_clk  = table->entries[level].clk;
 748         else
 749                 cz_hwmgr->sclk_dpm.soft_max_clk  = table->entries[table->count - 1].clk;
 750
 751         clock = hwmgr->display_config.min_core_set_clock;
 752 ;
 753         if (clock == 0)
 754                 printk(KERN_INFO "[ powerplay ] min_core_set_clock not set\n");
 755
 756         if (cz_hwmgr->sclk_dpm.hard_min_clk != clock) {
 757                 cz_hwmgr->sclk_dpm.hard_min_clk = clock;
 758
 759                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 760                                                 PPSMC_MSG_SetSclkHardMin,
 761                                                  cz_get_sclk_level(hwmgr,
 762                                         cz_hwmgr->sclk_dpm.hard_min_clk,
 763                                              PPSMC_MSG_SetSclkHardMin));
 764         }
 765
 766         clock = cz_hwmgr->sclk_dpm.soft_min_clk;
 767
 768         /* update minimum clocks for Stable P-State feature */
 769         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 770                                      PHM_PlatformCaps_StablePState)) {
 771                 percentage = 75;
 772                 /*Sclk - calculate sclk value based on percentage and find FLOOR sclk from VddcDependencyOnSCLK table  */
 773                 stable_pstate_sclk = (hwmgr->dyn_state.max_clock_voltage_on_ac.mclk *
 774                                         percentage) / 100;
 775
 776                 if (clock < stable_pstate_sclk)
 777                         clock = stable_pstate_sclk;
 778         } else {
 779                 if (clock < hwmgr->gfx_arbiter.sclk)
 780                         clock = hwmgr->gfx_arbiter.sclk;
 781         }
 782
 783         if (cz_hwmgr->sclk_dpm.soft_min_clk != clock) {
 784                 cz_hwmgr->sclk_dpm.soft_min_clk = clock;
 785                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 786                                                 PPSMC_MSG_SetSclkSoftMin,
 787                                                 cz_get_sclk_level(hwmgr,
 788                                         cz_hwmgr->sclk_dpm.soft_min_clk,
 789                                              PPSMC_MSG_SetSclkSoftMin));
 790         }
 791
 792         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 793                                     PHM_PlatformCaps_StablePState) &&
 794                          cz_hwmgr->sclk_dpm.soft_max_clk != clock) {
 795                 cz_hwmgr->sclk_dpm.soft_max_clk = clock;
 796                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 797                                                 PPSMC_MSG_SetSclkSoftMax,
 798                                                 cz_get_sclk_level(hwmgr,
 799                                         cz_hwmgr->sclk_dpm.soft_max_clk,
 800                                         PPSMC_MSG_SetSclkSoftMax));
 801         }
 802
 803         return 0;
 804 }
 805
 806 static int cz_tf_set_deep_sleep_sclk_threshold(struct pp_hwmgr *hwmgr,
 807                                         void *input, void *output,
 808                                         void *storage, int result)
 809 {
 810         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 811                                 PHM_PlatformCaps_SclkDeepSleep)) {
 812                 uint32_t clks = hwmgr->display_config.min_core_set_clock_in_sr;
 813                 if (clks == 0)
 814                         clks = CZ_MIN_DEEP_SLEEP_SCLK;
 815
 816                 PP_DBG_LOG("Setting Deep Sleep Clock: %d\n", clks);
 817
 818                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 819                                 PPSMC_MSG_SetMinDeepSleepSclk,
 820                                 clks);
 821         }
 822
 823         return 0;
 824 }
 825
 826 static int cz_tf_set_watermark_threshold(struct pp_hwmgr *hwmgr,
 827                                         void *input, void *output,
 828                                         void *storage, int result)
 829 {
 830         struct cz_hwmgr *cz_hwmgr =
 831                                   (struct cz_hwmgr *)(hwmgr->backend);
 832
 833         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 834                                         PPSMC_MSG_SetWatermarkFrequency,
 835                                       cz_hwmgr->sclk_dpm.soft_max_clk);
 836
 837         return 0;
 838 }
 839
 840 static int cz_tf_set_enabled_levels(struct pp_hwmgr *hwmgr,
 841                                         void *input, void *output,
 842                                         void *storage, int result)
 843 {
 844         return 0;
 845 }
 846
 847
 848 static int cz_tf_enable_nb_dpm(struct pp_hwmgr *hwmgr,
 849                                         void *input, void *output,
 850                                         void *storage, int result)
 851 {
 852         int ret = 0;
 853
 854         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
 855         unsigned long dpm_features = 0;
 856
 857         if (!cz_hwmgr->is_nb_dpm_enabled) {
 858                 PP_DBG_LOG("enabling ALL SMU features.\n");
 859                 dpm_features |= NB_DPM_MASK;
 860                 ret = smum_send_msg_to_smc_with_parameter(
 861                                                              hwmgr->smumgr,
 862                                          PPSMC_MSG_EnableAllSmuFeatures,
 863                                                              dpm_features);
 864                 if (ret == 0)
 865                         cz_hwmgr->is_nb_dpm_enabled = true;
 866         }
 867
 868         return ret;
 869 }
 870
 871 static int cz_nbdpm_pstate_enable_disable(struct pp_hwmgr *hwmgr, bool enable, bool lock)
 872 {
 873         struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
 874
 875         if (hw_data->is_nb_dpm_enabled) {
 876                 if (enable) {
 877                         PP_DBG_LOG("enable Low Memory PState.\n");
 878
 879                         return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 880                                                 PPSMC_MSG_EnableLowMemoryPstate,
 881                                                 (lock ? 1 : 0));
 882                 } else {
 883                         PP_DBG_LOG("disable Low Memory PState.\n");
 884
 885                         return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 886                                                 PPSMC_MSG_DisableLowMemoryPstate,
 887                                                 (lock ? 1 : 0));
 888                 }
 889         }
 890
 891         return 0;
 892 }
 893
 894 static int cz_tf_update_low_mem_pstate(struct pp_hwmgr *hwmgr,
 895                                         void *input, void *output,
 896                                         void *storage, int result)
 897 {
 898         bool disable_switch;
 899         bool enable_low_mem_state;
 900         struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
 901         const struct phm_set_power_state_input *states = (struct phm_set_power_state_input *)input;
 902         const struct cz_power_state *pnew_state = cast_const_PhwCzPowerState(states->pnew_state);
 903
 904         if (hw_data->sys_info.nb_dpm_enable) {
 905                 disable_switch = hw_data->cc6_settings.nb_pstate_switch_disable ? true : false;
 906                 enable_low_mem_state = hw_data->cc6_settings.nb_pstate_switch_disable ? false : true;
 907
 908                 if (pnew_state->action == FORCE_HIGH)
 909                         cz_nbdpm_pstate_enable_disable(hwmgr, false, disable_switch);
 910                 else if (pnew_state->action == CANCEL_FORCE_HIGH)
 911                         cz_nbdpm_pstate_enable_disable(hwmgr, true, disable_switch);
 912                 else
 913                         cz_nbdpm_pstate_enable_disable(hwmgr, enable_low_mem_state, disable_switch);
 914         }
 915         return 0;
 916 }
 917
 918 static const struct phm_master_table_item cz_set_power_state_list[] = {
 919         {NULL, cz_tf_update_sclk_limit},
 920         {NULL, cz_tf_set_deep_sleep_sclk_threshold},
 921         {NULL, cz_tf_set_watermark_threshold},
 922         {NULL, cz_tf_set_enabled_levels},
 923         {NULL, cz_tf_enable_nb_dpm},
 924         {NULL, cz_tf_update_low_mem_pstate},
 925         {NULL, NULL}
 926 };
 927
 928 static const struct phm_master_table_header cz_set_power_state_master = {
 929         0,
 930         PHM_MasterTableFlag_None,
 931         cz_set_power_state_list
 932 };
 933
 934 static const struct phm_master_table_item cz_setup_asic_list[] = {
 935         {NULL, cz_tf_reset_active_process_mask},
 936         {NULL, cz_tf_upload_pptable_to_smu},
 937         {NULL, cz_tf_init_sclk_limit},
 938         {NULL, cz_tf_init_uvd_limit},
 939         {NULL, cz_tf_init_vce_limit},
 940         {NULL, cz_tf_init_acp_limit},
 941         {NULL, cz_tf_init_power_gate_state},
 942         {NULL, cz_tf_init_sclk_threshold},
 943         {NULL, NULL}
 944 };
 945
 946 static const struct phm_master_table_header cz_setup_asic_master = {
 947         0,
 948         PHM_MasterTableFlag_None,
 949         cz_setup_asic_list
 950 };
 951
 952 static int cz_tf_power_up_display_clock_sys_pll(struct pp_hwmgr *hwmgr,
 953                                         void *input, void *output,
 954                                         void *storage, int result)
 955 {
 956         struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
 957         hw_data->disp_clk_bypass_pending = false;
 958         hw_data->disp_clk_bypass = false;
 959
 960         return 0;
 961 }
 962
 963 static int cz_tf_clear_nb_dpm_flag(struct pp_hwmgr *hwmgr,
 964                                         void *input, void *output,
 965                                         void *storage, int result)
 966 {
 967         struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
 968         hw_data->is_nb_dpm_enabled = false;
 969
 970         return 0;
 971 }
 972
 973 static int cz_tf_reset_cc6_data(struct pp_hwmgr *hwmgr,
 974                                         void *input, void *output,
 975                                         void *storage, int result)
 976 {
 977         struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
 978
 979         hw_data->cc6_settings.cc6_setting_changed = false;
 980         hw_data->cc6_settings.cpu_pstate_separation_time = 0;
 981         hw_data->cc6_settings.cpu_cc6_disable = false;
 982         hw_data->cc6_settings.cpu_pstate_disable = false;
 983
 984         return 0;
 985 }
 986
 987 static const struct phm_master_table_item cz_power_down_asic_list[] = {
 988         {NULL, cz_tf_power_up_display_clock_sys_pll},
 989         {NULL, cz_tf_clear_nb_dpm_flag},
 990         {NULL, cz_tf_reset_cc6_data},
 991         {NULL, NULL}
 992 };
 993
 994 static const struct phm_master_table_header cz_power_down_asic_master = {
 995         0,
 996         PHM_MasterTableFlag_None,
 997         cz_power_down_asic_list
 998 };
 999
1000 static int cz_tf_program_voting_clients(struct pp_hwmgr *hwmgr, void *input,
1001                                 void *output, void *storage, int result)
1002 {
1003         PHMCZ_WRITE_SMC_REGISTER(hwmgr->device, CG_FREQ_TRAN_VOTING_0,
1004                                 PPCZ_VOTINGRIGHTSCLIENTS_DFLT0);
1005         return 0;
1006 }
1007
1008 static int cz_tf_start_dpm(struct pp_hwmgr *hwmgr, void *input, void *output,
1009                            void *storage, int result)
1010 {
1011         int res = 0xff;
1012         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1013         unsigned long dpm_features = 0;
1014
1015         cz_hwmgr->dpm_flags |= DPMFlags_SCLK_Enabled;
1016         dpm_features |= SCLK_DPM_MASK;
1017
1018         res = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1019                                 PPSMC_MSG_EnableAllSmuFeatures,
1020                                 dpm_features);
1021
1022         return res;
1023 }
1024
1025 static int cz_tf_program_bootup_state(struct pp_hwmgr *hwmgr, void *input,
1026                                 void *output, void *storage, int result)
1027 {
1028         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1029
1030         cz_hwmgr->sclk_dpm.soft_min_clk = cz_hwmgr->sys_info.bootup_engine_clock;
1031         cz_hwmgr->sclk_dpm.soft_max_clk = cz_hwmgr->sys_info.bootup_engine_clock;
1032
1033         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1034                                 PPSMC_MSG_SetSclkSoftMin,
1035                                 cz_get_sclk_level(hwmgr,
1036                                 cz_hwmgr->sclk_dpm.soft_min_clk,
1037                                 PPSMC_MSG_SetSclkSoftMin));
1038
1039         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1040                                 PPSMC_MSG_SetSclkSoftMax,
1041                                 cz_get_sclk_level(hwmgr,
1042                                 cz_hwmgr->sclk_dpm.soft_max_clk,
1043                                 PPSMC_MSG_SetSclkSoftMax));
1044
1045         return 0;
1046 }
1047
1048 int cz_tf_reset_acp_boot_level(struct pp_hwmgr *hwmgr, void *input,
1049                                 void *output, void *storage, int result)
1050 {
1051         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1052
1053         cz_hwmgr->acp_boot_level = 0xff;
1054         return 0;
1055 }
1056
1057 static bool cz_dpm_check_smu_features(struct pp_hwmgr *hwmgr,
1058                                 unsigned long check_feature)
1059 {
1060         int result;
1061         unsigned long features;
1062
1063         result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_GetFeatureStatus, 0);
1064         if (result == 0) {
1065                 features = smum_get_argument(hwmgr->smumgr);
1066                 if (features & check_feature)
1067                         return true;
1068         }
1069
1070         return result;
1071 }
1072
1073 static int cz_tf_check_for_dpm_disabled(struct pp_hwmgr *hwmgr, void *input,
1074                                 void *output, void *storage, int result)
1075 {
1076         if (cz_dpm_check_smu_features(hwmgr, SMU_EnabledFeatureScoreboard_SclkDpmOn))
1077                 return PP_Result_TableImmediateExit;
1078         return 0;
1079 }
1080
1081 static int cz_tf_enable_didt(struct pp_hwmgr *hwmgr, void *input,
1082                                 void *output, void *storage, int result)
1083 {
1084         /* TO DO */
1085         return 0;
1086 }
1087
1088 static int cz_tf_check_for_dpm_enabled(struct pp_hwmgr *hwmgr,
1089                                                 void *input, void *output,
1090                                                 void *storage, int result)
1091 {
1092         if (!cz_dpm_check_smu_features(hwmgr,
1093                              SMU_EnabledFeatureScoreboard_SclkDpmOn))
1094                 return PP_Result_TableImmediateExit;
1095         return 0;
1096 }
1097
1098 static const struct phm_master_table_item cz_disable_dpm_list[] = {
1099         { NULL, cz_tf_check_for_dpm_enabled},
1100         {NULL, NULL},
1101 };
1102
1103
1104 static const struct phm_master_table_header cz_disable_dpm_master = {
1105         0,
1106         PHM_MasterTableFlag_None,
1107         cz_disable_dpm_list
1108 };
1109
1110 static const struct phm_master_table_item cz_enable_dpm_list[] = {
1111         { NULL, cz_tf_check_for_dpm_disabled },
1112         { NULL, cz_tf_program_voting_clients },
1113         { NULL, cz_tf_start_dpm},
1114         { NULL, cz_tf_program_bootup_state},
1115         { NULL, cz_tf_enable_didt },
1116         { NULL, cz_tf_reset_acp_boot_level },
1117         {NULL, NULL},
1118 };
1119
1120 static const struct phm_master_table_header cz_enable_dpm_master = {
1121         0,
1122         PHM_MasterTableFlag_None,
1123         cz_enable_dpm_list
1124 };
1125
1126 static int cz_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
1127                                 struct pp_power_state  *prequest_ps,
1128                         const struct pp_power_state *pcurrent_ps)
1129 {
1130         struct cz_power_state *cz_ps =
1131                                 cast_PhwCzPowerState(&prequest_ps->hardware);
1132
1133         const struct cz_power_state *cz_current_ps =
1134                                 cast_const_PhwCzPowerState(&pcurrent_ps->hardware);
1135
1136         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1137         struct PP_Clocks clocks = {0, 0, 0, 0};
1138         bool force_high;
1139         uint32_t  num_of_active_displays = 0;
1140         struct cgs_display_info info = {0};
1141
1142         cz_ps->evclk = hwmgr->vce_arbiter.evclk;
1143         cz_ps->ecclk = hwmgr->vce_arbiter.ecclk;
1144
1145         cz_ps->need_dfs_bypass = true;
1146
1147         cz_hwmgr->video_start = (hwmgr->uvd_arbiter.vclk != 0 || hwmgr->uvd_arbiter.dclk != 0 ||
1148                                 hwmgr->vce_arbiter.evclk != 0 || hwmgr->vce_arbiter.ecclk != 0);
1149
1150         cz_hwmgr->battery_state = (PP_StateUILabel_Battery == prequest_ps->classification.ui_label);
1151
1152         clocks.memoryClock = hwmgr->display_config.min_mem_set_clock != 0 ?
1153                                 hwmgr->display_config.min_mem_set_clock :
1154                                 cz_hwmgr->sys_info.nbp_memory_clock[1];
1155
1156         cgs_get_active_displays_info(hwmgr->device, &info);
1157         num_of_active_displays = info.display_count;
1158
1159         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
1160                 clocks.memoryClock = hwmgr->dyn_state.max_clock_voltage_on_ac.mclk;
1161
1162         if (clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
1163                 clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
1164
1165         force_high = (clocks.memoryClock > cz_hwmgr->sys_info.nbp_memory_clock[CZ_NUM_NBPMEMORYCLOCK - 1])
1166                         || (num_of_active_displays >= 3);
1167
1168         cz_ps->action = cz_current_ps->action;
1169
1170         if (!force_high && (cz_ps->action == FORCE_HIGH))
1171                 cz_ps->action = CANCEL_FORCE_HIGH;
1172         else if (force_high && (cz_ps->action != FORCE_HIGH))
1173                 cz_ps->action = FORCE_HIGH;
1174         else
1175                 cz_ps->action = DO_NOTHING;
1176
1177         return 0;
1178 }
1179
1180 static int cz_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
1181 {
1182         int result = 0;
1183         struct cz_hwmgr *data;
1184
1185         data = kzalloc(sizeof(struct cz_hwmgr), GFP_KERNEL);
1186         if (data == NULL)
1187                 return -ENOMEM;
1188
1189         hwmgr->backend = data;
1190
1191         result = cz_initialize_dpm_defaults(hwmgr);
1192         if (result != 0) {
1193                 printk(KERN_ERR "[ powerplay ] cz_initialize_dpm_defaults failed\n");
1194                 return result;
1195         }
1196
1197         result = cz_get_system_info_data(hwmgr);
1198         if (result != 0) {
1199                 printk(KERN_ERR "[ powerplay ] cz_get_system_info_data failed\n");
1200                 return result;
1201         }
1202
1203         cz_construct_boot_state(hwmgr);
1204
1205         result = phm_construct_table(hwmgr, &cz_setup_asic_master,
1206                                 &(hwmgr->setup_asic));
1207         if (result != 0) {
1208                 printk(KERN_ERR "[ powerplay ] Fail to construct setup ASIC\n");
1209                 return result;
1210         }
1211
1212         result = phm_construct_table(hwmgr, &cz_power_down_asic_master,
1213                                 &(hwmgr->power_down_asic));
1214         if (result != 0) {
1215                 printk(KERN_ERR "[ powerplay ] Fail to construct power down ASIC\n");
1216                 return result;
1217         }
1218
1219         result = phm_construct_table(hwmgr, &cz_disable_dpm_master,
1220                                 &(hwmgr->disable_dynamic_state_management));
1221         if (result != 0) {
1222                 printk(KERN_ERR "[ powerplay ] Fail to disable_dynamic_state\n");
1223                 return result;
1224         }
1225         result = phm_construct_table(hwmgr, &cz_enable_dpm_master,
1226                                 &(hwmgr->enable_dynamic_state_management));
1227         if (result != 0) {
1228                 printk(KERN_ERR "[ powerplay ] Fail to enable_dynamic_state\n");
1229                 return result;
1230         }
1231         result = phm_construct_table(hwmgr, &cz_set_power_state_master,
1232                                 &(hwmgr->set_power_state));
1233         if (result != 0) {
1234                 printk(KERN_ERR "[ powerplay ] Fail to construct set_power_state\n");
1235                 return result;
1236         }
1237         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =  CZ_MAX_HARDWARE_POWERLEVELS;
1238
1239         result = phm_construct_table(hwmgr, &cz_phm_enable_clock_power_gatings_master, &(hwmgr->enable_clock_power_gatings));
1240         if (result != 0) {
1241                 printk(KERN_ERR "[ powerplay ] Fail to construct enable_clock_power_gatings\n");
1242                 return result;
1243         }
1244         return result;
1245 }
1246
1247 static int cz_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
1248 {
1249         if (hwmgr != NULL || hwmgr->backend != NULL) {
1250                 kfree(hwmgr->backend);
1251                 kfree(hwmgr);
1252         }
1253         return 0;
1254 }
1255
1256 int cz_phm_force_dpm_highest(struct pp_hwmgr *hwmgr)
1257 {
1258         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1259
1260         if (cz_hwmgr->sclk_dpm.soft_min_clk !=
1261                                 cz_hwmgr->sclk_dpm.soft_max_clk)
1262                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1263                                                 PPSMC_MSG_SetSclkSoftMin,
1264                                                 cz_get_sclk_level(hwmgr,
1265                                                 cz_hwmgr->sclk_dpm.soft_max_clk,
1266                                                 PPSMC_MSG_SetSclkSoftMin));
1267         return 0;
1268 }
1269
1270 int cz_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
1271 {
1272         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1273         struct phm_clock_voltage_dependency_table *table =
1274                                 hwmgr->dyn_state.vddc_dependency_on_sclk;
1275         unsigned long clock = 0, level;
1276
1277         if (NULL == table || table->count <= 0)
1278                 return -EINVAL;
1279
1280         cz_hwmgr->sclk_dpm.soft_min_clk = table->entries[0].clk;
1281         cz_hwmgr->sclk_dpm.hard_min_clk = table->entries[0].clk;
1282
1283         level = cz_get_max_sclk_level(hwmgr) - 1;
1284
1285         if (level < table->count)
1286                 clock = table->entries[level].clk;
1287         else
1288                 clock = table->entries[table->count - 1].clk;
1289
1290         cz_hwmgr->sclk_dpm.soft_max_clk = clock;
1291         cz_hwmgr->sclk_dpm.hard_max_clk = clock;
1292
1293         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1294                                 PPSMC_MSG_SetSclkSoftMin,
1295                                 cz_get_sclk_level(hwmgr,
1296                                 cz_hwmgr->sclk_dpm.soft_min_clk,
1297                                 PPSMC_MSG_SetSclkSoftMin));
1298
1299         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1300                                 PPSMC_MSG_SetSclkSoftMax,
1301                                 cz_get_sclk_level(hwmgr,
1302                                 cz_hwmgr->sclk_dpm.soft_max_clk,
1303                                 PPSMC_MSG_SetSclkSoftMax));
1304
1305         return 0;
1306 }
1307
1308 int cz_phm_force_dpm_lowest(struct pp_hwmgr *hwmgr)
1309 {
1310         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1311
1312         if (cz_hwmgr->sclk_dpm.soft_min_clk !=
1313                                 cz_hwmgr->sclk_dpm.soft_max_clk) {
1314                 cz_hwmgr->sclk_dpm.soft_max_clk =
1315                         cz_hwmgr->sclk_dpm.soft_min_clk;
1316
1317                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1318                                 PPSMC_MSG_SetSclkSoftMax,
1319                                 cz_get_sclk_level(hwmgr,
1320                                 cz_hwmgr->sclk_dpm.soft_max_clk,
1321                                 PPSMC_MSG_SetSclkSoftMax));
1322         }
1323
1324         return 0;
1325 }
1326
1327 static int cz_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
1328                                 enum amd_dpm_forced_level level)
1329 {
1330         int ret = 0;
1331
1332         switch (level) {
1333         case AMD_DPM_FORCED_LEVEL_HIGH:
1334                 ret = cz_phm_force_dpm_highest(hwmgr);
1335                 if (ret)
1336                         return ret;
1337                 break;
1338         case AMD_DPM_FORCED_LEVEL_LOW:
1339                 ret = cz_phm_force_dpm_lowest(hwmgr);
1340                 if (ret)
1341                         return ret;
1342                 break;
1343         case AMD_DPM_FORCED_LEVEL_AUTO:
1344                 ret = cz_phm_unforce_dpm_levels(hwmgr);
1345                 if (ret)
1346                         return ret;
1347                 break;
1348         default:
1349                 break;
1350         }
1351
1352         hwmgr->dpm_level = level;
1353
1354         return ret;
1355 }
1356
1357 int cz_dpm_powerdown_uvd(struct pp_hwmgr *hwmgr)
1358 {
1359         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1360                                          PHM_PlatformCaps_UVDPowerGating))
1361                 return smum_send_msg_to_smc(hwmgr->smumgr,
1362                                                      PPSMC_MSG_UVDPowerOFF);
1363         return 0;
1364 }
1365
1366 int cz_dpm_powerup_uvd(struct pp_hwmgr *hwmgr)
1367 {
1368         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1369                                          PHM_PlatformCaps_UVDPowerGating)) {
1370                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1371                                   PHM_PlatformCaps_UVDDynamicPowerGating)) {
1372                         return smum_send_msg_to_smc_with_parameter(
1373                                                                 hwmgr->smumgr,
1374                                                    PPSMC_MSG_UVDPowerON, 1);
1375                 } else {
1376                         return smum_send_msg_to_smc_with_parameter(
1377                                                                 hwmgr->smumgr,
1378                                                    PPSMC_MSG_UVDPowerON, 0);
1379                 }
1380         }
1381
1382         return 0;
1383 }
1384
1385 int cz_dpm_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
1386 {
1387         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1388         struct phm_uvd_clock_voltage_dependency_table *ptable =
1389                 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
1390
1391         if (!bgate) {
1392                 /* Stable Pstate is enabled and we need to set the UVD DPM to highest level */
1393                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1394                                          PHM_PlatformCaps_StablePState)) {
1395                         cz_hwmgr->uvd_dpm.hard_min_clk =
1396                                    ptable->entries[ptable->count - 1].vclk;
1397
1398                         smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1399                                                      PPSMC_MSG_SetUvdHardMin,
1400                                                       cz_get_uvd_level(hwmgr,
1401                                              cz_hwmgr->uvd_dpm.hard_min_clk,
1402                                                    PPSMC_MSG_SetUvdHardMin));
1403
1404                         cz_enable_disable_uvd_dpm(hwmgr, true);
1405                 } else
1406                         cz_enable_disable_uvd_dpm(hwmgr, true);
1407         } else
1408                 cz_enable_disable_uvd_dpm(hwmgr, false);
1409
1410         return 0;
1411 }
1412
1413 int  cz_dpm_update_vce_dpm(struct pp_hwmgr *hwmgr)
1414 {
1415         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1416         struct phm_vce_clock_voltage_dependency_table *ptable =
1417                 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
1418
1419         /* Stable Pstate is enabled and we need to set the VCE DPM to highest level */
1420         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1421                                          PHM_PlatformCaps_StablePState)) {
1422                 cz_hwmgr->vce_dpm.hard_min_clk =
1423                                   ptable->entries[ptable->count - 1].ecclk;
1424
1425                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1426                                         PPSMC_MSG_SetEclkHardMin,
1427                                         cz_get_eclk_level(hwmgr,
1428                                              cz_hwmgr->vce_dpm.hard_min_clk,
1429                                                 PPSMC_MSG_SetEclkHardMin));
1430         } else {
1431                 /*EPR# 419220 -HW limitation to to */
1432                 cz_hwmgr->vce_dpm.hard_min_clk = hwmgr->vce_arbiter.ecclk;
1433                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1434                                             PPSMC_MSG_SetEclkHardMin,
1435                                             cz_get_eclk_level(hwmgr,
1436                                      cz_hwmgr->vce_dpm.hard_min_clk,
1437                                           PPSMC_MSG_SetEclkHardMin));
1438
1439         }
1440         return 0;
1441 }
1442
1443 int cz_dpm_powerdown_vce(struct pp_hwmgr *hwmgr)
1444 {
1445         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1446                                          PHM_PlatformCaps_VCEPowerGating))
1447                 return smum_send_msg_to_smc(hwmgr->smumgr,
1448                                                      PPSMC_MSG_VCEPowerOFF);
1449         return 0;
1450 }
1451
1452 int cz_dpm_powerup_vce(struct pp_hwmgr *hwmgr)
1453 {
1454         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1455                                          PHM_PlatformCaps_VCEPowerGating))
1456                 return smum_send_msg_to_smc(hwmgr->smumgr,
1457                                                      PPSMC_MSG_VCEPowerON);
1458         return 0;
1459 }
1460
1461 static int cz_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
1462 {
1463         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1464
1465         return cz_hwmgr->sys_info.bootup_uma_clock;
1466 }
1467
1468 static int cz_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
1469 {
1470         struct pp_power_state  *ps;
1471         struct cz_power_state  *cz_ps;
1472
1473         if (hwmgr == NULL)
1474                 return -EINVAL;
1475
1476         ps = hwmgr->request_ps;
1477
1478         if (ps == NULL)
1479                 return -EINVAL;
1480
1481         cz_ps = cast_PhwCzPowerState(&ps->hardware);
1482
1483         if (low)
1484                 return cz_ps->levels[0].engineClock;
1485         else
1486                 return cz_ps->levels[cz_ps->level-1].engineClock;
1487 }
1488
1489 static int cz_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
1490                                         struct pp_hw_power_state *hw_ps)
1491 {
1492         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1493         struct cz_power_state *cz_ps = cast_PhwCzPowerState(hw_ps);
1494
1495         cz_ps->level = 1;
1496         cz_ps->nbps_flags = 0;
1497         cz_ps->bapm_flags = 0;
1498         cz_ps->levels[0] = cz_hwmgr->boot_power_level;
1499
1500         return 0;
1501 }
1502
1503 static int cz_dpm_get_pp_table_entry_callback(
1504                                                      struct pp_hwmgr *hwmgr,
1505                                            struct pp_hw_power_state *hw_ps,
1506                                                           unsigned int index,
1507                                                      const void *clock_info)
1508 {
1509         struct cz_power_state *cz_ps = cast_PhwCzPowerState(hw_ps);
1510
1511         const ATOM_PPLIB_CZ_CLOCK_INFO *cz_clock_info = clock_info;
1512
1513         struct phm_clock_voltage_dependency_table *table =
1514                                     hwmgr->dyn_state.vddc_dependency_on_sclk;
1515         uint8_t clock_info_index = cz_clock_info->index;
1516
1517         if (clock_info_index > (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1))
1518                 clock_info_index = (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1);
1519
1520         cz_ps->levels[index].engineClock = table->entries[clock_info_index].clk;
1521         cz_ps->levels[index].vddcIndex = (uint8_t)table->entries[clock_info_index].v;
1522
1523         cz_ps->level = index + 1;
1524
1525         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
1526                 cz_ps->levels[index].dsDividerIndex = 5;
1527                 cz_ps->levels[index].ssDividerIndex = 5;
1528         }
1529
1530         return 0;
1531 }
1532
1533 static int cz_dpm_get_num_of_pp_table_entries(struct pp_hwmgr *hwmgr)
1534 {
1535         int result;
1536         unsigned long ret = 0;
1537
1538         result = pp_tables_get_num_of_entries(hwmgr, &ret);
1539
1540         return result ? 0 : ret;
1541 }
1542
1543 static int cz_dpm_get_pp_table_entry(struct pp_hwmgr *hwmgr,
1544                     unsigned long entry, struct pp_power_state *ps)
1545 {
1546         int result;
1547         struct cz_power_state *cz_ps;
1548
1549         ps->hardware.magic = PhwCz_Magic;
1550
1551         cz_ps = cast_PhwCzPowerState(&(ps->hardware));
1552
1553         result = pp_tables_get_entry(hwmgr, entry, ps,
1554                         cz_dpm_get_pp_table_entry_callback);
1555
1556         cz_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK;
1557         cz_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK;
1558
1559         return result;
1560 }
1561
1562 int cz_get_power_state_size(struct pp_hwmgr *hwmgr)
1563 {
1564         return sizeof(struct cz_power_state);
1565 }
1566
1567 static void
1568 cz_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m)
1569 {
1570         struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
1571
1572         struct phm_clock_voltage_dependency_table *table =
1573                                 hwmgr->dyn_state.vddc_dependency_on_sclk;
1574
1575         struct phm_vce_clock_voltage_dependency_table *vce_table =
1576                 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
1577
1578         struct phm_uvd_clock_voltage_dependency_table *uvd_table =
1579                 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
1580
1581         uint32_t sclk_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX),
1582                                         TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX);
1583         uint32_t uvd_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
1584                                         TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_UVD_INDEX);
1585         uint32_t vce_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
1586                                         TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_VCE_INDEX);
1587
1588         uint32_t sclk, vclk, dclk, ecclk, tmp, activity_percent;
1589         uint16_t vddnb, vddgfx;
1590         int result;
1591
1592         if (sclk_index >= NUM_SCLK_LEVELS) {
1593                 seq_printf(m, "\n invalid sclk dpm profile %d\n", sclk_index);
1594         } else {
1595                 sclk = table->entries[sclk_index].clk;
1596                 seq_printf(m, "\n index: %u sclk: %u MHz\n", sclk_index, sclk/100);
1597         }
1598
1599         tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_NB_CURRENTVID) &
1600                 CURRENT_NB_VID_MASK) >> CURRENT_NB_VID__SHIFT;
1601         vddnb = cz_convert_8Bit_index_to_voltage(hwmgr, tmp);
1602         tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_GFX_CURRENTVID) &
1603                 CURRENT_GFX_VID_MASK) >> CURRENT_GFX_VID__SHIFT;
1604         vddgfx = cz_convert_8Bit_index_to_voltage(hwmgr, (u16)tmp);
1605         seq_printf(m, "\n vddnb: %u vddgfx: %u\n", vddnb, vddgfx);
1606
1607         seq_printf(m, "\n uvd    %sabled\n", cz_hwmgr->uvd_power_gated ? "dis" : "en");
1608         if (!cz_hwmgr->uvd_power_gated) {
1609                 if (uvd_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
1610                         seq_printf(m, "\n invalid uvd dpm level %d\n", uvd_index);
1611                 } else {
1612                         vclk = uvd_table->entries[uvd_index].vclk;
1613                         dclk = uvd_table->entries[uvd_index].dclk;
1614                         seq_printf(m, "\n index: %u uvd vclk: %u MHz dclk: %u MHz\n", uvd_index, vclk/100, dclk/100);
1615                 }
1616         }
1617
1618         seq_printf(m, "\n vce    %sabled\n", cz_hwmgr->vce_power_gated ? "dis" : "en");
1619         if (!cz_hwmgr->vce_power_gated) {
1620                 if (vce_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
1621                         seq_printf(m, "\n invalid vce dpm level %d\n", vce_index);
1622                 } else {
1623                         ecclk = vce_table->entries[vce_index].ecclk;
1624                         seq_printf(m, "\n index: %u vce ecclk: %u MHz\n", vce_index, ecclk/100);
1625                 }
1626         }
1627
1628         result = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetAverageGraphicsActivity);
1629         if (0 == result) {
1630                 activity_percent = cgs_read_register(hwmgr->device, mmSMU_MP1_SRBM2P_ARG_0);
1631                 activity_percent = activity_percent > 100 ? 100 : activity_percent;
1632         } else {
1633                 activity_percent = 50;
1634         }
1635
1636         seq_printf(m, "\n [GPU load]: %u %%\n\n", activity_percent);
1637 }
1638
1639 static void cz_hw_print_display_cfg(
1640         const struct cc6_settings *cc6_settings)
1641 {
1642         PP_DBG_LOG("New Display Configuration:\n");
1643
1644         PP_DBG_LOG("   cpu_cc6_disable: %d\n",
1645                         cc6_settings->cpu_cc6_disable);
1646         PP_DBG_LOG("   cpu_pstate_disable: %d\n",
1647                         cc6_settings->cpu_pstate_disable);
1648         PP_DBG_LOG("   nb_pstate_switch_disable: %d\n",
1649                         cc6_settings->nb_pstate_switch_disable);
1650         PP_DBG_LOG("   cpu_pstate_separation_time: %d\n\n",
1651                         cc6_settings->cpu_pstate_separation_time);
1652 }
1653
1654  static int cz_set_cpu_power_state(struct pp_hwmgr *hwmgr)
1655 {
1656         struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
1657         uint32_t data = 0;
1658
1659         if (hw_data->cc6_settings.cc6_setting_changed) {
1660
1661                 hw_data->cc6_settings.cc6_setting_changed = false;
1662
1663                 cz_hw_print_display_cfg(&hw_data->cc6_settings);
1664
1665                 data |= (hw_data->cc6_settings.cpu_pstate_separation_time
1666                         & PWRMGT_SEPARATION_TIME_MASK)
1667                         << PWRMGT_SEPARATION_TIME_SHIFT;
1668
1669                 data |= (hw_data->cc6_settings.cpu_cc6_disable ? 0x1 : 0x0)
1670                         << PWRMGT_DISABLE_CPU_CSTATES_SHIFT;
1671
1672                 data |= (hw_data->cc6_settings.cpu_pstate_disable ? 0x1 : 0x0)
1673                         << PWRMGT_DISABLE_CPU_PSTATES_SHIFT;
1674
1675                 PP_DBG_LOG("SetDisplaySizePowerParams data: 0x%X\n",
1676                         data);
1677
1678                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1679                                                 PPSMC_MSG_SetDisplaySizePowerParams,
1680                                                 data);
1681         }
1682
1683         return 0;
1684 }
1685
1686
1687 static int cz_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time,
1688                         bool cc6_disable, bool pstate_disable, bool pstate_switch_disable)
1689 {
1690         struct cz_hwmgr *hw_data = (struct cz_hwmgr *)(hwmgr->backend);
1691
1692         if (separation_time !=
1693                 hw_data->cc6_settings.cpu_pstate_separation_time
1694                 || cc6_disable !=
1695                 hw_data->cc6_settings.cpu_cc6_disable
1696                 || pstate_disable !=
1697                 hw_data->cc6_settings.cpu_pstate_disable
1698                 || pstate_switch_disable !=
1699                 hw_data->cc6_settings.nb_pstate_switch_disable) {
1700
1701                 hw_data->cc6_settings.cc6_setting_changed = true;
1702
1703                 hw_data->cc6_settings.cpu_pstate_separation_time =
1704                         separation_time;
1705                 hw_data->cc6_settings.cpu_cc6_disable =
1706                         cc6_disable;
1707                 hw_data->cc6_settings.cpu_pstate_disable =
1708                         pstate_disable;
1709                 hw_data->cc6_settings.nb_pstate_switch_disable =
1710                         pstate_switch_disable;
1711
1712         }
1713
1714         return 0;
1715 }
1716
1717 static int cz_get_dal_power_level(struct pp_hwmgr *hwmgr,
1718                 struct amd_pp_simple_clock_info *info)
1719 {
1720         uint32_t i;
1721         const struct phm_clock_voltage_dependency_table *table =
1722                         hwmgr->dyn_state.vddc_dep_on_dal_pwrl;
1723         const struct phm_clock_and_voltage_limits *limits =
1724                         &hwmgr->dyn_state.max_clock_voltage_on_ac;
1725
1726         info->engine_max_clock = limits->sclk;
1727         info->memory_max_clock = limits->mclk;
1728
1729         for (i = table->count - 1; i > 0; i--) {
1730                 if (limits->vddc >= table->entries[i].v) {
1731                         info->level = table->entries[i].clk;
1732                         return 0;
1733                 }
1734         }
1735         return -EINVAL;
1736 }
1737
1738 static int cz_force_clock_level(struct pp_hwmgr *hwmgr,
1739                 enum pp_clock_type type, uint32_t mask)
1740 {
1741         if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1742                 return -EINVAL;
1743
1744         switch (type) {
1745         case PP_SCLK:
1746                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1747                                 PPSMC_MSG_SetSclkSoftMin,
1748                                 mask);
1749                 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
1750                                 PPSMC_MSG_SetSclkSoftMax,
1751                                 mask);
1752                 break;
1753         default:
1754                 break;
1755         }
1756
1757         return 0;
1758 }
1759
1760 static int cz_print_clock_levels(struct pp_hwmgr *hwmgr,
1761                 enum pp_clock_type type, char *buf)
1762 {
1763         struct phm_clock_voltage_dependency_table *sclk_table =
1764                         hwmgr->dyn_state.vddc_dependency_on_sclk;
1765         int i, now, size = 0;
1766
1767         switch (type) {
1768         case PP_SCLK:
1769                 now = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device,
1770                                 CGS_IND_REG__SMC,
1771                                 ixTARGET_AND_CURRENT_PROFILE_INDEX),
1772                                 TARGET_AND_CURRENT_PROFILE_INDEX,
1773                                 CURR_SCLK_INDEX);
1774
1775                 for (i = 0; i < sclk_table->count; i++)
1776                         size += sprintf(buf + size, "%d: %uMhz %s\n",
1777                                         i, sclk_table->entries[i].clk / 100,
1778                                         (i == now) ? "*" : "");
1779                 break;
1780         default:
1781                 break;
1782         }
1783         return size;
1784 }
1785
1786 static int cz_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
1787                                 PHM_PerformanceLevelDesignation designation, uint32_t index,
1788                                 PHM_PerformanceLevel *level)
1789 {
1790         const struct cz_power_state *ps;
1791         struct cz_hwmgr *data;
1792         uint32_t level_index;
1793         uint32_t i;
1794
1795         if (level == NULL || hwmgr == NULL || state == NULL)
1796                 return -EINVAL;
1797
1798         data = (struct cz_hwmgr *)(hwmgr->backend);
1799         ps = cast_const_PhwCzPowerState(state);
1800
1801         level_index = index > ps->level - 1 ? ps->level - 1 : index;
1802
1803         level->coreClock  = ps->levels[level_index].engineClock;
1804
1805         if (designation == PHM_PerformanceLevelDesignation_PowerContainment) {
1806                 for (i = 1; i < ps->level; i++) {
1807                         if (ps->levels[i].engineClock > data->dce_slow_sclk_threshold) {
1808                                 level->coreClock = ps->levels[i].engineClock;
1809                                 break;
1810                         }
1811                 }
1812         }
1813
1814         if (level_index == 0)
1815                 level->memory_clock = data->sys_info.nbp_memory_clock[CZ_NUM_NBPMEMORYCLOCK - 1];
1816         else
1817                 level->memory_clock = data->sys_info.nbp_memory_clock[0];
1818
1819         level->vddc = (cz_convert_8Bit_index_to_voltage(hwmgr, ps->levels[level_index].vddcIndex) + 2) / 4;
1820         level->nonLocalMemoryFreq = 0;
1821         level->nonLocalMemoryWidth = 0;
1822
1823         return 0;
1824 }
1825
1826 static int cz_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr,
1827         const struct pp_hw_power_state *state, struct pp_clock_info *clock_info)
1828 {
1829         const struct cz_power_state *ps = cast_const_PhwCzPowerState(state);
1830
1831         clock_info->min_eng_clk = ps->levels[0].engineClock / (1 << (ps->levels[0].ssDividerIndex));
1832         clock_info->max_eng_clk = ps->levels[ps->level - 1].engineClock / (1 << (ps->levels[ps->level - 1].ssDividerIndex));
1833
1834         return 0;
1835 }
1836
1837 static int cz_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type,
1838                                                 struct amd_pp_clocks *clocks)
1839 {
1840         struct cz_hwmgr *data = (struct cz_hwmgr *)(hwmgr->backend);
1841         int i;
1842         struct phm_clock_voltage_dependency_table *table;
1843
1844         clocks->count = cz_get_max_sclk_level(hwmgr);
1845         switch (type) {
1846         case amd_pp_disp_clock:
1847                 for (i = 0; i < clocks->count; i++)
1848                         clocks->clock[i] = data->sys_info.display_clock[i];
1849                 break;
1850         case amd_pp_sys_clock:
1851                 table = hwmgr->dyn_state.vddc_dependency_on_sclk;
1852                 for (i = 0; i < clocks->count; i++)
1853                         clocks->clock[i] = table->entries[i].clk;
1854                 break;
1855         case amd_pp_mem_clock:
1856                 clocks->count = CZ_NUM_NBPMEMORYCLOCK;
1857                 for (i = 0; i < clocks->count; i++)
1858                         clocks->clock[i] = data->sys_info.nbp_memory_clock[clocks->count - 1 - i];
1859                 break;
1860         default:
1861                 return -1;
1862         }
1863
1864         return 0;
1865 }
1866
1867 static int cz_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks)
1868 {
1869         struct phm_clock_voltage_dependency_table *table =
1870                                         hwmgr->dyn_state.vddc_dependency_on_sclk;
1871         unsigned long level;
1872         const struct phm_clock_and_voltage_limits *limits =
1873                         &hwmgr->dyn_state.max_clock_voltage_on_ac;
1874
1875         if ((NULL == table) || (table->count <= 0) || (clocks == NULL))
1876                 return -EINVAL;
1877
1878         level = cz_get_max_sclk_level(hwmgr) - 1;
1879
1880         if (level < table->count)
1881                 clocks->engine_max_clock = table->entries[level].clk;
1882         else
1883                 clocks->engine_max_clock = table->entries[table->count - 1].clk;
1884
1885         clocks->memory_max_clock = limits->mclk;
1886
1887         return 0;
1888 }
1889
1890 static const struct pp_hwmgr_func cz_hwmgr_funcs = {
1891         .backend_init = cz_hwmgr_backend_init,
1892         .backend_fini = cz_hwmgr_backend_fini,
1893         .asic_setup = NULL,
1894         .apply_state_adjust_rules = cz_apply_state_adjust_rules,
1895         .force_dpm_level = cz_dpm_force_dpm_level,
1896         .get_power_state_size = cz_get_power_state_size,
1897         .powerdown_uvd = cz_dpm_powerdown_uvd,
1898         .powergate_uvd = cz_dpm_powergate_uvd,
1899         .powergate_vce = cz_dpm_powergate_vce,
1900         .get_mclk = cz_dpm_get_mclk,
1901         .get_sclk = cz_dpm_get_sclk,
1902         .patch_boot_state = cz_dpm_patch_boot_state,
1903         .get_pp_table_entry = cz_dpm_get_pp_table_entry,
1904         .get_num_of_pp_table_entries = cz_dpm_get_num_of_pp_table_entries,
1905         .print_current_perforce_level = cz_print_current_perforce_level,
1906         .set_cpu_power_state = cz_set_cpu_power_state,
1907         .store_cc6_data = cz_store_cc6_data,
1908         .force_clock_level = cz_force_clock_level,
1909         .print_clock_levels = cz_print_clock_levels,
1910         .get_dal_power_level = cz_get_dal_power_level,
1911         .get_performance_level = cz_get_performance_level,
1912         .get_current_shallow_sleep_clocks = cz_get_current_shallow_sleep_clocks,
1913         .get_clock_by_type = cz_get_clock_by_type,
1914         .get_max_high_clocks = cz_get_max_high_clocks,
1915 };
1916
1917 int cz_hwmgr_init(struct pp_hwmgr *hwmgr)
1918 {
1919         hwmgr->hwmgr_func = &cz_hwmgr_funcs;
1920         hwmgr->pptable_func = &pptable_funcs;
1921         return 0;
1922 }