drivers/gpu/drm/amd/powerplay/inc/hwmgr.h

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #ifndef _HWMGR_H_
  24 #define _HWMGR_H_
  25
  26 #include <linux/seq_file.h>
  27 #include "amd_powerplay.h"
  28 #include "pp_instance.h"
  29 #include "hardwaremanager.h"
  30 #include "pp_power_source.h"
  31 #include "hwmgr_ppt.h"
  32 #include "ppatomctrl.h"
  33 #include "hwmgr_ppt.h"
  34
  35 struct pp_instance;
  36 struct pp_hwmgr;
  37 struct pp_hw_power_state;
  38 struct pp_power_state;
  39 struct PP_VCEState;
  40 struct phm_fan_speed_info;
  41 struct pp_atomctrl_voltage_table;
  42
  43
  44 enum DISPLAY_GAP {
  45         DISPLAY_GAP_VBLANK_OR_WM = 0,   /* Wait for vblank or MCHG watermark. */
  46         DISPLAY_GAP_VBLANK       = 1,   /* Wait for vblank. */
  47         DISPLAY_GAP_WATERMARK    = 2,   /* Wait for MCHG watermark. (Note that HW may deassert WM in VBI depending on DC_STUTTER_CNTL.) */
  48         DISPLAY_GAP_IGNORE       = 3    /* Do not wait. */
  49 };
  50 typedef enum DISPLAY_GAP DISPLAY_GAP;
  51
  52
  53 struct vi_dpm_level {
  54         bool enabled;
  55         uint32_t value;
  56         uint32_t param1;
  57 };
  58
  59 struct vi_dpm_table {
  60         uint32_t count;
  61         struct vi_dpm_level dpm_level[1];
  62 };
  63
  64 enum PP_Result {
  65         PP_Result_TableImmediateExit = 0x13,
  66 };
  67
  68 #define PCIE_PERF_REQ_REMOVE_REGISTRY   0
  69 #define PCIE_PERF_REQ_FORCE_LOWPOWER    1
  70 #define PCIE_PERF_REQ_GEN1         2
  71 #define PCIE_PERF_REQ_GEN2         3
  72 #define PCIE_PERF_REQ_GEN3         4
  73
  74 enum PHM_BackEnd_Magic {
  75         PHM_Dummy_Magic       = 0xAA5555AA,
  76         PHM_RV770_Magic       = 0xDCBAABCD,
  77         PHM_Kong_Magic        = 0x239478DF,
  78         PHM_NIslands_Magic    = 0x736C494E,
  79         PHM_Sumo_Magic        = 0x8339FA11,
  80         PHM_SIslands_Magic    = 0x369431AC,
  81         PHM_Trinity_Magic     = 0x96751873,
  82         PHM_CIslands_Magic    = 0x38AC78B0,
  83         PHM_Kv_Magic          = 0xDCBBABC0,
  84         PHM_VIslands_Magic    = 0x20130307,
  85         PHM_Cz_Magic          = 0x67DCBA25
  86 };
  87
  88
  89 #define PHM_PCIE_POWERGATING_TARGET_GFX            0
  90 #define PHM_PCIE_POWERGATING_TARGET_DDI            1
  91 #define PHM_PCIE_POWERGATING_TARGET_PLLCASCADE     2
  92 #define PHM_PCIE_POWERGATING_TARGET_PHY            3
  93
  94 typedef int (*phm_table_function)(struct pp_hwmgr *hwmgr, void *input,
  95                                   void *output, void *storage, int result);
  96
  97 typedef bool (*phm_check_function)(struct pp_hwmgr *hwmgr);
  98
  99 struct phm_set_power_state_input {
 100         const struct pp_hw_power_state *pcurrent_state;
 101         const struct pp_hw_power_state *pnew_state;
 102 };
 103
 104 struct phm_acp_arbiter {
 105         uint32_t acpclk;
 106 };
 107
 108 struct phm_uvd_arbiter {
 109         uint32_t vclk;
 110         uint32_t dclk;
 111         uint32_t vclk_ceiling;
 112         uint32_t dclk_ceiling;
 113 };
 114
 115 struct phm_vce_arbiter {
 116         uint32_t   evclk;
 117         uint32_t   ecclk;
 118 };
 119
 120 struct phm_gfx_arbiter {
 121         uint32_t sclk;
 122         uint32_t mclk;
 123         uint32_t sclk_over_drive;
 124         uint32_t mclk_over_drive;
 125         uint32_t sclk_threshold;
 126         uint32_t num_cus;
 127 };
 128
 129 /* Entries in the master tables */
 130 struct phm_master_table_item {
 131         phm_check_function isFunctionNeededInRuntimeTable;
 132         phm_table_function tableFunction;
 133 };
 134
 135 enum phm_master_table_flag {
 136         PHM_MasterTableFlag_None         = 0,
 137         PHM_MasterTableFlag_ExitOnError  = 1,
 138 };
 139
 140 /* The header of the master tables */
 141 struct phm_master_table_header {
 142         uint32_t storage_size;
 143         uint32_t flags;
 144         const struct phm_master_table_item *master_list;
 145 };
 146
 147 struct phm_runtime_table_header {
 148         uint32_t storage_size;
 149         bool exit_error;
 150         phm_table_function *function_list;
 151 };
 152
 153 struct phm_clock_array {
 154         uint32_t count;
 155         uint32_t values[1];
 156 };
 157
 158 struct phm_clock_voltage_dependency_record {
 159         uint32_t clk;
 160         uint32_t v;
 161 };
 162
 163 struct phm_vceclock_voltage_dependency_record {
 164         uint32_t ecclk;
 165         uint32_t evclk;
 166         uint32_t v;
 167 };
 168
 169 struct phm_uvdclock_voltage_dependency_record {
 170         uint32_t vclk;
 171         uint32_t dclk;
 172         uint32_t v;
 173 };
 174
 175 struct phm_samuclock_voltage_dependency_record {
 176         uint32_t samclk;
 177         uint32_t v;
 178 };
 179
 180 struct phm_acpclock_voltage_dependency_record {
 181         uint32_t acpclk;
 182         uint32_t v;
 183 };
 184
 185 struct phm_clock_voltage_dependency_table {
 186         uint32_t count;                                                                         /* Number of entries. */
 187         struct phm_clock_voltage_dependency_record entries[1];          /* Dynamically allocate count entries. */
 188 };
 189
 190 struct phm_phase_shedding_limits_record {
 191         uint32_t  Voltage;
 192         uint32_t    Sclk;
 193         uint32_t    Mclk;
 194 };
 195
 196
 197 extern int phm_dispatch_table(struct pp_hwmgr *hwmgr,
 198                               struct phm_runtime_table_header *rt_table,
 199                               void *input, void *output);
 200
 201 extern int phm_construct_table(struct pp_hwmgr *hwmgr,
 202                                const struct phm_master_table_header *master_table,
 203                                struct phm_runtime_table_header *rt_table);
 204
 205 extern int phm_destroy_table(struct pp_hwmgr *hwmgr,
 206                              struct phm_runtime_table_header *rt_table);
 207
 208
 209 struct phm_uvd_clock_voltage_dependency_record {
 210         uint32_t vclk;
 211         uint32_t dclk;
 212         uint32_t v;
 213 };
 214
 215 struct phm_uvd_clock_voltage_dependency_table {
 216         uint8_t count;
 217         struct phm_uvd_clock_voltage_dependency_record entries[1];
 218 };
 219
 220 struct phm_acp_clock_voltage_dependency_record {
 221         uint32_t acpclk;
 222         uint32_t v;
 223 };
 224
 225 struct phm_acp_clock_voltage_dependency_table {
 226         uint32_t count;
 227         struct phm_acp_clock_voltage_dependency_record entries[1];
 228 };
 229
 230 struct phm_vce_clock_voltage_dependency_record {
 231         uint32_t ecclk;
 232         uint32_t evclk;
 233         uint32_t v;
 234 };
 235
 236 struct phm_phase_shedding_limits_table {
 237         uint32_t                           count;
 238         struct phm_phase_shedding_limits_record  entries[1];
 239 };
 240
 241 struct phm_vceclock_voltage_dependency_table {
 242         uint8_t count;                                    /* Number of entries. */
 243         struct phm_vceclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
 244 };
 245
 246 struct phm_uvdclock_voltage_dependency_table {
 247         uint8_t count;                                    /* Number of entries. */
 248         struct phm_uvdclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
 249 };
 250
 251 struct phm_samuclock_voltage_dependency_table {
 252         uint8_t count;                                    /* Number of entries. */
 253         struct phm_samuclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
 254 };
 255
 256 struct phm_acpclock_voltage_dependency_table {
 257         uint32_t count;                                    /* Number of entries. */
 258         struct phm_acpclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
 259 };
 260
 261 struct phm_vce_clock_voltage_dependency_table {
 262         uint8_t count;
 263         struct phm_vce_clock_voltage_dependency_record entries[1];
 264 };
 265
 266 struct pp_hwmgr_func {
 267         int (*backend_init)(struct pp_hwmgr *hw_mgr);
 268         int (*backend_fini)(struct pp_hwmgr *hw_mgr);
 269         int (*asic_setup)(struct pp_hwmgr *hw_mgr);
 270         int (*get_power_state_size)(struct pp_hwmgr *hw_mgr);
 271
 272         int (*apply_state_adjust_rules)(struct pp_hwmgr *hwmgr,
 273                                 struct pp_power_state  *prequest_ps,
 274                         const struct pp_power_state *pcurrent_ps);
 275
 276         int (*force_dpm_level)(struct pp_hwmgr *hw_mgr,
 277                                         enum amd_dpm_forced_level level);
 278
 279         int (*dynamic_state_management_enable)(
 280                                                 struct pp_hwmgr *hw_mgr);
 281         int (*dynamic_state_management_disable)(
 282                                                 struct pp_hwmgr *hw_mgr);
 283
 284         int (*patch_boot_state)(struct pp_hwmgr *hwmgr,
 285                                      struct pp_hw_power_state *hw_ps);
 286
 287         int (*get_pp_table_entry)(struct pp_hwmgr *hwmgr,
 288                             unsigned long, struct pp_power_state *);
 289         int (*get_num_of_pp_table_entries)(struct pp_hwmgr *hwmgr);
 290         int (*powerdown_uvd)(struct pp_hwmgr *hwmgr);
 291         int (*powergate_vce)(struct pp_hwmgr *hwmgr, bool bgate);
 292         int (*powergate_uvd)(struct pp_hwmgr *hwmgr, bool bgate);
 293         int (*get_mclk)(struct pp_hwmgr *hwmgr, bool low);
 294         int (*get_sclk)(struct pp_hwmgr *hwmgr, bool low);
 295         int (*power_state_set)(struct pp_hwmgr *hwmgr,
 296                                                 const void *state);
 297         void (*print_current_perforce_level)(struct pp_hwmgr *hwmgr,
 298                                                         struct seq_file *m);
 299         int (*enable_clock_power_gating)(struct pp_hwmgr *hwmgr);
 300         int (*notify_smc_display_config_after_ps_adjustment)(struct pp_hwmgr *hwmgr);
 301         int (*display_config_changed)(struct pp_hwmgr *hwmgr);
 302         int (*disable_clock_power_gating)(struct pp_hwmgr *hwmgr);
 303         int (*update_clock_gatings)(struct pp_hwmgr *hwmgr,
 304                                                 const uint32_t *msg_id);
 305         int (*set_max_fan_rpm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm);
 306         int (*set_max_fan_pwm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm);
 307         int (*get_temperature)(struct pp_hwmgr *hwmgr);
 308         int (*stop_thermal_controller)(struct pp_hwmgr *hwmgr);
 309         int (*get_fan_speed_info)(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info);
 310         int (*set_fan_control_mode)(struct pp_hwmgr *hwmgr, uint32_t mode);
 311         int (*get_fan_control_mode)(struct pp_hwmgr *hwmgr);
 312         int (*set_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t percent);
 313         int (*get_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t *speed);
 314         int (*set_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t percent);
 315         int (*get_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t *speed);
 316         int (*reset_fan_speed_to_default)(struct pp_hwmgr *hwmgr);
 317         int (*uninitialize_thermal_controller)(struct pp_hwmgr *hwmgr);
 318         int (*register_internal_thermal_interrupt)(struct pp_hwmgr *hwmgr,
 319                                         const void *thermal_interrupt_info);
 320         bool (*check_smc_update_required_for_display_configuration)(struct pp_hwmgr *hwmgr);
 321         int (*check_states_equal)(struct pp_hwmgr *hwmgr,
 322                                         const struct pp_hw_power_state *pstate1,
 323                                         const struct pp_hw_power_state *pstate2,
 324                                         bool *equal);
 325         int (*set_cpu_power_state)(struct pp_hwmgr *hwmgr);
 326         int (*store_cc6_data)(struct pp_hwmgr *hwmgr, uint32_t separation_time,
 327                                 bool cc6_disable, bool pstate_disable,
 328                                 bool pstate_switch_disable);
 329         int (*get_dal_power_level)(struct pp_hwmgr *hwmgr,
 330                         struct amd_pp_simple_clock_info *info);
 331         int (*get_performance_level)(struct pp_hwmgr *, const struct pp_hw_power_state *,
 332                         PHM_PerformanceLevelDesignation, uint32_t, PHM_PerformanceLevel *);
 333         int (*get_current_shallow_sleep_clocks)(struct pp_hwmgr *hwmgr,
 334                                 const struct pp_hw_power_state *state, struct pp_clock_info *clock_info);
 335         int (*get_clock_by_type)(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks);
 336         int (*get_max_high_clocks)(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);
 337         int (*power_off_asic)(struct pp_hwmgr *hwmgr);
 338         int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask);
 339         int (*print_clock_levels)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, char *buf);
 340         int (*enable_per_cu_power_gating)(struct pp_hwmgr *hwmgr, bool enable);
 341         int (*get_sclk_od)(struct pp_hwmgr *hwmgr);
 342         int (*set_sclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
 343         int (*get_mclk_od)(struct pp_hwmgr *hwmgr);
 344         int (*set_mclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
 345 };
 346
 347 struct pp_table_func {
 348         int (*pptable_init)(struct pp_hwmgr *hw_mgr);
 349         int (*pptable_fini)(struct pp_hwmgr *hw_mgr);
 350         int (*pptable_get_number_of_vce_state_table_entries)(struct pp_hwmgr *hw_mgr);
 351         int (*pptable_get_vce_state_table_entry)(
 352                                                 struct pp_hwmgr *hwmgr,
 353                                                 unsigned long i,
 354                                                 struct PP_VCEState *vce_state,
 355                                                 void **clock_info,
 356                                                 unsigned long *flag);
 357 };
 358
 359 union phm_cac_leakage_record {
 360         struct {
 361                 uint16_t Vddc;          /* in CI, we use it for StdVoltageHiSidd */
 362                 uint32_t Leakage;       /* in CI, we use it for StdVoltageLoSidd */
 363         };
 364         struct {
 365                 uint16_t Vddc1;
 366                 uint16_t Vddc2;
 367                 uint16_t Vddc3;
 368         };
 369 };
 370
 371 struct phm_cac_leakage_table {
 372         uint32_t count;
 373         union phm_cac_leakage_record entries[1];
 374 };
 375
 376 struct phm_samu_clock_voltage_dependency_record {
 377         uint32_t samclk;
 378         uint32_t v;
 379 };
 380
 381
 382 struct phm_samu_clock_voltage_dependency_table {
 383         uint8_t count;
 384         struct phm_samu_clock_voltage_dependency_record entries[1];
 385 };
 386
 387 struct phm_cac_tdp_table {
 388         uint16_t usTDP;
 389         uint16_t usConfigurableTDP;
 390         uint16_t usTDC;
 391         uint16_t usBatteryPowerLimit;
 392         uint16_t usSmallPowerLimit;
 393         uint16_t usLowCACLeakage;
 394         uint16_t usHighCACLeakage;
 395         uint16_t usMaximumPowerDeliveryLimit;
 396         uint16_t usOperatingTempMinLimit;
 397         uint16_t usOperatingTempMaxLimit;
 398         uint16_t usOperatingTempStep;
 399         uint16_t usOperatingTempHyst;
 400         uint16_t usDefaultTargetOperatingTemp;
 401         uint16_t usTargetOperatingTemp;
 402         uint16_t usPowerTuneDataSetID;
 403         uint16_t usSoftwareShutdownTemp;
 404         uint16_t usClockStretchAmount;
 405         uint16_t usTemperatureLimitHotspot;
 406         uint16_t usTemperatureLimitLiquid1;
 407         uint16_t usTemperatureLimitLiquid2;
 408         uint16_t usTemperatureLimitVrVddc;
 409         uint16_t usTemperatureLimitVrMvdd;
 410         uint16_t usTemperatureLimitPlx;
 411         uint8_t  ucLiquid1_I2C_address;
 412         uint8_t  ucLiquid2_I2C_address;
 413         uint8_t  ucLiquid_I2C_Line;
 414         uint8_t  ucVr_I2C_address;
 415         uint8_t  ucVr_I2C_Line;
 416         uint8_t  ucPlx_I2C_address;
 417         uint8_t  ucPlx_I2C_Line;
 418         uint32_t usBoostPowerLimit;
 419         uint8_t  ucCKS_LDO_REFSEL;
 420 };
 421
 422 struct phm_ppm_table {
 423         uint8_t   ppm_design;
 424         uint16_t  cpu_core_number;
 425         uint32_t  platform_tdp;
 426         uint32_t  small_ac_platform_tdp;
 427         uint32_t  platform_tdc;
 428         uint32_t  small_ac_platform_tdc;
 429         uint32_t  apu_tdp;
 430         uint32_t  dgpu_tdp;
 431         uint32_t  dgpu_ulv_power;
 432         uint32_t  tj_max;
 433 };
 434
 435 struct phm_vq_budgeting_record {
 436         uint32_t ulCUs;
 437         uint32_t ulSustainableSOCPowerLimitLow;
 438         uint32_t ulSustainableSOCPowerLimitHigh;
 439         uint32_t ulMinSclkLow;
 440         uint32_t ulMinSclkHigh;
 441         uint8_t  ucDispConfig;
 442         uint32_t ulDClk;
 443         uint32_t ulEClk;
 444         uint32_t ulSustainableSclk;
 445         uint32_t ulSustainableCUs;
 446 };
 447
 448 struct phm_vq_budgeting_table {
 449         uint8_t numEntries;
 450         struct phm_vq_budgeting_record entries[1];
 451 };
 452
 453 struct phm_clock_and_voltage_limits {
 454         uint32_t sclk;
 455         uint32_t mclk;
 456         uint16_t vddc;
 457         uint16_t vddci;
 458         uint16_t vddgfx;
 459 };
 460
 461 /* Structure to hold PPTable information */
 462
 463 struct phm_ppt_v1_information {
 464         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk;
 465         struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk;
 466         struct phm_clock_array *valid_sclk_values;
 467         struct phm_clock_array *valid_mclk_values;
 468         struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
 469         struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
 470         struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
 471         struct phm_ppm_table *ppm_parameter_table;
 472         struct phm_cac_tdp_table *cac_dtp_table;
 473         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table;
 474         struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
 475         struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table;
 476         struct phm_ppt_v1_pcie_table *pcie_table;
 477         uint16_t us_ulv_voltage_offset;
 478 };
 479
 480 struct phm_dynamic_state_info {
 481         struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk;
 482         struct phm_clock_voltage_dependency_table *vddci_dependency_on_mclk;
 483         struct phm_clock_voltage_dependency_table *vddc_dependency_on_mclk;
 484         struct phm_clock_voltage_dependency_table *mvdd_dependency_on_mclk;
 485         struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
 486         struct phm_clock_array                    *valid_sclk_values;
 487         struct phm_clock_array                    *valid_mclk_values;
 488         struct phm_clock_and_voltage_limits       max_clock_voltage_on_dc;
 489         struct phm_clock_and_voltage_limits       max_clock_voltage_on_ac;
 490         uint32_t                                  mclk_sclk_ratio;
 491         uint32_t                                  sclk_mclk_delta;
 492         uint32_t                                  vddc_vddci_delta;
 493         uint32_t                                  min_vddc_for_pcie_gen2;
 494         struct phm_cac_leakage_table              *cac_leakage_table;
 495         struct phm_phase_shedding_limits_table    *vddc_phase_shed_limits_table;
 496
 497         struct phm_vce_clock_voltage_dependency_table
 498                                             *vce_clock_voltage_dependency_table;
 499         struct phm_uvd_clock_voltage_dependency_table
 500                                             *uvd_clock_voltage_dependency_table;
 501         struct phm_acp_clock_voltage_dependency_table
 502                                             *acp_clock_voltage_dependency_table;
 503         struct phm_samu_clock_voltage_dependency_table
 504                                            *samu_clock_voltage_dependency_table;
 505
 506         struct phm_ppm_table                          *ppm_parameter_table;
 507         struct phm_cac_tdp_table                      *cac_dtp_table;
 508         struct phm_clock_voltage_dependency_table         *vdd_gfx_dependency_on_sclk;
 509         struct phm_vq_budgeting_table                             *vq_budgeting_table;
 510 };
 511
 512 struct pp_fan_info {
 513         bool bNoFan;
 514         uint8_t   ucTachometerPulsesPerRevolution;
 515         uint32_t   ulMinRPM;
 516         uint32_t   ulMaxRPM;
 517 };
 518
 519 struct pp_advance_fan_control_parameters {
 520         uint16_t  usTMin;                          /* The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. */
 521         uint16_t  usTMed;                          /* The middle temperature where we change slopes. */
 522         uint16_t  usTHigh;                         /* The high temperature for setting the second slope. */
 523         uint16_t  usPWMMin;                        /* The minimum PWM value in percent (0.01% increments). */
 524         uint16_t  usPWMMed;                        /* The PWM value (in percent) at TMed. */
 525         uint16_t  usPWMHigh;                       /* The PWM value at THigh. */
 526         uint8_t   ucTHyst;                         /* Temperature hysteresis. Integer. */
 527         uint32_t   ulCycleDelay;                   /* The time between two invocations of the fan control routine in microseconds. */
 528         uint16_t  usTMax;                          /* The max temperature */
 529         uint8_t   ucFanControlMode;
 530         uint16_t  usFanPWMMinLimit;
 531         uint16_t  usFanPWMMaxLimit;
 532         uint16_t  usFanPWMStep;
 533         uint16_t  usDefaultMaxFanPWM;
 534         uint16_t  usFanOutputSensitivity;
 535         uint16_t  usDefaultFanOutputSensitivity;
 536         uint16_t  usMaxFanPWM;                     /* The max Fan PWM value for Fuzzy Fan Control feature */
 537         uint16_t  usFanRPMMinLimit;                /* Minimum limit range in percentage, need to calculate based on minRPM/MaxRpm */
 538         uint16_t  usFanRPMMaxLimit;                /* Maximum limit range in percentage, usually set to 100% by default */
 539         uint16_t  usFanRPMStep;                    /* Step increments/decerements, in percent */
 540         uint16_t  usDefaultMaxFanRPM;              /* The max Fan RPM value for Fuzzy Fan Control feature, default from PPTable */
 541         uint16_t  usMaxFanRPM;                     /* The max Fan RPM value for Fuzzy Fan Control feature, user defined */
 542         uint16_t  usFanCurrentLow;                 /* Low current */
 543         uint16_t  usFanCurrentHigh;                /* High current */
 544         uint16_t  usFanRPMLow;                     /* Low RPM */
 545         uint16_t  usFanRPMHigh;                    /* High RPM */
 546         uint32_t   ulMinFanSCLKAcousticLimit;      /* Minimum Fan Controller SCLK Frequency Acoustic Limit. */
 547         uint8_t   ucTargetTemperature;             /* Advanced fan controller target temperature. */
 548         uint8_t   ucMinimumPWMLimit;               /* The minimum PWM that the advanced fan controller can set.  This should be set to the highest PWM that will run the fan at its lowest RPM. */
 549         uint16_t  usFanGainEdge;                   /* The following is added for Fiji */
 550         uint16_t  usFanGainHotspot;
 551         uint16_t  usFanGainLiquid;
 552         uint16_t  usFanGainVrVddc;
 553         uint16_t  usFanGainVrMvdd;
 554         uint16_t  usFanGainPlx;
 555         uint16_t  usFanGainHbm;
 556 };
 557
 558 struct pp_thermal_controller_info {
 559         uint8_t ucType;
 560         uint8_t ucI2cLine;
 561         uint8_t ucI2cAddress;
 562         struct pp_fan_info fanInfo;
 563         struct pp_advance_fan_control_parameters advanceFanControlParameters;
 564 };
 565
 566 struct phm_microcode_version_info {
 567         uint32_t SMC;
 568         uint32_t DMCU;
 569         uint32_t MC;
 570         uint32_t NB;
 571 };
 572
 573 /**
 574  * The main hardware manager structure.
 575  */
 576 struct pp_hwmgr {
 577         uint32_t chip_family;
 578         uint32_t chip_id;
 579         uint32_t hw_revision;
 580         uint32_t sub_sys_id;
 581         uint32_t sub_vendor_id;
 582
 583         void *device;
 584         struct pp_smumgr *smumgr;
 585         const void *soft_pp_table;
 586         uint32_t soft_pp_table_size;
 587         void *hardcode_pp_table;
 588         bool need_pp_table_upload;
 589         enum amd_dpm_forced_level dpm_level;
 590         bool block_hw_access;
 591         struct phm_gfx_arbiter gfx_arbiter;
 592         struct phm_acp_arbiter acp_arbiter;
 593         struct phm_uvd_arbiter uvd_arbiter;
 594         struct phm_vce_arbiter vce_arbiter;
 595         uint32_t usec_timeout;
 596         void *pptable;
 597         struct phm_platform_descriptor platform_descriptor;
 598         void *backend;
 599         enum PP_DAL_POWERLEVEL dal_power_level;
 600         struct phm_dynamic_state_info dyn_state;
 601         struct phm_runtime_table_header setup_asic;
 602         struct phm_runtime_table_header power_down_asic;
 603         struct phm_runtime_table_header disable_dynamic_state_management;
 604         struct phm_runtime_table_header enable_dynamic_state_management;
 605         struct phm_runtime_table_header set_power_state;
 606         struct phm_runtime_table_header enable_clock_power_gatings;
 607         struct phm_runtime_table_header display_configuration_changed;
 608         struct phm_runtime_table_header start_thermal_controller;
 609         struct phm_runtime_table_header set_temperature_range;
 610         const struct pp_hwmgr_func *hwmgr_func;
 611         const struct pp_table_func *pptable_func;
 612         struct pp_power_state    *ps;
 613         enum pp_power_source  power_source;
 614         uint32_t num_ps;
 615         struct pp_thermal_controller_info thermal_controller;
 616         bool fan_ctrl_is_in_default_mode;
 617         bool powercontainment_enabled;
 618         uint32_t fan_ctrl_default_mode;
 619         uint32_t tmin;
 620         struct phm_microcode_version_info microcode_version_info;
 621         uint32_t ps_size;
 622         struct pp_power_state    *current_ps;
 623         struct pp_power_state    *request_ps;
 624         struct pp_power_state    *boot_ps;
 625         struct pp_power_state    *uvd_ps;
 626         struct amd_pp_display_configuration display_config;
 627 };
 628
 629
 630 extern int hwmgr_init(struct amd_pp_init *pp_init,
 631                       struct pp_instance *handle);
 632
 633 extern int hwmgr_fini(struct pp_hwmgr *hwmgr);
 634
 635 extern int hw_init_power_state_table(struct pp_hwmgr *hwmgr);
 636
 637 extern int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index,
 638                                 uint32_t value, uint32_t mask);
 639
 640 extern int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
 641                                 uint32_t index, uint32_t value, uint32_t mask);
 642
 643 extern uint32_t phm_read_indirect_register(struct pp_hwmgr *hwmgr,
 644                 uint32_t indirect_port, uint32_t index);
 645
 646 extern void phm_write_indirect_register(struct pp_hwmgr *hwmgr,
 647                 uint32_t indirect_port,
 648                 uint32_t index,
 649                 uint32_t value);
 650
 651 extern void phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
 652                                 uint32_t indirect_port,
 653                                 uint32_t index,
 654                                 uint32_t value,
 655                                 uint32_t mask);
 656
 657 extern void phm_wait_for_indirect_register_unequal(
 658                                 struct pp_hwmgr *hwmgr,
 659                                 uint32_t indirect_port,
 660                                 uint32_t index,
 661                                 uint32_t value,
 662                                 uint32_t mask);
 663
 664 extern bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr);
 665 extern bool phm_cf_want_vce_power_gating(struct pp_hwmgr *hwmgr);
 666 extern bool phm_cf_want_microcode_fan_ctrl(struct pp_hwmgr *hwmgr);
 667
 668 extern int phm_trim_voltage_table(struct pp_atomctrl_voltage_table *vol_table);
 669 extern int phm_get_svi2_mvdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table);
 670 extern int phm_get_svi2_vddci_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table);
 671 extern int phm_get_svi2_vdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_voltage_lookup_table *lookup_table);
 672 extern void phm_trim_voltage_table_to_fit_state_table(uint32_t max_vol_steps, struct pp_atomctrl_voltage_table *vol_table);
 673 extern int phm_reset_single_dpm_table(void *table, uint32_t count, int max);
 674 extern void phm_setup_pcie_table_entry(void *table, uint32_t index, uint32_t pcie_gen, uint32_t pcie_lanes);
 675 extern int32_t phm_get_dpm_level_enable_mask_value(void *table);
 676 extern uint8_t phm_get_voltage_index(struct phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t voltage);
 677 extern uint16_t phm_find_closest_vddci(struct pp_atomctrl_voltage_table *vddci_table, uint16_t vddci);
 678 extern int phm_find_boot_level(void *table, uint32_t value, uint32_t *boot_level);
 679 extern int phm_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr, phm_ppt_v1_voltage_lookup_table *lookup_table,
 680                                                                 uint16_t virtual_voltage_id, int32_t *sclk);
 681 extern int phm_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr);
 682 extern int phm_hwmgr_backend_fini(struct pp_hwmgr *hwmgr);
 683 extern uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask);
 684 extern void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr);
 685
 686 #define PHM_ENTIRE_REGISTER_MASK 0xFFFFFFFFU
 687
 688 #define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
 689 #define PHM_FIELD_MASK(reg, field) reg##__##field##_MASK
 690
 691 #define PHM_SET_FIELD(origval, reg, field, fieldval)    \
 692         (((origval) & ~PHM_FIELD_MASK(reg, field)) |    \
 693          (PHM_FIELD_MASK(reg, field) & ((fieldval) << PHM_FIELD_SHIFT(reg, field))))
 694
 695 #define PHM_GET_FIELD(value, reg, field)        \
 696         (((value) & PHM_FIELD_MASK(reg, field)) >>      \
 697          PHM_FIELD_SHIFT(reg, field))
 698
 699
 700 #define PHM_WAIT_REGISTER_GIVEN_INDEX(hwmgr, index, value, mask)        \
 701         phm_wait_on_register(hwmgr, index, value, mask)
 702
 703 #define PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, index, value, mask)        \
 704         phm_wait_for_register_unequal(hwmgr, index, value, mask)
 705
 706 #define PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, index, value, mask) \
 707         phm_wait_on_indirect_register(hwmgr, mm##port##_INDEX, index, value, mask)
 708
 709 #define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, index, value, mask) \
 710         phm_wait_for_indirect_register_unequal(hwmgr, mm##port##_INDEX, index, value, mask)
 711
 712 #define PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, index, value, mask)    \
 713         phm_wait_on_indirect_register(hwmgr, mm##port##_INDEX_0, index, value, mask)
 714
 715 #define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, index, value, mask)    \
 716         phm_wait_for_indirect_register_unequal(hwmgr, mm##port##_INDEX_0, index, value, mask)
 717
 718 /* Operations on named registers. */
 719
 720 #define PHM_WAIT_REGISTER(hwmgr, reg, value, mask)      \
 721         PHM_WAIT_REGISTER_GIVEN_INDEX(hwmgr, mm##reg, value, mask)
 722
 723 #define PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, value, mask)      \
 724         PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, mm##reg, value, mask)
 725
 726 #define PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, value, mask)       \
 727         PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
 728
 729 #define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask)       \
 730         PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
 731
 732 #define PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, value, mask)  \
 733         PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
 734
 735 #define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask)  \
 736         PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
 737
 738 /* Operations on named fields. */
 739
 740 #define PHM_READ_FIELD(device, reg, field)      \
 741         PHM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field)
 742
 743 #define PHM_READ_INDIRECT_FIELD(device, port, reg, field)       \
 744         PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg),     \
 745                         reg, field)
 746
 747 #define PHM_READ_VFPF_INDIRECT_FIELD(device, port, reg, field)  \
 748         PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg),     \
 749                         reg, field)
 750
 751 #define PHM_WRITE_FIELD(device, reg, field, fieldval)   \
 752         cgs_write_register(device, mm##reg, PHM_SET_FIELD(      \
 753                                 cgs_read_register(device, mm##reg), reg, field, fieldval))
 754
 755 #define PHM_WRITE_INDIRECT_FIELD(device, port, reg, field, fieldval)    \
 756         cgs_write_ind_register(device, port, ix##reg,   \
 757                         PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg),     \
 758                                 reg, field, fieldval))
 759
 760 #define PHM_WRITE_VFPF_INDIRECT_FIELD(device, port, reg, field, fieldval)       \
 761         cgs_write_ind_register(device, port, ix##reg,   \
 762                         PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg),     \
 763                                 reg, field, fieldval))
 764
 765 #define PHM_WAIT_FIELD(hwmgr, reg, field, fieldval)     \
 766         PHM_WAIT_REGISTER(hwmgr, reg, (fieldval)        \
 767                         << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
 768
 769 #define PHM_WAIT_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval)      \
 770         PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) \
 771                         << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
 772
 773 #define PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \
 774         PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval)    \
 775                         << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
 776
 777 #define PHM_WAIT_FIELD_UNEQUAL(hwmgr, reg, field, fieldval)     \
 778         PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, (fieldval)        \
 779                         << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
 780
 781 #define PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval)      \
 782         PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, (fieldval) \
 783                         << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
 784
 785 #define PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \
 786         PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, (fieldval)    \
 787                         << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
 788
 789 /* Operations on arrays of registers & fields. */
 790
 791 #define PHM_READ_ARRAY_REGISTER(device, reg, offset)    \
 792         cgs_read_register(device, mm##reg + (offset))
 793
 794 #define PHM_WRITE_ARRAY_REGISTER(device, reg, offset, value)    \
 795         cgs_write_register(device, mm##reg + (offset), value)
 796
 797 #define PHM_WAIT_ARRAY_REGISTER(hwmgr, reg, offset, value, mask)        \
 798         PHM_WAIT_REGISTER_GIVEN_INDEX(hwmgr, mm##reg + (offset), value, mask)
 799
 800 #define PHM_WAIT_ARRAY_REGISTER_UNEQUAL(hwmgr, reg, offset, value, mask)        \
 801         PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, mm##reg + (offset), value, mask)
 802
 803 #define PHM_READ_ARRAY_FIELD(hwmgr, reg, offset, field) \
 804         PHM_GET_FIELD(PHM_READ_ARRAY_REGISTER(hwmgr->device, reg, offset), reg, field)
 805
 806 #define PHM_WRITE_ARRAY_FIELD(hwmgr, reg, offset, field, fieldvalue)    \
 807         PHM_WRITE_ARRAY_REGISTER(hwmgr->device, reg, offset,    \
 808                         PHM_SET_FIELD(PHM_READ_ARRAY_REGISTER(hwmgr->device, reg, offset),      \
 809                                 reg, field, fieldvalue))
 810
 811 #define PHM_WAIT_ARRAY_FIELD(hwmgr, reg, offset, field, fieldvalue)     \
 812         PHM_WAIT_REGISTER_GIVEN_INDEX(hwmgr, mm##reg + (offset),        \
 813                         (fieldvalue) << PHM_FIELD_SHIFT(reg, field),    \
 814                         PHM_FIELD_MASK(reg, field))
 815
 816 #define PHM_WAIT_ARRAY_FIELD_UNEQUAL(hwmgr, reg, offset, field, fieldvalue)     \
 817         PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, mm##reg + (offset),        \
 818                         (fieldvalue) << PHM_FIELD_SHIFT(reg, field),    \
 819                         PHM_FIELD_MASK(reg, field))
 820
 821 #endif /* _HWMGR_H_ */