drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/types.h>
  24 #include <linux/kernel.h>
  25 #include <linux/slab.h>
  26 #include <linux/gfp.h>
  27
  28 #include "smumgr.h"
  29 #include "tonga_smumgr.h"
  30 #include "pp_debug.h"
  31 #include "smu_ucode_xfer_vi.h"
  32 #include "tonga_ppsmc.h"
  33 #include "smu/smu_7_1_2_d.h"
  34 #include "smu/smu_7_1_2_sh_mask.h"
  35 #include "cgs_common.h"
  36
  37 #define TONGA_SMC_SIZE                  0x20000
  38 #define BUFFER_SIZE                     80000
  39 #define MAX_STRING_SIZE                 15
  40 #define BUFFER_SIZETWO              131072 /*128 *1024*/
  41
  42 /**
  43 * Set the address for reading/writing the SMC SRAM space.
  44 * @param    smumgr  the address of the powerplay hardware manager.
  45 * @param    smcAddress the address in the SMC RAM to access.
  46 */
  47 static int tonga_set_smc_sram_address(struct pp_smumgr *smumgr,
  48                                 uint32_t smcAddress, uint32_t limit)
  49 {
  50         if (smumgr == NULL || smumgr->device == NULL)
  51                 return -EINVAL;
  52         PP_ASSERT_WITH_CODE((0 == (3 & smcAddress)),
  53                 "SMC address must be 4 byte aligned.",
  54                 return -1;);
  55
  56         PP_ASSERT_WITH_CODE((limit > (smcAddress + 3)),
  57                 "SMC address is beyond the SMC RAM area.",
  58                 return -1;);
  59
  60         cgs_write_register(smumgr->device, mmSMC_IND_INDEX_0, smcAddress);
  61         SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0);
  62
  63         return 0;
  64 }
  65
  66 /**
  67 * Copy bytes from an array into the SMC RAM space.
  68 *
  69 * @param    smumgr  the address of the powerplay SMU manager.
  70 * @param    smcStartAddress the start address in the SMC RAM to copy bytes to.
  71 * @param    src the byte array to copy the bytes from.
  72 * @param    byteCount the number of bytes to copy.
  73 */
  74 int tonga_copy_bytes_to_smc(struct pp_smumgr *smumgr,
  75                 uint32_t smcStartAddress, const uint8_t *src,
  76                 uint32_t byteCount, uint32_t limit)
  77 {
  78         uint32_t addr;
  79         uint32_t data, orig_data;
  80         int result = 0;
  81         uint32_t extra_shift;
  82
  83         if (smumgr == NULL || smumgr->device == NULL)
  84                 return -EINVAL;
  85         PP_ASSERT_WITH_CODE((0 == (3 & smcStartAddress)),
  86                 "SMC address must be 4 byte aligned.",
  87                 return 0;);
  88
  89         PP_ASSERT_WITH_CODE((limit > (smcStartAddress + byteCount)),
  90                 "SMC address is beyond the SMC RAM area.",
  91                 return 0;);
  92
  93         addr = smcStartAddress;
  94
  95         while (byteCount >= 4) {
  96                 /*
  97                  * Bytes are written into the
  98                  * SMC address space with the MSB first
  99                  */
 100                 data = (src[0] << 24) + (src[1] << 16) + (src[2] << 8) + src[3];
 101
 102                 result = tonga_set_smc_sram_address(smumgr, addr, limit);
 103
 104                 if (result)
 105                         goto out;
 106
 107                 cgs_write_register(smumgr->device, mmSMC_IND_DATA_0, data);
 108
 109                 src += 4;
 110                 byteCount -= 4;
 111                 addr += 4;
 112         }
 113
 114         if (0 != byteCount) {
 115                 /* Now write odd bytes left, do a read modify write cycle */
 116                 data = 0;
 117
 118                 result = tonga_set_smc_sram_address(smumgr, addr, limit);
 119                 if (result)
 120                         goto out;
 121
 122                 orig_data = cgs_read_register(smumgr->device,
 123                                                         mmSMC_IND_DATA_0);
 124                 extra_shift = 8 * (4 - byteCount);
 125
 126                 while (byteCount > 0) {
 127                         data = (data << 8) + *src++;
 128                         byteCount--;
 129                 }
 130
 131                 data <<= extra_shift;
 132                 data |= (orig_data & ~((~0UL) << extra_shift));
 133
 134                 result = tonga_set_smc_sram_address(smumgr, addr, limit);
 135                 if (result)
 136                         goto out;
 137
 138                 cgs_write_register(smumgr->device, mmSMC_IND_DATA_0, data);
 139         }
 140
 141 out:
 142         return result;
 143 }
 144
 145
 146 int tonga_program_jump_on_start(struct pp_smumgr *smumgr)
 147 {
 148         static const unsigned char pData[] = { 0xE0, 0x00, 0x80, 0x40 };
 149
 150         tonga_copy_bytes_to_smc(smumgr, 0x0, pData, 4, sizeof(pData)+1);
 151
 152         return 0;
 153 }
 154
 155 /**
 156 * Return if the SMC is currently running.
 157 *
 158 * @param    smumgr  the address of the powerplay hardware manager.
 159 */
 160 static int tonga_is_smc_ram_running(struct pp_smumgr *smumgr)
 161 {
 162         return ((0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
 163                                         SMC_SYSCON_CLOCK_CNTL_0, ck_disable))
 164                         && (0x20100 <= cgs_read_ind_register(smumgr->device,
 165                                         CGS_IND_REG__SMC, ixSMC_PC_C)));
 166 }
 167
 168 static int tonga_send_msg_to_smc_offset(struct pp_smumgr *smumgr)
 169 {
 170         if (smumgr == NULL || smumgr->device == NULL)
 171                 return -EINVAL;
 172
 173         SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
 174
 175         cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, 0x20000);
 176         cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, PPSMC_MSG_Test);
 177
 178         SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
 179
 180         return 0;
 181 }
 182
 183 /**
 184 * Send a message to the SMC, and wait for its response.
 185 *
 186 * @param    smumgr  the address of the powerplay hardware manager.
 187 * @param    msg the message to send.
 188 * @return   The response that came from the SMC.
 189 */
 190 static int tonga_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
 191 {
 192         if (smumgr == NULL || smumgr->device == NULL)
 193                 return -EINVAL;
 194
 195         if (!tonga_is_smc_ram_running(smumgr))
 196                 return -1;
 197
 198         SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
 199         PP_ASSERT_WITH_CODE(
 200                 1 == SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP),
 201                 "Failed to send Previous Message.",
 202                 );
 203
 204         cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg);
 205
 206         SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
 207         PP_ASSERT_WITH_CODE(
 208                 1 == SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP),
 209                 "Failed to send Message.",
 210                 );
 211
 212         return 0;
 213 }
 214
 215 /*
 216 * Send a message to the SMC, and do not wait for its response.
 217 *
 218 * @param    smumgr  the address of the powerplay hardware manager.
 219 * @param    msg the message to send.
 220 * @return   The response that came from the SMC.
 221 */
 222 static int tonga_send_msg_to_smc_without_waiting
 223                                 (struct pp_smumgr *smumgr, uint16_t msg)
 224 {
 225         if (smumgr == NULL || smumgr->device == NULL)
 226                 return -EINVAL;
 227
 228         SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
 229         PP_ASSERT_WITH_CODE(
 230                 1 == SMUM_READ_FIELD(smumgr->device, SMC_RESP_0, SMC_RESP),
 231                 "Failed to send Previous Message.",
 232                 );
 233         cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg);
 234
 235         return 0;
 236 }
 237
 238 /*
 239 * Send a message to the SMC with parameter
 240 *
 241 * @param    smumgr:  the address of the powerplay hardware manager.
 242 * @param    msg: the message to send.
 243 * @param    parameter: the parameter to send
 244 * @return   The response that came from the SMC.
 245 */
 246 static int tonga_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
 247                                 uint16_t msg, uint32_t parameter)
 248 {
 249         if (smumgr == NULL || smumgr->device == NULL)
 250                 return -EINVAL;
 251
 252         if (!tonga_is_smc_ram_running(smumgr))
 253                 return PPSMC_Result_Failed;
 254
 255         SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
 256         cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter);
 257
 258         return tonga_send_msg_to_smc(smumgr, msg);
 259 }
 260
 261 /*
 262 * Send a message to the SMC with parameter, do not wait for response
 263 *
 264 * @param    smumgr:  the address of the powerplay hardware manager.
 265 * @param    msg: the message to send.
 266 * @param    parameter: the parameter to send
 267 * @return   The response that came from the SMC.
 268 */
 269 static int tonga_send_msg_to_smc_with_parameter_without_waiting(
 270                         struct pp_smumgr *smumgr,
 271                         uint16_t msg, uint32_t parameter)
 272 {
 273         if (smumgr == NULL || smumgr->device == NULL)
 274                 return -EINVAL;
 275
 276         SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0);
 277
 278         cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter);
 279
 280         return tonga_send_msg_to_smc_without_waiting(smumgr, msg);
 281 }
 282
 283 /*
 284  * Read a 32bit value from the SMC SRAM space.
 285  * ALL PARAMETERS ARE IN HOST BYTE ORDER.
 286  * @param    smumgr  the address of the powerplay hardware manager.
 287  * @param    smcAddress the address in the SMC RAM to access.
 288  * @param    value and output parameter for the data read from the SMC SRAM.
 289  */
 290 int tonga_read_smc_sram_dword(struct pp_smumgr *smumgr,
 291                                         uint32_t smcAddress, uint32_t *value,
 292                                         uint32_t limit)
 293 {
 294         int result;
 295
 296         result = tonga_set_smc_sram_address(smumgr, smcAddress, limit);
 297
 298         if (0 != result)
 299                 return result;
 300
 301         *value = cgs_read_register(smumgr->device, mmSMC_IND_DATA_0);
 302
 303         return 0;
 304 }
 305
 306 /*
 307  * Write a 32bit value to the SMC SRAM space.
 308  * ALL PARAMETERS ARE IN HOST BYTE ORDER.
 309  * @param    smumgr  the address of the powerplay hardware manager.
 310  * @param    smcAddress the address in the SMC RAM to access.
 311  * @param    value to write to the SMC SRAM.
 312  */
 313 int tonga_write_smc_sram_dword(struct pp_smumgr *smumgr,
 314                                         uint32_t smcAddress, uint32_t value,
 315                                         uint32_t limit)
 316 {
 317         int result;
 318
 319         result = tonga_set_smc_sram_address(smumgr, smcAddress, limit);
 320
 321         if (0 != result)
 322                 return result;
 323
 324         cgs_write_register(smumgr->device, mmSMC_IND_DATA_0, value);
 325
 326         return 0;
 327 }
 328
 329 static int tonga_smu_fini(struct pp_smumgr *smumgr)
 330 {
 331         if (smumgr->backend != NULL) {
 332                 kfree(smumgr->backend);
 333                 smumgr->backend = NULL;
 334         }
 335         return 0;
 336 }
 337
 338 static enum cgs_ucode_id tonga_convert_fw_type_to_cgs(uint32_t fw_type)
 339 {
 340         enum cgs_ucode_id result = CGS_UCODE_ID_MAXIMUM;
 341
 342         switch (fw_type) {
 343         case UCODE_ID_SMU:
 344                 result = CGS_UCODE_ID_SMU;
 345                 break;
 346         case UCODE_ID_SDMA0:
 347                 result = CGS_UCODE_ID_SDMA0;
 348                 break;
 349         case UCODE_ID_SDMA1:
 350                 result = CGS_UCODE_ID_SDMA1;
 351                 break;
 352         case UCODE_ID_CP_CE:
 353                 result = CGS_UCODE_ID_CP_CE;
 354                 break;
 355         case UCODE_ID_CP_PFP:
 356                 result = CGS_UCODE_ID_CP_PFP;
 357                 break;
 358         case UCODE_ID_CP_ME:
 359                 result = CGS_UCODE_ID_CP_ME;
 360                 break;
 361         case UCODE_ID_CP_MEC:
 362                 result = CGS_UCODE_ID_CP_MEC;
 363                 break;
 364         case UCODE_ID_CP_MEC_JT1:
 365                 result = CGS_UCODE_ID_CP_MEC_JT1;
 366                 break;
 367         case UCODE_ID_CP_MEC_JT2:
 368                 result = CGS_UCODE_ID_CP_MEC_JT2;
 369                 break;
 370         case UCODE_ID_RLC_G:
 371                 result = CGS_UCODE_ID_RLC_G;
 372                 break;
 373         default:
 374                 break;
 375         }
 376
 377         return result;
 378 }
 379
 380 /**
 381  * Convert the PPIRI firmware type to SMU type mask.
 382  * For MEC, we need to check all MEC related type
 383 */
 384 static uint16_t tonga_get_mask_for_firmware_type(uint16_t firmwareType)
 385 {
 386         uint16_t result = 0;
 387
 388         switch (firmwareType) {
 389         case UCODE_ID_SDMA0:
 390                 result = UCODE_ID_SDMA0_MASK;
 391                 break;
 392         case UCODE_ID_SDMA1:
 393                 result = UCODE_ID_SDMA1_MASK;
 394                 break;
 395         case UCODE_ID_CP_CE:
 396                 result = UCODE_ID_CP_CE_MASK;
 397                 break;
 398         case UCODE_ID_CP_PFP:
 399                 result = UCODE_ID_CP_PFP_MASK;
 400                 break;
 401         case UCODE_ID_CP_ME:
 402                 result = UCODE_ID_CP_ME_MASK;
 403                 break;
 404         case UCODE_ID_CP_MEC:
 405         case UCODE_ID_CP_MEC_JT1:
 406         case UCODE_ID_CP_MEC_JT2:
 407                 result = UCODE_ID_CP_MEC_MASK;
 408                 break;
 409         case UCODE_ID_RLC_G:
 410                 result = UCODE_ID_RLC_G_MASK;
 411                 break;
 412         default:
 413                 break;
 414         }
 415
 416         return result;
 417 }
 418
 419 /**
 420  * Check if the FW has been loaded,
 421  * SMU will not return if loading has not finished.
 422 */
 423 static int tonga_check_fw_load_finish(struct pp_smumgr *smumgr, uint32_t fwType)
 424 {
 425         uint16_t fwMask = tonga_get_mask_for_firmware_type(fwType);
 426
 427         if (0 != SMUM_WAIT_VFPF_INDIRECT_REGISTER(smumgr, SMC_IND,
 428                                 SOFT_REGISTERS_TABLE_28, fwMask, fwMask)) {
 429                 printk(KERN_ERR "[ powerplay ] check firmware loading failed\n");
 430                 return -EINVAL;
 431         }
 432
 433         return 0;
 434 }
 435
 436 /* Populate one firmware image to the data structure */
 437 static int tonga_populate_single_firmware_entry(struct pp_smumgr *smumgr,
 438                                 uint16_t firmware_type,
 439                                 struct SMU_Entry *pentry)
 440 {
 441         int result;
 442         struct cgs_firmware_info info = {0};
 443
 444         result = cgs_get_firmware_info(
 445                                 smumgr->device,
 446                                 tonga_convert_fw_type_to_cgs(firmware_type),
 447                                 &info);
 448
 449         if (result == 0) {
 450                 pentry->version = 0;
 451                 pentry->id = (uint16_t)firmware_type;
 452                 pentry->image_addr_high = smu_upper_32_bits(info.mc_addr);
 453                 pentry->image_addr_low = smu_lower_32_bits(info.mc_addr);
 454                 pentry->meta_data_addr_high = 0;
 455                 pentry->meta_data_addr_low = 0;
 456                 pentry->data_size_byte = info.image_size;
 457                 pentry->num_register_entries = 0;
 458
 459                 if (firmware_type == UCODE_ID_RLC_G)
 460                         pentry->flags = 1;
 461                 else
 462                         pentry->flags = 0;
 463         } else {
 464                 return result;
 465         }
 466
 467         return result;
 468 }
 469
 470 static int tonga_request_smu_reload_fw(struct pp_smumgr *smumgr)
 471 {
 472         struct tonga_smumgr *tonga_smu =
 473                 (struct tonga_smumgr *)(smumgr->backend);
 474         uint16_t fw_to_load;
 475         int result = 0;
 476         struct SMU_DRAMData_TOC *toc;
 477         /**
 478          * First time this gets called during SmuMgr init,
 479          * we haven't processed SMU header file yet,
 480          * so Soft Register Start offset is unknown.
 481          * However, for this case, UcodeLoadStatus is already 0,
 482          * so we can skip this if the Soft Registers Start offset is 0.
 483          */
 484         cgs_write_ind_register(smumgr->device,
 485                 CGS_IND_REG__SMC, ixSOFT_REGISTERS_TABLE_28, 0);
 486
 487         tonga_send_msg_to_smc_with_parameter(smumgr,
 488                 PPSMC_MSG_SMU_DRAM_ADDR_HI,
 489                 tonga_smu->smu_buffer.mc_addr_high);
 490         tonga_send_msg_to_smc_with_parameter(smumgr,
 491                 PPSMC_MSG_SMU_DRAM_ADDR_LO,
 492                 tonga_smu->smu_buffer.mc_addr_low);
 493
 494         toc = (struct SMU_DRAMData_TOC *)tonga_smu->pHeader;
 495         toc->num_entries = 0;
 496         toc->structure_version = 1;
 497
 498         PP_ASSERT_WITH_CODE(
 499                 0 == tonga_populate_single_firmware_entry(smumgr,
 500                 UCODE_ID_RLC_G,
 501                 &toc->entry[toc->num_entries++]),
 502                 "Failed to Get Firmware Entry.\n",
 503                 return -1);
 504         PP_ASSERT_WITH_CODE(
 505                 0 == tonga_populate_single_firmware_entry(smumgr,
 506                 UCODE_ID_CP_CE,
 507                 &toc->entry[toc->num_entries++]),
 508                 "Failed to Get Firmware Entry.\n",
 509                 return -1);
 510         PP_ASSERT_WITH_CODE(
 511                 0 == tonga_populate_single_firmware_entry
 512                 (smumgr, UCODE_ID_CP_PFP, &toc->entry[toc->num_entries++]),
 513                 "Failed to Get Firmware Entry.\n", return -1);
 514         PP_ASSERT_WITH_CODE(
 515                 0 == tonga_populate_single_firmware_entry
 516                 (smumgr, UCODE_ID_CP_ME, &toc->entry[toc->num_entries++]),
 517                 "Failed to Get Firmware Entry.\n", return -1);
 518         PP_ASSERT_WITH_CODE(
 519                 0 == tonga_populate_single_firmware_entry
 520                 (smumgr, UCODE_ID_CP_MEC, &toc->entry[toc->num_entries++]),
 521                 "Failed to Get Firmware Entry.\n", return -1);
 522         PP_ASSERT_WITH_CODE(
 523                 0 == tonga_populate_single_firmware_entry
 524                 (smumgr, UCODE_ID_CP_MEC_JT1, &toc->entry[toc->num_entries++]),
 525                 "Failed to Get Firmware Entry.\n", return -1);
 526         PP_ASSERT_WITH_CODE(
 527                 0 == tonga_populate_single_firmware_entry
 528                 (smumgr, UCODE_ID_CP_MEC_JT2, &toc->entry[toc->num_entries++]),
 529                 "Failed to Get Firmware Entry.\n", return -1);
 530         PP_ASSERT_WITH_CODE(
 531                 0 == tonga_populate_single_firmware_entry
 532                 (smumgr, UCODE_ID_SDMA0, &toc->entry[toc->num_entries++]),
 533                 "Failed to Get Firmware Entry.\n", return -1);
 534         PP_ASSERT_WITH_CODE(
 535                 0 == tonga_populate_single_firmware_entry
 536                 (smumgr, UCODE_ID_SDMA1, &toc->entry[toc->num_entries++]),
 537                 "Failed to Get Firmware Entry.\n", return -1);
 538
 539         tonga_send_msg_to_smc_with_parameter(smumgr,
 540                 PPSMC_MSG_DRV_DRAM_ADDR_HI,
 541                 tonga_smu->header_buffer.mc_addr_high);
 542         tonga_send_msg_to_smc_with_parameter(smumgr,
 543                 PPSMC_MSG_DRV_DRAM_ADDR_LO,
 544                 tonga_smu->header_buffer.mc_addr_low);
 545
 546         fw_to_load = UCODE_ID_RLC_G_MASK
 547                         + UCODE_ID_SDMA0_MASK
 548                         + UCODE_ID_SDMA1_MASK
 549                         + UCODE_ID_CP_CE_MASK
 550                         + UCODE_ID_CP_ME_MASK
 551                         + UCODE_ID_CP_PFP_MASK
 552                         + UCODE_ID_CP_MEC_MASK;
 553
 554         PP_ASSERT_WITH_CODE(
 555                 0 == tonga_send_msg_to_smc_with_parameter_without_waiting(
 556                 smumgr, PPSMC_MSG_LoadUcodes, fw_to_load),
 557                 "Fail to Request SMU Load uCode", return 0);
 558
 559         return result;
 560 }
 561
 562 static int tonga_request_smu_load_specific_fw(struct pp_smumgr *smumgr,
 563                                 uint32_t firmwareType)
 564 {
 565         return 0;
 566 }
 567
 568 /**
 569  * Upload the SMC firmware to the SMC microcontroller.
 570  *
 571  * @param    smumgr  the address of the powerplay hardware manager.
 572  * @param    pFirmware the data structure containing the various sections of the firmware.
 573  */
 574 static int tonga_smu_upload_firmware_image(struct pp_smumgr *smumgr)
 575 {
 576         const uint8_t *src;
 577         uint32_t byte_count;
 578         uint32_t *data;
 579         struct cgs_firmware_info info = {0};
 580
 581         if (smumgr == NULL || smumgr->device == NULL)
 582                 return -EINVAL;
 583
 584         cgs_get_firmware_info(smumgr->device,
 585                 tonga_convert_fw_type_to_cgs(UCODE_ID_SMU), &info);
 586
 587         if (info.image_size & 3) {
 588                 printk(KERN_ERR "[ powerplay ] SMC ucode is not 4 bytes aligned\n");
 589                 return -EINVAL;
 590         }
 591
 592         if (info.image_size > TONGA_SMC_SIZE) {
 593                 printk(KERN_ERR "[ powerplay ] SMC address is beyond the SMC RAM area\n");
 594                 return -EINVAL;
 595         }
 596
 597         cgs_write_register(smumgr->device, mmSMC_IND_INDEX_0, 0x20000);
 598         SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 1);
 599
 600         byte_count = info.image_size;
 601         src = (const uint8_t *)info.kptr;
 602
 603         data = (uint32_t *)src;
 604         for (; byte_count >= 4; data++, byte_count -= 4)
 605                 cgs_write_register(smumgr->device, mmSMC_IND_DATA_0, data[0]);
 606
 607         SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0);
 608
 609         return 0;
 610 }
 611
 612 static int tonga_start_in_protection_mode(struct pp_smumgr *smumgr)
 613 {
 614         int result;
 615
 616         /* Assert reset */
 617         SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
 618                 SMC_SYSCON_RESET_CNTL, rst_reg, 1);
 619
 620         result = tonga_smu_upload_firmware_image(smumgr);
 621         if (result)
 622                 return result;
 623
 624         /* Clear status */
 625         cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
 626                 ixSMU_STATUS, 0);
 627
 628         /* Enable clock */
 629         SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
 630                 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
 631
 632         /* De-assert reset */
 633         SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
 634                 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
 635
 636         /* Set SMU Auto Start */
 637         SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
 638                 SMU_INPUT_DATA, AUTO_START, 1);
 639
 640         /* Clear firmware interrupt enable flag */
 641         cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
 642                 ixFIRMWARE_FLAGS, 0);
 643
 644         SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND,
 645                 RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1);
 646
 647         /**
 648          * Call Test SMU message with 0x20000 offset to trigger SMU start
 649          */
 650         tonga_send_msg_to_smc_offset(smumgr);
 651
 652         /* Wait for done bit to be set */
 653         SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND,
 654                 SMU_STATUS, SMU_DONE, 0);
 655
 656         /* Check pass/failed indicator */
 657         if (1 != SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device,
 658                                 CGS_IND_REG__SMC, SMU_STATUS, SMU_PASS)) {
 659                 printk(KERN_ERR "[ powerplay ] SMU Firmware start failed\n");
 660                 return -EINVAL;
 661         }
 662
 663         /* Wait for firmware to initialize */
 664         SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND,
 665                 FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
 666
 667         return 0;
 668 }
 669
 670
 671 static int tonga_start_in_non_protection_mode(struct pp_smumgr *smumgr)
 672 {
 673         int result = 0;
 674
 675         /* wait for smc boot up */
 676         SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND,
 677                 RCU_UC_EVENTS, boot_seq_done, 0);
 678
 679         /*Clear firmware interrupt enable flag*/
 680         cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
 681                 ixFIRMWARE_FLAGS, 0);
 682
 683
 684         SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
 685                 SMC_SYSCON_RESET_CNTL, rst_reg, 1);
 686
 687         result = tonga_smu_upload_firmware_image(smumgr);
 688
 689         if (result != 0)
 690                 return result;
 691
 692         /* Set smc instruct start point at 0x0 */
 693         tonga_program_jump_on_start(smumgr);
 694
 695
 696         SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
 697                 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
 698
 699         /*De-assert reset*/
 700         SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
 701                 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
 702
 703         /* Wait for firmware to initialize */
 704         SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND,
 705                 FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
 706
 707         return result;
 708 }
 709
 710 static int tonga_start_smu(struct pp_smumgr *smumgr)
 711 {
 712         int result;
 713
 714         /* Only start SMC if SMC RAM is not running */
 715         if (!tonga_is_smc_ram_running(smumgr)) {
 716                 /*Check if SMU is running in protected mode*/
 717                 if (0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
 718                                         SMU_FIRMWARE, SMU_MODE)) {
 719                         result = tonga_start_in_non_protection_mode(smumgr);
 720                         if (result)
 721                                 return result;
 722                 } else {
 723                         result = tonga_start_in_protection_mode(smumgr);
 724                         if (result)
 725                                 return result;
 726                 }
 727         }
 728
 729         result = tonga_request_smu_reload_fw(smumgr);
 730
 731         return result;
 732 }
 733
 734 /**
 735  * Write a 32bit value to the SMC SRAM space.
 736  * ALL PARAMETERS ARE IN HOST BYTE ORDER.
 737  * @param    smumgr  the address of the powerplay hardware manager.
 738  * @param    smcAddress the address in the SMC RAM to access.
 739  * @param    value to write to the SMC SRAM.
 740  */
 741 static int tonga_smu_init(struct pp_smumgr *smumgr)
 742 {
 743         struct tonga_smumgr *tonga_smu;
 744         uint8_t *internal_buf;
 745         uint64_t mc_addr = 0;
 746         /* Allocate memory for backend private data */
 747         tonga_smu = (struct tonga_smumgr *)(smumgr->backend);
 748         tonga_smu->header_buffer.data_size =
 749                 ((sizeof(struct SMU_DRAMData_TOC) / 4096) + 1) * 4096;
 750         tonga_smu->smu_buffer.data_size = 200*4096;
 751
 752         smu_allocate_memory(smumgr->device,
 753                 tonga_smu->header_buffer.data_size,
 754                 CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
 755                 PAGE_SIZE,
 756                 &mc_addr,
 757                 &tonga_smu->header_buffer.kaddr,
 758                 &tonga_smu->header_buffer.handle);
 759
 760         tonga_smu->pHeader = tonga_smu->header_buffer.kaddr;
 761         tonga_smu->header_buffer.mc_addr_high = smu_upper_32_bits(mc_addr);
 762         tonga_smu->header_buffer.mc_addr_low = smu_lower_32_bits(mc_addr);
 763
 764         PP_ASSERT_WITH_CODE((NULL != tonga_smu->pHeader),
 765                 "Out of memory.",
 766                 kfree(smumgr->backend);
 767                 cgs_free_gpu_mem(smumgr->device,
 768                 (cgs_handle_t)tonga_smu->header_buffer.handle);
 769                 return -1);
 770
 771         smu_allocate_memory(smumgr->device,
 772                 tonga_smu->smu_buffer.data_size,
 773                 CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
 774                 PAGE_SIZE,
 775                 &mc_addr,
 776                 &tonga_smu->smu_buffer.kaddr,
 777                 &tonga_smu->smu_buffer.handle);
 778
 779         internal_buf = tonga_smu->smu_buffer.kaddr;
 780         tonga_smu->smu_buffer.mc_addr_high = smu_upper_32_bits(mc_addr);
 781         tonga_smu->smu_buffer.mc_addr_low = smu_lower_32_bits(mc_addr);
 782
 783         PP_ASSERT_WITH_CODE((NULL != internal_buf),
 784                 "Out of memory.",
 785                 kfree(smumgr->backend);
 786                 cgs_free_gpu_mem(smumgr->device,
 787                 (cgs_handle_t)tonga_smu->smu_buffer.handle);
 788                 return -1;);
 789
 790         return 0;
 791 }
 792
 793 static const struct pp_smumgr_func tonga_smu_funcs = {
 794         .smu_init = &tonga_smu_init,
 795         .smu_fini = &tonga_smu_fini,
 796         .start_smu = &tonga_start_smu,
 797         .check_fw_load_finish = &tonga_check_fw_load_finish,
 798         .request_smu_load_fw = &tonga_request_smu_reload_fw,
 799         .request_smu_load_specific_fw = &tonga_request_smu_load_specific_fw,
 800         .send_msg_to_smc = &tonga_send_msg_to_smc,
 801         .send_msg_to_smc_with_parameter = &tonga_send_msg_to_smc_with_parameter,
 802         .download_pptable_settings = NULL,
 803         .upload_pptable_settings = NULL,
 804 };
 805
 806 int tonga_smum_init(struct pp_smumgr *smumgr)
 807 {
 808         struct tonga_smumgr *tonga_smu = NULL;
 809
 810         tonga_smu = kzalloc(sizeof(struct tonga_smumgr), GFP_KERNEL);
 811
 812         if (tonga_smu == NULL)
 813                 return -ENOMEM;
 814
 815         smumgr->backend = tonga_smu;
 816         smumgr->smumgr_funcs = &tonga_smu_funcs;
 817
 818         return 0;
 819 }