drivers/gpu/drm/etnaviv/etnaviv_gpu.c

   1 /*
   2  * Copyright (C) 2015 Etnaviv Project
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License version 2 as published by
   6  * the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include <linux/component.h>
  18 #include <linux/fence.h>
  19 #include <linux/moduleparam.h>
  20 #include <linux/of_device.h>
  21 #include "etnaviv_dump.h"
  22 #include "etnaviv_gpu.h"
  23 #include "etnaviv_gem.h"
  24 #include "etnaviv_mmu.h"
  25 #include "etnaviv_iommu.h"
  26 #include "etnaviv_iommu_v2.h"
  27 #include "common.xml.h"
  28 #include "state.xml.h"
  29 #include "state_hi.xml.h"
  30 #include "cmdstream.xml.h"
  31
  32 static const struct platform_device_id gpu_ids[] = {
  33         { .name = "etnaviv-gpu,2d" },
  34         { },
  35 };
  36
  37 static bool etnaviv_dump_core = true;
  38 module_param_named(dump_core, etnaviv_dump_core, bool, 0600);
  39
  40 /*
  41  * Driver functions:
  42  */
  43
  44 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value)
  45 {
  46         switch (param) {
  47         case ETNAVIV_PARAM_GPU_MODEL:
  48                 *value = gpu->identity.model;
  49                 break;
  50
  51         case ETNAVIV_PARAM_GPU_REVISION:
  52                 *value = gpu->identity.revision;
  53                 break;
  54
  55         case ETNAVIV_PARAM_GPU_FEATURES_0:
  56                 *value = gpu->identity.features;
  57                 break;
  58
  59         case ETNAVIV_PARAM_GPU_FEATURES_1:
  60                 *value = gpu->identity.minor_features0;
  61                 break;
  62
  63         case ETNAVIV_PARAM_GPU_FEATURES_2:
  64                 *value = gpu->identity.minor_features1;
  65                 break;
  66
  67         case ETNAVIV_PARAM_GPU_FEATURES_3:
  68                 *value = gpu->identity.minor_features2;
  69                 break;
  70
  71         case ETNAVIV_PARAM_GPU_FEATURES_4:
  72                 *value = gpu->identity.minor_features3;
  73                 break;
  74
  75         case ETNAVIV_PARAM_GPU_FEATURES_5:
  76                 *value = gpu->identity.minor_features4;
  77                 break;
  78
  79         case ETNAVIV_PARAM_GPU_FEATURES_6:
  80                 *value = gpu->identity.minor_features5;
  81                 break;
  82
  83         case ETNAVIV_PARAM_GPU_STREAM_COUNT:
  84                 *value = gpu->identity.stream_count;
  85                 break;
  86
  87         case ETNAVIV_PARAM_GPU_REGISTER_MAX:
  88                 *value = gpu->identity.register_max;
  89                 break;
  90
  91         case ETNAVIV_PARAM_GPU_THREAD_COUNT:
  92                 *value = gpu->identity.thread_count;
  93                 break;
  94
  95         case ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE:
  96                 *value = gpu->identity.vertex_cache_size;
  97                 break;
  98
  99         case ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT:
 100                 *value = gpu->identity.shader_core_count;
 101                 break;
 102
 103         case ETNAVIV_PARAM_GPU_PIXEL_PIPES:
 104                 *value = gpu->identity.pixel_pipes;
 105                 break;
 106
 107         case ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE:
 108                 *value = gpu->identity.vertex_output_buffer_size;
 109                 break;
 110
 111         case ETNAVIV_PARAM_GPU_BUFFER_SIZE:
 112                 *value = gpu->identity.buffer_size;
 113                 break;
 114
 115         case ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT:
 116                 *value = gpu->identity.instruction_count;
 117                 break;
 118
 119         case ETNAVIV_PARAM_GPU_NUM_CONSTANTS:
 120                 *value = gpu->identity.num_constants;
 121                 break;
 122
 123         case ETNAVIV_PARAM_GPU_NUM_VARYINGS:
 124                 *value = gpu->identity.varyings_count;
 125                 break;
 126
 127         default:
 128                 DBG("%s: invalid param: %u", dev_name(gpu->dev), param);
 129                 return -EINVAL;
 130         }
 131
 132         return 0;
 133 }
 134
 135
 136 #define etnaviv_is_model_rev(gpu, mod, rev) \
 137         ((gpu)->identity.model == chipModel_##mod && \
 138          (gpu)->identity.revision == rev)
 139 #define etnaviv_field(val, field) \
 140         (((val) & field##__MASK) >> field##__SHIFT)
 141
 142 static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
 143 {
 144         if (gpu->identity.minor_features0 &
 145             chipMinorFeatures0_MORE_MINOR_FEATURES) {
 146                 u32 specs[4];
 147                 unsigned int streams;
 148
 149                 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS);
 150                 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2);
 151                 specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3);
 152                 specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4);
 153
 154                 gpu->identity.stream_count = etnaviv_field(specs[0],
 155                                         VIVS_HI_CHIP_SPECS_STREAM_COUNT);
 156                 gpu->identity.register_max = etnaviv_field(specs[0],
 157                                         VIVS_HI_CHIP_SPECS_REGISTER_MAX);
 158                 gpu->identity.thread_count = etnaviv_field(specs[0],
 159                                         VIVS_HI_CHIP_SPECS_THREAD_COUNT);
 160                 gpu->identity.vertex_cache_size = etnaviv_field(specs[0],
 161                                         VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE);
 162                 gpu->identity.shader_core_count = etnaviv_field(specs[0],
 163                                         VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT);
 164                 gpu->identity.pixel_pipes = etnaviv_field(specs[0],
 165                                         VIVS_HI_CHIP_SPECS_PIXEL_PIPES);
 166                 gpu->identity.vertex_output_buffer_size =
 167                         etnaviv_field(specs[0],
 168                                 VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE);
 169
 170                 gpu->identity.buffer_size = etnaviv_field(specs[1],
 171                                         VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE);
 172                 gpu->identity.instruction_count = etnaviv_field(specs[1],
 173                                         VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT);
 174                 gpu->identity.num_constants = etnaviv_field(specs[1],
 175                                         VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS);
 176
 177                 gpu->identity.varyings_count = etnaviv_field(specs[2],
 178                                         VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT);
 179
 180                 /* This overrides the value from older register if non-zero */
 181                 streams = etnaviv_field(specs[3],
 182                                         VIVS_HI_CHIP_SPECS_4_STREAM_COUNT);
 183                 if (streams)
 184                         gpu->identity.stream_count = streams;
 185         }
 186
 187         /* Fill in the stream count if not specified */
 188         if (gpu->identity.stream_count == 0) {
 189                 if (gpu->identity.model >= 0x1000)
 190                         gpu->identity.stream_count = 4;
 191                 else
 192                         gpu->identity.stream_count = 1;
 193         }
 194
 195         /* Convert the register max value */
 196         if (gpu->identity.register_max)
 197                 gpu->identity.register_max = 1 << gpu->identity.register_max;
 198         else if (gpu->identity.model == chipModel_GC400)
 199                 gpu->identity.register_max = 32;
 200         else
 201                 gpu->identity.register_max = 64;
 202
 203         /* Convert thread count */
 204         if (gpu->identity.thread_count)
 205                 gpu->identity.thread_count = 1 << gpu->identity.thread_count;
 206         else if (gpu->identity.model == chipModel_GC400)
 207                 gpu->identity.thread_count = 64;
 208         else if (gpu->identity.model == chipModel_GC500 ||
 209                  gpu->identity.model == chipModel_GC530)
 210                 gpu->identity.thread_count = 128;
 211         else
 212                 gpu->identity.thread_count = 256;
 213
 214         if (gpu->identity.vertex_cache_size == 0)
 215                 gpu->identity.vertex_cache_size = 8;
 216
 217         if (gpu->identity.shader_core_count == 0) {
 218                 if (gpu->identity.model >= 0x1000)
 219                         gpu->identity.shader_core_count = 2;
 220                 else
 221                         gpu->identity.shader_core_count = 1;
 222         }
 223
 224         if (gpu->identity.pixel_pipes == 0)
 225                 gpu->identity.pixel_pipes = 1;
 226
 227         /* Convert virtex buffer size */
 228         if (gpu->identity.vertex_output_buffer_size) {
 229                 gpu->identity.vertex_output_buffer_size =
 230                         1 << gpu->identity.vertex_output_buffer_size;
 231         } else if (gpu->identity.model == chipModel_GC400) {
 232                 if (gpu->identity.revision < 0x4000)
 233                         gpu->identity.vertex_output_buffer_size = 512;
 234                 else if (gpu->identity.revision < 0x4200)
 235                         gpu->identity.vertex_output_buffer_size = 256;
 236                 else
 237                         gpu->identity.vertex_output_buffer_size = 128;
 238         } else {
 239                 gpu->identity.vertex_output_buffer_size = 512;
 240         }
 241
 242         switch (gpu->identity.instruction_count) {
 243         case 0:
 244                 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
 245                     gpu->identity.model == chipModel_GC880)
 246                         gpu->identity.instruction_count = 512;
 247                 else
 248                         gpu->identity.instruction_count = 256;
 249                 break;
 250
 251         case 1:
 252                 gpu->identity.instruction_count = 1024;
 253                 break;
 254
 255         case 2:
 256                 gpu->identity.instruction_count = 2048;
 257                 break;
 258
 259         default:
 260                 gpu->identity.instruction_count = 256;
 261                 break;
 262         }
 263
 264         if (gpu->identity.num_constants == 0)
 265                 gpu->identity.num_constants = 168;
 266
 267         if (gpu->identity.varyings_count == 0) {
 268                 if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0)
 269                         gpu->identity.varyings_count = 12;
 270                 else
 271                         gpu->identity.varyings_count = 8;
 272         }
 273
 274         /*
 275          * For some cores, two varyings are consumed for position, so the
 276          * maximum varying count needs to be reduced by one.
 277          */
 278         if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) ||
 279             etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
 280             etnaviv_is_model_rev(gpu, GC4000, 0x5245) ||
 281             etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
 282             etnaviv_is_model_rev(gpu, GC3000, 0x5435) ||
 283             etnaviv_is_model_rev(gpu, GC2200, 0x5244) ||
 284             etnaviv_is_model_rev(gpu, GC2100, 0x5108) ||
 285             etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
 286             etnaviv_is_model_rev(gpu, GC1500, 0x5246) ||
 287             etnaviv_is_model_rev(gpu, GC880, 0x5107) ||
 288             etnaviv_is_model_rev(gpu, GC880, 0x5106))
 289                 gpu->identity.varyings_count -= 1;
 290 }
 291
 292 static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
 293 {
 294         u32 chipIdentity;
 295
 296         chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY);
 297
 298         /* Special case for older graphic cores. */
 299         if (etnaviv_field(chipIdentity, VIVS_HI_CHIP_IDENTITY_FAMILY) == 0x01) {
 300                 gpu->identity.model    = chipModel_GC500;
 301                 gpu->identity.revision = etnaviv_field(chipIdentity,
 302                                          VIVS_HI_CHIP_IDENTITY_REVISION);
 303         } else {
 304
 305                 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL);
 306                 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV);
 307
 308                 /*
 309                  * !!!! HACK ALERT !!!!
 310                  * Because people change device IDs without letting software
 311                  * know about it - here is the hack to make it all look the
 312                  * same.  Only for GC400 family.
 313                  */
 314                 if ((gpu->identity.model & 0xff00) == 0x0400 &&
 315                     gpu->identity.model != chipModel_GC420) {
 316                         gpu->identity.model = gpu->identity.model & 0x0400;
 317                 }
 318
 319                 /* Another special case */
 320                 if (etnaviv_is_model_rev(gpu, GC300, 0x2201)) {
 321                         u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE);
 322                         u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME);
 323
 324                         if (chipDate == 0x20080814 && chipTime == 0x12051100) {
 325                                 /*
 326                                  * This IP has an ECO; put the correct
 327                                  * revision in it.
 328                                  */
 329                                 gpu->identity.revision = 0x1051;
 330                         }
 331                 }
 332         }
 333
 334         dev_info(gpu->dev, "model: GC%x, revision: %x\n",
 335                  gpu->identity.model, gpu->identity.revision);
 336
 337         gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE);
 338
 339         /* Disable fast clear on GC700. */
 340         if (gpu->identity.model == chipModel_GC700)
 341                 gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
 342
 343         if ((gpu->identity.model == chipModel_GC500 &&
 344              gpu->identity.revision < 2) ||
 345             (gpu->identity.model == chipModel_GC300 &&
 346              gpu->identity.revision < 0x2000)) {
 347
 348                 /*
 349                  * GC500 rev 1.x and GC300 rev < 2.0 doesn't have these
 350                  * registers.
 351                  */
 352                 gpu->identity.minor_features0 = 0;
 353                 gpu->identity.minor_features1 = 0;
 354                 gpu->identity.minor_features2 = 0;
 355                 gpu->identity.minor_features3 = 0;
 356                 gpu->identity.minor_features4 = 0;
 357                 gpu->identity.minor_features5 = 0;
 358         } else
 359                 gpu->identity.minor_features0 =
 360                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0);
 361
 362         if (gpu->identity.minor_features0 &
 363             chipMinorFeatures0_MORE_MINOR_FEATURES) {
 364                 gpu->identity.minor_features1 =
 365                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1);
 366                 gpu->identity.minor_features2 =
 367                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2);
 368                 gpu->identity.minor_features3 =
 369                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3);
 370                 gpu->identity.minor_features4 =
 371                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4);
 372                 gpu->identity.minor_features5 =
 373                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5);
 374         }
 375
 376         /* GC600 idle register reports zero bits where modules aren't present */
 377         if (gpu->identity.model == chipModel_GC600) {
 378                 gpu->idle_mask = VIVS_HI_IDLE_STATE_TX |
 379                                  VIVS_HI_IDLE_STATE_RA |
 380                                  VIVS_HI_IDLE_STATE_SE |
 381                                  VIVS_HI_IDLE_STATE_PA |
 382                                  VIVS_HI_IDLE_STATE_SH |
 383                                  VIVS_HI_IDLE_STATE_PE |
 384                                  VIVS_HI_IDLE_STATE_DE |
 385                                  VIVS_HI_IDLE_STATE_FE;
 386         } else {
 387                 gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP;
 388         }
 389
 390         etnaviv_hw_specs(gpu);
 391 }
 392
 393 static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock)
 394 {
 395         gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock |
 396                   VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD);
 397         gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
 398 }
 399
 400 static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
 401 {
 402         u32 control, idle;
 403         unsigned long timeout;
 404         bool failed = true;
 405
 406         /* TODO
 407          *
 408          * - clock gating
 409          * - puls eater
 410          * - what about VG?
 411          */
 412
 413         /* We hope that the GPU resets in under one second */
 414         timeout = jiffies + msecs_to_jiffies(1000);
 415
 416         while (time_is_after_jiffies(timeout)) {
 417                 control = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS |
 418                           VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40);
 419
 420                 /* enable clock */
 421                 etnaviv_gpu_load_clock(gpu, control);
 422
 423                 /* Wait for stable clock.  Vivante's code waited for 1ms */
 424                 usleep_range(1000, 10000);
 425
 426                 /* isolate the GPU. */
 427                 control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
 428                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 429
 430                 /* set soft reset. */
 431                 control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
 432                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 433
 434                 /* wait for reset. */
 435                 msleep(1);
 436
 437                 /* reset soft reset bit. */
 438                 control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
 439                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 440
 441                 /* reset GPU isolation. */
 442                 control &= ~VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
 443                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 444
 445                 /* read idle register. */
 446                 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
 447
 448                 /* try reseting again if FE it not idle */
 449                 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) {
 450                         dev_dbg(gpu->dev, "FE is not idle\n");
 451                         continue;
 452                 }
 453
 454                 /* read reset register. */
 455                 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
 456
 457                 /* is the GPU idle? */
 458                 if (((control & VIVS_HI_CLOCK_CONTROL_IDLE_3D) == 0) ||
 459                     ((control & VIVS_HI_CLOCK_CONTROL_IDLE_2D) == 0)) {
 460                         dev_dbg(gpu->dev, "GPU is not idle\n");
 461                         continue;
 462                 }
 463
 464                 failed = false;
 465                 break;
 466         }
 467
 468         if (failed) {
 469                 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
 470                 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
 471
 472                 dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n",
 473                         idle & VIVS_HI_IDLE_STATE_FE ? "" : "not ",
 474                         control & VIVS_HI_CLOCK_CONTROL_IDLE_3D ? "" : "not ",
 475                         control & VIVS_HI_CLOCK_CONTROL_IDLE_2D ? "" : "not ");
 476
 477                 return -EBUSY;
 478         }
 479
 480         /* We rely on the GPU running, so program the clock */
 481         control = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS |
 482                   VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40);
 483
 484         /* enable clock */
 485         etnaviv_gpu_load_clock(gpu, control);
 486
 487         return 0;
 488 }
 489
 490 static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
 491 {
 492         u16 prefetch;
 493
 494         if ((etnaviv_is_model_rev(gpu, GC320, 0x5007) ||
 495              etnaviv_is_model_rev(gpu, GC320, 0x5220)) &&
 496             gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) {
 497                 u32 mc_memory_debug;
 498
 499                 mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff;
 500
 501                 if (gpu->identity.revision == 0x5007)
 502                         mc_memory_debug |= 0x0c;
 503                 else
 504                         mc_memory_debug |= 0x08;
 505
 506                 gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug);
 507         }
 508
 509         /*
 510          * Update GPU AXI cache atttribute to "cacheable, no allocate".
 511          * This is necessary to prevent the iMX6 SoC locking up.
 512          */
 513         gpu_write(gpu, VIVS_HI_AXI_CONFIG,
 514                   VIVS_HI_AXI_CONFIG_AWCACHE(2) |
 515                   VIVS_HI_AXI_CONFIG_ARCACHE(2));
 516
 517         /* GC2000 rev 5108 needs a special bus config */
 518         if (etnaviv_is_model_rev(gpu, GC2000, 0x5108)) {
 519                 u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG);
 520                 bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK |
 521                                 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK);
 522                 bus_config |= VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(1) |
 523                               VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(0);
 524                 gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config);
 525         }
 526
 527         /* set base addresses */
 528         gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_RA, gpu->memory_base);
 529         gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_FE, gpu->memory_base);
 530         gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_TX, gpu->memory_base);
 531         gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PEZ, gpu->memory_base);
 532         gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PE, gpu->memory_base);
 533
 534         /* setup the MMU page table pointers */
 535         etnaviv_iommu_domain_restore(gpu, gpu->mmu->domain);
 536
 537         /* Start command processor */
 538         prefetch = etnaviv_buffer_init(gpu);
 539
 540         gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U);
 541         gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS,
 542                   gpu->buffer->paddr - gpu->memory_base);
 543         gpu_write(gpu, VIVS_FE_COMMAND_CONTROL,
 544                   VIVS_FE_COMMAND_CONTROL_ENABLE |
 545                   VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch));
 546 }
 547
 548 int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
 549 {
 550         int ret, i;
 551         struct iommu_domain *iommu;
 552         enum etnaviv_iommu_version version;
 553         bool mmuv2;
 554
 555         ret = pm_runtime_get_sync(gpu->dev);
 556         if (ret < 0)
 557                 return ret;
 558
 559         etnaviv_hw_identify(gpu);
 560
 561         if (gpu->identity.model == 0) {
 562                 dev_err(gpu->dev, "Unknown GPU model\n");
 563                 ret = -ENXIO;
 564                 goto fail;
 565         }
 566
 567         /* Exclude VG cores with FE2.0 */
 568         if (gpu->identity.features & chipFeatures_PIPE_VG &&
 569             gpu->identity.features & chipFeatures_FE20) {
 570                 dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n");
 571                 ret = -ENXIO;
 572                 goto fail;
 573         }
 574
 575         ret = etnaviv_hw_reset(gpu);
 576         if (ret)
 577                 goto fail;
 578
 579         /* Setup IOMMU.. eventually we will (I think) do this once per context
 580          * and have separate page tables per context.  For now, to keep things
 581          * simple and to get something working, just use a single address space:
 582          */
 583         mmuv2 = gpu->identity.minor_features1 & chipMinorFeatures1_MMU_VERSION;
 584         dev_dbg(gpu->dev, "mmuv2: %d\n", mmuv2);
 585
 586         if (!mmuv2) {
 587                 iommu = etnaviv_iommu_domain_alloc(gpu);
 588                 version = ETNAVIV_IOMMU_V1;
 589         } else {
 590                 iommu = etnaviv_iommu_v2_domain_alloc(gpu);
 591                 version = ETNAVIV_IOMMU_V2;
 592         }
 593
 594         if (!iommu) {
 595                 ret = -ENOMEM;
 596                 goto fail;
 597         }
 598
 599         gpu->mmu = etnaviv_iommu_new(gpu, iommu, version);
 600         if (!gpu->mmu) {
 601                 iommu_domain_free(iommu);
 602                 ret = -ENOMEM;
 603                 goto fail;
 604         }
 605
 606         /* Create buffer: */
 607         gpu->buffer = etnaviv_gpu_cmdbuf_new(gpu, PAGE_SIZE, 0);
 608         if (!gpu->buffer) {
 609                 ret = -ENOMEM;
 610                 dev_err(gpu->dev, "could not create command buffer\n");
 611                 goto destroy_iommu;
 612         }
 613         if (gpu->buffer->paddr - gpu->memory_base > 0x80000000) {
 614                 ret = -EINVAL;
 615                 dev_err(gpu->dev,
 616                         "command buffer outside valid memory window\n");
 617                 goto free_buffer;
 618         }
 619
 620         /* Setup event management */
 621         spin_lock_init(&gpu->event_spinlock);
 622         init_completion(&gpu->event_free);
 623         for (i = 0; i < ARRAY_SIZE(gpu->event); i++) {
 624                 gpu->event[i].used = false;
 625                 complete(&gpu->event_free);
 626         }
 627
 628         /* Now program the hardware */
 629         mutex_lock(&gpu->lock);
 630         etnaviv_gpu_hw_init(gpu);
 631         mutex_unlock(&gpu->lock);
 632
 633         pm_runtime_mark_last_busy(gpu->dev);
 634         pm_runtime_put_autosuspend(gpu->dev);
 635
 636         return 0;
 637
 638 free_buffer:
 639         etnaviv_gpu_cmdbuf_free(gpu->buffer);
 640         gpu->buffer = NULL;
 641 destroy_iommu:
 642         etnaviv_iommu_destroy(gpu->mmu);
 643         gpu->mmu = NULL;
 644 fail:
 645         pm_runtime_mark_last_busy(gpu->dev);
 646         pm_runtime_put_autosuspend(gpu->dev);
 647
 648         return ret;
 649 }
 650
 651 #ifdef CONFIG_DEBUG_FS
 652 struct dma_debug {
 653         u32 address[2];
 654         u32 state[2];
 655 };
 656
 657 static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug)
 658 {
 659         u32 i;
 660
 661         debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
 662         debug->state[0]   = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
 663
 664         for (i = 0; i < 500; i++) {
 665                 debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
 666                 debug->state[1]   = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
 667
 668                 if (debug->address[0] != debug->address[1])
 669                         break;
 670
 671                 if (debug->state[0] != debug->state[1])
 672                         break;
 673         }
 674 }
 675
 676 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m)
 677 {
 678         struct dma_debug debug;
 679         u32 dma_lo, dma_hi, axi, idle;
 680         int ret;
 681
 682         seq_printf(m, "%s Status:\n", dev_name(gpu->dev));
 683
 684         ret = pm_runtime_get_sync(gpu->dev);
 685         if (ret < 0)
 686                 return ret;
 687
 688         dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW);
 689         dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH);
 690         axi = gpu_read(gpu, VIVS_HI_AXI_STATUS);
 691         idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
 692
 693         verify_dma(gpu, &debug);
 694
 695         seq_puts(m, "\tfeatures\n");
 696         seq_printf(m, "\t minor_features0: 0x%08x\n",
 697                    gpu->identity.minor_features0);
 698         seq_printf(m, "\t minor_features1: 0x%08x\n",
 699                    gpu->identity.minor_features1);
 700         seq_printf(m, "\t minor_features2: 0x%08x\n",
 701                    gpu->identity.minor_features2);
 702         seq_printf(m, "\t minor_features3: 0x%08x\n",
 703                    gpu->identity.minor_features3);
 704         seq_printf(m, "\t minor_features4: 0x%08x\n",
 705                    gpu->identity.minor_features4);
 706         seq_printf(m, "\t minor_features5: 0x%08x\n",
 707                    gpu->identity.minor_features5);
 708
 709         seq_puts(m, "\tspecs\n");
 710         seq_printf(m, "\t stream_count:  %d\n",
 711                         gpu->identity.stream_count);
 712         seq_printf(m, "\t register_max: %d\n",
 713                         gpu->identity.register_max);
 714         seq_printf(m, "\t thread_count: %d\n",
 715                         gpu->identity.thread_count);
 716         seq_printf(m, "\t vertex_cache_size: %d\n",
 717                         gpu->identity.vertex_cache_size);
 718         seq_printf(m, "\t shader_core_count: %d\n",
 719                         gpu->identity.shader_core_count);
 720         seq_printf(m, "\t pixel_pipes: %d\n",
 721                         gpu->identity.pixel_pipes);
 722         seq_printf(m, "\t vertex_output_buffer_size: %d\n",
 723                         gpu->identity.vertex_output_buffer_size);
 724         seq_printf(m, "\t buffer_size: %d\n",
 725                         gpu->identity.buffer_size);
 726         seq_printf(m, "\t instruction_count: %d\n",
 727                         gpu->identity.instruction_count);
 728         seq_printf(m, "\t num_constants: %d\n",
 729                         gpu->identity.num_constants);
 730         seq_printf(m, "\t varyings_count: %d\n",
 731                         gpu->identity.varyings_count);
 732
 733         seq_printf(m, "\taxi: 0x%08x\n", axi);
 734         seq_printf(m, "\tidle: 0x%08x\n", idle);
 735         idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP;
 736         if ((idle & VIVS_HI_IDLE_STATE_FE) == 0)
 737                 seq_puts(m, "\t FE is not idle\n");
 738         if ((idle & VIVS_HI_IDLE_STATE_DE) == 0)
 739                 seq_puts(m, "\t DE is not idle\n");
 740         if ((idle & VIVS_HI_IDLE_STATE_PE) == 0)
 741                 seq_puts(m, "\t PE is not idle\n");
 742         if ((idle & VIVS_HI_IDLE_STATE_SH) == 0)
 743                 seq_puts(m, "\t SH is not idle\n");
 744         if ((idle & VIVS_HI_IDLE_STATE_PA) == 0)
 745                 seq_puts(m, "\t PA is not idle\n");
 746         if ((idle & VIVS_HI_IDLE_STATE_SE) == 0)
 747                 seq_puts(m, "\t SE is not idle\n");
 748         if ((idle & VIVS_HI_IDLE_STATE_RA) == 0)
 749                 seq_puts(m, "\t RA is not idle\n");
 750         if ((idle & VIVS_HI_IDLE_STATE_TX) == 0)
 751                 seq_puts(m, "\t TX is not idle\n");
 752         if ((idle & VIVS_HI_IDLE_STATE_VG) == 0)
 753                 seq_puts(m, "\t VG is not idle\n");
 754         if ((idle & VIVS_HI_IDLE_STATE_IM) == 0)
 755                 seq_puts(m, "\t IM is not idle\n");
 756         if ((idle & VIVS_HI_IDLE_STATE_FP) == 0)
 757                 seq_puts(m, "\t FP is not idle\n");
 758         if ((idle & VIVS_HI_IDLE_STATE_TS) == 0)
 759                 seq_puts(m, "\t TS is not idle\n");
 760         if (idle & VIVS_HI_IDLE_STATE_AXI_LP)
 761                 seq_puts(m, "\t AXI low power mode\n");
 762
 763         if (gpu->identity.features & chipFeatures_DEBUG_MODE) {
 764                 u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0);
 765                 u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1);
 766                 u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE);
 767
 768                 seq_puts(m, "\tMC\n");
 769                 seq_printf(m, "\t read0: 0x%08x\n", read0);
 770                 seq_printf(m, "\t read1: 0x%08x\n", read1);
 771                 seq_printf(m, "\t write: 0x%08x\n", write);
 772         }
 773
 774         seq_puts(m, "\tDMA ");
 775
 776         if (debug.address[0] == debug.address[1] &&
 777             debug.state[0] == debug.state[1]) {
 778                 seq_puts(m, "seems to be stuck\n");
 779         } else if (debug.address[0] == debug.address[1]) {
 780                 seq_puts(m, "adress is constant\n");
 781         } else {
 782                 seq_puts(m, "is runing\n");
 783         }
 784
 785         seq_printf(m, "\t address 0: 0x%08x\n", debug.address[0]);
 786         seq_printf(m, "\t address 1: 0x%08x\n", debug.address[1]);
 787         seq_printf(m, "\t state 0: 0x%08x\n", debug.state[0]);
 788         seq_printf(m, "\t state 1: 0x%08x\n", debug.state[1]);
 789         seq_printf(m, "\t last fetch 64 bit word: 0x%08x 0x%08x\n",
 790                    dma_lo, dma_hi);
 791
 792         ret = 0;
 793
 794         pm_runtime_mark_last_busy(gpu->dev);
 795         pm_runtime_put_autosuspend(gpu->dev);
 796
 797         return ret;
 798 }
 799 #endif
 800
 801 /*
 802  * Power Management:
 803  */
 804 static int enable_clk(struct etnaviv_gpu *gpu)
 805 {
 806         if (gpu->clk_core)
 807                 clk_prepare_enable(gpu->clk_core);
 808         if (gpu->clk_shader)
 809                 clk_prepare_enable(gpu->clk_shader);
 810
 811         return 0;
 812 }
 813
 814 static int disable_clk(struct etnaviv_gpu *gpu)
 815 {
 816         if (gpu->clk_core)
 817                 clk_disable_unprepare(gpu->clk_core);
 818         if (gpu->clk_shader)
 819                 clk_disable_unprepare(gpu->clk_shader);
 820
 821         return 0;
 822 }
 823
 824 static int enable_axi(struct etnaviv_gpu *gpu)
 825 {
 826         if (gpu->clk_bus)
 827                 clk_prepare_enable(gpu->clk_bus);
 828
 829         return 0;
 830 }
 831
 832 static int disable_axi(struct etnaviv_gpu *gpu)
 833 {
 834         if (gpu->clk_bus)
 835                 clk_disable_unprepare(gpu->clk_bus);
 836
 837         return 0;
 838 }
 839
 840 /*
 841  * Hangcheck detection for locked gpu:
 842  */
 843 static void recover_worker(struct work_struct *work)
 844 {
 845         struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
 846                                                recover_work);
 847         unsigned long flags;
 848         unsigned int i;
 849
 850         dev_err(gpu->dev, "hangcheck recover!\n");
 851
 852         if (pm_runtime_get_sync(gpu->dev) < 0)
 853                 return;
 854
 855         mutex_lock(&gpu->lock);
 856
 857         /* Only catch the first event, or when manually re-armed */
 858         if (etnaviv_dump_core) {
 859                 etnaviv_core_dump(gpu);
 860                 etnaviv_dump_core = false;
 861         }
 862
 863         etnaviv_hw_reset(gpu);
 864
 865         /* complete all events, the GPU won't do it after the reset */
 866         spin_lock_irqsave(&gpu->event_spinlock, flags);
 867         for (i = 0; i < ARRAY_SIZE(gpu->event); i++) {
 868                 if (!gpu->event[i].used)
 869                         continue;
 870                 fence_signal(gpu->event[i].fence);
 871                 gpu->event[i].fence = NULL;
 872                 gpu->event[i].used = false;
 873                 complete(&gpu->event_free);
 874         }
 875         spin_unlock_irqrestore(&gpu->event_spinlock, flags);
 876         gpu->completed_fence = gpu->active_fence;
 877
 878         etnaviv_gpu_hw_init(gpu);
 879         gpu->switch_context = true;
 880
 881         mutex_unlock(&gpu->lock);
 882         pm_runtime_mark_last_busy(gpu->dev);
 883         pm_runtime_put_autosuspend(gpu->dev);
 884
 885         /* Retire the buffer objects in a work */
 886         etnaviv_queue_work(gpu->drm, &gpu->retire_work);
 887 }
 888
 889 static void hangcheck_timer_reset(struct etnaviv_gpu *gpu)
 890 {
 891         DBG("%s", dev_name(gpu->dev));
 892         mod_timer(&gpu->hangcheck_timer,
 893                   round_jiffies_up(jiffies + DRM_ETNAVIV_HANGCHECK_JIFFIES));
 894 }
 895
 896 static void hangcheck_handler(unsigned long data)
 897 {
 898         struct etnaviv_gpu *gpu = (struct etnaviv_gpu *)data;
 899         u32 fence = gpu->completed_fence;
 900         bool progress = false;
 901
 902         if (fence != gpu->hangcheck_fence) {
 903                 gpu->hangcheck_fence = fence;
 904                 progress = true;
 905         }
 906
 907         if (!progress) {
 908                 u32 dma_addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
 909                 int change = dma_addr - gpu->hangcheck_dma_addr;
 910
 911                 if (change < 0 || change > 16) {
 912                         gpu->hangcheck_dma_addr = dma_addr;
 913                         progress = true;
 914                 }
 915         }
 916
 917         if (!progress && fence_after(gpu->active_fence, fence)) {
 918                 dev_err(gpu->dev, "hangcheck detected gpu lockup!\n");
 919                 dev_err(gpu->dev, "     completed fence: %u\n", fence);
 920                 dev_err(gpu->dev, "     active fence: %u\n",
 921                         gpu->active_fence);
 922                 etnaviv_queue_work(gpu->drm, &gpu->recover_work);
 923         }
 924
 925         /* if still more pending work, reset the hangcheck timer: */
 926         if (fence_after(gpu->active_fence, gpu->hangcheck_fence))
 927                 hangcheck_timer_reset(gpu);
 928 }
 929
 930 static void hangcheck_disable(struct etnaviv_gpu *gpu)
 931 {
 932         del_timer_sync(&gpu->hangcheck_timer);
 933         cancel_work_sync(&gpu->recover_work);
 934 }
 935
 936 /* fence object management */
 937 struct etnaviv_fence {
 938         struct etnaviv_gpu *gpu;
 939         struct fence base;
 940 };
 941
 942 static inline struct etnaviv_fence *to_etnaviv_fence(struct fence *fence)
 943 {
 944         return container_of(fence, struct etnaviv_fence, base);
 945 }
 946
 947 static const char *etnaviv_fence_get_driver_name(struct fence *fence)
 948 {
 949         return "etnaviv";
 950 }
 951
 952 static const char *etnaviv_fence_get_timeline_name(struct fence *fence)
 953 {
 954         struct etnaviv_fence *f = to_etnaviv_fence(fence);
 955
 956         return dev_name(f->gpu->dev);
 957 }
 958
 959 static bool etnaviv_fence_enable_signaling(struct fence *fence)
 960 {
 961         return true;
 962 }
 963
 964 static bool etnaviv_fence_signaled(struct fence *fence)
 965 {
 966         struct etnaviv_fence *f = to_etnaviv_fence(fence);
 967
 968         return fence_completed(f->gpu, f->base.seqno);
 969 }
 970
 971 static void etnaviv_fence_release(struct fence *fence)
 972 {
 973         struct etnaviv_fence *f = to_etnaviv_fence(fence);
 974
 975         kfree_rcu(f, base.rcu);
 976 }
 977
 978 static const struct fence_ops etnaviv_fence_ops = {
 979         .get_driver_name = etnaviv_fence_get_driver_name,
 980         .get_timeline_name = etnaviv_fence_get_timeline_name,
 981         .enable_signaling = etnaviv_fence_enable_signaling,
 982         .signaled = etnaviv_fence_signaled,
 983         .wait = fence_default_wait,
 984         .release = etnaviv_fence_release,
 985 };
 986
 987 static struct fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu)
 988 {
 989         struct etnaviv_fence *f;
 990
 991         f = kzalloc(sizeof(*f), GFP_KERNEL);
 992         if (!f)
 993                 return NULL;
 994
 995         f->gpu = gpu;
 996
 997         fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock,
 998                    gpu->fence_context, ++gpu->next_fence);
 999
1000         return &f->base;
1001 }
1002
1003 int etnaviv_gpu_fence_sync_obj(struct etnaviv_gem_object *etnaviv_obj,
1004         unsigned int context, bool exclusive)
1005 {
1006         struct reservation_object *robj = etnaviv_obj->resv;
1007         struct reservation_object_list *fobj;
1008         struct fence *fence;
1009         int i, ret;
1010
1011         if (!exclusive) {
1012                 ret = reservation_object_reserve_shared(robj);
1013                 if (ret)
1014                         return ret;
1015         }
1016
1017         /*
1018          * If we have any shared fences, then the exclusive fence
1019          * should be ignored as it will already have been signalled.
1020          */
1021         fobj = reservation_object_get_list(robj);
1022         if (!fobj || fobj->shared_count == 0) {
1023                 /* Wait on any existing exclusive fence which isn't our own */
1024                 fence = reservation_object_get_excl(robj);
1025                 if (fence && fence->context != context) {
1026                         ret = fence_wait(fence, true);
1027                         if (ret)
1028                                 return ret;
1029                 }
1030         }
1031
1032         if (!exclusive || !fobj)
1033                 return 0;
1034
1035         for (i = 0; i < fobj->shared_count; i++) {
1036                 fence = rcu_dereference_protected(fobj->shared[i],
1037                                                 reservation_object_held(robj));
1038                 if (fence->context != context) {
1039                         ret = fence_wait(fence, true);
1040                         if (ret)
1041                                 return ret;
1042                 }
1043         }
1044
1045         return 0;
1046 }
1047
1048 /*
1049  * event management:
1050  */
1051
1052 static unsigned int event_alloc(struct etnaviv_gpu *gpu)
1053 {
1054         unsigned long ret, flags;
1055         unsigned int i, event = ~0U;
1056
1057         ret = wait_for_completion_timeout(&gpu->event_free,
1058                                           msecs_to_jiffies(10 * 10000));
1059         if (!ret)
1060                 dev_err(gpu->dev, "wait_for_completion_timeout failed");
1061
1062         spin_lock_irqsave(&gpu->event_spinlock, flags);
1063
1064         /* find first free event */
1065         for (i = 0; i < ARRAY_SIZE(gpu->event); i++) {
1066                 if (gpu->event[i].used == false) {
1067                         gpu->event[i].used = true;
1068                         event = i;
1069                         break;
1070                 }
1071         }
1072
1073         spin_unlock_irqrestore(&gpu->event_spinlock, flags);
1074
1075         return event;
1076 }
1077
1078 static void event_free(struct etnaviv_gpu *gpu, unsigned int event)
1079 {
1080         unsigned long flags;
1081
1082         spin_lock_irqsave(&gpu->event_spinlock, flags);
1083
1084         if (gpu->event[event].used == false) {
1085                 dev_warn(gpu->dev, "event %u is already marked as free",
1086                          event);
1087                 spin_unlock_irqrestore(&gpu->event_spinlock, flags);
1088         } else {
1089                 gpu->event[event].used = false;
1090                 spin_unlock_irqrestore(&gpu->event_spinlock, flags);
1091
1092                 complete(&gpu->event_free);
1093         }
1094 }
1095
1096 /*
1097  * Cmdstream submission/retirement:
1098  */
1099
1100 struct etnaviv_cmdbuf *etnaviv_gpu_cmdbuf_new(struct etnaviv_gpu *gpu, u32 size,
1101         size_t nr_bos)
1102 {
1103         struct etnaviv_cmdbuf *cmdbuf;
1104         size_t sz = size_vstruct(nr_bos, sizeof(cmdbuf->bo[0]),
1105                                  sizeof(*cmdbuf));
1106
1107         cmdbuf = kzalloc(sz, GFP_KERNEL);
1108         if (!cmdbuf)
1109                 return NULL;
1110
1111         cmdbuf->vaddr = dma_alloc_writecombine(gpu->dev, size, &cmdbuf->paddr,
1112                                                GFP_KERNEL);
1113         if (!cmdbuf->vaddr) {
1114                 kfree(cmdbuf);
1115                 return NULL;
1116         }
1117
1118         cmdbuf->gpu = gpu;
1119         cmdbuf->size = size;
1120
1121         return cmdbuf;
1122 }
1123
1124 void etnaviv_gpu_cmdbuf_free(struct etnaviv_cmdbuf *cmdbuf)
1125 {
1126         dma_free_writecombine(cmdbuf->gpu->dev, cmdbuf->size,
1127                               cmdbuf->vaddr, cmdbuf->paddr);
1128         kfree(cmdbuf);
1129 }
1130
1131 static void retire_worker(struct work_struct *work)
1132 {
1133         struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
1134                                                retire_work);
1135         u32 fence = gpu->completed_fence;
1136         struct etnaviv_cmdbuf *cmdbuf, *tmp;
1137         unsigned int i;
1138
1139         mutex_lock(&gpu->lock);
1140         list_for_each_entry_safe(cmdbuf, tmp, &gpu->active_cmd_list, node) {
1141                 if (!fence_is_signaled(cmdbuf->fence))
1142                         break;
1143
1144                 list_del(&cmdbuf->node);
1145                 fence_put(cmdbuf->fence);
1146
1147                 for (i = 0; i < cmdbuf->nr_bos; i++) {
1148                         struct etnaviv_gem_object *etnaviv_obj = cmdbuf->bo[i];
1149
1150                         atomic_dec(&etnaviv_obj->gpu_active);
1151                         /* drop the refcount taken in etnaviv_gpu_submit */
1152                         etnaviv_gem_put_iova(gpu, &etnaviv_obj->base);
1153                 }
1154
1155                 etnaviv_gpu_cmdbuf_free(cmdbuf);
1156                 /*
1157                  * We need to balance the runtime PM count caused by
1158                  * each submission.  Upon submission, we increment
1159                  * the runtime PM counter, and allocate one event.
1160                  * So here, we put the runtime PM count for each
1161                  * completed event.
1162                  */
1163                 pm_runtime_put_autosuspend(gpu->dev);
1164         }
1165
1166         gpu->retired_fence = fence;
1167
1168         mutex_unlock(&gpu->lock);
1169
1170         wake_up_all(&gpu->fence_event);
1171 }
1172
1173 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
1174         u32 fence, struct timespec *timeout)
1175 {
1176         int ret;
1177
1178         if (fence_after(fence, gpu->next_fence)) {
1179                 DRM_ERROR("waiting on invalid fence: %u (of %u)\n",
1180                                 fence, gpu->next_fence);
1181                 return -EINVAL;
1182         }
1183
1184         if (!timeout) {
1185                 /* No timeout was requested: just test for completion */
1186                 ret = fence_completed(gpu, fence) ? 0 : -EBUSY;
1187         } else {
1188                 unsigned long remaining = etnaviv_timeout_to_jiffies(timeout);
1189
1190                 ret = wait_event_interruptible_timeout(gpu->fence_event,
1191                                                 fence_completed(gpu, fence),
1192                                                 remaining);
1193                 if (ret == 0) {
1194                         DBG("timeout waiting for fence: %u (retired: %u completed: %u)",
1195                                 fence, gpu->retired_fence,
1196                                 gpu->completed_fence);
1197                         ret = -ETIMEDOUT;
1198                 } else if (ret != -ERESTARTSYS) {
1199                         ret = 0;
1200                 }
1201         }
1202
1203         return ret;
1204 }
1205
1206 /*
1207  * Wait for an object to become inactive.  This, on it's own, is not race
1208  * free: the object is moved by the retire worker off the active list, and
1209  * then the iova is put.  Moreover, the object could be re-submitted just
1210  * after we notice that it's become inactive.
1211  *
1212  * Although the retirement happens under the gpu lock, we don't want to hold
1213  * that lock in this function while waiting.
1214  */
1215 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
1216         struct etnaviv_gem_object *etnaviv_obj, struct timespec *timeout)
1217 {
1218         unsigned long remaining;
1219         long ret;
1220
1221         if (!timeout)
1222                 return !is_active(etnaviv_obj) ? 0 : -EBUSY;
1223
1224         remaining = etnaviv_timeout_to_jiffies(timeout);
1225
1226         ret = wait_event_interruptible_timeout(gpu->fence_event,
1227                                                !is_active(etnaviv_obj),
1228                                                remaining);
1229         if (ret > 0) {
1230                 struct etnaviv_drm_private *priv = gpu->drm->dev_private;
1231
1232                 /* Synchronise with the retire worker */
1233                 flush_workqueue(priv->wq);
1234                 return 0;
1235         } else if (ret == -ERESTARTSYS) {
1236                 return -ERESTARTSYS;
1237         } else {
1238                 return -ETIMEDOUT;
1239         }
1240 }
1241
1242 int etnaviv_gpu_pm_get_sync(struct etnaviv_gpu *gpu)
1243 {
1244         return pm_runtime_get_sync(gpu->dev);
1245 }
1246
1247 void etnaviv_gpu_pm_put(struct etnaviv_gpu *gpu)
1248 {
1249         pm_runtime_mark_last_busy(gpu->dev);
1250         pm_runtime_put_autosuspend(gpu->dev);
1251 }
1252
1253 /* add bo's to gpu's ring, and kick gpu: */
1254 int etnaviv_gpu_submit(struct etnaviv_gpu *gpu,
1255         struct etnaviv_gem_submit *submit, struct etnaviv_cmdbuf *cmdbuf)
1256 {
1257         struct fence *fence;
1258         unsigned int event, i;
1259         int ret;
1260
1261         ret = etnaviv_gpu_pm_get_sync(gpu);
1262         if (ret < 0)
1263                 return ret;
1264
1265         mutex_lock(&gpu->lock);
1266
1267         /*
1268          * TODO
1269          *
1270          * - flush
1271          * - data endian
1272          * - prefetch
1273          *
1274          */
1275
1276         event = event_alloc(gpu);
1277         if (unlikely(event == ~0U)) {
1278                 DRM_ERROR("no free event\n");
1279                 ret = -EBUSY;
1280                 goto out_unlock;
1281         }
1282
1283         fence = etnaviv_gpu_fence_alloc(gpu);
1284         if (!fence) {
1285                 event_free(gpu, event);
1286                 ret = -ENOMEM;
1287                 goto out_unlock;
1288         }
1289
1290         gpu->event[event].fence = fence;
1291         submit->fence = fence->seqno;
1292         gpu->active_fence = submit->fence;
1293
1294         if (gpu->lastctx != cmdbuf->ctx) {
1295                 gpu->mmu->need_flush = true;
1296                 gpu->switch_context = true;
1297                 gpu->lastctx = cmdbuf->ctx;
1298         }
1299
1300         etnaviv_buffer_queue(gpu, event, cmdbuf);
1301
1302         cmdbuf->fence = fence;
1303         list_add_tail(&cmdbuf->node, &gpu->active_cmd_list);
1304
1305         /* We're committed to adding this command buffer, hold a PM reference */
1306         pm_runtime_get_noresume(gpu->dev);
1307
1308         for (i = 0; i < submit->nr_bos; i++) {
1309                 struct etnaviv_gem_object *etnaviv_obj = submit->bos[i].obj;
1310                 u32 iova;
1311
1312                 /* Each cmdbuf takes a refcount on the iova */
1313                 etnaviv_gem_get_iova(gpu, &etnaviv_obj->base, &iova);
1314                 cmdbuf->bo[i] = etnaviv_obj;
1315                 atomic_inc(&etnaviv_obj->gpu_active);
1316
1317                 if (submit->bos[i].flags & ETNA_SUBMIT_BO_WRITE)
1318                         reservation_object_add_excl_fence(etnaviv_obj->resv,
1319                                                           fence);
1320                 else
1321                         reservation_object_add_shared_fence(etnaviv_obj->resv,
1322                                                             fence);
1323         }
1324         cmdbuf->nr_bos = submit->nr_bos;
1325         hangcheck_timer_reset(gpu);
1326         ret = 0;
1327
1328 out_unlock:
1329         mutex_unlock(&gpu->lock);
1330
1331         etnaviv_gpu_pm_put(gpu);
1332
1333         return ret;
1334 }
1335
1336 /*
1337  * Init/Cleanup:
1338  */
1339 static irqreturn_t irq_handler(int irq, void *data)
1340 {
1341         struct etnaviv_gpu *gpu = data;
1342         irqreturn_t ret = IRQ_NONE;
1343
1344         u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE);
1345
1346         if (intr != 0) {
1347                 int event;
1348
1349                 pm_runtime_mark_last_busy(gpu->dev);
1350
1351                 dev_dbg(gpu->dev, "intr 0x%08x\n", intr);
1352
1353                 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR) {
1354                         dev_err(gpu->dev, "AXI bus error\n");
1355                         intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR;
1356                 }
1357
1358                 while ((event = ffs(intr)) != 0) {
1359                         struct fence *fence;
1360
1361                         event -= 1;
1362
1363                         intr &= ~(1 << event);
1364
1365                         dev_dbg(gpu->dev, "event %u\n", event);
1366
1367                         fence = gpu->event[event].fence;
1368                         gpu->event[event].fence = NULL;
1369                         fence_signal(fence);
1370
1371                         /*
1372                          * Events can be processed out of order.  Eg,
1373                          * - allocate and queue event 0
1374                          * - allocate event 1
1375                          * - event 0 completes, we process it
1376                          * - allocate and queue event 0
1377                          * - event 1 and event 0 complete
1378                          * we can end up processing event 0 first, then 1.
1379                          */
1380                         if (fence_after(fence->seqno, gpu->completed_fence))
1381                                 gpu->completed_fence = fence->seqno;
1382
1383                         event_free(gpu, event);
1384                 }
1385
1386                 /* Retire the buffer objects in a work */
1387                 etnaviv_queue_work(gpu->drm, &gpu->retire_work);
1388
1389                 ret = IRQ_HANDLED;
1390         }
1391
1392         return ret;
1393 }
1394
1395 static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu)
1396 {
1397         int ret;
1398
1399         ret = enable_clk(gpu);
1400         if (ret)
1401                 return ret;
1402
1403         ret = enable_axi(gpu);
1404         if (ret) {
1405                 disable_clk(gpu);
1406                 return ret;
1407         }
1408
1409         return 0;
1410 }
1411
1412 static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu)
1413 {
1414         int ret;
1415
1416         ret = disable_axi(gpu);
1417         if (ret)
1418                 return ret;
1419
1420         ret = disable_clk(gpu);
1421         if (ret)
1422                 return ret;
1423
1424         return 0;
1425 }
1426
1427 static int etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu)
1428 {
1429         if (gpu->buffer) {
1430                 unsigned long timeout;
1431
1432                 /* Replace the last WAIT with END */
1433                 etnaviv_buffer_end(gpu);
1434
1435                 /*
1436                  * We know that only the FE is busy here, this should
1437                  * happen quickly (as the WAIT is only 200 cycles).  If
1438                  * we fail, just warn and continue.
1439                  */
1440                 timeout = jiffies + msecs_to_jiffies(100);
1441                 do {
1442                         u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
1443
1444                         if ((idle & gpu->idle_mask) == gpu->idle_mask)
1445                                 break;
1446
1447                         if (time_is_before_jiffies(timeout)) {
1448                                 dev_warn(gpu->dev,
1449                                          "timed out waiting for idle: idle=0x%x\n",
1450                                          idle);
1451                                 break;
1452                         }
1453
1454                         udelay(5);
1455                 } while (1);
1456         }
1457
1458         return etnaviv_gpu_clk_disable(gpu);
1459 }
1460
1461 #ifdef CONFIG_PM
1462 static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu)
1463 {
1464         u32 clock;
1465         int ret;
1466
1467         ret = mutex_lock_killable(&gpu->lock);
1468         if (ret)
1469                 return ret;
1470
1471         clock = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS |
1472                 VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40);
1473
1474         etnaviv_gpu_load_clock(gpu, clock);
1475         etnaviv_gpu_hw_init(gpu);
1476
1477         gpu->switch_context = true;
1478
1479         mutex_unlock(&gpu->lock);
1480
1481         return 0;
1482 }
1483 #endif
1484
1485 static int etnaviv_gpu_bind(struct device *dev, struct device *master,
1486         void *data)
1487 {
1488         struct drm_device *drm = data;
1489         struct etnaviv_drm_private *priv = drm->dev_private;
1490         struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1491         int ret;
1492
1493 #ifdef CONFIG_PM
1494         ret = pm_runtime_get_sync(gpu->dev);
1495 #else
1496         ret = etnaviv_gpu_clk_enable(gpu);
1497 #endif
1498         if (ret < 0)
1499                 return ret;
1500
1501         gpu->drm = drm;
1502         gpu->fence_context = fence_context_alloc(1);
1503         spin_lock_init(&gpu->fence_spinlock);
1504
1505         INIT_LIST_HEAD(&gpu->active_cmd_list);
1506         INIT_WORK(&gpu->retire_work, retire_worker);
1507         INIT_WORK(&gpu->recover_work, recover_worker);
1508         init_waitqueue_head(&gpu->fence_event);
1509
1510         setup_timer(&gpu->hangcheck_timer, hangcheck_handler,
1511                         (unsigned long)gpu);
1512
1513         priv->gpu[priv->num_gpus++] = gpu;
1514
1515         pm_runtime_mark_last_busy(gpu->dev);
1516         pm_runtime_put_autosuspend(gpu->dev);
1517
1518         return 0;
1519 }
1520
1521 static void etnaviv_gpu_unbind(struct device *dev, struct device *master,
1522         void *data)
1523 {
1524         struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1525
1526         DBG("%s", dev_name(gpu->dev));
1527
1528         hangcheck_disable(gpu);
1529
1530 #ifdef CONFIG_PM
1531         pm_runtime_get_sync(gpu->dev);
1532         pm_runtime_put_sync_suspend(gpu->dev);
1533 #else
1534         etnaviv_gpu_hw_suspend(gpu);
1535 #endif
1536
1537         if (gpu->buffer) {
1538                 etnaviv_gpu_cmdbuf_free(gpu->buffer);
1539                 gpu->buffer = NULL;
1540         }
1541
1542         if (gpu->mmu) {
1543                 etnaviv_iommu_destroy(gpu->mmu);
1544                 gpu->mmu = NULL;
1545         }
1546
1547         gpu->drm = NULL;
1548 }
1549
1550 static const struct component_ops gpu_ops = {
1551         .bind = etnaviv_gpu_bind,
1552         .unbind = etnaviv_gpu_unbind,
1553 };
1554
1555 static const struct of_device_id etnaviv_gpu_match[] = {
1556         {
1557                 .compatible = "vivante,gc"
1558         },
1559         { /* sentinel */ }
1560 };
1561
1562 static int etnaviv_gpu_platform_probe(struct platform_device *pdev)
1563 {
1564         struct device *dev = &pdev->dev;
1565         struct etnaviv_gpu *gpu;
1566         u32 dma_mask;
1567         int err = 0;
1568
1569         gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL);
1570         if (!gpu)
1571                 return -ENOMEM;
1572
1573         gpu->dev = &pdev->dev;
1574         mutex_init(&gpu->lock);
1575
1576         /*
1577          * Set the GPU linear window to be at the end of the DMA window, where
1578          * the CMA area is likely to reside. This ensures that we are able to
1579          * map the command buffers while having the linear window overlap as
1580          * much RAM as possible, so we can optimize mappings for other buffers.
1581          */
1582         dma_mask = (u32)dma_get_required_mask(dev);
1583         if (dma_mask < PHYS_OFFSET + SZ_2G)
1584                 gpu->memory_base = PHYS_OFFSET;
1585         else
1586                 gpu->memory_base = dma_mask - SZ_2G + 1;
1587
1588         /* Map registers: */
1589         gpu->mmio = etnaviv_ioremap(pdev, NULL, dev_name(gpu->dev));
1590         if (IS_ERR(gpu->mmio))
1591                 return PTR_ERR(gpu->mmio);
1592
1593         /* Get Interrupt: */
1594         gpu->irq = platform_get_irq(pdev, 0);
1595         if (gpu->irq < 0) {
1596                 err = gpu->irq;
1597                 dev_err(dev, "failed to get irq: %d\n", err);
1598                 goto fail;
1599         }
1600
1601         err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 0,
1602                                dev_name(gpu->dev), gpu);
1603         if (err) {
1604                 dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err);
1605                 goto fail;
1606         }
1607
1608         /* Get Clocks: */
1609         gpu->clk_bus = devm_clk_get(&pdev->dev, "bus");
1610         DBG("clk_bus: %p", gpu->clk_bus);
1611         if (IS_ERR(gpu->clk_bus))
1612                 gpu->clk_bus = NULL;
1613
1614         gpu->clk_core = devm_clk_get(&pdev->dev, "core");
1615         DBG("clk_core: %p", gpu->clk_core);
1616         if (IS_ERR(gpu->clk_core))
1617                 gpu->clk_core = NULL;
1618
1619         gpu->clk_shader = devm_clk_get(&pdev->dev, "shader");
1620         DBG("clk_shader: %p", gpu->clk_shader);
1621         if (IS_ERR(gpu->clk_shader))
1622                 gpu->clk_shader = NULL;
1623
1624         /* TODO: figure out max mapped size */
1625         dev_set_drvdata(dev, gpu);
1626
1627         /*
1628          * We treat the device as initially suspended.  The runtime PM
1629          * autosuspend delay is rather arbitary: no measurements have
1630          * yet been performed to determine an appropriate value.
1631          */
1632         pm_runtime_use_autosuspend(gpu->dev);
1633         pm_runtime_set_autosuspend_delay(gpu->dev, 200);
1634         pm_runtime_enable(gpu->dev);
1635
1636         err = component_add(&pdev->dev, &gpu_ops);
1637         if (err < 0) {
1638                 dev_err(&pdev->dev, "failed to register component: %d\n", err);
1639                 goto fail;
1640         }
1641
1642         return 0;
1643
1644 fail:
1645         return err;
1646 }
1647
1648 static int etnaviv_gpu_platform_remove(struct platform_device *pdev)
1649 {
1650         component_del(&pdev->dev, &gpu_ops);
1651         pm_runtime_disable(&pdev->dev);
1652         return 0;
1653 }
1654
1655 #ifdef CONFIG_PM
1656 static int etnaviv_gpu_rpm_suspend(struct device *dev)
1657 {
1658         struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1659         u32 idle, mask;
1660
1661         /* If we have outstanding fences, we're not idle */
1662         if (gpu->completed_fence != gpu->active_fence)
1663                 return -EBUSY;
1664
1665         /* Check whether the hardware (except FE) is idle */
1666         mask = gpu->idle_mask & ~VIVS_HI_IDLE_STATE_FE;
1667         idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask;
1668         if (idle != mask)
1669                 return -EBUSY;
1670
1671         return etnaviv_gpu_hw_suspend(gpu);
1672 }
1673
1674 static int etnaviv_gpu_rpm_resume(struct device *dev)
1675 {
1676         struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1677         int ret;
1678
1679         ret = etnaviv_gpu_clk_enable(gpu);
1680         if (ret)
1681                 return ret;
1682
1683         /* Re-initialise the basic hardware state */
1684         if (gpu->drm && gpu->buffer) {
1685                 ret = etnaviv_gpu_hw_resume(gpu);
1686                 if (ret) {
1687                         etnaviv_gpu_clk_disable(gpu);
1688                         return ret;
1689                 }
1690         }
1691
1692         return 0;
1693 }
1694 #endif
1695
1696 static const struct dev_pm_ops etnaviv_gpu_pm_ops = {
1697         SET_RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend, etnaviv_gpu_rpm_resume,
1698                            NULL)
1699 };
1700
1701 struct platform_driver etnaviv_gpu_driver = {
1702         .driver = {
1703                 .name = "etnaviv-gpu",
1704                 .owner = THIS_MODULE,
1705                 .pm = &etnaviv_gpu_pm_ops,
1706                 .of_match_table = etnaviv_gpu_match,
1707         },
1708         .probe = etnaviv_gpu_platform_probe,
1709         .remove = etnaviv_gpu_platform_remove,
1710         .id_table = gpu_ids,
1711 };